From nobody Mon Feb 9 18:45:02 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+76033+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+76033+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1622782637; cv=none; d=zohomail.com; s=zohoarc; b=fjhNT9uW9qln/98A1e3TTNc9MtdOQb4EiaDFy6M3qfTKBHQ/otTDTKswmcwt0vw2/3+82d9Cs3KOGSZXg5jxrQw4q1AZhGuUgJ8HqRr8IlTwBR82stlmyKMCQRq+UjPYYWd6/glK0rvEMoHwYJfcvpUz92L+nVnqY7REUkbtN68= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622782637; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ElrBNQPx2Zf8P0zZJBtuVMgtrnA8dqw/Xrwwv6unW7Y=; b=FtV/QeixdyVDejGxx8hX88/s4Ysc4vn6ZpJxQPLgH9ibkvvL4fhawnceVdircEV2/4uxLQiSeMiWgSpd1MS1PLbfl1QXuALuS1yFgoGBAIH0/vHY5UB5GP3IbrDgyo9fX6GBeVn/zH4l2F1abwLlraretjzCrnxS7/+MiqF5IUQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+76033+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1622782637232526.0209095264356; Thu, 3 Jun 2021 21:57:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id HXOtYY1788612xPZV3rzKA2O; Thu, 03 Jun 2021 21:57:16 -0700 X-Received: from mga07.intel.com (mga07.intel.com []) by mx.groups.io with SMTP id smtpd.web09.4396.1622782621682193304 for ; Thu, 03 Jun 2021 21:57:02 -0700 IronPort-SDR: giA1DVOY+mDbhXB4fT0rdPBT6VITVXTEo4Zcn7IK0vzsWi6OzeG0iS28v9I7ACoG50lR1a6fIH 1Tg7FCKQGdGg== X-IronPort-AV: E=McAfee;i="6200,9189,10004"; a="268087111" X-IronPort-AV: E=Sophos;i="5.83,247,1616482800"; d="scan'208";a="268087111" X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2021 21:57:00 -0700 IronPort-SDR: 2X1JAhRYAWFV+jz2QAXQ+V+zbZdh3C8/vCqKml6b0nrhehPD7W1MPAMvXgWgyyHQQ2itX0TpXr dWaN3TX0rypA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,247,1616482800"; d="scan'208";a="480502766" X-Received: from fieedk002.ccr.corp.intel.com ([10.239.158.144]) by orsmga001.jf.intel.com with ESMTP; 03 Jun 2021 21:56:59 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Maurice Ma , Guo Dong , Benjamin You Subject: [edk2-devel] [Patch V2 3/9] UefiPayloadPkg: UefiPayload retrieve PCI root bridge from Guid Hob Date: Fri, 4 Jun 2021 12:56:38 +0800 Message-Id: <20210604045644.1721-4-zhiguang.liu@intel.com> In-Reply-To: <20210604045644.1721-1-zhiguang.liu@intel.com> References: <20210604045644.1721-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: exL9wCn1XQFtrldJ6IXkByDtx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1622782636; bh=neq+LlRBs/afkNjeUy+5PmlfM6k672oyYFfurkvwjc4=; h=Cc:Date:From:Reply-To:Subject:To; b=pIHCxYGXdzvzsIUUiUSPI7k9arwRwViYlT7XbLaK/8S2pM8s7QESR1JIEu9y5siun08 JgphhzEeV3jm5vjZZrya+NjzGgsI+EZm/lVUI06DoxOhDEx7YM9zt+xQ3JEoF7SdVwmTd 33c80gLU7P33qP29vQ7Jj+Oz4CB0xYrI8YY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" UefiPayload parse gPldPciRootBridgeInfoGuid Guid Hob to retrieve PCI root b= ridges information. gPldPciRootBridgeInfoGuid Guid Hob should be created by Bootlo= ader. Cc: Maurice Ma Cc: Guo Dong Cc: Benjamin You Signed-off-by: Zhiguang Liu --- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h | 40 ++++++= ++++++++++++++++++++++++++++++++-- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 42 ++++++= +++++++++++++++++++++++++++++++++--- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 8 ++++++= +- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 73 ++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- UefiPayloadPkg/UefiPayloadPkg.dsc | 2 +- 5 files changed, 157 insertions(+), 8 deletions(-) diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h b/Uefi= PayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h index c2961b3bee..b22703e79e 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h @@ -2,7 +2,7 @@ Header file of PciHostBridgeLib. =20 Copyright (C) 2016, Red Hat, Inc. - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -11,14 +11,38 @@ #ifndef _PCI_HOST_BRIDGE_H #define _PCI_HOST_BRIDGE_H =20 +#include + typedef struct { ACPI_HID_DEVICE_PATH AcpiDevicePath; EFI_DEVICE_PATH_PROTOCOL EndDevicePath; } CB_PCI_ROOT_BRIDGE_DEVICE_PATH; =20 +/** + Scan for all root bridges in platform. + + @param[out] NumberOfRootBridges Number of root bridges detected + + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array. +**/ PCI_ROOT_BRIDGE * ScanForRootBridges ( - UINTN *NumberOfRootBridges + OUT UINTN *NumberOfRootBridges +); + +/** + Scan for all root bridges from PldPciRootBridgeInfoHob + + @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob + @param[out] NumberOfRootBridges Number of root bridges detected + + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array. + +**/ +PCI_ROOT_BRIDGE * +RetrieveRootBridgeInfoFromHob ( + IN PLD_PCI_ROOT_BRIDGES *PciRootBridgeInfo, + OUT UINTN *NumberOfRootBridges ); =20 /** @@ -77,4 +101,16 @@ InitRootBridge ( OUT PCI_ROOT_BRIDGE *RootBus ); =20 +/** + Initialize DevicePath for a PCI_ROOT_BRIDGE. + @param[in] HID HID for device path + @param[in] UID UID for device path + + @retval A pointer to the new created device patch. +**/ +EFI_DEVICE_PATH_PROTOCOL * +CreateRootBridgeDevicePath ( + IN UINT32 HID, + IN UINT32 UID +); #endif diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/U= efiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c index 512c3127cc..0b4ba66e0e 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -2,7 +2,7 @@ Library instance of PciHostBridgeLib library class for coreboot. =20 Copyright (C) 2016, Red Hat, Inc. - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -19,6 +19,7 @@ #include #include #include +#include =20 #include "PciHostBridge.h" =20 @@ -48,7 +49,6 @@ CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTempl= ate =3D { } }; =20 - /** Initialize a PCI_ROOT_BRIDGE structure. =20 @@ -145,6 +145,27 @@ InitRootBridge ( return EFI_SUCCESS; } =20 +/** + Initialize DevicePath for a PCI_ROOT_BRIDGE. + @param[in] HID HID for device path + @param[in] UID UID for device path + + @retval A pointer to the new created device patch. +**/ +EFI_DEVICE_PATH_PROTOCOL * +CreateRootBridgeDevicePath ( + IN UINT32 HID, + IN UINT32 UID +) +{ + CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath; + DevicePath =3D AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate), + &mRootBridgeDevicePathTemplate); + ASSERT (DevicePath !=3D NULL); + DevicePath->AcpiDevicePath.HID =3D HID; + DevicePath->AcpiDevicePath.UID =3D UID; + return (EFI_DEVICE_PATH_PROTOCOL *)DevicePath; +} =20 /** Return all the root bridge instances in an array. @@ -161,10 +182,25 @@ PciHostBridgeGetRootBridges ( UINTN *Count ) { + PLD_PCI_ROOT_BRIDGES *PciRootBridgeInfo; + EFI_HOB_GUID_TYPE *GuidHob; + // + // Find PLD PCI Root Bridge Info hob + // + GuidHob =3D GetFirstGuidHob (&gPldPciRootBridgeInfoGuid); + if (IS_PLD_HEADER_HAS_REVISION(GuidHob, PLD_PCI_ROOT_BRIDGES_REVISION)) { + // + // PLD_PCI_ROOT_BRIDGES structure is used when Revision equals to PLD_= PCI_ROOT_BRIDGES_REVISION + // + PciRootBridgeInfo =3D (PLD_PCI_ROOT_BRIDGES *) GET_GUID_HOB_DATA (Guid= Hob); + if ((PciRootBridgeInfo->PldHeader.Length >=3D sizeof (PLD_PCI_ROOT_BRI= DGES)) &&=20 + PciRootBridgeInfo->Count <=3D (GET_GUID_HOB_DATA_SIZE (GuidHob) = - sizeof(PLD_PCI_ROOT_BRIDGES)) / sizeof(PLD_PCI_ROOT_BRIDGE)) { + return RetrieveRootBridgeInfoFromHob (PciRootBridgeInfo, Count); + } + } return ScanForRootBridges (Count); } =20 - /** Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b= /UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf index 7896df2416..1c6a47828a 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -2,7 +2,7 @@ # Library instance of PciHostBridgeLib library class for coreboot. # # Copyright (C) 2016, Red Hat, Inc. -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -39,3 +39,9 @@ DevicePathLib MemoryAllocationLib PciLib + +[Guids] + gPldPciRootBridgeInfoGuid + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c= b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c index fffbf04cad..d6d59b6659 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c @@ -1,7 +1,7 @@ /** @file Scan the entire PCI bus for root bridges to support coreboot UEFI payloa= d. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -582,3 +582,74 @@ ScanForRootBridges ( =20 return RootBridges; } + +/** + Scan for all root bridges from PldPciRootBridgeInfoHob + + @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob + @param[out] NumberOfRootBridges Number of root bridges detected + + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array. + +**/ +PCI_ROOT_BRIDGE * +RetrieveRootBridgeInfoFromHob ( + IN PLD_PCI_ROOT_BRIDGES *PciRootBridgeInfo, + OUT UINTN *NumberOfRootBridges +) +{ + PCI_ROOT_BRIDGE *PciRootBridges; + UINTN Size; + UINT8 Index; + + ASSERT (PciRootBridgeInfo !=3D NULL); + ASSERT (NumberOfRootBridges !=3D NULL); + if (PciRootBridgeInfo =3D=3D NULL) { + return NULL; + } + if (PciRootBridgeInfo->Count =3D=3D 0) { + return NULL; + } + Size =3D PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE); + PciRootBridges =3D (PCI_ROOT_BRIDGE *) AllocatePool (Size); + ASSERT (PciRootBridges !=3D NULL); + if (PciRootBridges =3D=3D NULL) { + return NULL; + } + ZeroMem (PciRootBridges, PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRI= DGE)); + + // + // Create all root bridges with PciRootBridgeInfoHob + // + for (Index =3D 0; Index < PciRootBridgeInfo->Count; Index++) { + PciRootBridges[Index].Segment =3D PciRootBridgeInfo->Roo= tBridge[Index].Segment; + PciRootBridges[Index].Supports =3D PciRootBridgeInfo->Roo= tBridge[Index].Supports; + PciRootBridges[Index].Attributes =3D PciRootBridgeInfo->Roo= tBridge[Index].Attributes; + PciRootBridges[Index].DmaAbove4G =3D PciRootBridgeInfo->Roo= tBridge[Index].DmaAbove4G; + PciRootBridges[Index].NoExtendedConfigSpace =3D PciRootBridgeInfo->Roo= tBridge[Index].NoExtendedConfigSpace; + PciRootBridges[Index].ResourceAssigned =3D PciRootBridgeInfo->Res= ourceAssigned; + PciRootBridges[Index].AllocationAttributes =3D PciRootBridgeInfo->Roo= tBridge[Index].AllocationAttributes; + PciRootBridges[Index].DevicePath =3D CreateRootBridgeDevice= Path(PciRootBridgeInfo->RootBridge[Index].HID, PciRootBridgeInfo->RootBridg= e[Index].UID); + CopyMem(&PciRootBridges[Index].Bus, &PciRootBridgeInfo->RootBr= idge[Index].Bus, sizeof(PLD_PCI_ROOT_BRIDGE_APERTURE)); + CopyMem(&PciRootBridges[Index].Io, &PciRootBridgeInfo->RootBr= idge[Index].Io, sizeof(PLD_PCI_ROOT_BRIDGE_APERTURE)); + CopyMem(&PciRootBridges[Index].Mem, &PciRootBridgeInfo->RootBr= idge[Index].Mem, sizeof(PLD_PCI_ROOT_BRIDGE_APERTURE)); + CopyMem(&PciRootBridges[Index].MemAbove4G, &PciRootBridgeInfo->RootBr= idge[Index].MemAbove4G, sizeof(PLD_PCI_ROOT_BRIDGE_APERTURE)); + CopyMem(&PciRootBridges[Index].PMem, &PciRootBridgeInfo->RootBr= idge[Index].PMem, sizeof(PLD_PCI_ROOT_BRIDGE_APERTURE)); + CopyMem(&PciRootBridges[Index].PMemAbove4G, &PciRootBridgeInfo->RootBr= idge[Index].PMemAbove4G, sizeof(PLD_PCI_ROOT_BRIDGE_APERTURE)); + } + + *NumberOfRootBridges =3D PciRootBridgeInfo->Count; + + // + // Now, this library only supports RootBridge that ResourceAssigned is T= rue + // + if (PciRootBridgeInfo->ResourceAssigned) { + PcdSetBoolS (PcdPciDisableBusEnumeration, TRUE); + } else { + DEBUG ((DEBUG_ERROR, "There is root bridge whose ResourceAssigned is F= ALSE\n")); + PcdSetBoolS (PcdPciDisableBusEnumeration, FALSE); + return NULL; + } + + return PciRootBridges; +} diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload= Pkg.dsc index 37ad5a0ae7..e9211adf86 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -323,7 +323,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTRO= L) gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTE= NDED_TX_FIFO_SIZE) =20 - gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE) gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS) gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY) @@ -363,6 +362,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE =20 ##########################################################################= ###### # --=20 2.30.0.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#76033): https://edk2.groups.io/g/devel/message/76033 Mute This Topic: https://groups.io/mt/83301964/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-