From nobody Sun Feb 8 18:31:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+75976+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+75976+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1622647871; cv=none; d=zohomail.com; s=zohoarc; b=KDpfvIyCm9FZXkaNylHNBOqTTkcZo+CihMoTAqV3ObcfnpxZZzVKk3pTggW7KkpbLku9Mds2lqORhh+knTkPMuL+27AE/BsMDy5/XvTguTtXTmjvWuf0ZcgM6vSdypHKHhAJbiOqmubHf2qc3g7uODZ5VmrrXzyDIvMjV6deBZk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622647871; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=a2D4YxOWCeJQiiFB6r1AWASB9z7na2J/v1ZHwCgXrFE=; b=eHY1TL6JWc6BllGVH/xewHqbFrxSWb2nlUzTRRUH0vCfYrmhgLX01b0hq8+e1Wf/3ZQXSR/+wFQwwzyuKpibGF1OA7ylCEu3FOtPWAtnDHIhkPUCSsVgGlp9l9ECRzBXr/KRcUSrJwTDyTjPJwr2VVKJxf+rbQl8DMuUD5UCpU0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+75976+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1622647871174616.1175515914273; Wed, 2 Jun 2021 08:31:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6hpXYY1788612xZJDGMBqcx2; Wed, 02 Jun 2021 08:31:10 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.9780.1622618166204192851 for ; Wed, 02 Jun 2021 00:16:06 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AFA0B6D; Wed, 2 Jun 2021 00:16:05 -0700 (PDT) X-Received: from usa.arm.com (unknown [10.163.35.111]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 263FB3F73D; Wed, 2 Jun 2021 00:16:02 -0700 (PDT) From: "Khasim Mohammed" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Khasim Syed Mohammed Subject: [edk2-devel] [edk2-platforms][PATCH V1 1/4] Silicon/ARM/NeoverseN1Soc: Add mem regions to support multi-chip usecase Date: Wed, 2 Jun 2021 12:45:49 +0530 Message-Id: <20210602071552.1207-2-khasim.mohammed@arm.com> In-Reply-To: <20210602071552.1207-1-khasim.mohammed@arm.com> References: <20210602071552.1207-1-khasim.mohammed@arm.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,khasim.mohammed@arm.com X-Gm-Message-State: MMAcW2HyOI8q85Rnr92jj5Iix1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1622647870; bh=8NRaioUreXan+GXnL8FamE/4OyhND5EElzmZMO0JrZQ=; h=Cc:Date:From:Reply-To:Subject:To; b=qCYB5R6NcDGw694HYWF5WMQcZz8+6aKHoR9ZqPaMaAwErvIugE10S+UMKpEPJL2og/B 14vPuCPzbGNJqRWtPooel+hzefP4dl3k4E4RdAYeYH0UP+coIx2gLdZR/i9FRyeVy1x89 jhtWOvqUbLWbsyTuLs9DunSuYVzwa9uvPyM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds resource descriptor for multi-chip usecase and introduces corresponding PCD definitions. Signed-off-by: Chandni Cherukuri Signed-off-by: Khasim Syed Mohammed --- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 30= ++++++- Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf | 28= ++++--- Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 10= +-- Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c | 18= ++--- Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c | 43= ++++++++-- Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 84= +++++++++++++++++--- 6 files changed, 172 insertions(+), 41 deletions(-) diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/Neov= erseN1Soc/NeoverseN1Soc.dec index 54b793a937ff..8789795bbae3 100644 --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec @@ -1,5 +1,7 @@ +## @file +# Describes the entire platform configuration. # -# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -33,8 +35,8 @@ [PcdsFixedAtBuild] gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007 - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x000= 00008 - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x000000= 09 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x001FFFF|UINT32|0x0000= 0008 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x020000|UINT32|0x00000009 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32|0= x0000000A gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x00= 00000B gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32|0= x0000000C @@ -44,3 +46,25 @@ [PcdsFixedAtBuild] gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64= |0x00000010 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x= 00000011 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00= 000012 + + # CCIX + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax|17|UINT32|0x00000017 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UIN= T32|0x00000019 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x00000= 01B + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0= x00000001D + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x00= 00001E + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0= x00000001F + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00= 000020 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00= 000021 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x= 00000022 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64= |0x00000023 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x= 00000024 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00= 000025 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000= 000|UINT32|0x00000026 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000= |UINT32|0x00000027 + + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0= x00000029 diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf = b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf index 166c9e044483..8e2154aadf47 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -1,6 +1,7 @@ ## @file +# Platform Library for N1Sdp. # -# Copyright (c) 2018-2020, ARM Limited. All rights reserved. +# Copyright (c) 2018-2021, ARM Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -29,13 +30,17 @@ [Sources.AARCH64] AArch64/Helper.S | GCC =20 [FixedPcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize - gArmTokenSpaceGuid.PcdArmPrimaryCore - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask - + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base @@ -45,7 +50,12 @@ [FixedPcd] gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize =20 - gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress =20 [Guids] gEfiHobListGuid ## CONSUMES ## SystemTable diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/AR= M/NeoverseN1Soc/Include/NeoverseN1Soc.h index 097160c7e2d1..309a5c627845 100644 --- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h @@ -1,9 +1,9 @@ /** @file -* -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + + Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + **/ =20 #ifndef NEOVERSEN1SOC_PLATFORM_H_ diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBrid= geLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeL= ib.c index 9332939f63eb..ac88415fd24c 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -1,10 +1,10 @@ /** @file -* PCI Host Bridge Library instance for ARM Neoverse N1 platform -* -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + PCI Host Bridge Library instance for ARM Neoverse N1 platform + + Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + **/ =20 #include @@ -96,7 +96,7 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D { /** Return all the root bridge instances in an array. =20 - @param Count Return the count of root bridge instances. + @param Count Return the count of root bridge instances. =20 @return All the root bridge instances in an array. The array should be passed into PciHostBridgeFreeRootBridges() @@ -115,8 +115,8 @@ PciHostBridgeGetRootBridges ( /** Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges(). =20 - @param Bridges The root bridge instances array. - @param Count The count of the array. + @param Bridges The root bridge instances array. + @param Count The count of the array. **/ VOID EFIAPI diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/= Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c index f722080e566b..d5ec0ff30d10 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c @@ -1,9 +1,9 @@ /** @file -* -* Copyright (c) 2018-2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + + Copyright (c) 2018-2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + **/ =20 #include @@ -17,6 +17,12 @@ STATIC ARM_CORE_INFO mCoreInfoTable[] =3D { { 0x1, 0x1 } // Cluster 1, Core 1 }; =20 +/** + Return the current Boot Mode. + + This function returns the boot reason on the platform. + +**/ EFI_BOOT_MODE ArmPlatformGetBootMode ( VOID @@ -25,6 +31,15 @@ ArmPlatformGetBootMode ( return BOOT_WITH_FULL_CONFIGURATION; } =20 +/** + Initialize controllers that must be setup in the normal world. + + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/= PlatformPeim + in the PEI phase. + + @param[in] MpId Processor ID + +**/ RETURN_STATUS ArmPlatformInitialize ( IN UINTN MpId @@ -33,6 +48,15 @@ ArmPlatformInitialize ( return RETURN_SUCCESS; } =20 +/** + Populate the Platform core information. + + This function populates the ARM_MP_CORE_INFO_PPI with information about = the cores. + + @param[out] CoreCount Number of cores + @param[out] ArmCoreTable Table containing information about the cores + +**/ EFI_STATUS PrePeiCoreGetMpCoreInfo ( OUT UINTN *CoreCount, @@ -56,6 +80,15 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { } }; =20 +/** + Return the Platform specific PPIs + + This function exposes the N1Sdp Specific PPIs. + + @param[out] PpiListSize Size in Bytes of the Platform PPI List + @param[out] PpiList Platform PPI List + +**/ VOID ArmPlatformGetPlatformPpiList ( OUT UINTN *PpiListSize, diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c= b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c index f9b3d037537d..ebdcf437599a 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -1,9 +1,9 @@ /** @file -* -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + + Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + **/ =20 #include @@ -13,7 +13,7 @@ #include =20 // The total number of descriptors, including the final "end-of-table" des= criptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 =20 /** Returns the Virtual Memory Map of the platform. @@ -21,21 +21,23 @@ This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. =20 - @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing - a Physical-to-Virtual Memory mapping. This = array - must be ended by a zero-filled entry. + @param[in] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR des= cribing + a Physical-to-Virtual Memory mapping. Thi= s array + must be ended by a zero-filled entry. **/ VOID ArmPlatformGetVirtualMemoryMap ( IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap ) { - UINTN Index =3D 0; + UINTN Index; ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; NEOVERSEN1SOC_PLAT_INFO *PlatInfo; UINT64 DramBlock2Size; + UINT64 RemoteDdrSize; =20 + Index =3D 0; PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_B= ASE; DramBlock2Size =3D ((UINT64)(PlatInfo->LocalDdrSize - NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * @@ -55,6 +57,24 @@ ArmPlatformGetVirtualMemoryMap ( FixedPcdGet64 (PcdDramBlock2Base), DramBlock2Size); =20 + if (PlatInfo->MultichipMode =3D=3D 1) { + RemoteDdrSize =3D ((PlatInfo->RemoteDdrSize - 2) * 1024UL * 1024UL * 1= 024UL); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdSystemMemoryBa= se), + PcdGet64 (PcdSystemMemorySize) + ); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdDramBlock2Base= ), + RemoteDdrSize + ); + } + ASSERT (VirtualMemoryMap !=3D NULL); Index =3D 0; =20 @@ -114,6 +134,32 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdPcieMmio64Siz= e); VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 + // CCIX RC Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdCcixRootPortC= onfigBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdCcixRootPortC= onfigBaseAddress); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdCcixRootPortC= onfigBaseSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // CCIX ECAM Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdCcixExpressBa= seAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdCcixExpressBa= seAddress); + VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdCcixBus= Max) - + FixedPcdGet32 (PcdCcixBusMi= n) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // CCIX MMIO32 Memory Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdCcixMmio32Bas= e); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdCcixMmio32Bas= e); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdCcixMmio32Siz= e); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // CCIX MMIO64 Memory Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdCcixMmio64Bas= e); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdCcixMmio64Bas= e); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdCcixMmio64Siz= e); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + // SubSystem Pheripherals - UART0 VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_UART0_BASE; VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_UART0_BASE; @@ -138,6 +184,24 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_EXP_PERIPH_B= ASE0_SZ; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 + if (PlatInfo->MultichipMode =3D=3D 1) { + //Remote DDR (2GB) + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdExtMemorySp= ace) + + PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdExtMemorySp= ace) + + PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemor= ySize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_WRITE_THROUGH; + + //Remote DDR + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdExtMemorySp= ace) + + PcdGet64 (PcdDramBlock2Bas= e); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdExtMemorySp= ace) + + PcdGet64 (PcdDramBlock2Bas= e); + VirtualMemoryTable[Index].Length =3D RemoteDdrSize; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_WRITE_THROUGH; + } + // End of Table VirtualMemoryTable[++Index].PhysicalBase =3D 0; VirtualMemoryTable[Index].VirtualBase =3D 0; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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