From nobody Tue Feb 10 13:17:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+75556+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+75556+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1621940291; cv=none; d=zohomail.com; s=zohoarc; b=Gwc6RGr8zHkvbqbxD493f+9BP2CwkQrhvFNswax3r6jGCXGYEIIcvsAavgyXNtG9EcSP+VI8CjmmLyhuN4X5pgMIZ23iwDo6CXGg2LZvnoW0Eksyp9yvP+KEqwJd6c/DQ6HGdAcVgkxHf6o9BlqhUMV+EvSD9tbd4RIPM8wiXXI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621940291; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jum9Q2KSQFVgD9+xf4u+v8f/6n3BO3rZlDtOkhngaVQ=; b=kRxlBYDJFkckSs7xwSy4N/wzOydmxlqKlIo4Zw3GGZB57QUy+/F4bzFoS2j6Xg4aUBmESRzLhp/T0d/nNILLbWtPAu5aZHychYYyhmQQ9vbdesNPtBgBqYG5IlaEwJ44oZ/xe8YuyaVGpRRSSQO1lXiY0EQymYcJqKMq388gGf0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+75556+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1621940291914664.0601635408699; Tue, 25 May 2021 03:58:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id YAOtYY1788612xD8CX2EtPZS; Tue, 25 May 2021 03:58:11 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.8120.1621940290904463198 for ; Tue, 25 May 2021 03:58:11 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7A82E101E; Tue, 25 May 2021 03:58:10 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 504C53F719; Tue, 25 May 2021 03:58:09 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 2/6] Platform/Sgi: ACPI PPTT table for RD-N2-Cfg1 platform Date: Tue, 25 May 2021 16:27:57 +0530 Message-Id: <20210525105801.13793-3-pranav.madhu@arm.com> In-Reply-To: <20210525105801.13793-1-pranav.madhu@arm.com> References: <20210525105801.13793-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: QpkvJaNPvRqxbt7jt1ihyjUSx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1621940291; bh=ROTdaDSGbL2hMKshwnyNz/msAqHWt6mushiFQ1oLimY=; h=Cc:Date:From:Reply-To:Subject:To; b=PNY1lJB7L1hvaVpEFA9Lj/aMS26s+LPixwheaugz0hPy6DScRgn/Jas94lntcxjEF3z UPWWKDOcPAUJibnNTRayhbUEdDLt5Tlw5xipTsk6HWkSvhEre/IsWGHDjfNiF/CmzL8tQ oICoYmXA1W/HWbpt+AKKXnZ116dhFNKxkug= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-N2-Cfg1 platform includes eight single-thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes a system level cache of 8MB. Add PPTT table for RD-N2-Cfg1 platform with this information. Signed-off-by: Pranav Madhu Reviewed-by: Sami Mujawar --- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 166 ++++++++++++++= ++++++ 2 files changed, 167 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf index f96353087b68..58468096de4f 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf @@ -22,6 +22,7 @@ Mcfg.aslc RdN2Cfg1/Dsdt.asl RdN2Cfg1/Madt.aslc + RdN2Cfg1/Pptt.aslc Spcr.aslc Ssdt.asl SsdtRos.asl diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc new file mode 100644 index 000000000000..5890544c0b92 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc @@ -0,0 +1,166 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform +* +* This file describes the topological structure of the processor block on = the +* RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-N2= -Cfg1 +* platform includes eight single-thread CPUS. Each of the CPUs include 64KB +* L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform = also +* includes system level cache of 8MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +/** Define helper macro for populating processor core information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. + @param [in] CpuId CPU instance number. +**/ +#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId]), /* Parent */ = \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ + 2 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_1MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +/** Define helper macro for populating processor container information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. +**/ +#define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package), /* Parent */ = \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ), = \ + = \ + /* Initialize child core */ = \ + { = \ + PPTT_CORE_INIT (PackageId, ClusterId, 0) = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_SLC_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), + + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + Package.Slc), + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ + 0, /* Next level of cache */ + SIZE_8MB, /* Size */ + 8192, /* Num of sets */ + 16, /* Associativity */ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ + 64 /* Line size */ + ), + + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + PPTT_CLUSTER_INIT (0, 2), + PPTT_CLUSTER_INIT (0, 3), + PPTT_CLUSTER_INIT (0, 4), + PPTT_CLUSTER_INIT (0, 5), + PPTT_CLUSTER_INIT (0, 6), + PPTT_CLUSTER_INIT (0, 7), + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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