From nobody Tue Feb 10 04:17:36 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+75529+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+75529+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1621866521; cv=none; d=zohomail.com; s=zohoarc; b=W7XpORaTqNeBEXXqdtSJd0UHSbh1Kj3D7CczjC0Wkrc5FimAg1J6kFQ/vmPkGUVf7Xh3UCY163AAe3cmt3KCZeNFCcPqs2z9W2T6Vn0YhCDTnXC2Wl2aIxfpgmAjGaG+eS3xg7Hay0HEbZuPt23ZQYvHYb1OIqcN7qW6TCMz5UM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621866521; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ahNf2tOgYKOMwh1w4HfrGz1LdikSX/Eystw++B1Vn+Q=; b=QajPNjDn8F7j51pP3XbSxXayVwutv/+HVL0qPnZs/iMZxMfG/jtMPWChkHnvn/H12A0NPsDrHOYFR3jYd3Or5aVcDOazS3zYG819n6PlNW2hMhICnh8tzwgGYCq4c8FQ9on3tjYZ/2DtNL4rVuTII1R6FNcIYDBnuFgF1r5E3tY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+75529+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1621866521886833.0648725793377; Mon, 24 May 2021 07:28:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZIu9YY1788612x0CVm3VUH8s; Mon, 24 May 2021 07:28:41 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.23867.1621866519512530028 for ; Mon, 24 May 2021 07:28:39 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2A838ED1; Mon, 24 May 2021 07:28:39 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BD1213F719; Mon, 24 May 2021 07:28:37 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V4 07/11] Platform/Sgi: Add SMBIOS Type7 Table Date: Mon, 24 May 2021 19:58:12 +0530 Message-Id: <20210524142816.9967-8-pranav.madhu@arm.com> In-Reply-To: <20210524142816.9967-1-pranav.madhu@arm.com> References: <20210524142816.9967-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: lYr1RYiTuzpct6VuOomQDDH8x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1621866521; bh=7B9mZ5q/CM4iYQ6YmHUb8xONHk2RABNE9ohfkIaE8yA=; h=Cc:Date:From:Reply-To:Subject:To; b=SK521DgrL0tR2ZVM8s5vRXiLDfg4XMwLw2yRQhjw4LdKv/NoD9AlU5dxNpY2qeLie0R s+Qt6pg3F7Sp6+e7JW2FuNYJhrwyxI2bIqU/fAg2Kh33cOL5RjTePCa4cJIXgv7mFkn0r 4+gJavA08YrjGPlJKfCLkEPxhkvj6ZeubG0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add the SMBIOS type 7 table (Cache Information) that includes information about cache levels implemented, cache configuration, ways of associativity and other information related to cache memory installed. Signed-off-by: Pranav Madhu Reviewed-by: Sami Mujawar --- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | = 1 + Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h | 1= 9 ++ Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | = 1 + Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 34= 2 ++++++++++++++++++++ 4 files changed, 363 insertions(+) diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDx= e.inf b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf index 4652a9c62b88..ee00b773912b 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -19,6 +19,7 @@ Type1SystemInformation.c Type3SystemEnclosure.c Type4ProcessorInformation.c + Type7CacheInformation.c =20 [Packages] ArmPkg/ArmPkg.dec diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDx= e.h b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h index 7c2164ae04bf..43f35ea0518f 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h @@ -85,6 +85,25 @@ InstallType4ProcessorInformation ( IN EFI_SMBIOS_PROTOCOL *Smbios ); =20 +/** + Install SMBIOS Cache information Table + + Install the SMBIOS Cache information (type 7) table for Arm's Reference + Design platforms. + + @param[in] Smbios SMBIOS protocol. + + @retval EFI_SUCCESS Record was added. + @retval EFI_NOT_FOUND Unknown product id. + @retval EFI_OUT_OF_RESOURCES Record was not added. + @retval EFI_ALREADY_STARTED The SmbiosHandle passed is already in use. +**/ +EFI_STATUS +EFIAPI +InstallType7CacheInformation ( + IN EFI_SMBIOS_PROTOCOL *Smbios + ); + typedef enum { SMBIOS_HANDLE_ENCLOSURE =3D 0x1000, SMBIOS_HANDLE_CLUSTER1, diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDx= e.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c index 7ef6f88a783d..d3b161b77550 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -30,6 +30,7 @@ ARM_RD_SMBIOS_TABLE_INSTALL_FPTR mSmbiosTableList[] =3D { &InstallType1SystemInformation, &InstallType3SystemEnclosure, &InstallType4ProcessorInformation, + &InstallType7CacheInformation, }; =20 /** diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInform= ation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformati= on.c new file mode 100644 index 000000000000..6be62900bd71 --- /dev/null +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c @@ -0,0 +1,342 @@ +/** @file + SMBIOS Type 7 (Cache information) table for ARM RD platforms. + + This file installs SMBIOS Type 7 (Cache information) table for Arm's + Reference Design platforms. It includes information about cache levels + implemented, cache configuration, ways of associativity and other + information related to cache memory installed. + + Copyright (c) 2021, ARM Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - SMBIOS Reference Specification 3.4.0, Chapter 7.8 +**/ + +#include +#include + +#include "SgiPlatform.h" +#include "SmbiosPlatformDxe.h" + +#define TYPE7_STRINGS \ + "L1 Instruction\0" /* L1I */ \ + "L1 Data\0" /* L1D */ \ + "L2\0" /* L2 */ \ + "L3\0" /* L3 */ \ + "SLC\0" /* L4 */ + +typedef enum { + L1Instruction =3D 1, + L1Data, + L2, + L3, + SLC, +} TYPE7_STRING_ELEMENTS; + +/* SMBIOS Type7 structure */ +#pragma pack(1) +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + CHAR8 Strings[sizeof (TYPE7_STRINGS)]; +} ARM_RD_SMBIOS_TYPE7; +#pragma pack() + +/* Cache information */ +STATIC ARM_RD_SMBIOS_TYPE7 mArmRdSmbiosType7[] =3D { + { // Entry 0, L1 instruction cache + { + { + // SMBIOS header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7 + sizeof (SMBIOS_TABLE_TYPE7), // Length + SMBIOS_HANDLE_L1I_CACHE, // Handle number + }, + L1Instruction, + ( + (1 << 8) | // Write-back + (1 << 7) | // Cache enabled + (1 << 3) | // Cache socketed + 0x0 // Cache level 1 + ), + 0xFFFF, // Uses Maximum cache size 2 field + 0xFFFF, // Uses Installed cache size 2 field + {0, 1}, // Supported SRAM type unknown + {0, 1}, // Current SRAM type unknown + 0, // Cache Speed Unknown + 0x02, // Error correction type unknown + 0x03, // Instruction cache + 0, // Associativity, update dynamically + 0, // Maximum cache size 2, update dynamically + 0 // Installed cache size 2, update dynamically + }, + // Text strings (unformatted area) + TYPE7_STRINGS + }, + { // Entry 1, L1 data cache + { + { + // SMBIOS header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7 + sizeof (SMBIOS_TABLE_TYPE7), // Length + SMBIOS_HANDLE_L1D_CACHE, // Handle number + }, + L1Data, + ( + (1 << 8) | // Write-back + (1 << 7) | // Cache enabled + (1 << 3) | // Cache socketed + 0x0 // Cache level 1 + ), + 0xFFFF, // Uses Maximum cache size 2 field + 0xFFFF, // Uses Installed cache size 2 field + {0, 1}, // Supported SRAM type unknown + {0, 1}, // Current SRAM type unknown + 0, // Cache Speed Unknown + 0x02, // Error correction type unknown + 0x04, // Data cache + 0, // Associativity, update dynamically + 0, // Maximum cache size 2, update dynamically + 0 // Installed cache size 2, update dynamically + }, + // Text strings (unformatted area) + TYPE7_STRINGS + }, + { // Entry 2, L2 cache + { + { + // SMBIOS header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7 + sizeof (SMBIOS_TABLE_TYPE7), // Length + SMBIOS_HANDLE_L2_CACHE, // Handle number + }, + L2, + ( + (1 << 8) | // Write-back + (1 << 7) | // Cache enabled + (1 << 3) | // Cache socketed + 0x1 // Cache level 2 + ), + 0xFFFF, // Uses Maximum cache size 2 field + 0xFFFF, // Uses Installed cache size 2 field + {0, 1}, // Supported SRAM type unknown + {0, 1}, // Current SRAM type unknown + 0, // Cache Speed Unknown + 0x02, // Error correction type unknown + 0x05, // Unified cache + 0, // Associativity, update dynamically + 0, // Maximum cache size 2, update dynamically + 0 // Installed cache size 2, update dynamically + }, + // Text strings (unformatted area) + TYPE7_STRINGS + }, + { // Entry 3, L3 cache + { + { + // SMBIOS header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7 + sizeof (SMBIOS_TABLE_TYPE7), // Length + SMBIOS_HANDLE_L3_CACHE, // Handle number + }, + L3, + ( + (1 << 8) | // Write-back + (1 << 7) | // Cache enabled + (1 << 3) | // Cache socketed + 0x2 // Cache level 3 + ), + 0xFFFF, // Uses Maximum cache size 2 field + 0xFFFF, // Uses Installed cache size 2 field + {0, 1}, // Supported SRAM type unknown + {0, 1}, // Current SRAM type unknown + 0, // Cache Speed Unknown + 0x02, // Error correction type unknown + 0x05, // Unified cache + 0, // Associativity, update dynamically + 0, // Maximum cache size 2, update dynamically + 0 // Installed cache size 2, update dynamically + }, + // Text strings (unformatted area) + TYPE7_STRINGS + }, + { // Entry 4, SLC Cache + { + { + // SMBIOS header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7 + sizeof (SMBIOS_TABLE_TYPE7), // Length + SMBIOS_HANDLE_L4_CACHE, // Handle number + }, + SLC, + ( + (1 << 8) | // Write-back + (1 << 7) | // Cache enabled + (1 << 3) | // Cache socketed + 0x3 // Cache level 4 + ), + 0xFFFF, // Uses Maximum cache size 2 field + 0xFFFF, // Uses Installed cache size 2 field + {0, 1}, // Supported SRAM type unknown + {0, 1}, // Current SRAM type unknown + 0, // Cache Speed Unknown + 0x02, // Error correction type unknown + 0x05, // Unified cache + 0, // Associativity, update dynamically + 0, // Maximum cache size 2, update dynamically + 0 // Installed cache size 2, update dynamically + }, + // Text strings (unformatted area) + TYPE7_STRINGS + } +}; + +/** + Install SMBIOS Cache information Table + + Install the SMBIOS Cache information (type 7) table for Arm's Reference + Design platforms. + + @param[in] Smbios SMBIOS protocol. + + @retval EFI_SUCCESS Record was added. + @retval EFI_NOT_FOUND Unknown product id. + @retval EFI_OUT_OF_RESOURCES Record was not added. + @retval EFI_ALREADY_STARTED The SmbiosHandle passed is already in use. +**/ +EFI_STATUS +InstallType7CacheInformation ( + IN EFI_SMBIOS_PROTOCOL *Smbios + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + UINT8 CacheIdx; + + /* Update the cache attributes based on the product */ + switch (SgiGetProductId ()) { + case Sgi575: + /* L1 instruction cache */ + mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.Associativity =3D CacheAssociativity4Way; + /* L1 data cache */ + mArmRdSmbiosType7[1].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.Associativity =3D CacheAssociativity16Way; + /* L2 cache */ + mArmRdSmbiosType7[2].Base.MaximumCacheSize2 =3D 512; // 512KB + mArmRdSmbiosType7[2].Base.InstalledSize2 =3D 512; // 512KB + mArmRdSmbiosType7[2].Base.Associativity =3D CacheAssociativity8Way; + /* L3 cache */ + mArmRdSmbiosType7[3].Base.MaximumCacheSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.InstalledSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.Associativity =3D CacheAssociativity16Way; + break; + case RdN1Edge: + case RdN1EdgeX2: + /* L1 instruction cache */ + mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.Associativity =3D CacheAssociativity4Way; + /* L1 data cache */ + mArmRdSmbiosType7[1].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.Associativity =3D CacheAssociativity4Way; + /* L2 cache */ + mArmRdSmbiosType7[2].Base.MaximumCacheSize2 =3D 512; // 512KB + mArmRdSmbiosType7[2].Base.InstalledSize2 =3D 512; // 512KB + mArmRdSmbiosType7[2].Base.Associativity =3D CacheAssociativity8Way; + /* L3 cache */ + mArmRdSmbiosType7[3].Base.MaximumCacheSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.InstalledSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.Associativity =3D CacheAssociativity16Way; + /* System level cache */ + mArmRdSmbiosType7[4].Base.MaximumCacheSize2 =3D 8192; // 8MB SLC per = chip + mArmRdSmbiosType7[4].Base.InstalledSize2 =3D 8192; // 8MB SLC per = chip + mArmRdSmbiosType7[4].Base.Associativity =3D CacheAssociativity16Way; + break; + case RdE1Edge: + /* L1 instruction cache */ + mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 32; // 32KB + mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 32; // 32KB + mArmRdSmbiosType7[0].Base.Associativity =3D CacheAssociativity4Way; + /* L1 data cache */ + mArmRdSmbiosType7[1].Base.MaximumCacheSize2 =3D 32; // 32KB + mArmRdSmbiosType7[1].Base.InstalledSize2 =3D 32; // 32KB + mArmRdSmbiosType7[1].Base.Associativity =3D CacheAssociativity4Way; + /* L2 cache */ + mArmRdSmbiosType7[2].Base.MaximumCacheSize2 =3D 256; // 256KB + mArmRdSmbiosType7[2].Base.InstalledSize2 =3D 256; // 256KB + mArmRdSmbiosType7[2].Base.Associativity =3D CacheAssociativity4Way; + /* L3 cache */ + mArmRdSmbiosType7[3].Base.MaximumCacheSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.InstalledSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.Associativity =3D CacheAssociativity16Way; + /* System level cache */ + mArmRdSmbiosType7[4].Base.MaximumCacheSize2 =3D 8192; // 8MB SLC + mArmRdSmbiosType7[4].Base.InstalledSize2 =3D 8192; // 8MB SLC + mArmRdSmbiosType7[4].Base.Associativity =3D CacheAssociativity16Way; + break; + case RdV1: + case RdV1Mc: + /* L1 instruction cache */ + mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.Associativity =3D CacheAssociativity4Way; + /* L1 data cache */ + mArmRdSmbiosType7[1].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.Associativity =3D CacheAssociativity4Way; + /* L2 cache */ + mArmRdSmbiosType7[2].Base.MaximumCacheSize2 =3D 1024; // 1MB + mArmRdSmbiosType7[2].Base.InstalledSize2 =3D 1024; // 1MB + mArmRdSmbiosType7[2].Base.Associativity =3D CacheAssociativity8Way; + /* System level cache */ + mArmRdSmbiosType7[4].Base.MaximumCacheSize2 =3D 16384; // 16MB SLC per= chip + mArmRdSmbiosType7[4].Base.InstalledSize2 =3D 16384; // 16MB SLC per= chip + mArmRdSmbiosType7[4].Base.Associativity =3D CacheAssociativity16Way; + break; + case RdN2: + /* L1 instruction cache */ + mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.Associativity =3D CacheAssociativity4Way; + /* L1 data cache */ + mArmRdSmbiosType7[1].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.Associativity =3D CacheAssociativity4Way; + /* L2 cache */ + mArmRdSmbiosType7[2].Base.MaximumCacheSize2 =3D 1024; // 1MB + mArmRdSmbiosType7[2].Base.InstalledSize2 =3D 1024; // 1MB + mArmRdSmbiosType7[2].Base.Associativity =3D CacheAssociativity8Way; + /* System level cache */ + mArmRdSmbiosType7[4].Base.MaximumCacheSize2 =3D 32768; // 32MB SLC + mArmRdSmbiosType7[4].Base.InstalledSize2 =3D 32768; // 32MB SLC + mArmRdSmbiosType7[4].Base.Associativity =3D CacheAssociativity16Way; + break; + } + + /* Install valid cache information tables */ + for (CacheIdx =3D 0; CacheIdx < ARRAY_SIZE (mArmRdSmbiosType7); CacheIdx= ++) { + if (mArmRdSmbiosType7[CacheIdx].Base.MaximumCacheSize2 =3D=3D 0) { + continue; + } + + SmbiosHandle =3D ((EFI_SMBIOS_TABLE_HEADER *)&mArmRdSmbiosType7[CacheI= dx])->Handle; + Status =3D Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *)&mArmRdSmbiosType7[Cache= Idx] + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "SMBIOS: Failed to install Type7 SMBIOS table.\n" + )); + } + } + + return Status; +} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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