From nobody Sun May 19 11:31:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+75477+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+75477+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1621834177; cv=none; d=zohomail.com; s=zohoarc; b=dnuTJEdgXkVlsPsBNrXMJdZCrKpw70uC+z4lds5v1IrU1ZnD+MkOx/09QPd3YHTQInRHR4d+lMOXjLJwvPHiyJyGrD7uS3ytrJPT56CiJOBl5YE922ox8z20hDMdRKEZ+wQYCLxRUYJRfsAgbKZIDq2msnMUFQ2PFJ3A5lupr4w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621834177; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=V7d+dy6F8YatkajZtVrv27yldRPY0lYqbtH2KkZf1iM=; b=e5rbDD8FhDi/RqzduGA0VrY8gdOwbS3U476pPcguOCwzb9wq9KSYwt4aMG7HLgxUzx5X69b4gQARcqETsYE9oj/BZA3IOW+3SHG4/KopvdNMldmgrvCy+ZR8iu/QwkMO/lrgVVpAKHh88LlyMkMNNtRedHAuyH0W9GFfc1dPAek= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+75477+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16218341778041019.1050184663094; Sun, 23 May 2021 22:29:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id F6FtYY1788612xh4Rk5a7dfJ; Sun, 23 May 2021 22:29:37 -0700 X-Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) by mx.groups.io with SMTP id smtpd.web12.19101.1621834175452641485 for ; Sun, 23 May 2021 22:29:35 -0700 X-Received: by mail-lj1-f178.google.com with SMTP id a4so17128676ljd.5 for ; Sun, 23 May 2021 22:29:35 -0700 (PDT) X-Gm-Message-State: 7uOXZNrXXGdsMi0uJIJgh4k8x1787277AA= X-Google-Smtp-Source: ABdhPJyV/ra0e4ivfcxOpICeN0f8+BSJyVsMtZC31yC47dJlWHkFPfvlhfMdhKfAY04/GYxz+Vm6jw== X-Received: by 2002:a2e:9a90:: with SMTP id p16mr15773621lji.7.1621834173767; Sun, 23 May 2021 22:29:33 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (host-193.106.246.138.static.3s.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id w17sm90739lfp.300.2021.05.23.22.29.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 22:29:33 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, Samer.El-Haj-Mahmoud@arm.com, sunny.Wang@arm.com, gjb@semihalf.com, upstream@semihalf.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 1/6] Marvell/Drivers: SmbiosPlatformDxe: Align Type17 to SMBIOS v3.2 Date: Mon, 24 May 2021 07:29:14 +0200 Message-Id: <20210524052919.2496579-2-mw@semihalf.com> In-Reply-To: <20210524052919.2496579-1-mw@semihalf.com> References: <20210524052919.2496579-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1621834177; bh=Pr2zfjLyeGBUBSW/FtERUXn89LZK7SCsUKII8O3lmrw=; h=Cc:Date:From:Reply-To:Subject:To; b=gBarzLi1AEazebsFCq8VtLjSleUzpbrJB/jHSMUg69KuwDR0CFUKGnIXs9q7l/1k8dz O6WvQIEbdZ7z4Bh6AQVfwXT8s3xHVrvZjpfosxIcCAVoGE7JSNnnaWu45YGHcbGPtZLH/ bffdny6iD+nsNkIs1Hhl8bFbWn31ZpGSoKc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This patch adds missing entries required for SMBIOS v3.2 compliance of the Type17 table. On the occasion improve Type4 table contents. Signed-off-by: Marcin Wojtas Reviewed-by: Samer El-Haj-Mahmoud --- Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 39 +++++++= +++++++++++-- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c = b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c index 2ecaec2af5..a99291e902 100644 --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -181,7 +181,7 @@ STATIC SMBIOS_TABLE_TYPE4 mArmadaDefaultType4 =3D { 3, //version {0,0,0,0,0,1}, //voltage 0, //external clock - 2000, //max speed + 2200, //max speed 0, //current speed - requires update 0x41, //status ProcessorUpgradeOther, @@ -196,6 +196,9 @@ STATIC SMBIOS_TABLE_TYPE4 mArmadaDefaultType4 =3D { 4, //threads per socket 0xEC, //processor characteristics ProcessorFamilyARM, //ARM core + 0, // CoreCount2; + 0, // EnabledCoreCount2; + 0, // ThreadCount2; }; =20 STATIC CHAR8 CONST *mArmadaDefaultType4Strings[] =3D { @@ -457,7 +460,7 @@ STATIC SMBIOS_TABLE_TYPE17 mArmadaDefaultType17 =3D { 0, //Memory size obtained dynamically MemoryFormFactorRowOfChips, //Memory factor 0, //Not part of a set - 1, //Right side of board + 1, //Location 2, //Bank 0 MemoryTypeDdr4, //DDR4 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, //unbuffered @@ -467,10 +470,36 @@ STATIC SMBIOS_TABLE_TYPE17 mArmadaDefaultType17 =3D { 0, //asset tag 0, //part number 0, //rank + 0, // ExtendedSize; (since Size < 32GB-1) + 0, // ConfiguredMemoryClockSpeed - initialized at runtime + 0, // MinimumVoltage; (unknown) + 0, // MaximumVoltage; (unknown) + 0, // ConfiguredVoltage; (unknown) + MemoryTechnologyDram, // MemoryTechnology + {{ // MemoryOperatingModeCapability + 0, // Reserved :1; + 0, // Other :1; + 0, // Unknown :1; + 1, // VolatileMemory :1; + 0, // ByteAccessiblePersistentMemory :1; + 0, // BlockAccessiblePersistentMemory :1; + 0 // Reserved :10; + }}, + 0, // FirwareVersion + 0, // ModuleManufacturerID (unknown) + 0, // ModuleProductID (unknown) + 0, // MemorySubsystemControllerManufacturerID (unknown) + 0, // MemorySubsystemControllerProductID (unknown) + 0, // NonVolatileSize + 0, // VolatileSize - initialized at runtime + 0, // CacheSize + 0, // LogicalSize + 0, // ExtendedSpeed, + 0 // ExtendedConfiguredMemorySpeed }; =20 STATIC CHAR8 CONST *mArmadaDefaultType17Strings[] =3D { - "RIGHT SIDE\0", /* location */ + "DIMM SLOT\0", /* location */ "BANK 0\0", /* bank description */ NULL }; @@ -735,9 +764,10 @@ SmbiosMemoryInstall ( } =20 // - // Update TYPE17 memory size field + // Update TYPE17 memory size fields // mArmadaDefaultType17.Size =3D (UINT16)(MemorySize >> 20); + mArmadaDefaultType17.VolatileSize =3D MemorySize; =20 return EFI_SUCCESS; } @@ -767,6 +797,7 @@ SmbiosInstallAllStructures ( mArmadaDefaultType0.SystemBiosMinorRelease =3D FirmwareMinorRevisionNumb= er; mArmadaDefaultType4.CurrentSpeed =3D SampleAtResetGetCpuFrequency (); mArmadaDefaultType17.Speed =3D SampleAtResetGetDramFrequency (); + mArmadaDefaultType17.ConfiguredMemoryClockSpeed =3D SampleAtResetGetDram= Frequency (); =20 // // Generate memory descriptors. --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id w17sm90739lfp.300.2021.05.23.22.29.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 22:29:34 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, Samer.El-Haj-Mahmoud@arm.com, sunny.Wang@arm.com, gjb@semihalf.com, upstream@semihalf.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 2/6] Marvell: Armada7k8k/OcteonTx: Fix RT debug prints Date: Mon, 24 May 2021 07:29:15 +0200 Message-Id: <20210524052919.2496579-3-mw@semihalf.com> In-Reply-To: <20210524052919.2496579-1-mw@semihalf.com> References: <20210524052919.2496579-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1621834177; bh=vWo3/epa8v4NLJFFieDiSVb/YLNF1MppAWUi6ECFZ90=; h=Cc:Date:From:Reply-To:Subject:To; b=klJ7FL2ujLy9m7PwdfUIbHLCbwg1VwhvyXXHRV9N8YH5KTCPOF/b0FkhI4EcqP/JFbO qvq2YcYnuyHGq8sJVSaKarlaR2ffrlVHjub7vXplk7fQ+cd2jCHRUsnxhWd8wDuWrOH5N GQnAvZhPN6kv0kz0w/BmZNvitiL8lfJ7xdw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Resolution of the DebugLib for the DXE_RUNTIME_DRIVER library class was limited to non-RELEASE builds. This caused crashes during FWTS in case the RT attempted to use UART. Fix that by allowing to use DxeRuntimeDebugLibSerialPort in all kind of builds. Signed-off-by: Marcin Wojtas Reviewed-By: Samer El-Haj-Mahmoud Reviewed-by: Sunny Wang --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index 4cdafe8b1f..939fbf14d9 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -195,9 +195,7 @@ !else CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf !endif -!if $(TARGET) !=3D RELEASE DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibS= erialPort.inf -!endif VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf =20 [LibraryClasses.ARM, LibraryClasses.AARCH64] --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#75478): https://edk2.groups.io/g/devel/message/75478 Mute This Topic: https://groups.io/mt/83044528/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 11:31:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+75479+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+75479+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1621834183; cv=none; d=zohomail.com; s=zohoarc; b=HplT82v3sqc33QhZdNN6nG49l7tntwCMhtXqsVsRTzptF04FvLLRmsCa/FJipJJ+UTxmMQUDAz4yCksINVRiUYxnQwPktUVjenOqKpkU50jv8SN1Ebslvur47sO8r/9fzlgfz1MMGDQDcNkPAJzfypS7/VzB+OIuqN0SXInDpGE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621834183; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=eV+ExjKdN1crG2lK27XcbP5Mod8nWzfwD1RvdObBbPU=; b=ViP3pTsOVFYIMX5Ppuk/gQ471jjgtU7HIbugEXEo/f4jZq2pJakyVkOR1ixox3dAOBXNuCcIzJUjCiMKo2nZ5b/gg3wmSfnfItr2VeiSVjGgRghrlAh2U1dr4lDxtTVe6PgHhBb40H/pDBJg8SPff986UEFxm0ZqmUyB1Q1pDj4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+75479+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16218341838411014.9667243989505; Sun, 23 May 2021 22:29:43 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id VSdpYY1788612xSbEoV6Kddp; Sun, 23 May 2021 22:29:43 -0700 X-Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) by mx.groups.io with SMTP id smtpd.web08.19183.1621834177517179038 for ; Sun, 23 May 2021 22:29:37 -0700 X-Received: by mail-lj1-f175.google.com with SMTP id p20so31949358ljj.8 for ; Sun, 23 May 2021 22:29:37 -0700 (PDT) X-Gm-Message-State: zZFPL7PjdspP7hvePDDKZQO4x1787277AA= X-Google-Smtp-Source: ABdhPJzRS8LOzxQ3wpMgVBczTOGEvax+1OVf4HhtrWenLp2XCKNMkEdYp2mBSn7DtJIpXBODhQ7PHA== X-Received: by 2002:a2e:a553:: with SMTP id e19mr15526405ljn.280.1621834175802; Sun, 23 May 2021 22:29:35 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (host-193.106.246.138.static.3s.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id w17sm90739lfp.300.2021.05.23.22.29.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 22:29:35 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, Samer.El-Haj-Mahmoud@arm.com, sunny.Wang@arm.com, gjb@semihalf.com, upstream@semihalf.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 3/6] Marvell: Armada7k8k/OcteonTx: Switch SPCR UART subtype to 0x1 Date: Mon, 24 May 2021 07:29:16 +0200 Message-Id: <20210524052919.2496579-4-mw@semihalf.com> In-Reply-To: <20210524052919.2496579-1-mw@semihalf.com> References: <20210524052919.2496579-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1621834183; bh=FUBWYCtfzQgUfL92Hit8ep4y4tEm1PrwOxyIypH8+ZY=; h=Cc:Date:From:Reply-To:Subject:To; b=IJ0aRMr7P7Tn00n9p8Dz3b0JwauNNGzya9+lqs2JOB93wSpqX0VWUAVNckXrR6pzn4o WWkQyuLy6yYq/cR7+NOF9r1RslL/d4nS1ma+z1VEY64LmlllvqqQsaYrDQE5WoZyidtel 9AvuO/rhhGu4wB7nK1IMnsspg9MGEmszoOc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" DBG2 ACPI table description [1] specifies three subtypes related to 16550 UART: 0x0 - 16550 compatible 0x1 - 16550 subset 0x12 - 16550 compatible with parameters defined in Generic Address Structure (GAS) It turned out however, that the Windows OS treats 0x0 subtype as legacy x86 UART with 8-bit access. ARM SoCs can use types 0x1 (16550 with fixed mmio32 access) or 0x12 (16550 with fully respected GAS contents). Switch Marvell SoCs ACPI UART subtype to 0x1 - thanks to that the same firmware can run properly with UART output in Windows 10, Linux and ESXI hypervisor. [1] https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-= debug-port-table Signed-off-by: Marcin Wojtas Reviewed-by: Sunny Wang --- Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 2 +- Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Spcr.aslc index 438cf7880e..6efc175bdf 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc @@ -22,7 +22,7 @@ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION ), - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, //= InterfaceType + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16450, //= InterfaceType { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, //= Reserved1[3] diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Spcr.aslc index f663d8ade8..2a3415f0a6 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc @@ -22,7 +22,7 @@ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION ), - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, //= InterfaceType + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16450, //= InterfaceType { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, //= Reserved1[3] --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id w17sm90739lfp.300.2021.05.23.22.29.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 22:29:36 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, Samer.El-Haj-Mahmoud@arm.com, sunny.Wang@arm.com, gjb@semihalf.com, upstream@semihalf.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 4/6] Marvell/Cn913xDbA: AcpiTables: Use unique UID's Date: Mon, 24 May 2021 07:29:17 +0200 Message-Id: <20210524052919.2496579-5-mw@semihalf.com> In-Reply-To: <20210524052919.2496579-1-mw@semihalf.com> References: <20210524052919.2496579-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1621834184; bh=YDHbpiWpgjQqvUVJhOwKfgmjprqeCMM1lSOC79QCjJY=; h=Cc:Date:From:Reply-To:Subject:To; b=iaw6uSGg7OJ5rU3/cEfM2VlwXXcC5GgChqcO9Pj3LM6IEQ7AlgYdIihlFrqH9HyEeRg c9E+XycPmdmfct4rKaOuN6qSDK1QchPJsHmHGyJW4UQ/P91lF9n374VzxlTDIQ5HvlIgg Rv21p1fJtN7QTQFSH7rrGQ03P3u2/Y4U9Xw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The CN9131 variant's SSDT comprised UID's, whose values overlapped the ones used in the main DSDT file. Fix that. Signed-off-by: Marcin Wojtas Reviewed-By: Samer El-Haj-Mahmoud Reviewed-by: Sunny Wang --- Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl index dc32fe836a..691a709c18 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl @@ -18,7 +18,7 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU "= , "CN9131", 3) Device (AHC1) { Name (_HID, "LNRO001E") // _HID: Hardware ID - Name (_UID, 0x00) // _UID: Unique ID + Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute Name (_CLS, Package (0x03) // _CLS: Class Code { @@ -43,7 +43,7 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU "= , "CN9131", 3) Device (XHC2) { Name (_HID, "PNP0D10") // _HID: Hardware ID - Name (_UID, 0x01) // _UID: Unique ID + Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings @@ -62,7 +62,7 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU "= , "CN9131", 3) { Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller - Name (_UID, 0x00) // _UID: U= nique ID + Name (_UID, 0x01) // _UID: U= nique ID Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id w17sm90739lfp.300.2021.05.23.22.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 22:29:37 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, Samer.El-Haj-Mahmoud@arm.com, sunny.Wang@arm.com, gjb@semihalf.com, upstream@semihalf.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 5/6] Marvell: RealTimeClockLib: Fix daylight and timezone handling Date: Mon, 24 May 2021 07:29:18 +0200 Message-Id: <20210524052919.2496579-6-mw@semihalf.com> In-Reply-To: <20210524052919.2496579-1-mw@semihalf.com> References: <20210524052919.2496579-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1621834180; bh=t8uxHYOtMm1sWIAo4E8eyul+3dYqCSqzMjoFSMsR+/8=; h=Cc:Date:From:Reply-To:Subject:To; b=uoHoop6Mfrc8/4MdLkVrV1R23t+YeSApaoStFB8scYZ9eyfjguWTOk9dy2fYQeb1MGr zg7elMyxHb+EZnzutmk5OnBhRiHVIKe70b04TEGlyH6w0Ym8J2SKDjQgXpC5VvxPWCUVc +Dsx4l8bXIMV6QNQW11BGRqr8K2nwyuzepQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The Marvell implementation of the RealTimeClockLib was unnecessarily overriding the daylight and timezone values, which are handled by non-volatile variables in the generic code. Fix that. Signed-off-by: Marcin Wojtas Reviewed-by: Samer El-Haj-Mahmoud --- Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c | 3= --- 1 file changed, 3 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.c b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCloc= kLib.c index 40ab01ed41..a48d44ed83 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c @@ -79,9 +79,6 @@ LibGetTime ( // Convert from internal 32-bit time to UEFI time EpochToEfiTime (RegVal, Time); =20 - Time->TimeZone =3D EFI_UNSPECIFIED_TIMEZONE; - Time->Daylight =3D 0; - return Status; } =20 --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id w17sm90739lfp.300.2021.05.23.22.29.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 22:29:38 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, Samer.El-Haj-Mahmoud@arm.com, sunny.Wang@arm.com, gjb@semihalf.com, upstream@semihalf.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 6/6] Marvell: RealTimeClockLib: Rework LibGetWakeupTime/LibSetWakeupTime Date: Mon, 24 May 2021 07:29:19 +0200 Message-Id: <20210524052919.2496579-7-mw@semihalf.com> In-Reply-To: <20210524052919.2496579-1-mw@semihalf.com> References: <20210524052919.2496579-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1621834186; bh=OE7RYT5nt6DJBgSd4M7dPsZLPbqj8eAbV9o8zqadRHk=; h=Cc:Date:From:Reply-To:Subject:To; b=E2lK0dsho4mzp3KhmsHLthAsI9dd+PuOIPGZbRezNeyLSokcUwiMmG23uxwQtqTgY3K wQDwxp7AqKs78A7r+4iLXKr61xUe7hSZTadGnQYQqXXAPH0VPUIsVkXDnV7MzPxV/qulQ tyyImjCv2MMqc/SHRvnwldEVA9ht1RZ+nLQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Apply multiple fixes to the Marvell RealTimeClockLib wakeup library callbacks. LibGetWakeupTime: * Add input parameters validation * Fix 'Pending' value check LibSetWakeupTime: * Allow disabling the wakeup timer regardless the input 'Time' value * Use more generic 'Time' value verification, which is more strict than the replaced custom one. * Use proper alarm mask for 'Pending' signalling With above the ACS3.0 FWTS and SCT timer tests pass cleanly. Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.h | = 2 +- Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c | 2= 9 ++++++++++---------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.h b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCloc= kLib.h index 7fa1d092e4..c33e63d107 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.h @@ -17,7 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define RTC_BRIDGE_TIMING_CTRL0_REG_OFFS 0x80 #define RTC_BRIDGE_TIMING_CTRL1_REG_OFFS 0x84 #define RTC_IRQ_STATUS_REG 0x90 -#define RTC_IRQ_ALARM_MASK 0x1 +#define RTC_IRQ_ALARM_MASK 0x2 #define RTC_WRITE_PERIOD_DELAY_MASK 0xFFFF #define RTC_WRITE_PERIOD_DELAY_DEFAULT 0x3FF #define RTC_WRITE_SETUP_DELAY_MASK (0xFFFF << 16) diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.c b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCloc= kLib.c index a48d44ed83..49c9385d53 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c @@ -140,11 +140,15 @@ LibGetWakeupTime ( { UINT32 WakeupSeconds; =20 + if (Time =3D=3D NULL || Enabled =3D=3D NULL || Pending =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + *Enabled =3D MmioRead32 (mArmadaRtcBase + RTC_IRQ_2_CONFIG_REG) & RTC_IR= Q_ALARM_EN; =20 *Pending =3D MmioRead32 (mArmadaRtcBase + RTC_IRQ_STATUS_REG) & RTC_IRQ_= ALARM_MASK; // Ack pending alarm - if (Pending) { + if (*Pending) { MmioWrite32 (mArmadaRtcBase + RTC_IRQ_STATUS_REG, RTC_IRQ_ALARM_MASK); } =20 @@ -176,14 +180,14 @@ LibSetWakeupTime ( { UINTN WakeupSeconds; =20 - // - // Because the Armada RTC uses a 32-bit counter for seconds, - // the maximum time span is just over 136 years. - // Time is stored in Unix Epoch format, so it starts in 1970, - // Therefore it can not exceed the year 2106. - // - if ((Time->Year < 1970) || (Time->Year >=3D 2106)) { - return EFI_UNSUPPORTED; + // Handle timer disabling case + if (!Enabled) { + RtcDelayedWrite (RTC_IRQ_2_CONFIG_REG, 0); + return EFI_SUCCESS; + } + + if (Time =3D=3D NULL || !IsTimeValid (Time)) { + return EFI_INVALID_PARAMETER; } =20 // Convert time to raw seconds @@ -195,11 +199,8 @@ LibSetWakeupTime ( // Issue delayed write to alarm register RtcDelayedWrite (RTC_ALARM_2_REG, (UINT32)WakeupSeconds); =20 - if (Enabled) { - MmioWrite32 (mArmadaRtcBase + RTC_IRQ_2_CONFIG_REG, RTC_IRQ_ALARM_EN); - } else { - MmioWrite32 (mArmadaRtcBase + RTC_IRQ_2_CONFIG_REG, 0); - } + // Enable wakeup timer + RtcDelayedWrite (RTC_IRQ_2_CONFIG_REG, RTC_IRQ_ALARM_EN); =20 return EFI_SUCCESS; } --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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