From nobody Sun May 19 12:00:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74969+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74969+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1620726524; cv=none; d=zohomail.com; s=zohoarc; b=hvPmm/FWqewUJ0NVAH4COVI0lQRwtZWcJKagQsqfL4XOVORs+FdZ58uSK9TjigFgcD3iXihWcoVBU7tP7FDCLV+5zU4MOhEgjfSgpqVd7X5xpyiX6do8KlzbUeI/EZ9EarhWA3PJKzluwztnyfM+sUXM59jcNrdorBqp7g2ua0I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620726524; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QitIRiJszohIB20gdfGOorxMBGhX8L4RJdR8G5p4sWE=; b=GJeKM6nmL9s0AwZEPTPIUcww+zHjzwRBuHEh4doTo5ixy8t/8u9ybEChpYTbd7kXv97hbd7vXabWZ8svqTzD+auzfbtKUeJdtwZUP65XOofD77osHQI+J1NbzJNk3hCv8cL/KBZbjVX8kXmzHvh90QaKXtYtOsI4tnCsucLcSHk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74969+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1620726524394277.4324126177879; Tue, 11 May 2021 02:48:44 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id k3gXYY1788612x9TAX4ZSxUl; Tue, 11 May 2021 02:48:44 -0700 X-Received: from mga17.intel.com (mga17.intel.com []) by mx.groups.io with SMTP id smtpd.web08.10549.1620726522478040095 for ; Tue, 11 May 2021 02:48:43 -0700 IronPort-SDR: UYFdZWu54EpwTefB6jCSkvoiscMLU3XD9x3xRn1eF/6dTn8PW95qbnKvV5u/weP6k19+606N5M MJgjRlJwl+gQ== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="179664949" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="179664949" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:41 -0700 IronPort-SDR: DzI0A2bF7rqAtMoKRGP5VqiSdlJBEFr0g48/ehFDnkrVitJqCM6h2GEBZl+KhrJ4NICWxkOTSE dntHsbP89UQQ== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436573917" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:40 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 01/18] PurleyRefreshSiliconPkg: Add DEC and DSC files. Date: Tue, 11 May 2021 02:48:09 -0700 Message-Id: <20210511094826.12495-2-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: vP0oF2sE6hfJFep8Bv5talpFx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726524; bh=xXl3Ff7m6HD17RrNjKPY6L6rOys5EBM4F4CpQIXfTUw=; h=Cc:Date:From:Reply-To:Subject:To; b=FUdTLpRSiNkLmfIHMKDbh5d0s52osiZCY4Xa/R3wXN0rU5ft2xB9FJ5NoaouZCIbinu CsZibDfHpHRZvFlDRrC4qYyqJuW6dl7LToBCfKZMzveuhNlZd7tyurDcWOp/5DTpIH8Nz hHoWZ7aLoU5lgHQoZq6ZyH5B5NHSzB/W/w4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../Intel/PurleyRefreshSiliconPkg/SiPkg.dec | 390 ++++++++++++++++++ .../SiPkgCommonLib.dsc | 33 ++ .../PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc | 22 + .../PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc | 12 + 4 files changed, 457 insertions(+) create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgCommonLib.dsc create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec b/Silicon/Inte= l/PurleyRefreshSiliconPkg/SiPkg.dec new file mode 100644 index 0000000000..1ec91ee25a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec @@ -0,0 +1,390 @@ +## @file +# Component description file for the Purley Refresh Silicon Reference Code. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D PurleyRefreshSiliconPkg + PACKAGE_GUID =3D 0BF28B71-A81D-4029-BEC2-A4BE58A0D0D5 + PACKAGE_VERSION =3D 0.1 + +[Includes] + Include + Include/Library + Include/Guid + + Library/BaseMemoryCoreLib/Core + Library/BaseMemoryCoreLib/Core/Include + Library/BaseMemoryCoreLib/Platform/Purley/Include + + Library/BaseMemoryCoreLib/Chip/Skx + Library/BaseMemoryCoreLib/Chip/Skx/Include + Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio + Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol + Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup + + Library/ProcMemInit/Chip/Include + Override/IA32FamilyCpuPkg + Override/IA32FamilyCpuPkg/Include + + Iio/Include + Iio/Include/Protocol + + Pch + Pch/Include + Pch/IncludePrivate + Pch/AcpiTables/Dsdt + +[LibraryClasses] + + ## @libraryclass Provides services to get the silicon access library. + SiliconAccessLib|Include/Library/UsraAccessApi.h + + ## @libraryclass Provides services to convert CSR to PCIE address libr= ary. + CsrToPcieLib|PurleyRefreshSiliconPkg/Include/Library/CsrToPcieAddress.h + + ## @libraryclass Provides services to PCIE address library. + PcieAddrLib|PurleyRefreshSiliconPkg/Include/Library/PcieAddress.h + + ## @libraryclass Provides services to get PCI Express Address Base lib= rary. + MmPciLib|PurleyRefreshSiliconPkg/Include/Library/MmPciBaseLib.h + + ## @libraryclass Provides services to get the silicon access library. + UsraLib|PurleyRefreshSiliconPkg/Include/Protocol/SiliconRegAccess.h + +[Guids] + + ## Include/Guid/CpRcPkgTokenSpace.h + gEfiCpRcPkgTokenSpaceGuid =3D { 0xfcdd2efc, 0x= 6ca8, 0x4d0b, { 0x9d, 0x00, 0x6f, 0x9c, 0xfa, 0x57, 0x8f, 0x98 }} + gRcPkgTokenSpaceGuid =3D { 0x86cf2b1a, 0x= b3da, 0x4642, { 0x95, 0xf5, 0xd0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }} + gEfiPchTokenSpaceGuid =3D { 0x89a1b278, 0x= a1a1, 0x4df7, { 0xb1, 0x37, 0xde, 0x5a, 0xd7, 0xc4, 0x79, 0x13 }} + gEfiCommonPkgTokenSpaceGuid =3D { 0x86cf2b1a, 0x= b3da, 0x4642, { 0x95, 0xf5, 0xd0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }} + gEfiPchTokenSpaceGuid =3D { 0x977c97c1, 0x= 47e1, 0x4b6b, { 0x96, 0x69, 0x43, 0x66, 0x99, 0xcb, 0xe4, 0x5b }} + gCpuUncoreTokenSpaceGuid =3D { 0x9044434c, 0x= 40e8, 0x47a1, { 0xa3, 0xba, 0x85, 0x07, 0xf3, 0xc0, 0xe2, 0x56 }} + gPlatformTokenSpaceGuid =3D { 0x07dfa0d2, 0x= 2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 }} + + # + # Uncore + # + gProcessorProducerGuid =3D { 0x1bf06aea, 0x= 5bec, 0x4a8d, { 0x95, 0x76, 0x74, 0x9b, 0x09, 0x56, 0x2d, 0x30 }} + gEfiCpuHtCapableGuid =3D { 0x0d1b9c8e, 0x= f77b, 0x4632, { 0x83, 0x43, 0x91, 0xf4, 0x3d, 0x9a, 0x85, 0x60 }} + gEfiMemoryConfigDataGuid =3D { 0x80dbd530, 0x= b74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }} + gEfiMemoryConfigDataHobGuid =3D { 0x1de25879, 0x= 6e2a, 0x4d72, { 0xa7, 0x68, 0x28, 0x8c, 0xcb, 0x9f, 0xa7, 0x19 }} + gEfiMemorySetupGuid =3D { 0x3eeff35f, 0x= 147c, 0x4cd1, { 0xa2, 0x34, 0x92, 0xa0, 0x69, 0x70, 0x0d, 0xb6 }} + gEfiMemoryMapGuid =3D { 0xf8870015, 0x= 6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f }} + gEfiMemoryMapDataHobBdatGuid =3D { 0x3417b225, 0x= 916a, 0x49f5, { 0x9a, 0xf5, 0xc9, 0xc7, 0xbf, 0x93, 0x7e, 0xa2 }} + gEfiMpstNodeDataGuid =3D { 0x418bc604, 0x= f15e, 0x4843, { 0x85, 0xd0, 0x2d, 0x24, 0x80, 0xb7, 0xe4, 0x88 }} + gReadyForLockProtocolGuid =3D { 0x8d6f1add, 0x= 45a5, 0x45a8, { 0x8b, 0xb8, 0x0c, 0x3a, 0x95, 0x31, 0x48, 0xfa }} + + gEfiSocketIioVariableGuid =3D { 0xdd84017e, 0x= 7f52, 0x48f9, { 0xb1, 0x6e, 0x50, 0xed, 0x9e, 0x0d, 0xbe, 0x27 }} + gEfiSocketCommonRcVariableGuid =3D { 0x4402ca38, 0x= 808f, 0x4279, { 0xbc, 0xec, 0x5b, 0xaf, 0x8d, 0x59, 0x09, 0x2f }} + gEfiSocketMpLinkVariableGuid =3D { 0x2b9b22de, 0x= 2ad4, 0x4abc, { 0x95, 0x7d, 0x5f, 0x18, 0xc5, 0x04, 0xa0, 0x5c }} + gEfiSocketPciResourceDataGuid =3D { 0xca3ff937, 0x= d646, 0x4936, { 0x90, 0xe8, 0x1b, 0x95, 0x06, 0x49, 0xb3, 0x89 }} + gEfiSocketMemoryVariableGuid =3D { 0x98cf19ed, 0x= 4109, 0x4681, { 0xb7, 0x9d, 0x91, 0x96, 0x75, 0x7c, 0x78, 0x24 }} + gEfiSocketPowermanagementVarGuid =3D { 0xA1047342, 0x= BDBA, 0x4DAE, { 0xA6, 0x7A, 0x40, 0x97, 0x9B, 0x65, 0xC7, 0xF8 }} + gEfiSocketProcessorCoreVarGuid =3D { 0x07013588, 0x= C789, 0x4E12, { 0xA7, 0xC3, 0x88, 0xFA, 0xFA, 0xE7, 0x9F, 0x7C }} + gSocketPkgListGuid =3D { 0x5c0083db, 0x= 3f7d, 0x4b20, { 0xac, 0x9b, 0x73, 0xfc, 0x65, 0x1b, 0x25, 0x03 }} + gEfiVolatileMemModeVariableGuid =3D { 0x0633a0f1, 0x= 78fe, 0x4139, { 0xb8, 0x78, 0x00, 0x45, 0xe8, 0x1c, 0xb8, 0xab }} + gEfiQpiRcParmGuid =3D { 0x8149fbb8, 0x= a2cf, 0x4234, { 0xb5, 0x06, 0xb7, 0x62, 0x55, 0xf7, 0xa3, 0x6d }} + gAddressBasedMirrorGuid =3D { 0x7b9be2e0, 0x= e28a, 0x4197, { 0xad, 0x3e, 0x32, 0xf0, 0x62, 0xf9, 0x46, 0x2c }} + gClvBootTimeTestExecution =3D { 0x3ff7d152, 0x= ef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 }} + gEfiRasClvTesterGuid =3D { 0x9bd36f4f, 0x= 08dc, 0x4eab, { 0x86, 0x37, 0x2b, 0xc1, 0xbd, 0x5e, 0x0d, 0x95 }} + gSocketPkgFpgaGuid =3D { 0x624b948f, 0x= 6eba, 0x4dfd, { 0x9d, 0xda, 0x10, 0xb0, 0x07, 0x3a, 0x37, 0x35 }} + gIioPolicyHobGuid =3D { 0xcabb327, 0x= 11fe, 0x416b, { 0xae, 0x80, 0x2d, 0xe5, 0xdf, 0x60, 0xf7, 0x7d }} + gEfiSmmPeiSmramMemoryReserveGuid =3D { 0x6dadf1d1, 0x= d4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d }} + + # + # Pch + # + gSataControllerDriverGuid =3D { 0xbb929da9, 0x= 68f7, 0x4035, { 0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 }} + gPchInitVariableGuid =3D { 0xe6c2f70a, 0x= b604, 0x4877, { 0x85, 0xba, 0xde, 0xec, 0x89, 0xe1, 0x17, 0xeb }} + gPchS3ImageGuid =3D { 0x271dd6f2, 0x= 54cb, 0x45e6, { 0x85, 0x85, 0x8c, 0x92, 0x3c, 0x1a, 0xc7, 0x06 }} + gEfiSmbusArpMapGuid =3D { 0x707be83e, 0x= 0bf6, 0x40a5, { 0xbe, 0x64, 0x34, 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 }} + mPchSataRsteProtocolGuid =3D { 0x3ea94650, 0x= fc5b, 0x11e1, { 0xa2, 0x1f, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 }} + mPchSataRstProtocolGuid =3D { 0xfc5f2e00, 0x= fc68, 0x11e1, { 0xa2, 0x1f, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 }} + gPchInitPeiVariableGuid =3D { 0xa31b27a4, 0x= cae6, 0x48ff, { 0x8c, 0x5a, 0x29, 0x42, 0x21, 0xe6, 0xf3, 0x89 }} + gChipsetInitInfoHobGuid =3D { 0xc1392859, 0x= 1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }} + gPchOemSmmGuid =3D { 0xc0cfaf36, 0x= 4296, 0x40ba, { 0xa9, 0xf1, 0x77, 0x10, 0x9b, 0x91, 0xce, 0x19 }} + gPchPowerCycleResetGuid =3D { 0x8d8ee25b, 0x= 66dd, 0x4ed8, { 0x8a, 0xbd, 0x14, 0x16, 0xe8, 0x8e, 0x1d, 0x24 }} + gPchGlobalResetGuid =3D { 0x9db31b4c, 0x= f5ef, 0x48bb, { 0x94, 0x2b, 0x18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }} + gPchGlobalResetWithEcGuid =3D { 0xd22e6b72, 0x= 53cd, 0x4158, { 0x83, 0x3f, 0x6f, 0xd8, 0x7e, 0xbe, 0xa9, 0x93 }} +#S3 add + gPchS3CodeInLockBoxGuid =3D { 0x1f18c5b3, 0x= 29ed, 0x4d9e, { 0xa5, 0x04, 0x6d, 0x97, 0x8e, 0x7e, 0xd5, 0x69 }} + gPchS3ContextInLockBoxGuid =3D { 0xe5769ea9, 0x= e706, 0x454b, { 0x95, 0x7f, 0xaf, 0xc6, 0xdb, 0x4b, 0x8a, 0x0d }} +#S3 add + gMeBiosExtensionSetupGuid =3D { 0x1bad711c, 0x= d451, 0x4241, { 0xb1, 0xf3, 0x85, 0x37, 0x81, 0x2e, 0x0c, 0x70 }} + gAmtForcePushPetPolicyGuid =3D { 0xacc8e1e4, 0x= 9f9f, 0x4e40, { 0xa5, 0x7e, 0xf9, 0x9e, 0x52, 0xf3, 0x4c, 0xa5 }} + gEfiAcpiVariableGuid =3D { 0xc020489e, 0x= 6db2, 0x4ef2, { 0x9a, 0xa5, 0xca, 0x06, 0xfc, 0x11, 0xd3, 0x6a }} + gSiPolicyHobGuid =3D { 0xb3903068, 0x= 7482, 0x4424, { 0xba, 0x4b, 0x40, 0x5f, 0x8f, 0xd7, 0x65, 0x4e }} + gPchPolicyHobGuid =3D { 0x524ed3ca, 0x= b250, 0x49f5, { 0x94, 0xd9, 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }} + gPchDeviceTableHobGuid =3D { 0xb3e123d0, 0x= 7a1e, 0x4db4, { 0xaf, 0x66, 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }} + gPchChipsetInitHobGuid =3D { 0xc1392859, 0x= 1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }} + gWdtHobGuid =3D { 0x65675786, 0x= acca, 0x4b11, { 0x8a, 0xb7, 0xf8, 0x43, 0xaa, 0x2a, 0x8b, 0xea }} + # PCH_SERVER_BIOS_FLAG add + gPchPsfErrorHobGuid =3D { 0x9ee875f4, 0x= a463, 0x4b29, { 0x88, 0x79, 0x11, 0x2a, 0x4d, 0x05, 0x47, 0x7f }} #PCH_SERV= ER_BIOS_FLAG + + # + # PreMem Performance + # + gPerfPchPrePolicyGuid =3D { 0x3112356F, 0x= CC77, 0x4E82, { 0x86, 0xD5, 0x3E, 0x25, 0xEE, 0x81, 0x92, 0xA4 }} + gPerfSiValidateGuid =3D { 0x681F96E6, 0x= F9CF, 0x464D, { 0x97, 0x9A, 0xB1, 0x11, 0x33, 0xDE, 0x37, 0xA9 }} + gPerfPchValidateGuid =3D { 0xD0FF37D6, 0x= A569, 0x4058, { 0xB3, 0xDA, 0x29, 0x0B, 0x38, 0xC5, 0x32, 0x25 }} + gPerfAmtValidateGuid =3D { 0x9E949422, 0x= 4A7A, 0x4E41, { 0xB0, 0xAB, 0x3C, 0x0D, 0x88, 0x0A, 0x00, 0xFF }} + gPerfCpuValidateGuid =3D { 0xB760CFCC, 0x= DEEF, 0x4C7E, { 0x99, 0x5B, 0xED, 0xFE, 0xF2, 0x23, 0xB2, 0x09 }} + gPerfMeValidateGuid =3D { 0x8CF7A498, 0x= 588D, 0x4D39, { 0xBD, 0xAC, 0x51, 0x0C, 0x31, 0xAF, 0x45, 0xD0 }} + gPerfSaValidateGuid =3D { 0xA73B382B, 0x= 62D4, 0x4A19, { 0xBB, 0xF9, 0x09, 0x3E, 0xC5, 0xA5, 0x93, 0x11 }} + gPerfHeciPreMemGuid =3D { 0xD815D922, 0x= 4994, 0x40B3, { 0x97, 0xCC, 0x07, 0xF3, 0x7D, 0x42, 0xE7, 0x97 }} + gPerfPchPreMemGuid =3D { 0xBB73E2B1, 0x= B9FD, 0x4A80, { 0xB8, 0x1A, 0x52, 0x39, 0xE9, 0x4D, 0x06, 0x2E }} + gPerfCpuPreMemGuid =3D { 0xAC5FCBC6, 0x= 084D, 0x445D, { 0xB3, 0xF3, 0xCA, 0x16, 0xDE, 0xE9, 0xBB, 0x47 }} + gPerfMePreMemGuid =3D { 0x6051338E, 0x= 0FFA, 0x40F7, { 0xAF, 0xEF, 0xAB, 0x86, 0x7A, 0x38, 0xCC, 0xF3 }} + gPerfAmtPreMemGuid =3D { 0xDB732D50, 0x= 9BB8, 0x489A, { 0xA1, 0xD1, 0xDD, 0xD2, 0x16, 0x1D, 0x72, 0xB8 }} + gPerfSaPreMemGuid =3D { 0x76F18BDA, 0x= 2195, 0x4FB6, { 0x9A, 0x94, 0x0E, 0x0B, 0xAC, 0xDE, 0xEC, 0xAB }} + gPerfEvlGuid =3D { 0x8221518B, 0x= AC19, 0x4E32, { 0xAB, 0x5F, 0x00, 0x47, 0x0A, 0x50, 0x69, 0x40 }} + gPerfMemGuid =3D { 0x2B57B316, 0x= 5CF7, 0x4847, { 0xB0, 0x76, 0x6B, 0x5D, 0x23, 0xC3, 0xAA, 0x3E }} + gPlatformGpioConfigGuid =3D { 0xd66acbe3, 0x= 3293, 0x4ba1, { 0xb0, 0x0b, 0xb3, 0x8f, 0x64, 0x8d, 0x8d, 0x5e }} + +[Protocols] + ## Include/Protocol/SiliconRegAccess.h + gUsraProtocolGuid =3D { 0xfd480a76, 0x= b134, 0x4ef7, { 0xad, 0xfe, 0xb0, 0xe0, 0x54, 0x63, 0x98, 0x07 }} + + # + # Uncore + # + gEfiIioUdsProtocolGuid =3D { 0xa7ced760, 0x= c71c, 0x4e1a, { 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, 0xcb }} + gEfiIioSystemProtocolGuid =3D { 0xddc3080a, 0x= 2740, 0x4ec2, { 0x9a, 0xa5, 0xa0, 0xad, 0xef, 0xd6, 0xff, 0x9c }} + gEfiCpuCsrAccessGuid =3D { 0x0067835f, 0x= 9a50, 0x433a, { 0x8c, 0xbb, 0x85, 0x20, 0x78, 0x19, 0x78, 0x14 }} + gEfiQuiesceProtocolGuid =3D { 0x20d6e759, 0x= 4c4a, 0x40c0, { 0x95, 0x33, 0x2b, 0xf0, 0x06, 0x68, 0x50, 0xfd }} + gEfiGlobalNvsAreaProtocolGuid =3D { 0x074e1e48, 0x= 8132, 0x47a1, { 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }} + gEfiHpIoxAccessGuid =3D { 0x62652b53, 0x= 79d9, 0x4cf2, { 0xb5, 0xaa, 0xad, 0x99, 0x81, 0x0a, 0x7f, 0x17 }} + gEfiPciCallbackProtocolGuid =3D { 0x1ca0e202, 0x= fe9e, 0x4776, { 0x9f, 0xaa, 0x57, 0x0c, 0x19, 0x61, 0x7a, 0x06 }} + + # + # Pch + # + gEfiSpiProtocolGuid =3D { 0xf8b84ae6, 0x= 8465, 0x4f95, { 0x9f, 0x0b, 0xea, 0xaa, 0x37, 0xc6, 0x15, 0x5a }} + gEfiActiveBiosProtocolGuid =3D { 0xebbe2d1b, 0x= 1647, 0x4bda, { 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a }} + gEfiSerialGpioProtocolGuid =3D { 0xf52c3858, 0x= 5ef8, 0x4d41, { 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 }} + gWdtProtocolGuid =3D { 0xB42B8D12, 0x= 2ACB, 0x499a, { 0xA9, 0x20, 0xDD, 0x5B, 0xE6, 0xCF, 0x09, 0xB1 }} + gPchPlatformPolicyProtocolGuid =3D { 0x782ee5ae, 0x= 586b, 0x47c1, { 0xa4, 0x1d, 0xce, 0x7f, 0xa0, 0x9c, 0x25, 0x9a }} + gEfiPchS3SupportProtocolGuid =3D { 0x2224aee3, 0x= 8d0b, 0x480a, { 0xb2, 0x72, 0x2a, 0xbe, 0x92, 0xcd, 0x4e, 0x78 }} + gEfiPchInfoProtocolGuid =3D { 0x984eb4e9, 0x= 5a95, 0x41de, { 0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0 }} + gEfiSmmSmbusProtocolGuid =3D { 0x72e40094, 0x= 2ee1, 0x497a, { 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c }} + gEfiSmmSpiProtocolGuid =3D { 0xbd75fe35, 0x= fdce, 0x49d7, { 0xa9, 0xdd, 0xb2, 0x6f, 0x1f, 0xc6, 0xb4, 0x37 }} + gEfiSmmIchnDispatchExProtocolGuid =3D { 0x3920405b, 0x= c897, 0x44da, { 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 }} + gEfiSmmIoTrapDispatchProtocolGuid =3D { 0xdb7f536b, 0x= ede4, 0x4714, { 0xa5, 0xc8, 0xe3, 0x46, 0xeb, 0xaa, 0x20, 0x1d }} + gPchResetCallbackProtocolGuid =3D { 0x3a3300ab, 0x= c929, 0x487d, { 0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0 }} + gPchResetProtocolGuid =3D { 0xdb63592c, 0x= b8cc, 0x44c8, { 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a }} + gEfiGlobalNvsAreaProtocolGuid =3D { 0x074e1e48, 0x= 8132, 0x47a1, { 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }} + gPchSmmIoTrapControlGuid =3D { 0x514D2AFD, 0x= 2096, 0x4283, { 0x9D, 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 }} + gEfiPchSetTmcSrcClkProtocolGuid =3D { 0xfbaa2549, 0x= 053d, 0x4012, { 0x86, 0x6c, 0x7a, 0x86, 0xcc, 0x21, 0xae, 0x21 }} + gPchPlatformPolicyProtocolGuid =3D { 0x782ee5ae, 0x= 586b, 0x47c1, { 0xa4, 0x1d, 0xce, 0x7f, 0xa0, 0x9c, 0x25, 0x9a }} + gPchInfoProtocolGuid =3D { 0x984eb4e9, 0x= 5a95, 0x41de, { 0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0 }} + gPchNvsAreaProtocolGuid =3D { 0x2E058B2B, 0x= EDC1, 0x4431, { 0x87, 0xD9, 0xC6, 0xC4, 0xEA, 0x10, 0x2B, 0xE3 }} + gPchSerialIoUartDebugInfoProtocolGuid =3D { 0x2fd2b1bd, 0x= 0387, 0x4ec6, { 0x94, 0x1f, 0xf1, 0x4b, 0x7f, 0x1c, 0x94, 0xb6 }} + gHeciProtocolGuid =3D { 0xcfb33810, 0x= 6e87, 0x4284, { 0xb2, 0x03, 0xa6, 0x6a, 0xbe, 0x07, 0xf6, 0xe8 }} + gPchSerialGpioProtocolGuid =3D { 0xf52c3858, 0x= 5ef8, 0x4d41, { 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 }} + gEfiLoadPeImageProtocolGuid =3D { 0x5CB5C776, 0x= 60D5, 0x45EE, { 0x88, 0x3C, 0x45, 0x27, 0x08, 0xCD, 0x74, 0x3F }} + gEfiSmmVariableProtocolGuid =3D { 0xed32d533, 0x= 99e6, 0x4209, { 0x9c, 0xc0, 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7 }} + gDxePchPlatformResetPolicyProtocolGuid =3D { 0x45ada968, 0x= a8c5, 0x4f30, { 0xac, 0xd4, 0xf5, 0x13, 0xbc, 0xe5, 0xb0, 0xb3 }} + gDxePchPlatformPolicyProtocolGuid =3D { 0x4b0165a9, 0x= 61d6, 0x4e23, { 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 }} + gEfiLegacyInterruptProtocolGuid =3D { 0x31ce593d, 0x= 108a, 0x485d, { 0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe }} + gEfiSmmIchnDispatchProtocolGuid =3D { 0xc50b323e, 0x= 9075, 0x4f2a, { 0xac, 0x8e, 0xd2, 0x59, 0x6a, 0x10, 0x85, 0xcc }} + gEfiLegacy8259ProtocolGuid =3D { 0x38321dba, 0x= 4fe0, 0x4e17, { 0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1 }} + gPlatformEmmcInfoProtocolGuid =3D { 0xf103dd83, 0x= 3b17, 0x4e1e, { 0x9b, 0x80, 0x5d, 0xcc, 0x9c, 0x59, 0x0b, 0x2f }} + gPchEmmcTuningProtocolGuid =3D { 0x10fe7e3b, 0x= dbe5, 0x4cfa, { 0x90, 0x25, 0x40, 0x02, 0xcf, 0xdd, 0xbb, 0x89 }} + gPchTcoSmiDispatchProtocolGuid =3D { 0x9E71D609, 0x= 6D24, 0x47FD, { 0xB5, 0x72, 0x61, 0x40, 0xF8, 0xD9, 0xC2, 0xA4 }} + gPchPcieSmiDispatchProtocolGuid =3D { 0x3E7D2B56, 0x= 3F47, 0x42AA, { 0x8F, 0x6B, 0x22, 0xF5, 0x19, 0x81, 0x8D, 0xAB }} + gPchAcpiSmiDispatchProtocolGuid =3D { 0xD52BB262, 0x= F022, 0x49EC, { 0x86, 0xD2, 0x7A, 0x29, 0x3A, 0x7A, 0x05, 0x4B }} + gPchGpioUnlockSmiDispatchProtocolGuid =3D { 0x83339EF7, 0x= 9392, 0x4716, { 0x8D, 0x3A, 0xD1, 0xFC, 0x67, 0xCD, 0x55, 0xDB }} + gPchSmiDispatchProtocolGuid =3D { 0x4566C59F, 0x= 650B, 0x4B63, { 0xB1, 0xEF, 0x4F, 0x36, 0x66, 0x54, 0x4B, 0xEF }} + gEfiSmmIchnDispatch2ProtocolGuid =3D { 0xe0f0cc19, 0x= 8912, 0x4077, { 0xbf, 0x8a, 0x6a, 0x5c, 0x27, 0x0a, 0x3e, 0x65 }} + gEfiSmmIchnDispatch2ExProtocolGuid =3D { 0x8497455b, 0x= b489, 0x4ac7, { 0xbd, 0x51, 0x78, 0xdf, 0x4e, 0x1f, 0x1a, 0xcd }} + gPchEspiSmiDispatchProtocolGuid =3D { 0xca236c1b, 0x= 625c, 0x4753, { 0xb5, 0x53, 0x19, 0x05, 0xfc, 0xec, 0x2e, 0xa7 }} + gPchPcieIoTrapProtocolGuid =3D { 0xd66a1cf, 0x= 79ad, 0x494b, { 0x97, 0x8b, 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 }} + gPchSataEfiLoadProtocolGuid =3D { 0xaee24780, 0x= 4511, 0x4f23, { 0xa0, 0x28, 0xeb, 0x82, 0x04, 0xd4, 0x82, 0x9c }} + gPchsSataEfiLoadProtocolGuid =3D { 0x8580afee, 0x= 40ad, 0x4f63, { 0xa5, 0x48, 0x3d, 0x7f, 0x4a, 0x09, 0x86, 0x7d }} + gPchSmmPeriodicTimerControlGuid =3D { 0x6906E93B, 0x= 603B, 0x4A0F, { 0x86, 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB }} + +[Ppis] + ## Include/Protocol/SiliconRegAccess.h + gUsraPpiGuid =3D { 0x90766a99, 0x= 9ca5, 0x44de, { 0x94, 0xda, 0xdc, 0xc1, 0xd2, 0xd6, 0xda, 0x1f }} + + # + # Uncore + # + gPeiBaseMemoryTestPpiGuid =3D { 0xb6ec423c, 0x= 21d2, 0x490d, { 0x85, 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74 }} + gPeiPlatformMemorySizePpiGuid =3D { 0x9a7ef41e, 0x= c140, 0x4bd1, { 0xb8, 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6 }} + gPeiMpServicePpiGuid =3D { 0xee16160a, 0x= e8be, 0x47a6, { 0x82, 0x0a, 0xc6, 0x90, 0x0d, 0xb0, 0x25, 0x0a }} + + # + # Pch + # + gPchPmcXramOffsetDataPpiGuid =3D { 0xc1392859, 0x= 1f65, 0x446e, { 0xa3, 0xf6, 0x85, 0x36, 0xfc, 0xc7, 0xd1, 0xc4 }} + gPchPlatformPolicyPpiGuid =3D { 0xdfe2b897, 0x= 0e8e, 0x4926, { 0xbc, 0x69, 0xe5, 0xed, 0xd3, 0xf9, 0x38, 0xe1 }} + gPchInitPreMemDonePpiGuid =3D { 0xb795d447, 0x= 7524, 0x4819, { 0xa6, 0x2c, 0xff, 0x6f, 0x46, 0x71, 0xf2, 0xff }} + gPeiUsbControllerPpiGuid =3D { 0x3BC1F6DE, 0x= 693E, 0x4547, { 0xA3, 0x00, 0x21, 0x82, 0x3C, 0xA4, 0x20, 0xB2 }} + gPchUsbPolicyPpiGuid =3D { 0xc02b0573, 0x= 2b4e, 0x4a31, { 0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c }} + gPchInitPpiGuid =3D { 0x908c7f8b, 0x= 5c48, 0x47fb, { 0x83, 0x57, 0xf5, 0xfd, 0x4e, 0x23, 0x52, 0x76 }} + gWdtPpiGuid =3D { 0xF38D1338, 0x= AF7A, 0x4FB6, { 0x91, 0xDB, 0x1A, 0x9C, 0x21, 0x83, 0x57, 0x0D }} + gPeiSpiPpiGuid =3D { 0xfbf26154, 0x= 4e55, 0x4bdc, { 0xaf, 0x7b, 0xd9, 0x18, 0xac, 0x44, 0x3f, 0x61 }} + gPchDmiTcVcMapPpiGuid =3D { 0xed097352, 0x= 9041, 0x445a, { 0x80, 0xb6, 0xb2, 0x9d, 0x50, 0x9e, 0x88, 0x45 }} + gPeiSmbusPolicyPpiGuid =3D { 0x63b6e435, 0x= 32bc, 0x49c6, { 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c }} + gPchResetCallbackPpiGuid =3D { 0x17865dc0, 0x= 0b8b, 0x4da8, { 0x8b, 0x42, 0x7c, 0x46, 0xb8, 0x5c, 0xca, 0x4d }} + gPchPeiInitDonePpiGuid =3D { 0x1edcbdf9, 0x= ffc6, 0x4bd4, { 0x94, 0xf6, 0x19, 0x5d, 0x1d, 0xe1, 0x70, 0x56 }} + gPchResetPpiGuid =3D { 0x433e0f9f, 0x= 05ae, 0x410a, { 0xa0, 0xc3, 0xbf, 0x29, 0x8e, 0xcb, 0x25, 0xac }} + gPchHdaVerbTablePpiGuid =3D { 0x220307a4, 0x= 3670, 0x42a5, { 0xaa, 0x01, 0x32, 0x9d, 0xcd, 0x3e, 0x91, 0x6b }} + gPchPcieDeviceTablePpiGuid =3D { 0xaf4a1998, 0x= 4949, 0x4545, { 0x9c, 0x4c, 0xc1, 0xe7, 0xc0, 0x42, 0xe0, 0x56 }} + gPchSmmIoTrapControlGuid =3D { 0x514D2AFD, 0x= 2096, 0x4283, { 0x9D, 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 }} + gSaPlatformPolicyPpiGuid =3D { 0x573eaf99, 0x= f445, 0x46b5, { 0xa5, 0xd5, 0xbc, 0x4a, 0x93, 0x35, 0x98, 0xf3 }} + gPeiSmmControlPpiGuid =3D { 0x61c68702, 0x= 4d7e, 0x4f43, { 0x8d, 0xef, 0xa7, 0x43, 0x05, 0xce, 0x74, 0xc5 }} + gPchHsioPtssTablePpiGuid =3D { 0x220307a4, 0x= 3671, 0x42b5, { 0xaa, 0x02, 0x32, 0x9d, 0xcd, 0x3e, 0x91, 0x6b }} + gDirtyWarmResetSignalGuid =3D { 0x24b9a592, 0x= 4cfc, 0x4c8f, { 0x86, 0xf4, 0x87, 0x28, 0x2d, 0x7f, 0x9e, 0x9c }} + gDirtyWarmResetGuid =3D { 0xe60fe263, 0x= ac2b, 0x43d6, { 0xb3, 0xc7, 0x0d, 0x9d, 0xdc, 0x5a, 0x99, 0x1c }} + +[PcdsFeatureFlag] + ## Indicate whether USRA can support S3 + gEfiCpRcPkgTokenSpaceGuid.PcdUsraSupportS3|TRUE|BOOLEAN|0x00000012 + + ## Use this feature PCD to support Single PCIe segment with static MMCFG= Base + gEfiCpRcPkgTokenSpaceGuid.PcdSingleSegFixMmcfg|TRUE|BOOLEAN|0x00000014 + + ## enable/disable USRA trace. + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceEnable|FALSE|BOOLEAN|0x00000016 + + ## enable/disable Quiesce feature. + gEfiCpRcPkgTokenSpaceGuid.PcdQuiesceSupport|TRUE|BOOLEAN|0x00000017 + + gEfiCpuTokenSpaceGuid.PcdCpuIvyBridgeFamilyFlag|TRUE|BOOLEAN|0x10000031 + gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|TRUE|BOOLEAN|0x100000= 01 + + ## This PCD specifies whether StatusCode is reported via USB Serial port. + gEfiCpuTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE|BOOLEAN|0x1000000F + +[PcdsFixedAtBuild] + ## Indicates the size of each PCIE segment + gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize|0x10000000|UINT64|0x00000010 + gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg|0x00000008|UINT32|0x00000013 + ## Indicates the max nested level + gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000008|UINT32|0x00000018 + ## Maximum number of sockets supported for this firmware build. + # This PCD should be used sparingly. Dynamic allocation of data and + # dynamic control flows are preferred over using this PCD for static + # data allocation and control. + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|0x04|UINT32|0x00000019 + + gPlatformTokenSpaceGuid.PcdBusStack|0x06|UINT8|0x30000006 + gPlatformTokenSpaceGuid.PcdUboDev|0x08|UINT8|0x3000000D + gPlatformTokenSpaceGuid.PcdUboFunc|0x02|UINT8|0x3000000E + gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC|UINT8|0x3000000F + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0x00FFD00000|UINT32|= 0x2000000D + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x0000300000|UINT32|= 0x2000000E + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|0xFFFB0000|UINT3= 2|0x30000004 + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize|0x00010000|UINT3= 2|0x30000005 + gCpuUncoreTokenSpaceGuid.PcdWaSlowModeEnable|0|BOOLEAN|0x30000008 + + gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress|0x500|UINT16|0x30000003 + gEfiPchTokenSpaceGuid.PcdSmmActivationData|0x55|UINT8|0x30000005 + gEfiPchTokenSpaceGuid.PcdSmmActivationPort|0xb2|UINT16|0x30000001 + gEfiPchTokenSpaceGuid.PcdSmmDataPort|0xb3|UINT16|0x30000002 + gEfiCommonPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT3= 2|0x30001033 + + ## From MdeModulePkg.dec + ## Progress Code for S3 Suspend end. + # PROGRESS_CODE_S3_SUSPEND_END =3D (EFI_SOFTWARE_SMM_DRIVER | (EFI_OE= M_SPECIFIC | 0x00000001)) =3D 0x03078001 + gEfiPchTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30= 001033 + + ## TraceHub Configuration + ## PcdTraceHubEnMode: 0 for Disabled, 1 for Internal Debugger, 2 for Hos= t Debugger + + ## TraceHub temporary disabled, until TraceHubInitialize is not working = correctly. Sighting 4929727. + gEfiPchTokenSpaceGuid.PcdTraceHubEnMode|0x00|UINT8|0x30003001 + + ## PcdTraceHubEnFWTrace: 0 for Disabled, 1 for Enabled + gEfiPchTokenSpaceGuid.PcdTraceHubEnFwTrace|0x01|UINT8|0x30003002 + ## PcdTraceHubDest: 0 for Mem, 1 for PTI, 2 for USB3, 3 for BSSB + gEfiPchTokenSpaceGuid.PcdTraceHubDest|0x02|UINT8|0x30003003 + ## PcdTraceHubTempCsrMtbBar: Temporary CSR MTB BAR + gEfiPchTokenSpaceGuid.PcdTraceHubTempCsrMtbBar|0xFE100000|UINT32|0x30003= 004 + + gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x100000= 01 + gEfiPchTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x10000002 + +[PcdsFixedAtBuild,PcdsPatchableInModule] + ## From MdeModulePkg.dec + ## Default OEM ID for ACPI table creation, its length must be 0x6 bytes = to follow ACPI specification. + gEfiPchTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034 + ## Default OEM Table ID for ACPI table creation, it is "EDK2 ". + gEfiPchTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64= |0x30001035 + ## Default OEM Revision for ACPI table creation. + gEfiPchTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0x3000= 1036 + ## Default Creator ID for ACPI table creation. + gEfiPchTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x300010= 37 + ## Default Creator Revision for ACPI table creation. + gEfiPchTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x= 30001038 + gEfiPchTokenSpaceGuid.PcdSmbusBaseAddress|0x0780|UINT16|0x00010031 + gEfiPchTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034 + + ## + ## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection + ## value of the struct + ## 0x00 EfiGcdAllocateAnySearchBottomUp + ## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp + ## 0x03 EfiGcdAllocateAnySearchTopDown + ## 0x04 EfiGcdAllocateMaxAddressSearchTopDown + ## + ## below value should not using in this situation + ## 0x05 EfiGcdMaxAllocateType : design for max value of struct + ## 0x02 EfiGcdAllocateAddress : design for speccification address alloc= ate + ## + gEfiPchTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000 + +[PcdsDynamicEx] + ## | = MMCFG Table Header | = Segment 0 | = Segment 1 | = Segment 2 |= Segment 3 = | Segment 4 = | Segment 5 = | Segment 6 = | Segment 7 = | + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0}|VOID*|0x00000011 + gEfiCpRcPkgTokenSpaceGuid.PcdRcRevision|0|UINT32|0x00000015 + + gPlatformTokenSpaceGuid.PcdFpgaSwSmiInputValue|0|UINT8|0x30000007 + gEfiCpuTokenSpaceGuid.PcdSbspSelection|0xFF|UINT8|0x6000801B + gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue|0x0|UINT8|0x60008009 + gEfiCpuTokenSpaceGuid.PcdCpuTurboOverride|0x0|UINT32|0x60008022 + gEfiCpuTokenSpaceGuid.PcdCpuProcessorMsrLockCtrl|0x0|UINT8|0x60008018 + gEfiCpuTokenSpaceGuid.PcdCpuIioLlcWaysBitMask|0x0|UINT64|0x60008019 + gEfiCpuTokenSpaceGuid.PcdCpuExpandedIioLlcWaysBitMask|0x0|UINT64|0x60008= 01C + gEfiCpuTokenSpaceGuid.PcdCpuRemoteWaysBitMask|0x0|UINT64|0x60008023 + gEfiCpuTokenSpaceGuid.PcdPchTraceHubEn|0x0|UINT8|0x6000801D + gEfiCpuTokenSpaceGuid.PcdCpuQlruCfgBitMask|0x0|UINT64|0x6000801A + gEfiCpuTokenSpaceGuid.PcdCpuPmStructAddr|0x0|UINT64|0x60008020 + gEfiCpuTokenSpaceGuid.PcdCpuRRQCountThreshold|0x0|UINT64|0x60008024 + gPlatformTokenSpaceGuid.PcdPlatformType|0x00000000|UINT8|0x30000041 + ## PCD for ServerCommonPkg\Override\IA32FamilyCpuPkg\CpuMpDxe.inf + ## This PCD is the AP state on POST. The value is defined as below. + # 1: ApInHltLoop, AP is in the Hlt-Loop state. + # 2: ApInMwaitLoop, AP is in the Mwait-Loop state. + # 3: ApInRunLoop, AP is in the Run-Loop state. + gEfiCpuTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x10001004 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + gEfiPchTokenSpaceGuid.PcdWakeOnRTCS5|FALSE|BOOLEAN|0x30000018 + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeHour|0|UINT8|0x30000019 + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeMinute|0|UINT8|0x30000020 + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeSecond|0|UINT8|0x30000021 + gEfiPchTokenSpaceGuid.PcdPchSataInitReg78Data|0x88880000|UINT32|0x300000= 07 + gEfiPchTokenSpaceGuid.PcdPchSataInitReg88Data|0x88338822|UINT32|0x300000= 09 + + ## + ## SerialIo Uart Configuration + ## + gEfiPchTokenSpaceGuid.PcdSerialIoUartDebugEnable|FALSE|BOOLEAN|0x00100001 + gEfiPchTokenSpaceGuid.PcdSerialIoUartNumber|2|UINT8|0x00100002 + + # + # PcdFviSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF) defined= in SMBIOS, + # values 0-0x7F will be treated as disable FVI reporting. + # FVI structure uses it as SMBIOS OEM type to provide version informatio= n. + # + gEfiPchTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x00010037 diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgCommonLib.dsc b/Sil= icon/Intel/PurleyRefreshSiliconPkg/SiPkgCommonLib.dsc new file mode 100644 index 0000000000..1ba7285f79 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgCommonLib.dsc @@ -0,0 +1,33 @@ +## @file +# Build description file for Purley Refresh silicon PEI and DXE libraries. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[LibraryClasses.common] + + # + # Uncore + # + PcieAddrLib|$(PLATFORM_SI_PACKAGE)/Library/PcieAddressLib/PcieAddressLib= .inf + SiliconAccessLib|$(PLATFORM_SI_PACKAGE)/Library/UsraAccessLib/UsraAccess= Lib.inf + CsrToPcieLib|$(PLATFORM_SI_PACKAGE)/Library/CsrToPcieLibNull/BaseCsrToPc= ieLibNull.inf + PcieAddrLib|$(PLATFORM_SI_PACKAGE)/Library/PcieAddressLib/PcieAddressLib= .inf + MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/MmPciBaseLib/MmPciBaseLib.inf + + # + # Pch + # + GpioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpi= oLib.inf + PchPolicyLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchPolicyLib/PeiPchPo= licyLib.inf + PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchCycle= DecodingLib/PeiDxeSmmPchCycleDecodingLib.inf + PchGbeLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchGbeLib/PeiDxeSm= mPchGbeLib.inf + PchInfoLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxe= SmmPchInfoLib.inf + PchP2sbLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchP2sbLib/PeiDxe= SmmPchP2sbLib.inf + PchPcrLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPcrLib/PeiDxeSm= mPchPcrLib.inf + PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSbiAccess= Lib/PeiDxeSmmPchSbiAccessLib.inf + PchResetCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/LibraryPrivate/BasePchReset= CommonLib/BasePchResetCommonLib.inf + PchPmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSm= mPchPmcLib.inf diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc b/Silico= n/Intel/PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc new file mode 100644 index 0000000000..be40e45d69 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc @@ -0,0 +1,22 @@ +## @file +# Build description file for Purley Refresh silicon DXE libraries. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[LibraryClasses.common.DXE_DRIVER] + MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.= inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.= inf + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf + +[LibraryClasses.common.DXE_SMM_DRIVER] + MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.= inf + CsrToPcieLib|$(PLATFORM_SI_PACKAGE)/Library/CsrToPcieLib/CsrToPcieDxeLib= .inf + SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLi= b/SmmSpiFlashCommonLib.inf + +[LibraryClasses.X64.UEFI_APPLICATION] diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc b/Silico= n/Intel/PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc new file mode 100644 index 0000000000..98c83dc097 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc @@ -0,0 +1,12 @@ +## @file +# Build description file for Purley Refresh silicon PEI libraries. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[LibraryClasses.common.PEIM] + CsrToPcieLib|$(PLATFORM_SI_PACKAGE)/Library/CsrToPcieLib/CsrToPciePeiLib= .inf + PcieAddrLib|$(PLATFORM_SI_PACKAGE)/Library/PcieAddressLib/PcieAddressLib= .inf --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Tue, 11 May 2021 02:48:43 -0700 IronPort-SDR: 5qwnaER2cgaClfnGwgP0Zvy/pClFcVr2llsxTukiu/IzjHWHsJOrTrAeZzKOdED1Kth2ywFbI2 5M1CYIlVh1OQ== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="179664951" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="179664951" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:42 -0700 IronPort-SDR: mF/ezWX3qBkcpX8aHsfySe1oT/O6CdMr0Lv/+vHC5PSFKsSEdhY3tGo4b5k6vSJ7JqYsJISP7a 6Tn7bGt26ZFw== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436573924" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:41 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 02/18] PurleyRefreshSiliconPkg/Pch: Add Register Header Files Date: Tue, 11 May 2021 02:48:10 -0700 Message-Id: <20210511094826.12495-3-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: 0w7hwXuq6XlRPgDzrg0GsslFx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726524; bh=rEHDiQVHl3EmURenGtyeesPxR8BDwA8Rwo9r12jVOvk=; h=Cc:Date:From:Reply-To:Subject:To; b=X49Iq6U/H/K7p8EAUQ/HUAwFexTgR7Ul5WCvHFTSRP39fD205Hkf1UxmI7vBFyUrcCl YMuWZjUHCUpZeDgOp2fcYM/qVPuE2ZGS51IEcRYqpa82MRu0HIBNnjj9rnqvh68UCop7h +3aSbzRpZUKAv62jNVwe6hZX2dV99PVSCzM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../Pch/Include/Register/PchRegsDci.h | 24 + .../Pch/Include/Register/PchRegsDmi.h | 188 ++++++ .../Pch/Include/Register/PchRegsEva.h | 110 +++ .../Pch/Include/Register/PchRegsFia.h | 81 +++ .../Pch/Include/Register/PchRegsGpio.h | 511 ++++++++++++++ .../Pch/Include/Register/PchRegsHda.h | 226 +++++++ .../Pch/Include/Register/PchRegsHsio.h | 171 +++++ .../Pch/Include/Register/PchRegsIsh.h | 51 ++ .../Pch/Include/Register/PchRegsItss.h | 68 ++ .../Pch/Include/Register/PchRegsLan.h | 135 ++++ .../Pch/Include/Register/PchRegsLpc.h | 430 ++++++++++++ .../Pch/Include/Register/PchRegsP2sb.h | 100 +++ .../Pch/Include/Register/PchRegsPcie.h | 513 ++++++++++++++ .../Pch/Include/Register/PchRegsPcr.h | 64 ++ .../Pch/Include/Register/PchRegsPmc.h | 627 +++++++++++++++++ .../Pch/Include/Register/PchRegsPsf.h | 210 ++++++ .../Pch/Include/Register/PchRegsPsth.h | 46 ++ .../Pch/Include/Register/PchRegsSata.h | 634 ++++++++++++++++++ .../Pch/Include/Register/PchRegsScs.h | 152 +++++ .../Pch/Include/Register/PchRegsSerialIo.h | 282 ++++++++ .../Pch/Include/Register/PchRegsSmbus.h | 134 ++++ .../Pch/Include/Register/PchRegsSpi.h | 291 ++++++++ .../Pch/Include/Register/PchRegsThermal.h | 93 +++ .../Pch/Include/Register/PchRegsTraceHub.h | 125 ++++ .../Pch/Include/Register/PchRegsUsb.h | 463 +++++++++++++ 25 files changed, 5729 insertions(+) create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsDci.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsDmi.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsEva.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsFia.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsGpio.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsHda.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsHsio.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsIsh.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsItss.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsLan.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsLpc.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsP2sb.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsPcie.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsPcr.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsPmc.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsPsf.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsPsth.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsSata.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsScs.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsSerialIo.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsSmbus.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsSpi.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsThermal.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsTraceHub.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Regis= ter/PchRegsUsb.h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsDci.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsDci.h new file mode 100644 index 0000000000..93d54793f3 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsDci= .h @@ -0,0 +1,24 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_DCI_H_ +#define _PCH_REGS_DCI_H_ + +// +// DCI PCR Registers +// +#define R_PCH_PCR_DCI_ECTRL 0x04 ///< DCI= Control Register +#define B_PCH_PCR_DCI_ECTRL_HDCILOCK BIT0 ///< Hos= t DCI lock +#define B_PCH_PCR_DCI_ECTRL_HDCIEN BIT4 ///< Hos= t DCI enable +#define R_PCH_PCR_DCI_ECKPWRCTL 0x08 ///< DCI= Power Control +#define R_PCH_PCR_DCI_PCE 0x30 ///< DCI= Power Control Enable Register +#define B_PCH_PCR_DCI_PCE_HAE BIT5 ///< Har= dware Autonomous Enable +#define B_PCH_PCR_DCI_PCE_D3HE BIT2 ///< D3-= Hot Enable +#define B_PCH_PCR_DCI_PCE_I3E BIT1 ///< I3 = Enable +#define B_PCH_PCR_DCI_PCE_PMCRE BIT0 ///< PMC= Request Enable + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsDmi.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsDmi.h new file mode 100644 index 0000000000..098cac742a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsDmi= .h @@ -0,0 +1,188 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_DMI_H_ +#define _PCH_REGS_DMI_H_ + +// +// DMI Chipset Configuration Registers (PID:DMI) +// + +// +// VC Configuration (Common) +// +#define R_PCH_PCR_DMI_V0CTL 0x2014 /= //< Virtual channel 0 resource control +#define B_PCH_PCR_DMI_V0CTL_EN BIT31 +#define B_PCH_PCR_DMI_V0CTL_ID (7 << 24) /= //< Bit[26:24] +#define N_PCH_PCR_DMI_V0CTL_ID 24 +#define V_PCH_PCR_DMI_V0CTL_ETVM_MASK 0xFC00 +#define V_PCH_PCR_DMI_V0CTL_TVM_MASK 0x7E +#define R_PCH_PCR_DMI_V0STS 0x201A /= //< Virtual channel 0 status +#define B_PCH_PCR_DMI_V0STS_NP BIT1 +#define R_PCH_PCR_DMI_V1CTL 0x2020 /= //< Virtual channel 1 resource control +#define B_PCH_PCR_DMI_V1CTL_EN BIT31 +#define B_PCH_PCR_DMI_V1CTL_ID (0x0F << 24) /= //< Bit[27:24] +#define N_PCH_PCR_DMI_V1CTL_ID 24 +#define V_PCH_PCR_DMI_V1CTL_ETVM_MASK 0xFC00 +#define V_PCH_PCR_DMI_V1CTL_TVM_MASK 0xFE +#define R_PCH_PCR_DMI_V1STS 0x2026 /= //< Virtual channel 1 status +#define B_PCH_PCR_DMI_V1STS_NP BIT1 +#define R_PCH_PCR_DMI_VMCTL 0x2040 /= //< ME Virtual Channel (VCm) resource control +#define R_PCH_PCR_DMI_VMSTS 0x2046 /= //< ME Virtual Channel Resource Status +#define R_PCH_PCR_DMI_UEM 0x2088 /= //< Uncorrectable Error Mask +#define R_PCH_PCR_DMI_REC 0x20AC /= //< Root Error Command + +// +// Internal Link Configuration (DMI Only) +// +#define R_PCH_PCR_DMI_LCAP 0x21A4 /= //< Link Capabilities +#define B_PCH_PCR_DMI_LCAP_EL1 (BIT17 | BIT16 | BIT15) +#define B_PCH_PCR_DMI_LCAP_EL0 (BIT14 | BIT13 | BIT12) +#define B_PCH_PCR_DMI_LCAP_APMS (BIT11 | BIT10) /= //< L0 is supported on DMI +#define B_PCH_PCR_DMI_LCAP_MLW 0x000003F0 +#define B_PCH_PCR_DMI_LCAP_MLS 0x0000000F +#define R_PCH_PCR_DMI_LCTL 0x21A8 /= //< Link Control +#define B_PCH_PCR_DMI_LCTL_ES BIT7 +#define B_PCH_PCR_DMI_LCTL_ASPM (BIT1 | BIT0) /= //< Link ASPM +#define R_PCH_PCR_DMI_LSTS 0x21AA /= //< Link Status +#define R_PCH_PCR_DMI_LCTL2 0x21B0 /= //< Link Control 2 +#define R_PCH_PCR_DMI_LSTS2 0x21B2 /= //< Link Status 2 +#define R_PCH_PCR_DMI_L01EC 0x21BC /= //< Lane 0 and Lane 1 Equalization Control +#define R_PCH_PCR_DMI_L23EC 0x21C0 /= //< Lane 2 and Lane 3 Equalization Control +#define B_PCH_PCR_DMI_UPL13RPH 0x0F000000 /= //< Upstream Port Lane 1/3 Transmitter Preset Hint mask +#define N_PCH_PCR_DMI_UPL13RPH 24 /= //< Upstream Port Lane 1/3 Transmitter Preset Hint value offset +#define B_PCH_PCR_DMI_UPL02RPH 0x000000F0 /= //< Upstream Port Lane 0/2 Transmitter Preset Hint mask +#define N_PCH_PCR_DMI_UPL02RPH 8 /= //< Upstream Port Lane 0/2 Transmitter Preset Hint value offset +#define V_PCH_PCR_DMI_UPL0RPH 7 /= //< Upstream Port Lane 0 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL1RPH 7 /= //< Upstream Port Lane 1 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL2RPH 7 /= //< Upstream Port Lane 2 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL3RPH 7 /= //< Upstream Port Lane 3 Transmitter Preset Hint value + + +// +// North Port Error Injection Configuration (DMI Only) +// +#define R_PCH_PCR_DMI_DMIEN 0x2230 /= //< DMI Error Injection Enable + +// +// DMI Control +// +#define R_PCH_PCR_DMI_DMIC 0x2234 = ///< DMI Control +#define B_PCH_PCR_DMI_DMIC_SRL BIT31 = ///< Secured register lock +#define B_PCH_PCR_DMI_DMIC_ORCE (BIT25 | BIT24) = ///< Offset Re-Calibration Enable +#define N_PCH_PCR_DMI_DMIC_ORCE 24 +#define V_PCH_PCR_DMI_DMIC_ORCE_EN_GEN2_GEN3 1 = ///< Enable offset re-calibration for Gen 2 and Gen 3 data rate only. +#define B_PCH_PCR_DMI_DMIC_DMICGEN (BIT4 | BIT3 | BIT2 | BIT1 | = BIT0) ///< DMI Clock Gate Enable +#define R_PCH_PCR_DMI_DMIHWAWC 0x2238 = ///< DMI HW Autonomus Width Control +#define R_PCH_PCR_DMI_IOSFSBCS 0x223E = ///< IOSF Sideband Control and Status +#define B_PCH_PCR_DMI_IOSFSBCS_DMICGEN (BIT6 | BIT5 | BIT3 | BIT2) = ///< DMI Clock Gate Enable + +#define R_PCH_PCR_DMI_2300 0x2300 +#define R_PCH_PCR_DMI_2304 0x2304 +#define R_PCH_PCR_DMI_2310 0x2310 +#define R_PCH_PCR_DMI_2314 0x2314 +#define R_PCH_PCR_DMI_2320 0x2320 +#define R_PCH_PCR_DMI_2324 0x2324 +#define R_PCH_PCR_DMI_232C 0x232C +#define R_PCH_PCR_DMI_2334 0x2334 +#define R_PCH_PCR_DMI_2338 0x2338 +#define R_PCH_PCR_DMI_2340 0x2340 +#define R_PCH_PCR_DMI_2344 0x2344 +#define R_PCH_PCR_DMI_2348 0x2348 +#define R_PCH_PCR_DMI_234C 0x234C + +// +// Port Configuration Extension(DMI Only) +// +#define R_PCH_PCR_DMI_EQCFG1 0x2450 +#define B_PCH_PCR_DMI_EQCFG1_RTLEPCEB BIT16 +#define R_PCH_PCR_DMI_LTCO1 0x2470 /= //< Local Transmitter Coefficient Override 1 +#define R_PCH_PCR_DMI_LTCO2 0x2474 /= //< Local Transmitter Coefficient Override 2 +#define B_PCH_PCR_DMI_L13TCOE BIT25 /= //< Lane 1/3 Transmitter Coefficient Override Enable +#define B_PCH_PCR_DMI_L02TCOE BIT24 /= //< Lane 0/2 Transmitter Coefficient Override Enable +#define B_PCH_PCR_DMI_L13TPOSTCO 0x00fc0000 /= //< Lane 1/3 Transmitter Post-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L13TPOSTCO 18 /= //< Lane 1/3 Transmitter Post-Cursor Coefficient Override value offset +#define B_PCH_PCR_DMI_L13TPRECO 0x0003f000 /= //< Lane 1/3 Transmitter Pre-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L13TPRECO 12 /= //< Lane 1/3 Transmitter Pre-Cursor Coefficient Override value offset +#define B_PCH_PCR_DMI_L02TPOSTCO 0x00000fc0 /= //< Lane 0/2 Transmitter Post-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L02TPOSTCO 6 /= //< Lane 0/2 Transmitter Post-Cursor Coefficient Override value offset +#define B_PCH_PCR_DMI_L02TPRECO 0x0000003f /= //< Lane 0/2 Transmitter Pre-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L02TPRECO 0 /= //< Lane 0/2 Transmitter Pre-Cursor Coefficient Override value offset +#define R_PCH_PCR_DMI_G3L0SCTL 0x2478 /= //< GEN3 L0s Control + +// +// OP-DMI Specific Registers (OP-DMI Only) +// +#define R_PCH_PCR_OPDMI_LCTL 0x2600 = ///< Link Control +#define R_PCH_PCR_OPDMI_STC 0x260C = ///< Sideband Timing Control +#define R_PCH_PCR_OPDMI_LPMC 0x2614 = ///< Link Power Management Control +#define R_PCH_PCR_OPDMI_LCFG 0x2618 = ///< Link Configuration + +// +// DMI Source Decode PCRs (Common) +// +#define R_PCH_PCR_DMI_PCIEPAR1E 0x2700 ///< PCIE Po= rt IOxAPIC Range 1 Enable +#define R_PCH_PCR_DMI_PCIEPAR2E 0x2704 ///< PCIE Po= rt IOxAPIC Range 2 Enable +#define R_PCH_PCR_DMI_PCIEPAR3E 0x2708 ///< PCIE Po= rt IOxAPIC Range 3 Enable +#define R_PCH_PCR_DMI_PCIEPAR4E 0x270C ///< PCIE Po= rt IOxAPIC Range 4 Enable +#define R_PCH_PCR_DMI_PCIEPAR1DID 0x2710 ///< PCIE Po= rt IOxAPIC Range 1 Destination ID +#define R_PCH_PCR_DMI_PCIEPAR2DID 0x2714 ///< PCIE Po= rt IOxAPIC Range 2 Destination ID +#define R_PCH_PCR_DMI_PCIEPAR3DID 0x2718 ///< PCIE Po= rt IOxAPIC Range 3 Destination ID +#define R_PCH_PCR_DMI_PCIEPAR4DID 0x271C ///< PCIE Po= rt IOxAPIC Range 4 Destination ID +#define R_PCH_PCR_DMI_P2SBIOR 0x2720 ///< P2SB IO= Range +#define R_PCH_PCR_DMI_TTTBARB 0x2724 ///< Thermal= Throttling BIOS Assigned Thermal Base Address +#define R_PCH_PCR_DMI_TTTBARBH 0x2728 ///< Thermal= Throttling BIOS Assigned Thermal Base High Address +#define R_PCH_PCR_DMI_LPCLGIR1 0x2730 ///< LPC Gen= eric I/O Range 1 +#define R_PCH_PCR_DMI_LPCLGIR2 0x2734 ///< LPC Gen= eric I/O Range 2 +#define R_PCH_PCR_DMI_LPCLGIR3 0x2738 ///< LPC Gen= eric I/O Range 3 +#define R_PCH_PCR_DMI_LPCLGIR4 0x273C ///< LPC Gen= eric I/O Range 4 +#define R_PCH_PCR_DMI_LPCGMR 0x2740 ///< LPC Gen= eric Memory Range +#define R_PCH_PCR_DMI_LPCBDE 0x2744 ///< LPC BIO= S Decode Enable +#define R_PCH_PCR_DMI_UCPR 0x2748 ///< uCode P= atch Region +#define B_PCH_PCR_DMI_UCPR_UPRE BIT0 ///< uCode P= atch Region Enable +#define R_PCH_PCR_DMI_GCS 0x274C ///< Generic= Control and Status +#define B_PCH_PCR_DMI_RPRDID 0xFFFF0000 ///< RPR Des= tination ID +#define B_PCH_PCR_DMI_BBS BIT10 ///< Boot BI= OS Strap +#define B_PCH_PCR_DMI_RPR BIT11 ///< Reserve= d Page Route +#define B_PCH_PCR_DMI_BILD BIT0 ///< BIOS In= terface Lock-Down +#define R_PCH_PCR_DMI_IOT1 0x2750 ///< I/O Tra= p Register 1 +#define R_PCH_PCR_DMI_IOT2 0x2758 ///< I/O Tra= p Register 2 +#define R_PCH_PCR_DMI_IOT3 0x2760 ///< I/O Tra= p Register 3 +#define R_PCH_PCR_DMI_IOT4 0x2768 ///< I/O Tra= p Register 4 +#define R_PCH_PCR_DMI_LPCIOD 0x2770 ///< LPC I/O= Decode Ranges +#define R_PCH_PCR_DMI_LPCIOE 0x2774 ///< LPC I/O= Enables +#define R_PCH_PCR_DMI_TCOBASE 0x2778 ///< TCO Bas= e Address +#define B_PCH_PCR_DMI_TCOBASE_TCOBA 0xFFE0 ///< TCO Bas= e Address Mask +#define R_PCH_PCR_DMI_GPMR1 0x277C ///< General= Purpose Memory Range 1 +#define R_PCH_PCR_DMI_GPMR1DID 0x2780 ///< General= Purpose Memory Range 1 Destination ID +#define R_PCH_PCR_DMI_GPMR2 0x2784 ///< General= Purpose Memory Range 2 +#define R_PCH_PCR_DMI_GPMR2DID 0x2788 ///< General= Purpose Memory Range 2 Destination ID +#define R_PCH_PCR_DMI_GPMR3 0x278C ///< General= Purpose Memory Range 3 +#define R_PCH_PCR_DMI_GPMR3DID 0x2790 ///< General= Purpose Memory Range 3 Destination ID +#define R_PCH_PCR_DMI_GPIOR1 0x2794 ///< General= Purpose I/O Range 1 +#define R_PCH_PCR_DMI_GPIOR1DID 0x2798 ///< General= Purpose I/O Range 1 Destination ID +#define R_PCH_PCR_DMI_GPIOR2 0x279C ///< General= Purpose I/O Range 2 +#define R_PCH_PCR_DMI_GPIOR2DID 0x27A0 ///< General= Purpose I/O Range 2 Destination ID +#define R_PCH_PCR_DMI_GPIOR3 0x27A4 ///< General= Purpose I/O Range 3 +#define R_PCH_PCR_DMI_GPIOR3DID 0x27A8 ///< General= Purpose I/O Range 3 Destination ID +#define R_PCH_PCR_DMI_PMBASEA 0x27AC ///< PM Base= Address +#define R_PCH_PCR_DMI_PMBASEC 0x27B0 ///< PM Base= Control +#define R_PCH_PCR_DMI_ACPIBA 0x27B4 ///< ACPI Ba= se Address +#define R_PCH_PCR_DMI_ACPIBDID 0x27B8 ///< ACPI Ba= se Destination ID + + +// +// Opi PHY registers +// +#define R_PCH_PCR_OPIPHY_0110 0x0110 +#define R_PCH_PCR_OPIPHY_0118 0x0118 +#define R_PCH_PCR_OPIPHY_011C 0x011C +#define R_PCH_PCR_OPIPHY_0354 0x0354 +#define R_PCH_PCR_OPIPHY_B104 0xB104 +#define R_PCH_PCR_OPIPHY_B10C 0xB10C + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsEva.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsEva.h new file mode 100644 index 0000000000..b429afa1e3 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsEva= .h @@ -0,0 +1,110 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_EVA_H_ +#define _PCH_REGS_EVA_H_ + +#define PCI_DEVICE_NUMBER_EVA 17 +#define PCI_FUNCTION_NUMBER_EVA_MROM0 0 +#define PCI_FUNCTION_NUMBER_EVA_MROM1 1 +#define PCI_FUNCTION_NUMBER_EVA_SSATA 5 + +/// +/// Lewisburg SKUs +/// +#define LBG_SKU_G 1 +#define LBG_SKU_X 2 +#define LBG_SKU_A 3 + +#define PCI_DEVICE_NUMBER_PCH_SSATA 17 +#define PCI_FUNCTION_NUMBER_PCH_SSATA 5 + +#define PCH_SSATA_MAX_CONTROLLERS 1 +#define PCH_SSATA_MAX_PORTS 6 // But only 4 ports are enable, BIOS= needs to disable Port 4 and 5 + +#define R_PCH_LBG_SSATA_DEVICE_ID 0x02 + +/// +/// LBG Production sSATA Controller DID definition +/// +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_AHCI 0xA1D2 = // LBG Production Server Secondary AHCI Mode (Ports 0-4) +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID 0xA1D4 = // LBG Production Server RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID_PREMIUM 0xA1D6 = // LBG Production Server RAID 0/1/5/10 - premium +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID1 0xA1DE = // LBG Production Server RAID 1/RRT + +/// +/// LBG Production (PRQ) MSUint SMBUS DID definition +/// +#define V_PCH_LBG_PROD_MROM_DEVICE_ID_0 0xA1F0 = // LBG MS Unit MROM 0 PRQ DID +#define V_PCH_LBG_PROD_MROM_DEVICE_ID_1 0xA1F1 = // LBG MS Unit MROM 1 PRQ DID + + +/// +/// LBG SSX (Super SKUs and Pre Production) sSATA Controller DID definiti= on +/// +#define V_PCH_LBG_SSATA_DEVICE_ID_D_AHCI 0xA252 // L= BG SSX Server Secondary AHCI Mode (Ports 0-4) +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID 0xA254 // L= BG SSX Server RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM 0xA256 // L= BG SSX Server RAID 0/1/5/10 - premium +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID1 0xA25E // L= BG SSX Server RAID 1/RRT + +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0 0x2823 /= / Server RAID 0/1/5/10 - premium - Alternate ID for RST +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1 0x2827 /= / Server RAID 0/1/5/10 - premium - Alternate ID for RSTe + +/// +/// LBG Super SKU (SSX) MSUint DID definition +/// +#define V_PCH_LBG_MROM_DEVICE_ID_0 0xA270 // = LBG NS MS Unit MROM 0 Super SKU DID +#define V_PCH_LBG_MROM_DEVICE_ID_1 0xA271 // = LBG NS MS Unit MROM 1 Super SKU DID + +#define R_PCH_LBG_MROM_DEVCLKGCTL 0xE4 + +#define R_PCH_LBG_MROM_PLKCTL 0xE8 + +#define ADR_TMR_HELD_OFF_SETUP_OPTION 2 +#define R_PCH_LBG_MROM_ADRTIMERCTRL 0x180 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_MASK (BIT27|BIT26|BIT25|BIT24) +#define N_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT 24 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_1 0x0 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_8 0x1 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_24 0x2 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_40 0x3 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_56 0x4 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_64 0x5 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_72 0x6 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_80 0x7 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_88 0x8 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_96 0x9 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_MAX (V_PCH_LBG_MROM_ADRTIMER= CTRL_ADR_MULT_96) +#define ADR_MULT_SETUP_DEFAULT_POR 99 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_DBG_DIS BIT28 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_DIS BIT29 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_MASK (BIT30|BIT31) +#define N_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR 30 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_25US 0x0 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_50US 0x1 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_100US 0x2 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_0US 0x3 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_MAX (V_PCH_LBG_MROM_ADRTIMER= CTRL_ADR_TMR_0US) +#define ADR_TMR_SETUP_DEFAULT_POR 4 + +/// +/// MS Unit Hide Control Register +/// +#define PCH_LBG_MSUINT_FUNCS 3 +#define R_PCH_LBG_MSUINT_MSDEVFUNCHIDE 0xD4 +#define B_PCH_LBG_MSUINT_MSDEVFUNCHIDE_RSVD (BIT30|BIT29|BIT28|BIT27|BI= T26|BIT25|BIT24|\ + BIT23|BIT22|BIT21|BIT20|BIT19|= BIT18|BIT17|\ + BIT16|BIT15|BIT14|BIT13|BIT12|= BIT11|BIT10|\ + BIT9|BIT8|BIT7|BIT6|BIT4|BIT3|= BIT2) + +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_SSATA (BIT5) + +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_MROM1 BIT1 +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_MROM0 BIT0 +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_REGLOCK BIT31 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsFia.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsFia.h new file mode 100644 index 0000000000..985e1e2a1d --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsFia= .h @@ -0,0 +1,81 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_FIA_H_ +#define _PCH_REGS_FIA_H_ + + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI p= rogramming as well. +// + +// +// PID:FIA +// +#define PCH_MAX_FIA_DRCRM 3 +#define R_PCH_PCR_FIA_CC 0 +#define B_PCH_PCR_FIA_CC_SRL BIT31 +#define B_PCH_PCR_FIA_CC_PTOCGE BIT17 +#define B_PCH_PCR_FIA_CC_OSCDCGE BIT16 +#define B_PCH_PCR_FIA_CC_SCPTCGE BIT15 + +#define R_PCH_PCR_FIA_PLLCTL 0x20 +#define R_PCH_PCR_FIA_DRCRM1 0x100 +#define R_PCH_PCR_FIA_DRCRM2 0x104 +#define R_PCH_PCR_FIA_DRCRM3 0x108 +#define S_PCH_PCR_FIA_DRCRM 4 +#define R_PCH_PCR_FIA_STRPFUSECFG1_REG_BASE 0x200 +#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIE_PEN BIT31 +#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL (BIT30 | BIT29 |= BIT28) +#define N_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL 28 +#define R_PCH_PCR_FIA_PCIESATA_FUSECFG_REG_BASE 0x204 +#define R_PCH_PCR_FIA_PCIESATA_STRPCFG_REG_BASE 0x208 +#define R_PCH_PCR_FIA_PCIEUSB3_STRPFUSECFG_REG_BASE 0x20C +#define R_PCH_PCR_FIA_EXP_FUSECFG_REG_BASE 0x210 +#define R_PCH_PCR_FIA_USB3SSIC_STRPFUSECFG_REG_BASE 0x214 +#define R_PCH_PCR_FIA_CSI3_STRPFUSECFG_REG_BASE 0x218 +#define R_PCH_PCR_FIA_USB3SATA_STRPFUSECFG_REG_BASE 0x21C +#define R_PCH_PCR_FIA_UFS_STRPFUSECFG_REG_BASE 0x220 +#define R_PCH_PCR_FIA_LOS1_REG_BASE 0x250 +#define R_PCH_PCR_FIA_LOS2_REG_BASE 0x254 +#define R_PCH_PCR_FIA_LOS3_REG_BASE 0x258 +#define R_PCH_PCR_FIA_LOS4_REG_BASE 0x25C +#define V_PCH_PCR_FIA_LANE_OWN_PCIEDMI 0x0 +#define V_PCH_PCR_FIA_LANE_OWN_USB3 0x1 +#define V_PCH_PCR_FIA_LANE_OWN_SATA 0x2 +#define V_PCH_PCR_FIA_LANE_OWN_GBE 0x3 +#define V_PCH_PCR_FIA_LANE_OWN_SSIC 0x5 + +#define B_PCH_PCR_FIA_L0O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_PCR_FIA_L1O (BIT7 | BIT6 | B= IT5 | BIT4) +#define B_PCH_PCR_FIA_L2O (BIT11 | BIT10 |= BIT9 | BIT8) +#define B_PCH_PCR_FIA_L3O (BIT15 | BIT14 |= BIT13 | BIT12) +#define B_PCH_PCR_FIA_L4O (BIT19 | BIT18 |= BIT17 | BIT16) +#define B_PCH_PCR_FIA_L5O (BIT23 | BIT22 |= BIT21 | BIT20) +#define B_PCH_PCR_FIA_L6O (BIT27 | BIT26 |= BIT25 | BIT24) +#define B_PCH_PCR_FIA_L7O (BIT31 | BIT30 |= BIT29 | BIT28) +#define B_PCH_PCR_FIA_L8O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_PCR_FIA_L9O (BIT7 | BIT6 | B= IT5 | BIT4) +#define B_PCH_PCR_FIA_L10O (BIT11 | BIT10 |= BIT9 | BIT8) +#define B_PCH_PCR_FIA_L11O (BIT15 | BIT14 |= BIT13 | BIT12) +#define B_PCH_PCR_FIA_L12O (BIT19 | BIT18 |= BIT17 | BIT16) +#define B_PCH_PCR_FIA_L13O (BIT23 | BIT22 |= BIT21 | BIT20) +#define B_PCH_PCR_FIA_L14O (BIT27 | BIT26 |= BIT25 | BIT24) +#define B_PCH_PCR_FIA_L15O (BIT31 | BIT30 |= BIT29 | BIT28) +#define B_PCH_PCR_FIA_L16O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_PCR_FIA_L17O (BIT7 | BIT6 | B= IT5 | BIT4) +#define B_PCH_PCR_FIA_L18O (BIT11 | BIT10 |= BIT9 | BIT8) +#define B_PCH_PCR_FIA_L19O (BIT15 | BIT14 |= BIT13 | BIT12) +#define B_PCH_PCR_FIA_L20O (BIT19 | BIT18 |= BIT17 | BIT16) +#define B_PCH_PCR_FIA_L21O (BIT23 | BIT22 |= BIT21 | BIT20) +#define B_PCH_PCR_FIA_L22O (BIT27 | BIT26 |= BIT25 | BIT24) +#define B_PCH_PCR_FIA_L23O (BIT31 | BIT30 |= BIT29 | BIT28) +#define B_PCH_PCR_FIA_L24O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_PCR_FIA_L25O (BIT7 | BIT6 | B= IT5 | BIT4) + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsGpio.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsGpio.h new file mode 100644 index 0000000000..3e5afb182c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsGpi= o.h @@ -0,0 +1,511 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_GPIO_H_ +#define _PCH_REGS_GPIO_H_ + +#define V_PCH_GPIO_GPP_A_PAD_MAX 24 +#define V_PCH_GPIO_GPP_B_PAD_MAX 24 +#define V_PCH_GPIO_GPP_C_PAD_MAX 24 +#define V_PCH_GPIO_GPP_D_PAD_MAX 24 +#define V_PCH_LP_GPIO_GPP_E_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_E_PAD_MAX 13 +#define V_PCH_GPIO_GPP_F_PAD_MAX 24 +#define V_PCH_LP_GPIO_GPP_G_PAD_MAX 8 +#define V_PCH_H_GPIO_GPP_G_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_H_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_J_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_K_PAD_MAX 11 +#define V_PCH_H_GPIO_GPP_L_PAD_MAX 20 +#define V_PCH_H_GPIO_GPP_I_PAD_MAX 11 + +#define V_PCH_GPIO_GPD_PAD_MAX 12 + +#define V_PCH_GPIO_GROUP_MAX 13 +#define V_PCH_H_GPIO_GROUP_MAX V_PCH_GPIO_GROUP_MAX +#define V_PCH_LP_GPIO_GROUP_MAX 8 +#define V_PCH_GPIO_NUM_SUPPORTED_GPIS 261 +#define S_PCH_GPIO_GP_SMI_EN 4 +#define S_PCH_GPIO_GP_SMI_STS 4 + +/// +/// Groups mapped to 2-tier General Purpose Event will all be under +/// one master GPE_111 (0x6F) +/// +#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F + + +// +// GPIO Common Private Configuration Registers +// +#define R_PCH_PCR_GPIO_REV_ID 0x00 +#define R_PCH_PCR_GPIO_CAP_LIST 0x04 +#define R_PCH_PCR_GPIO_FAMBAR 0x08 +#define R_PCH_PCR_GPIO_PADBAR 0x0C +#define B_PCH_PCR_GPIO_PADBAR 0x0000FFFF +#define R_PCH_PCR_GPIO_MISCCFG 0x10 +#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW2 16 +#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12) +#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW1 12 +#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW0 8 +#define B_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE BIT3 +#define N_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE 3 +#define B_PCH_PCR_GPIO_MISCCFG_GPDPCGEN BIT1 +#define B_PCH_PCR_GPIO_MISCCFG_GPDLCGEN BIT0 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_MISCSECCFG 0x14 + +// +// GPIO Community 0 Private Configuration Registers +// +// SKL PCH-LP +#define R_PCH_LP_PCR_GPIO_GPP_A_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_B_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_A_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_B_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCKTX 0xAC +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN 0x38 +#define R_PCH_H_PCR_GPIO_GPP_A_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_B_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_VWM_EN 0x58 +#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCK 0x70 +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX 0x74 +#define R_PCH_H_PCR_GPIO_GPP_F_HOSTSW_OWN 0x88 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IS 0x0108 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IE 0x0118 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0128 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0138 +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x580 + +// Common +#define R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN 0x80 +#define R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN 0x84 +#define R_PCH_PCR_GPIO_GPP_A_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPP_B_GPI_IS 0x0104 +#define R_PCH_PCR_GPIO_GPP_A_GPI_IE 0x0110 +#define R_PCH_PCR_GPIO_GPP_B_GPI_IE 0x0114 +#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS 0x0120 +#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS 0x0124 +#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_EN 0x0130 +#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_EN 0x0134 +#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0144 +#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x0154 +#define R_PCH_PCR_GPIO_GPP_B_NMI_STS 0x0164 +#define R_PCH_PCR_GPIO_GPP_B_NMI_EN 0x0174 +#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0 + +// +// GPIO Community 1 Private Configuration Registers +// +//SKL PCH-LP: +#define R_PCH_LP_PCR_GPIO_GPP_C_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_D_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_E_PAD_OWN 0x40 +#define R_PCH_LP_PCR_GPIO_GPP_C_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_D_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_E_GPI_VWM_EN 0x88 +#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCKTX 0xAC +#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCK 0xB0 +#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCKTX 0xB4 +//SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN 0x38 +// Server SKX PCH +#define R_PCH_H_PCR_GPIO_GPP_C_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_D_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_E_GPI_VWM_EN 0x58 +#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCK 0x70 +#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX 0x74 +// Common +#define R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN 0x80 +#define R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN 0x84 +#define R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN 0x88 +#define R_PCH_PCR_GPIO_GPP_C_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPP_D_GPI_IS 0x0104 +#define R_PCH_PCR_GPIO_GPP_E_GPI_IS 0x0108 +#define R_PCH_PCR_GPIO_GPP_C_GPI_IE 0x0110 +#define R_PCH_PCR_GPIO_GPP_D_GPI_IE 0x0114 +#define R_PCH_PCR_GPIO_GPP_E_GPI_IE 0x0114 +#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS 0x0120 +#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS 0x0124 +#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS 0x0128 +#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_EN 0x0130 +#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_EN 0x0134 +#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_EN 0x0138 +#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0140 +#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0144 +#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0148 +#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x0150 +#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x0154 +#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x0158 +#define R_PCH_PCR_GPIO_GPP_C_NMI_STS 0x0160 +#define R_PCH_PCR_GPIO_GPP_D_NMI_STS 0x0164 +#define R_PCH_PCR_GPIO_GPP_E_NMI_STS 0x0168 +#define R_PCH_PCR_GPIO_GPP_C_NMI_EN 0x0170 +#define R_PCH_PCR_GPIO_GPP_D_NMI_EN 0x0174 +#define R_PCH_PCR_GPIO_GPP_E_NMI_EN 0x0178 + + +// Common: +#define R_PCH_PCR_GPIO_CAP_LIST_1_PWM 0x0200 +#define R_PCH_PCR_GPIO_PWMC 0x0204 +#define R_PCH_PCR_GPIO_CAP_LIST_2_SER_BLINK 0x0208 +#define R_PCH_PCR_GPIO_GP_SER_BLINK 0x020C +#define B_PCH_PCR_GPIO_GP_SER_BLINK 0x1F +#define R_PCH_PCR_GPIO_GP_SER_CMDSTS 0x0210 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_DLS (BIT23 | BIT22) +#define N_PCH_PCR_GPIO_GP_SER_CMDSTS_DLS 22 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_DRS 0x003F0000 +#define N_PCH_PCR_GPIO_GP_SER_CMDSTS_DRS 16 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_BUSY BIT8 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_GO BIT0 +#define R_PCH_PCR_GPIO_GP_SER_DATA 0x0210 +// Common: +#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0 +#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580 + +// +// GPIO Community 2 Private Configuration Registers +// +// SKL PCH-LP +#define R_PCH_LP_PCR_GPIO_GPD_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPD_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCKTX 0xA4 +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPD_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPD_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX 0x64 +// Common +#define R_PCH_PCR_GPIO_GPD_HOSTSW_OWN 0x80 +#define R_PCH_PCR_GPIO_GPD_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPD_GPI_IE 0x0110 +#define R_PCH_PCR_GPIO_GPD_GPI_GPE_STS 0x0120 +#define R_PCH_PCR_GPIO_GPD_GPI_GPE_EN 0x0130 +#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400 + +// +// GPIO Community 3 Private Configuration Registers +// +// SKL PCH-LP: +#define R_PCH_LP_PCR_GPIO_GPP_F_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_G_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCKTX 0xAC +#define R_PCH_LP_PCR_GPIO_GPP_F_HOSTSW_OWN 0xD0 +#define R_PCH_LP_PCR_GPIO_GPP_G_HOSTSW_OWN 0xD4 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IS 0x0100 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IS 0x0104 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IE 0x0120 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IE 0x0124 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0140 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0144 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0160 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0164 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0 + +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_I_HOSTSW_OWN 0x80 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IS 0x0100 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IE 0x0110 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS 0x0120 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_EN 0x0130 +#define R_PCH_H_PCR_GPIO_GPP_I_SMI_STS 0x0140 +#define R_PCH_H_PCR_GPIO_GPP_I_SMI_EN 0x0150 +#define R_PCH_H_PCR_GPIO_GPP_I_NMI_STS 0x0160 +#define R_PCH_H_PCR_GPIO_GPP_I_NMI_EN 0x0170 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFG_OFFSET 0x400 + +// +// GPIO Community 4 Private Configuration Registers +// + +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_J_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_K_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_J_HOSTSW_OWN 0x80 +#define R_PCH_H_PCR_GPIO_GPP_K_HOSTSW_OWN 0x84 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IS 0x0100 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IS 0x0104 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IE 0x0110 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IE 0x0114 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_STS 0x0120 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS 0x0124 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_EN 0x0130 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_EN 0x0134 +#define R_PCH_H_PCR_GPIO_GPP_J_PADCFG_OFFSET 0x400 +#define R_PCH_H_PCR_GPIO_GPP_K_PADCFG_OFFSET 0x4C0 + +// +// GPIO Community 5 Private Configuration Registers +// + +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_L_PAD_OWN 0x38 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_VWM_EN 0x58 +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCK 0x70 +#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCKTX 0x74 +#define R_PCH_H_PCR_GPIO_GPP_G_HOSTSW_OWN 0x80 +#define R_PCH_H_PCR_GPIO_GPP_H_HOSTSW_OWN 0x84 +#define R_PCH_H_PCR_GPIO_GPP_L_HOSTSW_OWN 0x88 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IS 0x0100 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IS 0x0104 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IS 0x0108 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IE 0x0110 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IE 0x0114 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IE 0x0118 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0120 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS 0x0124 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_STS 0x0128 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0130 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_EN 0x0134 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_EN 0x0138 +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x400 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFG_OFFSET 0x4C0 +#define R_PCH_H_PCR_GPIO_GPP_L_PADCFG_OFFSET 0x580 + + + + +// +// Define Pad Number +// +#define V_GPIO_PAD0 0 +#define V_GPIO_PAD1 1 +#define V_GPIO_PAD2 2 +#define V_GPIO_PAD3 3 +#define V_GPIO_PAD4 4 +#define V_GPIO_PAD5 5 +#define V_GPIO_PAD6 6 +#define V_GPIO_PAD7 7 +#define V_GPIO_PAD8 8 +#define V_GPIO_PAD9 9 +#define V_GPIO_PAD10 10 +#define V_GPIO_PAD11 11 +#define V_GPIO_PAD12 12 +#define V_GPIO_PAD13 13 +#define V_GPIO_PAD14 14 +#define V_GPIO_PAD15 15 +#define V_GPIO_PAD16 16 +#define V_GPIO_PAD17 17 +#define V_GPIO_PAD18 18 +#define V_GPIO_PAD19 19 +#define V_GPIO_PAD20 20 +#define V_GPIO_PAD21 21 +#define V_GPIO_PAD22 22 +#define V_GPIO_PAD23 23 + +// +// Host Software Pad Ownership modes +// +#define V_PCH_PCR_GPIO_HOSTSW_OWN_ACPI 0x00 +#define V_PCH_PCR_GPIO_HOSTSW_OWN_GPIO 0x01 + +// +// Pad Ownership modes +// +#define V_PCH_PCR_GPIO_PAD_OWN_HOST 0x00 +#define V_PCH_PCR_GPIO_PAD_OWN_CSME 0x01 +#define V_PCH_PCR_GPIO_PAD_OWN_ISH 0x02 + +// +// Pad Configuration Register DW0 +// + +//Pad Reset Config +#define B_PCH_GPIO_RST_CONF (BIT31 | BIT30) +#define N_PCH_GPIO_RST_CONF 30 +#define V_PCH_GPIO_RST_CONF_POW_GOOD 0x00 +#define V_PCH_GPIO_RST_CONF_DEEP_RST 0x01 +#define V_PCH_GPIO_RST_CONF_GPIO_RST 0x02 +#define V_PCH_GPIO_RST_CONF_RESUME_RST 0x03 // Only for GPD Group + +//RX Pad State Select +#define B_PCH_GPIO_RX_PAD_STATE BIT29 +#define N_PCH_GPIO_RX_PAD_STATE 29 +#define V_PCH_GPIO_RX_PAD_STATE_RAW 0x00 +#define V_PCH_GPIO_RX_PAD_STATE_INT 0x01 + +//RX Raw Overrride to 1 +#define B_PCH_GPIO_RX_RAW1 BIT28 +#define N_PCH_GPIO_RX_RAW1 28 +#define V_PCH_GPIO_RX_RAW1_DIS 0x00 +#define V_PCH_GPIO_RX_RAW1_EN 0x01 + +//RX Level/Edge Configuration +#define B_PCH_GPIO_RX_LVL_EDG (BIT26 | BIT25) +#define N_PCH_GPIO_RX_LVL_EDG 25 +#define V_PCH_GPIO_RX_LVL_EDG_LVL 0x00 +#define V_PCH_GPIO_RX_LVL_EDG_EDG 0x01 +#define V_PCH_GPIO_RX_LVL_EDG_0 0x02 +#define V_PCH_GPIO_RX_LVL_EDG_RIS_FAL 0x03 + +//RX Invert +#define B_PCH_GPIO_RXINV BIT23 +#define N_PCH_GPIO_RXINV 23 +#define V_PCH_GPIO_RXINV_NO 0x00 +#define V_PCH_GPIO_RXINV_YES 0x01 + +//GPIO Input Route IOxAPIC +#define B_PCH_GPIO_RX_APIC_ROUTE BIT20 +#define N_PCH_GPIO_RX_APIC_ROUTE 20 +#define V_PCH_GPIO_RX_APIC_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01 + +//GPIO Input Route SCI +#define B_PCH_GPIO_RX_SCI_ROUTE BIT19 +#define N_PCH_GPIO_RX_SCI_ROUTE 19 +#define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01 + +//GPIO Input Route SMI +#define B_PCH_GPIO_RX_SMI_ROUTE BIT18 +#define N_PCH_GPIO_RX_SMI_ROUTE 18 +#define V_PCH_GPIO_RX_SMI_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_SMI_ROUTE_EN 0x01 + +//GPIO Input Route NMI +#define B_PCH_GPIO_RX_NMI_ROUTE BIT17 +#define N_PCH_GPIO_RX_NMI_ROUTE 17 +#define V_PCH_GPIO_RX_NMI_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_NMI_ROUTE_EN 0x01 + +//GPIO Pad Mode +#define B_PCH_GPIO_PAD_MODE (BIT12 | BIT11 | BIT10) +#define N_PCH_GPIO_PAD_MODE 10 +#define V_PCH_GPIO_PAD_MODE_GPIO 0 +#define V_PCH_GPIO_PAD_MODE_NAT_1 1 +#define V_PCH_GPIO_PAD_MODE_NAT_2 2 +#define V_PCH_GPIO_PAD_MODE_NAT_3 3 +#define V_PCH_GPIO_PAD_MODE_NAT_4 4 // SPT-H only + +//GPIO RX Disable +#define B_PCH_GPIO_RXDIS BIT9 +#define N_PCH_GPIO_RXDIS 9 +#define V_PCH_GPIO_RXDIS_EN 0x00 +#define V_PCH_GPIO_RXDIS_DIS 0x01 + +//GPIO TX Disable +#define B_PCH_GPIO_TXDIS BIT8 +#define N_PCH_GPIO_TXDIS 8 +#define V_PCH_GPIO_TXDIS_EN 0x00 +#define V_PCH_GPIO_TXDIS_DIS 0x01 + +//GPIO RX State +#define B_PCH_GPIO_RX_STATE BIT1 +#define N_PCH_GPIO_RX_STATE 1 +#define V_PCH_GPIO_RX_STATE_LOW 0x00 +#define V_PCH_GPIO_RX_STATE_HIGH 0x01 + +//GPIO TX State +#define B_PCH_GPIO_TX_STATE BIT0 +#define N_PCH_GPIO_TX_STATE 0 +#define V_PCH_GPIO_TX_STATE_LOW 0x00 +#define V_PCH_GPIO_TX_STATE_HIGH 0x01 + +// +// Pad Configuration Register DW1 +// + +//Padtol +#define B_PCH_GPIO_PADTOL BIT25 +#define N_PCH_GPIO_PADTOL 25 +#define V_PCH_GPIO_PADTOL_NONE 0x00 +#define V_PCH_GPIO_PADTOL_CLEAR 0x00 +#define V_PCH_GPIO_PADTOL_SET 0x01 + +//Termination +#define B_PCH_GPIO_TERM (BIT13 | BIT12 | BIT11 | BIT10) +#define N_PCH_GPIO_TERM 10 +#define V_PCH_GPIO_TERM_WPD_NONE 0x00 +#define V_PCH_GPIO_TERM_WPD_5K 0x02 +#define V_PCH_GPIO_TERM_WPD_20K 0x04 +#define V_PCH_GPIO_TERM_WPU_NONE 0x08 +#define V_PCH_GPIO_TERM_WPU_1K 0x09 +#define V_PCH_GPIO_TERM_WPU_2K 0x0B +#define V_PCH_GPIO_TERM_WPU_5K 0x0A +#define V_PCH_GPIO_TERM_WPU_20K 0x0C +#define V_PCH_GPIO_TERM_WPU_1K_2K 0x0D +#define V_PCH_GPIO_TERM_NATIVE 0x0F + +//Interrupt number +#define B_PCH_GPIO_INTSEL 0x7F +#define N_PCH_GPIO_INTSEL 0 + +// +// Ownership +// +#define V_PCH_GPIO_OWN_GPIO 0x01 +#define V_PCH_GPIO_OWN_ACPI 0x00 + +// +// GPE +// +#define V_PCH_GPIO_GPE_EN 0x01 +#define V_PCH_GPIO_GPE_DIS 0x00 +// +// SMI +// +#define V_PCH_GPIO_SMI_EN 0x01 +#define V_PCH_GPIO_SMI_DIS 0x00 +// +// NMI +// +#define V_PCH_GPIO_NMI_EN 0x01 +#define V_PCH_GPIO_NMI_DIS 0x00 +// +// Reserved: RSVD1 +// +#define V_PCH_GPIO_RSVD1 0x00 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsHda.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsHda.h new file mode 100644 index 0000000000..a6049cb5aa --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsHda= .h @@ -0,0 +1,226 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_HDA_H_ +#define _PCH_REGS_HDA_H_ + +// +// HD-A Controller Registers (D31:F3) +// +// PCI Configuration Space Registers +// +#define PCI_DEVICE_NUMBER_PCH_HDA 31 +#define PCI_FUNCTION_NUMBER_PCH_HDA 3 + +#define V_PCH_HDA_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_LP_HDA_DEVICE_ID_0 0x9D70 +#define V_PCH_LP_HDA_DEVICE_ID_1 0x9D71 +#define V_PCH_LP_HDA_DEVICE_ID_2 0x9D72 +#define V_PCH_LP_HDA_DEVICE_ID_3 0x9D73 +#define V_PCH_LP_HDA_DEVICE_ID_4 0x9D74 +#define V_PCH_LP_HDA_DEVICE_ID_5 0x9D75 +#define V_PCH_LP_HDA_DEVICE_ID_6 0x9D76 +#define V_PCH_LP_HDA_DEVICE_ID_7 0x9D77 +#define V_PCH_H_HDA_DEVICE_ID_0 0xA170 +#define V_PCH_H_HDA_DEVICE_ID_1 0xA171 +#define V_PCH_H_HDA_DEVICE_ID_2 0xA172 +#define V_PCH_H_HDA_DEVICE_ID_3 0xA173 +#define V_PCH_H_HDA_DEVICE_ID_4 0xA174 +#define V_PCH_H_HDA_DEVICE_ID_5 0xA175 +#define V_PCH_H_HDA_DEVICE_ID_6 0xA176 +#define V_PCH_H_HDA_DEVICE_ID_7 0xA177 +// +// LBG SSX (Super SKU) DIDs +// +#define V_PCH_LBG_HDA_DEVICE_ID_0 0xA270 +#define V_PCH_LBG_HDA_DEVICE_ID_1 0xA271 +#define V_PCH_LBG_HDA_DEVICE_ID_2 0xA272 +#define V_PCH_LBG_HDA_DEVICE_ID_3 0xA273 +#define V_PCH_LBG_HDA_DEVICE_ID_4 0xA274 +#define V_PCH_LBG_HDA_DEVICE_ID_5 0xA275 +#define V_PCH_LBG_HDA_DEVICE_ID_6 0xA276 +#define V_PCH_LBG_HDA_DEVICE_ID_7 0xA277 +// +// LBG PRODUCTION (PRQ) DIDs +// +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_0 0xA1F0 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_1 0xA1F1 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_2 0xA1F2 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_3 0xA1F3 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_4 0xA1F4 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_5 0xA1F5 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_6 0xA1F6 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_7 0xA1F7 + + +#define R_PCH_HDA_PI 0x09 +#define V_PCH_HDA_PI_ADSP_UAA 0x80 +#define R_PCH_HDA_SCC 0x0A +#define V_PCH_HDA_SCC_ADSP 0x01 +#define R_PCH_HDA_HDALBA 0x10 +#define B_PCH_HDA_HDALBA_LBA 0xFFFFC000 +#define V_PCH_HDA_HDBAR_SIZE (1 << 14) +#define R_PCH_HDA_HDAUBA 0x14 +#define B_PCH_HDA_HDAUBA_UBA 0xFFFFFFFF +#define R_PCH_HDA_CGCTL 0x48 +#define B_PCH_HDA_CGCTL_MEMDCGE BIT0 +#define B_PCH_HDA_CGCTL_HDALDCGE BIT3 +#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6 +#define B_PCH_HDA_CGCTL_ODMABDCGE BIT4 +#define B_PCH_HDA_CGCTL_IDMABDCGE BIT5 +#define B_PCH_HDA_CGCTL_IOSFBDCGE BIT7 +#define B_PCH_HDA_CGCTL_IOSFSDCGE BIT8 +#define B_PCH_HDA_CGCTL_APTCGE BIT16 +#define B_PCH_HDA_CGCTL_XOTCGE BIT17 +#define B_PCH_HDA_CGCTL_SROTCGE BIT18 +#define B_PCH_HDA_CGCTL_IOSFBTCGE BIT19 +#define B_PCH_HDA_CGCTL_IOSFSTCGE BIT20 +#define B_PCH_HDA_CGCTL_FROTCGE BIT21 +#define B_PCH_HDA_CGCTL_APLLSE BIT31 +#define R_PCH_HDA_CGCTL 0x48 +#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6 +#define R_PCH_HDA_PC 0x52 +#define V_PCH_HDA_PC_PMES 0x18 +#define N_PCH_HDA_PC_PMES 11 +#define R_PCH_HDA_PCS 0x54 +#define B_PCH_HDA_PCS_PMES BIT15 +#define B_PCH_HDA_PCS_PMEE BIT8 +#define B_PCH_HDA_PCS_PS (BIT1 | BIT0) +#define R_PCH_HDA_MMC 0x62 +#define B_PCH_HDA_MMC_ME BIT0 +#define R_PCH_HDA_DEVC 0x78 +#define B_PCH_HDA_DEVC_NSNPEN BIT11 +#define R_PCH_HDA_SEM1 0xC0 +#define B_PCH_HDA_SEM1_LFLCS BIT24 +#define B_PCH_HDA_SEM1_BLKC3DIS BIT17 +#define B_PCH_HDA_SEM1_TMODE BIT12 +#define B_PCH_HDA_SEM1_FIFORDYSEL (BIT10 | BIT9) +#define R_PCH_HDA_SEM2 0xC4 +#define B_PCH_HDA_SEM2_BSMT (BIT27 | BIT26) +#define V_PCH_HDA_SEM2_BSMT 0x1 +#define N_PCH_HDA_SEM2_BSMT 26 +#define B_PCH_HDA_SEM2_VC0PSNR BIT24 +#define R_PCH_HDA_SEM3L 0xC8 +#define B_PCH_HDA_SEM3L_ISL1EXT2 (BIT21 | BIT20) +#define V_PCH_HDA_SEM3L_ISL1EXT2 0x2 +#define N_PCH_HDA_SEM3L_ISL1EXT2 20 +#define R_PCH_HDA_SEM4L 0xD0 +#define B_PCH_HDA_SEM4L_OSL1EXT2 (BIT21 | BIT20) +#define V_PCH_HDA_SEM4L_OSL1EXT2 0x3 +#define N_PCH_HDA_SEM4L_OSL1EXT2 20 + +// +// Memory Space Registers +// +// +// Resides in 'HD Audio Global Registers' (0000h) +// +#define R_PCH_HDABA_GCAP 0x00 +#define R_PCH_HDABA_GCTL 0x08 +#define B_PCH_HDABA_GCTL_CRST BIT0 + +#define R_PCH_HDABA_OUTPAY 0x04 +#define R_PCH_HDABA_INPAY 0x06 +#define V_PCH_HDABA_INPAY_DEFAULT 0x1C + +#define R_PCH_HDABA_WAKEEN 0x0C +#define B_PCH_HDABA_WAKEEN_SDI_3 BIT3 +#define B_PCH_HDABA_WAKEEN_SDI_2 BIT2 +#define B_PCH_HDABA_WAKEEN_SDI_1 BIT1 +#define B_PCH_HDABA_WAKEEN_SDI_0 BIT0 + +#define R_PCH_HDABA_WAKESTS 0x0E +#define B_PCH_HDABA_WAKESTS_SDIN3 BIT3 +#define B_PCH_HDABA_WAKESTS_SDIN2 BIT2 +#define B_PCH_HDABA_WAKESTS_SDIN1 BIT1 +#define B_PCH_HDABA_WAKESTS_SDIN0 BIT0 + +// +// Resides in 'HD Audio Controller Registers' (0030h) +// +#define R_PCH_HDABA_IC 0x60 +#define R_PCH_HDABA_IR 0x64 +#define R_PCH_HDABA_ICS 0x68 +#define B_PCH_HDABA_ICS_IRV BIT1 +#define B_PCH_HDABA_ICS_ICB BIT0 + +// +// Resides in 'HD Audio Processing Pipe Capability Structure' (0800h) +// +#define R_PCH_HDABA_PPC 0x0800 // Processing Pipe = Capability Structure (Memory Space, offset 0800h) +#define R_PCH_HDABA_PPCTL (R_PCH_HDABA_PPC + 0x04) +#define B_PCH_HDABA_PPCTL_GPROCEN BIT30 + +// +// Resides in 'HD Audio Multiple Links Capability Structure' (0C00h) +// +#define V_PCH_HDA_HDALINK_INDEX 0 +#define V_PCH_HDA_IDISPLINK_INDEX 1 + +#define R_PCH_HDABA_MLC 0x0C00 // Multiple Links C= apability Structure (Memory Space, offset 0C00h) +#define R_PCH_HDABA_LCTLX(x) (R_PCH_HDABA_MLC + (0x40 += (0x40 * (x)) + 0x04)) // x - Link index: 0 - HDA Link, 1 - iDisp Link +#define B_PCH_HDABA_LCTLX_CPA BIT23 +#define B_PCH_HDABA_LCTLX_SPA BIT16 +#define N_PCH_HDABA_LCTLX_SCF 0 +#define V_PCH_HDABA_LCTLX_SCF_6MHZ 0x0 +#define V_PCH_HDABA_LCTLX_SCF_12MHZ 0x1 +#define V_PCH_HDABA_LCTLX_SCF_24MHZ 0x2 +#define V_PCH_HDABA_LCTLX_SCF_48MHZ 0x3 +#define V_PCH_HDABA_LCTLX_SCF_96MHZ 0x4 + +// +// Resides in 'HD Audio Vendor Specific Registers' (1000h) +// +#define R_PCH_HDABA_LTRC 0x1048 +#define V_PCH_HDABA_LTRC_GB 0x29 +#define N_PCH_HDABA_LTRC_GB 0 +#define R_PCH_HDABA_PCE 0x104B +#define B_PCH_HDABA_PCE_D3HE BIT2 + +// +// Private Configuration Space Registers +// +// +// Resides in IOSF & Fabric Configuration Registers (000h) +// +#define R_PCH_PCR_HDA_TTCCFG 0xE4 +#define B_PCH_PCR_HDA_TTCCFG_HCDT BIT1 + +// +// Resides in PCI & Codec Configuration Registers (500h) +// +#define R_PCH_PCR_HDA_PCICDCCFG 0x500 // PCI & Codec Confi= guration Registers (PCR, offset 500h) +#define B_PCH_PCR_HDA_PCICDCCFG_ACPIIN 0x0000FF00 +#define N_PCH_PCR_HDA_PCICDCCFG_ACPIIN 8 +#define R_PCH_PCR_HDA_FNCFG (R_PCH_PCR_HDA_PCICDCCFG += 0x30) +#define B_PCH_PCR_HDA_FNCFG_PGD BIT5 +#define B_PCH_PCR_HDA_FNCFG_BCLD BIT4 +#define B_PCH_PCR_HDA_FNCFG_CGD BIT3 +#define B_PCH_PCR_HDA_FNCFG_ADSPD BIT2 +#define B_PCH_PCR_HDA_FNCFG_HDASD BIT0 +#define R_PCH_PCR_HDA_CDCCFG (R_PCH_PCR_HDA_PCICDCCFG += 0x34) +#define B_PCH_PCR_HDA_CDCCFG_DIS_SDIN2 BIT2 + +// +// Resides in Power Management & EBB Configuration Registers (600h) +// +#define R_PCH_PCR_HDA_PWRMANCFG 0x600 // Power Management = & EBB Configuration Registers (PCR, offset 600h) +#define R_PCH_PCR_HDA_APLLP0 (R_PCH_PCR_HDA_PWRMANCFG += 0x10) +#define V_PCH_PCR_HDA_APLLP0 0xFC1E0000 +#define R_PCH_PCR_HDA_APLLP1 (R_PCH_PCR_HDA_PWRMANCFG += 0x14) +#define V_PCH_PCR_HDA_APLLP1 0x00003F00 +#define R_PCH_PCR_HDA_APLLP2 (R_PCH_PCR_HDA_PWRMANCFG += 0x18) +#define V_PCH_PCR_HDA_APLLP2 0x0000011D +#define R_PCH_PCR_HDA_IOBCTL (R_PCH_PCR_HDA_PWRMANCFG += 0x1C) +#define B_PCH_PCR_HDA_IOBCTL_OSEL (BIT9 | BIT8) +#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK 0 +#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK_I2S 1 +#define V_PCH_PCR_HDA_IOBCTL_OSEL_I2S 3 +#define N_PCH_PCR_HDA_IOBCTL_OSEL 8 +#define B_PCH_PCR_HDA_IOBCTL_VSEL BIT1 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsHsio.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsHsio.h new file mode 100644 index 0000000000..8eb62a64a1 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsHsi= o.h @@ -0,0 +1,171 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_HSIO_H_ +#define _PCH_REGS_HSIO_H_ + +#define B_PCH_HSIO_ACCESS_TYPE (BIT15 | BIT14) +#define N_PCH_HSIO_ACCESS_TYPE 14 +#define V_PCH_HSIO_ACCESS_TYPE_BDCAST (BIT15 | BIT14) +#define V_PCH_HSIO_ACCESS_TYPE_MULCAST BIT15 +#define B_PCH_HSIO_LANE_GROUP_NO (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9) +#define B_PCH_HSIO_FUNCTION_NO (BIT8 | BIT7) +#define N_PCH_HSIO_FUNCTION_NO 7 +#define B_PCH_HSIO_REG_OFFSET (BIT6 | BIT5 | B= IT4 | BIT3 | BIT2 | BIT1 | BIT0) + +#define V_PCH_HSIO_ACCESS_TYPE_BCAST 0x03 +#define V_PCH_HSIO_ACCESS_TYPE_MCAST 0x02 +#define V_PCH_HSIO_ACCESS_TYPE_UCAST 0x00 + +#define V_PCH_HSIO_LANE_GROUP_NO_CMN_LANE 0x00 + +#define V_PCH_HSIO_FUNCTION_NO_PCS 0x00 +#define V_PCH_HSIO_FUNCTION_NO_TX 0x01 +#define V_PCH_HSIO_FUNCTION_NO_RX 0x02 + +#define V_PCH_HSIO_FUNCTION_NO_CMNDIG 0x00 +#define V_PCH_HSIO_FUNCTION_NO_CMNANA 0x01 +#define V_PCH_HSIO_FUNCTION_NO_PLL 0x02 + +#define R_PCH_HSIO_PCS_DWORD4 0x10 + +#define R_PCH_HSIO_PCS_DWORD8 0x20 +#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_PTR_INIT_4_0 0x1F000000 +#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 0x001F0000 +#define N_PCH_HSIO_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 16 +#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 0x00001F00 +#define N_PCH_HSIO_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 8 + +#define R_PCH_HSIO_PCS_DWORD9 0x24 +#define B_PCH_HSIO_PCS_DWORD9_REG_ENABLE_PWR_GATING BIT29 + +#define R_PCH_HSIO_RX_DWORD8 0x120 +#define B_PCH_HSIO_RX_DWORD8_ICFGDFETAP3_EN BIT10 + +#define R_PCH_HSIO_RX_DWORD9 0x124 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP4_OVERRIDE_EN BIT24 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP3_OVERRIDE_EN BIT26 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP2_OVERRIDE_EN BIT28 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP1_OVERRIDE_EN BIT30 + +#define R_PCH_HSIO_RX_DWORD12 0x130 +#define B_PCH_HSIO_RX_DWORD12_O_CFGEWMARGINSEL BIT14 + +#define R_PCH_HSIO_RX_DWORD20 0x150 +#define B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 (BIT29 | BIT28= | BIT27 | BIT26 | BIT25 | BIT24) +#define N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 24 + +#define R_PCH_HSIO_RX_DWORD21 0x154 +#define B_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12= | BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 8 +#define B_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 (BIT5 | BIT4 |= BIT3 | BIT2 | BIT1 | BIT0) +#define N_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 0 + +#define R_PCH_HSIO_RX_DWORD23 0x15C +#define B_PCH_HSIO_RX_DWORD23_ICFGVGABLWTAP_OVERRIDE_EN BIT2 +#define B_PCH_HSIO_RX_DWORD23_CFGVGATAP_ADAPT_OVERRIDE_EN BIT4 + +#define R_PCH_HSIO_RX_DWORD25 0x164 +#define B_PCH_HSIO_RX_DWORD25_RX_TAP_CFG_CTRL BIT3 +#define B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 0x1F0000 +#define N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 16 + +#define R_PCH_HSIO_RX_DWORD26 0x168 +#define B_PCH_HSIO_RX_DWORD26_SATA_EQ_DIS BIT16 + +#define R_PCH_HSIO_RX_DWORD34 0x188 +#define B_PCH_HSIO_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 | BIT13 | B= IT12) +#define N_PCH_HSIO_RX_DWORD34_MM_PH_OFC_SCALE_2_0 12 + +#define R_PCH_HSIO_RX_DWORD44 0x1B0 +#define B_PCH_HSIO_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 0xFF0000 +#define N_PCH_HSIO_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 16 + +#define R_PCH_HSIO_RX_DWORD56 0x1E0 +#define B_PCH_HSIO_RX_DWORD56_ICFGPIDACCFGVALID BIT16 + +#define R_PCH_HSIO_RX_DWORD57 0x1E4 +#define B_PCH_HSIO_RX_DWORD57_JIM_COURSE BIT30 +#define B_PCH_HSIO_RX_DWORD57_JIM_ENABLE BIT29 +#define B_PCH_HSIO_RX_DWORD57_JIMMODE BIT28 +#define B_PCH_HSIO_RX_DWORD57_JIMNUMCYCLES_3_0 0x0F000000 +#define N_PCH_HSIO_RX_DWORD57_JIMNUMCYCLES_3_0 24 +#define B_PCH_HSIO_RX_DWORD57_ICFGMARGINEN BIT0 + +#define R_PCH_HSIO_RX_DWORD59 0x1EC +#define R_PCH_HSIO_RX_DWORD60 0x1F0 + +#define R_PCH_HSIO_TX_DWORD5 0x94 +#define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21 | BIT20 | B= IT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 16 +#define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 8 + +#define R_PCH_HSIO_TX_DWORD6 0x98 +#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21 | BIT20 | B= IT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 16 +#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 8 +#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN1DEEMPH6P0_5_0 (BIT5 | BIT4 | BIT= 3 | BIT2 | BIT1 | BIT0) + +#define R_PCH_HSIO_TX_DWORD8 0xA0 +#define B_PCH_HSIO_TX_DWORD8_ORATE10MARGIN_5_0 (BIT29 | BIT28 | B= IT27 | BIT26 | BIT25 | BIT24) +#define N_PCH_HSIO_TX_DWORD8_ORATE10MARGIN_5_0 24 +#define B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 | BIT20 | B= IT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0 16 +#define B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0 8 + +#define R_PCH_HSIO_TX_DWORD19 0xCC + +#define R_PCH_LP_HSIO_LANE10_PCS_DWORD8 0x020 +#define R_PCH_LP_HSIO_LANE11_PCS_DWORD8 0x220 +#define R_PCH_LP_HSIO_LANE14_PCS_DWORD8 0x820 +#define R_PCH_LP_HSIO_LANE15_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE18_PCS_DWORD8 0x820 +#define R_PCH_H_HSIO_LANE19_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE22_PCS_DWORD8 0x020 +#define R_PCH_H_HSIO_LANE23_PCS_DWORD8 0x220 +#define R_PCH_H_HSIO_LANE24_PCS_DWORD8 0x420 +#define R_PCH_H_HSIO_LANE25_PCS_DWORD8 0x620 +#define R_PCH_H_HSIO_LANE26_PCS_DWORD8 0x820 +#define R_PCH_H_HSIO_LANE27_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE28_PCS_DWORD8 0xC20 +#define R_PCH_H_HSIO_LANE29_PCS_DWORD8 0xE20 + +#define R_PCH_HSIO_CLANE0_CMN_ANA_DWORD2 0x8088 +#define B_PCH_HSIO_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_PLLEN_H_OVRDEN = BIT5 +#define B_PCH_HSIO_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_FULLCALRESET_L_OVERDE= N BIT3 + +#define R_PCH_HSIO_PLL_SSC_DWORD2 0x8108 +#define B_PCH_HSIO_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 | BIT22 | B= IT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 16 +#define B_PCH_HSIO_PLL_SSC_DWORD2_SSCSEN BIT10 +#define N_PCH_HSIO_PLL_SSC_DWORD2_SSCSEN 10 + +#define R_PCH_HSIO_PLL_SSC_DWORD3 0x810C +#define B_PCH_HSIO_PLL_SSC_DWORD3_SSC_PROPAGATE BIT0 + +#define R_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12 0x8030 +#define B_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12_O_CFG_PWR_GATING_CTRL BIT0 + +// +// xHCI SSIC Private Configuration Register, but with opcode 4/5 for read/= write access +// +#define R_PCH_PCR_MMP0_LANE_0_OFFSET 0x0 +#define R_PCH_PCR_MMP0_LANE_1_OFFSET 0x2000 +#define R_PCH_PCR_MMP0_IMPREG21 0x1050 +#define R_PCH_PCR_MMP0_IMPREG22 0x1054 +#define R_PCH_PCR_MMP0_IMPREG23 0x1058 +#define R_PCH_PCR_MMP0_IMPREG24 0x105C +#define R_PCH_PCR_MMP0_IMPREG25 0x1060 +#define R_PCH_PCR_MMP0_CMNREG4 0xF00C +#define R_PCH_PCR_MMP0_CMNREG15 0xF038 +#define R_PCH_PCR_MMP0_CMNREG16 0xF03C + +#endif //_PCH_REGS_HSIO_H_ + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsIsh.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsIsh.h new file mode 100644 index 0000000000..2f519c539f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsIsh= .h @@ -0,0 +1,51 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_ISH_H_ +#define _PCH_REGS_ISH_H_ + +// +// ISH Controller Registers (D19:F0) +// +// PCI Configuration Space Registers +#define PCI_DEVICE_NUMBER_PCH_ISH 19 +#define PCI_FUNCTION_NUMBER_PCH_ISH 0 +#define V_PCH_ISH_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_ISH_DEVICE_ID 0xA135 +#define V_PCH_LP_ISH_DEVICE_ID 0x9D35 + +#define R_PCH_ISH_BAR0_LOW 0x10 +#define R_PCH_ISH_BAR0_HIGH 0x14 +#define V_PCH_ISH_BAR0_SIZE 0x100000 +#define N_PCH_ISH_BAR0_ALIGNMENT 20 +#define R_PCH_ISH_BAR1_LOW 0x18 +#define R_PCH_ISH_BAR1_HIGH 0x1C +#define V_PCH_ISH_BAR1_SIZE 0x1000 +#define N_PCH_ISH_BAR1_ALIGNMENT 12 + +// +// ISH Private Configuration Space Registers (IOSF2OCP) +// (PID:ISH) +// +#define R_PCH_PCR_ISH_PMCTL 0x1D0 = ///< Power Management +#define R_PCH_PCR_ISH_PCICFGCTRL 0x200 = ///< PCI Configuration Control +#define B_PCH_PCR_ISH_PCICFGCTR_PCI_IRQ 0x0FF00000 = ///< PCI IRQ number +#define N_PCH_PCR_ISH_PCICFGCTR_PCI_IRQ 20 +#define B_PCH_PCR_ISH_PCICFGCTR_ACPI_IRQ 0x000FF000 = ///< ACPI IRQ number +#define N_PCH_PCR_ISH_PCICFGCTR_ACPI_IRQ 12 +#define B_PCH_PCR_ISH_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8= ) ///< Interrupt Pin +#define N_PCH_PCR_ISH_PCICFGCTR_IPIN1 8 +#define B_PCH_PCR_ISH_PCICFGCTRL_BAR1DIS BIT7 = ///< BAR1 Disable + +// +// Number of pins used by ISH controllers +// +#define PCH_ISH_PINS_PER_I2C_CONTROLLER 2 +#define PCH_ISH_PINS_PER_UART_CONTROLLER 4 +#define PCH_ISH_PINS_PER_SPI_CONTROLLER 4 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsItss.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsItss.h new file mode 100644 index 0000000000..762fbe3b8e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsIts= s.h @@ -0,0 +1,68 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_ITSS_H_ +#define _PCH_REGS_ITSS_H_ + +// +// ITSS PCRs (PID:ITSS) +// +#define R_PCH_PCR_ITSS_PIRQA_ROUT 0x3100 ///< PIRQA R= outing Control register +#define R_PCH_PCR_ITSS_PIRQB_ROUT 0x3101 ///< PIRQB R= outing Control register +#define R_PCH_PCR_ITSS_PIRQC_ROUT 0x3102 ///< PIRQC R= outing Control register +#define R_PCH_PCR_ITSS_PIRQD_ROUT 0x3103 ///< PIRQD R= outing Control register +#define R_PCH_PCR_ITSS_PIRQE_ROUT 0x3104 ///< PIRQE R= outing Control register +#define R_PCH_PCR_ITSS_PIRQF_ROUT 0x3105 ///< PIRQF R= outing Control register +#define R_PCH_PCR_ITSS_PIRQG_ROUT 0x3106 ///< PIRQG R= outing Control register +#define R_PCH_PCR_ITSS_PIRQH_ROUT 0x3107 ///< PIRQH R= outing Control register +#define B_PCH_PCR_ITSS_PIRQX_ROUT_REN 0x80 ///< Interru= pt Routing Enable +#define B_PCH_PCR_ITSS_PIRQX_ROUT_IR 0x0F ///< IRQ Rou= tng +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_3 0x03 ///< Route P= IRQx to IRQ3 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_4 0x04 ///< Route P= IRQx to IRQ4 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_5 0x05 ///< Route P= IRQx to IRQ5 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_6 0x06 ///< Route P= IRQx to IRQ6 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_7 0x07 ///< Route P= IRQx to IRQ7 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_9 0x09 ///< Route P= IRQx to IRQ9 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_10 0x0A ///< Route P= IRQx to IRQ10 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_11 0x0B ///< Route P= IRQx to IRQ11 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_12 0x0C ///< Route P= IRQx to IRQ12 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_14 0x0E ///< Route P= IRQx to IRQ14 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_15 0x0F ///< Route P= IRQx to IRQ15 + +#define R_PCH_PCR_ITSS_PIR0 0x3140 ///< PCI Int= errupt Route 0 +#define R_PCH_PCR_ITSS_PIR1 0x3142 ///< PCI Int= errupt Route 1 +#define R_PCH_PCR_ITSS_PIR2 0x3144 ///< PCI Int= errupt Route 2 +#define R_PCH_PCR_ITSS_PIR3 0x3146 ///< PCI Int= errupt Route 3 +#define R_PCH_PCR_ITSS_PIR4 0x3148 ///< PCI Int= errupt Route 4 +#define R_PCH_PCR_ITSS_PIR5 0x314A ///< PCI Int= errupt Route 5 +#define R_PCH_PCR_ITSS_PIR6 0x314C ///< PCI Int= errupt Route 6 +#define R_PCH_PCR_ITSS_PIR7 0x314E ///< PCI Int= errupt Route 7 +#define R_PCH_PCR_ITSS_PIR8 0x3150 ///< PCI Int= errupt Route 8 +#define R_PCH_PCR_ITSS_PIR9 0x3152 ///< PCI Int= errupt Route 9 +#define R_PCH_PCR_ITSS_PIR10 0x3154 ///< PCI Int= errupt Route 10 +#define R_PCH_PCR_ITSS_PIR11 0x3156 ///< PCI Int= errupt Route 11 +#define R_PCH_PCR_ITSS_PIR12 0x3158 ///< PCI Int= errupt Route 12 + +#define R_PCH_PCR_ITSS_GIC 0x31FC ///< General= Interrupt Control +#define B_PCH_PCR_ITSS_GIC_MAX_IRQ_24 BIT9 ///< Max IRQ= entry size, 1 =3D 24 entry size, 0 =3D 120 entry size +#define B_PCH_PCR_ITSS_GIC_AME BIT17 ///< Alterna= te Access Mode Enable +#define B_PCH_PCR_ITSS_GIC_SPS BIT16 ///< Shutdow= n Policy Select +#define R_PCH_PCR_ITSS_IPC0 0x3200 ///< Interru= pt Polarity Control 0 +#define R_PCH_PCR_ITSS_IPC1 0x3204 ///< Interru= pt Polarity Control 1 +#define R_PCH_PCR_ITSS_IPC2 0x3208 ///< Interru= pt Polarity Control 2 +#define R_PCH_PCR_ITSS_IPC3 0x320C ///< Interru= pt Polarity Control 3 +#define R_PCH_PCR_ITSS_ITSSPRC 0x3300 ///< ITSS Po= wer Reduction Control +#define B_PCH_PCR_ITSS_ITSSPRC_PGCBDCGE BIT4 ///< PGCB Dy= namic Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_HPETDCGE BIT3 ///< HPET Dy= namic Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_8254CGE BIT2 ///< 8254 St= atic Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_IOSFICGE BIT1 ///< IOSF-Si= deband Interface Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_ITSSCGE BIT0 ///< ITSS Cl= ock Gate Enable + +#define R_PCH_PCR_ITSS_MMC 0x3334 ///< Master = Message Control +#define B_PCH_PCR_ITSS_MMC_MSTRMSG_EN BIT0 ///< Master = Message Enable + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsLan.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsLan.h new file mode 100644 index 0000000000..473216f61f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsLan= .h @@ -0,0 +1,135 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_LAN_H_ +#define _PCH_REGS_LAN_H_ + +// +// Gigabit LAN Controller configuration registers (D31:F6) +// +#define PCI_DEVICE_NUMBER_PCH_LAN 31 +#define PCI_FUNCTION_NUMBER_PCH_LAN 6 + +#define V_PCH_LAN_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_LAN_DEVICE_ID 0x156F + +// +// LBG Production Gigabit LAN Controller Device ID +// +#define V_PCH_LBG_PROD_LAN_DEVICE_ID 0xA1A5 +// +// LBG SSX (Super SKU) Gigabit LAN Controller Device ID +// +#define V_PCH_LBG_LAN_DEVICE_ID 0xA225 + +#define V_PCH_LP_LAN_DEVICE_ID 0x156F +#define R_PCH_LAN_MBARA 0x10 +#define B_PCH_LAN_MBARA_BA 0xFFFE0000 +#define N_PCH_LAN_MBARA_ALIGN 17 +#define R_PCH_LAN_LTR_CAP 0xA8 +#define R_PCH_LAN_CLIST1 0xC8 +#define B_PCH_LAN_CLIST1_NEXT 0xFF00 +#define B_PCH_LAN_CLIST1_CID 0x00FF +#define R_PCH_LAN_PMC 0xCA +#define B_PCH_LAN_PMC_PMES 0xF800 +#define B_PCH_LAN_PMC_D2S BIT10 +#define B_PCH_LAN_PMC_D1S BIT9 +#define B_PCH_LAN_PMC_AC (BIT8 | BIT7 | BIT6) +#define B_PCH_LAN_PMC_DSI BIT5 +#define B_PCH_LAN_PMC_PMEC BIT3 +#define B_PCH_LAN_PMC_VS (BIT2 | BIT1 | BIT0) +#define R_PCH_LAN_PMCS 0xCC +#define B_PCH_LAN_PMCS_PMES BIT15 +#define B_PCH_LAN_PMCS_DSC (BIT14 | BIT13) +#define B_PCH_LAN_PMCS_DSL 0x1E00 +#define V_PCH_LAN_PMCS_DSL0 0x0000 +#define V_PCH_LAN_PMCS_DSL3 0x0600 +#define V_PCH_LAN_PMCS_DSL4 0x0800 +#define V_PCH_LAN_PMCS_DSL7 0x0E00 +#define V_PCH_LAN_PMCS_DSL8 0x1000 +#define B_PCH_LAN_PMCS_PMEE BIT8 +#define B_PCH_LAN_PMCS_PS (BIT1 | BIT0) +#define V_PCH_LAN_PMCS_PS0 0x00 +#define V_PCH_LAN_PMCS_PS3 0x03 +#define R_PCH_LAN_DR 0xCF +#define B_PCH_LAN_DR 0xFF +#define R_PCH_LAN_CLIST2 0xD0 +#define B_PCH_LAN_CLIST2_NEXT 0xFF00 +#define B_PCH_LAN_CLIST2_CID 0x00FF +#define R_PCH_LAN_MCTL 0xD2 +#define B_PCH_LAN_MCTL_CID BIT7 +#define B_PCH_LAN_MCTL_MME (BIT6 | BIT5 | BIT4) +#define B_PCH_LAN_MCTL_MMC (BIT3 | BIT2 | BIT1) +#define B_PCH_LAN_MCTL_MSIE BIT0 +#define R_PCH_LAN_MADDL 0xD4 +#define B_PCH_LAN_MADDL 0xFFFFFFFF +#define R_PCH_LAN_MADDH 0xD8 +#define B_PCH_LAN_MADDH 0xFFFFFFFF +#define R_PCH_LAN_MDAT 0xDC +#define B_PCH_LAN_MDAT 0xFFFFFFFF +#define R_PCH_LAN_FLRCAP 0xE0 +#define B_PCH_LAN_FLRCAP_NEXT 0xFF00 +#define B_PCH_LAN_FLRCAP_CID 0x00FF +#define V_PCH_LAN_FLRCAP_CID_SSEL0 0x13 +#define V_PCH_LAN_FLRCAP_CID_SSEL1 0x09 +#define R_PCH_LAN_FLRCLV 0xE2 +#define B_PCH_LAN_FLRCLV_FLRC_SSEL0 BIT9 +#define B_PCH_LAN_FLRCLV_TXP_SSEL0 BIT8 +#define B_PCH_LAN_FLRCLV_VSCID_SSEL1 0xF000 +#define B_PCH_LAN_FLRCLV_CAPVER_SSEL1 0x0F00 +#define B_PCH_LAN_FLRCLV_CAPLNG 0x00FF +#define R_PCH_LAN_DEVCTRL 0xE4 +#define B_PCH_LAN_DEVCTRL BIT0 +#define R_PCH_LAN_CPCE 0x80 +#define B_PCH_LAN_CPCE_HAE BIT5 +#define B_PCH_LAN_CPCE_SE BIT3 +#define B_PCH_LAN_CPCE_D3HE BIT2 +#define B_PCH_LAN_CPCE_I3E BIT1 +#define B_PCH_LAN_CPCE_PCMCRE BIT0 +#define R_PCH_LAN_CD0I3 0x84 +#define B_PCH_LAN_CD0I3_RR BIT3 +#define B_PCH_LAN_CD0I3_D0I3 BIT2 +#define R_PCH_LAN_CLCTL 0x94 +#define R_PCH_LAN_LANDISCTRL 0xA0 +#define B_PCH_LAN_LANDISCTRL_DISABLE BIT0 +#define R_PCH_LAN_LOCKLANDIS 0xA4 +#define B_PCH_LAN_LOCKLANDIS_LOCK BIT0 +// +// Gigabit LAN Capabilities and Status Registers (Memory space) +// +#define R_PCH_LAN_CSR_CTRL 0 +#define B_PCH_LAN_CSR_CTRL_MEHE BIT19 +#define R_PCH_LAN_CSR_STRAP 0x000C +#define B_PCH_LAN_CSR_STRAP_NVM_VALID BIT11 +#define R_PCH_LAN_CSR_FEXTNVM6 0x0010 +#define R_PCH_LAN_CSR_CTRL_EXT 0x0018 +#define B_PCH_LAN_CSR_CTRL_EXT_FORCE_SMB BIT11 +#define R_PCH_LAN_CSR_MDIC 0x0020 +#define B_PCH_LAN_CSR_MDIC_RB BIT28 +#define B_PCH_LAN_CSR_MDIC_DATA 0xFFFF +#define R_PCH_LAN_CSR_FEXT 0x002C +#define B_PCH_LAN_CSR_FEXT_WOL BIT30 +#define B_PCH_LAN_CSR_FEXT_WOL_VALID BIT31 +#define R_PCH_LAN_CSR_EXTCNF_CTRL 0x0F00 +#define B_PCH_LAN_CSR_EXTCNF_CTRL_SWFLAG BIT5 +#define B_PCH_LAN_CSR_EXTCNF_K1OFF_EN BIT8 +#define R_PCH_LAN_CSR_PHY_CTRL 0x0F10 +#define B_PCH_LAN_CSR_PHY_CTRL_GGD BIT6 +#define B_PCH_LAN_CSR_PHY_CTRL_GBEDIS BIT3 +#define B_PCH_LAN_CSR_PHY_CTRL_LPLUND BIT2 +#define B_PCH_LAN_CSR_PHY_CTRL_LPLUD BIT1 +#define R_PCH_LAN_CSR_F18 0x0F18 +#define B_PCH_LAN_CSR_F18_K1OFF_EN BIT31 +#define R_PCH_LAN_CSR_PBECCSTS 0x100C +#define B_PCH_LAN_CSR_PBECCSTS_ECC_EN BIT16 +#define R_PCH_LAN_CSR_RAL 0x5400 +#define R_PCH_LAN_CSR_RAH 0x5404 +#define B_PCH_LAN_CSR_RAH_RAH 0x0000FFFF +#define R_PCH_LAN_CSR_WUC 0x5800 +#define B_PCH_LAN_CSR_WUC_APME BIT0 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsLpc.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsLpc.h new file mode 100644 index 0000000000..27fb432fbf --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsLpc= .h @@ -0,0 +1,430 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_LPC_H_ +#define _PCH_REGS_LPC_H_ + +#include +// +// PCI to LPC Bridge Registers (D31:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LPC 31 +#define PCI_FUNCTION_NUMBER_PCH_LPC 0 + +typedef enum { + PchHA0 =3D 0x00, + PchHB0 =3D 0x01, + PchHC0, + PchHD0, + PchHD1, +#ifdef SIMICS_FLAG + PchLpA0 =3D 0x20, +#endif + PchLpB0 =3D 0x23, + PchLpB1, + PchLpC0, + PchLpC1, + LbgA0 =3D LBG_A0, + LbgB0, + LbgB1, + LbgB2, + LbgS0, + LbgS1, +#ifdef SKXD_EN + LbgB1_D, +#endif // SKXD_EN + PchSteppingMax +} PCH_STEPPING; + +#define PCH_H_MIN_SUPPORTED_STEPPING PchHA0 +#define PCH_LP_MIN_SUPPORTED_STEPPING PchLpB0 + +#define PCH_LBG_MIN_SUPPORTED_STEPPING LbgA0 +#define V_PCH_LPC_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +// +// +// SKL PCH Server/WS LPC Device IDs +// +#define V_PCH_H_LPC_DEVICE_ID_SVR_0 0xA149 ///< Ser= ver SKU Intel C236 Chipset +#define V_PCH_H_LPC_DEVICE_ID_SVR_1 0xA14A ///< Ser= ver SKU Intel C232 Chipset +#define V_PCH_H_LPC_DEVICE_ID_SVR_2 0xA150 ///< Ser= ver SKU Intel CM236 Chipset +#define V_PCH_H_LPC_DEVICE_ID_A14B 0xA14B ///< Sup= er SKU Unlocked + +// +// SKL PCH-H Desktop LPC Device IDs +// +#define V_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU 0xA141 ///< PCH= H Desktop Super SKU unlocked +#define V_PCH_H_LPC_DEVICE_ID_DT_0 0xA142 ///< PCH= H Desktop Super SKU locked +#define V_PCH_H_LPC_DEVICE_ID_DT_1 0xA143 ///< PCH= H Desktop H110 +#define V_PCH_H_LPC_DEVICE_ID_DT_2 0xA144 ///< PCH= H Desktop H170 +#define V_PCH_H_LPC_DEVICE_ID_DT_3 0xA145 ///< PCH= H Desktop Z170 +#define V_PCH_H_LPC_DEVICE_ID_DT_4 0xA146 ///< PCH= H Desktop Q170 +#define V_PCH_H_LPC_DEVICE_ID_DT_5 0xA147 ///< PCH= H Desktop Q150 +#define V_PCH_H_LPC_DEVICE_ID_DT_6 0xA148 ///< PCH= H Desktop B150 +#define V_PCH_H_LPC_DEVICE_ID_UNFUSE 0xA140 ///< PCH= -H Unfuse +// +// PCH-H Mobile LPC Device IDs +// +#define V_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU 0xA141 ///< PCH= H Mobile Super SKU unlocked +#define V_PCH_H_LPC_DEVICE_ID_MB_0 0xA14D ///< PCH= H Mobile QM170 +#define V_PCH_H_LPC_DEVICE_ID_MB_1 0xA14E ///< PCH= H Mobile HM170 +#define V_PCH_H_LPC_DEVICE_ID_MB_2 0xA14F ///< PCH= H Mobile QMS170 (SFF) +// +// PCH-LP LPC Device IDs +// +#define V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU 0x9D41 ///< PCH= LP Mobile Super SKU unlocked +#define V_PCH_LP_LPC_DEVICE_ID_MB_0 0x9D42 ///< PCH= LP Mobile Super SKU locked +#define V_PCH_LP_LPC_DEVICE_ID_MB_1 0x9D43 ///< PCH= LP Mobile (U) Base SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_2 0x9D46 ///< PCH= LP Mobile (Y) Premium SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_3 0x9D48 ///< PCH= LP Mobile (U) Premium SKU +#define V_PCH_LP_LPC_DEVICE_ID_UNFUSE 0x9D40 ///< PCH= LP Unfuse + +// +// Lewisburg Production LPC Device ID's +// +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_0 0xA1C0 ///< LBG= PRQ Unfused LBG 0 SKU +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_1G 0xA1C1 ///< LBG= PRQ Fused LBG 1G +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_2 0xA1C2 ///< LBG= PRQ Fused LBG 2 +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_4 0xA1C3 ///< LBG= PRQ Fused LBG 4 +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_E 0xA1C4 ///< LBG= PRQ Fused LBG E +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_M 0xA1C5 ///< LBG= PRQ Fused LBG M +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_T 0xA1C6 ///< LBG= PRQ Fused LBG T (both uplinks SKU - NS) +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_LP 0xA1C7 ///< LBG= PRQ Fused LBG LP + +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_RESERVED_MAX 0xA1CF ///< 0xA1= C8-0xA1CF reserved for future QS/PRQ SKUs + +// +// Lewisburg SSX (Super SKUs and pre production) LPC Device ID's +// +#define V_PCH_LBG_LPC_DEVICE_ID_UNFUSED 0xA240 ///< LBG= SSX Unfused SKU +#define V_PCH_LBG_LPC_DEVICE_ID_SS_0 0xA241 ///< LBG= SSX Super SKU 0 +#define V_PCH_LBG_LPC_DEVICE_ID_SS_4_SD 0xA242 ///< LBG= SSX Super SKU 4/SD +#define V_PCH_LBG_LPC_DEVICE_ID_SS_T80_NS 0xA243 ///< LBG= SSX Super SKU T80/NS +#define V_PCH_LBG_LPC_DEVICE_ID_SS_1G 0xA244 ///< LBG= SSX Super SKU 1G +#define V_PCH_LBG_LPC_DEVICE_ID_SS_T 0xA245 ///< LBG= Super SKU - T +#define V_PCH_LBG_LPC_DEVICE_ID_SS_L 0xA246 ///< LBG= Super SKU - L +#ifdef SKXD_EN +#define V_PCH_LBG_LPC_DEVICE_ID_SS_D1 0xA247 ///< LBG= Super SKU - D co.fb.sh.1 +#define V_PCH_LBG_LPC_DEVICE_ID_SS_D2 0xA248 ///< LBG= Super SKU - D st.gp.sh.2 +#define V_PCH_LBG_LPC_DEVICE_ID_SS_D3 0xA249 ///< LBG= Super SKU - D ne.gp.sh.1 +#endif // SKXD_EN + +#define V_PCH_LBG_LPC_DEVICE_ID_RESERVED_SS_MAX 0xA24F ///< 0xA= 247-0xA24F Super SKU reserved + + +#define V_PCH_LBG_LPC_RID_0 0x00 ///< A0 = stepping +#define V_PCH_LBG_LPC_RID_1 0x01 ///< A1 = stepping +#define V_PCH_LBG_LPC_RID_2 0x02 ///< B0 = stepping +#define V_PCH_LBG_LPC_RID_3 0x03 ///< B1 = stepping +#define V_PCH_LBG_LPC_RID_4 0x04 ///< B2 = stepping +#define V_PCH_LBG_LPC_RID_8 0x08 ///< S0 = stepping +#define V_PCH_LBG_LPC_RID_9 0x09 ///< S1 = stepping + +#define V_PCH_LPC_RID_0 0x00 +#define V_PCH_LPC_RID_1 0x01 +#define V_PCH_LPC_RID_9 0x09 +#define V_PCH_LPC_RID_10 0x10 +#define V_PCH_LPC_RID_11 0x11 +#define V_PCH_LPC_RID_20 0x20 +#define V_PCH_LPC_RID_21 0x21 +#define V_PCH_LPC_RID_30 0x30 +#define V_PCH_LPC_RID_31 0x31 +#define R_PCH_LPC_SERIRQ_CNT 0x64 +#define B_PCH_LPC_SERIRQ_CNT_SIRQEN 0x80 +#define B_PCH_LPC_SERIRQ_CNT_SIRQMD 0x40 +#define B_PCH_LPC_SERIRQ_CNT_SIRQSZ 0x3C +#define N_PCH_LPC_SERIRQ_CNT_SIRQSZ 2 +#define B_PCH_LPC_SERIRQ_CNT_SFPW 0x03 +#define N_PCH_LPC_SERIRQ_CNT_SFPW 0 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_4CLK 0x00 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_6CLK 0x01 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_8CLK 0x02 +#define R_PCH_LPC_IOD 0x80 +#define B_PCH_LPC_IOD_FDD 0x1000 +#define N_PCH_LPC_IOD_FDD 12 +#define V_PCH_LPC_IOD_FDD_3F0 0 +#define V_PCH_LPC_IOD_FDD_370 1 +#define B_PCH_LPC_IOD_LPT 0x0300 +#define N_PCH_LPC_IOD_LPT 8 +#define V_PCH_LPC_IOD_LPT_378 0 +#define V_PCH_LPC_IOD_LPT_278 1 +#define V_PCH_LPC_IOD_LPT_3BC 2 +#define B_PCH_LPC_IOD_COMB 0x0070 +#define N_PCH_LPC_IOD_COMB 4 +#define V_PCH_LPC_IOD_COMB_3F8 0 +#define V_PCH_LPC_IOD_COMB_2F8 1 +#define V_PCH_LPC_IOD_COMB_220 2 +#define V_PCH_LPC_IOD_COMB_228 3 +#define V_PCH_LPC_IOD_COMB_238 4 +#define V_PCH_LPC_IOD_COMB_2E8 5 +#define V_PCH_LPC_IOD_COMB_338 6 +#define V_PCH_LPC_IOD_COMB_3E8 7 +#define B_PCH_LPC_IOD_COMA 0x0007 +#define N_PCH_LPC_IOD_COMA 0 +#define V_PCH_LPC_IOD_COMA_3F8 0 +#define V_PCH_LPC_IOD_COMA_2F8 1 +#define V_PCH_LPC_IOD_COMA_220 2 +#define V_PCH_LPC_IOD_COMA_228 3 +#define V_PCH_LPC_IOD_COMA_238 4 +#define V_PCH_LPC_IOD_COMA_2E8 5 +#define V_PCH_LPC_IOD_COMA_338 6 +#define V_PCH_LPC_IOD_COMA_3E8 7 +#define R_PCH_LPC_IOE 0x82 +#define B_PCH_LPC_IOE_ME2 BIT13 ///< Mic= rocontroller Enable #2, Enables decoding of I/O locations 4Eh and 4Fh to LPC +#define B_PCH_LPC_IOE_SE BIT12 ///< Sup= er I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC. +#define B_PCH_LPC_IOE_ME1 BIT11 ///< Mic= rocontroller Enable #1, Enables decoding of I/O locations 62h and 66h to LP= C. +#define B_PCH_LPC_IOE_KE BIT10 ///< Key= board Enable, Enables decoding of the keyboard I/O locations 60h and 64h to= LPC. +#define B_PCH_LPC_IOE_HGE BIT9 ///< Hig= h Gameport Enable, Enables decoding of the I/O locations 208h to 20Fh to LP= C. +#define B_PCH_LPC_IOE_LGE BIT8 ///< Low= Gameport Enable, Enables decoding of the I/O locations 200h to 207h to LPC. +#define B_PCH_LPC_IOE_FDE BIT3 ///< Flo= ppy Drive Enable, Enables decoding of the FDD range to LPC. Range is select= ed by LIOD.FDE +#define B_PCH_LPC_IOE_PPE BIT2 ///< Par= allel Port Enable, Enables decoding of the LPT range to LPC. Range is selec= ted by LIOD.LPT. +#define B_PCH_LPC_IOE_CBE BIT1 ///< Com= Port B Enable, Enables decoding of the COMB range to LPC. Range is selecte= d LIOD.CB. +#define B_PCH_LPC_IOE_CAE BIT0 ///< Com= Port A Enable, Enables decoding of the COMA range to LPC. Range is selecte= d LIOD.CA. +#define R_PCH_LPC_GEN1_DEC 0x84 +#define R_PCH_LPC_GEN2_DEC 0x88 +#define R_PCH_LPC_GEN3_DEC 0x8C +#define R_PCH_LPC_GEN4_DEC 0x90 +#define B_PCH_LPC_GENX_DEC_IODRA 0x00FC0000 +#define B_PCH_LPC_GENX_DEC_IOBAR 0x0000FFFC +#define B_PCH_LPC_GENX_DEC_EN 0x00000001 +#define R_PCH_LPC_ULKMC 0x94 +#define B_PCH_LPC_ULKMC_SMIBYENDPS BIT15 +#define B_PCH_LPC_ULKMC_TRAPBY64W BIT11 +#define B_PCH_LPC_ULKMC_TRAPBY64R BIT10 +#define B_PCH_LPC_ULKMC_TRAPBY60W BIT9 +#define B_PCH_LPC_ULKMC_TRAPBY60R BIT8 +#define B_PCH_LPC_ULKMC_SMIATENDPS BIT7 +#define B_PCH_LPC_ULKMC_PSTATE BIT6 +#define B_PCH_LPC_ULKMC_A20PASSEN BIT5 +#define B_PCH_LPC_ULKMC_USBSMIEN BIT4 +#define B_PCH_LPC_ULKMC_64WEN BIT3 +#define B_PCH_LPC_ULKMC_64REN BIT2 +#define B_PCH_LPC_ULKMC_60WEN BIT1 +#define B_PCH_LPC_ULKMC_60REN BIT0 +#define R_PCH_LPC_LGMR 0x98 +#define B_PCH_LPC_LGMR_MA 0xFFFF0000 +#define B_PCH_LPC_LGMR_LMRD_EN BIT0 +#define LPC_ESPI_FIRST_SLAVE 0 +#define ESPI_SECONDARY_SLAVE 1 + +#define R_PCH_LPC_FWH_BIOS_SEL 0xD0 +#define B_PCH_LPC_FWH_BIOS_SEL_F8 0xF0000000 +#define B_PCH_LPC_FWH_BIOS_SEL_F0 0x0F000000 +#define B_PCH_LPC_FWH_BIOS_SEL_E8 0x00F00000 +#define B_PCH_LPC_FWH_BIOS_SEL_E0 0x000F0000 +#define B_PCH_LPC_FWH_BIOS_SEL_D8 0x0000F000 +#define B_PCH_LPC_FWH_BIOS_SEL_D0 0x00000F00 +#define B_PCH_LPC_FWH_BIOS_SEL_C8 0x000000F0 +#define B_PCH_LPC_FWH_BIOS_SEL_C0 0x0000000F +#define R_PCH_LPC_FWH_BIOS_SEL2 0xD4 +#define B_PCH_LPC_FWH_BIOS_SEL2_70 0xF000 +#define B_PCH_LPC_FWH_BIOS_SEL2_60 0x0F00 +#define B_PCH_LPC_FWH_BIOS_SEL2_50 0x00F0 +#define B_PCH_LPC_FWH_BIOS_SEL2_40 0x000F +#define R_PCH_LPC_BDE 0xD8 = ///< BIOS decode enable +#define B_PCH_LPC_BDE_F8 0x8000 +#define B_PCH_LPC_BDE_F0 0x4000 +#define B_PCH_LPC_BDE_E8 0x2000 +#define B_PCH_LPC_BDE_E0 0x1000 +#define B_PCH_LPC_BDE_D8 0x0800 +#define B_PCH_LPC_BDE_D0 0x0400 +#define B_PCH_LPC_BDE_C8 0x0200 +#define B_PCH_LPC_BDE_C0 0x0100 +#define B_PCH_LPC_BDE_LEG_F 0x0080 +#define B_PCH_LPC_BDE_LEG_E 0x0040 +#define B_PCH_LPC_BDE_70 0x0008 +#define B_PCH_LPC_BDE_60 0x0004 +#define B_PCH_LPC_BDE_50 0x0002 +#define B_PCH_LPC_BDE_40 0x0001 +#define R_PCH_LPC_PCC 0xE0 +#define B_PCH_LPC_PCC_CLKRUN_EN 0x0001 +#define B_PCH_LPC_FVEC0_USB_PORT_CAP 0x00000C00 +#define V_PCH_LPC_FVEC0_USB_14_PORT 0x00000000 +#define V_PCH_LPC_FVEC0_USB_12_PORT 0x00000400 +#define V_PCH_LPC_FVEC0_USB_10_PORT 0x00000800 +#define B_PCH_LPC_FVEC0_SATA_RAID_CAP 0x00000080 +#define B_PCH_LPC_FVEC0_SATA_PORT23_CAP 0x00000040 +#define B_PCH_LPC_FVEC0_SATA_PORT1_6GB_CAP 0x00000008 +#define B_PCH_LPC_FVEC0_SATA_PORT0_6GB_CAP 0x00000004 +#define B_PCH_LPC_FVEC0_PCI_CAP 0x00000002 +#define R_PCH_LPC_FVEC1 0x01 +#define B_PCH_LPC_FVEC1_USB_R_CAP 0x00400000 +#define R_PCH_LPC_FVEC2 0x02 +#define V_PCH_LPC_FVEC2_PCIE_PORT78_CAP 0x00200000 +#define V_PCH_LPC_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000 ///< PCH= Integrated Graphics Support Capability +#define R_PCH_LPC_FVEC3 0x03 +#define B_PCH_LPC_FVEC3_DCMI_CAP 0x00002000 ///< Dat= a Center Manageability Interface (DCMI) Capability +#define B_PCH_LPC_FVEC3_NM_CAP 0x00001000 ///< Nod= e Manager Capability + +#define R_PCH_LPC_MDAP 0xC0 +#define B_PCH_LPC_MDAP_POLICY_EN BIT31 +#define B_PCH_LPC_MDAP_PDMA_EN BIT30 +#define B_PCH_LPC_MDAP_VALUE 0x0001FFFF + +// +// APM Registers +// +#define R_PCH_APM_CNT 0xB2 +#define R_PCH_APM_STS 0xB3 + +#define R_PCH_LPC_BC 0xDC ///< Bio= s Control +#define S_PCH_LPC_BC 1 +#define B_PCH_LPC_BC_BILD BIT7 ///< BIO= S Interface Lock-Down +#define B_PCH_LPC_BC_BBS BIT6 ///< Boo= t BIOS strap +#define N_PCH_LPC_BC_BBS 6 +#define V_PCH_LPC_BC_BBS_SPI 0 ///< Boo= t BIOS strapped to SPI +#define V_PCH_LPC_BC_BBS_LPC 1 ///< Boo= t BIOS strapped to LPC +#define B_PCH_LPC_BC_EISS BIT5 ///< Ena= ble InSMM.STS +#define B_PCH_LPC_BC_TS BIT4 ///< Top= Swap +#define B_PCH_LPC_BC_LE BIT1 ///< Loc= k Enable +#define N_PCH_LPC_BC_LE 1 +#define B_PCH_LPC_BC_WPD BIT0 ///< Wri= te Protect Disable + +#define R_PCH_ESPI_PCBC 0xDC ///< Per= ipheral Channel BIOS Control +#define S_PCH_ESPI_PCBC 4 ///< Per= ipheral Channel BIOS Control register size +#define B_PCH_ESPI_PCBC_BWRE BIT11 ///< BIO= S Write Report Enable +#define N_PCH_ESPI_PCBC_BWRE 11 ///< BIO= S Write Report Enable bit position +#define B_PCH_ESPI_PCBC_BWRS BIT10 ///< BIO= S Write Report Status +#define N_PCH_ESPI_PCBC_BWRS 10 ///< BIO= S Write Report Status bit position +#define B_PCH_ESPI_PCBC_BWPDS BIT8 ///< BIO= S Write Protect Disable Status +#define N_PCH_ESPI_PCBC_BWPDS 8 ///< BIO= S Write Protect Disable Status bit position +#define B_PCH_ESPI_PCBC_ESPI_EN BIT2 ///< eSP= I Enable Pin Strap +#define B_PCH_ESPI_PCBC_LE BIT1 ///< Loc= k Enable + +// +// Processor interface registers +// +#define R_PCH_NMI_SC 0x61 +#define B_PCH_NMI_SC_SERR_NMI_STS BIT7 +#define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6 +#define B_PCH_NMI_SC_TMR2_OUT_STS BIT5 +#define B_PCH_NMI_SC_REF_TOGGLE BIT4 +#define B_PCH_NMI_SC_IOCHK_NMI_EN BIT3 +#define B_PCH_NMI_SC_PCI_SERR_EN BIT2 +#define B_PCH_NMI_SC_SPKR_DAT_EN BIT1 +#define B_PCH_NMI_SC_TIM_CNT2_EN BIT0 +#define R_PCH_NMI_EN 0x70 +#define B_PCH_NMI_EN_NMI_EN BIT7 + +// +// PCH I/O Port Defines +// +#define R_PCH_IOPORT_PCI_INDEX 0xCF8 +#define R_PCH_IOPORT_PCI_DATA 0xCFC +#define PCI_CF8_ADDR(Bus, Dev, Func, Off) \ + (((Off) & 0xFF) | (((Func) & 0x07) << 8) | (((Dev) & 0x1F) << 11= ) | (((Bus) & 0xFF) << 16) | (1 << 31)) + +#define PCH_LPC_CF8_ADDR(Offset) PCI_CF8_ADDR(DEFAULT_PCI_BUS_NUMBER_PC= H, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, Offset) +// +// Reset Generator I/O Port +// +#define R_PCH_RST_CNT 0xCF9 +#define B_PCH_RST_CNT_FULL_RST BIT3 +#define B_PCH_RST_CNT_RST_CPU BIT2 +#define B_PCH_RST_CNT_SYS_RST BIT1 +#define V_PCH_RST_CNT_FULLRESET 0x0E +#define V_PCH_RST_CNT_HARDRESET 0x06 +#define V_PCH_RST_CNT_SOFTRESET 0x04 +#define V_PCH_RST_CNT_HARDSTARTSTATE 0x02 +#define V_PCH_RST_CNT_SOFTSTARTSTATE 0x00 + +// +// RTC register +// +#define R_PCH_RTC_INDEX 0x70 +#define R_PCH_RTC_TARGET 0x71 +#define R_PCH_RTC_EXT_INDEX 0x72 +#define R_PCH_RTC_EXT_TARGET 0x73 +#define R_PCH_RTC_INDEX_ALT 0x74 +#define R_PCH_RTC_TARGET_ALT 0x75 +#define R_PCH_RTC_EXT_INDEX_ALT 0x76 +#define R_PCH_RTC_EXT_TARGET_ALT 0x77 +#define R_PCH_RTC_REGA 0x0A +#define B_PCH_RTC_REGA_UIP 0x80 +#define R_PCH_RTC_REGB 0x0B +#define B_PCH_RTC_REGB_SET 0x80 +#define B_PCH_RTC_REGB_PIE 0x40 +#define B_PCH_RTC_REGB_AIE 0x20 +#define B_PCH_RTC_REGB_UIE 0x10 +#define B_PCH_RTC_REGB_DM 0x04 +#define B_PCH_RTC_REGB_HOURFORM 0x02 +#define R_PCH_RTC_REGC 0x0C +#define R_PCH_RTC_REGD 0x0D + +// +// Private Configuration Register +// RTC PCRs (PID:RTC) +// +#define R_PCH_PCR_RTC_CONF 0x3400 ///= < RTC Configuration register +#define S_PCH_PCR_RTC_CONF 4 +#define B_PCH_PCR_RTC_CONF_UCMOS_LOCK BIT4 +#define B_PCH_PCR_RTC_CONF_LCMOS_LOCK BIT3 +#define B_PCH_PCR_RTC_CONF_RESERVED BIT31 +#define B_PCH_PCR_RTC_CONF_UCMOS_EN BIT2 ///= < Upper CMOS bank enable +#define R_PCH_PCR_RTC_BUC 0x3414 ///= < Backed Up Control +#define B_PCH_PCR_RTC_BUC_TS BIT0 ///= < Top Swap +#define R_PCH_PCR_RTC_RTCDCG 0x3418 ///= < RTC Dynamic Clock Gating Control +#define R_PCH_PCR_RTC_RTCDCG_RTCPCICLKDCGEN BIT1 ///= < ipciclk_clk (24 MHz) Dynamic Clock Gate Enable +#define R_PCH_PCR_RTC_RTCDCG_RTCROSIDEDCGEN BIT0 ///= < rosc_side_clk (120 MHz) Dynamic Clock Gate Enable +#define R_PCH_PCR_RTC_3F00 0x3F00 +#define R_PCH_PCR_RTC_UIPSMI 0x3F04 ///= < RTC Update In Progress SMI Control + +// +// LPC PCR Registers +// +#define R_PCH_PCR_LPC_HVMTCTL 0x3410 +#define R_PCH_PCR_LPC_GCFD 0x3418 +#define R_PCH_PCR_LPC_PCT 0x3420 +#define R_PCH_PCR_LPC_SCT 0x3424 +#define R_PCH_PCR_LPC_LPCCT 0x3428 +#define R_PCH_PCR_LPC_ULTOR 0x3500 + +// +// eSPI PCR Registers +// +#define R_PCH_PCR_ESPI_SLV_CFG_REG_CTL 0x4000 = ///< Slave Configuration Register and Link Control +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRE BIT31 = ///< Slave Configuration Register Access Enable +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) = ///< Slave Configuration Register Access Status +#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS 28 = ///< Slave Configuration Register Access Status bit position +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SBLCL BIT27 = ///< IOSF-SB eSPI Link Configuration Lock +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS_NOERR 7 = ///< No errors (transaction completed successfully) +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) = ///< Slave ID +#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SID 19 = ///< Slave ID bit position +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) = ///< Slave Configuration Register Access Type +#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT 16 = ///< Slave Configuration Register Access Type bit position +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_RD 0 = ///< Slave Configuration register read from address SCRA[11:0] +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_WR 1 = ///< Slave Configuration register write to address SCRA[11:0] +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_STS 2 = ///< Slave Status register read +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_RS 3 = ///< In-Band reset +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRA 0x00000FFF = ///< Slave Configuration Register Address +#define R_PCH_PCR_ESPI_SLV_CFG_REG_DATA 0x4004 = ///< Slave Configuration Register Data + +#define R_PCH_PCR_ESPI_PCERR_SLV0 0x4020 ///< Per= ipheral Channel Error for Slave 0 +#define R_PCH_PCR_ESPI_PCERR_SLV1 0x4024 ///< Per= ipheral Channel Error for Slave 1 +#define R_PCH_PCR_ESPI_VWERR_SLV0 0x4030 ///< Vir= tual Wire Channel Error for Slave 0 +#define R_PCH_PCR_ESPI_VWERR_SLV1 0x4034 ///< Vir= tual Wire Channel Error for Slave 1 +#define R_PCH_PCR_ESPI_FCERR_SLV0 0x4040 ///< Fla= sh Access Channel Error for Slave 0 +#define B_PCH_PCR_ESPI_XERR_XNFEE (BIT14 | BIT13) ///< Non= -Fatal Error Reporting Enable bits +#define N_PCH_PCR_ESPI_XERR_XNFEE 13 ///< Non= -Fatal Error Reporting Enable bit position +#define V_PCH_PCR_ESPI_XERR_XNFEE_SMI 3 ///< Ena= ble Non-Fatal Error Reporting as SMI +#define B_PCH_PCR_ESPI_XERR_XNFES BIT12 ///< Fat= al Error Status +#define B_PCH_PCR_ESPI_XERR_XFEE (BIT6 | BIT5) ///< Fat= al Error Reporting Enable bits +#define N_PCH_PCR_ESPI_XERR_XFEE 5 ///< Fat= al Error Reporting Enable bit position +#define V_PCH_PCR_ESPI_XERR_XFEE_SMI 3 ///< Ena= ble Fatal Error Reporting as SMI +#define B_PCH_PCR_ESPI_XERR_XFES BIT4 ///< Fat= al Error Status +#define B_PCH_PCR_ESPI_PCERR_SLV0_PCURD BIT24 ///< Per= ipheral Channel Unsupported Request Detected +#define R_PCH_PCR_ESPI_LNKERR_SLV0 0x4050 ///< Lin= k Error for Slave 0 +#define S_PCH_PCR_ESPI_LNKERR_SLV0 4 ///< Lin= k Error for Slave 0 register size +#define B_PCH_PCR_ESPI_LNKERR_SLV0_SLCRR BIT31 ///< eSP= I Link and Slave Channel Recovery Required +#define B_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fat= al Error Type 1 Reporting Enable +#define N_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E 21 ///< Fat= al Error Type 1 Reporting Enable bit position +#define V_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E_SMI 3 ///< Ena= ble Fatal Error Type 1 Reporting as SMI +#define B_PCH_PCR_ESPI_LNKERR_SLV0_LFET1S BIT20 ///< Lin= k Fatal Error Type 1 Status + + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsP2sb.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsP2sb.h new file mode 100644 index 0000000000..3a3f8d5967 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsP2s= b.h @@ -0,0 +1,100 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_P2SB_H_ +#define _PCH_REGS_P2SB_H_ + +// +// PCI to P2SB Bridge Registers (D31:F1) +// +#define PCI_DEVICE_NUMBER_PCH_P2SB 31 +#define PCI_FUNCTION_NUMBER_PCH_P2SB 1 + +#define V_PCH_P2SB_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_P2SB_SBREG_BAR 0x10 +#define B_PCH_P2SB_SBREG_RBA 0xFF000000 +#define R_PCH_P2SB_SBREG_BARH 0x14 +#define B_PCH_P2SB_SBREG_RBAH 0xFFFFFFFF +#define R_PCH_P2SB_VBDF 0x50 +#define B_PCH_P2SB_VBDF_BUF 0xFF00 +#define B_PCH_P2SB_VBDF_DEV 0x00F8 +#define B_PCH_P2SB_VBDF_FUNC 0x0007 +#define R_PCH_P2SB_ESMBDF 0x52 +#define B_PCH_P2SB_ESMBDF_BUF 0xFF00 +#define B_PCH_P2SB_ESMBDF_DEV 0x00F8 +#define B_PCH_P2SB_ESMBDF_FUNC 0x0007 +#define R_PCH_P2SB_RCFG 0x54 +#define B_PCH_P2SB_RCFG_RPRID 0x0000FF00 +#define B_PCH_P2SB_RCFG_RSE BIT0 +#define R_PCH_P2SB_HPTC 0x60 +#define B_PCH_P2SB_HPTC_AE BIT7 +#define B_PCH_P2SB_HPTC_AS 0x0003 +#define N_PCH_HPET_ADDR_ASEL 12 +#define V_PCH_HPET_BASE0 0xFED00000 +#define V_PCH_HPET_BASE1 0xFED01000 +#define V_PCH_HPET_BASE2 0xFED02000 +#define V_PCH_HPET_BASE3 0xFED03000 +#define R_PCH_P2SB_IOAC 0x64 +#define B_PCH_P2SB_IOAC_AE BIT8 +#define B_PCH_P2SB_IOAC_ASEL 0x00FF +#define N_PCH_IO_APIC_ASEL 12 +#define R_PCH_IO_APIC_INDEX 0xFEC00000 +#define R_PCH_IO_APIC_DATA 0xFEC00010 +#define R_PCH_IO_APIC_EOI 0xFEC00040 +#define R_PCH_P2SB_IBDF 0x6C +#define B_PCH_P2SB_IBDF_BUF 0xFF00 +#define B_PCH_P2SB_IBDF_DEV 0x00F8 +#define B_PCH_P2SB_IBDF_FUNC 0x0007 +#define R_PCH_P2SB_HBDF 0x70 +#define B_PCH_P2SB_HBDF_BUF 0xFF00 +#define B_PCH_P2SB_HBDF_DEV 0x00F8 +#define B_PCH_P2SB_HBDF_FUNC 0x0007 +#define R_PCH_P2SB_80 0x80 +#define R_PCH_P2SB_84 0x84 +#define R_PCH_P2SB_88 0x88 +#define R_PCH_P2SB_8C 0x8C +#define R_PCH_P2SB_90 0x90 +#define R_PCH_P2SB_94 0x94 +#define R_PCH_P2SB_98 0x98 +#define R_PCH_P2SB_9C 0x9C +#define R_PCH_P2SB_DISPBDF 0xA0 +#define B_PCH_P2SB_DISPBDF_DTBLK 0x00070000 +#define B_PCH_P2SB_DISPBDF_BUF 0x0000FF00 +#define B_PCH_P2SB_DISPBDF_DEV 0x000000F8 +#define B_PCH_P2SB_DISPBDF_FUNC 0x00000007 +#define R_PCH_P2SB_ICCOS 0xA4 +#define B_PCH_P2SB_ICCOS_MODBASE 0xFF00 +#define B_PCH_P2SB_ICCOS_BUFBASE 0x00FF + +// +// Definition for SBI +// +#define R_PCH_P2SB_SBIADDR 0xD0 +#define B_PCH_P2SB_SBIADDR_DESTID 0xFF000000 +#define B_PCH_P2SB_SBIADDR_RS 0x000F0000 +#define B_PCH_P2SB_SBIADDR_OFFSET 0x0000FFFF +#define R_PCH_P2SB_SBIDATA 0xD4 +#define B_PCH_P2SB_SBIDATA_DATA 0xFFFFFFFF +#define R_PCH_P2SB_SBISTAT 0xD8 +#define B_PCH_P2SB_SBISTAT_OPCODE 0xFF00 +#define B_PCH_P2SB_SBISTAT_POSTED BIT7 +#define B_PCH_P2SB_SBISTAT_RESPONSE 0x0006 +#define N_PCH_P2SB_SBISTAT_RESPONSE 1 +#define B_PCH_P2SB_SBISTAT_INITRDY BIT0 +#define R_PCH_P2SB_SBIRID 0xDA +#define B_PCH_P2SB_SBIRID_FBE 0xF000 +#define B_PCH_P2SB_SBIRID_BAR 0x0700 +#define B_PCH_P2SB_SBIRID_FID 0x00FF +#define R_PCH_P2SB_SBIEXTADDR 0xDC +#define B_PCH_P2SB_SBIEXTADDR_ADDR 0xFFFFFFFF + +// +// Others +// +#define R_PCH_P2SB_E0 0xE0 +#define R_PCH_P2SB_F4 0xF4 +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsPcie.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsPcie.h new file mode 100644 index 0000000000..e31d699b4d --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPci= e.h @@ -0,0 +1,513 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_PCIE_H_ +#define _PCH_REGS_PCIE_H_ + +// +// PCH PCI Express Root Ports (D28:F0~7 & D29:F0~3) +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8 7 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16 7 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20 3 + +#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +#define V_PCH_H_PCIE_DEVICE_ID_PORT1 0xA110 ///< PCI Express= Root Port #1, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT2 0xA111 ///< PCI Express= Root Port #2, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT3 0xA112 ///< PCI Express= Root Port #3, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT4 0xA113 ///< PCI Express= Root Port #4, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT5 0xA114 ///< PCI Express= Root Port #5, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT6 0xA115 ///< PCI Express= Root Port #6, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT7 0xA116 ///< PCI Express= Root Port #7, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT8 0xA117 ///< PCI Express= Root Port #8, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT9 0xA118 ///< PCI Express= Root Port #9, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT10 0xA119 ///< PCI Express= Root Port #10, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT11 0xA11A ///< PCI Express= Root Port #11, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT12 0xA11B ///< PCI Express= Root Port #12, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT13 0xA11C ///< PCI Express= Root Port #13, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT14 0xA11D ///< PCI Express= Root Port #14, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT15 0xA11E ///< PCI Express= Root Port #15, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT16 0xA11F ///< PCI Express= Root Port #16, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT17 0xA167 ///< PCI Express= Root Port #17, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT18 0xA168 ///< PCI Express= Root Port #18, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT19 0xA169 ///< PCI Express= Root Port #19, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT20 0xA16A ///< PCI Express= Root Port #20, SKL PCH H + +#define V_PCH_LP_PCIE_DEVICE_ID_PORT1 0x9D10 ///< PCI Express= Root Port #1, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT2 0x9D11 ///< PCI Express= Root Port #2, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT3 0x9D12 ///< PCI Express= Root Port #3, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT4 0x9D13 ///< PCI Express= Root Port #4, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT5 0x9D14 ///< PCI Express= Root Port #5, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT6 0x9D15 ///< PCI Express= Root Port #6, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT7 0x9D16 ///< PCI Express= Root Port #7, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT8 0x9D17 ///< PCI Express= Root Port #8, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT9 0x9D18 ///< PCI Express= Root Port #9, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT10 0x9D19 ///< PCI Express= Root Port #10, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT11 0x9D1A ///< PCI Express= Root Port #11, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT12 0x9D1B ///< PCI Express= Root Port #12, SKL PCH LP PCIe Device ID + +// +// LBG Production (PRQ) PCI Express Root Ports Device ID's +// +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT1 0xA190 ///< PCI Ex= press Root Port #1, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT2 0xA191 ///< PCI Ex= press Root Port #2, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT3 0xA192 ///< PCI Ex= press Root Port #3, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT4 0xA193 ///< PCI Ex= press Root Port #4, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT5 0xA194 ///< PCI Ex= press Root Port #5, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT6 0xA195 ///< PCI Ex= press Root Port #6, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT7 0xA196 ///< PCI Ex= press Root Port #7, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT8 0xA197 ///< PCI Ex= press Root Port #8, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT9 0xA198 ///< PCI Ex= press Root Port #9, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT10 0xA199 ///< PCI Ex= press Root Port #10, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT11 0xA19A ///< PCI Ex= press Root Port #11, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT12 0xA19B ///< PCI Ex= press Root Port #12, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT13 0xA19C ///< PCI Ex= press Root Port #13, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT14 0xA19D ///< PCI Ex= press Root Port #14, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT15 0xA19E ///< PCI Ex= press Root Port #15, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT16 0xA19F ///< PCI Ex= press Root Port #16, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT17 0xA1E7 ///< PCI Ex= press Root Port #17, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT18 0xA1E8 ///< PCI Ex= press Root Port #18, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT19 0xA1E9 ///< PCI Ex= press Root Port #19, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT20 0xA1EA ///< PCI Ex= press Root Port #20, LBG PRQ +// +// LBG Super SKU (SSX) PCI Express Root Ports Device ID's +// +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT1 0xA210 ///< PCI Express Ro= ot Port #1, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT2 0xA211 ///< PCI Express Ro= ot Port #2, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT3 0xA212 ///< PCI Express Ro= ot Port #3, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT4 0xA213 ///< PCI Express Ro= ot Port #4, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT5 0xA214 ///< PCI Express Ro= ot Port #5, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT6 0xA215 ///< PCI Express Ro= ot Port #6, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT7 0xA216 ///< PCI Express Ro= ot Port #7, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT8 0xA217 ///< PCI Express Ro= ot Port #8, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT9 0xA218 ///< PCI Express Ro= ot Port #9, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT10 0xA219 ///< PCI Express Ro= ot Port #10, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT11 0xA21A ///< PCI Express Ro= ot Port #11, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT12 0xA21B ///< PCI Express Ro= ot Port #12, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT13 0xA21C ///< PCI Express Ro= ot Port #13, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT14 0xA21D ///< PCI Express Ro= ot Port #14, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT15 0xA21E ///< PCI Express Ro= ot Port #15, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT16 0xA21F ///< PCI Express Ro= ot Port #16, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT17 0xA267 ///< PCI Express Ro= ot Port #17, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT18 0xA268 ///< PCI Express Ro= ot Port #18, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT19 0xA269 ///< PCI Express Ro= ot Port #19, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT20 0xA26A ///< PCI Express Ro= ot Port #20, LBG SSKU + +#define R_PCH_PCIE_CLIST 0x40 +#define R_PCH_PCIE_XCAP (R_PCH_PCIE_CLIST + R_PC= IE_XCAP_OFFSET) +#define R_PCH_PCIE_DCAP (R_PCH_PCIE_CLIST + R_PC= IE_DCAP_OFFSET) +#define R_PCH_PCIE_DCTL (R_PCH_PCIE_CLIST + R_PC= IE_DCTL_OFFSET) +#define R_PCH_PCIE_DSTS (R_PCH_PCIE_CLIST + R_PC= IE_DSTS_OFFSET) +#define R_PCH_PCIE_LCAP (R_PCH_PCIE_CLIST + R_PC= IE_LCAP_OFFSET) +#define B_PCH_PCIE_LCAP_PN 0xFF000000 +#define N_PCH_PCIE_LCAP_PN 24 +#define R_PCH_PCIE_LCTL (R_PCH_PCIE_CLIST + R_PC= IE_LCTL_OFFSET) +#define R_PCH_PCIE_LSTS (R_PCH_PCIE_CLIST + R_PC= IE_LSTS_OFFSET) +#define R_PCH_PCIE_SLCAP (R_PCH_PCIE_CLIST + R_PC= IE_SLCAP_OFFSET) +#define R_PCH_PCIE_SLCTL (R_PCH_PCIE_CLIST + R_PC= IE_SLCTL_OFFSET) +#define R_PCH_PCIE_SLSTS (R_PCH_PCIE_CLIST + R_PC= IE_SLSTS_OFFSET) +#define R_PCH_PCIE_RCTL (R_PCH_PCIE_CLIST + R_PC= IE_RCTL_OFFSET) +#define R_PCH_PCIE_RSTS (R_PCH_PCIE_CLIST + R_PC= IE_RSTS_OFFSET) +#define R_PCH_PCIE_DCAP2 (R_PCH_PCIE_CLIST + R_PC= IE_DCAP2_OFFSET) +#define R_PCH_PCIE_DCTL2 (R_PCH_PCIE_CLIST + R_PC= IE_DCTL2_OFFSET) +#define R_PCH_PCIE_LCTL2 (R_PCH_PCIE_CLIST + R_PC= IE_LCTL2_OFFSET) +#define R_PCH_PCIE_LSTS2 (R_PCH_PCIE_CLIST + R_PC= IE_LSTS2_OFFSET) + + +#define R_PCH_PCIE_MID 0x80 +#define S_PCH_PCIE_MID 2 +#define R_PCH_PCIE_MC 0x82 +#define S_PCH_PCIE_MC 2 +#define R_PCH_PCIE_MA 0x84 +#define S_PCH_PCIE_MA 4 +#define R_PCH_PCIE_MD 0x88 +#define S_PCH_PCIE_MD 2 + +#define R_PCH_PCIE_SVCAP 0x90 +#define S_PCH_PCIE_SVCAP 2 +#define R_PCH_PCIE_SVID 0x94 +#define S_PCH_PCIE_SVID 4 + +#define R_PCH_PCIE_PMCAP 0xA0 +#define R_PCH_PCIE_PMCS (R_PCH_PCIE_PMCAP + R_PC= IE_PMCS_OFFST) +#define R_PCH_PCIE_MPC2 0xD4 +#define S_PCH_PCIE_MPC2 4 +#define B_PCH_PCIE_MPC2_PTNFAE BIT12 +#define B_PCH_PCIE_MPC2_LSTP BIT6 +#define B_PCH_PCIE_MPC2_IEIME BIT5 +#define B_PCH_PCIE_MPC2_ASPMCOEN BIT4 +#define B_PCH_PCIE_MPC2_ASPMCO (BIT3 | BIT2) +#define V_PCH_PCIE_MPC2_ASPMCO_DISABLED 0 +#define V_PCH_PCIE_MPC2_ASPMCO_L0S (1 << 2) +#define V_PCH_PCIE_MPC2_ASPMCO_L1 (2 << 2) +#define V_PCH_PCIE_MPC2_ASPMCO_L0S_L1 (3 << 2) +#define B_PCH_PCIE_MPC2_EOIFD BIT1 + +#define R_PCH_PCIE_MPC 0xD8 +#define S_PCH_PCIE_MPC 4 +#define B_PCH_PCIE_MPC_PMCE BIT31 +#define B_PCH_PCIE_MPC_HPCE BIT30 +#define B_PCH_PCIE_MPC_MMBNCE BIT27 +#define B_PCH_PCIE_MPC_P8XDE BIT26 +#define B_PCH_PCIE_MPC_IRRCE BIT25 +#define B_PCH_PCIE_MPC_SRL BIT23 +#define B_PCH_PCIE_MPC_UCEL (BIT20 | BIT19 | BIT18) +#define N_PCH_PCIE_MPC_UCEL 18 +#define B_PCH_PCIE_MPC_CCEL (BIT17 | BIT16 | BIT15) +#define N_PCH_PCIE_MPC_CCEL 15 +#define B_PCH_PCIE_MPC_PCIESD (BIT14 | BIT13) +#define N_PCH_PCIE_MPC_PCIESD 13 +#define V_PCH_PCIE_MPC_PCIESD_GEN1 1 +#define V_PCH_PCIE_MPC_PCIESD_GEN2 2 +#define B_PCH_PCIE_MPC_MCTPSE BIT3 +#define B_PCH_PCIE_MPC_HPME BIT1 +#define N_PCH_PCIE_MPC_HPME 1 +#define B_PCH_PCIE_MPC_PMME BIT0 + +#define R_PCH_PCIE_SMSCS 0xDC +#define S_PCH_PCIE_SMSCS 4 +#define N_PCH_PCIE_SMSCS_LERSMIS 5 +#define N_PCH_PCIE_SMSCS_HPLAS 4 +#define N_PCH_PCIE_SMSCS_HPPDM 1 + +#define R_PCH_PCIE_RPDCGEN 0xE1 +#define S_PCH_PCIE_RPDCGEN 1 +#define B_PCH_PCIE_RPDCGEN_RPSCGEN BIT7 +#define B_PCH_PCIE_RPDCGEN_PTOCGE BIT6 +#define B_PCH_PCIE_RPDCGEN_LCLKREQEN BIT5 +#define B_PCH_PCIE_RPDCGEN_BBCLKREQEN BIT4 +#define B_PCH_PCIE_RPDCGEN_SRDBCGEN BIT2 +#define B_PCH_PCIE_RPDCGEN_RPDLCGEN BIT1 +#define B_PCH_PCIE_RPDCGEN_RPDBCGEN BIT0 + + +#define R_PCH_PCIE_PWRCTL 0xE8 +#define B_PCH_PCIE_PWRCTL_LTSSMRTC BIT20 +#define B_PCH_PCIE_PWRCTL_WPDMPGEP BIT17 +#define B_PCH_PCIE_PWRCTL_DBUPI BIT15 +#define B_PCH_PCIE_PWRCTL_TXSWING BIT13 +#define B_PCH_PCIE_PWRCTL_RPL1SQPOL BIT1 +#define B_PCH_PCIE_PWRCTL_RPDTSQPOL BIT0 + +#define R_PCH_PCIE_DC 0xEC +#define B_PCH_PCIE_DC_PCIBEM BIT2 + +#define R_PCH_PCIE_PHYCTL2 0xF5 +#define B_PCH_PCIE_PHYCTL2_TDFT (BIT7 | BIT6) +#define B_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4) +#define N_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT 4 +#define B_PCH_PCIE_PHYCTL2_PXPG3PLLOFFEN BIT1 +#define B_PCH_PCIE_PHYCTL2_PXPG2PLLOFFEN BIT0 + +#define R_PCH_PCIE_IOSFSBCS 0xF7 +#define B_PCH_PCIE_IOSFSBCS_SCPTCGE BIT6 +#define B_PCH_PCIE_IOSFSBCS_SIID (BIT3 | BIT2) + +#define R_PCH_PCIE_STRPFUSECFG 0xFC +#define B_PCH_PCIE_STRPFUSECFG_PXIP (BIT27 | BIT26 | BIT25 |= BIT24) +#define N_PCH_PCIE_STRPFUSECFG_PXIP 24 +#define B_PCH_PCIE_STRPFUSECFG_RPC (BIT15 | BIT14) +#define V_PCH_PCIE_STRPFUSECFG_RPC_1_1_1_1 0 +#define V_PCH_PCIE_STRPFUSECFG_RPC_2_1_1 1 +#define V_PCH_PCIE_STRPFUSECFG_RPC_2_2 2 +#define V_PCH_PCIE_STRPFUSECFG_RPC_4 3 +#define N_PCH_PCIE_STRPFUSECFG_RPC 14 +#define B_PCH_PCIE_STRPFUSECFG_MODPHYIOPMDIS BIT9 +#define B_PCH_PCIE_STRPFUSECFG_PLLSHTDWNDIS BIT8 +#define B_PCH_PCIE_STRPFUSECFG_STPGATEDIS BIT7 +#define B_PCH_PCIE_STRPFUSECFG_ASPMDIS BIT6 +#define B_PCH_PCIE_STRPFUSECFG_LDCGDIS BIT5 +#define B_PCH_PCIE_STRPFUSECFG_LTCGDIS BIT4 +#define B_PCH_PCIE_STRPFUSECFG_CDCGDIS BIT3 +#define B_PCH_PCIE_STRPFUSECFG_DESKTOPMOB BIT2 + +// +//PCI Express Extended Capability Registers +// + +#define R_PCH_PCIE_EXCAP_OFFSET 0x100 + +#define R_PCH_PCIE_EX_AECH 0x100 ///< Advanced Erro= r Reporting Capability Header +#define V_PCH_PCIE_EX_AEC_CV 0x1 +#define R_PCH_PCIE_EX_UEM (R_PCH_PCIE_EX_AECH + R_= PCIE_EX_UEM_OFFSET) + +#define R_PCH_PCIE_EX_CES 0x110 ///< Correctable E= rror Status +#define B_PCH_PCIE_EX_CES_BD BIT7 ///< Bad DLLP Stat= us +#define B_PCH_PCIE_EX_CES_BT BIT6 ///< Bad TLP Status +#define B_PCH_PCIE_EX_CES_RE BIT0 ///< Receiver Erro= r Status + + +//CES.RE, CES.BT, CES.BD + +#define R_PCH_PCIE_EX_ACSECH 0x140 ///< ACS Extended = Capability Header +#define V_PCH_PCIE_EX_ACS_CV 0x1 +#define R_PCH_PCIE_EX_ACSCAPR (R_PCH_PCIE_EX_ACSECH + = R_PCIE_EX_ACSCAPR_OFFSET) + +#define R_PCH_PCIE_EX_L1SECH 0x200 ///< L1 Sub-States= Extended Capability Header +#define V_PCH_PCIE_EX_L1S_CV 0x1 +#define R_PCH_PCIE_EX_L1SCAP (R_PCH_PCIE_EX_L1SECH + = R_PCIE_EX_L1SCAP_OFFSET) +#define R_PCH_PCIE_EX_L1SCTL1 (R_PCH_PCIE_EX_L1SECH + = R_PCIE_EX_L1SCTL1_OFFSET) +#define R_PCH_PCIE_EX_L1SCTL2 (R_PCH_PCIE_EX_L1SECH + = R_PCIE_EX_L1SCTL2_OFFSET) + +#define R_PCH_PCIE_EX_SPEECH 0x220 ///< Secondary PCI= Express Extended Capability Header +#define V_PCH_PCIE_EX_SPEECH_CV 0x1 + +#define R_PCH_PCIE_EX_LCTL3 (R_PCH_PCIE_EX_SPEECH + = R_PCIE_EX_LCTL3_OFFSET) +#define R_PCH_PCIE_EX_LES (R_PCH_PCIE_EX_SPEECH + = R_PCIE_EX_LES_OFFSET) +#define R_PCH_PCIE_EX_LECTL (R_PCH_PCIE_EX_SPEECH + = R_PCIE_EX_L01EC_OFFSET) +#define B_PCH_PCIE_EX_LECTL_UPTPH (BIT14 | BIT13 | BIT12) +#define N_PCH_PCIE_EX_LECTL_UPTPH 12 +#define B_PCH_PCIE_EX_LECTL_UPTP 0x0F00 +#define N_PCH_PCIE_EX_LECTL_UPTP 8 +#define B_PCH_PCIE_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4) +#define N_PCH_PCIE_EX_LECTL_DPTPH 4 +#define B_PCH_PCIE_EX_LECTL_DPTP 0x000F +#define N_PCH_PCIE_EX_LECTL_DPTP 0 + +#define R_PCH_PCIE_EX_L01EC (R_PCH_PCIE_EX_SPEECH + = R_PCIE_EX_L01EC_OFFSET) +#define R_PCH_PCIE_EX_L23EC (R_PCH_PCIE_EX_SPEECH + = R_PCIE_EX_L23EC_OFFSET) + +#define R_PCH_PCIE_PCIERTP1 0x300 +#define R_PCH_PCIE_PCIERTP2 0x304 +#define R_PCH_PCIE_PCIENFTS 0x314 +#define R_PCH_PCIE_PCIEL0SC 0x318 + +#define R_PCH_PCIE_PCIECFG2 0x320 +#define B_PCH_PCIE_PCIECFG2_LBWSSTE BIT30 +#define B_PCH_PCIE_PCIECFG2_RLLG3R BIT27 +#define B_PCH_PCIE_PCIECFG2_CROAOV BIT24 +#define B_PCH_PCIE_PCIECFG2_CROAOE BIT23 +#define B_PCH_PCIE_PCIECFG2_CRSREN BIT22 +#define B_PCH_PCIE_PCIECFG2_PMET (BIT21 | BIT20) +#define V_PCH_PCIE_PCIECFG2_PMET 1 +#define N_PCH_PCIE_PCIECFG2_PMET 20 + +#define R_PCH_PCIE_PCIEDBG 0x324 +#define B_PCH_PCIE_PCIEDBG_USSP (BIT27 | BIT26) +#define B_PCH_PCIE_PCIEDBG_LGCLKSQEXITDBTIMERS (BIT25 | BIT24) +#define B_PCH_PCIE_PCIEDBG_CTONFAE BIT14 +#define B_PCH_PCIE_PCIEDBG_SQOL0 BIT7 +#define B_PCH_PCIE_PCIEDBG_SPCE BIT5 +#define B_PCH_PCIE_PCIEDBG_LR BIT4 + +#define R_PCH_PCIE_PCIESTS1 0x328 +#define B_PCH_PCIE_PCIESTS1_LTSMSTATE 0xFF000000 +#define N_PCH_PCIE_PCIESTS1_LTSMSTATE 24 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDY 0x01 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDYECINP1CG 0x0E +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_L0 0x33 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAIT 0x5E +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAITPG 0x60 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYSPEEDREADY 0x6C +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYLNK2DETECT 0x6F + + +#define B_PCH_PCIE_PCIESTS1_LNKSTAT (BIT22 | BIT21 | BIT20 |= BIT19) +#define N_PCH_PCIE_PCIESTS1_LNKSTAT 19 +#define V_PCH_PCIE_PCIESTS1_LNKSTAT_L0 0x7 + +#define R_PCH_PCIE_PCIESTS2 0x32C +#define B_PCH_PCIE_PCIESTS2_P4PNCCWSSCMES BIT31 +#define B_PCH_PCIE_PCIESTS2_P3PNCCWSSCMES BIT30 +#define B_PCH_PCIE_PCIESTS2_P2PNCCWSSCMES BIT29 +#define B_PCH_PCIE_PCIESTS2_P1PNCCWSSCMES BIT28 +#define B_PCH_PCIE_PCIESTS2_CLRE 0x0000F000 +#define N_PCH_PCIE_PCIESTS2_CLRE 12 + +#define R_PCH_PCIE_PCIEALC 0x338 +#define B_PCH_PCIE_PCIEALC_ITLRCLD BIT29 +#define B_PCH_PCIE_PCIEALC_ILLRCLD BIT28 +#define B_PCH_PCIE_PCIEALC_BLKDQDA BIT26 +#define R_PCH_PCIE_PHYCTL4 0x408 +#define B_PCH_PCIE_PHYCTL4_SQDIS BIT27 + +#define R_PCH_PCIE_PCIEPMECTL2 0x424 +#define B_PCH_PCIE_PCIEPMECTL2_PHYCLPGE BIT11 +#define B_PCH_PCIE_PCIEPMECTL2_FDCPGE BIT8 +#define B_PCH_PCIE_PCIEPMECTL2_DETSCPGE BIT7 +#define B_PCH_PCIE_PCIEPMECTL2_L23RDYSCPGE BIT6 +#define B_PCH_PCIE_PCIEPMECTL2_DISSCPGE BIT5 +#define B_PCH_PCIE_PCIEPMECTL2_L1SCPGE BIT4 + +#define R_PCH_PCIE_PCE 0x428 +#define B_PCH_PCIE_PCE_HAE BIT5 +#define B_PCH_PCIE_PCE_PMCRE BIT0 + +#define R_PCH_PCIE_EQCFG1 0x450 +#define S_PCH_PCIE_EQCFG1 4 +#define B_PCH_PCIE_EQCFG1_REC 0xFF000000 +#define N_PCH_PCIE_EQCFG1_REC 24 +#define B_PCH_PCIE_EQCFG1_REIFECE BIT23 +#define N_PCH_PCIE_EQCFG1_LERSMIE 21 +#define B_PCH_PCIE_EQCFG1_LEP23B BIT18 +#define B_PCH_PCIE_EQCFG1_LEP3B BIT17 +#define B_PCH_PCIE_EQCFG1_RTLEPCEB BIT16 +#define B_PCH_PCIE_EQCFG1_RTPCOE BIT15 +#define B_PCH_PCIE_EQCFG1_HPCMQE BIT13 +#define B_PCH_PCIE_EQCFG1_HAED BIT12 +#define B_PCH_PCIE_EQCFG1_EQTS2IRRC BIT7 +#define B_PCH_PCIE_EQCFG1_TUPP BIT1 + +#define R_PCH_PCIE_RTPCL1 0x454 +#define B_PCH_PCIE_RTPCL1_PCM BIT31 +#define B_PCH_PCIE_RTPCL1_RTPRECL2PL4 0x3F000000 +#define B_PCH_PCIE_RTPCL1_RTPOSTCL1PL3 0xFC0000 +#define B_PCH_PCIE_RTPCL1_RTPRECL1PL2 0x3F000 +#define B_PCH_PCIE_RTPCL1_RTPOSTCL0PL1 0xFC0 +#define B_PCH_PCIE_RTPCL1_RTPRECL0PL0 0x3F + +#define R_PCH_PCIE_RTPCL2 0x458 +#define B_PCH_PCIE_RTPCL2_RTPOSTCL3PL 0x3F000 +#define B_PCH_PCIE_RTPCL2_RTPRECL3PL6 0xFC0 +#define B_PCH_PCIE_RTPCL2_RTPOSTCL2PL5 0x3F + +#define R_PCH_PCIE_RTPCL3 0x45C +#define B_PCH_PCIE_RTPCL3_RTPRECL7 0x3F000000 +#define B_PCH_PCIE_RTPCL3_RTPOSTCL6 0xFC0000 +#define B_PCH_PCIE_RTPCL3_RTPRECL6 0x3F000 +#define B_PCH_PCIE_RTPCL3_RTPOSTCL5 0xFC0 +#define B_PCH_PCIE_RTPCL3_RTPRECL5PL10 0x3F + +#define R_PCH_PCIE_RTPCL4 0x460 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL9 0x3F000000 +#define B_PCH_PCIE_RTPCL4_RTPRECL9 0xFC0000 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL8 0x3F000 +#define B_PCH_PCIE_RTPCL4_RTPRECL8 0xFC0 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL7 0x3F + +#define R_PCH_PCIE_FOMS 0x464 +#define B_PCH_PCIE_FOMS_I (BIT30 | BIT29) +#define N_PCH_PCIE_FOMS_I 29 +#define B_PCH_PCIE_FOMS_LN 0x1F000000 +#define N_PCH_PCIE_FOMS_LN 24 +#define B_PCH_PCIE_FOMS_FOMSV 0x00FFFFFF +#define B_PCH_PCIE_FOMS_FOMSV0 0x000000FF +#define N_PCH_PCIE_FOMS_FOMSV0 0 +#define B_PCH_PCIE_FOMS_FOMSV1 0x0000FF00 +#define N_PCH_PCIE_FOMS_FOMSV1 8 +#define B_PCH_PCIE_FOMS_FOMSV2 0x00FF0000 +#define N_PCH_PCIE_FOMS_FOMSV2 16 + +#define R_PCH_PCIE_HAEQ 0x468 +#define B_PCH_PCIE_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT29 |= BIT28) +#define N_PCH_PCIE_HAEQ_HAPCCPI 28 +#define B_PCH_PCIE_HAEQ_MACFOMC BIT19 + +#define R_PCH_PCIE_LTCO1 0x470 +#define B_PCH_PCIE_LTCO1_L1TCOE BIT25 +#define B_PCH_PCIE_LTCO1_L0TCOE BIT24 +#define B_PCH_PCIE_LTCO1_L1TPOSTCO 0xFC0000 +#define N_PCH_PCIE_LTCO1_L1TPOSTCO 18 +#define B_PCH_PCIE_LTCO1_L1TPRECO 0x3F000 +#define N_PCH_PCIE_LTCO1_L1TPRECO 12 +#define B_PCH_PCIE_LTCO1_L0TPOSTCO 0xFC0 +#define N_PCH_PCIE_LTCO1_L0TPOSTCO 6 +#define B_PCH_PCIE_LTCO1_L0TPRECO 0x3F +#define N_PCH_PCIE_LTCO1_L0TPRECO 0 + +#define R_PCH_PCIE_LTCO2 0x474 +#define B_PCH_PCIE_LTCO2_L3TCOE BIT25 +#define B_PCH_PCIE_LTCO2_L2TCOE BIT24 +#define B_PCH_PCIE_LTCO2_L3TPOSTCO 0xFC0000 +#define B_PCH_PCIE_LTCO2_L3TPRECO 0x3F000 +#define B_PCH_PCIE_LTCO2_L2TPOSTCO 0xFC0 +#define B_PCH_PCIE_LTCO2_L2TPRECO 0x3F + +#define R_PCH_PCIE_G3L0SCTL 0x478 +#define B_PCH_PCIE_G3L0SCTL_G3UCNFTS 0x0000FF00 +#define B_PCH_PCIE_G3L0SCTL_G3CCNFTS 0x000000FF + +#define R_PCH_PCIE_EQCFG2 0x47C +#define B_PCH_PCIE_EQCFG2_NTIC 0xFF000000 +#define B_PCH_PCIE_EQCFG2_EMD BIT23 +#define B_PCH_PCIE_EQCFG2_NTSS (BIT22 | BIT21 | BIT20) +#define B_PCH_PCIE_EQCFG2_PCET (BIT19 | BIT18 | BIT17 |= BIT16) +#define N_PCH_PCIE_EQCFG2_PCET 16 +#define B_PCH_PCIE_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT13 |= BIT12) +#define N_PCH_PCIE_EQCFG2_HAPCSB 12 +#define B_PCH_PCIE_EQCFG2_NTEME BIT11 +#define B_PCH_PCIE_EQCFG2_MPEME BIT10 +#define B_PCH_PCIE_EQCFG2_REWMETM (BIT9 | BIT8) +#define B_PCH_PCIE_EQCFG2_REWMET 0xFF + +#define R_PCH_PCIE_MM 0x480 +#define B_PCH_PCIE_MM_MSST 0xFFFFFF00 +#define N_PCH_PCIE_MM_MSST 8 +#define B_PCH_PCIE_MM_MSS 0xFF + +// +//PCI Express Extended End Point Capability Registers +// + +#define R_PCH_PCIE_LTRECH_OFFSET 0 +#define R_PCH_PCIE_LTRECH_CID 0x0018 +#define R_PCH_PCIE_LTRECH_MSLR_OFFSET 0x04 +#define R_PCH_PCIE_LTRECH_MNSLR_OFFSET 0x06 + + +// +// PCIE PCRs (PID:SPA SPB SPC SPD SPE) +// +#define R_PCH_PCR_SPX_PCD 0 = ///< Port configuration and disable +#define B_PCH_PCR_SPX_PCD_RP1FN (BIT2 | BIT1 | BIT0) = ///< Port 1 Function Number +#define B_PCH_PCR_SPX_PCD_RP1CH BIT3 = ///< Port 1 config hide +#define B_PCH_PCR_SPX_PCD_RP2FN (BIT6 | BIT5 | BIT4) = ///< Port 2 Function Number +#define B_PCH_PCR_SPX_PCD_RP2CH BIT7 = ///< Port 2 config hide +#define B_PCH_PCR_SPX_PCD_RP3FN (BIT10 | BIT9 | BIT8) = ///< Port 3 Function Number +#define B_PCH_PCR_SPX_PCD_RP3CH BIT11 = ///< Port 3 config hide +#define B_PCH_PCR_SPX_PCD_RP4FN (BIT14 | BIT13 | BIT12) = ///< Port 4 Function Number +#define B_PCH_PCR_SPX_PCD_RP4CH BIT15 = ///< Port 4 config hide +#define S_PCH_PCR_SPX_PCD_RP_FIELD 4 = ///< 4 bits for each RP FN +#define B_PCH_PCR_SPX_PCD_P1D BIT16 = ///< Port 1 disable +#define B_PCH_PCR_SPX_PCD_P2D BIT17 = ///< Port 2 disable +#define B_PCH_PCR_SPX_PCD_P3D BIT18 = ///< Port 3 disable +#define B_PCH_PCR_SPX_PCD_P4D BIT19 = ///< Port 4 disable +#define B_PCH_PCR_SPX_PCD_SRL BIT31 = ///< Secured Register Lock + +#define R_PCH_PCR_SPX_PCIEHBP 0x0004 = ///< PCI Express high-speed bypass +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPME BIT0 = ///< PCIe HBP mode enable +#define B_PCH_PCR_SPX_PCIEHBP_PCIEGMO (BIT2 | BIT1) = ///< PCIe gen mode override +#define B_PCH_PCR_SPX_PCIEHBP_PCIETIL0O BIT3 = ///< PCIe transmitter-in-L0 override +#define B_PCH_PCR_SPX_PCIEHBP_PCIERIL0O BIT4 = ///< PCIe receiver-in-L0 override +#define B_PCH_PCR_SPX_PCIEHBP_PCIELRO BIT5 = ///< PCIe link recovery override +#define B_PCH_PCR_SPX_PCIEHBP_PCIELDO BIT6 = ///< PCIe link down override +#define B_PCH_PCR_SPX_PCIEHBP_PCIESSM BIT7 = ///< PCIe SKP suppression mode +#define B_PCH_PCR_SPX_PCIEHBP_PCIESST BIT8 = ///< PCIe suppress SKP transmission +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPPS (BIT13 | BIT12) = ///< PCIe HBP port select +#define B_PCH_PCR_SPX_PCIEHBP_CRCSEL (BIT15 | BIT14) = ///< CRC select +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPCRC 0xFFFF0000 = ///< PCIe HBP CRC + + +// +// ICC PCR (PID: ICC) +// +#define R_PCH_PCR_ICC_TMCSRCCLK 0x1000 = ///< Timing Control SRC Clock Register +#define R_PCH_PCR_ICC_TMCSRCCLK2 0x1004 = ///< Timing Control SRC Clock Register 2 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsPcr.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsPcr.h new file mode 100644 index 0000000000..eea1b11ca8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPcr= .h @@ -0,0 +1,64 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_PCR_H_ +#define _PCH_REGS_PCR_H_ + +/// +/// Definition for PCR base address (defined in PchReservedResources.h) +/// +//#define PCH_PCR_BASE_ADDRESS 0xFD000000 +//#define PCH_PCR_MMIO_SIZE 0x01000000 +/** + Definition for PCR address + The PCR address is used to the PCR MMIO programming +**/ +#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | ((UINT8)(P= id) << 16) | (UINT16)(Offset)) + +/** + Definition for SBI PID + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI pro= gramming as well. +**/ +typedef enum { + PID_DMI =3D 0xEF, + PID_ESPISPI =3D 0xEE, + PID_MODPHY1 =3D 0xE9, + PID_OTG =3D 0xE5, + PID_SPE =3D 0xE4, // Reserved in SK= L PCH LP + PID_SPD =3D 0xE3, // Reserved in SK= L PCH LP + PID_SPC =3D 0xE2, + PID_SPB =3D 0xE1, + PID_SPA =3D 0xE0, + PID_ICC =3D 0xDC, + PID_DSP =3D 0xD7, + PID_FIA =3D 0xCF, + PID_FIAWM26 =3D 0x13, + PID_USB2 =3D 0xCA, + PID_LPC =3D 0xC7, + PID_SMB =3D 0xC6, + PID_ITSS =3D 0xC4, + PID_RTC =3D 0xC3, + PID_PSF4 =3D 0xBD, + PID_PSF3 =3D 0xBC, + PID_PSF2 =3D 0xBB, + PID_PSF1 =3D 0xBA, + PID_DCI =3D 0xB8, + PID_MMP0 =3D 0xB0, + PID_GPIOCOM0 =3D 0xAF, + PID_GPIOCOM1 =3D 0xAE, + PID_GPIOCOM2 =3D 0xAD, + PID_GPIOCOM3 =3D 0xAC, + PID_GPIOCOM4 =3D 0xAB, + PID_GPIOCOM5 =3D 0x11, + PID_MODPHY2 =3D 0xA9, + PID_MODPHY3 =3D 0xA8, + PID_CSME0 =3D 0x90, // CSE + PID_CSME_PSF =3D 0x8F, // ME PSF + PID_PSTH =3D 0x89 +} PCH_SBI_PID; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsPmc.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsPmc.h new file mode 100644 index 0000000000..e1d780be14 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPmc= .h @@ -0,0 +1,627 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_PMC_H_ +#define _PCH_REGS_PMC_H_ + +// +//PMC Registers (D31:F2) +// +#define PCI_DEVICE_NUMBER_PCH_PMC 31 +#define PCI_FUNCTION_NUMBER_PCH_PMC 2 + +#define V_PCH_PMC_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_PMC_DEVICE_ID 0x9D21 +// +// LBG Production (PRQ) PMC Device ID +// +#define V_PCH_LBG_PROD_PMC_DEVICE_ID 0xA1A1 +// +// LBG Super SKU (SSX) PMC Device ID +// +#define V_PCH_LBG_PMC_DEVICE_ID 0xA221 + +#define V_PCH_LP_PMC_DEVICE_ID 0x9D21 +#define R_PCH_PMC_PM_DATA_BAR 0x10 +#define B_PCH_PMC_PM_DATA_BAR 0xFFFFC000 +#define R_PCH_PMC_ACPI_BASE 0x40 +#define B_PCH_PMC_ACPI_BASE_BAR 0xFFFC +#define R_PCH_PMC_ACPI_CNT 0x44 +#define B_PCH_PMC_ACPI_CNT_PWRM_EN BIT8 = ///< PWRM enable +#define B_PCH_PMC_ACPI_CNT_ACPI_EN BIT7 = ///< ACPI eanble +#define B_PCH_PMC_ACPI_CNT_SCIS (BIT2 | BIT1 | BIT0) = ///< SCI IRQ select +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ9 0 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ10 1 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ11 2 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ20 4 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ21 5 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ22 6 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ23 7 +#define R_PCH_PMC_PWRM_BASE 0x48 +#define B_PCH_PMC_PWRM_BASE_BAR 0xFFFF0000 = ///< PWRM must be 64KB alignment to align the source decode. +#define R_PCH_PMC_GEN_PMCON_A 0xA0 +#define B_PCH_PMC_GEN_PMCON_A_DC_PP_DIS BIT30 +#define B_PCH_PMC_GEN_PMCON_A_DSX_PP_DIS BIT29 +#define B_PCH_PMC_GEN_PMCON_A_AG3_PP_EN BIT28 +#define B_PCH_PMC_GEN_PMCON_A_SX_PP_EN BIT27 +#define B_PCH_PMC_GEN_PMCON_A_DISB BIT23 +#define B_PCH_PMC_GEN_PMCON_A_MEM_SR BIT21 +#define B_PCH_PMC_GEN_PMCON_A_MS4V BIT18 +#define B_PCH_PMC_GEN_PMCON_A_GBL_RST_STS BIT16 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_PLL_SD_INC0 BIT13 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 BIT12 +#define B_PCH_PMC_GEN_PMCON_A_BIOS_PCI_EXP_EN BIT10 +#define B_PCH_PMC_GEN_PMCON_A_PWRBTN_LVL BIT9 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT7 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON BIT6 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON BIT5 +#define B_PCH_PMC_GEN_PMCON_A_SMI_LOCK BIT4 +#define B_PCH_PMC_GEN_PMCON_A_ESPI_SMI_LOCK BIT3 = ///< ESPI SMI lock +#define B_PCH_PMC_GEN_PMCON_A_PER_SMI_SEL 0x0003 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_64S 0x0000 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_32S 0x0001 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_16S 0x0002 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_8S 0x0003 +#define R_PCH_PMC_GEN_PMCON_B 0xA4 +#define B_PCH_PMC_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 = ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width +#define B_PCH_PMC_GEN_PMCON_B_ACPI_BASE_LOCK BIT17 = ///< Lock ACPI BASE at 0x40, only cleared by reset when set +#define B_PCH_PMC_GEN_PMCON_B_PM_DATA_BAR_DIS BIT16 +#define B_PCH_PMC_GEN_PMCON_B_PME_B0_S5_DIS BIT15 +#define B_PCH_PMC_GEN_PMCON_B_SUS_PWR_FLR BIT14 +#define B_PCH_PMC_GEN_PMCON_B_WOL_EN_OVRD BIT13 +#define B_PCH_PMC_GEN_PMCON_B_DISABLE_SX_STRETCH BIT12 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW 0xC00 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_60US 0x000 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_1MS 0x400 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_50MS 0x800 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_2S 0xC00 +#define B_PCH_PMC_GEN_PMCON_B_HOST_RST_STS BIT9 +#define B_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL 0xC0 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_64MS 0xC0 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_32MS 0x80 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_16MS 0x40 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_1_5MS 0x00 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW 0x30 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_1S 0x30 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_2S 0x20 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_3S 0x10 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_4S 0x00 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_ASE BIT3 +#define B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS BIT2 +#define B_PCH_PMC_GEN_PMCON_B_PWR_FLR BIT1 +#define B_PCH_PMC_GEN_PMCON_B_AFTERG3_EN BIT0 +#define R_PCH_PMC_BM_CX_CNF 0xA8 +#define B_PCH_PMC_BM_CX_CNF_STORAGE_BREAK_EN BIT31 +#define B_PCH_PMC_BM_CX_CNF_PCIE_BREAK_EN BIT30 +#define B_PCH_PMC_BM_CX_CNF_AZ_BREAK_EN BIT24 +#define B_PCH_PMC_BM_CX_CNF_DPSN_BREAK_EN BIT19 +#define B_PCH_PMC_BM_CX_CNF_XHCI_BREAK_EN BIT17 +#define B_PCH_PMC_BM_CX_CNF_SATA3_BREAK_EN BIT16 +#define B_PCH_PMC_BM_CX_CNF_SCRATCHPAD BIT15 +#define B_PCH_PMC_BM_CX_CNF_PHOLD_BM_STS_BLOCK BIT14 +#define B_PCH_PMC_BM_CX_CNF_MASK_CF BIT11 +#define B_PCH_PMC_BM_CX_CNF_BM_STS_ZERO_EN BIT10 +#define B_PCH_PMC_BM_CX_CNF_PM_SYNC_MSG_MODE BIT9 +#define R_PCH_PMC_ETR3 0xAC +#define B_PCH_PMC_ETR3_CF9LOCK BIT31 ///< CF9h= Lockdown +#define B_PCH_PMC_ETR3_USB_CACHE_DIS BIT21 +#define B_PCH_PMC_ETR3_CF9GR BIT20 ///< CF9h= Global Reset +#define B_PCH_PMC_ETR3_SKIP_HOST_RST_HS BIT19 +#define B_PCH_PMC_ETR3_CWORWRE BIT18 + +// +// ACPI and legacy I/O register offsets from ACPIBASE +// +#define R_PCH_ACPI_PM1_STS 0x00 +#define S_PCH_ACPI_PM1_STS 2 +#define B_PCH_ACPI_PM1_STS_WAK 0x8000 +#define B_PCH_ACPI_PM1_STS_PRBTNOR 0x0800 +#define B_PCH_ACPI_PM1_STS_RTC 0x0400 +#define B_PCH_ACPI_PM1_STS_PWRBTN 0x0100 +#define B_PCH_ACPI_PM1_STS_GBL 0x0020 +#define B_PCH_ACPI_PM1_STS_BM 0x0010 +#define B_PCH_ACPI_PM1_STS_TMROF 0x0001 +#define N_PCH_ACPI_PM1_STS_WAK 15 +#define N_PCH_ACPI_PM1_STS_PRBTNOR 11 +#define N_PCH_ACPI_PM1_STS_RTC 10 +#define N_PCH_ACPI_PM1_STS_PWRBTN 8 +#define N_PCH_ACPI_PM1_STS_GBL 5 +#define N_PCH_ACPI_PM1_STS_BM 4 +#define N_PCH_ACPI_PM1_STS_TMROF 0 + +#define R_PCH_ACPI_PM1_EN 0x02 +#define S_PCH_ACPI_PM1_EN 2 +#define B_PCH_ACPI_PM1_EN_RTC 0x0400 +#define B_PCH_ACPI_PM1_EN_PWRBTN 0x0100 +#define B_PCH_ACPI_PM1_EN_GBL 0x0020 +#define B_PCH_ACPI_PM1_EN_TMROF 0x0001 +#define N_PCH_ACPI_PM1_EN_RTC 10 +#define N_PCH_ACPI_PM1_EN_PWRBTN 8 +#define N_PCH_ACPI_PM1_EN_GBL 5 +#define N_PCH_ACPI_PM1_EN_TMROF 0 + +#define R_PCH_ACPI_PM1_CNT 0x04 +#define S_PCH_ACPI_PM1_CNT 4 +#define B_PCH_ACPI_PM1_CNT_SLP_EN 0x00002000 +#define B_PCH_ACPI_PM1_CNT_SLP_TYP 0x00001C00 +#define V_PCH_ACPI_PM1_CNT_S0 0x00000000 +#define V_PCH_ACPI_PM1_CNT_S1 0x00000400 +#define V_PCH_ACPI_PM1_CNT_S3 0x00001400 +#define V_PCH_ACPI_PM1_CNT_S4 0x00001800 +#define V_PCH_ACPI_PM1_CNT_S5 0x00001C00 +#define B_PCH_ACPI_PM1_CNT_GBL_RLS 0x00000004 +#define B_PCH_ACPI_PM1_CNT_BM_RLD 0x00000002 +#define B_PCH_ACPI_PM1_CNT_SCI_EN 0x00000001 + +#define R_PCH_ACPI_PM1_TMR 0x08 +#define V_PCH_ACPI_TMR_FREQUENCY 3579545 +#define B_PCH_ACPI_PM1_TMR_VAL 0xFFFFFF +#define V_PCH_ACPI_PM1_TMR_MAX_VAL 0x1000000 ///< The= timer is 24 bit overflow + +#define R_PCH_SMI_EN 0x30 +#define S_PCH_SMI_EN 4 +#define B_PCH_SMI_EN_LEGACY_USB3 BIT31 +#define B_PCH_SMI_EN_GPIO_UNLOCK_SMI BIT27 +#define B_PCH_SMI_EN_LEGACY_USB2 BIT17 +#define B_PCH_SMI_EN_PERIODIC BIT14 +#define B_PCH_SMI_EN_TCO BIT13 +#define B_PCH_SMI_EN_MCSMI BIT11 +#define B_PCH_SMI_EN_BIOS_RLS BIT7 +#define B_PCH_SMI_EN_SWSMI_TMR BIT6 +#define B_PCH_SMI_EN_APMC BIT5 +#define B_PCH_SMI_EN_ON_SLP_EN BIT4 +#define B_PCH_SMI_EN_LEGACY_USB BIT3 +#define B_PCH_SMI_EN_BIOS BIT2 +#define B_PCH_SMI_EN_EOS BIT1 +#define B_PCH_SMI_EN_GBL_SMI BIT0 +#define N_PCH_SMI_EN_LEGACY_USB3 31 +#define N_PCH_SMI_EN_ESPI 28 +#define N_PCH_SMI_EN_GPIO_UNLOCK 27 +#define N_PCH_SMI_EN_INTEL_USB2 18 +#define N_PCH_SMI_EN_LEGACY_USB2 17 +#define N_PCH_SMI_EN_PERIODIC 14 +#define N_PCH_SMI_EN_TCO 13 +#define N_PCH_SMI_EN_MCSMI 11 +#define N_PCH_SMI_EN_BIOS_RLS 7 +#define N_PCH_SMI_EN_SWSMI_TMR 6 +#define N_PCH_SMI_EN_APMC 5 +#define N_PCH_SMI_EN_ON_SLP_EN 4 +#define N_PCH_SMI_EN_LEGACY_USB 3 +#define N_PCH_SMI_EN_BIOS 2 +#define N_PCH_SMI_EN_EOS 1 +#define N_PCH_SMI_EN_GBL_SMI 0 + +#define R_PCH_SMI_STS 0x34 +#define S_PCH_SMI_STS 4 +#define B_PCH_SMI_STS_LEGACY_USB3 BIT31 +#define B_PCH_SMI_STS_GPIO_UNLOCK BIT27 +#define B_PCH_SMI_STS_SPI BIT26 +#define B_PCH_SMI_STS_MONITOR BIT21 +#define B_PCH_SMI_STS_PCI_EXP BIT20 +#define B_PCH_SMI_STS_PATCH BIT19 +#define B_PCH_SMI_STS_INTEL_USB2 BIT18 +#define B_PCH_SMI_STS_LEGACY_USB2 BIT17 +#define B_PCH_SMI_STS_SMBUS BIT16 +#define B_PCH_SMI_STS_SERIRQ BIT15 +#define B_PCH_SMI_STS_PERIODIC BIT14 +#define B_PCH_SMI_STS_TCO BIT13 +#define B_PCH_SMI_STS_DEVMON BIT12 +#define B_PCH_SMI_STS_MCSMI BIT11 +#define B_PCH_SMI_STS_GPIO_SMI BIT10 +#define B_PCH_SMI_STS_GPE0 BIT9 +#define B_PCH_SMI_STS_PM1_STS_REG BIT8 +#define B_PCH_SMI_STS_SWSMI_TMR BIT6 +#define B_PCH_SMI_STS_APM BIT5 +#define B_PCH_SMI_STS_ON_SLP_EN BIT4 +#define B_PCH_SMI_STS_LEGACY_USB BIT3 +#define B_PCH_SMI_STS_BIOS BIT2 +#define N_PCH_SMI_STS_LEGACY_USB3 31 +#define N_PCH_SMI_STS_ESPI 28 +#define N_PCH_SMI_STS_GPIO_UNLOCK 27 +#define N_PCH_SMI_STS_SPI 26 +#define N_PCH_SMI_STS_MONITOR 21 +#define N_PCH_SMI_STS_PCI_EXP 20 +#define N_PCH_SMI_STS_PATCH 19 +#define N_PCH_SMI_STS_INTEL_USB2 18 +#define N_PCH_SMI_STS_LEGACY_USB2 17 +#define N_PCH_SMI_STS_SMBUS 16 +#define N_PCH_SMI_STS_SERIRQ 15 +#define N_PCH_SMI_STS_PERIODIC 14 +#define N_PCH_SMI_STS_TCO 13 +#define N_PCH_SMI_STS_DEVMON 12 +#define N_PCH_SMI_STS_MCSMI 11 +#define N_PCH_SMI_STS_GPIO_SMI 10 +#define N_PCH_SMI_STS_GPE0 9 +#define N_PCH_SMI_STS_PM1_STS_REG 8 +#define N_PCH_SMI_STS_SWSMI_TMR 6 +#define N_PCH_SMI_STS_APM 5 +#define N_PCH_SMI_STS_ON_SLP_EN 4 +#define N_PCH_SMI_STS_LEGACY_USB 3 +#define N_PCH_SMI_STS_BIOS 2 + +#define R_PCH_ACPI_GPE_CNTL 0x40 +#define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL BIT17 + +#define R_PCH_DEVACT_STS 0x44 +#define S_PCH_DEVACT_STS 2 +#define B_PCH_DEVACT_STS_MASK 0x13E1 +#define B_PCH_DEVACT_STS_KBC 0x1000 +#define B_PCH_DEVACT_STS_PIRQDH 0x0200 +#define B_PCH_DEVACT_STS_PIRQCG 0x0100 +#define B_PCH_DEVACT_STS_PIRQBF 0x0080 +#define B_PCH_DEVACT_STS_PIRQAE 0x0040 +#define B_PCH_DEVACT_STS_D0_TRP 0x0001 +#define N_PCH_DEVACT_STS_KBC 12 +#define N_PCH_DEVACT_STS_PIRQDH 9 +#define N_PCH_DEVACT_STS_PIRQCG 8 +#define N_PCH_DEVACT_STS_PIRQBF 7 +#define N_PCH_DEVACT_STS_PIRQAE 6 + +#define R_PCH_ACPI_PM2_CNT 0x50 +#define B_PCH_ACPI_PM2_CNT_ARB_DIS 0x01 + +#define R_PCH_OC_WDT_CTL 0x54 +#define B_PCH_OC_WDT_CTL_RLD BIT31 +#define B_PCH_OC_WDT_CTL_ICCSURV_STS BIT25 +#define B_PCH_OC_WDT_CTL_NO_ICCSURV_STS BIT24 +#define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15 +#define B_PCH_OC_WDT_CTL_EN BIT14 +#define B_PCH_OC_WDT_CTL_ICCSURV BIT13 +#define B_PCH_OC_WDT_CTL_LCK BIT12 +#define B_PCH_OC_WDT_CTL_TOV_MASK 0x3FF +#define B_PCH_OC_WDT_CTL_FAILURE_STS BIT23 +#define B_PCH_OC_WDT_CTL_UNXP_RESET_STS BIT22 +#define B_PCH_OC_WDT_CTL_AFTER_POST 0x3F0000 +#define V_PCH_OC_WDT_CTL_STATUS_FAILURE 1 +#define V_PCH_OC_WDT_CTL_STATUS_OK 0 + +#define R_PCH_ACPI_GPE0_STS_127_96 0x8C +#define S_PCH_ACPI_GPE0_STS_127_96 4 +#define B_PCH_ACPI_GPE0_STS_127_96_WADT BIT18 +#define B_PCH_ACPI_GPE0_STS_127_96_LAN_WAKE BIT16 +#define B_PCH_ACPI_GPE0_STS_127_96_PME_B0 BIT13 +#define B_PCH_ACPI_GPE0_STS_127_96_ME_SCI BIT12 +#define B_PCH_ACPI_GPE0_STS_127_96_PME BIT11 +#define B_PCH_ACPI_GPE0_STS_127_96_BATLOW BIT10 +#define B_PCH_ACPI_GPE0_STS_127_96_PCI_EXP BIT9 +#define B_PCH_ACPI_GPE0_STS_127_96_RI BIT8 +#define B_PCH_ACPI_GPE0_STS_127_96_SMB_WAK BIT7 +#define B_PCH_ACPI_GPE0_STS_127_96_TC0SCI BIT6 +#define B_PCH_ACPI_GPE0_STS_127_96_SWGPE BIT2 +#define B_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG BIT1 +#define N_PCH_ACPI_GPE0_STS_127_96_PME_B0 13 +#define N_PCH_ACPI_GPE0_STS_127_96_PME 11 +#define N_PCH_ACPI_GPE0_STS_127_96_BATLOW 10 +#define N_PCH_ACPI_GPE0_STS_127_96_PCI_EXP 9 +#define N_PCH_ACPI_GPE0_STS_127_96_RI 8 +#define N_PCH_ACPI_GPE0_STS_127_96_SMB_WAK 7 +#define N_PCH_ACPI_GPE0_STS_127_96_TC0SCI 6 +#define N_PCH_ACPI_GPE0_STS_127_96_SWGPE 2 +#define N_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG 1 + +#define R_PCH_ACPI_GPE0_EN_31_0 0x90 +#define R_PCH_ACPI_GPE0_EN_63_31 0x94 +#define R_PCH_ACPI_GPE0_EN_94_64 0x98 +#define R_PCH_ACPI_GPE0_EN_127_96 0x9C +#define S_PCH_ACPI_GPE0_EN_127_96 4 +#define B_PCH_ACPI_GPE0_EN_127_96_WADT BIT18 +#define B_PCH_ACPI_GPE0_EN_127_96_LAN_WAKE BIT16 +#define B_PCH_ACPI_GPE0_EN_127_96_PME_B0 BIT13 +#define B_PCH_ACPI_GPE0_EN_127_96_ME_SCI BIT12 +#define B_PCH_ACPI_GPE0_EN_127_96_PME BIT11 +#define B_PCH_ACPI_GPE0_EN_127_96_BATLOW BIT10 +#define B_PCH_ACPI_GPE0_EN_127_96_PCI_EXP BIT9 +#define B_PCH_ACPI_GPE0_EN_127_96_RI BIT8 +#define B_PCH_ACPI_GPE0_EN_127_96_TC0SCI BIT6 +#define B_PCH_ACPI_GPE0_EN_127_96_SWGPE BIT2 +#define B_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG BIT1 +#define N_PCH_ACPI_GPE0_EN_127_96_PME_B0 13 +#define N_PCH_ACPI_GPE0_EN_127_96_USB3 12 +#define N_PCH_ACPI_GPE0_EN_127_96_PME 11 +#define N_PCH_ACPI_GPE0_EN_127_96_BATLOW 10 +#define N_PCH_ACPI_GPE0_EN_127_96_PCI_EXP 9 +#define N_PCH_ACPI_GPE0_EN_127_96_RI 8 +#define N_PCH_ACPI_GPE0_EN_127_96_TC0SCI 6 +#define N_PCH_ACPI_GPE0_EN_127_96_SWGPE 2 +#define N_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG 1 + + +// +// TCO register I/O map +// +#define R_PCH_TCO_RLD 0x0 +#define R_PCH_TCO_DAT_IN 0x2 +#define R_PCH_TCO_DAT_OUT 0x3 +#define R_PCH_TCO1_STS 0x04 +#define S_PCH_TCO1_STS 2 +#define B_PCH_TCO1_STS_DMISERR BIT12 +#define B_PCH_TCO1_STS_DMISMI BIT10 +#define B_PCH_TCO1_STS_DMISCI BIT9 +#define B_PCH_TCO1_STS_BIOSWR BIT8 +#define B_PCH_TCO1_STS_NEWCENTURY BIT7 +#define B_PCH_TCO1_STS_TIMEOUT BIT3 +#define B_PCH_TCO1_STS_TCO_INT BIT2 +#define B_PCH_TCO1_STS_SW_TCO_SMI BIT1 +#define B_PCH_TCO1_STS_NMI2SMI BIT0 +#define N_PCH_TCO1_STS_DMISMI 10 +#define N_PCH_TCO1_STS_BIOSWR 8 +#define N_PCH_TCO1_STS_NEWCENTURY 7 +#define N_PCH_TCO1_STS_TIMEOUT 3 +#define N_PCH_TCO1_STS_SW_TCO_SMI 1 +#define N_PCH_TCO1_STS_NMI2SMI 0 + +#define R_PCH_TCO2_STS 0x06 +#define S_PCH_TCO2_STS 2 +#define B_PCH_TCO2_STS_SMLINK_SLV_SMI BIT4 +#define B_PCH_TCO2_STS_BAD_BIOS BIT3 +#define B_PCH_TCO2_STS_BOOT BIT2 +#define B_PCH_TCO2_STS_SECOND_TO BIT1 +#define B_PCH_TCO2_STS_INTRD_DET BIT0 +#define N_PCH_TCO2_STS_INTRD_DET 0 + +#define R_PCH_TCO1_CNT 0x08 +#define S_PCH_TCO1_CNT 2 +#define B_PCH_TCO_CNT_LOCK BIT12 +#define B_PCH_TCO_CNT_TMR_HLT BIT11 +#define B_PCH_TCO_CNT_NMI2SMI_EN BIT9 +#define B_PCH_TCO_CNT_NMI_NOW BIT8 +#define N_PCH_TCO_CNT_NMI2SMI_EN 9 + +#define R_PCH_TCO2_CNT 0x0A +#define S_PCH_TCO2_CNT 2 +#define B_PCH_TCO2_CNT_OS_POLICY 0x0030 +#define B_PCH_TCO2_CNT_GPI11_ALERT_DISABLE 0x0008 +#define B_PCH_TCO2_CNT_INTRD_SEL 0x0006 +#define N_PCH_TCO2_CNT_INTRD_SEL 2 + +#define R_PCH_TCO_MESSAGE1 0x0C +#define R_PCH_TCO_MESSAGE2 0x0D +#define R_PCH_TCO_WDCNT 0x0E +#define R_PCH_TCO_SW_IRQ_GEN 0x10 +#define B_PCH_TCO_IRQ12_CAUSE BIT1 +#define B_PCH_TCO_IRQ1_CAUSE BIT0 +#define R_PCH_TCO_TMR 0x12 + +// +// PWRM Registers +// +#define R_PCH_WADT_AC 0x0 = ///< Wake Alarm Device Timer: AC +#define R_PCH_WADT_DC 0x4 = ///< Wake Alarm Device Timer: DC +#define R_PCH_WADT_EXP_AC 0x8 = ///< Wake Alarm Device Expired Timer: AC +#define R_PCH_WADT_EXP_DC 0xC = ///< Wake Alarm Device Expired Timer: DC +#define R_PCH_PWRM_PRSTS 0x10 = ///< Power and Reset Status +#define B_PCH_PWRM_PRSTS_VE_WD_TMR_STS BIT7 = ///< VE Watchdog Timer Status +#define B_PCH_PWRM_PRSTS_WOL_OVR_WK_STS BIT5 +#define B_PCH_PWRM_PRSTS_FIELD_1 BIT4 +#define B_PCH_PWRM_PRSTS_ME_WAKE_STS BIT0 +#define R_PCH_PWRM_14 0x14 +#define R_PCH_PWRM_CFG 0x18 = ///< Power Management Configuration +#define B_PCH_PWRM_CFG_ALLOW_24_OSC_SD BIT29 = ///< Allow 24MHz Crystal Oscillator Shutdown +#define B_PCH_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25 = ///< Allow USB2 Core Power Gating +#define B_PCH_PWRM_CFG_RTC_DS_WAKE_DIS BIT21 = ///< RTC Wake from Deep S4/S5 Disable +#define B_PCH_PWRM_CFG_SSMAW_MASK (BIT19 | BIT18= ) ///< SLP_SUS# Min Assertion Width +#define V_PCH_PWRM_CFG_SSMAW_4S (BIT19 | BIT18= ) ///< 4 seconds +#define V_PCH_PWRM_CFG_SSMAW_1S BIT19 = ///< 1 second +#define V_PCH_PWRM_CFG_SSMAW_0_5S BIT18 = ///< 0.5 second (500ms) +#define V_PCH_PWRM_CFG_SSMAW_0S 0 = ///< 0 second +#define B_PCH_PWRM_CFG_SAMAW_MASK (BIT17 | BIT16= ) ///< SLP_A# Min Assertion Width +#define V_PCH_PWRM_CFG_SAMAW_2S (BIT17 | BIT16= ) ///< 2 seconds +#define V_PCH_PWRM_CFG_SAMAW_98ms BIT17 = ///< 98ms +#define V_PCH_PWRM_CFG_SAMAW_4S BIT16 = ///< 4 seconds +#define V_PCH_PWRM_CFG_SAMAW_0S 0 = ///< 0 second +#define B_PCH_PWRM_CFG_RPCD_MASK (BIT9 | BIT8) = ///< Reset Power Cycle Duration +#define V_PCH_PWRM_CFG_RPCD_1S (BIT9 | BIT8) = ///< 1-2 seconds +#define V_PCH_PWRM_CFG_RPCD_2S BIT9 = ///< 2-3 seconds +#define V_PCH_PWRM_CFG_RPCD_3S BIT8 = ///< 3-4 seconds +#define V_PCH_PWRM_CFG_RPCD_4S 0 = ///< 4-5 seconds (Default) +#define R_PCH_PWRM_MTPMC 0x20 = ///< Message to PMC +#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_0_15 0xE = ///< Command to override lanes 0-15 power gating +#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_16_31 0xF = ///< Command to override lanes 16-31 power gating +#define B_PCH_PWRM_MTPMC_PG_CMD_DATA 0xFFFF0000 = ///< Data part of PowerGate Message to PMC +#define N_PCH_PWRM_MTPMC_PG_CMD_DATA 16 +#define R_PCH_PWRM_S3_PWRGATE_POL 0x28 = ///< S3 Power Gating Policies +#define B_PCH_PWRM_S3DC_GATE_SUS BIT1 = ///< Deep S3 Enable in DC Mode +#define B_PCH_PWRM_S3AC_GATE_SUS BIT0 = ///< Deep S3 Enable in AC Mode +#define R_PCH_PWRM_S4_PWRGATE_POL 0x2C = ///< Deep S4 Power Policies +#define B_PCH_PWRM_S4DC_GATE_SUS BIT1 = ///< Deep S4 Enable in DC Mode +#define B_PCH_PWRM_S4AC_GATE_SUS BIT0 = ///< Deep S4 Enable in AC Mode +#define R_PCH_PWRM_S5_PWRGATE_POL 0x30 = ///< Deep S5 Power Policies +#define B_PCH_PWRM_S5DC_GATE_SUS BIT15 = ///< Deep S5 Enable in DC Mode +#define B_PCH_PWRM_S5AC_GATE_SUS BIT14 = ///< Deep S5 Enable in AC Mode +#define R_PCH_PWRM_DSX_CFG 0x34 = ///< Deep SX Configuration +#define B_PCH_PWRM_DSX_CFG_WAKE_PIN_DSX_EN BIT2 = ///< WAKE# Pin DeepSx Enable +#define B_PCH_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS BIT1 = ///< AC_PRESENT pin pulldown in DeepSx disable +#define B_PCH_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 = ///< LAN_WAKE Pin DeepSx Enable +#define R_PCH_PWRM_CFG2 0x3C = ///< Power Management Configuration Reg 2 +#define B_PCH_PWRM_CFG2_PBOP (BIT31 | BIT30= | BIT29) ///< Power Button Override Period (PBOP) +#define N_PCH_PWRM_CFG2_PBOP 29 = ///< Power Button Override Period (PBOP) +#define B_PCH_PWRM_CFG2_PB_DIS BIT28 = ///< Power Button Native Mode Disable (PB_DIS) +#define B_PCH_PWRM_CFG2_DRAM_RESET_CTL BIT26 = ///< DRAM RESET# control +#define R_PCH_PWRM_EN_SN_SLOW_RING 0x48 = ///< Enable Snoop Request to SLOW_RING +#define R_PCH_PWRM_EN_SN_SLOW_RING2 0x4C = ///< Enable Snoop Request to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_SN_SA 0x50 = ///< Enable Snoop Request to SA +#define R_PCH_PWRM_EN_SN_SA2 0x54 = ///< Enable Snoop Request to SA 2nd Reg +#define R_PCH_PWRM_EN_SN_SLOW_RING_CF 0x58 = ///< Enable Snoop Request to SLOW_RING_CF +#define R_PCH_PWRM_EN_NS_SA 0x68 = ///< Enable Non-Snoop Request to SA +#define R_PCH_PWRM_EN_CW_SLOW_RING 0x80 = ///< Enable Clock Wake to SLOW_RING +#define R_PCH_PWRM_EN_CW_SLOW_RING2 0x84 = ///< Enable Clock Wake to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_CW_SA 0x88 = ///< Enable Clock Wake to SA +#define R_PCH_PWRM_EN_CW_SA2 0x8C = ///< Enable Clock Wake to SA 2nd Reg +#define R_PCH_PWRM_EN_CW_SLOW_RING_CF 0x98 = ///< Enable Clock Wake to SLOW_RING_CF +#define R_PCH_PWRM_EN_PA_SLOW_RING 0xA8 = ///< Enable Pegged Active to SLOW_RING +#define R_PCH_PWRM_EN_PA_SLOW_RING2 0xAC = ///< Enable Pegged Active to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_PA_SA 0xB0 = ///< Enable Pegged Active to SA +#define R_PCH_PWRM_EN_PA_SA2 0xB4 = ///< Enable Pegged Active to SA 2nd Reg +#define R_PCH_PWRM_EN_MISC_EVENT 0xC0 = ///< Enable Misc PM_SYNC Events +#define R_PCH_PWRM_PMSYNC_TPR_CONFIG 0xC4 +#define B_PCH_PWRM_PMSYNC_TPR_CONFIG_LOCK BIT31 +#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_EN BIT26 +#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 | BIT24) +#define N_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE 24 +#define V_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE_1 1 +#define R_PCH_PWRM_PMSYNC_MISC_CFG 0xC8 +#define B_PCH_PWRM_PMSYNC_PM_SYNC_LOCK BIT15 = ///< PM_SYNC Configuration Lock +#define B_PCH_PWRM_PMSYNC_GPIO_D_SEL BIT11 +#define B_PCH_PWRM_PMSYNC_GPIO_C_SEL BIT10 +#define PM_SYNC_GPIO_B 0 +#define R_PCH_PWRM_PM_SYNC_STATE_HYS 0xD0 = ///< PM_SYNC State Hysteresis +#define R_PCH_PWRM_PM_SYNC_MODE 0xD4 = ///< PM_SYNC Pin Mode +#define R_PCH_PWRM_CFG3 0xE0 = ///< Power Management Configuration Reg 3 +#define B_PCH_PWRM_CFG3_DSX_WLAN_PP_EN BIT16 = ///< Deep-Sx WLAN Phy Power Enable +#define B_PCH_PWRM_CFG3_HOST_WLAN_PP_EN BIT17 = ///< Host Wireless LAN Phy Power Enable +#define B_PCH_PWRM_CFG3_PWRG_LOCK BIT2 = ///< Lock power gating override messages +#define R_PCH_PWRM_PM_DOWN_PPB_CFG 0xE4 = ///< PM_DOWN PCH_POWER_BUDGET CONFIGURATION +#define R_PCH_PWRM_CFG4 0xE8 = ///< Power Management Configuration Reg 4 +#define B_PCH_PWRM_CFG4_U2_PHY_PG_EN BIT30 = ///< USB2 PHY SUS Well Power Gating Enable +#define B_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR (0x000001FF) = ///< CPU I/O VR Ramp Duration, [8:0] +#define N_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR 0 +#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_70US 0x007 +#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_240US 0x018 +#define R_PCH_PWRM_CPU_EPOC 0xEC +#define R_PCH_PWRM_VR_MISC_CTL 0x100 +#define B_PCH_PWRM_VR_MISC_CTL_VIDSOVEN BIT3 +#define R_PCH_PWRM_GPIO_CFG 0x120 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10= | BIT9 | BIT8) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW2 8 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 |= BIT5 | BIT4) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW1 4 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 |= BIT1 | BIT0) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW0 0 +#define R_PCH_PWRM_PM_SYNC_MODE_C0 0xF4 = ///< PM_SYNC Pin Mode in C0 +#define R_PCH_PWRM_124 0x124 +#define R_PCH_PWRM_HPR_CAUSE0 0x12C ///< = Host partition reset causes +#define B_PCH_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15 ///< = Global reset converted to host reset +#define R_PCH_PWRM_MODPHY_PM_CFG1 0x200 +#define R_PCH_PWRM_MODPHY_PM_CFG2 0x204 ///< = ModPHY Power Management Configuration Reg 2 +#define B_PCH_PWRM_MODPHY_PM_CFG2_MLSPDDGE BIT30 ///< = ModPHY Lane SUS Power Domain Dynamic Gating Enable +#define B_PCH_PWRM_MODPHY_PM_CFG2_EMFC BIT29 ///< = Enable ModPHY FET Control +#define B_PCH_PWRM_MODPHY_PM_CFG2_EFRT (BIT28 | BIT27= | BIT26 | BIT25 | BIT24) ///< External FET Ramp Time +#define N_PCH_PWRM_MODPHY_PM_CFG2_EFRT 24 +#define V_PCH_PWRM_MODPHY_PM_CFG2_EFRT_200US 0x0A +#define B_PCH_PWRM_MODPHY_PM_CFG2_ASLOR_UFS BIT16 ///< = UFS ModPHY SPD SPD Override +#define R_PCH_PWRM_MODPHY_PM_CFG3 0x208 ///< = ModPHY Power Management Configuration Reg 3 +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_UFS BIT16 ///< = UFS ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XDCI BIT15 ///< = xDCI ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XHCI BIT14 ///< = xHCI ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_GBE BIT13 ///< = GbE ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_SATA BIT12 ///< = SATA ModPHY SPD RT Request +#define R_PCH_PWRM_30C 0x30C +#define R_PCH_PWRM_OBFF_CFG 0x314 = ///< OBFF Configuration +#define R_PCH_PWRM_31C 0x31C +#define R_PCH_PWRM_CPPM_MISC_CFG 0x320 = ///< CPPM Miscellaneous Configuration +#define R_PCH_PWRM_CPPM_CG_POL1A 0x324 = ///< CPPM Clock Gating Policy Reg 1 +#define R_PCH_PWRM_CPPM_CG_POL2A 0x340 = ///< CPPM Clock Gating Policy Reg 3 +#define R_PCH_PWRM_34C 0x34C +#define R_PCH_PWRM_CPPM_CG_POL3A 0x3A8 = ///< CPPM Clock Gating Policy Reg 5 +#define B_PCH_PWRM_CPPM_CG_POLXA_CPPM_GX_QUAL BIT30 = ///< CPPM Shutdown Qualifier Enable for Clock Source Group X +#define B_PCH_PWRM_CPPM_CG_POLXA_LTR_GX_THRESH (0x000001FF) = ///< LTR Threshold for Clock Source Group X, [8:0] +#define R_PCH_PWRM_3D0 0x3D0 +#define R_PCH_PWRM_CPPM_MPG_POL1A 0x3E0 = ///< CPPM ModPHY Gating Policy Reg 1A +#define B_PCH_PWRM_CPPM_MPG_POL1A_CPPM_MODPHY_QUAL BIT30 = ///< CPPM Shutdown Qualifier Enable for ModPHY +#define B_PCH_PWRM_CPPM_MPG_POL1A_LT_MODPHY_SEL BIT29 = ///< ASLT/PLT Selection for ModPHY +#define B_PCH_PWRM_CPPM_MPG_POL1A_LTR_MODPHY_THRESH (0x000001FF) = ///< LTR Threshold for ModPHY, [8:0] +#define R_PCH_PWRM_CS_SD_CTL1 0x3E8 = ///< Clock Source Shutdown Control Reg 1 +#define B_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG (BIT22 | BIT21= | BIT20) ///< Clock Source 5 Control Configuration +#define N_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG 20 +#define B_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG (BIT2 | BIT1 |= BIT0) ///< Clock Source 1 Control Configuration +#define N_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG 0 +#define R_PCH_PWRM_CS_SD_CTL2 0x3EC = ///< Clock Source Shutdown Control Reg 2 +#define R_PCH_PWRM_HSWPGCR1 0x5D0 +#define B_PCH_PWRM_SW_PG_CTRL_LOCK BIT31 +#define B_PCH_PWRM_DFX_SW_PG_CTRL BIT0 +#define R_PCH_PWRM_600 0x600 +#define R_PCH_PWRM_604 0x604 +#define R_PCH_PWRM_ST_PG_FDIS_PMC_1 0x620 ///< Sta= tic PG Related Function Disable Register 1 +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Sta= tic Function Disable Lock (ST_FDIS_LK) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_CAM_FDIS_PMC BIT6 ///< Cam= era Function Disable (PMC Version) (CAM_FDIS_PMC) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ISH_FDIS_PMC BIT5 ///< SH = Function Disable (PMC Version) (ISH_FDIS_PMC) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_GBE_FDIS_PMC BIT0 ///< GBE= Function Disable (PMC Version) (GBE_FDIS_PMC) +#define R_PCH_PWRM_ST_PG_FDIS_PMC_2 0x624 ///< Sta= tic Function Disable Control Register 2 +#define V_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_FDIS_PMC 0x7FF ///< Sta= tic Function Disable Control Register 2 +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI1_FDIS_PMC BIT10 ///< Ser= ialIo Controller GSPI Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI0_FDIS_PMC BIT9 ///< Ser= ialIo Controller GSPI Device 0 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART2_FDIS_PMC BIT8 ///< Ser= ialIo Controller UART Device 2 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART1_FDIS_PMC BIT7 ///< Ser= ialIo Controller UART Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART0_FDIS_PMC BIT6 ///< Ser= ialIo Controller UART Device 0 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C5_FDIS_PMC BIT5 ///< Ser= ialIo Controller I2C Device 5 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC BIT4 ///< Ser= ialIo Controller I2C Device 4 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C3_FDIS_PMC BIT3 ///< Ser= ialIo Controller I2C Device 3 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C2_FDIS_PMC BIT2 ///< Ser= ialIo Controller I2C Device 2 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C1_FDIS_PMC BIT1 ///< Ser= ialIo Controller I2C Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C0_FDIS_PMC BIT0 ///< Ser= ialIo Controller I2C Device 0 Function Disable +#define R_PCH_PWRM_NST_PG_FDIS_1 0x628 +#define B_PCH_PWRM_NST_PG_FDIS_1_SCC_FDIS_PMC BIT25 ///< SCC= Function Disable. This is only avaiable in B0 onward. +#define B_PCH_PWRM_NST_PG_FDIS_1_XDCI_FDIS_PMC BIT24 ///< XDC= I Function Disable. This is only avaiable in B0 onward. +#define B_PCH_PWRM_NST_PG_FDIS_1_ADSP_FDIS_PMC BIT23 ///< ADS= P Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_SATA_FDIS_PMC BIT22 ///< SAT= A Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C3_FDIS_PMC BIT13 ///< PCI= e Controller C Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C2_FDIS_PMC BIT12 ///< PCI= e Controller C Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C1_FDIS_PMC BIT11 ///< PCI= e Controller C Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C0_FDIS_PMC BIT10 ///< PCI= e Controller C Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B3_FDIS_PMC BIT9 ///< PCI= e Controller B Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B2_FDIS_PMC BIT8 ///< PCI= e Controller B Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B1_FDIS_PMC BIT7 ///< PCI= e Controller B Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B0_FDIS_PMC BIT6 ///< PCI= e Controller B Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A3_FDIS_PMC BIT5 ///< PCI= e Controller A Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4 ///< PCI= e Controller A Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A1_FDIS_PMC BIT3 ///< PCI= e Controller A Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A0_FDIS_PMC BIT2 ///< PCI= e Controller A Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_XHCI_FDIS_PMC BIT0 ///< XHC= I Function Disable +#define R_PCH_PWRM_FUSE_DIS_RD_1 0x640 ///< Fus= e Disable Read 1 Register +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E3_FUSE_DIS BIT21 ///< PCI= e Controller E Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E2_FUSE_DIS BIT20 ///< PCI= e Controller E Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E1_FUSE_DIS BIT19 ///< PCI= e Controller E Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E0_FUSE_DIS BIT18 ///< PCI= e Controller E Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D3_FUSE_DIS BIT17 ///< PCI= e Controller D Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D2_FUSE_DIS BIT16 ///< PCI= e Controller D Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D1_FUSE_DIS BIT15 ///< PCI= e Controller D Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D0_FUSE_DIS BIT14 ///< PCI= e Controller D Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C3_FUSE_DIS BIT13 ///< PCI= e Controller C Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C2_FUSE_DIS BIT12 ///< PCI= e Controller C Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C1_FUSE_DIS BIT11 ///< PCI= e Controller C Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C0_FUSE_DIS BIT10 ///< PCI= e Controller C Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B3_FUSE_DIS BIT9 ///< PCI= e Controller B Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B2_FUSE_DIS BIT8 ///< PCI= e Controller B Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B1_FUSE_DIS BIT7 ///< PCI= e Controller B Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B0_FUSE_DIS BIT6 ///< PCI= e Controller B Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A3_FUSE_DIS BIT5 ///< PCI= e Controller A Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A2_FUSE_DIS BIT4 ///< PCI= e Controller A Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A1_FUSE_DIS BIT3 ///< PCI= e Controller A Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A0_FUSE_DIS BIT2 ///< PCI= e Controller A Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_XHCI_FUSE_DIS BIT0 ///< XHC= I Fuse Disable +#define R_PCH_PWRM_FUSE_DIS_RD_2 0x644 ///< Fus= e Disable Read 2 Register +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///< SPC= Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPB_SS_DIS BIT24 ///< SPB= Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPA_SS_DIS BIT23 ///< SPA= Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_PSTH_FUSE_SS_DIS BIT21 ///< PST= H Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_DMI_FUSE_SS_DIS BIT20 ///< DMI= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19 ///< OTG= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_XHCI_SS_DIS BIT18 ///< XHC= I Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_FIA_FUSE_SS_DIS BIT17 ///< FIA= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_DSP_FUSE_SS_DIS BIT16 ///< DSP= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15 ///< SAT= A Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ICC_FUSE_SS_DIS BIT14 ///< ICC= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_LPC_FUSE_SS_DIS BIT13 ///< LPC= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_RTC_FUSE_SS_DIS BIT12 ///< RTC= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_P2S_FUSE_SS_DIS BIT11 ///< P2S= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_TRSB_FUSE_SS_DIS BIT10 ///< TRS= B Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SMB_FUSE_SS_DIS BIT9 ///< SMB= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ITSS_FUSE_SS_DIS BIT8 ///< ITS= S Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS BIT6 ///< Ser= ialIo Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SCC_FUSE_SS_DIS BIT4 ///< SCC= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_P2D_FUSE_SS_DIS BIT3 ///< P2D= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_CAM_FUSE_SS_DIS BIT2 ///< Cam= era Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ISH_FUSE_SS_DIS BIT1 ///< ISH= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE= Fuse or Soft Strap Disable +#define R_PCH_PWRM_FUSE_DIS_RD_3 0x648 ///< Sta= tic PG Fuse and Soft Strap Disable Read Register 3 +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA3_FUSE_SS_DIS BIT3 ///< PNC= RA3 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA2_FUSE_SS_DIS BIT2 ///< PNC= RA2 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA1_FUSE_SS_DIS BIT1 ///< PNC= RA1 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA_FUSE_SS_DIS BIT0 ///< PNC= RA Fuse or Soft Strap Disable + + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsPsf.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsPsf.h new file mode 100644 index 0000000000..0eb61aa0b7 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPsf= .h @@ -0,0 +1,210 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_PSF_H_ +#define _PCH_REGS_PSF_H_ + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI p= rogramming as well. +// + +// +// PSFx segment registers +// +#define R_PCH_PCR_PSF_GLOBAL_CONFIG 0x4000 = ///< PSF Segment Global Configuration Register +#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENTCG BIT4 +#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENLCG BIT3 +#define R_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0 0x4014 = ///< PSF Segment Rootspace Configuration Register +#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0_ENADDRP2P BIT1 +#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0_VTDEN BIT0 +#define R_PCH_PCR_PSF_PORT_CONFIG_PG0_PORT0 0x4020 = ///< PSF Segment Port Configuration Register + +#define S_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR 4 +#define S_PCH_PSF_TARGET_GNTCNT_RELOAD 4 +#define B_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR_GNT_CNT_RELOAD 0x1F +#define B_PCH_PSF_TARGET_GNTCNT_RELOAD_GNT_CNT_RELOAD 0x1F + +// +// PSFx PCRs definitions +// +#define R_PCH_PCR_PSFX_T0_SHDW_BAR0 0 = ///< PCI BAR0 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR1 0x04 = ///< PCI BAR1 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR2 0x08 = ///< PCI BAR2 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR3 0x0C = ///< PCI BAR3 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR4 0x10 = ///< PCI BAR4 +#define R_PCH_PCR_PSFX_T0_SHDW_PCIEN 0x1C = ///< PCI configuration space enable bits +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR0DIS BIT16 = ///< Disable BAR0 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR1DIS BIT17 = ///< Disable BAR1 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR2DIS BIT18 = ///< Disable BAR2 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR3DIS BIT19 = ///< Disable BAR3 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR4DIS BIT20 = ///< Disable BAR4 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR5DIS BIT21 = ///< Disable BAR5 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS BIT8 = ///< Function disable +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_MEMEN BIT1 = ///< Memory decoding enable +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_IOEN BIT0 = ///< IO decoding enable +#define R_PCH_PCR_PSFX_T0_SHDW_PMCSR 0x20 = ///< PCI power management configuration +#define B_PCH_PCR_PSFX_T0_SHDW_PMCSR_PWRST (BIT1 | BIT0) = ///< Power status +#define R_PCH_PCR_PSFX_T0_SHDW_CFG_DIS 0x38 = ///< PCI configuration disable +#define B_PCH_PCR_PSFX_T0_SHDW_CFG_DIS_CFGDIS BIT0 = ///< config disable + +#define R_PCH_PCR_PSFX_T1_SHDW_PCIEN 0x3C = ///< PCI configuration space enable bits +#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_FUNDIS BIT8 = ///< Function disable +#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_MEMEN BIT1 = ///< Memory decoding enable +#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_IOEN BIT0 = ///< IO decoding enable + +#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 0x01F0 = ///< device number +#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 4 +#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION (BIT3 | BI= T2 | BIT1) ///< function number +#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION 1 + +#define V_PCH_LP_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38A00 +#define V_PCH_H_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38B00 + +// +// PSF1 PCRs +// +// PSF1 PCH-LP Specific Base Address +#define R_PCH_LP_PCR_PSF1_T0_SHDW_GBE_REG_BASE 0x0200 = ///< D31F6 PSF base address (GBE) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CAM_REG_BASE 0x0300 = ///< D20F3 PSF base address (CAM) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0500 = ///< D22F7 PSF base address (CSME: WLAN) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0700 = ///< D22F4 PSF base address (CSME: HECI3) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0800 = ///< D22F1 PSF base address (CSME: HECI2) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0900 = ///< D18F3 PSF base address (CSME: CSE UMA) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0A00 = ///< D22F0 PSF base address (CSME: HECI1) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0B00 = ///< D22F3 PSF base address (CSME: KT) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0C00 = ///< D22F2 PSF base address (CSME: IDER) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CLINK_REG_BASE 0x0D00 = ///< D18F1 PSF base address (CSME: CLINK) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_PMT_REG_BASE 0x0E00 = ///< D18F2 PSF base address (CSME: PMT) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_KVM_REG_BASE 0x0F00 = ///< D18F0 PSF base address (CSME: KVM) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_SATA_REG_BASE 0x1000 = ///< PCH-LP D23F0 PSF base address (SATA) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2000 = ///< PCH-LP D29F3 PSF base address (PCIE PORT 12) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2100 = ///< PCH-LP D29F2 PSF base address (PCIE PORT 11) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2200 = ///< PCH-LP D29F1 PSF base address (PCIE PORT 10) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2300 = ///< PCH-LP D29F0 PSF base address (PCIE PORT 09) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2400 = ///< PCH-LP D28F7 PSF base address (PCIE PORT 08) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2500 = ///< PCH-LP D28F6 PSF base address (PCIE PORT 07) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2600 = ///< PCH-LP D28F5 PSF base address (PCIE PORT 06) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2700 = ///< PCH-LP D28F4 PSF base address (PCIE PORT 05) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x2800 = ///< PCH-LP D28F3 PSF base address (PCIE PORT 04) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x2900 = ///< PCH-LP D28F2 PSF base address (PCIE PORT 03) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x2A00 = ///< PCH-LP D28F1 PSF base address (PCIE PORT 02) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x2B00 = ///< PCH-LP D28F0 PSF base address (PCIE PORT 01) + +// PSF1 PCH-H Specific Base Address +#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0200 = ///< D22F7 PSF base address (CSME: WLAN) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0300 = ///< SPT-H D22F4 PSF base address (CSME: HECI3) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0400 = ///< SPT-H D22F1 PSF base address (CSME: HECI2) +#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0500 = ///< D18F3 PSF base address (CSME: CSE UMA) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0600 = ///< SPT-H D22F0 PSF base address (CSME: HECI1) +#define R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0700 = ///< SPT-H D22F3 PSF base address (CSME: KT) +#define R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0800 = ///< SPT-H D22F2 PSF base address (CSME: IDER) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE20_REG_BASE 0x2000 = ///< PCH-H D27F3 PSF base address (PCIE PORT 20) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE19_REG_BASE 0x2100 = ///< PCH-H D27F2 PSF base address (PCIE PORT 19) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE18_REG_BASE 0x2200 = ///< PCH-H D27F1 PSF base address (PCIE PORT 18) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE17_REG_BASE 0x2300 = ///< PCH-H D27F0 PSF base address (PCIE PORT 17) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE16_REG_BASE 0x2400 = ///< PCH-H D29F7 PSF base address (PCIE PORT 16) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE15_REG_BASE 0x2500 = ///< PCH-H D29F6 PSF base address (PCIE PORT 15) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE14_REG_BASE 0x2600 = ///< PCH-H D29F5 PSF base address (PCIE PORT 14) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE13_REG_BASE 0x2700 = ///< PCH-H D29F4 PSF base address (PCIE PORT 13) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2800 = ///< PCH-H D29F3 PSF base address (PCIE PORT 10) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2900 = ///< PCH-H D29F2 PSF base address (PCIE PORT 11) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2A00 = ///< PCH-H D29F1 PSF base address (PCIE PORT 10) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2B00 = ///< PCH-H D29F0 PSF base address (PCIE PORT 09) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2C00 = ///< PCH-H D28F7 PSF base address (PCIE PORT 08) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2D00 = ///< PCH-H D28F6 PSF base address (PCIE PORT 07) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2E00 = ///< PCH-H D28F5 PSF base address (PCIE PORT 06) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2F00 = ///< PCH-H D28F4 PSF base address (PCIE PORT 05) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x3000 = ///< PCH-H D28F3 PSF base address (PCIE PORT 04) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x3100 = ///< PCH-H D28F2 PSF base address (PCIE PORT 03) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x3200 = ///< PCH-H D28F1 PSF base address (PCIE PORT 02) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x3300 = ///< PCH-H D28F0 PSF base address (PCIE PORT 01) + +// Other PSF1 PCRs definition +#define R_PCH_LP_PCR_PSF1_PSF_PORT_CONFIG_PG1_PORT7 0x403C= ///< PSF Port Configuration Register +#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST0_EOI 0x4050= ///< Multicast Control Register +#define R_PCH_LP_PCR_PSF1_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4060= ///< Destination ID + + +//PSF 1 Multicast Message Configuration + +#define R_PCH_PCR_PSF1_RC_OWNER_RS0 = 0x4008 ///< Destination ID + +#define B_PCH_PCR_PSF1_TARGET_CHANNELID = 0xFF +#define B_PCH_PCR_PSF1_TARGET_PORTID = 0x7F00 +#define N_PCH_PCR_PSF1_TARGET_PORTID = 8 +#define B_PCH_PCR_PSF1_TARGET_PORTGROUPID = BIT15 +#define N_PCH_PCR_PSF1_TARGET_PORTGROUPID = 15 +#define B_PCH_PCR_PSF1_TARGET_PSFID = 0xFF0000 +#define N_PCH_PCR_PSF1_TARGET_PSFID = 16 +#define B_PCH_PCR_PSF1_TARGET_CHANMAP = BIT31 + +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_CHANNELID = 0 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTID = 10 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTGROUPID_DOWNSTREAM = 1 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PMT = 0 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PSF1 = 1 + +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_UPST= REAM 0 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_DOWN= STREAM 1 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PSFID_PSF1 = 1 + +#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 = 0x4058 ///< Multicast Control Register + +#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_MULTCEN = BIT0 +#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC = 0xFE +#define N_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC = 1 + +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_CHANNELID_DMI = 0 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTID_DMI = 0 + + + +// +// controls the PCI configuration header of a PCI function +// +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F0 0x4198 /= //< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F1 0x419C /= //< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F2 0x41A0 /= //< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F3 0x41A4 /= //< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F4 0x41A8 /= //< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F5 0x41AC /= //< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F6 0x41B0 /= //< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F7 0x41B4 /= //< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F0 0x41B8 /= //< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F1 0x41BC /= //< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F2 0x41C0 /= //< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F3 0x41C4 /= //< SPC + + +// +// PSF1 grant count registers +// +#define R_PCH_LP_PSF1_DEV_GNTCNT_RELOAD_DGCR0 0x41CC +#define R_PCH_LP_PSF1_TARGET_GNTCNT_RELOAD_PG1_TGT0 0x45D0 + + +// +// PSF2 PCRs (PID:PSF2) +// +#define R_PCH_PCR_PSF2_T0_SHDW_TRH_REG_BASE 0x0100 = ///< D20F2 PSF base address (Thermal). // LP&H +// PSF2 PCH-LP Specific Base Address +#define R_PCH_LP_PCR_PSF2_T0_SHDW_UFS_REG_BASE 0x0200 = ///< D30F7 PSF base address (SCC: UFS) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDCARD_REG_BASE 0x0300 = ///< D30F6 PSF base address (SCC: SDCard) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDIO_REG_BASE 0x0400 = ///< D30F5 PSF base address (SCC: SDIO) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_EMMC_REG_BASE 0x0500 = ///< D30F4 PSF base address (SCC: eMMC) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0600 = ///< D20F1 PSF base address (USB device controller: OTG) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0700 = ///< D20F0 PSF base address (XHCI) +// PSF2 PCH-H Specific Base Address +#define R_PCH_H_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0200 = ///< D20F1 PSF base address (USB device controller: OTG) +#define R_PCH_H_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0300 = ///< D20F0 PSF base address (XHCI) + +// +// PSF3 PCRs (PID:PSF3) +// + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsPsth.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsPsth.h new file mode 100644 index 0000000000..6669cc2bb9 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPst= h.h @@ -0,0 +1,46 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_PSTH_H_ +#define _PCH_REGS_PSTH_H_ + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI p= rogramming as well. +// + +// +// PSTH and IO Trap PCRs (PID:PSTH) +// +#define R_PCH_PCR_PSTH_PSTHCTL 0x1D00 ///< PSTH co= ntrol register +#define B_PCH_PCR_PSTH_PSTHIOSFPTCGE BIT2 ///< PSTH IO= SF primary trunk clock gating enable +#define B_PCH_PCR_PSTH_PSTHIOSFSTCGE BIT1 ///< PSTH IO= SF sideband trunk clock gating enable +#define B_PCH_PCR_PSTH_PSTHDCGE BIT0 ///< PSTH dy= namic clock gating enable +#define R_PCH_PCR_PSTH_TRPST 0x1E00 ///< Trap st= atus regsiter +#define B_PCH_PCR_PSTH_TRPST_CTSS 0x0000000F ///< Cycle T= rap SMI# Status mask +#define R_PCH_PCR_PSTH_TRPC 0x1E10 ///< Trapped= cycle +#define B_PCH_PCR_PSTH_TRPC_RW BIT24 ///< Read/Wr= ite#: 1=3DRead, 0=3DWrite +#define B_PCH_PCR_PSTH_TRPC_AHBE 0x00000000000F0000 ///< Active = high byte enables +#define B_PCH_PCR_PSTH_TRPC_IOA 0x000000000000FFFC ///< Trap cy= cle I/O address +#define R_PCH_PCR_PSTH_TRPD 0x1E18 ///< Trapped= write data +#define B_PCH_PCR_PSTH_TRPD_IOD 0x00000000FFFFFFFF ///< Trap cy= cle I/O data +#define R_PCH_PCR_PSTH_TRPREG0 0x1E80 ///< IO Tarp= 0 register +#define R_PCH_PCR_PSTH_TRPREG1 0x1E88 ///< IO Tarp= 1 register +#define R_PCH_PCR_PSTH_TRPREG2 0x1E90 ///< IO Tarp= 2 register +#define R_PCH_PCR_PSTH_TRPREG3 0x1E98 ///< IO Tarp= 3 register +#define B_PCH_PCR_PSTH_TRPREG_RWM BIT17 ///< 49 - 32= for 32 bit access, Read/Write mask +#define B_PCH_PCR_PSTH_TRPREG_RWIO BIT16 ///< 48 - 32= for 32 bit access, Read/Write#, 1=3DRead, 0=3DWrite +#define N_PCH_PCR_PSTH_TRPREG_RWIO 16 ///< 48 - 32= for 32 bit access, 16bit shift for Read/Write field +#define N_PCH_PCR_PSTH_TRPREG_BEM (36 - 32) +#define B_PCH_PCR_PSTH_TRPREG_BEM 0x000000F000000000 ///< Byte en= able mask +#define B_PCH_PCR_PSTH_TRPREG_BE 0x0000000F00000000 ///< Byte en= able +#define B_PCH_PCR_PSTH_TRPREG_AM 0x0000000000FC0000 ///< IO Addr= ess mask +#define B_PCH_PCR_PSTH_TRPREG_AD 0x000000000000FFFC ///< IO Addr= ess +#define B_PCH_PCR_PSTH_TRPREG_TSE BIT0 ///< Trap an= d SMI# Enable + + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsSata.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsSata.h new file mode 100644 index 0000000000..7d91f19dbc --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSat= a.h @@ -0,0 +1,634 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_SATA_H_ +#define _PCH_REGS_SATA_H_ + +// +// SATA Controller Registers (D23:F0) +// +#define PCI_DEVICE_NUMBER_PCH_SATA 23 +#define PCI_FUNCTION_NUMBER_PCH_SATA 0 +#define V_PCH_SATA_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +#define PCH_SATA_FIRST_CONTROLLER 1 +#define PCH_SATA_SECOND_CONTROLLER 2 + +// +// SKL PCH-LP SATA Device ID's +// +#define V_PCH_LP_SATA_DEVICE_ID_M_AHCI 0x9D03 ///< SATA Controlle= r (AHCI) - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID 0x9D05 ///< SATA Controlle= r (RAID 0/1/5/10) - NOT premium - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_ALTDIS 0x282A ///< SATA Controlle= r (RAID 0/1/5/10) - NOT premium - Mobile - Alternate ID +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_PREM 0x9D07 ///< SATA Controlle= r (RAID 0/1/5/10) - premium - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_RRT 0x9D0F ///< SATA Controlle= r (RAID 1/RRT Only) - Mobile + +// +// SKL PCH-H SATA Device ID's +// +#define V_PCH_H_SATA_DEVICE_ID_D_AHCI 0xA102 ///< SATA Controlle= r (AHCI) +#define V_PCH_H_SATA_DEVICE_ID_D_AHCI_A0 0xA103 ///< SATA Controlle= r (AHCI) - SPTH A0 +#define V_PCH_H_SATA_DEVICE_ID_D_RAID 0xA105 ///< SATA Controlle= r (RAID 0/1/5/10) - NOT premium +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_ALTDIS 0x2822 ///< SATA Controlle= r (RAID 0/1/5/10) - premium - Alternate ID +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_RSTE 0x2826 ///< SATA Controlle= r (RAID 0/1/5/10) - RSTe of Server SKU +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_PREM 0xA107 ///< SATA Controlle= r (RAID 0/1/5/10) - premium +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_RRT 0xA10F ///< SATA Controlle= r (RAID 1/RRT Only) + + +// +// LBG PRODUCTION INCLUDING QUAL SAMPLES SATA Device ID's +// +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_AHCI 0xA182 ///= < Server AHCI Mode (Ports 0-5) +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID 0xA184 ///= < Server RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID_PREMIUM 0xA186 ///= < Server RAID 0/1/5/10 - premium +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID1 0xA18E ///= < Server RAID 1/RRT Only + +// +// LBG SSX (Super SKUs and Pre Production) SATA Device ID's +// +#define V_PCH_LBG_SATA_DEVICE_ID_D_AHCI 0xA202 ///< Server= AHCI Mode (Ports 0-5) +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID 0xA204 ///< Server= RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM 0xA206 ///< Server= RAID 0/1/5/10 - premium +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID1 0xA20E ///< Server= RAID 1/RRT Only + +// +// LBG Alternate RST Device IDs +// +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0 0x2822 ///< Ser= ver RAID 0/1/5/10 - premium - Alternate ID for RST +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1 0x2826 ///< Ser= ver RAID 0/1/5/10 - premium - Alternate ID for RSTe + +// +// SATA Controller common Registers +// +#define V_PCH_SATA_SUB_CLASS_CODE_AHCI 0x06 +#define V_PCH_SATA_SUB_CLASS_CODE_RAID 0x04 +#define R_PCH_SATA_AHCI_BAR 0x24 +#define B_PCH_SATA_AHCI_BAR_BA 0xFFFFF800 +#define V_PCH_SATA_AHCI_BAR_LENGTH 0x800 +#define N_PCH_SATA_AHCI_BAR_ALIGNMENT 11 +#define V_PCH_SATA_AHCI_BAR_LENGTH_512K 0x80000 +#define N_PCH_SATA_AHCI_BAR_ALIGNMENT_512K 19 +#define B_PCH_SATA_AHCI_BAR_PF BIT3 +#define B_PCH_SATA_AHCI_BAR_TP (BIT2 | BIT1) +#define B_PCH_SATA_AHCI_BAR_RTE BIT0 +#define R_PCH_SATA_PID 0x70 +#define B_PCH_SATA_PID_NEXT 0xFF00 +#define V_PCH_SATA_PID_NEXT_0 0xB000 +#define V_PCH_SATA_PID_NEXT_1 0xA800 +#define B_PCH_SATA_PID_CID 0x00FF +#define R_PCH_SATA_PC 0x72 +#define S_PCH_SATA_PC 2 +#define B_PCH_SATA_PC_PME (BIT15 | BIT14 | BIT13 | BIT12= | BIT11) +#define V_PCH_SATA_PC_PME_0 0x0000 +#define V_PCH_SATA_PC_PME_1 0x4000 +#define B_PCH_SATA_PC_D2_SUP BIT10 +#define B_PCH_SATA_PC_D1_SUP BIT9 +#define B_PCH_SATA_PC_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_PCH_SATA_PC_DSI BIT5 +#define B_PCH_SATA_PC_PME_CLK BIT3 +#define B_PCH_SATA_PC_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_SATA_PMCS 0x74 +#define B_PCH_SATA_PMCS_PMES BIT15 +#define B_PCH_SATA_PMCS_PMEE BIT8 +#define B_PCH_SATA_PMCS_NSFRST BIT3 +#define V_PCH_SATA_PMCS_NSFRST_1 0x01 +#define V_PCH_SATA_PMCS_NSFRST_0 0x00 +#define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) +#define V_PCH_SATA_PMCS_PS_3 0x03 +#define V_PCH_SATA_PMCS_PS_0 0x00 +#define R_PCH_SATA_MID 0x80 +#define B_PCH_SATA_MID_NEXT 0xFF00 +#define B_PCH_SATA_MID_CID 0x00FF +#define R_PCH_SATA_MC 0x82 +#define B_PCH_SATA_MC_C64 BIT7 +#define B_PCH_SATA_MC_MME (BIT6 | BIT5 | BIT4) +#define V_PCH_SATA_MC_MME_4 0x04 +#define V_PCH_SATA_MC_MME_2 0x02 +#define V_PCH_SATA_MC_MME_1 0x01 +#define V_PCH_SATA_MC_MME_0 0x00 +#define B_PCH_SATA_MC_MMC (BIT3 | BIT2 | BIT1) +#define V_PCH_SATA_MC_MMC_4 0x04 +#define V_PCH_SATA_MC_MMC_0 0x00 +#define B_PCH_SATA_MC_MSIE BIT0 +#define V_PCH_SATA_MC_MSIE_1 0x01 +#define V_PCH_SATA_MC_MSIE_0 0x00 +#define R_PCH_SATA_MA 0x84 +#define B_PCH_SATA_MA 0xFFFFFFFC +#define R_PCH_SATA_MD 0x88 +#define B_PCH_SATA_MD_MSIMD 0xFFFF + +// +// Sata Register for PCH-LP +// +#define R_PCH_LP_SATA_MAP 0x90 +#define B_PCH_LP_SATA_MAP_SPD (BIT10 | BIT9 | BIT8) +#define N_PCH_LP_SATA_MAP_SPD 8 +#define B_PCH_LP_SATA_MAP_SPD2 BIT10 +#define B_PCH_LP_SATA_MAP_SPD1 BIT9 +#define B_PCH_LP_SATA_MAP_SPD0 BIT8 +#define B_PCH_LP_SATA_MAP_SMS_MASK BIT6 +#define N_PCH_LP_SATA_MAP_SMS_MASK 6 +#define V_PCH_LP_SATA_MAP_SMS_AHCI 0x0 +#define V_PCH_LP_SATA_MAP_SMS_RAID 0x1 +#define R_PCH_LP_SATA_PCS 0x92 +#define B_PCH_LP_SATA_PCS_OOB_RETRY BIT15 +#define B_PCH_LP_SATA_PCS_P2P BIT10 +#define B_PCH_LP_SATA_PCS_P1P BIT9 +#define B_PCH_LP_SATA_PCS_P0P BIT8 +#define B_PCH_LP_SATA_PCS_PXE_MASK (BIT2 | BIT1 | BIT0) +#define B_PCH_LP_SATA_PCS_P2E BIT2 +#define B_PCH_LP_SATA_PCS_P1E BIT1 +#define B_PCH_LP_SATA_PCS_P0E BIT0 +#define R_PCH_LP_SATA_SCLKGC 0x94 +#define B_PCH_LP_SATA_SCLKGC_PCD (BIT26 | BIT25 | BIT24) +#define B_PCH_LP_SATA_SCLKGC_PORT2_PCD BIT26 +#define B_PCH_LP_SATA_SCLKGC_PORT1_PCD BIT25 +#define B_PCH_LP_SATA_SCLKGC_PORT0_PCD BIT24 +#define R_PCH_LP_SATA_98 0x98 + +// +// Sata Register for PCH-H +// +#define R_PCH_H_SATA_MAP 0x90 +#define B_PCH_H_SATA_MAP_SPD 0xFF0000 +#define N_PCH_H_SATA_MAP_SPD 16 +#define B_PCH_H_SATA_MAP_SPD7 BIT23 +#define B_PCH_H_SATA_MAP_SPD6 BIT22 +#define B_PCH_H_SATA_MAP_SPD5 BIT21 +#define B_PCH_H_SATA_MAP_SPD4 BIT20 +#define B_PCH_H_SATA_MAP_SPD3 BIT19 +#define B_PCH_H_SATA_MAP_SPD2 BIT18 +#define B_PCH_H_SATA_MAP_SPD1 BIT17 +#define B_PCH_H_SATA_MAP_SPD0 BIT16 +#define B_PCH_H_SATA_MAP_PCD 0xFF +#define B_PCH_H_SATA_MAP_PORT7_PCD BIT7 +#define B_PCH_H_SATA_MAP_PORT6_PCD BIT6 +#define B_PCH_H_SATA_MAP_PORT5_PCD BIT5 +#define B_PCH_H_SATA_MAP_PORT4_PCD BIT4 +#define B_PCH_H_SATA_MAP_PORT3_PCD BIT3 +#define B_PCH_H_SATA_MAP_PORT2_PCD BIT2 +#define B_PCH_H_SATA_MAP_PORT1_PCD BIT1 +#define B_PCH_H_SATA_MAP_PORT0_PCD BIT0 +#define R_PCH_H_SATA_PCS 0x94 +#define B_PCH_H_SATA_PCS_P7P BIT23 +#define B_PCH_H_SATA_PCS_P6P BIT22 +#define B_PCH_H_SATA_PCS_P5P BIT21 +#define B_PCH_H_SATA_PCS_P4P BIT20 +#define B_PCH_H_SATA_PCS_P3P BIT19 +#define B_PCH_H_SATA_PCS_P2P BIT18 +#define B_PCH_H_SATA_PCS_P1P BIT17 +#define B_PCH_H_SATA_PCS_P0P BIT16 +#define B_PCH_H_SATA_PCS_PXE_MASK 0xFF +#define B_PCH_H_SATA_PCS_P7E BIT7 +#define B_PCH_H_SATA_PCS_P6E BIT6 +#define B_PCH_H_SATA_PCS_P5E BIT5 +#define B_PCH_H_SATA_PCS_P4E BIT4 +#define B_PCH_H_SATA_PCS_P3E BIT3 +#define B_PCH_H_SATA_PCS_P2E BIT2 +#define B_PCH_H_SATA_PCS_P1E BIT1 +#define B_PCH_H_SATA_PCS_P0E BIT0 + +#define R_PCH_SATA_SATAGC 0x9C +#define B_PCH_H_SATA_SATAGC_SMS_MASK BIT16 +#define N_PCH_H_SATA_SATAGC_SMS_MASK 16 +#define V_PCH_H_SATA_SATAGC_SMS_AHCI 0x0 +#define V_PCH_H_SATA_SATAGC_SMS_RAID 0x1 +#define B_PCH_SATA_SATAGC_AIE BIT7 +#define B_PCH_SATA_SATAGC_AIES BIT6 +#define B_PCH_SATA_SATAGC_MSS (BIT4 | BIT3) +#define V_PCH_SATA_SATAGC_MSS_8K 0x2 +#define N_PCH_SATA_SATAGC_MSS 3 +#define B_PCH_SATA_SATAGC_ASSEL (BIT2 | BIT1 | BIT0) + +#define V_PCH_SATA_SATAGC_ASSEL_2K 0x0 +#define V_PCH_SATA_SATAGC_ASSEL_16K 0x1 +#define V_PCH_SATA_SATAGC_ASSEL_32K 0x2 +#define V_PCH_SATA_SATAGC_ASSEL_64K 0x3 +#define V_PCH_SATA_SATAGC_ASSEL_128K 0x4 +#define V_PCH_SATA_SATAGC_ASSEL_256K 0x5 +#define V_PCH_SATA_SATAGC_ASSEL_512K 0x6 + +#define R_PCH_SATA_SIRI 0xA0 +#define R_PCH_SATA_STRD 0xA4 +#define R_PCH_SATA_SIR_50 0x50 +#define R_PCH_SATA_SIR_54 0x54 +#define R_PCH_SATA_SIR_58 0x58 +#define R_PCH_SATA_SIR_5C 0x5C +#define R_PCH_SATA_SIR_60 0x60 +#define R_PCH_SATA_SIR_64 0x64 +#define R_PCH_SATA_SIR_68 0x68 +#define R_PCH_SATA_SIR_6C 0x6C +#define R_PCH_SATA_SIR_70 0x70 +#define R_PCH_SATA_SIR_80 0x80 +#define R_PCH_SATA_SIR_84 0x84 +#define R_PCH_SATA_SIR_8C 0x8C +#define R_PCH_SATA_SIR_90 0x90 +#define R_PCH_SATA_SIR_98 0x98 +#define R_PCH_SATA_SIR_9C 0x9C +#define R_PCH_SATA_SIR_A0 0xA0 +#define R_PCH_SATA_SIR_A4 0xA4 +#define R_PCH_SATA_SIR_A8 0xA8 +#define R_PCH_SATA_SIR_C8 0xC8 +#define R_PCH_SATA_SIR_CC 0xCC +#define R_PCH_SATA_SIR_D0 0xD0 +#define R_PCH_SATA_SIR_D4 0xD4 +#define B_PCH_SATA_STRD_DTA 0xFFFFFFFF +#define R_PCH_SATA_CR0 0xA8 +#define B_PCH_SATA_CR0_MAJREV 0x00F00000 +#define B_PCH_SATA_CR0_MINREV 0x000F0000 +#define B_PCH_SATA_CR0_NEXT 0x0000FF00 +#define B_PCH_SATA_CR0_CAP 0x000000FF +#define R_PCH_SATA_CR1 0xAC +#define B_PCH_SATA_CR1_BAROFST 0xFFF0 +#define B_PCH_SATA_CR1_BARLOC 0x000F +#define R_PCH_SATA_FLR_CID 0xB0 +#define B_PCH_SATA_FLR_CID_NEXT 0xFF00 +#define B_PCH_SATA_FLR_CID 0x00FF +#define V_PCH_SATA_FLR_CID_1 0x0009 +#define V_PCH_SATA_FLR_CID_0 0x0013 +#define R_PCH_SATA_FLR_CLV 0xB2 +#define B_PCH_SATA_FLR_CLV_FLRC_FLRCSSEL_0 BIT9 +#define B_PCH_SATA_FLR_CLV_TXPC_FLRCSSEL_0 BIT8 +#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_0 0x00FF +#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_1 0x00FF +#define V_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL 0x0006 +#define R_PCH_SATA_FLRC 0xB4 +#define B_PCH_SATA_FLRC_TXP BIT8 +#define B_PCH_SATA_FLRC_INITFLR BIT0 +#define R_PCH_SATA_SP 0xC0 +#define B_PCH_SATA_SP 0xFFFFFFFF +#define R_PCH_SATA_MXID 0xD0 +#define N_PCH_SATA_MXID_NEXT 8 + +#define R_PCH_SATA_BFCS 0xE0 +#define B_PCH_SATA_BFCS_P7BFI BIT17 +#define B_PCH_SATA_BFCS_P6BFI BIT16 +#define B_PCH_SATA_BFCS_P5BFI BIT15 +#define B_PCH_SATA_BFCS_P4BFI BIT14 +#define B_PCH_SATA_BFCS_P3BFI BIT13 +#define B_PCH_SATA_BFCS_P2BFI BIT12 +#define B_PCH_SATA_BFCS_P2BFS BIT11 +#define B_PCH_SATA_BFCS_P2BFF BIT10 +#define B_PCH_SATA_BFCS_P1BFI BIT9 +#define B_PCH_SATA_BFCS_P0BFI BIT8 +#define B_PCH_SATA_BFCS_BIST_FIS_T BIT7 +#define B_PCH_SATA_BFCS_BIST_FIS_A BIT6 +#define B_PCH_SATA_BFCS_BIST_FIS_S BIT5 +#define B_PCH_SATA_BFCS_BIST_FIS_L BIT4 +#define B_PCH_SATA_BFCS_BIST_FIS_F BIT3 +#define B_PCH_SATA_BFCS_BIST_FIS_P BIT2 +#define R_PCH_SATA_BFTD1 0xE4 +#define B_PCH_SATA_BFTD1 0xFFFFFFFF +#define R_PCH_SATA_BFTD2 0xE8 +#define B_PCH_SATA_BFTD2 0xFFFFFFFF + +#define R_PCH_SATA_VS_CAP 0xA4 +#define B_PCH_SATA_VS_CAP_NRMBE BIT0 = ///< NVM Remap Memory BAR Enable +#define B_PCH_SATA_VS_CAP_MSL 0x1FFE = ///< Memory Space Limit +#define N_PCH_SATA_VS_CAP_MSL 1 +#define V_PCH_SATA_VS_CAP_MSL 0x1EF = ///< Memory Space Limit Field Value +#define B_PCH_SATA_VS_CAP_NRMO 0xFFF0000 = ///< NVM Remapped Memory Offset +#define N_PCH_SATA_VS_CAP_NRMO 16 +#define V_PCH_SATA_VS_CAP_NRMO 0x10 = ///< NVM Remapped Memory Offset Field Value + +// +// RST PCIe Storage Remapping Registers +// +#define R_PCH_RST_PCIE_STORAGE_RCR 0x800 = ///< Remap Capability Register +#define B_PCH_RST_PCIE_STORAGE_RCR_NRS (BIT2|BIT1|BIT0) = ///< Number of Remapping Supported +#define B_PCH_RST_PCIE_STORAGE_RCR_NRS_CR1 BIT0 = ///< Number of Remapping Supported (RST PCIe Storage Cycle Router = #1) +#define R_PCH_RST_PCIE_STORAGE_SPR 0x80C = ///< Scratch Pad Register +#define R_PCH_RST_PCIE_STORAGE_CR1_DCC 0x880 = ///< CR#1 Device Class Code +#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_SCC 8 +#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_BCC 16 +#define B_PCH_RST_PCIE_STORAGE_CR1_DCC_DT BIT31 = ///< Device Type +#define V_PCH_RST_PCIE_STORAGE_REMAP_CONFIG_CR 0x80 = ///< Remapped Configuration for RST PCIe Storage Cycle Router #n +#define V_PCH_RST_PCIE_STORAGE_REMAP_RP_OFFSET 0x100 = ///< Remapped Root Port Offset Value +#define R_PCH_RST_PCIE_STORAGE_CCFG 0x1D0 = ///< Port Configuration Register + +// +// AHCI BAR Area related Registers +// +#define R_PCH_SATA_AHCI_CAP 0x0 +#define B_PCH_SATA_AHCI_CAP_S64A BIT31 +#define B_PCH_SATA_AHCI_CAP_SCQA BIT30 +#define B_PCH_SATA_AHCI_CAP_SSNTF BIT29 +#define B_PCH_SATA_AHCI_CAP_SIS BIT28 ///< Supports Interlock = Switch +#define B_PCH_SATA_AHCI_CAP_SSS BIT27 ///< Supports Stagger Sp= in-up +#define B_PCH_SATA_AHCI_CAP_SALP BIT26 +#define B_PCH_SATA_AHCI_CAP_SAL BIT25 +#define B_PCH_SATA_AHCI_CAP_SCLO BIT24 ///< Supports Command Li= st Override +#define B_PCH_SATA_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 | BIT20) +#define N_PCH_SATA_AHCI_CAP_ISS 20 ///< Interface Speed Sup= port +#define V_PCH_SATA_AHCI_CAP_ISS_1_5_G 0x01 +#define V_PCH_SATA_AHCI_CAP_ISS_3_0_G 0x02 +#define V_PCH_SATA_AHCI_CAP_ISS_6_0_G 0x03 +#define B_PCH_SATA_AHCI_CAP_SNZO BIT19 +#define B_PCH_SATA_AHCI_CAP_SAM BIT18 +#define B_PCH_SATA_AHCI_CAP_PMS BIT17 ///< Supports Port Multi= plier +#define B_PCH_SATA_AHCI_CAP_PMD BIT15 ///< PIO Multiple DRQ Bl= ock +#define B_PCH_SATA_AHCI_CAP_SSC BIT14 +#define B_PCH_SATA_AHCI_CAP_PSC BIT13 +#define B_PCH_SATA_AHCI_CAP_NCS 0x1F00 +#define B_PCH_SATA_AHCI_CAP_CCCS BIT7 +#define B_PCH_SATA_AHCI_CAP_EMS BIT6 +#define B_PCH_SATA_AHCI_CAP_SXS BIT5 ///< External SATA is su= pported +#define B_PCH_SATA_AHCI_CAP_NPS 0x001F + +#define R_PCH_SATA_AHCI_GHC 0x04 +#define B_PCH_SATA_AHCI_GHC_AE BIT31 +#define B_PCH_SATA_AHCI_GHC_MRSM BIT2 +#define B_PCH_SATA_AHCI_GHC_IE BIT1 +#define B_PCH_SATA_AHCI_GHC_HR BIT0 + +#define R_PCH_SATA_AHCI_IS 0x08 +#define B_PCH_SATA_AHCI_IS_PORT7 BIT7 +#define B_PCH_SATA_AHCI_IS_PORT6 BIT6 +#define B_PCH_SATA_AHCI_IS_PORT5 BIT5 +#define B_PCH_SATA_AHCI_IS_PORT4 BIT4 +#define B_PCH_SATA_AHCI_IS_PORT3 BIT3 +#define B_PCH_SATA_AHCI_IS_PORT2 BIT2 +#define B_PCH_SATA_AHCI_IS_PORT1 BIT1 +#define B_PCH_SATA_AHCI_IS_PORT0 BIT0 +#define R_PCH_SATA_AHCI_PI 0x0C +#define B_PCH_H_SATA_PORT_MASK 0xFF +#define B_PCH_LP_SATA_PORT_MASK 0x03 +#define B_PCH_SATA_PORT7_IMPLEMENTED BIT7 +#define B_PCH_SATA_PORT6_IMPLEMENTED BIT6 +#define B_PCH_SATA_PORT5_IMPLEMENTED BIT5 +#define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 +#define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 +#define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 +#define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 +#define B_PCH_SATA_PORT0_IMPLEMENTED BIT0 +#define R_PCH_SATA_AHCI_VS 0x10 +#define B_PCH_SATA_AHCI_VS_MJR 0xFFFF0000 +#define B_PCH_SATA_AHCI_VS_MNR 0x0000FFFF +#define R_PCH_SATA_AHCI_EM_LOC 0x1C +#define B_PCH_SATA_AHCI_EM_LOC_OFST 0xFFFF0000 +#define B_PCH_SATA_AHCI_EM_LOC_SZ 0x0000FFFF +#define R_PCH_SATA_AHCI_EM_CTRL 0x20 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_ALHD BIT26 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_XMT BIT25 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_SMB BIT24 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SGPIO BIT19 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SES2 BIT18 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SAFTE BIT17 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_LED BIT16 +#define B_PCH_SATA_AHCI_EM_CTRL_RST BIT9 +#define B_PCH_SATA_AHCI_EM_CTRL_CTL_TM BIT8 +#define B_PCH_SATA_AHCI_EM_CTRL_STS_MR BIT0 +#define R_PCH_SATA_AHCI_CAP2 0x24 +#define B_PCH_SATA_AHCI_CAP2_DESO BIT5 +#define B_PCH_SATA_AHCI_CAP2_SADM BIT4 +#define B_PCH_SATA_AHCI_CAP2_SDS BIT3 +#define B_PCH_SATA_AHCI_CAP2_APST BIT2 ///< Automatic Partial t= o Slumber Transitions +#define R_PCH_SATA_AHCI_VSP 0xA0 +#define B_PCH_SATA_AHCI_VSP_SLPD BIT0 +#define R_PCH_SATA_AHCI_RSTF 0xC8 ///< RST Feature Capabil= ities +#define B_PCH_SATA_AHCI_RSTF_OUD (BIT11 | BIT10) +#define N_PCH_SATA_AHCI_RSTF_OUD 10 +#define B_PCH_SATA_AHCI_RSTF_SEREQ BIT9 +#define B_PCH_SATA_AHCI_RSTF_IROES BIT8 +#define B_PCH_SATA_AHCI_RSTF_LEDL BIT7 +#define B_PCH_SATA_AHCI_RSTF_HDDLK BIT6 +#define B_PCH_SATA_AHCI_RSTF_IRSTOROM BIT5 +#define B_PCH_SATA_AHCI_RSTF_RSTE BIT4 +#define B_PCH_SATA_AHCI_RSTF_R5E BIT3 +#define B_PCH_SATA_AHCI_RSTF_R10E BIT2 +#define B_PCH_SATA_AHCI_RSTF_R1E BIT1 +#define B_PCH_SATA_AHCI_RSTF_R0E BIT0 +#define B_PCH_SATA_AHCI_RSTF_LOWBYTES 0x1FF +#define R_PCH_SATA_AHCI_P0CLB 0x100 +#define R_PCH_SATA_AHCI_P1CLB 0x180 +#define R_PCH_SATA_AHCI_P2CLB 0x200 +#define R_PCH_SATA_AHCI_P3CLB 0x280 +#define R_PCH_SATA_AHCI_P4CLB 0x300 +#define R_PCH_SATA_AHCI_P5CLB 0x380 +#define R_PCH_SATA_AHCI_P6CLB 0x400 +#define R_PCH_SATA_AHCI_P7CLB 0x480 +#define B_PCH_SATA_AHCI_PXCLB 0xFFFFFC00 +#define R_PCH_SATA_AHCI_P0CLBU 0x104 +#define R_PCH_SATA_AHCI_P1CLBU 0x184 +#define R_PCH_SATA_AHCI_P2CLBU 0x204 +#define R_PCH_SATA_AHCI_P3CLBU 0x284 +#define R_PCH_SATA_AHCI_P4CLBU 0x304 +#define R_PCH_SATA_AHCI_P5CLBU 0x384 +#define R_PCH_SATA_AHCI_P6CLBU 0x404 +#define R_PCH_SATA_AHCI_P7CLBU 0x484 +#define B_PCH_SATA_AHCI_PXCLBU 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0FB 0x108 +#define R_PCH_SATA_AHCI_P1FB 0x188 +#define R_PCH_SATA_AHCI_P2FB 0x208 +#define R_PCH_SATA_AHCI_P3FB 0x288 +#define R_PCH_SATA_AHCI_P4FB 0x308 +#define R_PCH_SATA_AHCI_P5FB 0x388 +#define R_PCH_SATA_AHCI_P6FB 0x408 +#define R_PCH_SATA_AHCI_P7FB 0x488 +#define B_PCH_SATA_AHCI_PXFB 0xFFFFFF00 +#define R_PCH_SATA_AHCI_P0FBU 0x10C +#define R_PCH_SATA_AHCI_P1FBU 0x18C +#define R_PCH_SATA_AHCI_P2FBU 0x20C +#define R_PCH_SATA_AHCI_P3FBU 0x28C +#define R_PCH_SATA_AHCI_P4FBU 0x30C +#define R_PCH_SATA_AHCI_P5FBU 0x38C +#define R_PCH_SATA_AHCI_P6FBU 0x40C +#define R_PCH_SATA_AHCI_P7FBU 0x48C +#define B_PCH_SATA_AHCI_PXFBU 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0IS 0x110 +#define R_PCH_SATA_AHCI_P1IS 0x190 +#define R_PCH_SATA_AHCI_P2IS 0x210 +#define R_PCH_SATA_AHCI_P3IS 0x290 +#define R_PCH_SATA_AHCI_P4IS 0x310 +#define R_PCH_SATA_AHCI_P5IS 0x390 +#define R_PCH_SATA_AHCI_P6IS 0x410 +#define R_PCH_SATA_AHCI_P7IS 0x490 +#define B_PCH_SATA_AHCI_PXIS_CPDS BIT31 +#define B_PCH_SATA_AHCI_PXIS_TFES BIT30 +#define B_PCH_SATA_AHCI_PXIS_HBFS BIT29 +#define B_PCH_SATA_AHCI_PXIS_HBDS BIT28 +#define B_PCH_SATA_AHCI_PXIS_IFS BIT27 +#define B_PCH_SATA_AHCI_PXIS_INFS BIT26 +#define B_PCH_SATA_AHCI_PXIS_OFS BIT24 +#define B_PCH_SATA_AHCI_PXIS_IPMS BIT23 +#define B_PCH_SATA_AHCI_PXIS_PRCS BIT22 +#define B_PCH_SATA_AHCI_PXIS_DIS BIT7 +#define B_PCH_SATA_AHCI_PXIS_PCS BIT6 +#define B_PCH_SATA_AHCI_PXIS_DPS BIT5 +#define B_PCH_SATA_AHCI_PXIS_UFS BIT4 +#define B_PCH_SATA_AHCI_PXIS_SDBS BIT3 +#define B_PCH_SATA_AHCI_PXIS_DSS BIT2 +#define B_PCH_SATA_AHCI_PXIS_PSS BIT1 +#define B_PCH_SATA_AHCI_PXIS_DHRS BIT0 +#define R_PCH_SATA_AHCI_P0IE 0x114 +#define R_PCH_SATA_AHCI_P1IE 0x194 +#define R_PCH_SATA_AHCI_P2IE 0x214 +#define R_PCH_SATA_AHCI_P3IE 0x294 +#define R_PCH_SATA_AHCI_P4IE 0x314 +#define R_PCH_SATA_AHCI_P5IE 0x394 +#define R_PCH_SATA_AHCI_P6IE 0x414 +#define R_PCH_SATA_AHCI_P7IE 0x494 +#define B_PCH_SATA_AHCI_PXIE_CPDE BIT31 +#define B_PCH_SATA_AHCI_PXIE_TFEE BIT30 +#define B_PCH_SATA_AHCI_PXIE_HBFE BIT29 +#define B_PCH_SATA_AHCI_PXIE_HBDE BIT28 +#define B_PCH_SATA_AHCI_PXIE_IFE BIT27 +#define B_PCH_SATA_AHCI_PXIE_INFE BIT26 +#define B_PCH_SATA_AHCI_PXIE_OFE BIT24 +#define B_PCH_SATA_AHCI_PXIE_IPME BIT23 +#define B_PCH_SATA_AHCI_PXIE_PRCE BIT22 +#define B_PCH_SATA_AHCI_PXIE_DIE BIT7 +#define B_PCH_SATA_AHCI_PXIE_PCE BIT6 +#define B_PCH_SATA_AHCI_PXIE_DPE BIT5 +#define B_PCH_SATA_AHCI_PXIE_UFIE BIT4 +#define B_PCH_SATA_AHCI_PXIE_SDBE BIT3 +#define B_PCH_SATA_AHCI_PXIE_DSE BIT2 +#define B_PCH_SATA_AHCI_PXIE_PSE BIT1 +#define B_PCH_SATA_AHCI_PXIE_DHRE BIT0 +#define R_PCH_SATA_AHCI_P0CMD 0x118 +#define R_PCH_SATA_AHCI_P1CMD 0x198 +#define R_PCH_SATA_AHCI_P2CMD 0x218 +#define R_PCH_SATA_AHCI_P3CMD 0x298 +#define R_PCH_SATA_AHCI_P4CMD 0x318 +#define R_PCH_SATA_AHCI_P5CMD 0x398 +#define R_PCH_SATA_AHCI_P6CMD 0x418 +#define R_PCH_SATA_AHCI_P7CMD 0x498 +#define B_PCH_SATA_AHCI_PxCMD_ICC (BIT31 | BIT30 | BIT29 | BIT28) +#define B_PCH_SATA_AHCI_PxCMD_MASK (BIT27 | BIT26 | BIT22 | BIT21= | BIT19 | BIT18) +#define B_PCH_SATA_AHCI_PxCMD_ASP BIT27 +#define B_PCH_SATA_AHCI_PxCMD_ALPE BIT26 +#define B_PCH_SATA_AHCI_PxCMD_DLAE BIT25 +#define B_PCH_SATA_AHCI_PxCMD_ATAPI BIT24 +#define B_PCH_SATA_AHCI_PxCMD_APSTE BIT23 +#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1 +#define R_PCH_SATA_AHCI_P0DEVSLP 0x144 +#define R_PCH_SATA_AHCI_P1DEVSLP 0x1C4 +#define R_PCH_SATA_AHCI_P2DEVSLP 0x244 +#define R_PCH_SATA_AHCI_P3DEVSLP 0x2C4 +#define R_PCH_SATA_AHCI_P4DEVSLP 0x344 +#define R_PCH_SATA_AHCI_P5DEVSLP 0x3C4 +#define R_PCH_SATA_AHCI_P6DEVSLP 0x444 +#define R_PCH_SATA_AHCI_P7DEVSLP 0x4C4 +#define B_PCH_SATA_AHCI_PxDEVSLP_DSP BIT1 +#define B_PCH_SATA_AHCI_PxDEVSLP_ADSE BIT0 +#define B_PCH_SATA_AHCI_PxDEVSLP_DITO_MASK 0x01FF8000 +#define V_PCH_SATA_AHCI_PxDEVSLP_DITO_625 0x01388000 +#define B_PCH_SATA_AHCI_PxDEVSLP_DM_MASK 0x1E000000 +#define V_PCH_SATA_AHCI_PxDEVSLP_DM_16 0x1E000000 +#define B_PCH_SATA_AHCI_PxCMD_ESP BIT21 ///< Used with an extern= al SATA device +#define B_PCH_SATA_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Switch A= ttached to Port +#define B_PCH_SATA_AHCI_PxCMD_HPCP BIT18 ///< Hotplug capable +#define B_PCH_SATA_AHCI_PxCMD_CR BIT15 +#define B_PCH_SATA_AHCI_PxCMD_FR BIT14 +#define B_PCH_SATA_AHCI_PxCMD_ISS BIT13 +#define B_PCH_SATA_AHCI_PxCMD_CCS 0x00001F00 +#define B_PCH_SATA_AHCI_PxCMD_FRE BIT4 +#define B_PCH_SATA_AHCI_PxCMD_CLO BIT3 +#define B_PCH_SATA_AHCI_PxCMD_POD BIT2 +#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1 +#define B_PCH_SATA_AHCI_PxCMD_ST BIT0 +#define R_PCH_SATA_AHCI_P0TFD 0x120 +#define R_PCH_SATA_AHCI_P1TFD 0x1A0 +#define R_PCH_SATA_AHCI_P2TFD 0x220 +#define R_PCH_SATA_AHCI_P3TFD 0x2A0 +#define R_PCH_SATA_AHCI_P4TFD 0x320 +#define R_PCH_SATA_AHCI_P5TFD 0x3A0 +#define R_PCH_SATA_AHCI_P6TFD 0x420 +#define B_PCH_SATA_AHCI_PXTFD_ERR 0x0000FF00 +#define B_PCH_SATA_AHCI_PXTFD_STS 0x000000FF +#define R_PCH_SATA_AHCI_P0SIG 0x124 +#define R_PCH_SATA_AHCI_P1SIG 0x1A4 +#define R_PCH_SATA_AHCI_P2SIG 0x224 +#define R_PCH_SATA_AHCI_P3SIG 0x2A4 +#define R_PCH_SATA_AHCI_P4SIG 0x324 +#define R_PCH_SATA_AHCI_P5SIG 0x3A4 +#define R_PCH_SATA_AHCI_P6SIG 0x424 +#define B_PCH_SATA_AHCI_PXSIG_LBA_HR 0xFF000000 +#define B_PCH_SATA_AHCI_PXSIG_LBA_MR 0x00FF0000 +#define B_PCH_SATA_AHCI_PXSIG_LBA_LR 0x0000FF00 +#define B_PCH_SATA_AHCI_PXSIG_SCR 0x000000FF +#define R_PCH_SATA_AHCI_P0SSTS 0x128 +#define R_PCH_SATA_AHCI_P1SSTS 0x1A8 +#define R_PCH_SATA_AHCI_P2SSTS 0x228 +#define R_PCH_SATA_AHCI_P3SSTS 0x2A8 +#define R_PCH_SATA_AHCI_P4SSTS 0x328 +#define R_PCH_SATA_AHCI_P5SSTS 0x3A8 +#define R_PCH_SATA_AHCI_P6SSTS 0x428 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030 +#define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001 +#define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003 +#define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004 +#define R_PCH_SATA_AHCI_P0SCTL 0x12C +#define R_PCH_SATA_AHCI_P1SCTL 0x1AC +#define R_PCH_SATA_AHCI_P2SCTL 0x22C +#define R_PCH_SATA_AHCI_P3SCTL 0x2AC +#define R_PCH_SATA_AHCI_P4SCTL 0x32C +#define R_PCH_SATA_AHCI_P5SCTL 0x3AC +#define R_PCH_SATA_AHCI_P6SCTL 0x42C +#define B_PCH_SATA_AHCI_PXSCTL_IPM 0x00000F00 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_1 0x00000100 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_2 0x00000200 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_3 0x00000300 +#define B_PCH_SATA_AHCI_PXSCTL_SPD 0x000000F0 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_1 0x00000010 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_2 0x00000020 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_3 0x00000030 +#define B_PCH_SATA_AHCI_PXSCTL_DET 0x0000000F +#define V_PCH_SATA_AHCI_PXSCTL_DET_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_DET_1 0x00000001 +#define V_PCH_SATA_AHCI_PXSCTL_DET_4 0x00000004 +#define R_PCH_SATA_AHCI_P0SERR 0x130 +#define R_PCH_SATA_AHCI_P1SERR 0x1B0 +#define R_PCH_SATA_AHCI_P2SERR 0x230 +#define R_PCH_SATA_AHCI_P3SERR 0x2B0 +#define R_PCH_SATA_AHCI_P4SERR 0x330 +#define R_PCH_SATA_AHCI_P5SERR 0x3B0 +#define R_PCH_SATA_AHCI_P6SERR 0x430 +#define B_PCH_SATA_AHCI_PXSERR_EXCHG BIT26 +#define B_PCH_SATA_AHCI_PXSERR_UN_FIS_TYPE BIT25 +#define B_PCH_SATA_AHCI_PXSERR_TRSTE_24 BIT24 +#define B_PCH_SATA_AHCI_PXSERR_TRSTE_23 BIT23 +#define B_PCH_SATA_AHCI_PXSERR_HANDSHAKE BIT22 +#define B_PCH_SATA_AHCI_PXSERR_CRC_ERROR BIT21 +#define B_PCH_SATA_AHCI_PXSERR_10B8B_DECERR BIT19 +#define B_PCH_SATA_AHCI_PXSERR_COMM_WAKE BIT18 +#define B_PCH_SATA_AHCI_PXSERR_PHY_ERROR BIT17 +#define B_PCH_SATA_AHCI_PXSERR_PHY_RDY_CHG BIT16 +#define B_PCH_SATA_AHCI_PXSERR_INTRNAL_ERR BIT11 +#define B_PCH_SATA_AHCI_PXSERR_PROTOCOL_ERR BIT10 +#define B_PCH_SATA_AHCI_PXSERR_PCDIE BIT9 +#define B_PCH_SATA_AHCI_PXSERR_TDIE BIT8 +#define B_PCH_SATA_AHCI_PXSERR_RCE BIT1 +#define B_PCH_SATA_AHCI_PXSERR_RDIE BIT0 +#define R_PCH_SATA_AHCI_P0SACT 0x134 +#define R_PCH_SATA_AHCI_P1SACT 0x1B4 +#define R_PCH_SATA_AHCI_P2SACT 0x234 +#define R_PCH_SATA_AHCI_P3SACT 0x2B4 +#define R_PCH_SATA_AHCI_P4SACT 0x334 +#define R_PCH_SATA_AHCI_P5SACT 0x3B4 +#define R_PCH_SATA_AHCI_P6SACT 0x434 +#define B_PCH_SATA_AHCI_PXSACT_DS 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0CI 0x138 +#define R_PCH_SATA_AHCI_P1CI 0x1B8 +#define R_PCH_SATA_AHCI_P2CI 0x238 +#define R_PCH_SATA_AHCI_P3CI 0x2B8 +#define R_PCH_SATA_AHCI_P4CI 0x338 +#define R_PCH_SATA_AHCI_P5CI 0x3B8 +#define R_PCH_SATA_AHCI_P6CI 0x438 +#define B_PCH_SATA_AHCI_PXCI 0xFFFFFFFF + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsScs.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsScs.h new file mode 100644 index 0000000000..9684a6d259 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsScs= .h @@ -0,0 +1,152 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_SCS_H_ +#define _PCH_REGS_SCS_H_ + +// +// SCS Devices PCI Config Space Registers +// +#define R_PCH_SCS_DEV_PCS 0x84 = ///< PME Control Status +#define B_PCH_SCS_DEV_PCS_PMESTS BIT15 = ///< PME Status +#define B_PCH_SCS_DEV_PCS_PMEEN BIT8 = ///< PME Enable +#define B_PCH_SCS_DEV_PCS_NSS BIT3 = ///< No Soft Reset +#define B_PCH_SCS_DEV_PCS_PS (BIT1 | BIT0) = ///< Power State +#define B_PCH_SCS_DEV_PCS_PS_D3HOT (BIT1 | BIT0) = ///< Power State: D3Hot State +#define R_PCH_SCS_DEV_PG_CONFIG 0xA2 = ///< PG Config +#define B_PCH_SCS_DEV_PG_CONFIG_SE BIT3 = ///< Sleep Enable +#define B_PCH_SCS_DEV_PG_CONFIG_PGE BIT2 = ///< PG Enable +#define B_PCH_SCS_DEV_PG_CONFIG_I3E BIT1 = ///< I3 Enable +#define B_PCH_SCS_DEV_PG_CONFIG_PMCRE BIT0 = ///< PMC Request Enable +#define V_PCH_SCS_DEV_BAR0_SIZE 0x1000 = ///< BAR0 size +// +// SCS Devices MMIO Space Register +// +#define R_PCH_SCS_DEV_MEM_DMAADR 0x00 +#define R_PCH_SCS_DEV_MEM_BLKSZ 0x04 +#define R_PCH_SCS_DEV_MEM_BLKCNT 0x06 +#define R_PCH_SCS_DEV_MEM_CMDARG 0x08 +#define R_PCH_SCS_DEV_MEM_XFRMODE 0x0C +#define B_PCH_SCS_DEV_MEM_XFRMODE_DMA_EN BIT0 +#define B_PCH_SCS_DEV_MEM_XFRMODE_BLKCNT_EN BIT1 +#define B_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD_EN_MASK (BIT2 | BIT3) +#define V_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD12_EN 1 +#define B_PCH_SCS_DEV_MEM_XFRMODE_DATA_TRANS_DIR BIT4 = ///< 1: Read (Card to Host), 0: Write (Host to Card) +#define B_PCH_SCS_DEV_MEM_XFRMODE_MULTI_SINGLE_BLK BIT5 = ///< 1: Multiple Block, 0: Single Block +#define R_PCH_SCS_DEV_MEM_SDCMD 0x0E +#define B_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_MASK (BIT0 | BIT1) +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_NO_RESP 0 +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP136 1 +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP48 2 +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP48_CHK 3 +#define B_PCH_SCS_DEV_MEM_SDCMD_CMD_CRC_CHECK_EN BIT3 +#define B_PCH_SCS_DEV_MEM_SDCMD_CMD_INDEX_CHECK_EN BIT4 +#define B_PCH_SCS_DEV_MEM_SDCMD_DATA_PRESENT_SEL BIT5 +#define R_PCH_SCS_DEV_MEM_RESP 0x10 +#define R_PCH_SCS_DEV_MEM_BUFDATAPORT 0x20 +#define R_PCH_SCS_DEV_MEM_PSTATE 0x24 +#define B_PCH_SCS_DEV_MEM_PSTATE_DAT0 BIT20 +#define R_PCH_SCS_DEV_MEM_PWRCTL 0x29 +#define R_PCH_SCS_DEV_MEM_CLKCTL 0x2C +#define R_PCH_SCS_DEV_MEM_TIMEOUT_CTL 0x2E = ///< Timeout Control +#define B_PCH_SCS_DEV_MEM_TIMEOUT_CTL_DTCV 0x0F = ///< Data Timeout Counter Value +#define R_PCH_SCS_DEV_MEM_SWRST 0x2F +#define B_PCH_SCS_DEV_MEM_SWRST_CMDLINE BIT1 +#define B_PCH_SCS_DEV_MEM_SWRST_DATALINE BIT2 +#define R_PCH_SCS_DEV_MEM_NINTSTS 0x30 +#define B_PCH_SCS_DEV_MEM_NINTSTS_MASK 0xFFFF +#define B_PCH_SCS_DEV_MEM_NINTSTS_CLEAR_MASK 0x60FF +#define B_PCH_SCS_DEV_MEM_NINTSTS_CMD_COMPLETE BIT0 +#define B_PCH_SCS_DEV_MEM_NINTSTS_TRANSFER_COMPLETE BIT1 +#define B_PCH_SCS_DEV_MEM_NINTSTS_DMA_INTERRUPT BIT3 +#define B_PCH_SCS_DEV_MEM_NINTSTS_BUF_READ_READY_INTR BIT5 +#define R_PCH_SCS_DEV_MEM_ERINTSTS 0x32 +#define B_PCH_SCS_DEV_MEM_ERINTSTS_MASK 0x13FF +#define B_PCH_SCS_DEV_MEM_ERINTSTS_CLEAR_MASK 0x13FF +#define R_PCH_SCS_DEV_MEM_NINTEN 0x34 +#define B_PCH_SCS_DEV_MEM_NINTEN_MASK 0x7FFF +#define R_PCH_SCS_DEV_MEM_ERINTEN 0x36 +#define B_PCH_SCS_DEV_MEM_ERINTEN_MASK 0x13FF +#define R_PCH_SCS_DEV_MEM_NINTSIGNEN 0x38 +#define B_PCH_SCS_DEV_MEM_NINTSIGNEN_MASK 0x7FFF +#define R_PCH_SCS_DEV_MEM_ERINTSIGNEN 0x3A +#define B_PCH_SCS_DEV_MEM_ERINTSIGNEN_MASK 0x13FF +#define R_PCH_SCS_DEV_MEM_HOST_CTL2 0x3E +#define B_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_MASK (BIT0 | BIT1 | B= IT2) +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_HS400 5 +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_DDR50 4 +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_SDR104 3 +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_SDR25 1 +#define R_PCH_SCS_DEV_MEM_CAP1 0x40 +#define R_PCH_SCS_DEV_MEM_CAP2 0x44 +#define B_PCH_SCS_DEV_MEM_CAP2_HS400_SUPPORT BIT31 +#define B_PCH_SCS_DEV_MEM_CAP2_SDR104_SUPPORT BIT1 +#define R_PCH_SCS_DEV_MEM_CESHC2 0x3C = ///< Auto CMD12 Error Status Register & Host Control 2 +#define B_PCH_SCS_DEV_MEM_CESHC2_ASYNC_INT BIT30 = ///< Asynchronous Interrupt Enable +#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_CONTROL 0x810 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_CONTROL_EN 0x5A +#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1 0x814 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_EMMC_DEFAULTS 0x3C80= EB1E +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SDIO_DEFAULTS 0x1C80= EF1E +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SDCARD_DEFAULTS 0x1C80= E75C +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_HS400 BIT29 +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ (BIT27= | BIT26 | BIT25 | BIT24 | BIT23 | BIT22) +#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ 22 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ 0x1 +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT (BIT20= | BIT19 | BIT18 | BIT17) +#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT 17 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT 0x8 +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE (BIT12= | BIT11) +#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE 11 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE_EMBEDDED 0x1 +#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2 0x818 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_EMMC_DEFAULTS 0x0400= 40C8 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_SDIO_DEFAULTS 0x0400= 00C8 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_SDCARD_DEFAULTS 0x0400= 00C8 +#define R_PCH_SCS_DEV_MEM_TX_CMD_DLL_CNTL1 0x820 +#define R_PCH_SCS_DEV_MEM_TX_CMD_DLL_CNTL2 0x80C +#define R_PCH_SCS_DEV_MEM_TX_DATA_DLL_CNTL1 0x824 +#define R_PCH_SCS_DEV_MEM_TX_DATA_DLL_CNTL2 0x828 +#define R_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL1 0x82C +#define R_PCH_SCS_DEV_MEM_RX_STROBE_DLL_CNTL 0x830 +#define R_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2 0x834 +#define N_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX 16 +#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_AUTO 0x2 +#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_BEFORE 0x1 +#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_AFTER 0x0 + +// +// SCS Private Configuration Space Registers +// +#define R_PCH_PCR_SCS_IOSFCTL 0x00 = ///< IOSF Control +#define B_PCH_PCR_SCS_IOSFCTL_NSNPDIS BIT7 = ///< Non-Snoop Disable +#define B_PCH_PCR_SCS_IOSFCTL_MAX_RD_PEND (BIT3 | BIT2 | BIT1 | BI= T0) ///< Max upstream pending reads +#define R_PCH_PCR_SCS_OCPCTL 0x10 = ///< OCP Control +#define B_PCH_PCR_SCS_OCPCTL_NPEN BIT0 = ///< Downstream non-posted memory write capability +#define R_PCH_PCR_SCS_PMCTL 0x1D0 = ///< Power Management Control +#define R_PCH_PCR_SCS_PCICFGCTR1 0x200 = ///< PCI Configuration Control 1 - eMMC +#define R_PCH_PCR_SCS_PCICFGCTR2 0x204 = ///< PCI Configuration Control 2 - SDIO +#define R_PCH_PCR_SCS_PCICFGCTR3 0x208 = ///< PCI Configuration Control 3 - SD Card +#define B_PCH_PCR_SCS_PCICFGCTR_PCI_IRQ 0x0FF00000 = ///< PCI IRQ number +#define N_PCH_PCR_SCS_PCICFGCTR_PCI_IRQ 20 +#define B_PCH_PCR_SCS_PCICFGCTR_ACPI_IRQ 0x000FF000 = ///< ACPI IRQ number +#define N_PCH_PCR_SCS_PCICFGCTR_ACPI_IRQ 12 +#define B_PCH_PCR_SCS_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | = BIT8) ///< Interrupt Pin +#define N_PCH_PCR_SCS_PCICFGCTR_IPIN1 8 +#define B_PCH_PCR_SCS_PCICFGCTR_BAR1DIS BIT7 = ///< BAR 1 Disable +#define B_PCH_PCR_SCS_PCICFGCTR_PS 0x7C = ///< PME Support +#define B_PCH_PCR_SCS_PCICFGCTR_ACPI_INT_EN BIT1 = ///< ACPI Interrupt Enable +#define B_PCH_PCR_SCS_PCICFGCTR_PCI_CFG_DIS BIT0 = ///< PCI Configuration Space Disable + +#define R_PCH_PCR_SCS_GPPRVRW1 0x600 = ///< Clock Gating Control +#define R_PCH_PCR_SCS_GPPRVRW2 0x604 = ///< Host Controller Disable +#define B_PCH_PCR_SCS_GPPRVRW2_EMMC_DIS BIT1 = ///< eMMC Host Controller Disable +#define B_PCH_PCR_SCS_GPPRVRW2_SDIO_SDCARD_DIS BIT2 = ///< 1: SDIO Host Controller Disable, 0: SDCARD Host Controller Disab= le +#define R_PCH_PCR_SCS_GPPRVRW6 0x614 = ///< 1.8V Signal Select Delay Control +#define V_PCH_PCR_SCS_GPPRVRW6_1P8_SEL_DELAY 0x7F = ///< Rcomp SDCARD 10ms delay during switch + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsSerialIo.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register= /PchRegsSerialIo.h new file mode 100644 index 0000000000..3142e702f2 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSer= ialIo.h @@ -0,0 +1,282 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_SERIAL_IO_ +#define _PCH_REGS_SERIAL_IO_ + + +// +// Serial IO I2C0 Controller Registers (D21:F0) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0 0 +#define V_PCH_LP_SERIAL_IO_I2C0_SKL_DEVICE_ID 0x9D60 +#define V_PCH_H_SERIAL_IO_I2C0_SKL_DEVICE_ID 0xA160 + +// +// Serial IO I2C1 Controller Registers (D21:F1) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1 1 +#define V_PCH_LP_SERIAL_IO_I2C1_SKL_DEVICE_ID 0x9D61 +#define V_PCH_H_SERIAL_IO_I2C1_SKL_DEVICE_ID 0xA161 + +// +// Serial IO I2C2 Controller Registers (D21:F2) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2 2 +#define V_PCH_LP_SERIAL_IO_I2C2_SKL_DEVICE_ID 0x9D62 +#define V_PCH_H_SERIAL_IO_I2C2_SKL_DEVICE_ID 0xA162 + +// +// Serial IO I2C3 Controller Registers (D21:F3) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3 3 +#define V_PCH_LP_SERIAL_IO_I2C3_SKL_DEVICE_ID 0x9D63 +#define V_PCH_H_SERIAL_IO_I2C3_SKL_DEVICE_ID 0xA163 + +// +// Serial IO I2C4 Controller Registers (D25:F2) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4 25 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4 2 +#define V_PCH_LP_SERIAL_IO_I2C4_SKL_DEVICE_ID 0x9D64 + +// +// Serial IO I2C5 Controller Registers (D25:F1) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5 25 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5 1 +#define V_PCH_LP_SERIAL_IO_I2C5_SKL_DEVICE_ID 0x9D65 + +// +// Serial IO SPI0 Controller Registers (D30:F2) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0 2 +#define V_PCH_LP_SERIAL_IO_SPI0_SKL_DEVICE_ID 0x9D29 +#define V_PCH_H_SERIAL_IO_SPI0_SKL_DEVICE_ID 0xA129 + +// +// Serial IO SPI1 Controller Registers (D30:F3) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1 3 +#define V_PCH_LP_SERIAL_IO_SPI1_SKL_DEVICE_ID 0x9D2A +#define V_PCH_H_SERIAL_IO_SPI1_SKL_DEVICE_ID 0xA129 + +// +// Serial IO UART0 Controller Registers (D30:F0) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0 0 +#define V_PCH_LP_SERIAL_IO_UART0_SKL_DEVICE_ID 0x9D28 +#define V_PCH_H_SERIAL_IO_UART0_SKL_DEVICE_ID 0xA128 + +// +// Serial IO UART1 Controller Registers (D30:F1) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1 1 +#define V_PCH_LP_SERIAL_IO_UART1_SKL_DEVICE_ID 0x9D66 +#define V_PCH_H_SERIAL_IO_UART1_SKL_DEVICE_ID 0xA166 + +#define V_PCH_SERIAL_IO_DEV_MIN_FUN 0 +#define V_PCH_SERIAL_IO_DEV_MAX_FUN 5 + +// +// Serial IO Controllers General PCI Configuration Registers +// registers accessed using PciD21FxRegBase + offset +// +#define R_PCH_SERIAL_IO_BAR0_LOW 0x10 +#define B_PCH_SERIAL_IO_BAR0_LOW_BAR 0xFFFFF000 +#define R_PCH_SERIAL_IO_BAR0_HIGH 0x14 +#define R_PCH_SERIAL_IO_BAR1_LOW 0x18 +#define B_PCH_SERIAL_IO_BAR1_LOW_BAR 0xFFFFF000 +#define R_PCH_SERIAL_IO_BAR1_HIGH 0x1C +#define V_PCH_SERIAL_IO_BAR_SIZE (4 * 1024) +#define N_PCH_SERIAL_IO_BAR_ALIGNMENT 12 + +#define R_PCH_SERIAL_IO_PME_CTRL_STS 0x84 +#define B_PCH_SERIAL_IO_PME_CTRL_STS_PWR_ST (BIT1| BIT0) + +#define R_PCH_SERIAL_IO_D0I3MAXDEVPG 0xA0 +#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_PMCRE BIT16 +#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_I3E BIT17 +#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_PGE BIT18 + +#define R_PCH_SERIAL_IO_INTERRUPTREG 0x3C +#define B_PCH_SERIAL_IO_INTERRUPTREG_INTLINE 0x000000FF + +// +// Serial IO Controllers Private Registers +// registers accessed : BAR0 + offset +// +#define R_PCH_SERIAL_IO_SSCR1 0x4 +#define B_PCH_SERIAL_IO_SSCR1_IFS BIT16 + +#define R_PCH_SERIAL_IO_PPR_CLK 0x200 +#define B_PCH_SERIAL_IO_PPR_CLK_EN BIT0 +#define B_PCH_SERIAL_IO_PPR_CLK_UPDATE BIT31 +#define V_PCH_SERIAL_IO_PPR_CLK_M_DIV 0x30 +#define V_PCH_SERIAL_IO_PPR_CLK_N_DIV 0xC35 + +#define R_PCH_SERIAL_IO_PPR_RESETS 0x204 +#define B_PCH_SERIAL_IO_PPR_RESETS_FUNC BIT0 +#define B_PCH_SERIAL_IO_PPR_RESETS_APB BIT1 +#define B_PCH_SERIAL_IO_PPR_RESETS_IDMA BIT2 + +#define R_PCH_SERIAL_IO_ACTIVE_LTR 0x210 +#define R_PCH_SERIAL_IO_IDLE_LTR 0x214 +#define B_PCH_SERIAL_IO_LTR_SNOOP_VALUE 0x000003FF +#define B_PCH_SERIAL_IO_LTR_SNOOP_SCALE 0x00001C00 +#define B_PCH_SERIAL_IO_LTR_SNOOP_REQUIREMENT BIT15 + +#define R_PCH_SERIAL_IO_SPI_CS_CONTROL 0x224 +#define B_PCH_SERIAL_IO_SPI_CS_CONTROL_STATE BIT1 +#define B_PCH_SERIAL_IO_SPI_CS_CONTROL_MODE BIT0 + +#define R_PCH_SERIAL_IO_REMAP_ADR_LOW 0x240 +#define R_PCH_SERIAL_IO_REMAP_ADR_HIGH 0x244 + +#define R_PCH_SERIAL_IO_I2C_SDA_HOLD 0x7C +#define V_PCH_SERIAL_IO_I2C_SDA_HOLD_VALUE 0x002C002C + +// +// I2C Controller +// Registers accessed through BAR0 + offset +// +#define R_IC_CON 0x00 // I2c Control +#define B_IC_MASTER_MODE BIT0 +#define B_IC_RESTART_EN BIT5 +#define B_IC_SLAVE_DISABLE BIT6 +#define V_IC_SPEED_STANDARD 0x02 +#define V_IC_SPEED_FAST 0x04 +#define V_IC_SPEED_HIGH 0x06 + +#define R_IC_TAR 0x04 // I2c Target Address +#define B_IC_TAR_10BITADDR_MASTER BIT12 + +#define R_IC_DATA_CMD 0x10 // I2c Rx/Tx Data Buf= fer and Command +#define B_IC_CMD_READ BIT8 // 1 =3D read, 0 = =3D write +#define B_IC_CMD_STOP BIT9 // 1 =3D STOP +#define B_IC_CMD_RESTART BIT10 // 1 =3D IC_RESTART= _EN +#define V_IC_WRITE_CMD_MASK 0xFF + +#define R_IC_SS_SCL_HCNT 0x14 // Standard Speed I2c = Clock SCL High Count +#define R_IC_SS_SCL_LCNT 0x18 // Standard Speed I2c = Clock SCL Low Count +#define R_IC_FS_SCL_HCNT 0x1C // Full Speed I2c Cloc= k SCL High Count +#define R_IC_FS_SCL_LCNT 0x20 // Full Speed I2c Cloc= k SCL Low Count +#define R_IC_HS_SCL_HCNT 0x24 // High Speed I2c Cloc= k SCL High Count +#define R_IC_HS_SCL_LCNT 0x28 // High Speed I2c Cloc= k SCL Low Count +#define R_IC_INTR_STAT 0x2C // I2c Inetrrupt Status +#define R_IC_INTR_MASK 0x30 // I2c Interrupt Mask +#define B_IC_INTR_GEN_CALL BIT11 // General call rece= ived +#define B_IC_INTR_START_DET BIT10 +#define B_IC_INTR_STOP_DET BIT9 +#define B_IC_INTR_ACTIVITY BIT8 +#define B_IC_INTR_TX_ABRT BIT6 // Set on NACK +#define B_IC_INTR_TX_EMPTY BIT4 +#define B_IC_INTR_TX_OVER BIT3 +#define B_IC_INTR_RX_FULL BIT2 // Data bytes in RX = FIFO over threshold +#define B_IC_INTR_RX_OVER BIT1 +#define B_IC_INTR_RX_UNDER BIT0 +#define R_IC_RAW_INTR_STAT ( 0x34) // I2c Raw Interrupt = Status +#define R_IC_RX_TL ( 0x38) // I2c Receive FIFO T= hreshold +#define R_IC_TX_TL ( 0x3C) // I2c Transmit FIFO = Threshold +#define R_IC_CLR_INTR ( 0x40) // Clear Combined and= Individual Interrupts +#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Int= errupt +#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinter= rupt +#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER inte= rrupt +#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ inter= rupt +#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT inte= rrupt +#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE inte= rrupt +#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY int= errupt +#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET int= errupt +#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET in= terrupt +#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL int= errupt +#define R_IC_ENABLE ( 0x6C) // I2c Enable + +#define R_IC_STATUS 0x70 // I2c Status +#define B_IC_STATUS_RFF BIT4 // RX FIFO is comple= tely full +#define B_IC_STATUS_RFNE BIT3 // RX FIFO is not em= pty +#define B_IC_STATUS_TFE BIT2 // TX FIFO is comple= tely empty +#define B_IC_STATUS_TFNF BIT1 // TX FIFO is not fu= ll +#define B_IC_STATUS_ACTIVITY BIT0 // Controller Activi= ty Status. + +#define R_IC_TXFL R ( 0x74) // Transmit FIFO Leve= l Register +#define R_IC_RXFLR ( 0x78) // Receive FIFO Level= Register +#define R_IC_SDA_HOLD ( 0x7C) +#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2c Transmit Abort= Status Register +#define B_IC_TX_ABRT_7B_ADDR_NACK BIT0 // NACK on 7-bit address + +#define R_IC_SDA_SETUP ( 0x94) // I2c SDA Setup Regi= ster +#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2c ACK General Ca= ll Register +#define R_IC_ENABLE_STATUS ( 0x9C) // I2c Enable Status = Register +#define B_IC_EN BIT0 // I2c enable status + +#define R_IC_CLK_GATE (0xC0) +#define R_IC_COMP_PARAM ( 0xF4) // Component Paramete= r Register +#define R_IC_COMP_VERSION ( 0xF8) // Component Version = ID +#define R_IC_COMP_TYPE ( 0xFC) // Component Type + + + +// +// Bridge Private Configuration Registers +// accessed only through SB messaging. SB access =3D SerialIo IOSF2OCP Bri= dge Port ID + offset +// +#define R_PCH_PCR_SERIAL_IO_PMCTL 0x1D0 +#define V_PCH_PCR_SERIAL_IO_PMCTL_PWR_GATING 0x3F + +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRLx 0x200 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_N_OFFS 0x04 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL1 0x200 //I2C0 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL2 0x204 //I2C1 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL3 0x208 //I2C2 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL4 0x20C //I2C3 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL5 0x210 //I2C4 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL6 0x214 //I2C5 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL9 0x218 //UA00 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL10 0x21C //UA01 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL11 0x220 //UA02 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL13 0x224 //SPI0 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL14 0x228 //SPI1 + +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_CFG_DIS BIT0 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_INTR_EN BIT1 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_BAR1_DIS BIT7 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_INT_PIN (BIT11 | BIT10 | B= IT9 | BIT8) +#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_INT_PIN 8 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTA 0x01 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTB 0x02 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTC 0x03 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTD 0x04 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_IRQ 0x000FF000 +#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_IRQ 12 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_IRQ 0x0FF00000 +#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_IRQ 20 + +#define R_PCH_PCR_SERIAL_IO_GPPRVRW2 0x604 +#define V_PCH_PCR_SERIAL_IO_GPPRVRW2_CLK_GATING (BIT11 | BIT1) + +#define R_PCH_PCR_SERIAL_IO_GPPRVRW7 0x618 +#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART0_BYTE_ADDR_EN BIT0 +#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART1_BYTE_ADDR_EN BIT1 +#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART2_BYTE_ADDR_EN BIT2 + +// +// Number of pins used by SerialIo controllers +// +#define PCH_SERIAL_IO_PINS_PER_I2C_CONTROLLER 2 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 +#define PCH_SERIAL_IO_PINS_PER_SPI_CONTROLLER 4 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsSmbus.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pc= hRegsSmbus.h new file mode 100644 index 0000000000..1f0912bec8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSmb= us.h @@ -0,0 +1,134 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_SMBUS_H_ +#define _PCH_REGS_SMBUS_H_ + +// +// SMBus Controller Registers (D31:F4) +// +#define PCI_DEVICE_NUMBER_PCH_SMBUS 31 +#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4 +#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_SMBUS_DEVICE_ID 0xA123 +// +// LBG Production SMBus Controller Device ID +// +#define V_PCH_LBG_PROD_SMBUS_DEVICE_ID 0xA1A3 +// +// LBG SSX (Super SKU) SMBus Controller Device ID +// +#define V_PCH_LBG_SMBUS_DEVICE_ID 0xA223 +#define V_PCH_LP_SMBUS_DEVICE_ID 0x9D23 +#define R_PCH_SMBUS_BASE 0x20 +#define V_PCH_SMBUS_BASE_SIZE (1 << 5) +#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 +#define R_PCH_SMBUS_HOSTC 0x40 +#define B_PCH_SMBUS_HOSTC_SPDWD BIT4 +#define B_PCH_SMBUS_HOSTC_SSRESET BIT3 +#define B_PCH_SMBUS_HOSTC_I2C_EN BIT2 +#define B_PCH_SMBUS_HOSTC_SMI_EN BIT1 +#define B_PCH_SMBUS_HOSTC_HST_EN BIT0 +#define R_PCH_SMBUS_TCOBASE 0x50 +#define B_PCH_SMBUS_TCOBASE_BAR 0x0000FFE0 +#define R_PCH_SMBUS_TCOCTL 0x54 +#define B_PCH_SMBUS_TCOCTL_TCO_BASE_EN BIT8 +#define B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK BIT0 +#define R_PCH_SMBUS_64 0x64 +#define R_PCH_SMBUS_80 0x80 + +// +// SMBus I/O Registers +// +#define R_PCH_SMBUS_HSTS 0x00 ///< Host Status Register = R/W +#define B_PCH_SMBUS_HBSY 0x01 +#define B_PCH_SMBUS_INTR 0x02 +#define B_PCH_SMBUS_DERR 0x04 +#define B_PCH_SMBUS_BERR 0x08 +#define B_PCH_SMBUS_FAIL 0x10 +#define B_PCH_SMBUS_SMBALERT_STS 0x20 +#define B_PCH_SMBUS_IUS 0x40 +#define B_PCH_SMBUS_BYTE_DONE_STS 0x80 +#define B_PCH_SMBUS_ERROR (B_PCH_SMBUS_DERR | B_PCH_SMBUS_= BERR | B_PCH_SMBUS_FAIL) +#define B_PCH_SMBUS_HSTS_ALL 0xFF +#define R_PCH_SMBUS_HCTL 0x02 ///< Host Control Register= R/W +#define B_PCH_SMBUS_INTREN 0x01 +#define B_PCH_SMBUS_KILL 0x02 +#define B_PCH_SMBUS_SMB_CMD 0x1C +#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 +#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 +#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 +#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C +#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 +#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 +#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 +#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C +#define B_PCH_SMBUS_LAST_BYTE 0x20 +#define B_PCH_SMBUS_START 0x40 +#define B_PCH_SMBUS_PEC_EN 0x80 +#define R_PCH_SMBUS_HCMD 0x03 ///< Host Command Register= R/W +#define R_PCH_SMBUS_TSA 0x04 ///< Transmit Slave Addres= s Register R/W +#define B_PCH_SMBUS_RW_SEL 0x01 +#define B_PCH_SMBUS_READ 0x01 // RW +#define B_PCH_SMBUS_WRITE 0x00 // RW +#define B_PCH_SMBUS_ADDRESS 0xFE +#define R_PCH_SMBUS_HD0 0x05 ///< Data 0 Register R/W +#define R_PCH_SMBUS_HD1 0x06 ///< Data 1 Register R/W +#define R_PCH_SMBUS_HBD 0x07 ///< Host Block Data Regis= ter R/W +#define R_PCH_SMBUS_PEC 0x08 ///< Packet Error Check Da= ta Register R/W +#define R_PCH_SMBUS_RSA 0x09 ///< Receive Slave Address= Register R/W +#define B_PCH_SMBUS_SLAVE_ADDR 0x7F +#define R_PCH_SMBUS_SD 0x0A ///< Receive Slave Data Re= gister R/W +#define R_PCH_SMBUS_AUXS 0x0C ///< Auxiliary Status Regi= ster R/WC +#define B_PCH_SMBUS_CRCE 0x01 +#define B_PCH_SMBUS_STCO 0x02 ///< SMBus TCO Mode +#define R_PCH_SMBUS_AUXC 0x0D ///< Auxiliary Control Reg= ister R/W +#define B_PCH_SMBUS_AAC 0x01 +#define B_PCH_SMBUS_E32B 0x02 +#define R_PCH_SMBUS_SMLC 0x0E ///< SMLINK Pin Control Re= gister R/W +#define B_PCH_SMBUS_SMLINK0_CUR_STS 0x01 +#define B_PCH_SMBUS_SMLINK1_CUR_STS 0x02 +#define B_PCH_SMBUS_SMLINK_CLK_CTL 0x04 +#define R_PCH_SMBUS_SMBC 0x0F ///< SMBus Pin Control Reg= ister R/W +#define B_PCH_SMBUS_SMBCLK_CUR_STS 0x01 +#define B_PCH_SMBUS_SMBDATA_CUR_STS 0x02 +#define B_PCH_SMBUS_SMBCLK_CTL 0x04 +#define R_PCH_SMBUS_SSTS 0x10 ///< Slave Status Register= R/WC +#define B_PCH_SMBUS_HOST_NOTIFY_STS 0x01 +#define R_PCH_SMBUS_SCMD 0x11 ///< Slave Command Registe= r R/W +#define B_PCH_SMBUS_HOST_NOTIFY_INTREN 0x01 +#define B_PCH_SMBUS_HOST_NOTIFY_WKEN 0x02 +#define B_PCH_SMBUS_SMBALERT_DIS 0x04 +#define R_PCH_SMBUS_NDA 0x14 ///< Notify Device Address= Register RO +#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE +#define R_PCH_SMBUS_NDLB 0x16 ///< Notify Data Low Byte = Register RO +#define R_PCH_SMBUS_NDHB 0x17 ///< Notify Data High Byte= Register RO + +// +// SMBus Private Config Registers +// (PID:SMB) +// +#define R_PCH_PCR_SMBUS_TCOCFG 0x00 = ///< TCO Configuration register +#define B_PCH_PCR_SMBUS_TCOCFG_IE BIT7 = ///< TCO IRQ Enable +#define B_PCH_PCR_SMBUS_TCOCFG_IS (BIT2 | BIT1 | BIT0) = ///< TCO IRQ Select +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_9 0x00 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_10 0x01 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_11 0x02 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_20 0x04 = ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_21 0x05 = ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_22 0x06 = ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_23 0x07 = ///< only if APIC enabled +#define R_PCH_PCR_SMBUS_SMBTM 0x04 = ///< SMBus Test Mode +#define B_PCH_PCR_SMBUS_SMBTM_SMBCT BIT1 = ///< SMBus Counter +#define B_PCH_PCR_SMBUS_SMBTM_SMBDG BIT0 = ///< SMBus Deglitch +#define R_PCH_PCR_SMBUS_SCTM 0x08 = ///< Short Counter Test Mode +#define B_PCH_PCR_SMBUS_SCTM_SSU BIT31 = ///< Simulation Speed-Up +#define R_PCH_PCR_SMBUS_GC 0x0C = ///< General Control +#define B_PCH_PCR_SMBUS_GC_FD BIT0 = ///< Function Disable +#define B_PCH_PCR_SMBUS_GC_NR BIT1 = ///< No Reboot +#define B_PCH_PCR_SMBUS_GC_SMBSCGE BIT2 = ///< SMB Static Clock Gating Enable +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsSpi.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsSpi.h new file mode 100644 index 0000000000..ef5dd8ea18 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSpi= .h @@ -0,0 +1,291 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_SPI_H_ +#define _PCH_REGS_SPI_H_ + +// +// SPI Registers (D31:F5) +// + +#define PCI_DEVICE_NUMBER_PCH_SPI 31 +#define PCI_FUNCTION_NUMBER_PCH_SPI 5 +#define V_PCH_SPI_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_SPI_DEVICE_ID 0xA124 +// +// LBG PRODUCTION SPI Device ID +// +#define V_PCH_LBG_PROD_SPI_DEVICE_ID 0xA1A4 +// +// LBG SSX (Super SKU) SPI Device ID +// +#define V_PCH_LBG_SPI_DEVICE_ID 0xA224 +#define V_PCH_LP_SPI_DEVICE_ID 0x9D24 +#define R_PCH_SPI_BAR0 0x10 +#define B_PCH_SPI_BAR0_MASK 0x0FFF + +#define R_PCH_SPI_BDE 0xD8 +#define B_PCH_SPI_BDE_F8 0x8000 +#define B_PCH_SPI_BDE_F0 0x4000 +#define B_PCH_SPI_BDE_E8 0x2000 +#define B_PCH_SPI_BDE_E0 0x1000 +#define B_PCH_SPI_BDE_D8 0x0800 +#define B_PCH_SPI_BDE_D0 0x0400 +#define B_PCH_SPI_BDE_C8 0x0200 +#define B_PCH_SPI_BDE_C0 0x0100 +#define B_PCH_SPI_BDE_LEG_F 0x0080 +#define B_PCH_SPI_BDE_LEG_E 0x0040 +#define B_PCH_SPI_BDE_70 0x0008 +#define B_PCH_SPI_BDE_60 0x0004 +#define B_PCH_SPI_BDE_50 0x0002 +#define B_PCH_SPI_BDE_40 0x0001 + +#define R_PCH_SPI_BC 0xDC +#define S_PCH_SPI_BC 4 +#define N_PCH_SPI_BC_ASE_BWP 11 +#define B_PCH_SPI_BC_ASE_BWP BIT11 +#define N_PCH_SPI_BC_ASYNC_SS 10 +#define B_PCH_SPI_BC_ASYNC_SS BIT10 +#define B_PCH_SPI_BC_OSFH BIT9 ///< OS Functi= on Hide +#define N_PCH_SPI_BC_SYNC_SS 8 +#define B_PCH_SPI_BC_SYNC_SS BIT8 +#define B_PCH_SPI_BC_BILD BIT7 +#define B_PCH_SPI_BC_BBS BIT6 ///< Boot BIOS= strap +#define N_PCH_SPI_BC_BBS 6 +#define V_PCH_SPI_BC_BBS_SPI 0 ///< Boot BIOS= strapped to SPI +#define V_PCH_SPI_BC_BBS_LPC 1 ///< Boot BIOS= strapped to LPC +#define B_PCH_SPI_BC_EISS BIT5 ///< Enable In= SMM.STS +#define B_PCH_SPI_BC_TSS BIT4 +#define B_PCH_SPI_BC_SRC (BIT3 | BIT2) +#define N_PCH_SPI_BC_SRC 2 +#define V_PCH_SPI_BC_SRC_PREF_EN_CACHE_EN 0x02 ///< Prefetchi= ng and Caching enabled +#define V_PCH_SPI_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefet= ching and no caching +#define V_PCH_SPI_BC_SRC_PREF_DIS_CACHE_EN 0x00 ///< No prefet= ching, but caching enabled +#define B_PCH_SPI_BC_LE BIT1 ///< Lock Enab= le +#define N_PCH_SPI_BC_BLE 1 +#define B_PCH_SPI_BC_WPD BIT0 ///< Write Pro= tect Disable + +// +// BIOS Flash Program Registers (based on SPI_BAR0) +// +#define R_PCH_SPI_BFPR 0x00 = ///< BIOS Flash Primary Region Register(32bits), which is RO and contains t= he same value from FREG1 +#define B_PCH_SPI_BFPR_PRL 0x7FFF0000 = ///< BIOS Flash Primary Region Limit mask +#define N_PCH_SPI_BFPR_PRL 16 = ///< BIOS Flash Primary Region Limit bit position +#define B_PCH_SPI_BFPR_PRB 0x00007FFF = ///< BIOS Flash Primary Region Base mask +#define N_PCH_SPI_BFPR_PRB 0 = ///< BIOS Flash Primary Region Base bit position +#define R_PCH_SPI_HSFSC 0x04 = ///< Hardware Sequencing Flash Status and Control Register(32bits) +#define B_PCH_SPI_HSFSC_FSMIE BIT31 = ///< Flash SPI SMI# Enable +#define B_PCH_SPI_HSFSC_FDBC_MASK 0x3F000000 = ///< Flash Data Byte Count ( <=3D 64), Count =3D (Value in this field) + 1. +#define N_PCH_SPI_HSFSC_FDBC 24 +#define B_PCH_SPI_HSFSC_CYCLE_MASK 0x001E0000 = ///< Flash Cycle. +#define N_PCH_SPI_HSFSC_CYCLE 17 +#define V_PCH_SPI_HSFSC_CYCLE_READ 0 = ///< Flash Cycle Read +#define V_PCH_SPI_HSFSC_CYCLE_WRITE 2 = ///< Flash Cycle Write +#define V_PCH_SPI_HSFSC_CYCLE_4K_ERASE 3 = ///< Flash Cycle 4K Block Erase +#define V_PCH_SPI_HSFSC_CYCLE_64K_ERASE 4 = ///< Flash Cycle 64K Sector Erase +#define V_PCH_SPI_HSFSC_CYCLE_READ_SFDP 5 = ///< Flash Cycle Read SFDP +#define V_PCH_SPI_HSFSC_CYCLE_READ_JEDEC_ID 6 = ///< Flash Cycle Read JEDEC ID +#define V_PCH_SPI_HSFSC_CYCLE_WRITE_STATUS 7 = ///< Flash Cycle Write Status +#define V_PCH_SPI_HSFSC_CYCLE_READ_STATUS 8 = ///< Flash Cycle Read Status +#define B_PCH_SPI_HSFSC_CYCLE_FGO BIT16 = ///< Flash Cycle Go. +#define B_PCH_SPI_HSFSC_FLOCKDN BIT15 = ///< Flash Configuration Lock-Down +#define B_PCH_SPI_HSFSC_FDV BIT14 = ///< Flash Descriptor Valid, once valid software can use hareware sequencin= g regs +#define B_PCH_SPI_HSFSC_FDOPSS BIT13 = ///< Flash Descriptor Override Pin-Strap Status +#define B_PCH_SPI_HSFSC_PRR34_LOCKDN BIT12 = ///< PRR3 PRR4 Lock-Down +#define B_PCH_SPI_HSFSC_SAF_CE BIT8 = ///< SAF ctype error +#define B_PCH_SPI_HSFSC_SAF_MODE_ACTIVE BIT7 = ///< Indicates flash is attached either directly to the PCH via the SPI bus= or EC/BMC +#define B_PCH_SPI_HSFSC_SAF_LE BIT6 = ///< SAF link error +#define B_PCH_SPI_HSFSC_SCIP BIT5 = ///< SPI cycle in progress +#define B_PCH_SPI_HSFSC_SAF_DLE BIT4 = ///< SAF Data length error +#define B_PCH_SPI_HSFSC_SAF_ERROR BIT3 = ///< SAF Error +#define B_PCH_SPI_HSFSC_AEL BIT2 = ///< Access Error Log +#define B_PCH_SPI_HSFSC_FCERR BIT1 = ///< Flash Cycle Error +#define B_PCH_SPI_HSFSC_FDONE BIT0 = ///< Flash Cycle Done +#define R_PCH_SPI_FADDR 0x08 = ///< SPI Flash Address +#define B_PCH_SPI_FADDR_MASK 0x07FFFFFF = ///< SPI Flash Address Mask (0~26bit) +#define R_PCH_SPI_DLOCK 0x0C = ///< Discrete Lock Bits +#define B_PCH_SPI_DLOCK_PR0LOCKDN BIT8 = ///< PR0LOCKDN +#define R_PCH_SPI_FDATA00 0x10 = ///< SPI Data 00 (32 bits) +#define R_PCH_SPI_FDATA01 0x14 = ///< SPI Data 01 +#define R_PCH_SPI_FDATA02 0x18 = ///< SPI Data 02 +#define R_PCH_SPI_FDATA03 0x1C = ///< SPI Data 03 +#define R_PCH_SPI_FDATA04 0x20 = ///< SPI Data 04 +#define R_PCH_SPI_FDATA05 0x24 = ///< SPI Data 05 +#define R_PCH_SPI_FDATA06 0x28 = ///< SPI Data 06 +#define R_PCH_SPI_FDATA07 0x2C = ///< SPI Data 07 +#define R_PCH_SPI_FDATA08 0x30 = ///< SPI Data 08 +#define R_PCH_SPI_FDATA09 0x34 = ///< SPI Data 09 +#define R_PCH_SPI_FDATA10 0x38 = ///< SPI Data 10 +#define R_PCH_SPI_FDATA11 0x3C = ///< SPI Data 11 +#define R_PCH_SPI_FDATA12 0x40 = ///< SPI Data 12 +#define R_PCH_SPI_FDATA13 0x44 = ///< SPI Data 13 +#define R_PCH_SPI_FDATA14 0x48 = ///< SPI Data 14 +#define R_PCH_SPI_FDATA15 0x4C = ///< SPI Data 15 +#define R_PCH_SPI_FRAP 0x50 = ///< Flash Region Access Permisions Register +#define B_PCH_SPI_FRAP_BRWA_MASK 0x0000FF00 = ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIO= S; 2: ME; 3: GbE; 4: PlatformData +#define N_PCH_SPI_FRAP_BRWA 8 = ///< BIOS Region Write Access bit position +#define B_PCH_SPI_FRAP_BRRA_MASK 0x000000FF = ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS= ; 2: ME; 3: GbE; 4: PlatformData +#define B_PCH_SPI_FRAP_BMRAG_MASK 0x00FF0000 = ///< BIOS Master Read Access Grant +#define B_PCH_SPI_FRAP_BMWAG_MASK 0xFF000000 = ///< BIOS Master Write Access Grant +#define R_PCH_SPI_FREG0_FLASHD 0x54 = ///< Flash Region 0(Flash Descriptor)(32bits) +#define R_PCH_SPI_FREG1_BIOS 0x58 = ///< Flash Region 1(BIOS)(32bits) +#define R_PCH_SPI_FREG2_ME 0x5C = ///< Flash Region 2(ME)(32bits) +#define R_PCH_SPI_FREG3_GBE 0x60 = ///< Flash Region 3(GbE)(32bits) +#define R_PCH_SPI_FREG4_PLATFORM_DATA 0x64 = ///< Flash Region 4(Platform Data)(32bits) +#define R_PCH_SPI_FREG5_DER 0x68 = ///< Flash Region 5(Device Expansion Region)(32bits) +#define S_PCH_SPI_FREGX 4 = ///< Size of Flash Region register +#define B_PCH_SPI_FREGX_LIMIT_MASK 0x7FFF0000 = ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to b= e FFFh +#define N_PCH_SPI_FREGX_LIMIT 16 = ///< Region limit bit position +#define N_PCH_SPI_FREGX_LIMIT_REPR 12 = ///< Region limit bit represents position +#define B_PCH_SPI_FREGX_BASE_MASK 0x00007FFF = ///< Flash Region Base, [14:0] represents [26:12] +#define N_PCH_SPI_FREGX_BASE 0 = ///< Region base bit position +#define N_PCH_SPI_FREGX_BASE_REPR 12 = ///< Region base bit represents position +#define R_PCH_SPI_PR0 0x84 = ///< Protected Region 0 Register +#define R_PCH_SPI_PR1 0x88 = ///< Protected Region 1 Register +#define R_PCH_SPI_PR2 0x8C = ///< Protected Region 2 Register +#define R_PCH_SPI_PR3 0x90 = ///< Protected Region 3 Register +#define R_PCH_SPI_PR4 0x94 = ///< Protected Region 4 Register +#define S_PCH_SPI_PRX 4 = ///< Protected Region X Register size +#define B_PCH_SPI_PRX_WPE BIT31 = ///< Write Protection Enable +#define B_PCH_SPI_PRX_PRL_MASK 0x7FFF0000 = ///< Protected Range Limit Mask, [30:16] here represents upper limit of add= ress [26:12] +#define N_PCH_SPI_PRX_PRL 16 = ///< Protected Range Limit bit position +#define B_PCH_SPI_PRX_RPE BIT15 = ///< Read Protection Enable +#define B_PCH_SPI_PRX_PRB_MASK 0x00007FFF = ///< Protected Range Base Mask, [14:0] here represents base limit of addres= s [26:12] +#define N_PCH_SPI_PRX_PRB 0 = ///< Protected Range Base bit position +#define R_PCH_SPI_SFRAP 0xB0 = ///< Secondary Flash Regions Access Permisions Register +#define R_PCH_SPI_FDOC 0xB4 = ///< Flash Descriptor Observability Control Register(32 bits) +#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) = ///< Flash Descritor Section Select +#define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 = ///< Flash Signature and Descriptor Map +#define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 = ///< Component +#define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 = ///< Region +#define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 = ///< Master +#define V_PCH_SPI_FDOC_FDSS_PCHS 0x4000 = ///< PCH soft straps +#define V_PCH_SPI_FDOC_FDSS_SFDP 0x5000 = ///< SFDP Parameter Table +#define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC = ///< Flash Descriptor Section Index +#define R_PCH_SPI_FDOD 0xB8 = ///< Flash Descriptor Observability Data Register(32 bits) +#define R_PCH_SPI_SFDP0_VSCC0 0xC4 = ///< Vendor Specific Component Capabilities Register(32 bits) +#define B_PCH_SPI_SFDPX_VSCCX_CPPTV BIT31 = ///< Component Property Parameter Table Valid +#define B_PCH_SPI_SFDP0_VSCC0_VCL BIT30 = ///< Vendor Component Lock +#define B_PCH_SPI_SFDPX_VSCCX_EO_64K BIT29 = ///< 64k Erase valid (EO_64k_valid) +#define B_PCH_SPI_SFDPX_VSCCX_EO_4K BIT28 = ///< 4k Erase valid (EO_4k_valid) +#define B_PCH_SPI_SFDPX_VSCCX_RPMC BIT27 = ///< RPMC Supported +#define B_PCH_SPI_SFDPX_VSCCX_DPD BIT26 = ///< Deep Powerdown Supported +#define B_PCH_SPI_SFDPX_VSCCX_SUSRES BIT25 = ///< Suspend/Resume Supported +#define B_PCH_SPI_SFDPX_VSCCX_SOFTRES BIT24 = ///< Soft Reset Supported +#define B_PCH_SPI_SFDPX_VSCCX_64k_EO_MASK 0x00FF0000 = ///< 64k Erase Opcode (EO_64k) +#define B_PCH_SPI_SFDPX_VSCCX_4k_EO_MASK 0x0000FF00 = ///< 4k Erase Opcode (EO_4k) +#define B_PCH_SPI_SFDPX_VSCCX_QER (BIT7 | BIT6 | BIT5) = ///< Quad Enable Requirements +#define B_PCH_SPI_SFDPX_VSCCX_WEWS BIT4 = ///< Write Enable on Write Status +#define B_PCH_SPI_SFDPX_VSCCX_WSR BIT3 = ///< Write Status Required +#define B_PCH_SPI_SFDPX_VSCCX_WG_64B BIT2 = ///< Write Granularity, 0: 1 Byte; 1: 64 Bytes +#define R_PCH_SPI_SFDP1_VSCC1 0xC8 = ///< Vendor Specific Component Capabilities Register(32 bits) +#define R_PCH_SPI_PINTX 0xCC = ///< Parameter Table Index +#define N_PCH_SPI_PINTX_SPT 14 +#define V_PCH_SPI_PINTX_SPT_CPT0 0x0 = ///< Component 0 Property Parameter Table +#define V_PCH_SPI_PINTX_SPT_CPT1 0x1 = ///< Component 1 Property Parameter Table +#define N_PCH_SPI_PINTX_HORD 12 +#define V_PCH_SPI_PINTX_HORD_SFDP 0x0 = ///< SFDP Header +#define V_PCH_SPI_PINTX_HORD_PT 0x1 = ///< Parameter Table Header +#define V_PCH_SPI_PINTX_HORD_DATA 0x2 = ///< Data +#define R_PCH_SPI_PTDATA 0xD0 = ///< Parameter Table Data +#define R_PCH_SPI_SBRS 0xD4 = ///< SPI Bus Requester Status +#define R_PCH_SPI_SSML 0xF0 = ///< Set Strap Msg Lock +#define B_PCH_SPI_SSML_SSL BIT0 = ///< Set_Strap Lock +#define R_PCH_SPI_SSMC 0xF4 = ///< Set Strap Msg Control +#define B_PCH_SPI_SSMC_SSMS BIT0 = ///< Set_Strap Mux Select +#define R_PCH_SPI_SSMD 0xF8 = ///< Set Strap Msg Data +// +// @todo Follow up with EDS owner if it should be 3FFF or FFFF. +// +#define B_PCH_SPI_SRD_SSD 0x0000FFFF = ///< Set_Strap Data +// +// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0 +// +#define R_PCH_SPI_FDBAR_FLVALSIG 0x00 = ///< Flash Valid Signature +#define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A +#define R_PCH_SPI_FDBAR_FLASH_MAP0 0x04 +#define B_PCH_SPI_FDBAR_FCBA 0x000000FF = ///< Flash Component Base Address +#define B_PCH_SPI_FDBAR_NC 0x00000300 = ///< Number Of Components +#define N_PCH_SPI_FDBAR_NC 8 = ///< Number Of Components +#define V_PCH_SPI_FDBAR_NC_1 0x00000000 +#define V_PCH_SPI_FDBAR_NC_2 0x00000100 +#define B_PCH_SPI_FDBAR_FRBA 0x00FF0000 = ///< Flash Region Base Address +#define B_PCH_SPI_FDBAR_NR 0x07000000 = ///< Number Of Regions +#define R_PCH_SPI_FDBAR_FLASH_MAP1 0x08 +#define B_PCH_SPI_FDBAR_FMBA 0x000000FF = ///< Flash Master Base Address +#define B_PCH_SPI_FDBAR_NM 0x00000700 = ///< Number Of Masters +#define B_PCH_SPI_FDBAR_FPSBA 0x00FF0000 = ///< PCH Strap Base Address, [23:16] represents [11:4] +#define N_PCH_SPI_FDBAR_FPSBA 16 = ///< PCH Strap base Address bit position +#define N_PCH_SPI_FDBAR_FPSBA_REPR 4 = ///< PCH Strap base Address bit represents position +#define B_PCH_SPI_FDBAR_PCHSL 0xFF000000 = ///< PCH Strap Length, [31:24] represents number of Dwords +#define N_PCH_SPI_FDBAR_PCHSL 24 = ///< PCH Strap Length bit position +#define R_PCH_SPI_FDBAR_FLASH_MAP2 0x0C +#define B_PCH_SPI_FDBAR_FCPUSBA 0x000000FF = ///< CPU Strap Base Address, [7:0] represents [11:4] +#define N_PCH_SPI_FDBAR_FCPUSBA 0 = ///< CPU Strap Base Address bit position +#define N_PCH_SPI_FDBAR_FCPUSBA_REPR 4 = ///< CPU Strap Base Address bit represents position +#define B_PCH_SPI_FDBAR_CPUSL 0x0000FF00 = ///< CPU Strap Length, [15:8] represents number of Dwords +#define N_PCH_SPI_FDBAR_CPUSL 8 = ///< CPU Strap Length bit position +// +// Flash Component Base Address (FCBA) from Flash Region 0 +// +#define R_PCH_SPI_FCBA_FLCOMP 0x00 = ///< Flash Components Register +#define B_PCH_SPI_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27) = ///< Read ID and Read Status Clock Frequency +#define B_PCH_SPI_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24) = ///< Write and Erase Clock Frequency +#define B_PCH_SPI_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21) = ///< Fast Read Clock Frequency +#define B_PCH_SPI_FLCOMP_FR_SUP BIT20 = ///< Fast Read Support. +#define B_PCH_SPI_FLCOMP_RC_FREQ (BIT19 | BIT18 | BIT17) = ///< Read Clock Frequency. +#define V_PCH_SPI_FLCOMP_FREQ_48MHZ 0x02 +#define V_PCH_SPI_FLCOMP_FREQ_30MHZ 0x04 +#define V_PCH_SPI_FLCOMP_FREQ_17MHZ 0x06 +#define B_PCH_SPI_FLCOMP_COMP1_MASK 0xF0 = ///< Flash Component 1 Size MASK +#define N_PCH_SPI_FLCOMP_COMP1 4 = ///< Flash Component 1 Size bit position +#define B_PCH_SPI_FLCOMP_COMP0_MASK 0x0F = ///< Flash Component 0 Size MASK +#define V_PCH_SPI_FLCOMP_COMP_512KB 0x80000 +// +// Descriptor Upper Map Section from Flash Region 0 +// +#define R_PCH_SPI_FLASH_UMAP1 0xEFC = ///< Flash Upper Map 1 +#define B_PCH_SPI_FLASH_UMAP1_VTBA 0x000000FF = ///< VSCC Table Base Address +#define B_PCH_SPI_FLASH_UMAP1_VTL 0x0000FF00 = ///< VSCC Table Length + +#define R_PCH_SPI_VTBA_JID0 0x00 = ///< JEDEC-ID 0 Register +#define S_PCH_SPI_VTBA_JID0 0x04 +#define B_PCH_SPI_VTBA_JID0_VID 0x000000FF +#define B_PCH_SPI_VTBA_JID0_DID0 0x0000FF00 +#define B_PCH_SPI_VTBA_JID0_DID1 0x00FF0000 +#define N_PCH_SPI_VTBA_JID0_DID0 0x08 +#define N_PCH_SPI_VTBA_JID0_DID1 0x10 +#define R_PCH_SPI_VTBA_VSCC0 0x04 +#define S_PCH_SPI_VTBA_VSCC0 0x04 + + +// +// SPI Private Configuration Space Registers +// +#define R_PCH_PCR_SPI_CLK_CTL 0xC004 +#define R_PCH_PCR_SPI_PWR_CTL 0xC008 + +// +// MMP0 +// +#define R_PCH_SPI_STRP_MMP0 0xC4 ///< MMP0 Soft strap o= ffset +#define B_PCH_SPI_STRP_MMP0 0x10 ///< MMP0 Soft strap b= it + + +#define R_PCH_SPI_STRP_SFDP 0xF0 ///< PCH Soft Strap SF= DP +#define B_PCH_SPI_STRP_SFDP_QIORE BIT3 = ///< Quad IO Read Enable +#define B_PCH_SPI_STRP_SFDP_QORE BIT2 = ///< Quad Output Read Enable +#define B_PCH_SPI_STRP_SFDP_DIORE BIT1 = ///< Dual IO Read Enable +#define B_PCH_SPI_STRP_SFDP_DORE BIT0 = ///< Dual Output Read Enable + +// +// Descriptor Record 0 +// +#define R_PCH_SPI_STRP_DSCR_0 0x00 ///< PCH Soft Strap 0 +#define B_PCH_SPI_STRP_DSCR_0_PTT_SUPP BIT22 ///< PTT Supported + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsThermal.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/= PchRegsThermal.h new file mode 100644 index 0000000000..dfd6d4e37c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsThe= rmal.h @@ -0,0 +1,93 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_THERMAL_H_ +#define _PCH_REGS_THERMAL_H_ + +// +// Thermal Device Registers (D20:2) +// +#define PCI_DEVICE_NUMBER_PCH_THERMAL 20 +#define PCI_FUNCTION_NUMBER_PCH_THERMAL 2 +#define V_PCH_THERMAL_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_THERMAL_DEVICE_ID 0x8C24 + +// +// LBG Production Thermal Device Device ID +// +#define V_PCH_LBG_PROD_THERMAL_DEVICE_ID 0xA1B1 +// +// LBG SSX (Super SKU) Thermal Device Device ID +// +#define V_PCH_LBG_THERMAL_DEVICE_ID 0xA231 + +#define V_PCH_LP_THERMAL_DEVICE_ID 0x9C24 +#define R_PCH_THERMAL_TBAR 0x10 +#define V_PCH_THERMAL_TBAR_SIZE (4 * 1024) +#define N_PCH_THREMAL_TBAR_ALIGNMENT 12 +#define B_PCH_THERMAL_TBAR_MASK 0xFFFFF000 +#define R_PCH_THERMAL_TBARH 0x14 +#define R_PCH_THERMAL_TBARB 0x40 +#define V_PCH_THERMAL_TBARB_SIZE (4 * 1024) +#define N_PCH_THREMAL_TBARB_ALIGNMENT 12 +#define B_PCH_THERMAL_SPTYPEN BIT0 +#define R_PCH_THERMAL_TBARBH 0x44 +#define B_PCH_THERMAL_TBARB_MASK 0xFFFFF000 + +// +// Thermal TBAR MMIO registers +// +#define R_PCH_TBAR_TSC 0x04 +#define B_PCH_TBAR_TSC_PLD BIT7 +#define B_PCH_TBAR_TSC_CPDE BIT0 +#define R_PCH_TBAR_TSS 0x06 +#define R_PCH_TBAR_TSEL 0x08 +#define B_PCH_TBAR_TSEL_PLD BIT7 +#define B_PCH_TBAR_TSEL_ETS BIT0 +#define R_PCH_TBAR_TSREL 0x0A +#define R_PCH_TBAR_TSMIC 0x0C +#define B_PCH_TBAR_TSMIC_PLD BIT7 +#define B_PCH_TBAR_TSMIC_SMIE BIT0 +#define R_PCH_TBAR_CTT 0x10 +#define R_PCH_TBAR_TAHV 0x14 +#define R_PCH_TBAR_TALV 0x18 +#define R_PCH_TBAR_TSPM 0x1C +#define B_PCH_TBAR_TSPM_LTT (BIT8 | BIT7 | BIT6 | BIT5 | BIT4 = | BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_TBAR_TSPM_LTT 0x0C8 +#define B_PCH_TBAR_TSPM_MAXTSST (BIT11 | BIT10 | BIT9) +#define V_PCH_TBAR_TSPM_MAXTSST (0x4 << 9) +#define B_PCH_TBAR_TSPM_MINTSST BIT12 +#define B_PCH_TBAR_TSPM_DTSSIC0 BIT13 +#define B_PCH_TBAR_TSPM_DTSSS0EN BIT14 +#define B_PCH_TBAR_TSPM_TSPMLOCK BIT15 +#define R_PCH_TBAR_TL 0x40 +#define B_PCH_TBAR_TL_LOCK BIT31 +#define B_PCH_TBAR_TL_TTEN BIT29 +#define R_PCH_TBAR_TL2 0x50 +#define R_PCH_TBAR_TL2_LOCK BIT15 +#define R_PCH_TBAR_TL2_PMCTEN BIT14 +#define R_PCH_TBAR_PHL 0x60 +#define B_PCH_TBAR_PHLE BIT15 +#define R_PCH_TBAR_PHLC 0x62 +#define B_PCH_TBAR_PHLC_LOCK BIT0 +#define R_PCH_TBAR_TAS 0x80 +#define R_PCH_TBAR_TSPIEN 0x82 +#define R_PCH_TBAR_TSGPEN 0x84 +#define B_PCH_TBAR_TL2_PMCTEN BIT14 +#define R_PCH_TBAR_A4 0xA4 +#define R_PCH_TBAR_C0 0xC0 +#define R_PCH_TBAR_C4 0xC4 +#define R_PCH_TBAR_C8 0xC8 +#define R_PCH_TBAR_CC 0xCC +#define R_PCH_TBAR_D0 0xD0 +#define R_PCH_TBAR_E0 0xE0 +#define R_PCH_TBAR_E4 0xE4 +#define R_PCH_TBAR_E8 0xE8 +#define R_PCH_TBAR_TCFD 0xF0 ///< Thermal c= ontroller function disable +#define B_PCH_TBAR_TCFD_TCD BIT0 ///< Thermal c= ontroller disable + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsTraceHub.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register= /PchRegsTraceHub.h new file mode 100644 index 0000000000..43c2b7c699 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsTra= ceHub.h @@ -0,0 +1,125 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_TRACE_HUB_H_ +#define _PCH_REGS_TRACE_HUB_H_ + +// +// TraceHub Registers (D31:F7) +// +#define PCI_DEVICE_NUMBER_PCH_TRACE_HUB 31 +#define PCI_FUNCTION_NUMBER_PCH_TRACE_HUB 7 + +#define V_PCH_TRACE_HUB_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_TRACE_HUB_DEVICE_ID 0x0963 + +// +// LBG Production (PRQ) TraceHub Device ID +// +#define V_PCH_LBG_PROD_TRACE_HUB_DEVICE_ID 0xA1A6 +// +// LBG SuperSKU (SSX) TraceHub Device ID +// +#define V_PCH_LBG_TRACE_HUB_DEVICE_ID 0xA226 + +#define R_PCH_TRACE_HUB_CSR_MTB_LBAR 0x10 +#define B_PCH_TRACE_HUB_CSR_MTB_RBAL 0xFFF00000 +#define R_PCH_TRACE_HUB_CSR_MTB_UBAR 0x14 +#define B_PCH_TRACE_HUB_CSR_MTB_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_SW_LBAR 0x18 +#define B_PCH_TRACE_HUB_SW_RBAL 0xFFE00000 +#define R_PCH_TRACE_HUB_SW_UBAR 0x1C +#define B_PCH_TRACE_HUB_SW_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_RTIT_LBAR 0x20 +#define B_PCH_TRACE_HUB_RTIT_RBAL 0xFFFFFF00 +#define R_PCH_TRACE_HUB_RTIT_UBAR 0x24 +#define B_PCH_TRACE_HUB_RTIT_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_MSICID 0x40 +#define R_PCH_TRACE_HUB_MSINCP 0x41 +#define R_PCH_TRACE_HUB_MSIMC 0x42 +#define R_PCH_TRACE_HUB_MSILMA 0x44 +#define R_PCH_TRACE_HUB_MSIUMA 0x48 +#define R_PCH_TRACE_HUB_MSIMD 0x4C +#define B_PCH_TRACE_HUB_FW_RBAL 0xFFFC0000 +#define B_PCH_TRACE_HUB_FW_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_DSC 0x80 +#define B_PCH_TRACE_HUB_BYP BIT0 //< TraceHub By= pass +#define R_PCH_TRACE_HUB_DSS 0x81 +#define R_PCH_TRACE_HUB_ISTOT 0x84 +#define R_PCH_TRACE_HUB_ICTOT 0x88 +#define R_PCH_TRACE_HUB_IPAD 0x8C +#define R_PCH_TRACE_HUB_DSD 0x90 + +// +// Offsets from CSR_MTB_BAR +// +#define R_PCH_TRACE_HUB_MTB_GTHOPT0 0x00 +#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P0FLUSH BIT7 +#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P1FLUSH BIT15 +#define V_PCH_TRACE_HUB_MTB_SWDEST_PTI 0x0A +#define V_PCH_TRACE_HUB_MTB_SWDEST_MEMEXI 0x08 +#define V_PCH_TRACE_HUB_MTB_SWDEST_DISABLE 0x00 +#define R_PCH_TRACE_HUB_MTB_SWDEST_1 0x0C +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_1 0x0000000F +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_2 0x000000F0 +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_3 0x00000F00 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_1 0x0000F000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_2 0x000F0000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_3 0x00F00000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_AUDIO 0x0F000000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_PMC 0xF0000000 +#define R_PCH_TRACE_HUB_MTB_SWDEST_2 0x10 +#define B_PCH_TRACE_HUB_MTB_SWDEST_FTH 0x0000000F +#define R_PCH_TRACE_HUB_MTB_SWDEST_3 0x14 +#define B_PCH_TRACE_HUB_MTB_SWDEST_MAESTRO 0x00000F00 +#define B_PCH_TRACE_HUB_MTB_SWDEST_SKYCAM 0x0F000000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_AET 0xF0000000 +#define R_PCH_TRACE_HUB_MTB_SWDEST_4 0x18 +#define R_PCH_TRACE_HUB_MTB_MSC0CTL 0xA0100 +#define R_PCH_TRACE_HUB_MTB_MSC1CTL 0xA0200 +#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DCI 0x2 +#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DEBUG 0x3 +#define B_PCH_TRACE_HUB_MTB_MSCNLEN (BIT10 | BIT9 | BIT8) +#define B_PCH_TRACE_HUB_MTB_MSCNMODE (BIT5 | BIT4) +#define N_PCH_TRACE_HUB_MTB_MSCNMODE 0x4 +#define B_PCH_TRACE_HUB_MTB_MSCN_RD_HDR_OVRD BIT2 +#define B_PCH_TRACE_HUB_MTB_WRAPENN BIT1 +#define B_PCH_TRACE_HUB_MTB_MSCNEN BIT0 +#define R_PCH_TRACE_HUB_MTB_GTHSTAT 0xD4 +#define R_PCH_TRACE_HUB_MTB_SCR2 0xD8 +#define B_PCH_TRACE_HUB_MTB_SCR2_FCD BIT0 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF2 BIT2 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF3 BIT3 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF4 BIT4 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF5 BIT5 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF6 BIT6 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF7 BIT7 +#define R_PCH_TRACE_HUB_MTB_MSC0BAR 0xA0108 +#define R_PCH_TRACE_HUB_MTB_MSC0SIZE 0xA010C +#define R_PCH_TRACE_HUB_MTB_MSC1BAR 0xA0208 +#define R_PCH_TRACE_HUB_MTB_MSC1SIZE 0xA020C +#define R_PCH_TRACE_HUB_MTB_STREAMCFG1 0xA1000 +#define B_PCH_TRACE_HUB_MTB_STREAMCFG1_ENABLE BIT28 +#define R_PCH_TRACE_HUB_MTB_PTI_CTL 0x1C00 +#define B_PCH_TRACE_HUB_MTB_PTIMODESEL 0xF0 +#define B_PCH_TRACE_HUB_MTB_PTICLKDIV (BIT17 | BIT16) +#define B_PCH_TRACE_HUB_MTB_PATGENMOD (BIT22 | BIT21 | BIT= 20) +#define B_PCH_TRACE_HUB_MTB_PTI_EN BIT0 +#define R_PCH_TRACE_HUB_MTB_SCR 0xC8 +#define R_PCH_TRACE_HUB_MTB_GTH_FREQ 0xCC +#define V_PCH_TRACE_HUB_MTB_SCR 0x00130000 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD0 0xE0 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD1 0xE4 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD10 0xE40 +#define R_PCH_TRACE_HUB_MTB_CTPGCS 0x1C14 +#define B_PCH_TRACE_HUB_MTB_CTPEN BIT0 +#define V_PCH_TRACE_HUB_MTB_CHLCNT 0x80 +#define V_PCH_TRACE_HUB_MTB_STHMSTR 0x20 +#define R_PCH_TRACE_HUB_CSR_MTB_TSUCTRL 0x2000 +#define B_PCH_TRACE_HUB_CSR_MTB_TSUCTRL_CTCRESYNC BIT0 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/Pch= RegsUsb.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchR= egsUsb.h new file mode 100644 index 0000000000..a25e9981b3 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsUsb= .h @@ -0,0 +1,463 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_REGS_USB_H_ +#define _PCH_REGS_USB_H_ + +// +// USB3 (XHCI) related definitions +// +#define PCI_BUS_NUMBER_PCH_XHCI 0 +#define PCI_DEVICE_NUMBER_PCH_XHCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 + +// +// XHCI PCI Config Space registers +// +#define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_USB_DEVICE_ID_XHCI_1 0x8C31 ///< SKL PCH H XHCI#1 +// +// LBG Production (PRQ) XHCI Controller Device ID +// +#define V_PCH_LBG_PROD_USB_DEVICE_ID_XHCI_1 0xA1AF ///< LBG Production DI= D XHCI#1 +// +// LBG Super SKU (SSX) XHCI Controller Device ID +// +#define V_PCH_LBG_USB_DEVICE_ID_XHCI_1 0xA22F ///< LBG Super SKU DID= XHCI#1 +#define V_PCH_LP_USB_DEVICE_ID_XHCI_1 0x9C31 ///< SKL PCH LP XHCI#1 + +#define R_PCH_XHCI_MEM_BASE 0x10 +#define V_PCH_XHCI_MEM_LENGTH 0x10000 +#define N_PCH_XHCI_MEM_ALIGN 16 +#define B_PCH_XHCI_MEM_ALIGN_MASK 0xFFFF + +#define R_PCH_XHCI_XHCC1 0x40 +#define B_PCH_XHCI_XHCC1_ACCTRL BIT31 +#define B_PCH_XHCI_XHCC1_RMTASERR BIT24 +#define B_PCH_XHCI_XHCC1_URD BIT23 +#define B_PCH_XHCI_XHCC1_URRE BIT22 +#define B_PCH_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_DIS 0 +#define V_PCH_XHCI_XHCC1_IIL1E_32 (BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_64 (BIT20) +#define V_PCH_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_256 (BIT21) +#define V_PCH_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_1024 (BIT21 | BIT20) +#define V_PCH_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19) +#define B_PCH_XHCI_XHCC1_XHCIL1E BIT18 +#define B_PCH_XHCI_XHCC1_D3IL1E BIT17 +#define B_PCH_XHCI_XHCC1_UNPPA (BIT16 | BIT15 | BIT14 | BIT13= | BIT12) +#define B_PCH_XHCI_XHCC1_SWAXHCI BIT11 +#define B_PCH_XHCI_XHCC1_L23HRAWC (BIT10 | BIT9 | BIT8) +#define B_PCH_XHCI_XHCC1_UTAGCP (BIT7 | BIT6) +#define B_PCH_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4) +#define B_PCH_XHCI_XHCC1_UDAGCCP (BIT3 | BIT2) +#define B_PCH_XHCI_XHCC1_UDAGC (BIT1 | BIT0) + +#define R_PCH_XHCI_XHCC2 0x44 +#define B_PCH_XHCI_XHCC2_OCCFDONE BIT31 +#define B_PCH_XHCI_XHCC2_XHCUPRDROE BIT11 +#define B_PCH_XHCI_XHCC2_IOSFSRAD BIT10 +#define B_PCH_XHCI_XHCC2_SWACXIHB (BIT9 | BIT8) +#define B_PCH_XHCI_XHCC2_SWADMIL1IHB (BIT7 | BIT6) +#define B_PCH_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3) +#define B_PCH_XHCI_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0) + +#define R_PCH_XHCI_XHCLKGTEN 0x50 +#define B_PCH_XHCI_XHCLKGTEN_SSLSE BIT26 +#define B_PCH_XHCI_XHCLKGTEN_USB2PLLSE BIT25 +#define B_PCH_XHCI_XHCLKGTEN_IOSFSTCGE BIT24 +#define B_PCH_XHCI_XHCLKGTEN_HSTCGE (BIT23 | BIT22 | BIT21 | BIT20) +#define B_PCH_XHCI_XHCLKGTEN_SSTCGE (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_XHCI_XHCLKGTEN_XHCIGEU3S BIT15 +#define B_PCH_XHCI_XHCLKGTEN_XHCFTCLKSE BIT14 +#define B_PCH_XHCI_XHCLKGTEN_XHCBBTCGIPISO BIT13 +#define B_PCH_XHCI_XHCLKGTEN_XHCHSTCGU2NRWE BIT12 +#define B_PCH_XHCI_XHCLKGTEN_XHCUSB2PLLSDLE (BIT11 | BIT10) +#define B_PCH_XHCI_XHCLKGTEN_HSPLLSUE (BIT9 | BIT8) +#define B_PCH_XHCI_XHCLKGTEN_SSPLLSUE (BIT7 | BIT6 | BIT5) +#define B_PCH_XHCI_XHCLKGTEN_XHCBLCGE BIT4 +#define B_PCH_XHCI_XHCLKGTEN_HSLTCGE BIT3 +#define B_PCH_XHCI_XHCLKGTEN_SSLTCGE BIT2 +#define B_PCH_XHCI_XHCLKGTEN_IOSFBTCGE BIT1 +#define B_PCH_XHCI_XHCLKGTEN_IOSFGBLCGE BIT0 + +#define R_PCH_XHCI_USB_RELNUM 0x60 +#define B_PCH_XHCI_USB_RELNUM 0xFF +#define R_PCH_XHCI_FL_ADJ 0x61 +#define B_PCH_XHCI_FL_ADJ 0x3F +#define R_PCH_XHCI_PWR_CAPID 0x70 +#define B_PCH_XHCI_PWR_CAPID 0xFF +#define R_PCH_XHCI_NXT_PTR1 0x71 +#define B_PCH_XHCI_NXT_PTR1 0xFF +#define R_PCH_XHCI_PWR_CAP 0x72 +#define B_PCH_XHCI_PWR_CAP_PME_SUP 0xF800 +#define B_PCH_XHCI_PWR_CAP_D2_SUP BIT10 +#define B_PCH_XHCI_PWR_CAP_D1_SUP BIT9 +#define B_PCH_XHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_PCH_XHCI_PWR_CAP_DSI BIT5 +#define B_PCH_XHCI_PWR_CAP_PME_CLK BIT3 +#define B_PCH_XHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_XHCI_PWR_CNTL_STS 0x74 +#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15 +#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) +#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) +#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8 +#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) +#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) +#define R_PCH_XHCI_MSI_MCTL 0x82 +#define R_PCH_XHCI_U2OCM 0xB0 +#define R_PCH_XHCI_U3OCM 0xD0 +#define V_PCH_XHCI_NUMBER_OF_OC_PINS 8 + +#define R_PCH_XHCI_FUS 0xE0 +#define B_PCH_XHCI_FUS_USBR (BIT5) +#define V_PCH_XHCI_FUS_USBR_EN 0 +#define V_PCH_XHCI_FUS_USBR_DIS (BIT5) + +#define R_PCH_XHCI_FC 0xFC + +#define B_PCH_XHCI_FUS_SSPRTCNT (BIT4 | BIT3) +#define V_PCH_XHCI_FUS_SSPRTCNT_00B 0 +#define V_PCH_XHCI_FUS_SSPRTCNT_01B (BIT3) +#define V_PCH_XHCI_FUS_SSPRTCNT_10B (BIT4) +#define V_PCH_XHCI_FUS_SSPRTCNT_11B (BIT4 | BIT3) + +#define B_PCH_XHCI_FUS_HSPRTCNT (BIT2 | BIT1) +#define V_PCH_XHCI_FUS_HSPRTCNT_00B 0 +#define V_PCH_XHCI_FUS_HSPRTCNT_01B (BIT1) +#define V_PCH_XHCI_FUS_HSPRTCNT_10B (BIT2) +#define V_PCH_XHCI_FUS_HSPRTCNT_11B (BIT2 | BIT1) + +#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_CNT 6 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_CNT 4 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_CNT 2 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_CNT 0 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_MASK 0x3F +#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_MASK 0x0F +#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_MASK 0x03 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_MASK 0x00 + +#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_CNT 14 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_CNT 12 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_CNT 10 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_CNT 8 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_MASK 0x3FFF +#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_MASK 0x3F3F +#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_MASK 0x03FF +#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_MASK 0x00FF + +#define V_PCH_LP_XHCI_FIXED_SSPRTCNT 4 +#define V_PCH_LP_XHCI_FIXED_SSPRTCNT_MASK 0x0F + +#define V_PCH_LP_XHCI_FIXED_HSPRTCNT 8 +#define V_PCH_LP_XHCI_FIXED_HSPRTCNT_MASK 0x00FF + +// +// xHCI MMIO registers +// + +// +// 0x00 - 0x1F - Capability Registers +// +#define R_PCH_XHCI_CAPLENGTH 0x00 +#define R_PCH_XHCI_HCIVERSION 0x02 +#define R_PCH_XHCI_HCSPARAMS1 0x04 +#define R_PCH_XHCI_HCSPARAMS2 0x08 +#define R_PCH_XHCI_HCSPARAMS3 0x0C +#define B_PCH_XHCI_HCSPARAMS3_U2DEL 0xFFFF0000 +#define B_PCH_XHCI_HCSPARAMS3_U1DEL 0x0000FFFF +#define R_PCH_XHCI_HCCPARAMS 0x10 +#define B_PCH_XHCI_HCCPARAMS_LHRC BIT5 +#define B_PCH_XHCI_HCCPARAMS_MAXPSASIZE 0xF000 +#define R_PCH_XHCI_DBOFF 0x14 +#define R_PCH_XHCI_RTSOFF 0x18 + +// +// 0x80 - 0xBF - Operational Registers +// +#define R_PCH_XHCI_USBCMD 0x80 +#define B_PCH_XHCI_USBCMD_RS BIT0 ///< Run/Stop +#define B_PCH_XHCI_USBCMD_RST BIT1 ///< HCRST +#define R_PCH_XHCI_USBSTS 0x84 +#define B_PCH_XHCI_USBSTS_HCH BIT0 +#define B_PCH_XHCI_USBSTS_CNR BIT11 + +// +// 0x480 - 0x5CF - Port Status and Control Registers +// +#define R_PCH_LP_XHCI_PORTSC01USB2 0x480 +#define R_PCH_LP_XHCI_PORTSC02USB2 0x490 +#define R_PCH_LP_XHCI_PORTSC03USB2 0x4A0 +#define R_PCH_LP_XHCI_PORTSC04USB2 0x4B0 +#define R_PCH_LP_XHCI_PORTSC05USB2 0x4C0 +#define R_PCH_LP_XHCI_PORTSC06USB2 0x4D0 +#define R_PCH_LP_XHCI_PORTSC07USB2 0x4E0 +#define R_PCH_LP_XHCI_PORTSC08USB2 0x4F0 +#define R_PCH_LP_XHCI_PORTSC09USB2 0x500 +#define R_PCH_LP_XHCI_PORTSC10USB2 0x510 + + +#define R_PCH_LP_XHCI_PORTSC01USB3 0x540 +#define R_PCH_LP_XHCI_PORTSC02USB3 0x550 +#define R_PCH_LP_XHCI_PORTSC03USB3 0x560 +#define R_PCH_LP_XHCI_PORTSC04USB3 0x570 +#define R_PCH_LP_XHCI_PORTSC05USB3 0x580 +#define R_PCH_LP_XHCI_PORTSC06USB3 0x590 + +// +// 0x480 - 0x5CF - Port Status and Control Registers +// +#define R_PCH_H_XHCI_PORTSC01USB2 0x480 +#define R_PCH_H_XHCI_PORTSC02USB2 0x490 +#define R_PCH_H_XHCI_PORTSC03USB2 0x4A0 +#define R_PCH_H_XHCI_PORTSC04USB2 0x4B0 +#define R_PCH_H_XHCI_PORTSC05USB2 0x4C0 +#define R_PCH_H_XHCI_PORTSC06USB2 0x4D0 +#define R_PCH_H_XHCI_PORTSC07USB2 0x4E0 +#define R_PCH_H_XHCI_PORTSC08USB2 0x4F0 +#define R_PCH_H_XHCI_PORTSC09USB2 0x500 +#define R_PCH_H_XHCI_PORTSC10USB2 0x510 +#define R_PCH_H_XHCI_PORTSC11USB2 0x520 +#define R_PCH_H_XHCI_PORTSC12USB2 0x530 +#define R_PCH_H_XHCI_PORTSC13USB2 0x540 +#define R_PCH_H_XHCI_PORTSC14USB2 0x550 + +#define R_PCH_H_XHCI_PORTSC15USBR 0x560 +#define R_PCH_H_XHCI_PORTSC16USBR 0x570 + +#define R_PCH_H_XHCI_PORTSC01USB3 0x580 +#define R_PCH_H_XHCI_PORTSC02USB3 0x590 +#define R_PCH_H_XHCI_PORTSC03USB3 0x5A0 +#define R_PCH_H_XHCI_PORTSC04USB3 0x5B0 +#define R_PCH_H_XHCI_PORTSC05USB3 0x5C0 +#define R_PCH_H_XHCI_PORTSC06USB3 0x5D0 +#define R_PCH_H_XHCI_PORTSC07USB3 0x5E0 +#define R_PCH_H_XHCI_PORTSC08USB3 0x5F0 +#define R_PCH_H_XHCI_PORTSC09USB3 0x600 +#define R_PCH_H_XHCI_PORTSC10USB3 0x610 + +#define B_PCH_XHCI_PORTSCXUSB2_WPR BIT31 ///< Warm Port Reset +#define B_PCH_XHCI_PORTSCXUSB2_CEC BIT23 ///< Port Config Error = Change +#define B_PCH_XHCI_PORTSCXUSB2_PLC BIT22 ///< Port Link State Ch= ange +#define B_PCH_XHCI_PORTSCXUSB2_PRC BIT21 ///< Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB2_OCC BIT20 ///< Over-current Change +#define B_PCH_XHCI_PORTSCXUSB2_WRC BIT19 ///< Warm Port Reset Ch= ange +#define B_PCH_XHCI_PORTSCXUSB2_PEC BIT18 ///< Port Enabled Disab= led Change +#define B_PCH_XHCI_PORTSCXUSB2_CSC BIT17 ///< Connect Status Cha= nge +#define B_PCH_XHCI_PORTSCXUSB2_LWS BIT16 ///< Port Link State Wr= ite Strobe +#define B_PCH_XHCI_USB2_U3_EXIT (BIT5 | BIT6 | BIT7 | BIT8) +#define B_PCH_XHCI_USB2_U0_MASK (BIT5 | BIT6 | BIT7 | BIT8) +#define B_PCH_XHCI_PORTSCXUSB2_PP BIT9 +#define B_PCH_XHCI_PORTSCXUSB2_PLS (BIT5 | BIT6 | BIT7 | BIT8) /= //< Port Link State +#define B_PCH_XHCI_PORTSCXUSB2_PR BIT4 ///< Port Reset +#define B_PCH_XHCI_PORTSCXUSB2_PED BIT1 ///< Port Enable/Disabl= ed +#define B_PCH_XHCI_PORTSCXUSB2_CCS BIT0 ///< Current Connect St= atus +#define B_PCH_XHCI_PORT_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB2_CEC | = B_PCH_XHCI_PORTSCXUSB2_PLC | B_PCH_XHCI_PORTSCXUSB2_PRC | B_PCH_XHCI_PORTSC= XUSB2_OCC | B_PCH_XHCI_PORTSCXUSB2_WRC | B_PCH_XHCI_PORTSCXUSB2_PEC | B_PCH= _XHCI_PORTSCXUSB2_CSC | B_PCH_XHCI_PORTSCXUSB2_PED) +#define B_PCH_XHCI_PORTPMSCXUSB2_PTC (BIT28 | BIT29 | BIT30 | BIT31= ) ///< Port Test Control + +#define B_PCH_XHCI_PORTSCXUSB3_WPR BIT31 ///< Warm Port Reset +#define B_PCH_XHCI_PORTSCXUSB3_CEC BIT23 ///< Port Config Error = Change +#define B_PCH_XHCI_PORTSCXUSB3_PLC BIT22 ///< Port Link State Ch= ange +#define B_PCH_XHCI_PORTSCXUSB3_PRC BIT21 ///< Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB3_OCC BIT20 ///< Over-current Change +#define B_PCH_XHCI_PORTSCXUSB3_WRC BIT19 ///< Warm Port Reset Ch= ange +#define B_PCH_XHCI_PORTSCXUSB3_PEC BIT18 ///< Port Enabled Disab= led Change +#define B_PCH_XHCI_PORTSCXUSB3_CSC BIT17 ///< Connect Status Cha= nge +#define B_PCH_XHCI_PORTSCXUSB3_PP BIT9 ///< Port Power +#define B_PCH_XHCI_PORTSCXUSB3_PLS (BIT8 | BIT7 | BIT6 | BIT5) = ///< Port Link State +#define V_PCH_XHCI_PORTSCXUSB3_PLS_POLLING 0x000000E0 ///< Link is in = the Polling State +#define V_PCH_XHCI_PORTSCXUSB3_PLS_RXDETECT 0x000000A0 ///< Link is in = the RxDetect State +#define B_PCH_XHCI_PORTSCXUSB3_PR BIT4 ///< Port Reset +#define B_PCH_XHCI_PORTSCXUSB3_PED BIT1 ///< Port Enable/Disabl= ed +#define B_PCH_XHCI_PORTSCXUSB3_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB3= _CEC | B_PCH_XHCI_PORTSCXUSB3_PLC | B_PCH_XHCI_PORTSCXUSB3_PRC | B_PCH_XHCI= _PORTSCXUSB3_OCC | B_PCH_XHCI_PORTSCXUSB3_WRC | B_PCH_XHCI_PORTSCXUSB3_PEC = | B_PCH_XHCI_PORTSCXUSB3_CSC | B_PCH_XHCI_PORTSCXUSB3_PED) +// +// 0x2000 - 0x21FF - Runtime Registers +// 0x3000 - 0x307F - Doorbell Registers +// +#define R_PCH_XHCI_XECP_SUPP_USB2_2 0x8008 +#define R_PCH_XHCI_XECP_SUPP_USB3_2 0x8028 +#define R_PCH_XHCI_HOST_CTRL_SCH_REG 0x8094 +#define R_PCH_XHCI_HOST_CTRL_IDMA_REG 0x809C +#define R_PCH_XHCI_PMCTRL 0x80A4 +#define R_PCH_XHCI_PGCBCTRL 0x80A8 ///< PGCB Control +#define R_PCH_XHCI_HOST_CTRL_MISC_REG 0x80B0 ///< Host Controll= er Misc Reg +#define R_PCH_XHCI_HOST_CTRL_MISC_REG_2 0x80B4 ///< Host Controll= er Misc Reg 2 +#define R_PCH_XHCI_SSPE 0x80B8 ///< Super Speed P= ort Enables +#define B_PCH_XHCI_LP_SSPE_MASK 0x3F ///< LP: Mask for = 6 USB3 ports +#define B_PCH_XHCI_H_SSPE_MASK 0x3FF ///< H: Mask for 1= 0 USB3 ports +#define R_PCH_XHCI_DUAL_ROLE_CFG0 0x80D8 +#define R_PCH_XHCI_DUAL_ROLE_CFG1 0x80DC +#define R_PCH_XHCI_AUX_CTRL_REG1 0x80E0 +#define R_PCH_XHCI_HOST_CTRL_PORT_LINK_REG 0x80EC ///< SuperSpeed Po= rt Link Control +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG1 0x818C ///< Command Manag= er Control 1 +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG2 0x8190 ///< Command Manag= er Control 2 +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG3 0x8194 ///< Command Manag= er Control 3 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW1 0x80F0 ///< USB2_LINK_MGR= _CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW2 0x80F4 ///< USB2_LINK_MGR= _CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW3 0x80F8 ///< USB2_LINK_MGR= _CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW4 0x80FC ///< USB2_LINK_MGR= _CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_HOST_CTRL_TRM_REG2 0x8110 ///< HOST_CTRL_TRM= _REG2 - Host Controller Transfer Manager Control 2 +#define R_PCH_XHCI_AUX_CTRL_REG2 0x8154 ///< AUX_CTRL_REG2= - Aux PM Control Register 2 +#define R_PCH_XHCI_AUXCLKCTL 0x816C ///< xHCI Aux Cloc= k Control Register +#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG0 0x8140 ///< HOST_IF_PWR_C= TRL_REG0 - Power Scheduler Control 0 +#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG1 0x8144 ///< HOST_IF_PWR_C= TRL_REG1 - Power Scheduler Control 1 +#define R_PCH_XHCI_XHCLTVCTL2 0x8174 ///< xHC Latency T= olerance Parameters - LTV Control +#define R_PCH_XHCI_LTVHIT 0x817C ///< xHC Latency T= olerance Parameters - High Idle Time Control +#define R_PCH_XHCI_LTVMIT 0x8180 ///< xHC Latency T= olerance Parameters - Medium Idle Time Control +#define R_PCH_XHCI_LTVLIT 0x8184 ///< xHC Latency T= olerance Parameters - Low Idle Time Control +#define R_PCH_XHCI_USB2PHYPM 0x8164 ///< USB2 PHY Powe= r Management Control +#define R_PCH_XHCI_PDDIS 0x8198 ///< xHC Pulldown = Disable Control +#define R_PCH_XHCI_THROTT 0x819C ///< XHCI Throttle= Control +#define R_PCH_XHCI_LFPSPM 0x81A0 ///< LFPS PM Contr= ol +#define R_PCH_XHCI_THROTT2 0x81B4 ///< XHCI Throttle +#define R_PCH_XHCI_LFPSONCOUNT 0x81B8 ///< LFPS On Count +#define R_PCH_XHCI_D0I2CTRL 0x81BC ///< D0I2 Control = Register +#define R_PCH_XHCI_USB2PMCTRL 0x81C4 ///< USB2 Power Ma= nagement Control + +// +// SKL PCH LP FUSE +// +#define R_PCH_XHCI_LP_FUSE1 0x8410 +#define B_PCH_XHCI_LP_FUS_HSPRTCNT (BIT1) +#define B_PCH_XHCI_LP_FUS_USBR (BIT5) +#define R_PCH_XHCI_STRAP2 0x8420 ///< USB3 Mode Str= ap +#define R_PCH_XHCI_USBLEGCTLSTS 0x8470 ///< USB Legacy Su= pport Control Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIBAR BIT31 ///< SMI on BAR St= atus +#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCIC BIT30 ///< SMI on PCI Co= mmand Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSC BIT29 ///< SMI on OS Own= ership Change Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIBARE BIT15 ///< SMI on BAR En= able +#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCICE BIT14 ///< SMI on PCI Co= mmand Enable +#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSOE BIT13 ///< SMI on OS Own= ership Enable +#define B_PCH_XHCI_USBLEGCTLSTS_SMIHSEE BIT4 ///< SMI on Host S= ystem Error Enable +#define B_PCH_XHCI_USBLEGCTLSTS_USBSMIE BIT0 ///< USB SMI Enable + +// +// Extended Capability Registers +// +#define R_PCH_XHCI_USB2PDO 0x84F8 +#define B_PCH_XHCI_LP_USB2PDO_MASK 0x3FF ///< LP: Mask for = 10 USB2 ports +#define B_PCH_XHCI_H_USB2PDO_MASK 0x7FFF ///< H: Mask for 1= 4 USB2 ports +#define B_PCH_XHCI_USB2PDO_DIS_PORT0 BIT0 + +#define R_PCH_XHCI_USB3PDO 0x84FC +#define B_PCH_XHCI_LP_USB3PDO_MASK 0x3F ///< LP: Mask for = 6 USB3 ports +#define B_PCH_XHCI_H_USB3PDO_MASK 0x3FF ///< H: Mask for 1= 0 USB3 ports +#define B_PCH_XHCI_USB3PDO_DIS_PORT0 BIT0 + +// +// Debug Capability Descriptor Parameters +// +#define R_PCH_XHCI_DBC_DBCCTL 0x8760 ///< DBCCTL - Db= C Control + +// +// xDCI (OTG) USB Device Controller +// +#define PCI_DEVICE_NUMBER_PCH_XDCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1 + +// +// xDCI (OTG) PCI Config Space Registers +// +#define R_PCH_XDCI_MEM_BASE 0x10 +#define V_PCH_XDCI_MEM_LENGTH 0x200000 +#define R_PCH_XDCI_PMCSR 0x84 ///< Power Management = Control and Status Register +#define R_PCH_XDCI_GENERAL_PURPOSER_REG1 0xA0 ///< General Purpose P= CI RW Register1 +#define R_PCH_XDCI_CPGE 0xA2 ///< Chassis Power Gat= e Enable +#define R_PCH_XDCI_GENERAL_PURPOSER_REG4 0xAC ///< General Purpose P= CI RW Register4 +#define R_PCH_OTG_GENERAL_INPUT_REG 0xC0 ///< General Input Reg= ister + +// +// xDCI (OTG) MMIO registers +// +#define R_PCH_XDCI_GCTL 0xC110 ///< Xdci Global Ctrl +#define B_PCH_XDCI_GCTL_GHIBEREN BIT1 ///< Hibernation ena= ble +#define R_PCH_XDCI_GUSB2PHYCFG 0xC200 ///< Global USB2 PHY= Configuration Register +#define B_PCH_XDCI_GUSB2PHYCFG_SUSPHY BIT6 ///< Suspend USB2.0 = HS/FS/LS PHY +#define R_PCH_XDCI_GUSB3PIPECTL0 0xC2C0 ///< Global USB3 PIP= E Control Register 0 +#define B_PCH_XDCI_GUSB3PIPECTL0_UX_IN_PX BIT27 ///< Ux Exit in Px +#define R_PCH_XDCI_APBFC_U3PMU_CFG2 0x10F810 +#define R_PCH_XDCI_APBFC_U3PMU_CFG4 0x10F818 + +// +// xDCI (OTG) Private Configuration Registers +// (PID:OTG) +// +#define R_PCH_PCR_OTG_IOSF_A2 0xA2 +#define R_PCH_PCR_OTG_IOSF_PMCTL 0x1D0 +#define R_PCH_PCR_OTG_PCICFGCTRL1 0x200 +#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 0x0FF00000 +#define N_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 20 +#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 0x000FF000 +#define N_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 12 +#define B_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 0x00000F00 +#define N_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 8 +#define B_PCH_PCR_OTG_PCICFGCTRL_BAR1_DIS 0x00000080 +#define B_PCH_PCR_OTG_PCICFGCTRL_PME_SUP 0x0000007C +#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_INT_EN 0x00000002 +#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_CFG_DIS 0x00000001 + +// +// USB2 Private Configuration Registers +// USB2 HIP design featured +// (PID:USB2) +// +#define R_PCH_PCR_USB2_GLOBAL_PORT 0x4001 ///< USB2 GLOBAL P= ORT +#define R_PCH_PCR_USB2_400C 0x400C +#define R_PCH_PCR_USB2_PP_LANE_BASE_ADDR 0x4000 ///< PP LANE base = address +#define V_PCH_PCR_USB2_PER_PORT 0x00 ///< USB2 PER PORT= Addr[7:2] =3D 0x00 +#define V_PCH_PCR_USB2_UTMI_MISC_PER_PORT 0x08 ///< UTMI MISC REG= PER PORT Addr[7:2] =3D 0x08 +#define V_PCH_PCR_USB2_PER_PORT_2 0x26 ///< USB2 PER PORT= 2 Addr[7:2] =3D 0x26 +#define R_PCH_PCR_USB2_402A 0x402A +#define R_PCH_PCR_USB2_GLB_ADP_VBUS_REG 0x402B ///< GLB ADP VBUS = REG +#define R_PCH_PCR_USB2_GLOBAL_PORT_2 0x402C ///< USB2 GLOBAL P= ORT 2 +#define R_PCH_PCR_USB2_7034 0x7034 +#define R_PCH_PCR_USB2_7038 0x7038 +#define R_PCH_PCR_USB2_703C 0x703C +#define R_PCH_PCR_USB2_7040 0x7040 +#define R_PCH_PCR_USB2_7044 0x7044 +#define R_PCH_PCR_USB2_7048 0x7048 +#define R_PCH_PCR_USB2_704C 0x704C +#define R_PCH_PCR_USB2_CFG_COMPBG 0x7F04 ///< USB2 COMPBG + +// +// xHCI SSIC registers +// +#define R_PCH_XHCI_SSIC_GLOBAL_CONF_CTRL 0x8804 ///< SSIC Global C= onfiguration Control +#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_1 0x8808 ///< SSIC Configur= ation Register 1 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_1 0x880C ///< SSIC Configur= ation Register 2 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_1 0x8810 ///< SSIC Configur= ation Register 3 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_2 0x8838 ///< SSIC Configur= ation Register 1 Port 2 +#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_2 0x883C ///< SSIC Configur= ation Register 2 Port 2 +#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_2 0x8840 ///< SSIC Configur= ation Register 3 Port 2 +#define B_PCH_XHCI_SSIC_CONF_REG2_PORT_UNUSED BIT31 +#define B_PCH_XHCI_SSIC_CONF_REG2_PROG_DONE BIT30 + +#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_1 0x8900 ///< Profile Attri= butes: Port 1 ... N +#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_1 0x8904 ///< SSIC Port N R= egister Access Control: Port 1 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_0C 0x890C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_10 0x8910 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_14 0x8914 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_18 0x8918 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_1C 0x891C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_20 0x8920 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_24 0x8924 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_28 0x8928 + +#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_2 0x8A10 ///< Profile Attri= butes: Port 2 ... N +#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_2 0x8A14 ///< SSIC Port N R= egister Access Control: Port 2 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_0C 0x8A1C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_10 0x8A20 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_14 0x8A24 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_18 0x8A28 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_1C 0x8A2C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_20 0x8A30 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_24 0x8A34 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_28 0x8A38 + +#endif --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Tue, 11 May 2021 02:48:44 -0700 IronPort-SDR: O7nLDFdngSK7cLvBx5aat3MeMiEz2/H/8GystvAAw6EdiRWZaKewomZh9652kZNofb3vU96iii dd5OO+EgmgxA== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="179664953" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="179664953" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:43 -0700 IronPort-SDR: PodRTMAuoPZRdoW9S4oU/JBRj60zwKrLwVkxSCEuJ3m49BQ0upVRC5I1D2n5PVrXOjhCqMbeZy 8egUpzfunmsw== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436573929" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:41 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 03/18] PurleyRefreshSiliconPkg/Pch: Add Public Header Files Date: Tue, 11 May 2021 02:48:11 -0700 Message-Id: <20210511094826.12495-4-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: 96gEAtmY0sqWHPVUmasqnlwex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726538; bh=MxgqFHar6xlAW1iL0FaMPQz6vmvkSQf/8KL2kY2bH0s=; h=Cc:Date:From:Reply-To:Subject:To; b=Bi5Uko+CXfssGjV78U/Zwp2FU76E90d1qE2XL0aSDMRJK9WWSUTpLK7josPXAdQlNM7 pjoBsGVNMgLh4Tah6x2qI1tor1EZy3HLfM8QquYETA55ynvQaVWGzJy2ylIHWg0fEs0yV M2vij27ry9lREoD0z8WSnQbzgvqBX+qI9Gk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../Pch/Include/GpioConfig.h | 230 ++ .../Pch/Include/GpioPinsSklH.h | 298 +++ .../Pch/Include/GpioPinsSklLp.h | 201 ++ .../Pch/Include/Library/GpioLib.h | 777 ++++++ .../Pch/Include/Library/GpioNativeLib.h | 218 ++ .../Pch/Include/Library/PchCycleDecodingLib.h | 344 +++ .../Pch/Include/Library/PchGbeLib.h | 58 + .../Pch/Include/Library/PchInfoLib.h | 231 ++ .../Pch/Include/Library/PchP2sbLib.h | 154 ++ .../Pch/Include/Library/PchPcrLib.h | 190 ++ .../Pch/Include/Library/PchPmcLib.h | 56 + .../Pch/Include/Library/PchPolicyLib.h | 66 + .../Pch/Include/Library/PchSbiAccessLib.h | 156 ++ .../Pch/Include/Library/PchSerialIoLib.h | 212 ++ .../Pch/Include/Library/SpiFlashCommonLib.h | 96 + .../Pch/Include/PchAccess.h | 621 +++++ .../Pch/Include/PchLimits.h | 102 + .../Pch/Include/PchPolicyCommon.h | 2212 +++++++++++++++++ .../Pch/Include/PchReservedResources.h | 81 + .../Pch/Include/PcieRegs.h | 279 +++ .../Pch/Include/Ppi/PchPcieDeviceTable.h | 124 + .../Pch/Include/Ppi/PchPolicy.h | 19 + .../Pch/Include/Ppi/PchReset.h | 93 + .../Pch/Include/Ppi/Spi.h | 25 + .../Pch/Include/Protocol/PchReset.h | 112 + .../Pch/Include/Protocol/Spi.h | 306 +++ .../Pch/Include/SaRegs.h | 700 ++++++ 27 files changed, 7961 insertions(+) create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioC= onfig.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioP= insSklH.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioP= insSklLp.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/GpioLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/GpioNativeLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/PchCycleDecodingLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/PchGbeLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/PchInfoLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/PchP2sbLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/PchPcrLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/PchPmcLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/PchPolicyLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/PchSbiAccessLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/PchSerialIoLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/SpiFlashCommonLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchAc= cess.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchLi= mits.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchPo= licyCommon.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchRe= servedResources.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PcieR= egs.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/P= chPcieDeviceTable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/P= chPolicy.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/P= chReset.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/S= pi.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Proto= col/PchReset.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Proto= col/Spi.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/SaReg= s.h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioConfig.h= b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioConfig.h new file mode 100644 index 0000000000..854dcb645c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioConfig.h @@ -0,0 +1,230 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _GPIO_CONFIG_H_ +#define _GPIO_CONFIG_H_ + +#pragma pack(push, 1) + +/// +/// For any GpioPad usage in code use GPIO_PAD type +/// +typedef UINT32 GPIO_PAD; + + +/// +/// For any GpioGroup usage in code use GPIO_GROUP type +/// +typedef UINT32 GPIO_GROUP; + +/** + GPIO configuration structure used for pin programming. + Structure contains fields that can be used to configure pad. +**/ +typedef struct { + /** + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction (except Inversion), OutputState, + InterruptConfig and Host Software Pad Ownership are unnecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + **/ + UINT32 PadMode : 4; + /** + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + **/ + UINT32 HostSoftPadOwn : 2; + /** + GPIO Direction + Can choose between In, In with inversion Out, both In and Out, both In w= ith inversion and out or disabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + **/ + UINT32 Direction : 5; + /** + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + **/ + UINT32 OutputState : 2; + /** + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting i= s applicable only if GPIO is in input mode. + If GPIO is set to cause an SCI then also Gpe is enabled for this pad. + Refer to definition of GPIO_INT_CONFIG for supported settings. + **/ + UINT32 InterruptConfig : 8; + /** + GPIO Power Configuration. + This setting controls Pad Reset Configuration. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + **/ + UINT32 PowerConfig : 4; + + /** + GPIO Electrical Configuration + This setting controls pads termination and voltage tolerance. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + **/ + UINT32 ElectricalConfig : 7; + + /** + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + **/ + UINT32 LockConfig : 3; + /** + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + **/ + UINT32 OtherSettings : 2; + UINT32 RsvdBits : 27; ///< Reserved bits for future extension + UINT32 RsvdBits1; ///< Reserved bits for future extension +} GPIO_CONFIG; + + +typedef enum { + GpioHardwareDefault =3D 0x0 +} GPIO_HARDWARE_DEFAULT; + +/// +/// GPIO Pad Mode +/// +typedef enum { + GpioPadModeGpio =3D 0x1, + GpioPadModeNative1 =3D 0x3, + GpioPadModeNative2 =3D 0x5, + GpioPadModeNative3 =3D 0x7, + GpioPadModeNative4 =3D 0x9 +} GPIO_PAD_MODE; + +/// +/// Host Software Pad Ownership modes +/// +typedef enum { + GpioHostOwnDefault =3D 0x0, ///< Leave ownership value unmodified + GpioHostOwnAcpi =3D 0x1, ///< Set HOST ownership to ACPI + GpioHostOwnGpio =3D 0x3 ///< Set HOST ownership to GPIO +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault =3D 0x0, ///< Leave pad direction setti= ng unmodified + GpioDirInOut =3D (0x1 | (0x1 << 3)), ///< Set pad for both output a= nd input + GpioDirInInvOut =3D (0x1 | (0x3 << 3)), ///< Set pad for both output a= nd input with inversion + GpioDirIn =3D (0x3 | (0x1 << 3)), ///< Set pad for input only + GpioDirInInv =3D (0x3 | (0x3 << 3)), ///< Set pad for input with in= version + GpioDirOut =3D 0x5, ///< Set pad for output only + GpioDirNone =3D 0x7 ///< Disable both output and i= nput +} GPIO_DIRECTION; + +/// +/// GPIO Output State +/// +typedef enum { + GpioOutDefault =3D 0x0, ///< Leave output value unmodified + GpioOutLow =3D 0x1, ///< Set output to low + GpioOutHigh =3D 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/// +/// GPIO interrupt configuration +/// This setting is applicable only if GPIO is in input mode. +/// GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC= /SCI/SMI/NMI) +/// and how it is triggered (edge or level). +/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to= GpioIntBothEdgecan +/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel +/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad. +/// Not all GPIO are capable of generating an SMI or NMI interrupt +/// + +typedef enum { + GpioIntDefault =3D 0x0, ///< Leave value of interrupt routing = unmodified + GpioIntDis =3D 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI inter= rupt generation + GpioIntNmi =3D 0x3, ///< Enable NMI interrupt only + GpioIntSmi =3D 0x5, ///< Enable SMI interrupt only + GpioIntSci =3D 0x9, ///< Enable SCI interrupt only + GpioIntApic =3D 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel =3D (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge =3D (0x3 << 5), ///< Set interrupt as edge triggered (= type of edge depends on input inversion) + GpioIntLvlEdgDis =3D (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge =3D (0x7 << 5) ///< Set interrupt as both edge trigge= red +} GPIO_INT_CONFIG; + +#define GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CON= FIG for interrupt source +#define GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CON= FIG for interrupt type + +/// +/// GPIO Power Configuration +/// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified +/// Pad Register fields). +/// +typedef enum { + GpioResetDefault =3D 0x0, ///< Leave value of pad reset unmo= dified + GpioResetPwrGood =3D 0x1, ///< Powergood reset + GpioResetDeep =3D 0x3, ///< Deep GPIO Reset + GpioResetNormal =3D 0x5, ///< GPIO Reset + GpioResetResume =3D 0x7 ///< Resume Reset (applicable only= for GPD group) +} GPIO_RESET_CONFIG; + +/// +/// GPIO Electrical Configuration +/// Set GPIO termination and Pad Tolerance (applicable only for some pads) +/// Field from GpioTermDefault to GpioTermNative can be OR'ed with GpioTol= erance1v8. +/// +typedef enum { + GpioTermDefault =3D 0x0, ///< Leave termination setting unmo= dified + GpioTermNone =3D 0x1, ///< none + GpioTermWpd5K =3D 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K =3D 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K =3D 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K =3D 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K =3D 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K =3D 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K =3D 0x1B, ///< 1kOhm & 2kOhm weak pull-up + GpioTermNative =3D 0x1F, ///< Native function controls pads = termination + GpioNoTolerance1v8 =3D (0x1 << 5), ///< Disable 1.8V pad tolerance + GpioTolerance1v8 =3D (0x3 << 5) ///< Enable 1.8V pad tolerance +} GPIO_ELECTRICAL_CONFIG; + +#define GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for = GPIO_ELECTRICAL_CONFIG for termination value +#define GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for = GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting + +/// +/// GPIO LockConfiguration +/// Set GPIO configuration lock and output state lock +/// GpioLockPadConfig and GpioLockOutputState can be OR'ed +/// +typedef enum { + GpioLockDefault =3D 0x0, ///< Leave lock setting unmodified + GpioPadConfigLock =3D 0x3, ///< Lock Pad Configuration + GpioOutputStateLock =3D 0x5 ///< Lock GPIO pad output value +} GPIO_LOCK_CONFIG; + +/// +/// Other GPIO Configuration +/// GPIO_OTHER_CONFIG is used for less often settings and for future exten= sions +/// Supported settings: +/// - RX raw override to '1' - allows to override input value to '1' +/// This setting is applicable only if in input mode (both in GPIO and= native usage). +/// The override takes place at the internal pad state directly from b= uffer and before the RXINV. +/// +typedef enum { + GpioRxRaw1Default =3D 0x0, ///< Use default input override value + GpioRxRaw1Dis =3D 0x1, ///< Don't override input + GpioRxRaw1En =3D 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +#pragma pack(pop) + +#endif //_GPIO_CONFIG_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioPinsSklH= .h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioPinsSklH.h new file mode 100644 index 0000000000..ecd3df3e4d --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioPinsSklH.h @@ -0,0 +1,298 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _GPIO_PINS_SKL_H_H_ +#define _GPIO_PINS_SKL_H_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// +/// +/// SKL H GPIO Groups +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_H_GROUP_GPP_A 0x0100 +#define GPIO_SKL_H_GROUP_GPP_B 0x0101 +#define GPIO_SKL_H_GROUP_GPP_C 0x0102 +#define GPIO_SKL_H_GROUP_GPP_D 0x0103 +#define GPIO_SKL_H_GROUP_GPP_E 0x0104 +#define GPIO_SKL_H_GROUP_GPP_F 0x0105 +#define GPIO_SKL_H_GROUP_GPP_G 0x0106 +#define GPIO_SKL_H_GROUP_GPP_H 0x0107 +#define GPIO_SKL_H_GROUP_GPP_I 0x0108 +#define GPIO_SKL_H_GROUP_GPP_J 0x0109 +#define GPIO_SKL_H_GROUP_GPP_K 0x010A +#define GPIO_SKL_H_GROUP_GPP_L 0x010B +#define GPIO_SKL_H_GROUP_GPD 0x010C + +/// +/// SKL H GPIO pins +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_H_GPP_A0 0x01000000 +#define GPIO_SKL_H_GPP_A1 0x01000001 +#define GPIO_SKL_H_GPP_A2 0x01000002 +#define GPIO_SKL_H_GPP_A3 0x01000003 +#define GPIO_SKL_H_GPP_A4 0x01000004 +#define GPIO_SKL_H_GPP_A5 0x01000005 +#define GPIO_SKL_H_GPP_A6 0x01000006 +#define GPIO_SKL_H_GPP_A7 0x01000007 +#define GPIO_SKL_H_GPP_A8 0x01000008 +#define GPIO_SKL_H_GPP_A9 0x01000009 +#define GPIO_SKL_H_GPP_A10 0x0100000A +#define GPIO_SKL_H_GPP_A11 0x0100000B +#define GPIO_SKL_H_GPP_A12 0x0100000C +#define GPIO_SKL_H_GPP_A13 0x0100000D +#define GPIO_SKL_H_GPP_A14 0x0100000E +#define GPIO_SKL_H_GPP_A15 0x0100000F +#define GPIO_SKL_H_GPP_A16 0x01000010 +#define GPIO_SKL_H_GPP_A17 0x01000011 +#define GPIO_SKL_H_GPP_A18 0x01000012 +#define GPIO_SKL_H_GPP_A19 0x01000013 +#define GPIO_SKL_H_GPP_A20 0x01000014 +#define GPIO_SKL_H_GPP_A21 0x01000015 +#define GPIO_SKL_H_GPP_A22 0x01000016 +#define GPIO_SKL_H_GPP_A23 0x01000017 +#define GPIO_SKL_H_GPP_B0 0x01010000 +#define GPIO_SKL_H_GPP_B1 0x01010001 +#define GPIO_SKL_H_GPP_B2 0x01010002 +#define GPIO_SKL_H_GPP_B3 0x01010003 +#define GPIO_SKL_H_GPP_B4 0x01010004 +#define GPIO_SKL_H_GPP_B5 0x01010005 +#define GPIO_SKL_H_GPP_B6 0x01010006 +#define GPIO_SKL_H_GPP_B7 0x01010007 +#define GPIO_SKL_H_GPP_B8 0x01010008 +#define GPIO_SKL_H_GPP_B9 0x01010009 +#define GPIO_SKL_H_GPP_B10 0x0101000A +#define GPIO_SKL_H_GPP_B11 0x0101000B +#define GPIO_SKL_H_GPP_B12 0x0101000C +#define GPIO_SKL_H_GPP_B13 0x0101000D +#define GPIO_SKL_H_GPP_B14 0x0101000E +#define GPIO_SKL_H_GPP_B15 0x0101000F +#define GPIO_SKL_H_GPP_B16 0x01010010 +#define GPIO_SKL_H_GPP_B17 0x01010011 +#define GPIO_SKL_H_GPP_B18 0x01010012 +#define GPIO_SKL_H_GPP_B19 0x01010013 +#define GPIO_SKL_H_GPP_B20 0x01010014 +#define GPIO_SKL_H_GPP_B21 0x01010015 +#define GPIO_SKL_H_GPP_B22 0x01010016 +#define GPIO_SKL_H_GPP_B23 0x01010017 +#define GPIO_SKL_H_GPP_C0 0x01020000 +#define GPIO_SKL_H_GPP_C1 0x01020001 +#define GPIO_SKL_H_GPP_C2 0x01020002 +#define GPIO_SKL_H_GPP_C3 0x01020003 +#define GPIO_SKL_H_GPP_C4 0x01020004 +#define GPIO_SKL_H_GPP_C5 0x01020005 +#define GPIO_SKL_H_GPP_C6 0x01020006 +#define GPIO_SKL_H_GPP_C7 0x01020007 +#define GPIO_SKL_H_GPP_C8 0x01020008 +#define GPIO_SKL_H_GPP_C9 0x01020009 +#define GPIO_SKL_H_GPP_C10 0x0102000A +#define GPIO_SKL_H_GPP_C11 0x0102000B +#define GPIO_SKL_H_GPP_C12 0x0102000C +#define GPIO_SKL_H_GPP_C13 0x0102000D +#define GPIO_SKL_H_GPP_C14 0x0102000E +#define GPIO_SKL_H_GPP_C15 0x0102000F +#define GPIO_SKL_H_GPP_C16 0x01020010 +#define GPIO_SKL_H_GPP_C17 0x01020011 +#define GPIO_SKL_H_GPP_C18 0x01020012 +#define GPIO_SKL_H_GPP_C19 0x01020013 +#define GPIO_SKL_H_GPP_C20 0x01020014 +#define GPIO_SKL_H_GPP_C21 0x01020015 +#define GPIO_SKL_H_GPP_C22 0x01020016 +#define GPIO_SKL_H_GPP_C23 0x01020017 +#define GPIO_SKL_H_GPP_D0 0x01030000 +#define GPIO_SKL_H_GPP_D1 0x01030001 +#define GPIO_SKL_H_GPP_D2 0x01030002 +#define GPIO_SKL_H_GPP_D3 0x01030003 +#define GPIO_SKL_H_GPP_D4 0x01030004 +#define GPIO_SKL_H_GPP_D5 0x01030005 +#define GPIO_SKL_H_GPP_D6 0x01030006 +#define GPIO_SKL_H_GPP_D7 0x01030007 +#define GPIO_SKL_H_GPP_D8 0x01030008 +#define GPIO_SKL_H_GPP_D9 0x01030009 +#define GPIO_SKL_H_GPP_D10 0x0103000A +#define GPIO_SKL_H_GPP_D11 0x0103000B +#define GPIO_SKL_H_GPP_D12 0x0103000C +#define GPIO_SKL_H_GPP_D13 0x0103000D +#define GPIO_SKL_H_GPP_D14 0x0103000E +#define GPIO_SKL_H_GPP_D15 0x0103000F +#define GPIO_SKL_H_GPP_D16 0x01030010 +#define GPIO_SKL_H_GPP_D17 0x01030011 +#define GPIO_SKL_H_GPP_D18 0x01030012 +#define GPIO_SKL_H_GPP_D19 0x01030013 +#define GPIO_SKL_H_GPP_D20 0x01030014 +#define GPIO_SKL_H_GPP_D21 0x01030015 +#define GPIO_SKL_H_GPP_D22 0x01030016 +#define GPIO_SKL_H_GPP_D23 0x01030017 +#define GPIO_SKL_H_GPP_E0 0x01040000 +#define GPIO_SKL_H_GPP_E1 0x01040001 +#define GPIO_SKL_H_GPP_E2 0x01040002 +#define GPIO_SKL_H_GPP_E3 0x01040003 +#define GPIO_SKL_H_GPP_E4 0x01040004 +#define GPIO_SKL_H_GPP_E5 0x01040005 +#define GPIO_SKL_H_GPP_E6 0x01040006 +#define GPIO_SKL_H_GPP_E7 0x01040007 +#define GPIO_SKL_H_GPP_E8 0x01040008 +#define GPIO_SKL_H_GPP_E9 0x01040009 +#define GPIO_SKL_H_GPP_E10 0x0104000A +#define GPIO_SKL_H_GPP_E11 0x0104000B +#define GPIO_SKL_H_GPP_E12 0x0104000C +#define GPIO_SKL_H_GPP_F0 0x01050000 +#define GPIO_SKL_H_GPP_F1 0x01050001 +#define GPIO_SKL_H_GPP_F2 0x01050002 +#define GPIO_SKL_H_GPP_F3 0x01050003 +#define GPIO_SKL_H_GPP_F4 0x01050004 +#define GPIO_SKL_H_GPP_F5 0x01050005 +#define GPIO_SKL_H_GPP_F6 0x01050006 +#define GPIO_SKL_H_GPP_F7 0x01050007 +#define GPIO_SKL_H_GPP_F8 0x01050008 +#define GPIO_SKL_H_GPP_F9 0x01050009 +#define GPIO_SKL_H_GPP_F10 0x0105000A +#define GPIO_SKL_H_GPP_F11 0x0105000B +#define GPIO_SKL_H_GPP_F12 0x0105000C +#define GPIO_SKL_H_GPP_F13 0x0105000D +#define GPIO_SKL_H_GPP_F14 0x0105000E +#define GPIO_SKL_H_GPP_F15 0x0105000F +#define GPIO_SKL_H_GPP_F16 0x01050010 +#define GPIO_SKL_H_GPP_F17 0x01050011 +#define GPIO_SKL_H_GPP_F18 0x01050012 +#define GPIO_SKL_H_GPP_F19 0x01050013 +#define GPIO_SKL_H_GPP_F20 0x01050014 +#define GPIO_SKL_H_GPP_F21 0x01050015 +#define GPIO_SKL_H_GPP_F22 0x01050016 +#define GPIO_SKL_H_GPP_F23 0x01050017 +#define GPIO_SKL_H_GPP_G0 0x01060000 +#define GPIO_SKL_H_GPP_G1 0x01060001 +#define GPIO_SKL_H_GPP_G2 0x01060002 +#define GPIO_SKL_H_GPP_G3 0x01060003 +#define GPIO_SKL_H_GPP_G4 0x01060004 +#define GPIO_SKL_H_GPP_G5 0x01060005 +#define GPIO_SKL_H_GPP_G6 0x01060006 +#define GPIO_SKL_H_GPP_G7 0x01060007 +#define GPIO_SKL_H_GPP_G8 0x01060008 +#define GPIO_SKL_H_GPP_G9 0x01060009 +#define GPIO_SKL_H_GPP_G10 0x0106000A +#define GPIO_SKL_H_GPP_G11 0x0106000B +#define GPIO_SKL_H_GPP_G12 0x0106000C +#define GPIO_SKL_H_GPP_G13 0x0106000D +#define GPIO_SKL_H_GPP_G14 0x0106000E +#define GPIO_SKL_H_GPP_G15 0x0106000F +#define GPIO_SKL_H_GPP_G16 0x01060010 +#define GPIO_SKL_H_GPP_G17 0x01060011 +#define GPIO_SKL_H_GPP_G18 0x01060012 +#define GPIO_SKL_H_GPP_G19 0x01060013 +#define GPIO_SKL_H_GPP_G20 0x01060014 +#define GPIO_SKL_H_GPP_G21 0x01060015 +#define GPIO_SKL_H_GPP_G22 0x01060016 +#define GPIO_SKL_H_GPP_G23 0x01060017 +#define GPIO_SKL_H_GPP_H0 0x01070000 +#define GPIO_SKL_H_GPP_H1 0x01070001 +#define GPIO_SKL_H_GPP_H2 0x01070002 +#define GPIO_SKL_H_GPP_H3 0x01070003 +#define GPIO_SKL_H_GPP_H4 0x01070004 +#define GPIO_SKL_H_GPP_H5 0x01070005 +#define GPIO_SKL_H_GPP_H6 0x01070006 +#define GPIO_SKL_H_GPP_H7 0x01070007 +#define GPIO_SKL_H_GPP_H8 0x01070008 +#define GPIO_SKL_H_GPP_H9 0x01070009 +#define GPIO_SKL_H_GPP_H10 0x0107000A +#define GPIO_SKL_H_GPP_H11 0x0107000B +#define GPIO_SKL_H_GPP_H12 0x0107000C +#define GPIO_SKL_H_GPP_H13 0x0107000D +#define GPIO_SKL_H_GPP_H14 0x0107000E +#define GPIO_SKL_H_GPP_H15 0x0107000F +#define GPIO_SKL_H_GPP_H16 0x01070010 +#define GPIO_SKL_H_GPP_H17 0x01070011 +#define GPIO_SKL_H_GPP_H18 0x01070012 +#define GPIO_SKL_H_GPP_H19 0x01070013 +#define GPIO_SKL_H_GPP_H20 0x01070014 +#define GPIO_SKL_H_GPP_H21 0x01070015 +#define GPIO_SKL_H_GPP_H22 0x01070016 +#define GPIO_SKL_H_GPP_H23 0x01070017 +#define GPIO_SKL_H_GPP_I0 0x01080000 +#define GPIO_SKL_H_GPP_I1 0x01080001 +#define GPIO_SKL_H_GPP_I2 0x01080002 +#define GPIO_SKL_H_GPP_I3 0x01080003 +#define GPIO_SKL_H_GPP_I4 0x01080004 +#define GPIO_SKL_H_GPP_I5 0x01080005 +#define GPIO_SKL_H_GPP_I6 0x01080006 +#define GPIO_SKL_H_GPP_I7 0x01080007 +#define GPIO_SKL_H_GPP_I8 0x01080008 +#define GPIO_SKL_H_GPP_I9 0x01080009 +#define GPIO_SKL_H_GPP_I10 0x0108000A +#define GPIO_SKL_H_GPP_J0 0x01090000 +#define GPIO_SKL_H_GPP_J1 0x01090001 +#define GPIO_SKL_H_GPP_J2 0x01090002 +#define GPIO_SKL_H_GPP_J3 0x01090003 +#define GPIO_SKL_H_GPP_J4 0x01090004 +#define GPIO_SKL_H_GPP_J5 0x01090005 +#define GPIO_SKL_H_GPP_J6 0x01090006 +#define GPIO_SKL_H_GPP_J7 0x01090007 +#define GPIO_SKL_H_GPP_J8 0x01090008 +#define GPIO_SKL_H_GPP_J9 0x01090009 +#define GPIO_SKL_H_GPP_J10 0x0109000A +#define GPIO_SKL_H_GPP_J11 0x0109000B +#define GPIO_SKL_H_GPP_J12 0x0109000C +#define GPIO_SKL_H_GPP_J13 0x0109000D +#define GPIO_SKL_H_GPP_J14 0x0109000E +#define GPIO_SKL_H_GPP_J15 0x0109000F +#define GPIO_SKL_H_GPP_J16 0x01090010 +#define GPIO_SKL_H_GPP_J17 0x01090011 +#define GPIO_SKL_H_GPP_J18 0x01090012 +#define GPIO_SKL_H_GPP_J19 0x01090013 +#define GPIO_SKL_H_GPP_J20 0x01090014 +#define GPIO_SKL_H_GPP_J21 0x01090015 +#define GPIO_SKL_H_GPP_J22 0x01090016 +#define GPIO_SKL_H_GPP_J23 0x01090017 +#define GPIO_SKL_H_GPP_K0 0x010A0000 +#define GPIO_SKL_H_GPP_K1 0x010A0001 +#define GPIO_SKL_H_GPP_K2 0x010A0002 +#define GPIO_SKL_H_GPP_K3 0x010A0003 +#define GPIO_SKL_H_GPP_K4 0x010A0004 +#define GPIO_SKL_H_GPP_K5 0x010A0005 +#define GPIO_SKL_H_GPP_K6 0x010A0006 +#define GPIO_SKL_H_GPP_K7 0x010A0007 +#define GPIO_SKL_H_GPP_K8 0x010A0008 +#define GPIO_SKL_H_GPP_K9 0x010A0009 +#define GPIO_SKL_H_GPP_K10 0x010A000A +#define GPIO_SKL_H_GPP_L2 0x010B0002 +#define GPIO_SKL_H_GPP_L3 0x010B0003 +#define GPIO_SKL_H_GPP_L4 0x010B0004 +#define GPIO_SKL_H_GPP_L5 0x010B0005 +#define GPIO_SKL_H_GPP_L6 0x010B0006 +#define GPIO_SKL_H_GPP_L7 0x010B0007 +#define GPIO_SKL_H_GPP_L8 0x010B0008 +#define GPIO_SKL_H_GPP_L9 0x010B0009 +#define GPIO_SKL_H_GPP_L10 0x010B000A +#define GPIO_SKL_H_GPP_L11 0x010B000B +#define GPIO_SKL_H_GPP_L12 0x010B000C +#define GPIO_SKL_H_GPP_L13 0x010B000D +#define GPIO_SKL_H_GPP_L14 0x010B000E +#define GPIO_SKL_H_GPP_L15 0x010B000F +#define GPIO_SKL_H_GPP_L16 0x010B0010 +#define GPIO_SKL_H_GPP_L17 0x010B0011 +#define GPIO_SKL_H_GPP_L18 0x010B0012 +#define GPIO_SKL_H_GPP_L19 0x010B0013 +#define GPIO_SKL_H_GPD0 0x010C0000 +#define GPIO_SKL_H_GPD1 0x010C0001 +#define GPIO_SKL_H_GPD2 0x010C0002 +#define GPIO_SKL_H_GPD3 0x010C0003 +#define GPIO_SKL_H_GPD4 0x010C0004 +#define GPIO_SKL_H_GPD5 0x010C0005 +#define GPIO_SKL_H_GPD6 0x010C0006 +#define GPIO_SKL_H_GPD7 0x010C0007 +#define GPIO_SKL_H_GPD8 0x010C0008 +#define GPIO_SKL_H_GPD9 0x010C0009 +#define GPIO_SKL_H_GPD10 0x010C000A +#define GPIO_SKL_H_GPD11 0x010C000B + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioPinsSklL= p.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioPinsSklLp.h new file mode 100644 index 0000000000..8012f43275 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/GpioPinsSklLp.h @@ -0,0 +1,201 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _GPIO_PINS_SKL_LP_H_ +#define _GPIO_PINS_SKL_LP_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// + +/// +/// SKL LP GPIO Groups +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_LP_GROUP_GPP_A 0x0200 +#define GPIO_SKL_LP_GROUP_GPP_B 0x0201 +#define GPIO_SKL_LP_GROUP_GPP_C 0x0202 +#define GPIO_SKL_LP_GROUP_GPP_D 0x0203 +#define GPIO_SKL_LP_GROUP_GPP_E 0x0204 +#define GPIO_SKL_LP_GROUP_GPP_F 0x0205 +#define GPIO_SKL_LP_GROUP_GPP_G 0x0206 +#define GPIO_SKL_LP_GROUP_GPD 0x0207 + +/// +/// SKL LP GPIO pins +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_LP_GPP_A0 0x02000000 +#define GPIO_SKL_LP_GPP_A1 0x02000001 +#define GPIO_SKL_LP_GPP_A2 0x02000002 +#define GPIO_SKL_LP_GPP_A3 0x02000003 +#define GPIO_SKL_LP_GPP_A4 0x02000004 +#define GPIO_SKL_LP_GPP_A5 0x02000005 +#define GPIO_SKL_LP_GPP_A6 0x02000006 +#define GPIO_SKL_LP_GPP_A7 0x02000007 +#define GPIO_SKL_LP_GPP_A8 0x02000008 +#define GPIO_SKL_LP_GPP_A9 0x02000009 +#define GPIO_SKL_LP_GPP_A10 0x0200000A +#define GPIO_SKL_LP_GPP_A11 0x0200000B +#define GPIO_SKL_LP_GPP_A12 0x0200000C +#define GPIO_SKL_LP_GPP_A13 0x0200000D +#define GPIO_SKL_LP_GPP_A14 0x0200000E +#define GPIO_SKL_LP_GPP_A15 0x0200000F +#define GPIO_SKL_LP_GPP_A16 0x02000010 +#define GPIO_SKL_LP_GPP_A17 0x02000011 +#define GPIO_SKL_LP_GPP_A18 0x02000012 +#define GPIO_SKL_LP_GPP_A19 0x02000013 +#define GPIO_SKL_LP_GPP_A20 0x02000014 +#define GPIO_SKL_LP_GPP_A21 0x02000015 +#define GPIO_SKL_LP_GPP_A22 0x02000016 +#define GPIO_SKL_LP_GPP_A23 0x02000017 +#define GPIO_SKL_LP_GPP_B0 0x02010000 +#define GPIO_SKL_LP_GPP_B1 0x02010001 +#define GPIO_SKL_LP_GPP_B2 0x02010002 +#define GPIO_SKL_LP_GPP_B3 0x02010003 +#define GPIO_SKL_LP_GPP_B4 0x02010004 +#define GPIO_SKL_LP_GPP_B5 0x02010005 +#define GPIO_SKL_LP_GPP_B6 0x02010006 +#define GPIO_SKL_LP_GPP_B7 0x02010007 +#define GPIO_SKL_LP_GPP_B8 0x02010008 +#define GPIO_SKL_LP_GPP_B9 0x02010009 +#define GPIO_SKL_LP_GPP_B10 0x0201000A +#define GPIO_SKL_LP_GPP_B11 0x0201000B +#define GPIO_SKL_LP_GPP_B12 0x0201000C +#define GPIO_SKL_LP_GPP_B13 0x0201000D +#define GPIO_SKL_LP_GPP_B14 0x0201000E +#define GPIO_SKL_LP_GPP_B15 0x0201000F +#define GPIO_SKL_LP_GPP_B16 0x02010010 +#define GPIO_SKL_LP_GPP_B17 0x02010011 +#define GPIO_SKL_LP_GPP_B18 0x02010012 +#define GPIO_SKL_LP_GPP_B19 0x02010013 +#define GPIO_SKL_LP_GPP_B20 0x02010014 +#define GPIO_SKL_LP_GPP_B21 0x02010015 +#define GPIO_SKL_LP_GPP_B22 0x02010016 +#define GPIO_SKL_LP_GPP_B23 0x02010017 +#define GPIO_SKL_LP_GPP_C0 0x02020000 +#define GPIO_SKL_LP_GPP_C1 0x02020001 +#define GPIO_SKL_LP_GPP_C2 0x02020002 +#define GPIO_SKL_LP_GPP_C3 0x02020003 +#define GPIO_SKL_LP_GPP_C4 0x02020004 +#define GPIO_SKL_LP_GPP_C5 0x02020005 +#define GPIO_SKL_LP_GPP_C6 0x02020006 +#define GPIO_SKL_LP_GPP_C7 0x02020007 +#define GPIO_SKL_LP_GPP_C8 0x02020008 +#define GPIO_SKL_LP_GPP_C9 0x02020009 +#define GPIO_SKL_LP_GPP_C10 0x0202000A +#define GPIO_SKL_LP_GPP_C11 0x0202000B +#define GPIO_SKL_LP_GPP_C12 0x0202000C +#define GPIO_SKL_LP_GPP_C13 0x0202000D +#define GPIO_SKL_LP_GPP_C14 0x0202000E +#define GPIO_SKL_LP_GPP_C15 0x0202000F +#define GPIO_SKL_LP_GPP_C16 0x02020010 +#define GPIO_SKL_LP_GPP_C17 0x02020011 +#define GPIO_SKL_LP_GPP_C18 0x02020012 +#define GPIO_SKL_LP_GPP_C19 0x02020013 +#define GPIO_SKL_LP_GPP_C20 0x02020014 +#define GPIO_SKL_LP_GPP_C21 0x02020015 +#define GPIO_SKL_LP_GPP_C22 0x02020016 +#define GPIO_SKL_LP_GPP_C23 0x02020017 +#define GPIO_SKL_LP_GPP_D0 0x02030000 +#define GPIO_SKL_LP_GPP_D1 0x02030001 +#define GPIO_SKL_LP_GPP_D2 0x02030002 +#define GPIO_SKL_LP_GPP_D3 0x02030003 +#define GPIO_SKL_LP_GPP_D4 0x02030004 +#define GPIO_SKL_LP_GPP_D5 0x02030005 +#define GPIO_SKL_LP_GPP_D6 0x02030006 +#define GPIO_SKL_LP_GPP_D7 0x02030007 +#define GPIO_SKL_LP_GPP_D8 0x02030008 +#define GPIO_SKL_LP_GPP_D9 0x02030009 +#define GPIO_SKL_LP_GPP_D10 0x0203000A +#define GPIO_SKL_LP_GPP_D11 0x0203000B +#define GPIO_SKL_LP_GPP_D12 0x0203000C +#define GPIO_SKL_LP_GPP_D13 0x0203000D +#define GPIO_SKL_LP_GPP_D14 0x0203000E +#define GPIO_SKL_LP_GPP_D15 0x0203000F +#define GPIO_SKL_LP_GPP_D16 0x02030010 +#define GPIO_SKL_LP_GPP_D17 0x02030011 +#define GPIO_SKL_LP_GPP_D18 0x02030012 +#define GPIO_SKL_LP_GPP_D19 0x02030013 +#define GPIO_SKL_LP_GPP_D20 0x02030014 +#define GPIO_SKL_LP_GPP_D21 0x02030015 +#define GPIO_SKL_LP_GPP_D22 0x02030016 +#define GPIO_SKL_LP_GPP_D23 0x02030017 +#define GPIO_SKL_LP_GPP_E0 0x02040000 +#define GPIO_SKL_LP_GPP_E1 0x02040001 +#define GPIO_SKL_LP_GPP_E2 0x02040002 +#define GPIO_SKL_LP_GPP_E3 0x02040003 +#define GPIO_SKL_LP_GPP_E4 0x02040004 +#define GPIO_SKL_LP_GPP_E5 0x02040005 +#define GPIO_SKL_LP_GPP_E6 0x02040006 +#define GPIO_SKL_LP_GPP_E7 0x02040007 +#define GPIO_SKL_LP_GPP_E8 0x02040008 +#define GPIO_SKL_LP_GPP_E9 0x02040009 +#define GPIO_SKL_LP_GPP_E10 0x0204000A +#define GPIO_SKL_LP_GPP_E11 0x0204000B +#define GPIO_SKL_LP_GPP_E12 0x0204000C +#define GPIO_SKL_LP_GPP_E13 0x0204000D +#define GPIO_SKL_LP_GPP_E14 0x0204000E +#define GPIO_SKL_LP_GPP_E15 0x0204000F +#define GPIO_SKL_LP_GPP_E16 0x02040010 +#define GPIO_SKL_LP_GPP_E17 0x02040011 +#define GPIO_SKL_LP_GPP_E18 0x02040012 +#define GPIO_SKL_LP_GPP_E19 0x02040013 +#define GPIO_SKL_LP_GPP_E20 0x02040014 +#define GPIO_SKL_LP_GPP_E21 0x02040015 +#define GPIO_SKL_LP_GPP_E22 0x02040016 +#define GPIO_SKL_LP_GPP_E23 0x02040017 +#define GPIO_SKL_LP_GPP_F0 0x02050000 +#define GPIO_SKL_LP_GPP_F1 0x02050001 +#define GPIO_SKL_LP_GPP_F2 0x02050002 +#define GPIO_SKL_LP_GPP_F3 0x02050003 +#define GPIO_SKL_LP_GPP_F4 0x02050004 +#define GPIO_SKL_LP_GPP_F5 0x02050005 +#define GPIO_SKL_LP_GPP_F6 0x02050006 +#define GPIO_SKL_LP_GPP_F7 0x02050007 +#define GPIO_SKL_LP_GPP_F8 0x02050008 +#define GPIO_SKL_LP_GPP_F9 0x02050009 +#define GPIO_SKL_LP_GPP_F10 0x0205000A +#define GPIO_SKL_LP_GPP_F11 0x0205000B +#define GPIO_SKL_LP_GPP_F12 0x0205000C +#define GPIO_SKL_LP_GPP_F13 0x0205000D +#define GPIO_SKL_LP_GPP_F14 0x0205000E +#define GPIO_SKL_LP_GPP_F15 0x0205000F +#define GPIO_SKL_LP_GPP_F16 0x02050010 +#define GPIO_SKL_LP_GPP_F17 0x02050011 +#define GPIO_SKL_LP_GPP_F18 0x02050012 +#define GPIO_SKL_LP_GPP_F19 0x02050013 +#define GPIO_SKL_LP_GPP_F20 0x02050014 +#define GPIO_SKL_LP_GPP_F21 0x02050015 +#define GPIO_SKL_LP_GPP_F22 0x02050016 +#define GPIO_SKL_LP_GPP_F23 0x02050017 +#define GPIO_SKL_LP_GPP_G0 0x02060000 +#define GPIO_SKL_LP_GPP_G1 0x02060001 +#define GPIO_SKL_LP_GPP_G2 0x02060002 +#define GPIO_SKL_LP_GPP_G3 0x02060003 +#define GPIO_SKL_LP_GPP_G4 0x02060004 +#define GPIO_SKL_LP_GPP_G5 0x02060005 +#define GPIO_SKL_LP_GPP_G6 0x02060006 +#define GPIO_SKL_LP_GPP_G7 0x02060007 +#define GPIO_SKL_LP_GPD0 0x02070000 +#define GPIO_SKL_LP_GPD1 0x02070001 +#define GPIO_SKL_LP_GPD2 0x02070002 +#define GPIO_SKL_LP_GPD3 0x02070003 +#define GPIO_SKL_LP_GPD4 0x02070004 +#define GPIO_SKL_LP_GPD5 0x02070005 +#define GPIO_SKL_LP_GPD6 0x02070006 +#define GPIO_SKL_LP_GPD7 0x02070007 +#define GPIO_SKL_LP_GPD8 0x02070008 +#define GPIO_SKL_LP_GPD9 0x02070009 +#define GPIO_SKL_LP_GPD10 0x0207000A +#define GPIO_SKL_LP_GPD11 0x0207000B + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/Gpio= Lib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/GpioLib.h new file mode 100644 index 0000000000..dcee806ada --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/GpioLib.h @@ -0,0 +1,777 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _GPIO_LIB_H_ +#define _GPIO_LIB_H_ + +#include +#include + +typedef struct { + GPIO_PAD GpioPad; + GPIO_CONFIG GpioConfig; +} GPIO_INIT_CONFIG; +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG = structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware def= ault values. + Separate fields could be set to hardware default if it does not matter, = except + GpioPad and PadMode. + Some GpioPads are configured and switched to native mode by RC, those in= clude: + SerialIo pins, ISH pins, ClkReq Pins + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ); + +// +// Functions for setting/getting multiple GpioPad settings +// + +/** + This procedure will read multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[out] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadConfig ( + IN GPIO_PAD GpioPad, + OUT GPIO_CONFIG *GpioData + ); + +/** + This procedure will configure multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[in] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ); + +// +// Functions for setting/getting single GpioPad properties +// + +/** + This procedure will set GPIO output level + + @param[in] GpioPad GPIO pad + @param[in] Value Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetOutputValue ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO output level + + @param[in] GpioPad GPIO pad + @param[out] OutputVal GPIO Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetOutputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *OutputVal + ); + +/** + This procedure will get GPIO input level + + @param[in] GpioPad GPIO pad + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ); + +/** + This procedure will get GPIO IOxAPIC interrupt number + + @param[in] GpioPad GPIO pad + @param[out] IrqNum IRQ number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadIoApicIrqNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *IrqNum + ); + +/** + This procedure will configure GPIO input inversion + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIO input inversion + 0: No input inversion, 1: Invert input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetInputInversion ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO pad input inversion value + + @param[in] GpioPad GPIO pad + @param[out] InvertState GPIO inversion state + 0: No input inversion, 1: Inverted input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputInversion ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InvertState + ); + +/** + This procedure will set GPIO interrupt settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Level/Edge + use GPIO_INT_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadInterruptConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_INT_CONFIG Value + ); + +/** + This procedure will set GPIO electrical settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of termination + use GPIO_ELECTRICAL_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadElectricalConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_ELECTRICAL_CONFIG Value + ); + +/** + This procedure will set GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value for Pad Reset Configuration + use GPIO_RESET_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG Value + ); + +/** + This procedure will get GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Pad Reset Configuration + based on GPIO_RESET_CONFIG + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG *Value + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain gro= up + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for curre= nt group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] HostSwRegVal Value of Host Software Pad Ownership reg= ister + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver= mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *HostSwRegVal + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain gro= up + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for curre= nt group + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] HostSwRegVal Value of Host Software Pad Ownership reg= ister + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver= mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 HostSwRegVal + ); + +/** + This procedure will get Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadHostSwOwn Value of Host Software Pad Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadHostSwOwn + ); + +/** + This procedure will set Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[in] PadHostSwOwn Pad Host Software Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + IN UINT32 PadHostSwOwn + ); + +// +// Possible values of Pad Ownership +// +typedef enum { + GpioPadOwnHost =3D 0x0, + GpioPadOwnCsme =3D 0x1, + GpioPadOwnIsh =3D 0x2, +} GPIO_PAD_OWN; + +/** + This procedure will get Gpio Pad Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadOwnVal Value of Pad Ownership + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadOwnership ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_OWN *PadOwnVal + ); + +/** + This procedure will check state of Pad Config Lock for pads within one g= roup + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockRegVal Value of PadCfgLock register + Bit position - PadNumber + Bit value - 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockRegVal + ); + +/** + This procedure will check state of Pad Config Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLock for selected pad + 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLock ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLock + ); + +/** + This procedure will check state of Pad Config Tx Lock for pads within on= e group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register + Bit position - PadNumber + Bit value - 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockTxRegVal + ); + +/** + This procedure will check state of Pad Config Tx Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLockTx for selected pad + 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLockTx ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLockTx + ); + +/** + This procedure will clear PadCfgLock for selected pads within one group. + This function should be used only inside SMI. + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlock Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnlock, 1: Unlock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlock + ); + +/** + This procedure will clear PadCfgLock for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfg ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLock for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLock Bitmask for pads which are going to be l= ocked, + Bit position - PadNumber + Bit value - 0: DoNotLock, 1: Lock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLock + ); + +/** + This procedure will set PadCfgLock for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfg ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will clear PadCfgLockTx for selected pads within one grou= p. + This function should be used only inside SMI. + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlockTx Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlockTx + ); + +/** + This procedure will clear PadCfgLockTx for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTx ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLockTx for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLockTx Bitmask for pads which are going to be l= ocked, + Bit position - PadNumber + Bit value - 0: DoNotLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLockTx + ); + +/** + This procedure will set PadCfgLockTx for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfgTx ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get Group to GPE mapping. + + @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGroupToGpeDwX ( + IN GPIO_GROUP *GroupToGpeDw0, + IN GPIO_GROUP *GroupToGpeDw1, + IN GPIO_GROUP *GroupToGpeDw2 + ); + +/** + This procedure will set Group to GPE mapping. + + @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGroupToGpeDwX ( + IN GPIO_GROUP GroupToGpeDw0, + IN GPIO_GROUP GroupToGpeDw1, + IN GPIO_GROUP GroupToGpeDw2 + ); + +/** + This procedure will get GPE number for provided GpioPad. + PCH allows to configure mapping between GPIO groups and related GPE (Gpi= oSetGroupToGpeDwX()) + what results in the fact that certain Pad can cause different General Pu= rpose Event. Only three + GPIO groups can be mapped to cause unique GPE (1-tier), all others group= s will be under one common + event (GPE_111 for 2-tier). + + 1-tier: + Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used + to determine what _LXX ACPI method would be called on event on selected = GPIO pad + + 2-tier: + Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to = 1-tier GPE + will be under one master GPE_111 which is linked to _L6F ACPI method. If= it is needed to determine + what Pad from 2-tier has caused the event, _L6F method should check GPI_= GPE_STS and GPI_GPE_EN + registers for all GPIO groups not mapped to 1-tier GPE. + + @param[in] GpioPad GPIO pad + @param[out] GpeNumber GPE number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpeNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *GpeNumber + ); + +/** + This procedure is used to clear SMI STS for a specified Pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiSmiSts ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used by Smi Dispatcher and will clear + all GPI SMI Status bits + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearAllGpiSmiSts ( + VOID + ); + +/** + This procedure is used to disable all GPI SMI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioDisableAllGpiSmi ( + VOID + ); + +/** + This procedure is used to register GPI SMI dispatch function. + + @param[in] GpioPad GPIO pad + @param[out] GpiNum GPI number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiSmiNum ( + IN GPIO_PAD GpioPad, + OUT UINTN *GpiNum + ); + +/** + This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier = architecture + + @param[in] GpioPad GPIO pad + + @retval Data 0 means 1-tier, 1 means 2-tier +**/ +BOOLEAN +GpioCheckFor2Tier ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to clear GPE STS for a specified GpioPad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiGpeSts ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to read GPE STS for a specified Pad + + @param[in] GpioPad GPIO pad + @param[out] Data GPE STS data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiGpeSts ( + IN GPIO_PAD GpioPad, + OUT UINT32* Data + ); + +/** + This procedure will set GPIO Input Rout SCI + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIRoutSCI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiRoutSci ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will set GPIO Input Rout SMI + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIRoutSMI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiRoutSmi ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will set GPI SMI Enable setting for selected pad + + @param[in] GpioPad GPIO pad + @param[in] PadGpiSmiEn GPI SMI Enable setting for selected pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiSmiPadEn ( + IN GPIO_PAD GpioPad, + IN UINT32 PadGpiSmiEn + ); + +/** + This procedure will set GPI General Purpose Event Enable setting for sel= ected pad + + @param[in] GpioPad GPIO pad + @param[in] PadGpiGpeEn GPI General Purpose Event Enable setting= for selected pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiGpePadEn ( + IN GPIO_PAD GpioPad, + IN UINT32 PadGpiGpeEn + ); + +/** + Locks GPIO pads according to GPIO_INIT_CONFIG array from + gPlatformGpioConfigGuid HOB. Only locking is applied and no other GPIO = pad + configuration is changed. + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_NOT_FOUND gPlatformGpioConfigGuid not found +**/ +EFI_STATUS +GpioLockGpios ( + VOID + ); + +/** + Unlocks all PCH GPIO pads + + @retval None +**/ +VOID +GpioUnlockAllGpios ( + VOID + ); + +#endif // _GPIO_LIB_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/Gpio= NativeLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/Gpi= oNativeLib.h new file mode 100644 index 0000000000..357bd68b2a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/GpioNativeL= ib.h @@ -0,0 +1,218 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _GPIO_NATIVE_LIB_H_ +#define _GPIO_NATIVE_LIB_H_ + +#include + +/** + This procedure will get number of pads for certain GPIO group + + @param[in] Group GPIO group number + + @retval Value Pad number for group + If illegal group number then return 0 +**/ +UINT32 +GpioGetPadPerGroup ( + IN GPIO_GROUP Group + ); + +/** + This procedure will get number of groups + + @param[in] none + + @retval Value Group number +**/ +UINT8 +GpioGetNumberOfGroups ( + VOID + ); +/** + This procedure will get lowest group + + @param[in] none + + @retval Value Lowest Group +**/ +GPIO_GROUP +GpioGetLowestGroup ( + VOID + ); + +/** + This procedure will get highest group + + @param[in] none + + @retval Value Highest Group +**/ +GPIO_GROUP +GpioGetHighestGroup ( + VOID + ); + +/** + This procedure will get group + + @param[in] GpioPad Gpio Pad + + @retval Value Group +**/ +GPIO_GROUP +GpioGetGroupFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get group index (0 based) from GpioPad + + @param[in] GpioPad Gpio Pad + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get group index (0 based) from group + + @param[in] GpioGroup Gpio Group + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGroup ( + IN GPIO_GROUP GpioGroup + ); + +/** + This procedure will get pad number (0 based) from Gpio Pad + + @param[in] GpioPad Gpio Pad + + @retval Value Pad Number +**/ +UINT32 +GpioGetPadNumberFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will return GpioPad from Group and PadNumber + + @param[in] Group GPIO group + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupAndPadNumber ( + IN GPIO_GROUP Group, + IN UINT32 PadNumber + ); + +/** + This procedure will return GpioPad from GroupIndex and PadNumber + + @param[in] GroupIndex GPIO GroupIndex + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupIndexAndPadNumber ( + IN UINT32 GroupIndex, + IN UINT32 PadNumber + ); + +/** + This function sets SerialIo I2C controller pins into native mode + + @param[in] SerialIoI2cControllerNumber I2C controller + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoI2cPinsIntoNativeMode ( + IN UINT32 SerialIoI2cControllerNumber + ); + +/** + This function sets SerialIo I2C controller pins tolerance + + @param[in] SerialIoI2CControllerNumber I2C controller + @param[in] Pad1v8Tolerance TRUE: Enable 1v8 Pad toleran= ce + FALSE: Disable 1v8 Pad toleran= ce + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoI2CPinsTolerance ( + IN UINT32 SerialIoI2CControllerNumber, + IN BOOLEAN Pad1v8Tolerance + ); + +/** + This function sets SerialIo UART controller pins into native mode + + @param[in] SerialIoI2CControllerNumber UART controller + @param[in] HardwareFlowControl Hardware Flow control + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoUartPinsIntoNativeMode ( + IN UINT32 SerialIoUartControllerNumber, + IN BOOLEAN HardwareFlowControl + ); + +/** + This function sets SerialIo SPI controller pins into native mode + + @param[in] SerialIoI2CControllerNumber SPI controller + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoSpiPinsIntoNativeMode ( + IN UINT32 SerialIoUartControllerNumber + ); + +/** + This function checks if GPIO pin for SATA reset port is in GPIO MODE + + @param[in] SataPort SATA port number + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsSataResetPortInGpioMode ( + IN UINTN SataPort + ); + +/** + This function checks if SataDevSlp pin is in native mode + + @param[in] SataPort SATA port + @param[out] DevSlpPad DevSlpPad + + @retval TRUE DevSlp is in native mode + FALSE DevSlp is not in native mode +**/ +BOOLEAN +GpioIsSataDevSlpPinEnabled ( + IN UINTN SataPort, + OUT GPIO_PAD *DevSlpPad + ); + +#endif // _GPIO_NATIVE_LIB_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchC= ycleDecodingLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Libra= ry/PchCycleDecodingLib.h new file mode 100644 index 0000000000..52c664a76c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchCycleDec= odingLib.h @@ -0,0 +1,344 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_CYCLE_DECODING_LIB_H_ +#define _PCH_CYCLE_DECODING_LIB_H_ + +/** + Set PCH ACPI base address. + The Address should not be 0 and should be 256 bytes alignment, and it is= IO space, so must not exceed 0xFFFF. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. clear PMC PCI offset 44h [7] to diable ACPI base address first before= changing base address. + 2. program PMC PCI offset 40h [15:2] to ACPI base address. + 3. set PMC PCI offset 44h [7] to enable ACPI base address. + 4. program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] to [0x3F= , PMC PCI Offset 40h bit[15:2], 1]. + 5. Program "ACPI Base Destination ID" PCR[DMI] + 27B8h[31:0] to [0x23A0]. + + @param[in] Address Address for ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchAcpiBaseSet ( + IN UINT16 Address + ); + +/** + Get PCH ACPI base address. + + @param[out] Address Address of ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchAcpiBaseGet ( + OUT UINT16 *Address + ); + +/** + Set PCH PWRM base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. clear PMC PCI offset 44h [8] to diable PWRM base address first before= changing PWRM base address. + 2. program PMC PCI offset 48h [31:16] to PM base address. + 3. set PMC PCI offset 44h [8] to enable PWRM base address. + 4. program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to= the same value programmed in PMC PCI Offset 48h bit[31:16], this has an im= plication of making sure the PWRMBASE to be 64KB aligned. + program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] = to the value programmed in PMC PCI Offset 48h bit[31:16], this has an impli= cation of making sure the memory allocated to PWRMBASE to be 64KB in size. + 5. program "PM Base Control" PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A0]. + + @param[in] Address Address for PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchPwrmBaseSet ( + IN UINT32 Address + ); + +/** + Get PCH PWRM base address. + + @param[out] Address Address of PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchPwrmBaseGet ( + OUT UINT32 *Address + ); + +/** + Set PCH TCO base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. set Smbus PCI offset 54h [8] to enable TCO base address. + 2. program Smbus PCI offset 50h [15:5] to TCO base address. + 3. set Smbus PCI offset 54h [8] to enable TCO base address. + 4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI of= fset 50h[15:5], 1]. + + @param[in] Address Address for TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchTcoBaseSet ( + IN UINT16 Address + ); + +/** + Get PCH TCO base address. + + @param[out] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchTcoBaseGet ( + OUT UINT16 *Address + ); + +/// +/// structure of LPC general IO range register +/// It contains base address, address mask, and enable status. +/// +typedef struct { + UINT32 BaseAddr :16; + UINT32 Length :15; + UINT32 Enable : 1; +} PCH_LPC_GEN_IO_RANGE; + +#define PCH_LPC_GEN_IO_RANGE_MAX 4 +/// +/// structure of LPC general IO range register list +/// It lists all LPC general IO ran registers supported by PCH. +/// +typedef struct { + PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX]; +} PCH_LPC_GEN_IO_RANGE_LIST; + +/** + Set PCH LPC generic IO range. + For generic IO range, the base address must align to 4 and less than 0xF= FFF, and the length must be power of 2 + and less than or equal to 256. Moreover, the address must be length alig= ned. + This function basically checks the address and length, which should not = overlap with all other generic ranges. + If no more generic range register available, it returns out of resource = error. + This cycle decoding is allowed to set when DMIC.SRL is 0. + The IO ranges below 0x100 have fixed target. The target might be ITSS,RT= C,LPC,PMC or terminated inside P2SB + but all predefined and can't be changed. IO range below 0x100 will be sk= ipped except 0x80-0x8F. + Steps of programming generic IO range: + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. + 2. Program LPC/eSPI Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the = same value programmed in LPC/eSPI PCI Offset 84h~93h. + + @param[in] Address Address for generic IO range base = address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeSet ( + IN UINT16 Address, + IN UINTN Length + , IN UINT8 SlaveDevice + ); + +/** + Get PCH LPC generic IO range list. + This function returns a list of base address, length, and enable for all= LPC generic IO range regsiters. + + @param[out] LpcGenIoRangeList Return all LPC generic IO range re= gister status. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeGet ( + OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList + , IN UINT8 SlaveDevice + ); + +/** + Set PCH LPC memory range decoding. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program LPC/eSPI PCI 98h [0] to [0] to disable memory decoding first = before changing base address. + 2. Program LPC/eSPI PCI 98h [31:16, 0] to [Address, 1]. + 3. Program LPC/eSPI Memory Range, PCR[DMI] + 2740h to the same value pro= grammed in LPC/eSPI PCI Offset 98h. + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeSet ( + IN UINT32 Address + , IN UINT8 SlaveDevice + ); + +/** + Get PCH LPC memory range decoding address. + + @param[out] Address Address of LPC memory decoding bas= e address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeGet ( + OUT UINT32 *Address + , IN UINT8 SlaveDevice + ); + +/** + Set PCH BIOS range deocding. + This will check General Control and Status bit 10 (GCS.BBS) to identify = SPI or LPC/eSPI and program BDE register accordingly. + Please check EDS for detail of BiosDecodeEnable bit definition. + bit 15: F8-FF Enable + bit 14: F0-F8 Enable + bit 13: E8-EF Enable + bit 12: E0-E8 Enable + bit 11: D8-DF Enable + bit 10: D0-D7 Enable + bit 9: C8-CF Enable + bit 8: C0-C7 Enable + bit 7: Legacy F Segment Enable + bit 6: Legacy E Segment Enable + bit 5: Reserved + bit 4: Reserved + bit 3: 70-7F Enable + bit 2: 60-6F Enable + bit 1: 50-5F Enable + bit 0: 40-4F Enable + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable. + if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDe= codeEnable. + 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same= value programmed in LPC/eSPI or SPI PCI Offset D8h. + + @param[in] BiosDecodeEnable Bios decode enable setting. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +EFIAPI +PchBiosDecodeEnableSet ( + IN UINT16 BiosDecodeEnable + ); + +/** + Set PCH LPC IO decode ranges. + Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value = programmed in LPC offset 80h. + Please check EDS for detail of Lpc IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ); + +/** + Set PCH LPC IO enable decoding. + Setup LPC I/O Enables, PCR[DMI] + 2774h[15:0] to the same value program = in LPC offset 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field + in LPC 82h[13:10] is always forwarded by DMI to subtractive agent for ha= ndling. + Please check EDS for detail of Lpc IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding Lpc IO enable decoding bit setting= s. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + , IN UINT8 SlaveDevice + ); + +/** + Set PCH IO port 80h cycle decoding to PCIE root port. + System BIOS is likely to do this very soon after reset before PCI bus en= umeration, it must ensure that + the IO Base Address field (PCIe:1Ch[7:4]) contains a value greater than = the IO Limit field (PCIe:1Ch[15:12]) + before setting the IOSE bit. Otherwise the bridge will positively decode= IO range 000h - FFFh by its default + IO range values. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID = of RP. + 2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte = write on GCS+1 and leave the BILD bit which is RWO. + 3. Program IOSE bit of PCIE:Reg04h[0] to '1' for PCH to send such IO cy= cles to PCIe bus for subtractive decoding. + + @param[in] RpPhyNumber PCIE root port physical number. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +EFIAPI +PchIoPort80DecodeSet ( + IN UINTN RpPhyNumber + ); + +/** + Get IO APIC regsiters base address. + It returns IO APIC INDEX, DATA, and EOI regsiter address once the parame= ter is not NULL. + This function will be unavailable after P2SB is hidden by PSF. + + @param[out] IoApicIndex Buffer of IO APIC INDEX regsiter a= ddress + @param[out] IoApicData Buffer of IO APIC DATA regsiter ad= dress + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchIoApicBaseGet ( + OPTIONAL OUT UINT32 *IoApicIndex, + OPTIONAL OUT UINT32 *IoApicData + ); + +/** + Get HPET base address. + This function will be unavailable after P2SB is hidden by PSF. + + @param[out] HpetBase Buffer of HPET base address + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchHpetBaseGet ( + OUT UINT32 *HpetBase + ); + +#endif // _PCH_CYCLE_DECODING_LIB_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchG= beLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchGbeL= ib.h new file mode 100644 index 0000000000..53cbc0a839 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchGbeLib.h @@ -0,0 +1,58 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_GBE_LIB_H_ +#define _PCH_GBE_LIB_H_ + +/** + Check whether GbE region is valid + Check SPI region directly since GBE might be disabled in SW. + + @retval TRUE Gbe Region is valid + @retval FALSE Gbe Region is invalid +**/ +BOOLEAN +PchIsGbeRegionValid ( + VOID + ); + +/** + Returns GbE over PCIe port number based on a soft strap. + + @return Root port number (1-based) + @retval 0 GbE over PCIe disabled +**/ +UINT32 +PchGetGbePortNumber ( + VOID + ); + +/** + Check whether LAN controller is enabled in the platform. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbePresent ( + VOID + ); + +/** + Check whether LAN controller is enabled in the platform. + + @deprecated Use PchIsGbePresent instead. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbeAvailable ( + VOID + ); + +#endif // _PCH_GBE_LIB_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchI= nfoLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchInf= oLib.h new file mode 100644 index 0000000000..94e3502efe --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchInfoLib.h @@ -0,0 +1,231 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_INFO_LIB_H_ +#define _PCH_INFO_LIB_H_ + +#include + +typedef enum { + PchH =3D 1, + PchLp, + PchUnknownSeries +} PCH_SERIES; + +typedef enum { + SklPch =3D 1, + PchUnknownGeneration +} PCH_GENERATION; + +/** + Return Pch stepping type + + @retval PCH_STEPPING Pch stepping type +**/ +PCH_STEPPING +EFIAPI +PchStepping ( + VOID + ); + +/** + Determine if PCH is supported + + @retval TRUE PCH is supported + @retval FALSE PCH is not supported +**/ +BOOLEAN +IsPchSupported ( + VOID + ); + +/** + Return Pch Series + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +EFIAPI +GetPchSeries ( + VOID + ); + +/** + Return Pch Generation + + @retval PCH_GENERATION Pch Generation +**/ +PCH_GENERATION +EFIAPI +GetPchGeneration ( + VOID + ); + +/** + Get Pch Maximum Pcie Root Port Number + + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number +**/ +UINT8 +EFIAPI +GetPchMaxPciePortNum ( + VOID + ); + +/** + Get Pch Maximum Sata Port Number + + @retval Pch Maximum Sata Port Number +**/ +UINT8 +EFIAPI +GetPchMaxSataPortNum ( + VOID + ); + +/** + Get Pch Usb Maximum Physical Port Number + + @retval Pch Usb Maximum Physical Port Number +**/ +UINT8 +EFIAPI +GetPchUsbMaxPhysicalPortNum ( + VOID + ); + +/** + Get Pch Maximum Usb2 Port Number of XHCI Controller + + @retval Pch Maximum Usb2 Port Number of XHCI Controller +**/ +UINT8 +EFIAPI +GetPchXhciMaxUsb2PortNum ( + VOID + ); + +/** + Get Pch Maximum Usb3 Port Number of XHCI Controller + + @retval Pch Maximum Usb3 Port Number of XHCI Controller +**/ +UINT8 +EFIAPI +GetPchXhciMaxUsb3PortNum ( + VOID + ); + +/** + Return TRUE if Server Sata is present + + @retval BOOLEAN TRUE if sSata device is present +**/ +BOOLEAN +EFIAPI +GetIsPchsSataPresent ( + VOID + ); + +/** + Get Pch Maximum sSata Port Number + + @param[in] None + + @retval Pch Maximum sSata Port Number +**/ +UINT8 +EFIAPI +GetPchMaxsSataPortNum ( + VOID + ); + +/** + Get Pch Maximum sSata Controller Number + + @param[in] None + + @retval Pch Maximum sSata Controller Number +**/ +UINT8 +EFIAPI +GetPchMaxsSataControllerNum ( + VOID + ); + +/** + Return Pch Lpc Device Id + + @retval UINT16 Pch DeviceId +**/ +UINT16 +EFIAPI +GetPchLpcDeviceId ( + VOID + ); + +/** + Get PCH stepping ASCII string + The return string is zero terminated. + + @param [in] PchStep Pch stepping + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size wh= en buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The stepping is not supported, or = parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSteppingStr ( + IN PCH_STEPPING PchStep, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ); + +/** + Get PCH series ASCII string + The return string is zero terminated. + + @param [in] PchSeries Pch series + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size wh= en buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The series is not supported, or pa= rameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSeriesStr ( + IN PCH_SERIES PchSeries, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ); + +/** + Get PCH Sku ASCII string + The return string is zero terminated. + + @param [in] LpcDid LPC device id + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size wh= en buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The series is not supported, or pa= rameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSkuStr ( + IN UINT16 LpcDid, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ); + +#endif // _PCH_INFO_LIB_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchP= 2sbLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchP2s= bLib.h new file mode 100644 index 0000000000..edba54a7ce --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchP2sbLib.h @@ -0,0 +1,154 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_P2SB_LIB_H_ +#define _PCH_P2SB_LIB_H_ + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet32 ( + IN UINTN Offset, + OUT UINT32 *OutData + ); + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 2bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet16 ( + IN UINTN Offset, + OUT UINT16 *OutData + ); + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 1byte. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet8 ( + IN UINTN Offset, + OUT UINT8 *OutData + ); + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet32 ( + IN UINTN Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 2bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet16 ( + IN UINTN Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 1bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet8 ( + IN UINTN Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Hide P2SB device. + + @param[in] P2sbBase Pci base address of P2SB controlle= r. + + @retval EFI_SUCCESS Always return success. +**/ +EFI_STATUS +PchHideP2sb ( + IN UINTN P2sbBase + ); + +/** + Reveal P2SB device. + Also return the original P2SB status which is for Hidding P2SB or not af= ter. + If OrgStatus is not NULL, then TRUE means P2SB is unhidden, + and FALSE means P2SB is hidden originally. + + @param[in] P2sbBase Pci base address of P2SB controlle= r. + @param[out] OrgStatus Original P2SB hidding/unhidden sta= tus + + @retval EFI_SUCCESS Always return success. +**/ +EFI_STATUS +PchRevealP2sb ( + IN UINTN P2sbBase, + OUT BOOLEAN *OrgStatus + ); + +#endif // _PCH_P2SB_LIB_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchP= crLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchPcrL= ib.h new file mode 100644 index 0000000000..dc8078c0cf --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchPcrLib.h @@ -0,0 +1,190 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_PCR_LIB_H_ +#define _PCH_PCR_LIB_H_ + +#include + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT32 *OutData + ); + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT16 *OutData + ); + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT8 *OutData + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size = as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size = as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size = as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + +#endif // _PCH_PCR_LIB_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchP= mcLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchPmcL= ib.h new file mode 100644 index 0000000000..ff21ac51e4 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchPmcLib.h @@ -0,0 +1,56 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_PMC_LIB_H_ +#define _PCH_PMC_LIB_H_ + +typedef enum { + PchWarmBoot =3D 1, + PchColdBoot, + PwrFlr, + PwrFlrSys, + PwrFlrPch, + PchPmStatusMax +} PCH_PM_STATUS; + +/** + Query PCH to determine the Pm Status + + @param[in] PmStatus - The Pch Pm Status to be probed + + @retval Status TRUE if Status querried is Valid or FALSE if otherwise +**/ +BOOLEAN +GetPchPmStatus ( + PCH_PM_STATUS PmStatus + ); + +/** + Funtion to check if Battery lost or CMOS cleared. + + @reval TRUE Battery is always present. + @reval FALSE CMOS is cleared. +**/ +BOOLEAN +EFIAPI +PchIsRtcBatteryGood ( + VOID + ); + +/** + Funtion to check if DWR occurs + + @reval TRUE DWR occurs + @reval FALSE Normal boot flow +**/ +BOOLEAN +EFIAPI +PchIsDwrFlow ( + VOID + ); + +#endif // _PCH_PMC_LIB_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchP= olicyLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchP= olicyLib.h new file mode 100644 index 0000000000..b854f0f581 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchPolicyLi= b.h @@ -0,0 +1,66 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_PCH_POLICY_LIB_H_ +#define _PEI_PCH_POLICY_LIB_H_ + +#include + +/** + Print whole PCH_POLICY_PPI and serial out. + + @param[in] PchPolicyPpi The RC Policy PPI instance +**/ +VOID +EFIAPI +PchPrintPolicyPpi ( + IN PCH_POLICY_PPI *PchPolicyPpi + ); + +/** + PchCreatePolicyDefaults creates the default setting of PCH Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] PchPolicyPpi The pointer to get PCH Policy PPI = instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +PchCreatePolicyDefaults ( + OUT PCH_POLICY_PPI **PchPolicyPpi + ); + +/** + PchInstallPolicyPpi installs PchPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] PchPolicyPpi The pointer to PCH Policy PPI inst= ance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +PchInstallPolicyPpi ( + IN PCH_POLICY_PPI *PchPolicyPpi + ); + +/* + Apply RVP3 PCH specific default settings + + @param[in] PchPolicyPpi The pointer to PCH Policy PPI instance +*/ +VOID +EFIAPI +PchRvp3DefaultPolicy ( + IN PCH_POLICY_PPI *PchPolicy + ); + +#endif // _PEI_PCH_POLICY_LIB_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchS= biAccessLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/P= chSbiAccessLib.h new file mode 100644 index 0000000000..f5328c0c1c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchSbiAcces= sLib.h @@ -0,0 +1,156 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_SBI_ACCESS_LIB_H_ +#define _PCH_SBI_ACCESS_LIB_H_ + +/** + PCH SBI Register structure +**/ +typedef struct { + UINT32 SbiAddr; + UINT32 SbiExtAddr; + UINT32 SbiData; + UINT16 SbiStat; + UINT16 SbiRid; +} PCH_SBI_REGISTER_STRUCT; + +/** + PCH SBI opcode definitions +**/ +typedef enum { + MemoryRead =3D 0x0, + MemoryWrite =3D 0x1, + PciConfigRead =3D 0x4, + PciConfigWrite =3D 0x5, + PrivateControlRead =3D 0x6, + PrivateControlWrite =3D 0x7, + GpioLockUnlock =3D 0x13 +} PCH_SBI_OPCODE; + +/** + PCH SBI response status definitions +**/ +typedef enum { + SBI_SUCCESSFUL =3D 0, + SBI_UNSUCCESSFUL =3D 1, + SBI_POWERDOWN =3D 2, + SBI_MIXED =3D 3, + SBI_INVALID_RESPONSE +} PCH_SBI_RESPONSE; + +/** + Execute PCH SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiE= xecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. = If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be= checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would = provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter +**/ +EFI_STATUS +EFIAPI +PchSbiExecution ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +/** + Full function for executing PCH SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiE= xecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. = If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be= checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would = provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter +**/ +EFI_STATUS +EFIAPI +PchSbiExecutionEx ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +/** + This function saves all PCH SBI registers. + The save and restore operations must be done while using the PchSbiExecu= tion inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POS= T and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in, out] PchSbiRegister Structure for saving the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterSave ( + IN OUT PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ); + +/** + This function restores all PCH SBI registers + The save and restore operations must be done while using the PchSbiExecu= tion inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POS= T and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in] PchSbiRegister Structure for restoring the regist= ers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterRestore ( + IN PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ); + +#endif // _PCH_SBI_ACCESS_LIB_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchS= erialIoLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/Pc= hSerialIoLib.h new file mode 100644 index 0000000000..65820ce78c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/PchSerialIo= Lib.h @@ -0,0 +1,212 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_SERIAL_IO_LIB_H_ +#define _PCH_SERIAL_IO_LIB_H_ + +typedef enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5, + PchSerialIoIndexSpi0, + PchSerialIoIndexSpi1, + PchSerialIoIndexUart0, + PchSerialIoIndexUart1, + PchSerialIoIndexUart2, + PchSerialIoIndexMax +} PCH_SERIAL_IO_CONTROLLER; + +typedef enum { + PchSerialIoDisabled, + PchSerialIoAcpi, + PchSerialIoPci, + PchSerialIoAcpiHidden, + PchSerialIoLegacyUart, + PchSerialIoSkipInit +} PCH_SERIAL_IO_MODE; + +enum PCH_LP_SERIAL_IO_VOLTAGE_SEL { + PchSerialIoIs33V =3D 0, + PchSerialIoIs18V +}; +enum PCH_LP_SERIAL_IO_CS_POLARITY { + PchSerialIoCsActiveLow =3D 0, + PchSerialIoCsActiveHigh =3D 1 +}; +enum PCH_LP_SERIAL_IO_HW_FLOW_CTRL { + PchSerialIoHwFlowCtrlDisabled =3D 0, + PchSerialIoHwFlowControlEnabled =3D 1 +}; + +#define SERIALIO_HID_LENGTH 8 // including null terminator +#define SERIALIO_UID_LENGTH 1 +#define SERIALIO_CID_LENGTH 1 +#define SERIALIO_TOTAL_ID_LENGTH SERIALIO_HID_LENGTH+SERIALIO_UID_LENGTH+S= ERIALIO_CID_LENGTH + +/** + Returns index of the last i2c controller + + @param[in] Number Number of SerialIo controller + + @retval Index of I2C controller +**/ +PCH_SERIAL_IO_CONTROLLER +GetMaxI2cNumber ( + ); + +/** + Returns string with AcpiHID assigned to selected SerialIo controller + + @param[in] Number Number of SerialIo controller + + @retval pointer to 8-byte string +**/ +CHAR8* +GetSerialIoAcpiHID ( + IN PCH_SERIAL_IO_CONTROLLER Number + ); + +/** + Checks if Device with given PciDeviceId is one of SerialIo controllers + If yes, its number is returned through Number parameter, otherwise Numbe= r is not updated + + @param[in] PciDevId Device ID + @param[out] Number Number of SerialIo controller + + @retval TRUE Yes it is a SerialIo controller + @retval FALSE No it isn't a SerialIo controller +**/ +BOOLEAN +IsSerialIoPciDevId ( + IN UINT16 PciDevId, + OUT PCH_SERIAL_IO_CONTROLLER *Number + ); + +/** + Checks if Device with given AcpiHID string is one of SerialIo controllers + If yes, its number is returned through Number parameter, otherwise Numbe= r is not updated + + @param[in] AcpiHid String + @param[out] Number Number of SerialIo controller + + @retval TRUE yes it is a SerialIo controller + @retval FALSE no it isn't a SerialIo controller +**/ +BOOLEAN +IsSerialIoAcpiHid ( + IN CHAR8 *AcpiHid, + OUT PCH_SERIAL_IO_CONTROLLER *Number + ); + +/** + Configures Serial IO Controller + + @param[in] Controller + @param[in] DeviceMode + + @retval None +**/ +VOID +ConfigureSerialIoController ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode + ); + +/** + Initializes GPIO pins used by SerialIo I2C devices + + @param[in] Controller + @param[in] DeviceMode + @param[in] I2cVoltage + + @retval None +**/ +VOID +SerialIoI2cGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN UINT32 I2cVoltage + ); + +/** + Initializes GPIO pins used by SerialIo SPI devices + + @param[in] Controller + @param[in] DeviceMode + @param[in] SpiCsPolarity + + @retval None +**/ +VOID +SerialIoSpiGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN UINT32 SpiCsPolarity + ); + +/** + Initializes GPIO pins used by SerialIo devices + + @param[in] Controller + @param[in] DeviceMode + @param[in] HardwareFlowControl + + @retval None +**/ +VOID +SerialIoUartGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN BOOLEAN HardwareFlowControl + ); + +/** + Finds PCI Device Number of SerialIo devices. + SerialIo devices' BDF is configurable + + @param[in] SerialIoNumber 0=3DI2C0, ..., 11=3DUART2 + + @retval SerialIo device number +**/ +UINT8 +GetSerialIoDeviceNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ); + +/** + Finds PCI Function Number of SerialIo devices. + SerialIo devices' BDF is configurable + + @param[in] SerialIoNumber 0=3DI2C0, ..., 11=3DUART2 + + @retval SerialIo funciton number +**/ +UINT8 +GetSerialIoFunctionNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ); + +/** + Finds BAR values of SerialIo devices. + SerialIo devices can be configured to not appear on PCI so traditional m= ethod of reading BAR might not work. + + @param[in] SerialIoDevice 0=3DI2C0, ..., 11=3DUART2 + @param[in] BarNumber 0=3DBAR0, 1=3DBAR1 + + @retval SerialIo Bar value +**/ +UINTN +FindSerialIoBar ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice, + IN UINT8 BarNumber + ); + + +#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_LIB_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/SpiF= lashCommonLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library= /SpiFlashCommonLib.h new file mode 100644 index 0000000000..0e92c46c6b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Library/SpiFlashCom= monLib.h @@ -0,0 +1,96 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SPI_FLASH_COMMON_LIB_H__ +#define __SPI_FLASH_COMMON_LIB_H__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ); + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ); + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the wri= te. + @param[in,out] NumBytes On input, the number of bytes to write. = On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ); + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block t= o be erased. + This library assume that caller garantee tha= t the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical= block to be erased. + On output, the actual number of bytes erased. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchAccess.h = b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchAccess.h new file mode 100644 index 0000000000..923baaa3b0 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchAccess.h @@ -0,0 +1,621 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_ACCESS_H_ +#define _PCH_ACCESS_H_ + +#include "PchLimits.h" +#include "PchReservedResources.h" + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_SECOND +#define STALL_ONE_SECOND 1000000 +#endif + + +/// +/// The default PCH PCI bus number +/// +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + +// +// Default Vendor ID and Subsystem ID +// +#define V_PCH_INTEL_VENDOR_ID 0x8086 ///< Default Intel PCH Vendor = ID +#define V_PCH_DEFAULT_SID 0x7270 ///< Default Intel PCH Subsyst= em ID +#define V_PCH_DEFAULT_SVID_SID (V_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID <<= 16)) ///< Default INTEL PCH Vendor ID and Subsystem ID + +// +// Generic definitions for device enabling/disabling used by PCH code. +// +#define PCH_DEVICE_ENABLE 1 +#define PCH_DEVICE_DISABLE 0 +#define PCH_DEVICE_DEFAULT 2 + +// +// Include device register definitions +// +#include "PcieRegs.h" +#include "Register/PchRegsPcr.h" +#include "Register/PchRegsP2sb.h" +#include "Register/PchRegsHda.h" +#include "Register/PchRegsHsio.h" +#include "Register/PchRegsLan.h" +#include "Register/PchRegsLpc.h" +#include "Register/PchRegsPmc.h" +#include "Register/PchRegsPcie.h" +#include "Register/PchRegsSata.h" +#include "Register/PchRegsSmbus.h" +#include "Register/PchRegsSpi.h" +#include "Register/PchRegsThermal.h" +#include "Register/PchRegsUsb.h" +#include "Register/PchRegsGpio.h" +#include "Register/PchRegsTraceHub.h" +#include "Register/PchRegsDmi.h" +#include "Register/PchRegsItss.h" +#include "Register/PchRegsPsth.h" +#include "Register/PchRegsPsf.h" +#include "Register/PchRegsFia.h" +#include "Register/PchRegsDci.h" +#include "Register/PchRegsEva.h" + +// +// LPC Device ID macros +// +// +// Device IDs that are PCH-H Desktop specific +// +#define IS_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_0) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_1) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_2) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_3) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_4) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_5) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_6) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_UNFUSE) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU) \ + ) + +#define IS_PCH_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ) + +// +// Device IDs that are PCH-H Mobile specific +// + +#define IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_MB_0) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_MB_1) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_MB_2) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU) \ + ) + + +// +// Device IDs that are PCH-LP Mobile specific +// +#define IS_PCH_LP_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_UNFUSE) || \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU) || \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_MB_0) || \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_MB_1) || \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_MB_2) || \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_MB_3) \ + ) + +#define IS_PCH_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) || \ + IS_PCH_LP_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ) + +// +// Device IDS that are PCH Server\Workstation specific +#define IS_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_SVR_0) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_SVR_1) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_SVR_2) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_A14B) \ + ) + + +#define IS_PCH_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ) + +#define IS_PCH_H_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_DESKTOP (DeviceId) || \ + IS_PCH_H_LPC_DEVICE_ID_MOBILE (DeviceId) || \ + IS_PCH_H_LPC_DEVICE_ID_SERVER (DeviceId) \ + ) + +#define IS_PCH_LP_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_LPC_DEVICE_ID_MOBILE (DeviceId) \ + ) + +#define IS_PCH_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_LPC_DEVICE_ID(DeviceId) \ + ) + +#define IS_PCH_LBG_PROD_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId >=3D V_PCH_LBG_PROD_LPC_DEVICE_ID_0) && \ + (DeviceId <=3D V_PCH_LBG_PROD_LPC_DEVICE_ID_RESERVED_MAX) \ + ) + +#define IS_PCH_LBG_SSKU_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId >=3D V_PCH_LBG_LPC_DEVICE_ID_UNFUSED) && \ + (DeviceId <=3D V_PCH_LBG_LPC_DEVICE_ID_RESERVED_SS_MAX ) \ + ) + +#ifdef SKXD_EN +#define IS_PCH_LBG_D_SSKU_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId >=3D V_PCH_LBG_LPC_DEVICE_ID_SS_D1) && \ + (DeviceId <=3D V_PCH_LBG_LPC_DEVICE_ID_SS_D3 ) \ + ) +#endif // SKXD_EN + +#define IS_PCH_LBG_NS_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_LPC_DEVICE_ID_SS_T80_NS) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_LPC_DEVICE_ID_T) \ + ) + +#define IS_PCH_LBG_WS_LPC_DEVICE_ID(DeviceId) \ + ( \ + FALSE \ + ) + +#define IS_PCH_LBG_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_PROD_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_NS_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_WS_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_SSKU_LPC_DEVICE_ID(DeviceId) \ + ) + + +// +// SATA AHCI Device ID macros +// +#define IS_PCH_LBG_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SATA_DEVICE_ID_D_AHCI) || \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_AHCI) \ + ) + +#define IS_PCH_LBG_SSATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_AHCI) || \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_AHCI) \ + ) + + +#define IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_AHCI_A0) || \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_AHCI) \ + ) + +#define IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_SATA_DEVICE_ID_M_AHCI) \ + ) + +#define IS_PCH_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_AHCI_DEVICE_ID (DeviceId) \ + ) + + + +// +// SATA RAID Device ID macros +// +#define IS_PCH_LBG_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0) || \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1) || \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_RAID1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID1) \ + ) + +#define IS_PCH_LBG_SSATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_RAID) || \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0) || \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1) || \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_RAID1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID1) \ + ) + + +#define IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_RAID_PREM) || \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_RAID_ALTDIS) || \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_RAID_RSTE) || \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_RAID_RRT) \ + ) + + +#define IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_SATA_DEVICE_ID_M_RAID) || \ + (DeviceId =3D=3D V_PCH_LP_SATA_DEVICE_ID_M_RAID_ALTDIS) || \ + (DeviceId =3D=3D V_PCH_LP_SATA_DEVICE_ID_M_RAID_PREM) || \ + (DeviceId =3D=3D V_PCH_LP_SATA_DEVICE_ID_M_RAID_RRT) \ + ) + +#define IS_PCH_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_RAID_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_SSATA_RAID_DEVICE_ID(DeviceId) \ + ) + +// +// Combined SATA IDE/AHCI/RAID Device ID macros +// +#define IS_PCH_LBG_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SATA_RAID_DEVICE_ID (DeviceId) \ + ) +#define IS_PCH_LBG_SSATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SSATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_RAID_DEVICE_ID (DeviceId) \ + ) +#define IS_PCH_LBG_RAID_AVAILABLE(DeviceId) (TRUE) + +#define IS_PCH_H_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SATA_RAID_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_LP_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_SATA_RAID_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_H_RAID_AVAILABLE(DeviceId) (TRUE) +#define IS_PCH_LP_RAID_AVAILABLE(DeviceId) (TRUE) + +#define IS_PCH_RAID_AVAILABLE(DeviceId) \ + ( \ + IS_PCH_LBG_RAID_AVAILABLE(DeviceId) \ + ) + +// +// SPI Device ID macros +// +#define IS_PCH_LBG_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_SPI_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SPI_DEVICE_ID) \ + ) + +#define IS_PCH_H_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_SPI_DEVICE_ID) || \ + FALSE \ + ) + +#define IS_PCH_LP_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_SPI_DEVICE_ID) || \ + FALSE \ + ) + +#define IS_PCH_SPI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SPI_DEVICE_ID(DeviceId) \ + ) + +// +// USB Device ID macros +// +#define IS_PCH_LBG_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_USB_DEVICE_ID_XHCI_1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_USB_DEVICE_ID_XHCI_1) \ + ) + +#define IS_PCH_H_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_USB_DEVICE_ID_XHCI_1) \ + ) + +#define IS_PCH_LP_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_USB_DEVICE_ID_XHCI_1) \ + ) +#define IS_PCH_USB_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_USB_DEVICE_ID(DeviceId) \ + ) + +// +// PCIE Device ID macros +// +#define IS_PCH_LBG_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT20) \ + ) + +#define IS_PCH_LBG_PROD_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT20) \ + ) + + + +#define IS_PCH_H_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT20) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_MB_SUBD) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_DT_SUBD) \ + ) + +#define IS_PCH_LP_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT12) \ + ) + +#define IS_PCH_PCIE_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_PCIE_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_PROD_PCIE_DEVICE_ID(DeviceId) \ + ) + + +// +// HD Audio Device ID macros +// +#define IS_PCH_LBG_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_2) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_3) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_4) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_5) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_6) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_7) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_2) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_3) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_4) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_5) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_6) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_7) \ + ) + +#define IS_PCH_H_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_2) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_3) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_4) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_5) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_6) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_7) \ + ) + +#define IS_PCH_LP_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_2) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_3) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_4) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_5) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_6) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_7) \ + ) +#define IS_PCH_HDA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_HDA_DEVICE_ID(DeviceId) \ + ) + + +/// +/// Any device ID that is PCH-LBG +/// +#define IS_PCH_LBG_SMBUS_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_SMBUS_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SMBUS_DEVICE_ID) \ + ) + +#define IS_PCH_LBG_DEVICE_ID(DeviceId) \ + (\ + IS_PCH_LBG_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_PROD_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SMBUS_DEVICE_ID (DeviceId) || \ + (DeviceId =3D=3D V_PCH_LBG_MROM_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_MROM_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_LBG_MROM_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_MROM_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_LBG_THERMAL_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_THERMAL_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LBG_LAN_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_LAN_DEVICE_ID) \ + ) + +/// +/// Any device ID that is PCH-H +/// +#define IS_PCH_H_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_H_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_H_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SPI_DEVICE_ID (DeviceId) || \ + IS_PCH_H_HDA_DEVICE_ID (DeviceId) || \ + (DeviceId) =3D=3D V_PCH_H_THERMAL_DEVICE_ID || \ + (DeviceId) =3D=3D V_PCH_H_SMBUS_DEVICE_ID || \ + (DeviceId) =3D=3D V_PCH_H_LAN_DEVICE_ID \ + ) + +/// +/// Any device ID that is PCH-Lp +/// +#define IS_PCH_LP_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_HDA_DEVICE_ID (DeviceId) || \ + (DeviceId =3D=3D V_PCH_LP_THERMAL_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SMBUS_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SPI_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_LAN_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_DMA_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_I2C0_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_I2C1_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_SPI0_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_SPI1_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_UART0_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_UART1_DEVICE_ID ) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_SDIO_DEVICE_ID) \ + ) + +/// +/// Combined any device ID that is PCH-H or PCH-LP +/// +/// +/// And any device that is PCH LBG +/// +#define IS_PCH_DEVICE_ID(DeviceId) \ + (\ + IS_PCH_LBG_DEVICE_ID(DeviceId) \ + ) + + +/** + PCH PCR boot script accessing macro + Those macros are only available for DXE phase. +**/ +#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \ + S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), = Count, Buffer); \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), B= uffer, Buffer, 1, 1); + +#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd= ) \ + S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offse= t), DataOr, DataAnd); \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), D= ataOr, DataOr, 1, 1); + +#endif + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchLimits.h = b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchLimits.h new file mode 100644 index 0000000000..ce24100837 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchLimits.h @@ -0,0 +1,102 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_LIMITS_H_ +#define _PCH_LIMITS_H_ + +// +// PCIe limits +// +#define PCH_MAX_PCIE_ROOT_PORTS PCH_H_PCIE_MAX_ROOT_PORTS +#define PCH_H_PCIE_MAX_ROOT_PORTS 20 +#define PCH_LP_PCIE_MAX_ROOT_PORTS 12 + +#define PCH_MAX_PCIE_CONTROLLERS PCH_H_PCIE_MAX_CONTROLLERS +#define PCH_PCIE_CONTROLLER_PORTS 4 +#define PCH_H_PCIE_MAX_CONTROLLERS (PCH_H_PCIE_MAX_ROOT_PORTS / P= CH_PCIE_CONTROLLER_PORTS) +#define PCH_LP_PCIE_MAX_CONTROLLERS (PCH_LP_PCIE_MAX_ROOT_PORTS / = PCH_PCIE_CONTROLLER_PORTS) + +#define PCH_MAX_WM20_LANES_NUMBER 20 + +// +// PCIe clocks limits +// +#define PCH_MAX_PCIE_CLOCKS PCH_H_PCIE_MAX_ROOT_PORTS +#define PCH_LP_PCIE_MAX_CLK_REQ 6 +#define PCH_H_PCIE_MAX_CLK_REQ 16 + +// +// RST PCIe Storage Cycle Router limits +// +#define PCH_MAX_RST_PCIE_STORAGE_CR 3 + +// +// SATA limits +// +#define PCH_MAX_SATA_PORTS PCH_H_AHCI_MAX_PORTS +#define PCH_MAX_SSATA_PORTS 6 +#define PCH_H_AHCI_MAX_PORTS 8 ///< Max number of sat= a ports in SKL PCH H +#define PCH_LP_AHCI_MAX_PORTS 3 ///< Max number of sat= a ports in SKL PCH LP +#define PCH_SATA_MAX_DEVICES_PER_PORT 1 ///< Max support devic= e numner per port, Port Multiplier is not support. + +// +// USB limits +// +#define PCH_MAX_USB2_PORTS PCH_H_XHCI_MAX_USB2_PORTS + +#define PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS 14 ///< Max Physical Conn= ector XHCI, not counting virtual ports like USB-R. +#define PCH_LP_XHCI_MAX_USB2_PHYSICAL_PORTS 10 ///< Max Physical Conn= ector XHCI, not counting virtual ports like USB-R. + +#define PCH_H_XHCI_MAX_USB2_PORTS 16 ///< 14 High Speed lan= es + Including two ports reserved for USBr +#define PCH_LP_XHCI_MAX_USB2_PORTS 12 ///< 10 High Speed lan= es + Including two ports reserved for USBr + +#define PCH_MAX_USB3_PORTS PCH_H_XHCI_MAX_USB3_PORTS + +#define PCH_H_XHCI_MAX_USB3_PORTS 10 ///< 10 Super Speed la= nes +#define PCH_LP_XHCI_MAX_USB3_PORTS 6 ///< 6 Super Speed lan= es + +#define PCH_XHCI_MAX_SSIC_PORT_COUNT 2 ///< 2 SSIC ports in S= KL PCH-LP and SKL PCH-H + +// +// SerialIo limits +// +#define PCH_SERIALIO_MAX_CONTROLLERS 11 ///< Number of SerialIo c= ontrollers, this includes I2C, SPI and UART +#define PCH_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I= 2C controllers +#define PCH_LP_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I= 2C controllers for PCH-LP +#define PCH_H_SERIALIO_MAX_I2C_CONTROLLERS 4 ///< Number of SerialIo I= 2C controllers for PCH-H +#define PCH_SERIALIO_MAX_SPI_CONTROLLERS 2 ///< Number of SerialIo S= PI controllers +#define PCH_SERIALIO_MAX_UART_CONTROLLERS 3 ///< Number of SerialIo U= ART controllers + +// +// ISH limits +// +#define PCH_ISH_MAX_GP_PINS 8 +#define PCH_ISH_MAX_UART_CONTROLLERS 2 +#define PCH_ISH_MAX_I2C_CONTROLLERS 3 +#define PCH_ISH_MAX_SPI_CONTROLLERS 1 + +// +// SCS limits +// +#define PCH_SCS_MAX_CONTROLLERS 3 ///< Number of Storage and C= ommunication Subsystem controllers, this includes eMMC, SDIO, SDCARD + +// +// Flash Protection Range Register +// +#define PCH_FLASH_PROTECTED_RANGES 5 + +// +// Number of eSPI slaves +// +#define PCH_ESPI_MAX_SLAVE_ID 2 + +#define PCH_PCIE_SWEQ_COEFFS_MAX 5 + +#define LBG_A0 0x30 + +#endif // _PCH_LIMITS_H_ + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchPolicyCom= mon.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchPolicyCommon.h new file mode 100644 index 0000000000..243d15d45d --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchPolicyCommon.h @@ -0,0 +1,2212 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_POLICY_COMMON_H_ +#define _PCH_POLICY_COMMON_H_ + +#include "PchLimits.h" + +#pragma pack (push,1) +// +// ---------------------------- PCH General Config -----------------------= -------- +// + +typedef struct { + /** + Subsystem Vendor ID and Subsystem ID of the PCH devices. + This fields will be ignored if the value of SubSystemVendorId and SubS= ystemId + are both 0. + **/ + UINT16 SubSystemVendorId; ///< Default Subsystem Vendor ID o= f the PCH devices. Default is 0x8086 + UINT16 SubSystemId; ///< Default Subsystem ID of the P= CH devices. Default is 0x7270 + /** + This member describes whether or not the Compatibility Revision ID (CR= ID) feature + of PCH should be enabled. 0: Disable; 1: Enable + **/ + UINT32 Crid : 1; + UINT32 EnableClockSpreadSpec : 1; + UINT32 Serm : 1; + UINT32 RsvdBits0 : 30; ///< Reserved bits + UINT32 Rsvd0[2]; ///< Reserved bytes +} PCH_GENERAL_CONFIG; + + +#define FORCE_ENABLE 1 +#define FORCE_DISABLE 2 +#define PLATFORM_POR 0 +#define AUTO 0 +// +// ---------------------------- Reserved Page Config ---------------------= -------- +// + +enum PCH_RESERVED_PAGE_ROUTE { + PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC. + PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe. +}; + +// +// ---------------------------- PCI Express Config ---------------------- +// + +enum PCH_PCIE_SPEED { + PchPcieAuto, + PchPcieGen1, + PchPcieGen2, + PchPcieGen3 +}; + +/// +/// The values before AutoConfig match the setting of PCI Express Base Spe= cification 1.1, please be careful for adding new feature +/// +typedef enum { + PchPcieAspmDisabled, + PchPcieAspmL0s, + PchPcieAspmL1, + PchPcieAspmL0sL1, + PchPcieAspmAutoConfig, + PchPcieAspmMax +} PCH_PCIE_ASPM_CONTROL; + +/** + Refer to PCH EDS for the PCH implementation values corresponding + to below PCI-E spec defined ranges +**/ +typedef enum { + PchPcieL1SubstatesDisabled, + PchPcieL1SubstatesL1_1, + PchPcieL1SubstatesL1_2, + PchPcieL1SubstatesL1_1_2, + PchPcieL1SubstatesMax +} PCH_PCIE_L1SUBSTATES_CONTROL; + +enum PCH_PCIE_MAX_PAYLOAD { + PchPcieMaxPayload128 =3D 0, + PchPcieMaxPayload256, + PchPcieMaxPayloadMax +}; + +enum PCH_PCIE_COMPLETION_TIMEOUT { + PchPcieCompletionTO_Default, + PchPcieCompletionTO_50_100us, + PchPcieCompletionTO_1_10ms, + PchPcieCompletionTO_16_55ms, + PchPcieCompletionTO_65_210ms, + PchPcieCompletionTO_260_900ms, + PchPcieCompletionTO_1_3P5s, + PchPcieCompletionTO_4_13s, + PchPcieCompletionTO_17_64s, + PchPcieCompletionTO_Disabled +}; + +enum PCH_PCIE_MPL { + PchPcieMaxPayLoad128B, + PchPcieMaxPayLoad256B, + PchPcieMaxPayLoad512B, +}; + +typedef enum { + PchPcieEqDefault =3D 0, ///< Use reference code default (software = margining) + PchPcieEqHardware =3D 1, ///< Hardware equalization (experimental),= note this requires PCH-LP C0 or PCH-H D0 or newer + PchPcieEqSoftware =3D 2, ///< Use software margining flow + PchPcieEqStaticCoeff =3D 4 ///< Fixed equalization (requires Coeffici= ent settings per lane) +} PCH_PCIE_EQ_METHOD; + +/** + Represent lane specific PCIe Gen3 equalization parameters. +**/ +typedef struct { + UINT8 Cm; ///< Coefficient C-1 + UINT8 Cp; ///< Coefficient C+1 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM; + +/** + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability= of each PCH PCIe root port. +**/ +typedef struct { + UINT32 Enable : 1; ///< Root Port enabling,= 0: Disable; 1: Enable. + UINT32 HotPlug : 1; ///< Indicate whether th= e root port is hot plug available. 0: Disable; 1: Enable. + UINT32 PmSci : 1; ///< Indicate whether th= e root port power manager SCI is enabled. 0: Disable; 1: Enable. + UINT32 ExtSync : 1; ///< Indicate whether th= e extended synch is enabled. 0: Disable; 1: Enable. + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether th= e Transmitter Half Swing is enabled. 0: Disable; 1: Enable. + UINT32 AcsEnabled : 1; ///< Indicate whether th= e ACS is enabled. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 5; ///< Reserved bits. + UINT32 ClkReqSupported : 1; ///< Indicate whether de= dicated CLKREQ# is supported by the port. + /** + The ClkReq Signal mapped to this root port. Default is zero. Valid if = ClkReqSupported is TRUE. + This Number should not exceed the Maximum Available ClkReq Signals for= LP and H. + **/ + UINT32 ClkReqNumber : 4; + /** + Probe CLKREQ# signal before enabling CLKREQ# based power management. + Conforming device shall hold CLKREQ# low until CPM is enabled. This fe= ature attempts + to verify CLKREQ# signal is connected by testing pad state before enab= ling CPM. + In particular this helps to avoid issues with open-ended PCIe slots. + This is only applicable to non hot-plug ports. + 0: Disable; 1: Enable. + **/ + UINT32 ClkReqDetect : 1; + // + // Error handlings + // + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether th= e Advanced Error Reporting is enabled. 0: Disable; 1: Enable. + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether th= e Unsupported Request Report is enabled. 0: Disable; 1: Enable. + UINT32 FatalErrorReport : 1; ///< Indicate whether th= e Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 NoFatalErrorReport : 1; ///< Indicate whether th= e No Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 CorrectableErrorReport : 1; ///< Indicate whether th= e Correctable Error Report is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether th= e System Error on Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether th= e System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether th= e System Error on Correctable Error is enabled. 0: Disable; 1: Enabl= e. + /** + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX= _PAYLOAD + Changes Max Payload Size Supported field in Device Capabilities of the ro= ot port. + **/ + UINT32 MaxPayload : 2; + UINT32 RsvdBits1 : 3; ///< Reserved fields for= future expansion w/o protocol change + + UINT32 SlotImplemented : 1; + + UINT32 DeviceResetPadActiveHigh : 1; ///< Indicated whether P= ERST# is active 0: Low; 1: High, See: DeviceResetPad + /** + Determines each PCIE Port speed capability. + 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED) + **/ + UINT8 PcieSpeed; + /** + PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD). + 0: Default; 2: Software Search; 4: Fixed Coeficients + **/ + UINT8 Gen3EqPh3Method; + + UINT8 PhysicalSlotNumber; ///< Indicates the slot = number for the root port. Default is the value as root port index. + UINT8 CompletionTimeout; ///< The completion time= out configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT). Defa= ult is PchPcieCompletionTO_Default. + /** + The PCH pin assigned to device PERST# signal if available, zero otherw= ise. + This entry is used mainly in Gen3 software equalization flow. It is ne= cessary for some devices + (mainly some graphic adapters) to successfully complete the software e= qualization flow. + See also DeviceResetPadActiveHigh + **/ + UINT32 DeviceResetPad; + UINT32 Rsvd1; ///< Reserved bytes + // + // Power Management + // + UINT8 Aspm; ///< The ASPM configurat= ion of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAsp= mAutoConfig. + UINT8 L1Substates; ///< The L1 Substates co= nfiguration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default i= s PchPcieL1SubstatesL1_1_2. + UINT8 LtrEnable; ///< Latency Tolerance R= eporting Mechanism. 0: Disable; 1: Enable. + UINT8 LtrConfigLock; ///< 0: Disable; = 1: Enable. + UINT16 LtrMaxSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Snoop Latency. + UINT16 LtrMaxNoSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Non-Snoop Latency. + UINT8 SnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Mode. + UINT8 SnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Multiplier. + UINT16 SnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Value. + UINT8 NonSnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Mode. + UINT8 NonSnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Multiplier. + UINT16 NonSnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Value. + UINT32 SlotPowerLimitScale : 2; ///< (Test) Speci= fies scale used for slot power limit value. Leave as 0 to set to default. D= efault is zero. + UINT32 SlotPowerLimitValue : 12; ///< (Test) Speci= fies upper limit on power supplie by slot. Leave as 0 to set to default. De= fault is zero. + + UINT32 HsioRxSetCtleEnable : 1; ///< @deprecated, please= use HsioRxSetCtleEnable from PCH_HSIO_PCIE_LANE_CONFIG + UINT32 HsioRxSetCtle : 6; ///< @deprecated, please= use HsioRxSetCtle from PCH_HSIO_PCIE_LANE_CONFIG + // + // Gen3 Equaliztion settings + // + UINT32 Uptp : 4; ///< (Test) Upstr= eam Port Transmiter Preset used during Gen3 Link Equalization. Used for all= lanes. Default is 5. + UINT32 Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen3 Link Equalization. Used for a= ll lanes. Default is 7. + UINT32 RsvdBits3 : 3; ///< Reserved Bits + UINT32 Rsvd2[16]; ///< Reserved bytes +} PCH_PCIE_ROOT_PORT_CONFIG; + +/// +/// The PCH_PCIE_CONFIG block describes the expected configuration of the = PCH PCI Express controllers +/// +typedef struct { + /// + /// These members describe the configuration of each PCH PCIe root port. + /// + PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS]; + /// + /// Pci Delay (Latency) Optimization ECR - Engineering Change Request + /// + UINT8 PciDelayOptimizationEcr; + /// + /// Pch Pcie Max Read Request Size + /// + UINT8 MaxReadRequestSize; + /// + /// Gen3 Equalization settings for physiacal PCIe lane, index 0 represen= ts PCIe lane 1, etc. + /// Correstponding entries are used when root port EqPh3Method is PchPci= eEqStaticCoeff (default). + /// + PCH_PCIE_EQ_LANE_PARAM EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS= ]; + /// + /// (Test) This member describes whether PCIE root port Port 8xh = Decode is enabled. 0: Disable; 1: Enable. + /// + UINT32 EnablePort8xhDecode : 1; + /// + /// (Test) The Index of PCIe Port that is selected for Port8xh De= code (0 Based) + /// + UINT32 PchPciePort8xhDecodePortIndex : 5; + /// + /// This member describes whether the PCI Express Clock Gating for each = root port + /// is enabled by platform modules. 0: Disable; 1: Enable. + /// + UINT32 DisableRootPortClockGating : 1; + /// + /// This member describes whether Peer Memory Writes are enabled on the = platform. 0: Disable; 1: Enable. + /// + UINT32 EnablePeerMemoryWrite : 1; + /** + This member allows BIOS to control ICC PLL Shutdown by determining PCI= e devices are LTR capable + or leaving untouched. + - 0: Disable, ICC PLL Shutdown is determined by PCIe device LTR cap= ablility. + - To allow ICC PLL shutdown if all present PCIe devices are LTR capa= ble or if no PCIe devices are + presented for maximum power savings where possible. + - To disable ICC PLL shutdown when BIOS detects any non-LTR capable = PCIe device for ensuring device + functionality. + - 1: Enable, To allow ICC PLL shutdown even if some devices do not sup= port LTR capability. + **/ + UINT32 AllowNoLtrIccPllShutdown : 1; + /** + Compliance Test Mode shall be enabled when using Compliance Load Board. + 0: Disable, 1: Enable + **/ + UINT32 ComplianceTestMode : 1; + /** + RpFunctionSwap allows BIOS to use root port function number swapping w= hen root port of function 0 is disabled. + A PCIE device can have higher functions only when Function0 exists. To= satisfy this requirement, + BIOS will always enable Function0 of a device that contains more than = 0 enabled root ports. + - Enabled: One of enabled root ports get assigned to Function0. + This offers no guarantee that any particular root port will be avail= able at a specific DevNr:FuncNr location + - Disabled: Root port that corresponds to Function0 will be kept visib= le even though it might be not used. + That way rootport - to - DevNr:FuncNr assignment is constant. This o= ption will impact ports 1, 9, 17. + NOTE: This option will not work if ports 1, 9, 17 are fused or confi= gured for RST PCIe storage + NOTE: Disabling function swap may have adverse impact on power manag= ement. This option should ONLY + be used when each one of root ports 1, 9, 17: + - is configured as PCIe and has correctly configured ClkReq signal= , or + - does not own any mPhy lanes (they are configured as SATA or USB) + **/ + UINT32 RpFunctionSwap : 1; + + UINT32 RsvdBits0 : 21; + /** + The number of milliseconds reference code will wait for link to exit D= etect state for enabled ports + before assuming there is no device and potentially disabling the port. + It's assumed that the link will exit detect state before root port ini= tialization (sufficient time + elapsed since PLTRST de-assertion) therefore default timeout is zero. = However this might be useful + if device power-up seqence is controlled by BIOS or a specific device = requires more time to detect. + I case of non-common clock enabled the default timout is 15ms. + Default: 0 + **/ + UINT16 DetectTimeoutMs; + + /// + /// These are Competions Timeout settings for Uplink ports in Server PCH + /// + UINT8 PchPcieUX16CompletionTimeout; + UINT8 PchPcieUX8CompletionTimeout; + + /// + /// Max Payload Size settings for Upling ports in Server PCH + /// + UINT8 PchPcieUX16MaxPayload; + UINT8 PchPcieUX8MaxPayload; + + /// + /// Intel+ Virtual Technology for Directed I/O (VT-d) Support + /// + UINT8 VTdSupport; + UINT16 Rsvd0; ///< Reserved bytes + UINT32 Rsvd1[2]; ///< Reserved bytes +} PCH_PCIE_CONFIG; + + +/// +/// The PCH_PCIE_CONFIG2 block describes the additional configuration of t= he PCH PCI Express controllers +/// +typedef struct { + PCH_PCIE_EQ_PARAM SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX]; ///= < List of coefficients used during equalization (applicable to both softwar= e and hardware EQ) + PCH_PCIE_EQ_PARAM Rsvd0[3]; + UINT32 Rsvd1[4]; +} PCH_PCIE_CONFIG2; + +typedef struct { + UINT8 PchAdrEn; + UINT8 AdrTimerEn; + UINT8 AdrTimerVal; + UINT8 AdrMultiplierVal; + UINT8 AdrGpioSel; + UINT8 AdrHostPartitionReset; + UINT8 AdrSysPwrOk; + UINT8 AdrOverClockingWdt; + UINT8 AdrCpuThermalWdt; + UINT8 AdrPmcParityError; +} PCH_ADR_CONFIG; + +/** + The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane +**/ +typedef struct { + // + // HSIO Rx Eq + // Refer to the EDS for recommended values. + // Note that these setting are per-lane and not per-port + // + UINT32 HsioRxSetCtleEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 3 Set CTLE Value + UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set = CTLE Value + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value ove= rride + UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX O= utput Downscale Amplitude Adjustment value + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value ove= rride + UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX O= utput Downscale Amplitude Adjustment value + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value ove= rride + UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX O= utput Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved Bits + + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value ove= rride + UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX O= utput De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setti= ng value override + UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX O= utput -3.5dB Mode De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setti= ng value override + UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX O= utput -6.0dB Mode De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 11; ///< Reserved Bits + + // + // Server specific offsets + // + UINT32 HsioIcfgAdjLimitLoEnable : 1; /// < 0: Disable;= 1: Enable Set the floor on how many ticks the autovref can take. + UINT32 HsioIcfgAdjLimitLo : 5; /// < Set the floor on h= ow many ticks the autovref can take. (offset 0x9c) + UINT32 HsioSampOffstEvenErrSpEnable : 1; /// < 0: Disable;= 1: Enable EVEN ERR P sampler manual offset. + UINT32 HsioSampOffstEvenErrSp : 8; /// < EVEN ERR P sampler= manual offset. (offset 0xA0) + UINT32 RsvdBits2 : 17; ///< Reserved Bits + + UINT32 HsioRemainingSamplerOffEnable : 1; /// < 0: Disable;= 1: Enable Remaining EVEN/ODD ERR P and N sampler manual offset. + UINT32 HsioRemainingSamplerOff : 24; /// < Remaining EVEN/ODD= ERR P and N sampler manual offset. (offset 0xA4) + UINT32 HsioVgaGainCalEnable : 1; /// < 0: Disable;= 1: Enable VGA Gain CAL + UINT32 HsioVgaGainCal : 5; /// < VGA Gain Calibratio= n Value (offset 0x1C) + UINT32 RsvdBits3 : 1; ///< Reserved Bits + + UINT32 Rsvd4[12]; ///< Reserved bytes + +} PCH_HSIO_PCIE_LANE_CONFIG; + +/// +/// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO= for PCIe lanes +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for PCIe lanes. + /// + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS]; + UINT32 Rsvd0[3]; ///< Reserved bytes + +} PCH_HSIO_PCIE_CONFIG; + + +/// +/// The PCH_HSIO_PCIE_WM20_CONFIG block describes the configuration of the= HSIO for PCIe lanes +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for PCIe lanes. + /// + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_WM20_LANES_NUMBER]; + UINT32 Rsvd0[3]; ///< Reserved bytes + +} PCH_HSIO_PCIE_WM20_CONFIG; + +// +// ---------------------------- EVA Config ----------------------------- +// + +// EVA port function hide registers. + +typedef union { + UINT32 FuncHideVal; + struct _FuncHideBits { + UINT32 PchEvaMROM0Enable : 1; ///< MROM is never hidden + UINT32 PchEvaMROM1Hidden : 1; ///< Enable/disable MROM1 funcion, = 1 - hidden + UINT32 RsvdBits1 : 3; + UINT32 PchEvasSata1Hidden : 1; ///< Enable/disable sSata1, 1 - hid= den + UINT32 RsvdBits2 : 25; + UINT32 PchEvaLock : 1; ///< Lock registers in EVA + + } FuncHideBits; +} +PCH_EVA_DNDEVFUNCHIDE; + + +typedef struct { + PCH_EVA_DNDEVFUNCHIDE FuncHide; + UINT8 LockDown; +} +PCH_EVA_CONFIG; +// +// ---------------------------- SATA Config ----------------------------- +// + +typedef enum { + PchSataModeAhci, + PchSataModeRaid, + PchSataModeMax +} PCH_SATA_MODE; + +typedef enum { + PchSataOromDelay2sec, + PchSataOromDelay4sec, + PchSataOromDelay6sec, + PchSataOromDelay8sec +} PCH_SATA_OROM_DELAY; + +typedef enum { + PchSataSpeedDefault, + PchSataSpeedGen1, + PchSataSpeedGen2, + PchSataSpeedGen3 +} PCH_SATA_SPEED; + +/** + This structure configures the features, property, and capability for eac= h SATA port. +**/ +typedef struct { + /** + Enable SATA port. + It is highly recommended to disable unused ports for power savings + **/ + UINT32 Enable : 1; ///< 0: Disable; 1: E= nable + UINT32 HotPlug : 1; ///< 0: Disable; = 1: Enable + UINT32 InterlockSw : 1; ///< 0: Disable; = 1: Enable + UINT32 External : 1; ///< 0: Disable; = 1: Enable + UINT32 SpinUp : 1; ///< 0: Disable; = 1: Enable the COMRESET initialization Sequence to the device + UINT32 SolidStateDrive : 1; ///< 0: HDD; 1: S= SD + UINT32 DevSlp : 1; ///< 0: Disable; = 1: Enable DEVSLP on the port + UINT32 EnableDitoConfig : 1; ///< 0: Disable; = 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal) + UINT32 DmVal : 4; ///< DITO multiplier. De= fault is 15. + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout= (DITO), Default is 625. + /** + Support zero power ODD 0: Disable, 1: Enable. + This is also used to disable ModPHY dynamic power gate. + **/ + UINT32 ZpOdd : 1; + UINT32 RsvdBits0 : 9; ///< Reserved fields for= future expansion w/o protocol change + + UINT32 HsioRxEqBoostMagAdEnable : 1; ///< @deprecated, please= use HsioRxGen3EqBoostMagEnable + UINT32 HsioRxEqBoostMagAd : 6; ///< @deprecated, please= use HsioRxGen3EqBoostMag + + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< @deprecated, please= use HsioTxGen1DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen1DownscaleAmp : 6; ///< @deprecated, please= use HsioTxGen1DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< @deprecated, please= use HsioTxGen2DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen2DownscaleAmp : 6; ///< @deprecated, please= use HsioTxGen2DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + UINT32 Rsvd0 : 11; ///< Reserved bits + +} PCH_SATA_PORT_CONFIG; + +/** + Rapid Storage Technology settings. +**/ +typedef struct { + UINT32 RaidAlternateId : 1; ///< 0: Disable; 1: Enable = RAID Alternate ID + UINT32 Raid0 : 1; ///< 0: Disable; 1: Enable = RAID0 + UINT32 Raid1 : 1; ///< 0: Disable; 1: Enable = RAID1 + UINT32 Raid10 : 1; ///< 0: Disable; 1: Enable = RAID10 + UINT32 Raid5 : 1; ///< 0: Disable; 1: Enable = RAID5 + UINT32 Irrt : 1; ///< 0: Disable; 1: Enable = Intel Rapid Recovery Technology + UINT32 OromUiBanner : 1; ///< 0: Disable; 1: Enable = OROM UI and BANNER + UINT32 OromUiDelay : 2; ///< 00b: 2 secs; 01b: 4 se= cs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY) + UINT32 HddUnlock : 1; ///< 0: Disable; 1: Enable.= Indicates that the HDD password unlock in the OS is enabled + UINT32 LedLocate : 1; ///< 0: Disable; 1: Enable.= Indicates that the LED/SGPIO hardware is attached and ping to locate featu= re is enabled on the OS + UINT32 IrrtOnly : 1; ///< 0: Disable; 1: Enable.= Allow only IRRT drives to span internal and external ports + UINT32 SmartStorage : 1; ///< 0: Disable; 1: Enable = RST Smart Storage caching Bit + UINT32 EfiRaidDriverLoad :1; ///< 0: Dont load EFI RST/RSTe dri= ver; 1: Load EFI RST/RSTe driver + UINT32 Resvdbits : 18; ///< Reserved Bits +} PCH_SATA_RST_CONFIG; + +/** + This structure describes the details of Intel RST for PCIe Storage remap= ping + Note: In order to use this feature, Intel RST Driver is required +**/ +typedef struct { + /** + This member describes whether or not the Intel RST for PCIe Storage re= mapping should be enabled. 0: Disable; 1: Enable. + Note 1: If Sata Controller is disabled, PCIe Storage Remapping should = be disabled as well + Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI = controllers Class Code is configured as RAID + **/ + UINT32 Enable : 1; + /** + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <= b>0 =3D autodetect) + The supported ports for PCIe Storage remapping is different depend on = the platform and cycle router, the assignments are as below: + SKL PCH-LP RST PCIe Storage Cycle Router Assignment: + i.) RST PCIe Storage Cycle Router 2 -> RP5 - RP8 + ii.) RST PCIe Storage Cycle Router 3 -> RP9 - RP12 + + SKL PCH-H RST PCIe Storage Cycle Router Assignment: + i.) RST PCIe Storage Cycle Router 1 -> RP9 - RP12 + ii.) RST PCIe Storage Cycle Router 2 -> RP13 - RP16 + iii.) RST PCIe Storage Cycle Router 3 -> RP17 - RP20 + **/ + UINT32 RstPcieStoragePort : 5; + UINT32 RsvdBits0 : 2; ///< Reserved bit + /** + PCIe Storage Device Reset Delay in milliseconds (ms), which it guarant= ees such delay gap is fulfilled + before PCIe Storage Device configuration space is accessed after an re= set caused by the link disable and enable step. + Default value is 100ms. + **/ + UINT32 DeviceResetDelay : 8; + UINT32 RsvdBits1 : 16; ///< Reserved bits + + UINT32 Rsvd0[2]; ///< Reserved bytes +} PCH_RST_PCIE_STORAGE_CONFIG; + +/// +/// The PCH_SATA_CONFIG block describes the expected configuration of the = SATA controllers. +/// +typedef struct { + /// + /// This member describes whether or not the SATA controllers should be = enabled. 0: Disable; 1: Enable. + /// + UINT32 Enable : 1; + UINT32 TestMode : 1; ///< (Test)= 0: Disable; 1: Allow entrance to the PCH SATA test modes + UINT32 SalpSupport : 1; ///< 0: Disabl= e; 1: Enable Aggressive Link Power Management + UINT32 PwrOptEnable : 1; ///< 0: Disabl= e; 1: Enable SATA Power Optimizer on PCH side. + /** + eSATASpeedLimit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSA= TA port speed. + Please be noted, this setting could be cleared by HBA reset, which mig= ht be issued + by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver = after POST. + To support the Speed Limitation when POST, the EFI AHCI driver should = preserve the + setting before and after initialization. For support it after POST, it= 's dependent on + driver's behavior. + 0: Disable; 1: Enable + **/ + UINT32 eSATASpeedLimit : 1; + UINT32 EnclosureSupport : 1; ///< 0: Disa= ble; 1: Enable Enclosure Management Support + UINT32 Rsvdbits : 26; ///< Reserv= ed bits + + /** + Determines the system will be configured to which SATA mode (PCH_SATA_= MODE). Default is PchSataModeAhci. + **/ + PCH_SATA_MODE SataMode; + /** + Indicates the maximum speed the SATA controller can support + 0h: PchSataSpeedDefault; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2= ); 3h: 6 Gb/s (Gen 1) + **/ + PCH_SATA_SPEED SpeedLimit; + /** + This member configures the features, property, and capability for each= SATA port. + **/ + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS]; + PCH_SATA_RST_CONFIG Rst; ///< Setting a= pplicable to Rapid Storage Technology + /** + This member describes the details of implementation of Intel RST for P= CIe Storage remapping (Intel RST Driver is required) + **/ + PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORA= GE_CR]; + UINT32 Rsvd0[4]; ///< Reserved fiel= ds for future expansion +} PCH_SATA_CONFIG; + + +/** + The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane +**/ +typedef struct { + + // + // HSIO Rx Eq + // + UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value + + // + // HSIO Tx Eq + // + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value over= ride + UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Ou= tput Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved bits + + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value over= ride + UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Ou= tput Downscale Amplitude Adjustment + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value over= ride + UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Ou= tput Downscale Amplitude Adjustment + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride + UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Ou= tput De-Emphasis Adjustment Setting + + UINT32 HsioTxGen2DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride + UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Ou= tput De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 4; ///< Reserved bits + + UINT32 HsioTxGen3DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride + UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Ou= tput De-Emphasis Adjustment Setting value override + UINT32 RsvdBits2 : 25; ///< Reserved bits + + UINT32 Rsvd0[8]; ///< Reserved bytes +} PCH_HSIO_SATA_PORT_LANE; + + +/// +/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the= SATA controller. +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for SATA lanes. + /// + PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS]; + UINT32 Rsvd0[8]; /= //< Reserved bytes + +} PCH_HSIO_SATA_CONFIG; + +// +// --------------------------- IO APIC Config ----------------------------= -- +// +/** + The PCH_IOAPIC_CONFIG block describes the expected configuration of the = PCH + IO APIC, it's optional and PCH code would ignore it if the BdfValid bit = is + not TRUE. Bus:device:function fields will be programmed to the register + P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpos= e: + As the Requester ID when initiating Interrupt Messages to the processor. + As the Completer ID when responding to the reads targeting the IOxAPI's + Memory-Mapped I/O registers. + This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can + program this field to provide a unique Bus:Device:Function number for the + internal IOxAPIC. + The address resource range of IOAPIC must be reserved in E820 and ACPI as + system resource. +**/ +typedef struct { + UINT32 BdfValid : 1; ///< Set to 1 if BDF value is vali= d, PCH code will not program these fields if this bit is not TRUE. 0: Di= sable; 1: Enable. + UINT32 RsvdBits0 : 7; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus/Device/Function used as R= equestor / Completer ID. Default is 0xF0. + UINT32 DeviceNumber : 5; ///< Bus/Device/Function used as R= equestor / Completer ID. Default is 0x1F. + UINT32 FunctionNumber : 3; ///< Bus/Device/Function used as R= equestor / Completer ID. Default is 0x00. + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; 1: Enable = IOAPIC Entry 24-119 + UINT32 RsvdBits1 : 7; ///< Reserved bits + UINT8 IoApicId; ///< This member determines IOAPIC= ID. Default is 0x02. + UINT8 ApicRangeSelect; ///< Define address bits 19:12 for= the IOxAPIC range. Default is 0 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_IOAPIC_CONFIG; + +// +// ---------------------------- HPET Config ----------------------------- +// + +/** + The PCH_HPET_CONFIG block passes the bus/device/function value for HPET. + The address resource range of HPET must be reserved in E820 and ACPI as + system resource. +**/ +typedef struct { + /** + Determines if enable HPET timer. 0: Disable; 1: Enable. + The HPET timer address decode is always enabled. + This policy is used to configure the HPET timer count, and also the _S= TA of HPET device in ACPI. + While enabled, the HPET timer is started, else the HPET timer is halte= d. + **/ + UINT32 Enable : 1; + UINT32 BdfValid : 1; ///< Whether the BDF value is vali= d. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus Number HPETn used as Requ= estor / Completer ID. Default is 0xF0. + UINT32 DeviceNumber : 5; ///< Device Number HPETn used as R= equestor / Completer ID. Default is 0x1F. + UINT32 FunctionNumber : 3; ///< Function Number HPETn used as= Requestor / Completer ID. Default is 0x00. + UINT32 RsvdBits1 : 8; ///< Reserved bits + UINT32 Base; ///< The HPET base address. Defaul= t is 0xFED00000. +} PCH_HPET_CONFIG; + +// +// --------------------------- HD-Audio Config ---------------------------= --- +// +/// +/// The PCH_HDAUDIO_CONFIG block describes the expected configuration of t= he Intel HD Audio feature. +/// +#define PCH_HDAUDIO_AUTO 2 + +enum PCH_HDAUDIO_IO_BUFFER_OWNERSHIP { + PchHdaIoBufOwnerHdaLink =3D 0, ///< HD-Audio link owns all the I= /O buffers. + PchHdaIoBufOwnerHdaLinkI2sPort =3D 1, ///< HD-Audio link owns 4 and I2S= port owns 4 of the I/O buffers. + PchHdaIoBufOwnerI2sPort =3D 3 ///< I2S0 and I2S1 ports own all = the I/O buffers. +}; + +enum PCH_HDAUDIO_IO_BUFFER_VOLTAGE { + PchHdaIoBuf33V =3D 0, + PchHdaIoBuf18V =3D 1 +}; + +enum PCH_HDAUDIO_VC_TYPE { + PchHdaVc0 =3D 0, + PchHdaVc1 =3D 1 +}; + +enum PCH_HDAUDIO_DMIC_TYPE { + PchHdaDmicDisabled =3D 0, + PchHdaDmic2chArray =3D 1, + PchHdaDmic4chArray =3D 2, + PchHdaDmic1chArray =3D 3 +}; + +typedef enum { + PchHdaLinkFreq6MHz =3D 0, + PchHdaLinkFreq12MHz =3D 1, + PchHdaLinkFreq24MHz =3D 2, + PchHdaLinkFreq48MHz =3D 3, + PchHdaLinkFreq96MHz =3D 4, + PchHdaLinkFreqInvalid +} PCH_HDAUDIO_LINK_FREQUENCY; + +typedef enum { + PchHdaIDispMode2T =3D 0, + PchHdaIDispMode1T =3D 1 +} PCH_HDAUDIO_IDISP_TMODE; + +typedef struct { + /** + This member describes whether or not Intel HD Audio (Azalia) should be= enabled. + If enabled (in Auto mode) and no codec exists the reference code will = automatically disable + the HD Audio device. + 0: Disable, 1: Enable, 2: Auto (enabled if codec detected and initi= alized, disabled otherwise) + **/ + UINT32 Enable : 2; + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <= b>1: Enable + UINT32 Pme : 1; ///< Azalia wake-on-ring, 0: Di= sable; 1: Enable + UINT32 IoBufferOwnership : 2; ///< I/O Buffer Ownership Select: = 0: HD-A Link; 1: Shared, HD-A Link and I2S Port; 3: I2S Ports + UINT32 IoBufferVoltage : 1; ///< I/O Buffer Voltage Mode Selec= t: 0: 3.3V; 1: 1.8V + UINT32 VcType : 1; ///< Virtual Channel Type Select: = 0: VC0, 1: VC1 + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAUD= IO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HDA= UDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz + UINT32 IDispLinkTmode : 1; ///< iDisp-Link T-Mode (PCH_HDAUDI= O_IDISP_TMODE enum): 0: 2T, 1: 1T + /** + Universal Audio Architecture compliance for DSP enabled system: + 0: Not-UAA Compliant (Intel SST driver supported only), + 1: UAA Compliant (HDA Inbox driver or SST driver supported) + **/ + UINT32 DspUaaCompliance : 1; + UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconne= ction, 0: Not disconnected, enumerable; 1: Disconnected SDI, not enu= merable + UINT32 RsvdBits0 : 13; ///< Reserved bits 1 + /** + Bitmask of supported DSP endpoint configuration exposed via NHLT ACPI = table: + **/ + UINT32 DspEndpointDmic : 2; ///< DMIC Select (PCH_HDAUDIO_DMIC= _TYPE enum): 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array + UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: 0: D= isable; 1: Enable + UINT32 DspEndpointI2s : 1; ///< I2S enablement: 0: Disable= ; 1: Enable + UINT32 RsvdBits1 : 28; ///< Reserved bits 2 + /** + Bitmask of supported DSP features: + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT In= tel HFP; [BIT6] - BT Intel A2DP + [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel W= oV, 1: Windows Voice Activation + Default is zero. + **/ + UINT32 DspFeatureMask; + /** + Bitmask of supported DSP Pre/Post-Processing Modules. + Specific pre/post-processing module bit position must be coherent with= the ACPI implementation: + \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing Module Suppo= rt. + DspPpModuleMask is passed to ACPI as 'ADPM' NVS variable + Default is zero. + **/ + UINT32 DspPpModuleMask; + UINT16 ResetWaitTimer; ///< (Test) The delay timer= after Azalia reset, the value is number of microseconds. Default is 600= . + UINT8 Rsvd0[2]; ///< Reserved bytes, align to mult= iple 4 +} PCH_HDAUDIO_CONFIG; + +// +// ------------------------------ LAN Config -----------------------------= ---- +// + +/** + PCH intergrated LAN controller configuration settings. +**/ +typedef struct { + /** + Determines if enable PCH internal LAN, 0: Disable; 1: Enable. + When Enable is changed (from disabled to enabled or from enabled to di= sabled), + it needs to set LAN Disable regsiter, which might be locked by FDSWL r= egister. + So it's recommendated to issue a global reset when changing the status= for PCH Internal LAN. + **/ + UINT32 Enable : 1; + UINT32 K1OffEnable : 1; ///< Use CLKREQ for GbE power management;= 1: Enabled, 0: Disabled; + UINT32 RsvdBits0 : 4; ///< Reserved bits + UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# i= s supported; 1: Enabled, 0: Disabled; + UINT32 ClkReqNumber : 4; ///< CLKREQ# used by GbE. Valid if ClkReq= Supported is TRUE. + UINT32 RsvdBits1 : 21; ///< Reserved bits + UINT32 Rsvd0; ///< Reserved bytes +} PCH_LAN_CONFIG; + +// +// --------------------------- SMBUS Config ------------------------------ +// + +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128 + +/// +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capabl= e devices in the platform. +/// +typedef struct { + /** + This member describes whether or not the SMBus controller of PCH shoul= d be enabled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, = 0: Disable; 1: Enable. + UINT32 DynamicPowerGating : 1; ///< (Test) Disable = or Enable Smbus dynamic power gating. + UINT32 RsvdBits0 : 29; ///< Reserved bits + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space)= . Default is 0xEFA0. + UINT8 Rsvd0; ///< Reserved bytes + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the= RsvdSmbusAddressTable. + /** + Array of addresses reserved for non-ARP-capable SMBus devices. + **/ + UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; +} PCH_SMBUS_CONFIG; + +// +// --------------------------- Lock Down Config --------------------------= ---- +// +/** + The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of t= he PCH + for security requirement. +**/ +typedef struct { + /** + (Test) Enable SMI_LOCK bit to prevent writes to the Global SMI = Enable bit. 0: Disable; 1: Enable. + **/ + UINT32 GlobalSmi : 1; + /** + (Test) Enable BIOS Interface Lock Down bit to prevent writes to= the Backup Control Register + Top Swap bit and the General Control and Status Registers Boot BIOS St= raps. 0: Disable; 1: Enable. + **/ + UINT32 BiosInterface : 1; + /** + (Test) Enable RTC lower and upper 128 byte Lock bits to lock By= tes 38h-3Fh in the upper + and lower 128-byte bank of RTC RAM. 0: Disable; 1: Enable. + **/ + UINT32 RtcLock : 1; + /** + Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:Reg= DCh[5]) + for the BIOS region protection. When it is enabled, the BIOS Region ca= n only be + modified from SMM after EndOfDxe protocol is installed. + Note: When BiosLock is enabled, platform code also needs to update to = take care + of BIOS modification (including SetVariable) in DXE or runtime phase a= fter + EndOfDxe protocol is installed. 0: Disable; 1: Enable. + **/ + UINT32 BiosLock : 1; + /** + Enable InSMM.STS (EISS) in SPI + If this bit is set, then WPD must be a '1' and InSMM.STS must be '1' a= lso + in order to write to BIOS regions of SPI Flash. If this bit is clear, + then the InSMM.STS is a don't care. + The BIOS must set the EISS bit while BIOS Guard support is enabled. + In recovery path, platform can temporary disable EISS for SPI programm= ing in + PEI phase or early DXE phase. + 0: Clear EISS bit; 1: Set EISS bit. + **/ + UINT32 SpiEiss : 1; + /** + Lock configuration and/or state of vendor-defined set of GPIOs. + 0: Don't lock; 1: Lock + **/ + UINT32 GpioLockDown : 1; + /** + Lock TCO Base Address. + D31:F4 (SMBus Controller) Offset 54h: TCOCTL (TCO Control Register) Bi= t 0: TCO_BASE_LOCK (TCO Base Lock) + 0: Don't lock; 1: Lock + **/ + UINT32 TcoLock : 1; + + /** + (Test) Enable Lock bit for Device Function Hide Register in + MS Unit Device Function Hide Control Register (MSDEVFUNCHIDE) + 0: Disable; 1: Enable. + **/ + UINT32 EvaLockDown : 1; + UINT32 RsvdBits0 : 24; ///< Reserved bits +} PCH_LOCK_DOWN_CONFIG; + +// +// --------------------------- Thermal Config ----------------------------= -------- +// +/** + This structure lists PCH supported throttling register setting for custi= mization. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 T0Level : 9; ///< Custimized T0Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 T1Level : 9; ///< Custimized T1Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 T2Level : 9; ///< Custimized T2Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 TTEnable : 1; ///< Enable the thermal throttle f= unction. If SuggestedSetting is used, this settings is ignored. + /** + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13= will force at least T2 state. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTState13Enable : 1; + /** + When set to 1, this entire register (TL) is locked and remains locked = until the next platform reset. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTLock : 1; + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values. + /** + ULT processors support thermal management and cross thermal throttling= between the processor package + and LP PCH. The PMSYNC message from PCH to CPU includes specific bit f= ields to update the PCH + thermal status to the processor which is factored into the processor t= hrottling. + Enable/Disable PCH Cross Throttling; 0: Disabled, 1: Enabled. + **/ + UINT32 PchCrossThrottling : 1; + UINT32 Rsvd0; ///< Reserved bytes +} THERMAL_THROTTLE_LEVELS; + +/** + This structure allows to customize DMI HW Autonomous Width Control for T= hermal and Mechanical spec design. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonom= ous Width Enable + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 TS0TW : 2; ///< Thermal Sensor 0 Target Wi= dth + UINT32 TS1TW : 2; ///< Thermal Sensor 1 Target Wi= dth + UINT32 TS2TW : 2; ///< Thermal Sensor 2 Target Wi= dth + UINT32 TS3TW : 2; ///< Thermal Sensor 3 Target Wi= dth + UINT32 RsvdBits1 : 16; ///< Reserved bits +} DMI_HW_WIDTH_CONTROL; + +/** + This structure lists PCH supported SATA thermal throttling register sett= ing for custimization. + The settings is programmed through SATA Index/Data registers. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 P0T1M : 2; ///< Port 0 T1 Multipler + UINT32 P0T2M : 2; ///< Port 0 T2 Multipler + UINT32 P0T3M : 2; ///< Port 0 T3 Multipler + UINT32 P0TDisp : 2; ///< Port 0 Tdispatch + + UINT32 P1T1M : 2; ///< Port 1 T1 Multipler + UINT32 P1T2M : 2; ///< Port 1 T2 Multipler + UINT32 P1T3M : 2; ///< Port 1 T3 Multipler + UINT32 P1TDisp : 2; ///< Port 1 Tdispatch + + UINT32 P0Tinact : 2; ///< Port 0 Tinactive + UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init= Tdispatch + UINT32 P1Tinact : 2; ///< Port 1 Tinactive + UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init= Tdispatch + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values + UINT32 RsvdBits0 : 9; ///< Reserved bits +} SATA_THERMAL_THROTTLE; + +/** + This structure decides the settings of PCH Thermal throttling. When the = Suggested Setting + is enabled, PCH RC will use the suggested representative values. +**/ +typedef struct { + THERMAL_THROTTLE_LEVELS TTLevels; + DMI_HW_WIDTH_CONTROL DmiHaAWC; + SATA_THERMAL_THROTTLE SataTT; + SATA_THERMAL_THROTTLE sSataTT; +} PCH_THERMAL_THROTTLING; + +/** + This structure configures PCH memory throttling thermal sensor GPIO PIN = settings +**/ +typedef struct { + /** + GPIO PM_SYNC enable, 0:Diabled, 1:Enabled + When enabled, RC will overrides the selected GPIO native mode. + For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1 + For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2 + For SKL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, C= PU_GP_3 is GPP_B4. + **/ + UINT32 PmsyncEnable : 1; + UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 st= ate, 0:Disabled, 1:Enabled + UINT32 PinSelection : 1; ///< GPIO Pin assignment selection= , 0: default, 1: secondary + UINT32 RsvdBits0 : 29; +} TS_GPIO_PIN_SETTING; + +enum PCH_PMSYNC_GPIO_X_SELECTION { + TsGpioC, + TsGpioD, + MaxTsGpioPin +}; + +/** + This structure supports an external memory thermal sensor (TS-on-DIMM or= TS-on-Board). +**/ +typedef struct { + /** + This will enable PCH memory throttling. + While this policy is enabled, must also enable EnableExtts in SA policy. + 0: Disable; 1: Enable + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; + /** + GPIO_C and GPIO_D selection for memory throttling. + It's strongly recommended to choose GPIO_C and GPIO_D for memory throt= tling feature, + and route EXTTS# accordingly. + **/ + TS_GPIO_PIN_SETTING TsGpioPinSetting[2]; +} PCH_MEMORY_THROTTLING; + +/** + The PCH_THERMAL_CONFIG block describes the expected configuration of the= PCH for Thermal. +**/ +typedef struct { + /** + This field reports the status of Thermal Device. When it reports Therm= alDevice + is disabled, the PCI configuration space of thermal device will be hid= den by + setting TCFD and PCR[PSF2] TRH PCIEN[8] prior to end of POST. + **/ + UINT32 ThermalDeviceEnable : 2; ///< 0: Disabled, 1: Enabled in= PCI mode, 2: Enabled in ACPI mode + UINT32 TsmicLock : 1; ///< This locks down "SMI Enable o= n Alert Thermal Sensor Trip". 0: Disabled, 1: Enabled. + UINT32 RsvdBits0 : 29; + /** + This field decides the settings of Thermal throttling. When the Sugges= ted Setting + is enabled, PCH RC will use the suggested representative values. + **/ + PCH_THERMAL_THROTTLING ThermalThrottling; + /** + Memory Thermal Management settings + **/ + PCH_MEMORY_THROTTLING MemoryThrottling; + /** + This field decides the temperature, default is zero. + - 0x00 is the hottest + - 0x1FF is the lowest temperature + **/ + UINT16 PchHotLevel; + UINT8 Rsvd0[6]; +} PCH_THERMAL_CONFIG; + +enum PCH_THERMAL_DEVICE { + PchThermalDeviceDisabled, + PchThermalDeviceEnabledPci, + PchThermalDeviceEnabledAcpi, + PchThermalDeviceAuto +}; + +// +// ---------------------- Power Management Config ------------------------= -- +// +/** + This PCH_POWER_RESET_STATUS Specifies which Power/Reset bits need to be = cleared by the PCH Init Driver. + Usually platform drivers take care of these bits, but if not, let PCH In= it driver clear the bits. +**/ +typedef struct { + UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in = the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 MeHrstColdSts : 1; ///< Clear the ME_HRST_COLD_STS bi= t in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable<= /b>. + UINT32 MeHrstWarmSts : 1; ///< Clear the ME_HRST_WARM_STS bi= t in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable<= /b>. + UINT32 MeHostPowerDn : 1; ///< Clear the ME_HOST_PWRDN bit i= n the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit = in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 27; +} PCH_POWER_RESET_STATUS; + +/** + This PCH_GBL2HOST_EN specifes enable bits related to the "Convert Global= Resets to Host Resets" (G2H) feature +**/ +typedef union { + struct { + UINT32 G2H_FEA : 1; ///< G2H Feature Enable: 0: Disable; = 1: Enable. + UINT32 LTRESET : 1; ///< LT RESET G2H Enable: 0: Disable;= 1: Enable. + UINT32 PMCGBL : 1; ///< PMC FW-Initiated Global Reset G2= H Enable: 0: Disable; 1: Enable. + UINT32 CPUTHRM : 1; ///< CPU Thermal Trip G2H Enable: 0: = Disable; 1: Enable. + UINT32 PCHTHRM : 1; ///< PCH Internal Thermal Trip G2H En= able: Disable; 1: Enable. + UINT32 PBO : 1; ///< Power Button Override G2H Enable= : 0: Disable; 1: Enable. + UINT32 MEPBO : 1; ///< ME-Initiated Power Button Overri= de G2H: 0: Disable; 1: Enable. + UINT32 MEWDT : 1; ///< ME FW Watchdog Timer G2H Enable:= 0: Disable; 1: Enable. + UINT32 MEGBL : 1; ///< ME-Initiated Global Reset G2H En= able: Disable; 1: Enable. + UINT32 CTWDT : 1; ///< CPU Thermal Watchdog Timer G2H E= nable: Disable; 1: Enable. + UINT32 PMCWDT : 1; ///< PMC FW Watchdog Timer G2H Enable= : Disable; 1: Enable. + UINT32 ME_UERR : 1; ///< ME Uncorrectable Error G2H Enabl= e: Disable; 1: Enable. + UINT32 SYSPWR : 1; ///< SYS_PWROK Failure G2H Enable: Di= sable; 1: Enable. + UINT32 OCWDT : 1; ///< Over-Clocking WDT G2H Enable: Di= sable; 1: Enable. + UINT32 PMC_PARERR : 1; ///< PMC Parity Error G2H Enable: 0: = Disable; 1: Enable. + UINT32 Reserved : 1; ///< Reserved + UINT32 IEPBO : 1; ///< IE-Initiated Power Button Overri= de G2H: 0: Disable; 1: Enable. + UINT32 IEWDT : 1; ///< IE FW Watchdog Timer G2H Enable:= 0: Disable; 1: Enable. + UINT32 IEGBLN : 1; ///< IE-Initiated Global Reset G2H En= able: 0: Disable; 1: Enable. + UINT32 IE_UERRN : 1; ///< IE Uncorrectable Error G2H Enabl= e: 0: Disable; 1: Enable. + UINT32 ACRU_ERR_2H_EN : 1; ///< AC RU Error G2H Enable: 0: Disab= le; 1: Enable. + } Bits; + UINT32 Value; +} PCH_GBL2HOST_EN; + +/** + This structure allows to customize PCH wake up capability from S5 or Dee= pSx by WOL, LAN, PCIE wake events. +**/ +typedef struct { + /** + Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B= (GEN_PMCON_B) register. + When set to 1, this bit blocks wake events from PME_B0_STS in S5, rega= rdless of the state of PME_B0_EN. + When cleared (default), wake events from PME_B0_STS are allowed in S5 = if PME_B0_EN =3D 1. 0: Disable; 1: Enable. + **/ + UINT32 PmeB0S5Dis : 1; + UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enabl= e Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0= : Disable; 1: Enable. + UINT32 Gp27WakeFromDeepSx : 1; ///< @deprecated + UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to w= ake from deep Sx. 0: Disable; 1: Enable. + UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from S= x, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0= : Disable; 1: Enable. + UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from D= eepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <= b>0: Disable; 1: Enable. + UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wa= ke from deep Sx. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 25; +} PCH_WAKE_CONFIG; + +typedef enum { + PchDeepSxPolDisable, + PchDpS5BatteryEn, + PchDpS5AlwaysEn, + PchDpS4S5BatteryEn, + PchDpS4S5AlwaysEn, + PchDpS3S4S5BatteryEn, + PchDpS3S4S5AlwaysEn +} PCH_DEEP_SX_CONFIG; + +typedef enum { + PchSlpS360us, + PchSlpS31ms, + PchSlpS350ms, + PchSlpS32s +} PCH_SLP_S3_MIN_ASSERT; + +typedef enum { + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing a= nd Reset Signal Timings table + PchSlpS41s, + PchSlpS42s, + PchSlpS43s, + PchSlpS44s +} PCH_SLP_S4_MIN_ASSERT; + +typedef enum { + PchSlpSus0ms, + PchSlpSus500ms, + PchSlpSus1s, + PchSlpSus4s +} PCH_SLP_SUS_MIN_ASSERT; + +typedef enum { + PchSlpA0ms, + PchSlpA4s, + PchSlpA98ms, + PchSlpA2s +} PCH_SLP_A_MIN_ASSERT; + +typedef enum { + PchPmGrPfetDur1us, + PchPmGrPfetDur2us, + PchPmGrPfetDur5us, + PchPmGrPfetDur20us +} PCH_PM_GR_PFET_DUR; + +/** + The PCH_PM_CONFIG block describes expected miscellaneous power managemen= t settings. + The PowerResetStatusClear field would clear the Power/Reset status bits,= please + set the bits if you want PCH Init driver to clear it, if you want to che= ck the + status later then clear the bits. +**/ +typedef struct { + /** + Specify which Power/Reset bits need to be cleared by + the PCH Init Driver. + Usually platform drivers take care of these bits, but if + not, let PCH Init driver clear the bits. + **/ + PCH_POWER_RESET_STATUS PowerResetStatusClear; + PCH_WAKE_CONFIG WakeConfig; ///< Specify W= ake Policy + PCH_DEEP_SX_CONFIG PchDeepSxPol; ///< Deep Sx P= olicy. Default is PchDeepSxPolDisable. + PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert; ///< SLP_S3 Mi= nimum Assertion Width Policy. Default is PchSlpS350ms. + PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert; ///< SLP_S4 Mi= nimum Assertion Width Policy. Default is PchSlpS44s. + PCH_SLP_SUS_MIN_ASSERT PchSlpSusMinAssert; ///< SLP_SUS M= inimum Assertion Width Policy. Default is PchSlpSus4s. + PCH_SLP_A_MIN_ASSERT PchSlpAMinAssert; ///< SLP_A Min= imum Assertion Width Policy. Default is PchSlpA2s. + /** + This member describes whether or not the PCI ClockRun feature of PCH s= hould + be enabled. 0: Disable; 1: Enable + **/ + UINT32 PciClockRun : 1; + UINT32 SlpStrchSusUp : 1; ///< 0: Dis= able; 1: Enable SLP_X Stretching After SUS Well Power Up + /** + Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; 1: Enable. + Configure On DC PHY Power Diable according to policy SlpLanLowDc. + When this is enabled, SLP_LAN# will be driven low when ACPRESENT is lo= w. + This indicates that LAN PHY should be powered off on battery mode. + This will override the DC_PP_DIS setting by WolEnableOverride. + **/ + UINT32 SlpLanLowDc : 1; + /** + PCH power button override period. + 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s + Default is 0: 4s + **/ + UINT32 PwrBtnOverridePeriod : 3; + /** + (Test) + Disable/Enable PCH to CPU enery report feature. 0: Disable; 1: = Enable. + Enery Report is must have feature. Wihtout Energy Report, the performa= nce report + by workloads/benchmarks will be unrealistic because PCH's energy is no= t being accounted + in power/performance management algorithm. + If for some reason PCH energy report is too high, which forces CPU to = try to reduce + its power by throttling, then it could try to disable Energy Report to= do first debug. + This might be due to energy scaling factors are not correct or the LPM= settings are not + kicking in. + **/ + UINT32 DisableEnergyReport : 1; + /** + When set to Disable, PCH will internal pull down AC_PRESENT in deep SX= and during G3 exit. + When set to Enable, PCH will not pull down AC_PRESENT. + This setting is ignored when DeepSx is not supported. + Default is 0:Disable + **/ + UINT32 DisableDsxAcPresentPulldown : 1; + /** + (Test) + When set to true, this bit disallows host reads to PMC XRAM. + BIOS must set this bit (to disable and lock the feature) prior to pass= ing control to OS + 0:Disable, 1:Enable + **/ + UINT32 PmcReadDisable : 1; + /** + This determines the type of reset issued during the capsule update proc= ess by UpdateCapsule(). + The default is 0:S3 Resume, 1:Warm reset. + **/ + UINT32 CapsuleResetType : 1; + /** + Power button native mode disable. + While FALSE, the PMC's power button logic will act upon the input valu= e from the GPIO unit, as normal. + While TRUE, this will result in the PMC logic constantly seeing the po= wer button as de-asserted. + Default is FALSE. + **/ + UINT32 DisableNativePowerButton : 1; + /** + Indicates whether SLP_S0# is to be asserted when PCH reaches idle stat= e. + When set to one SLP_S0# will be asserted in idle state. + When set to zero SLP_S0# will not toggle and is always drivern high. + 0:Disable, 1:Enable + + Warning: In SKL PCH VCCPRIM_CORE must NOT be reduced based on SLP_S0# = being asserted. + If a platform is using SLP_S0 to lower PCH voltage the below policy mu= st be disabled. + **/ + UINT32 SlpS0Enable : 1; + UINT32 DirtyWarmReset : 1; ///< DirtyWarm= Reset enable + UINT32 StallDirtyWarmReset : 1; ///< Stall dur= ing DWR + UINT32 GrPfetDurOnDef : 2; ///< Global Re= set PFET duration + UINT32 Dwr_MeResetPrepDone : 1; ///< ME Reset = Prep Done + UINT32 Dwr_IeResetPrepDone : 1; ///< IE Reset = Prep Done + UINT32 Dwr_BmcRootPort : 8; ///< Root port= where BMC is connected to + UINT32 RsvdBits0 : 6; ///< @todo ADD= DESCRIPTION + + PCH_GBL2HOST_EN PchGbl2HostEn; + /** + Reset Power Cycle Duration could be customized in the unit of second. = Please refer to EDS + for all support settings. PCH HW default is 4 seconds, and range is 1~= 4 seconds, where + 0 is default, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds. + And make sure the setting correct, which never less than the following= register. + - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH + - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH + - PWRM_CFG.SLP_A_MIN_ASST_WDTH + - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH + **/ + UINT8 PchPwrCycDur; + /** + Specifies the Pcie Pll Spread Spectrum Percentage + The value of this policy is in 1/10th percent units. + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% + The default is 0xFF: AUTO - No BIOS override. + **/ + UINT8 PciePllSsc; + UINT8 Rsvd0[2]; ///< Reser= ved bytes + +} PCH_PM_CONFIG; + +// +// ---------------------------- DMI Config ----------------------------- +// + +/// +/// The PCH_DMI_CONFIG block describes the expected configuration of the P= CH for DMI. +/// +typedef struct { + /** + 0: Disable; 1: Enable ASPM on PCH side of the DMI Link. + While DmiAspm is enabled, DMI ASPM will be set to Intel recommended va= lue. + **/ + UINT32 DmiAspm : 1; + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable = DMI Power Optimizer on PCH side. + BOOLEAN DmiStopAndScreamEnable : 1; + UINT32 DmiLinkDownHangBypass : 1; + UINT32 Rsvdbits : 29; + UINT32 Rsvd0[6]; ///< Reserved bytes +} PCH_DMI_CONFIG; + +// +// --------------------------- Serial IRQ Config -------------------------= ----- +// + +typedef enum { + PchQuietMode, + PchContinuousMode +} PCH_SIRQ_MODE; +/// +/// Refer to PCH EDS for the details of Start Frame Pulse Width in Continu= ous and Quiet mode +/// +typedef enum { + PchSfpw4Clk, + PchSfpw6Clk, + PchSfpw8Clk +} PCH_START_FRAME_PULSE; + +/// +/// The PCH_LPC_SIRQ_CONFIG block describes the expected configuration of = the PCH for Serial IRQ. +/// +typedef struct { + UINT32 SirqEnable : 1; ///< Determines if enabl= e Serial IRQ. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; ///< Reserved bits + PCH_SIRQ_MODE SirqMode; ///< Serial IRQ Mode Sel= ect. 0: quiet mode 1: continuous mode. + PCH_START_FRAME_PULSE StartFramePulse; ///< Start Frame Pulse W= idth. Default is PchSfpw4Clk. + UINT32 Rsvd0; ///< Reserved bytes +} PCH_LPC_SIRQ_CONFIG; + + +// +// --------------------------- Port 61h Emulation in SMM -----------------= ------------- +// +/** + This structure is used for the emulation feature for Port61h read. The p= ort is trapped + and the SMI handler will toggle bit4 according to the handler's internal= state. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disabl= e; 1: Enable the emulation + UINT32 RsvdBits0 : 31; ///< Reserved = bits +} PCH_PORT61H_SMM_CONFIG; + +// +// --------------------- Interrupts Config ------------------------------ +// +typedef enum { + PchNoInt, ///< No Interrupt Pin + PchIntA, + PchIntB, + PchIntC, + PchIntD +} PCH_INT_PIN; + +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and= interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_I= NT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} PCH_DEVICE_INTERRUPT_CONFIG; + +#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices +#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers= in ITSS + +/// +/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. +/// +typedef struct { + UINT8 NumOfDevIntConfig; = ///< Number of entries in DevIntConfig table + UINT8 Rsvd0[3]; = ///< Reserved bytes, align to multiple 4. + PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFI= G]; ///< Array which stores PCH devices interrupts settings + UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; = ///< Array which stores interrupt routing for 8259 controller + UINT8 GpioIrqRoute; = ///< Interrupt routing for GPIO. Default is 14. + UINT8 SciIrqSelect; = ///< Interrupt select for SCI. Default is 9. + UINT8 TcoIrqSelect; = ///< Interrupt select for TCO. Default is 9. + UINT8 TcoIrqEnable; = ///< Enable IRQ generation for TCO. 0: Disable; 1: Enable. +} PCH_INTERRUPT_CONFIG; + +// +// --------------------- TraceHub Config ------------------------------ +// + +/// +/// The PCH_TRACE_HUB_CONFIG block describes TraceHub settings for PCH. +/// +typedef struct { + UINT32 EnableMode : 2; ///< 0 =3D Disable 2 =3D Host= Debugger enabled + UINT32 PchTraceHubHide : 1; + UINT32 RsvdBits0 : 29; ///< Reserved bits + UINT32 MemReg0Size; ///< Default is 0 (none). + UINT32 MemReg1Size; ///< Default is 0 (none). +} PCH_TRACE_HUB_CONFIG; + + +// +// ------------------- CIO2 FLIS registers Config -------------------- +// + +/// +/// The PCH_SKYCAM_CIO2_FLS_CONFIG block describes SkyCam CIO2 FLS registe= rs configuration. +/// +typedef struct { + UINT32 PortATrimEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port A Clk Trim + UINT32 PortBTrimEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port B Clk Trim + UINT32 PortCTrimEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port C Clk Trim + UINT32 PortDTrimEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port D Clk Trim + UINT32 PortACtleEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port A Ctle + UINT32 PortBCtleEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port B Ctle + UINT32 PortCDCtleEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port C/D Ctle + UINT32 RsvdBits0 : 25; + + UINT32 PortACtleCapValue : 4; /// Port A Ctle Cap Value + UINT32 PortBCtleCapValue : 4; /// Port B Ctle Cap Value + UINT32 PortCDCtleCapValue : 4; /// Port C/D Ctle Cap Value + UINT32 PortACtleResValue : 5; /// Port A Ctle Res Value + UINT32 PortBCtleResValue : 5; /// Port B Ctle Res Value + UINT32 PortCDCtleResValue : 5; /// Port C/D Ctle Res Value + UINT32 RsvdBits1 : 5; + + UINT32 PortAClkTrimValue : 4; /// Port A Clk Trim Value + UINT32 PortBClkTrimValue : 4; /// Port B Clk Trim Value + UINT32 PortCClkTrimValue : 4; /// Port C Clk Trim Value + UINT32 PortDClkTrimValue : 4; /// Port D Clk Trim Value + UINT32 PortADataTrimValue : 16; /// Port A Data Trim Value + + UINT32 PortBDataTrimValue : 16; /// Port B Data Trim Value + UINT32 PortCDDataTrimValue : 16; /// Port C/D Data Trim Value + +} PCH_SKYCAM_CIO2_FLS_CONFIG; +// +// ---------------------------- USB Config ----------------------------- +// +/// +/// Overcurrent pins, the values match the setting of PCH EDS, please refe= r to PCH EDS for more details +/// +#ifndef PCH_USB_OVERCURRENT_PIN_TYPE +#define PCH_USB_OVERCURRENT_PIN_TYPE +typedef enum { + PchUsbOverCurrentPin0 =3D 0, + PchUsbOverCurrentPin1, + PchUsbOverCurrentPin2, + PchUsbOverCurrentPin3, + PchUsbOverCurrentPin4, + PchUsbOverCurrentPin5, + PchUsbOverCurrentPin6, + PchUsbOverCurrentPin7, + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinMax +} PCH_USB_OVERCURRENT_PIN; +#endif + +/// +/// The location of the USB connectors. This information is use to decide= eye diagram tuning value for Usb 2.0 motherboard trace. +/// +enum PCH_USB_PORT_LOCATION{ + PchUsbPortLocationBackPanel =3D 0, + PchUsbPortLocationFrontPanel, + PchUsbPortLocationDock, + PchUsbPortLocationMiniPciE, + PchUsbPortLocationFlex, + PchUsbPortLocationInternalTopology, + PchUsbPortLocationSkip, + PchUsbPortLocationMax +}; + + +/** + This structure configures per USB2 AFE settings. + It allows to setup the port parameters. +**/ +typedef struct { +/** Per Port HS Preemphasis Bias (PERPORTPETXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Petxiset; +/** Per Port HS Transmitter Bias (PERPORTTXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Txiset; +/** + Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) + 00b - Emphasis OFF + 01b - De-emphasis ON + 10b - Pre-emphasis ON + 11b - Pre-emphasis & De-emphasis ON +**/ + UINT8 Predeemp; +/** + Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) + 1b - half-bit pre-emphasis + 0b - full-bit pre-emphasis +**/ + UINT8 Pehalfbit; +} PCH_USB20_AFE; + +/** + This structure configures per USB2 port physical settings. + It allows to setup the port location and port length, and configures the= port strength accordingly. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable= . + UINT32 RsvdBits0 : 31; ///< Reserved bits + /** + These members describe the specific over current pin number of USB 2.0= Port N. + It is SW's responsibility to ensure that a given port's bit map is set= only for + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same + OC pin (see: PCH_USB_OVERCURRENT_PIN). + **/ + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to= multiple 4. + PCH_USB20_AFE Afe; ///< USB2 AFE settings + UINT32 Rsvd1[1]; ///< Reserved bytes +} PCH_USB20_PORT_CONFIG; + +/** + This structure describes whether the USB3 Port N of PCH is enabled by pl= atform modules. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; ///< Reserved bits + /** + These members describe the specific over current pin number of USB 3.0= Port N. + It is SW's responsibility to ensure that a given port's bit map is set= only for + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same + OC pin (see: PCH_USB_OVERCURRENT_PIN). + **/ + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multipl= e 4 + + UINT32 HsioTxDeEmphEnable : 1; ///< Enable the write to USB 3= .0 TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable. + /** + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2dee= mph3p5) + HSIO_TX_DWORD5[21:16] + Default =3D 29h (approximately -3.5dB De-Emphasis) + **/ + UINT32 HsioTxDeEmph : 6; + + UINT32 HsioTxDownscaleAmpEnable : 1; ///< Enable the write to USB 3= .0 TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable. + /** + USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) + HSIO_TX_DWORD8[21:16] + Default =3D 00h + **/ + UINT32 HsioTxDownscaleAmp : 6; + + UINT32 RsvdBits1 : 18; ///< Reserved bits + UINT32 Rsvd1[1]; ///< Reserved bytes +} PCH_USB30_PORT_CONFIG; + +#define PCH_XHCI_MODE_OFF 0 +#define PCH_XHCI_MODE_ON 1 + +/** + These members describe some settings which are related to the SSIC ports. +**/ +typedef struct { + /** + 0: Disable; 1: Enable SSIC support. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits1 : 31; +} PCH_XHCI_SSIC_PORT; +/** + These members describe some settings which are related to the SSIC ports. +**/ +typedef struct { + PCH_XHCI_SSIC_PORT SsicPort[PCH_XHCI_MAX_SSIC_PORT_COUNT]; +} PCH_SSIC_CONFIG; + +/** + The PCH_XDCI_CONFIG block describes the configurations + of the xDCI Usb Device controller. +**/ +typedef struct { + /** + This member describes whether or not the xDCI controller should be ena= bled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PCH_XDCI_CONFIG; + + +/** + This member describes the expected configuration of the PCH USB controll= ers, + Platform modules may need to refer Setup options, schematic, BIOS specif= ication + to update this field. + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated = by referring + the schematic. +**/ +typedef struct { + /** + This feature intends to reduce the necessary initialization time for U= SB HC + and devices on root ports. It is assembled by PCHInit drivers in PEI a= nd DXE phase. + In PEI phase, the feature resets all USB HCs on PCH bus, including Int= el EHCI + and XHCI. After reset USB HC, continue the system initialization witho= ut waiting + for the USB XHC reset ready. After running to DXE phase, the feature r= esets + those USB devices installed on each USB HC root port in parallel, incl= uding + any non USB3 speed devices on XHCI root port if XHCI is enabled. + For USB3 protocol root port, USB3 speed devices will be advanced to + enable state if link training succeeds after XHC reset. + + UsbPrecondition =3D Enable , Force USB Init happen in PEI as part of 2= Sec Fast Boot bios optimization. + UsbPrecondition =3D Disable, USB Init happen in DXE just like traditio= nally where it happen. + Remark: With Precondition Enabled some USB2 devices which are not comp= liant with usb2 specification + are not being detected if installed in the system during S4/S5. + + + 0: Disable; 1: Enable. + **/ + UINT32 UsbPrecondition : 1; + /** + This policy will disable XHCI compliance mode on all ports. Complicanc= e Mode should be default enabled. + For the platform that support USB Type-C, it can disable Compliance Mo= de, and enable Compliance Mode when testing. + 0:Disable , 1: Enable + **/ + UINT32 DisableComplianceMode : 1; + // Following option is now exposed since there are no restricted registe= rs used. + UINT32 XhciOcMapEnabled : 1; = ///< 0: To disable OC mapping for USB XHCI ports 1: Set Xhci OC registers,= Set Xhci OCCDone bit, XHCI Access Control Bit. + UINT32 XhciWakeOnUsb : 1; = ///< 0: To disable Wake on USB connect/Disconnect 1: Enables Wake on USB c= onnect/disconnect event. + UINT32 XhciDisMSICapability : 1; + UINT32 RsvdBits0 : 27; ///< Re= served bits + + /** + These members describe whether the USB2 Port N of PCH is enabled by pl= atform modules. + Panel and Dock are used to describe the layout of USB port. Panel is o= nly available for Desktop PCH. + Dock is only available for Mobile LPT. + **/ + PCH_USB20_PORT_CONFIG PortUsb20[PCH_MAX_USB2_PORTS]; + /** + These members describe whether the USB3 Port N of PCH is enabled by pl= atform modules. + **/ + PCH_USB30_PORT_CONFIG PortUsb30[PCH_MAX_USB3_PORTS]; + /** + This member describes whether or not the xDCI controller should be ena= bled. + **/ + PCH_XDCI_CONFIG XdciConfig; + /** + These members describe some settings which are related to the SSIC por= ts. + **/ + PCH_SSIC_CONFIG SsicConfig; + + UINT32 Rsvd0[6]; ///< Reserved b= ytes +} PCH_USB_CONFIG; + +// +// --------------------------- Flash Protection Range Registers ----------= -------------------- +// +/** + The PCH provides a method for blocking writes and reads to specific rang= es + in the SPI flash when the Protected Ranges are enabled. + PROTECTED_RANGE is used to specify if flash protection are enabled, + the write protection enable bit and the read protection enable bit, + and to specify the upper limit and lower base for each register + Platform code is responsible to get the range base by PchGetSpiRegionAdd= resses routine, + and set the limit and base accordingly. +**/ +typedef struct { + UINT32 WriteProtectionEnable : 1; ///< Write or = erase is blocked by hardware. 0: Disable; 1: Enable. + UINT32 ReadProtectionEnable : 1; ///< Read is b= locked by hardware. 0: Disable; 1: Enable. + UINT32 RsvdBits : 30; ///< Reserved + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are a= ssumed to be FFFh for limit comparison + **/ + UINT16 ProtectedRangeLimit; + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are a= ssumed to be 0 + **/ + UINT16 ProtectedRangeBase; +} PROTECTED_RANGE; + +typedef struct { + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; +} PCH_FLASH_PROTECTION_CONFIG; + +// +// --------------------- WatchDog (WDT) Configuration --------------------= ---------- +// +/** + This policy clears status bits and disable watchdog, then lock the + WDT registers. + while WDT is designed to be disabled and locked by Policy, + bios should not enable WDT by WDT PPI. In such case, bios shows the + warning message but not disable and lock WDT register to make sure + WDT event trigger correctly. +**/ +typedef struct { + UINT32 DisableAndLock : 1; ///< (Test) Set 1 to clear = WDT status, then disable and lock WDT registers. 0: Disable; 1: Enab= le. + UINT32 RsvdBits : 31; +} PCH_WDT_CONFIG; + +// +// --------------------- P2SB Configuration ------------------------------ +// +/** + This structure contains the policies which are related to P2SB device. +**/ +typedef struct { + /** + (Test) + This unlock the SBI lock bit to allow SBI after post time. 0: Disab= le; 1: Enable. + NOTE: Do not set this policy "SbiUnlock" unless necessary. + **/ + UINT32 SbiUnlock : 1; + /** + (Test) + The PSF registers will be locked before 3rd party code execution. + This policy unlock the PSF space. 0: Disable; 1: Enable. + NOTE: Do not set this policy "PsfUnlock" unless necessary. + **/ + UINT32 PsfUnlock : 1; + /** + Debug + The P2SB PCIe device will be hidden at end of PEI stage. + This policy reveal P2SB PCIe device at end of EXE. 0: Disable (hidd= en); 1: Enable (visible). + NOTE: Do not set this policy "P2SbReveal" unless necessary. + **/ + UINT32 P2SbReveal : 1; + UINT32 RsvdBits : 29; +} PCH_P2SB_CONFIG; + +// +// --------------------- DCI Configuration ------------------------------ +// +/** + This structure contains the policies which are related to Direct Connect= ion Interface (DCI). +**/ +typedef struct { + /** + (Test) DCI enable (HDCIEN bit) + when Enabled, allow DCI to be enabled. When Disabled, the host control= is not enabling DCI feature. + BIOS provides policy to enable or disable DCI, and user would be able = to use BIOS option to change this policy. + The user changing the setting from disable to enable, is taken as a co= nsent from the user to enable this DCI feature. + 0:Disabled; 1:Enabled + **/ + UINT32 DciEn : 1; + /** + (Test) When set to Auto detect mode, it detects DCI being conne= cted during BIOS post time and enable DCI. + Else it disable DCI. This policy only apply when DciEn is disabled. + NOTE: this policy should not be visible to end customer. + 0: Disable AUTO mode, 1: Enable AUTO mode + **/ + UINT32 DciAutoDetect : 1; + UINT32 RsvdBits : 30; ///< Reserved bits +} PCH_DCI_CONFIG; + +// +// --------------------- LPC Configuration ------------------------------ +// +/** + This structure contains the policies which are related to LPC. +**/ +typedef struct { + /** + Enhance the port 8xh decoding. + Original LPC only decodes one byte of port 80h, with this enhancement = LPC can decode word or dword of port 80h-83h. + @note: this will occupy one LPC generic IO range register. While this = is enabled, read from port 80h always return 0x00. + 0: Disable, 1: Enable + **/ + UINT32 EnhancePort8xhDecoding : 1; + UINT32 RsvdBits : 31; ///< Reserved bits +} PCH_LPC_CONFIG; + +// +// --------------------- SPI Configuration ------------------------------ +// +/** + This structure contains the policies which are related to SPI. +**/ +typedef struct { + /** + Force to show SPI controller. + 0: FALSE, 1: TRUE + NOTE: For Windows OS, it MUST BE false. It's optional for other OSs. + **/ + UINT32 ShowSpiController : 1; + UINT32 RsvdBits : 31; ///< Reserved bits +} PCH_SPI_CONFIG; + +// +// --------------------------------------------------------------------- +// + +/** + PCH Policy revision number + Any backwards compatible changes to this structure will result in an upd= ate in the revision number +**/ +#define PCH_POLICY_REVISION 15 + +/** + The PCH Policy allows the platform code to publish a set of + configuration information that the PCH drivers will use to configure the= PCH hardware. + The Revision field is used to accommodate backward compatible changes to= the PPI/protocol. + The Revision should be initialized to PCH_POLICY_REVISION_X + by the PPI producer. + The BusNumber field is used for platform to assign Bus number with multi= ple instances. + + All reserved/unused fields must be initialized with zeros. +**/ +struct _PCH_POLICY { + /** + This member specifies the revision of the PCH policy PPI. This field i= s used to + indicate backwards compatible changes to the protocol. Platform code t= hat produces + this PPI must fill with the correct revision value for the PCH referen= ce code + to correctly interpret the content of the PPI fields. + + Revision 1: Original version + - Add DciAutoDetect policy in PCH_GENERAL_CONFIG. + - Add SbiUnlock policy in PCH_P2SB_CONFIG. + - Add the following policies in PCH_ISH_CONFIG: + - SpiGpioAssign + - Uart0GpioAssign + - Uart1GpioAssign + - I2c0GpioAssign + - I2c1GpioAssign + - I2c2GpioAssign + - Gp0GpioAssign + - Gp1GpioAssign + - Gp2GpioAssign + - Gp3GpioAssign + - Gp4GpioAssign + - Gp5GpioAssign + - Gp6GpioAssign + - Gp7GpioAssign + - Add ClkReqSupported and ClkReqDetect in PCH_PCIE_ROOT_PO= RT_CONFIG. + - Add the following in PCH_SKYCAM_CIO2_CONFIG + - SkyCamPortATermOvrEnable + - SkyCamPortBTermOvrEnable + - SkyCamPortCTermOvrEnable + - SkyCamPortDTermOvrEnable + - Add UartHwFlowCtrl in PCH_SERIAL_IO + - Move DciEn and DciAutoDetect to PCH_DCI_CONFIG + + + + Revision 2: Updated version + - Add Enable policy in PCH_SSIC_CONFIG + - Deprecated Target Debugger option of EnableMode in PCH_T= RACE_HUB_CONFIG + - Deprecated the following policies in PCH_TRACE_HUB_CONFIG + - MemReg0WrapEnable + - MemReg1WrapEnable + - TraceDestination + - PtiMode + - PtiSpeed + - PtiTraining + - Deprecated the Usb3PinsTermination and ManualModeUsb30Pe= rPinEnable in PCH_XHCI_CONFIG + - Redefine the Enable policy in PCH_HPET_CONFIG + - Add EnhancePort8xhDecoding in PCH_LPC_CONFIG + - Add PsfUnlock in PCH_P2SB_CONFIG + - Add AllowNoLtrIccPllShutdown in PCH_PCIE_CONFIG + - Add PdtUnlock in PCH_ISH_CONFIG + - Remove PwrmBase from policy since the base address is pr= edefined. + - Add DspEndpointDmic, DspEndpointBluetooth, DspEndpointI2= s in PCH_HDAUDIO_CONFIG + - Add Gen3EqPh3Method abd EqPh3LaneParam in PCH_PCIE_ROOT_= PORT_CONFIG/PCH_PCIE_CONFIG + - Remove SlotImplemented and PmeInterrupt from PCH_PCIE_RO= OT_PORT_CONFIG + + + + Revision 3: Updated version + - Add PwrBtnOverridePeriod policy in PCH_PM_CONFIG + - Add PCH_USB20_AFE in PCH_USB20_PORT_CONFIG + - Add ClkReqSupported in PCH_LAN_CONFIG + + + + Revision 4: Updated version + - Add DeviceResetPad and DeviceResetPadActiveHigh in PCH_P= CIE_ROOT_PORT_CONFIG + + + Revision 5: Updated version + - Deprecated ScsSdioMode in PCH_SCS_CONFIG + - Deprecated PchScsSdioMode (PCH_SCS_DEV_SD_MODE enum) for= ScsSdSwitch in PCH_SCS_CONFIG + - Add HSIO RX and TX EQ policy for PCIe and SATA + - Add ComplianceTestMode in PCH_PCIE_CONFIG + + Revision 6: Updated version + - Add DisableEnergyReport in PCH_PM_CONFIG + + + Revision 7: Updated version + - Deprecated Enabled as Acpi device option of DeviceEnable= in PCH_SKYCAM_CIO2_CONFIG + - Add PCH_SKYCAM_CIO2_FLS_CONFIG with the following elemen= ts: + - PortACtleEnable + - PortBCtleEnable + - PortCCtleEnable + - PortDCtleEnable + - PortACtleCapValue + - PortBCtleCapValue + - PortCCtleCapValue + - PortDCtleCapValue + - PortACtleResValue + - PortBCtleResValue + - PortCCtleResValue + - PortDCtleResValue + - PortATrimEnable + - PortBTrimEnable + - PortCTrimEnable + - PortDTrimEnable + - PortADataTrimValue + - PortBDataTrimValue + - PortCDataTrimValue + - PortDDataTrimValue + - PortAClkTrimValue + - PortBClkTrimValue + - PortCClkTrimValue + - PortDClkTrimValue + - Rename and reorder the policies for better understanding. + - HsioTxOutDownscaleAmpAd3GbsEnable to HsioTxGen1Downsca= leAmpEnable + - HsioTxOutDownscaleAmpAd6GbsEnable to HsioTxGen2Downsca= leAmpEnable + - HsioTxOutDownscaleAmpAd3Gbs to HsioTxGen2DownscaleAmp + - HsioTxOutDownscaleAmpAd6Gbs to HsioTxGen2DownscaleAmp + - Update SerialIo DevMode default to PCI mode. + + + Revision 8: Updated version + - Deprecate GP27WakeFromDeepSx and add LanWakeFromDeepSx t= o align EDS naming + - Add ShowSpiController policy and PCH_SPI_CONFIG. + - Add DspUaaCompliance in PCH_HDAUDIO_CONFIG + - Add PchPcieEqHardware support in PCH_PCIE_EQ_METHOD + + + Revision 9: Updated version + - Add DebugUartNumber and EnableDebugUartAfterPost in PCH_= SERIAL_IO_CONFIG + - Add DetectTimeoutMs in PCH_PCIE_CONFIG + - Add PciePllSsc in PCH_PM_CONFIG + + + Revision 10: Updated version + - Add HsioTxDeEmph in PCH_USB30_PORT_CONFIG + - Add HsioTxDownscaleAmp in PCH_USB30_PORT_CONFIG + - Add HsioTxDeEmphEnable in PCH_USB30_PORT_CONFIG + - Add HsioTxDownscaleAmpEnable in PCH_USB30_PORT_CONFIG + + - Deprecated PCH_SATA_PORT_CONFIG.HsioRxEqBoostMagAdEnable + - Deprecated PCH_SATA_PORT_CONFIG.HsioRxEqBoostMagAd + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen1DownscaleAmpEn= able + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen1DownscaleAmp + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen2DownscaleAmpEn= able + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen2DownscaleAmp + + - Add PCH_HSIO_SATA_CONFIG HsioSataConfig in PCH_POLICY + - Add HsioRxGen1EqBoostMagEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen1EqBoostMag in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen2EqBoostMagEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen2EqBoostMag in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen1DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen1DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen2DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen2DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DownscaleAmpEnable in PCH_HSIO_SATA_PORT_L= ANE + - Add HsioTxGen3DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + + - Add PCH_HSIO_PCIE_CONFIG HsioPcieConfig in PCH_POLICY + - Deprecated PCH_PCIE_ROOT_PORT_CONFIG.HsioRxSetCtleEnable + - Deprecated PCH_PCIE_ROOT_PORT_CONFIG.HsioRxSetCtle + - Add HsioRxSetCtleEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioRxSetCtle in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_C= ONFIG + - Add HsioTxGen1DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_C= ONFIG + - Add HsioTxGen2DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen3DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_C= ONFIG + - Add HsioTxGen3DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DeEmphEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DeEmph in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph3p5Enable in PCH_HSIO_PCIE_LANE_CONF= IG + - Add HsioTxGen2DeEmph3p5 in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph6p0Enable in PCH_HSIO_PCIE_LANE_CONF= IG + - Add HsioTxGen2DeEmph6p0 in PCH_HSIO_PCIE_LANE_CONFIG + + - Add DisableDsxAcPresentPulldown in PCH_PM_CONFIG + - Add DynamicPowerGating in PCH_SMBUS_CONFIG + - Add ZpOdd in PCH_SATA_PORT_CONFIG + - Add Uptp and Dptp in PCH_PCIE_ROOT_PORT_CONFIG + - Add PCH_PCIE_CONFIG2 PcieConfig2 in PCH_POLICY + + + Revision 11: Updated version + - Add DisableComplianceMode in PCH_USB_CONFIG + + + Revision 12: Updated version + - Add PmcReadDisable in PCH_PM_CONFIG + - Add CapsuleResetType in PCH_PM_CONFIG + - Add RpFunctionSwap in PCH_PCIE_CONFIG + + + Revision 13: Update version + - Add DisableNativePowerButton in PCH_PM_CONFIG + - Add MaxPayload in PCH_PCIE_ROOT_PORT_CONFIG + - Add IDispCodecDisconnect in PCH_HDAUDIO_CONFIG +#ifdef PCH_SERVER_BIOS_FLAG + Revision 13a: Server updates + - Add HsioIcfgAdjLimitLoEnable + - Add HsioIcfgAdjLimitLo + - Add HsioSampOffstEvenErrSpEnable + - Add HsioSampOffstEvenErrSp + - Add HsioRemainingSamplerOffEnable + - Add HsioRemainingSamplerOff + - Add HsioVgaGainCal + in PCH_HSIO_PCIE_LANE_CONFIG +#endif //PCH_SERVER_BIOS_FLAG + + **/ + UINT8 Revision; + + UINT8 Port80Route; ///< Control where the P= ort 80h cycles are sent, 0: LPC; 1: PCI. + UINT16 AcpiBase; ///< Power management I/= O base address. Default is 0x1800. + UINT32 Rsvd; + /// + /// PCH General configuration + /// + PCH_GENERAL_CONFIG PchConfig; + /// + /// This member describes PCI Express controller's related configuration. + /// + PCH_PCIE_CONFIG PcieConfig; + /** + SATA controller's related configuration. + SATA configuration that decides which Mode the SATA controller should = operate in + and whether PCH SATA TEST mode is enabled. + **/ + PCH_SATA_CONFIG SataConfig; + /// + /// This member describes USB controller's related configuration. + /// + PCH_USB_CONFIG UsbConfig; + /** + This member describes IOAPIC related configuration. + Determines IO APIC ID and IO APIC Range. + **/ + PCH_IOAPIC_CONFIG IoApicConfig; + /// + /// This member describes HPET related configuration. + /// + PCH_HPET_CONFIG HpetConfig; + /// + /// This member describes the Intel HD Audio (Azalia) related configurat= ion. + /// + PCH_HDAUDIO_CONFIG HdAudioConfig; + /// + /// LAN controller settings + /// + PCH_LAN_CONFIG LanConfig; + /// + /// This member describes SMBus related configuration. + /// + PCH_SMBUS_CONFIG SmbusConfig; + /// + /// This member describes LockDown related configuration. + /// + PCH_LOCK_DOWN_CONFIG LockDownConfig; + /// + /// This member describes Thermal related configuration. + /// + PCH_THERMAL_CONFIG ThermalConfig; + /// + /// This member describes miscellaneous platform power management config= urations. + /// + PCH_PM_CONFIG PmConfig; + /// + /// This member describes DMI related configuration. + /// + PCH_DMI_CONFIG DmiConfig; + /// + /// This member describes the expected configuration of the PCH for Seri= al IRQ. + /// + PCH_LPC_SIRQ_CONFIG SerialIrqConfig; + /// + /// This member describes interrupt settings for PCH. + /// + PCH_INTERRUPT_CONFIG PchInterruptConfig; + /// + /// This member describes TraceHub settings for PCH. + /// + PCH_TRACE_HUB_CONFIG PchTraceHubConfig; + /// + /// This member describes the enabling of emulation for port 61h + /// + PCH_PORT61H_SMM_CONFIG Port61hSmmConfig; + /// + /// This member describes the Flash Protection related configuration + /// + PCH_FLASH_PROTECTION_CONFIG FlashProtectConfig; + /// + /// This member describes the sSata related configuration + /// + PCH_SATA_CONFIG sSataConfig; + /// + /// This member contains WDT enable configuration. + /// + PCH_WDT_CONFIG WdtConfig; + /// + /// This member contains P2SB configuration. + /// + PCH_P2SB_CONFIG P2sbConfig; + /// + /// This member contains DCI configuration. + /// + PCH_DCI_CONFIG DciConfig; + + /// + /// Platform specific common policies that used by several silicon compo= nents. + /// + /// + /// Temp Bus Number range available to be assigned to each root port and= its downstream + /// devices for initialization of these devices before PCI Bus enumerati= on. + /// + UINT8 TempPciBusMin; + UINT8 TempPciBusMax; + /// + /// Temporary Memory Base Address for PCI devices to be used to initiali= ze MMIO registers. + /// Minimum size is 2MB bytes + /// + UINT32 TempMemBaseAddr; + /// + /// This member contains LPC configuration. + /// + PCH_LPC_CONFIG LpcConfig; + /// + /// This member describes SkyCam CIO2 FLS registers configuration. + /// + PCH_SKYCAM_CIO2_FLS_CONFIG PchCio2FlsConfig; + /// + /// This member contains SPI configuration. + /// + PCH_SPI_CONFIG SpiConfig; + /// + /// This member describes HSIO settings for SATA controller + /// + PCH_HSIO_SATA_CONFIG HsioSataConfig; + /// + /// This member describes HSIO settings for second SATA controller + /// + PCH_HSIO_SATA_CONFIG HsiosSataConfig; + /// + /// This member describes HSIO settings for PCIe controller + /// + PCH_HSIO_PCIE_CONFIG HsioPcieConfig; + /// + /// This member describes HSIO settings for FIA WM20 PCIe + /// + PCH_HSIO_PCIE_WM20_CONFIG HsioPcieConfigFIAWM20; + /// + /// This is the extension of PCIE CONFIG + /// + PCH_PCIE_CONFIG2 PcieConfig2; + + PCH_ADR_CONFIG AdrConfig; + +}; + +#pragma pack (pop) + +#endif // _PCH_POLICY_COMMON_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchReservedR= esources.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchReservedR= esources.h new file mode 100644 index 0000000000..62a3a39361 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PchReservedResource= s.h @@ -0,0 +1,81 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_PRESERVED_RESOURCES_H_ +#define _PCH_PRESERVED_RESOURCES_H_ + +/** +#ifdef SERVER_BIOS_FLAG + SKX map: +#endif //SERVER_BIOS_FLAG + PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF + + Detailed recommended static allocation + +-----------------------------------------------------------------------= --+ + | Size | Start | End | Usage = | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG = | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR = | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 = | + | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode = | + | 24 KB | 0xFE036000 | 0xFE03BFFF | Unused = | + | 4 KB | 0xFE03C000 | 0xFE03CFFF | Thermal Device in ACPI mode = | + | 524 KB | 0xFE03D000 | 0xFE0BFFFF | Unused = | + | 256 KB | 0xFE0C0000 | 0xFE0FFFFF | TraceHub FW BAR = | + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR = | + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub SW BAR = | + | 64 KB | 0xFE400000 | 0xFE40FFFF | CIO2 MMIO BAR in ACPI mode = | + | 2 MB - 64KB | 0xFE410000 | 0xFE5FFFFF | Unused = | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address = | + +-----------------------------------------------------------------------= --+ + +#ifdef SERVER_BIOS_FLAG + HSX map: + PCH preserved MMIO range, from 0xFC000000 to 0xFE7FFFFF + + Detailed recommended static allocation + +---------------------------------------------------------------------= ----+ + | Size | Start | End | Usage = | + | 256 KB | 0xFC0C0000 | 0xFC0FFFFF | TraceHub FW BAR = | + | 1 MB | 0xFC100000 | 0xFC1FFFFF | TraceHub MTB BAR = | + | 2 MB | 0xFC200000 | 0xFC3FFFFF | TraceHub SW BAR = | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG = | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR = | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 = | + | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode = | + | 24 KB | 0xFE036000 | 0xFE03BFFF | Unused = | + | 4 KB | 0xFE03C000 | 0xFE03CFFF | Thermal Device in ACPI mod= e | + | 524 KB | 0xFE03D000 | 0xFE0BFFFF | Unused = | + | 64 KB | 0xFE400000 | 0xFE40FFFF | CIO2 MMIO BAR in ACPI mode= | + | 2 MB - 64KB | 0xFE410000 | 0xFE5FFFFF | Unused = | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address = | + +---------------------------------------------------------------------= ----+ +#endif //SERVER_BIOS_FLAG +**/ +#define PCH_PRESERVED_BASE_ADDRESS 0xFD000000 ///< Pch preserved = MMIO base address +#define PCH_PRESERVED_MMIO_SIZE 0x01800000 ///< 24MB +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO bas= e address +#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO = base address +#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO = base address +#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB +#define PCH_THERMAL_BASE_ADDRESS 0xFE03C000 ///< Thermal Device= in ACPI mode +#define PCH_THERMAL_MMIO_SIZE 0x00001000 ///< 4KB + +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE0C0000 ///< TraceHub FW MM= IO base address +#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00040000 ///< 256KB +#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< TraceHub MTB M= MIO base address +#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB +#define PCH_TRACE_HUB_SW_BASE_ADDRESS 0xFE200000 ///< TraceHub SW MM= IO base address +#define PCH_TRACE_HUB_SW_MMIO_SIZE 0x00200000 ///< 2MB +#define PCH_CIO2_BASE_ADDRESS 0xFE400000 ///< CIO2 MMIO BAR = in ACPI mode +#define PCH_CIO2_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved temp= address for misc usage +#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB + +#endif // _PCH_PRESERVED_RESOURCES_H_ + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PcieRegs.h b= /Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PcieRegs.h new file mode 100644 index 0000000000..da8aebdd03 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/PcieRegs.h @@ -0,0 +1,279 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCIE_REGS_H_ +#define _PCIE_REGS_H_ + +#include + +// +// PCI type 0 Header +// +#define R_PCI_PI_OFFSET 0x09 +#define R_PCI_SCC_OFFSET 0x0A +#define R_PCI_BCC_OFFSET 0x0B + +// +// PCI type 1 Header +// +#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number Reg= ister +#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< Subordin= ate Bus Number +#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Secondar= y Bus Number +#define B_PCI_BRIDGE_BNUM_PBN 0x000000FF ///< Primary = Bus Number +#define B_PCI_BRIDGE_BNUM_SBBN_SCBN (B_PCI_BRIDGE_BNUM_SBBN = | B_PCI_BRIDGE_BNUM_SCBN) + +#define R_PCI_BRIDGE_IOBL 0x1C ///< I/O Base and L= imit Register + +#define R_PCI_BRIDGE_MBL 0x20 ///< Memory Base an= d Limit Register +#define B_PCI_BRIDGE_MBL_ML 0xFFF00000 ///< Memory L= imit +#define B_PCI_BRIDGE_MBL_MB 0x0000FFF0 ///< Memory B= ase + +#define R_PCI_BRIDGE_PMBL 0x24 ///< Prefetchable M= emory Base and Limit Register +#define B_PCI_BRIDGE_PMBL_PML 0xFFF00000 ///< Prefetch= able Memory Limit +#define B_PCI_BRIDGE_PMBL_I64L 0x000F0000 ///< 64-bit I= ndicator +#define B_PCI_BRIDGE_PMBL_PMB 0x0000FFF0 ///< Prefetch= able Memory Base +#define B_PCI_BRIDGE_PMBL_I64B 0x0000000F ///< 64-bit I= ndicator + +#define R_PCI_BRIDGE_PMBU32 0x28 ///< Prefetchable M= emory Base Upper 32-Bit Register +#define B_PCI_BRIDGE_PMBU32 0xFFFFFFFF + +#define R_PCI_BRIDGE_PMLU32 0x2C ///< Prefetchable M= emory Limit Upper 32-Bit Register +#define B_PCI_BRIDGE_PMLU32 0xFFFFFFFF + +// +// PCIE capabilities register +// +#define R_PCIE_CAP_ID_OFFSET 0x00 ///< Capability ID +#define R_PCIE_CAP_NEXT_PRT_OFFSET 0x01 ///< Next Capabilit= y Capability ID Pointer + +// +// PCI Express Capability List Register (CAPID:10h) +// +#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express Ca= pabilities Register (Offset 02h) +#define S_PCIE_XCAP 2 +#define B_PCIE_XCAP_SI BIT8 ///< Slot Implement= ed +#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BI= T4) ///< Device/Port Type +#define N_PCIE_XCAP_DT 4 + +#define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capabil= ities Register (Offset 04h) +#define S_PCIE_DCAP 4 +#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) /= //< Endpoint L1 Acceptable Latency +#define N_PCIE_DCAP_E1AL 9 +#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///= < Endpoint L0s Acceptable Latency +#define N_PCIE_DCAP_E0AL 6 +#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///= < Max_Payload_Size Supported + +#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control= Register (Offset 08h) +#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///= < Max_Payload_Size +#define N_PCIE_DCTL_MPS 5 +#define B_PCIE_DCTL_URE BIT3 ///< Unsupported Re= quest Reporting Enable +#define B_PCIE_DCTL_FEE BIT2 ///< Fatal Error Re= porting Enable +#define B_PCIE_DCTL_NFE BIT1 ///< Non-Fatal Erro= r Reporting Enable +#define B_PCIE_DCTL_CEE BIT0 ///< Correctable Er= ror Reporting Enable + +#define R_PCIE_DSTS_OFFSET 0x0A ///< Device Status = Register (Offset 0Ah) +#define B_PCIE_DSTS_TDP BIT5 ///< Transactions P= ending +#define B_PCIE_DSTS_APD BIT4 ///< AUX Power Dete= cted +#define B_PCIE_DSTS_URD BIT3 ///< Unsupported Re= quest Detected +#define B_PCIE_DSTS_FED BIT2 ///< Fatal Error De= tected +#define B_PCIE_DSTS_NFED BIT1 ///< Non-Fatal Erro= r Detected +#define B_PCIE_DSTS_CED BIT0 ///< Correctable Er= ror Detected + +#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilit= ies Register (Offset 0Ch) +#define B_PCIE_LCAP_ASPMOC BIT22 ///< ASPM Optional= ity Compliance +#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power M= anagement +#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) = ///< L1 Exit Latency +#define N_PCIE_LCAP_EL1 15 +#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) = ///< L0s Exit Latency +#define N_PCIE_LCAP_EL0 12 +#define B_PCIE_LCAP_APMS (BIT11 | BIT10) ///< Act= ive State Power Management (ASPM) Support +#define B_PCIE_LCAP_APMS_L0S BIT10 +#define B_PCIE_LCAP_APMS_L1 BIT11 +#define N_PCIE_LCAP_APMS 10 +#define B_PCIE_LCAP_MLW 0x000003F0 ///< Maximum = Link Width +#define N_PCIE_LCAP_MLW 4 +#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BI= T0) ///< Max Link Speed +#define V_PCIE_LCAP_MLS_GEN3 3 + +#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control R= egister (Offset 10h) +#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock P= ower Management +#define B_PCIE_LCTL_ES BIT7 ///< Extended Synch +#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock C= onfiguration +#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link +#define B_PCIE_LCTL_LD BIT4 ///< Link Disable +#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Activ= e State Power Management (ASPM) Control +#define V_PCIE_LCTL_ASPM_L0S 1 +#define V_PCIE_LCTL_ASPM_L1 2 +#define V_PCIE_LCTL_ASPM_L0S_L1 3 + +#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status Re= gister (Offset 12h) +#define B_PCIE_LSTS_LA BIT13 ///< Data Link Lay= er Link Active +#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock Co= nfiguration +#define B_PCIE_LSTS_LT BIT11 ///< Link Training +#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated L= ink Width +#define N_PCIE_LSTS_NLW 4 +#define V_PCIE_LSTS_NLW_1 0x0010 +#define V_PCIE_LSTS_NLW_2 0x0020 +#define V_PCIE_LSTS_NLW_4 0x0040 +#define B_PCIE_LSTS_CLS 0x000F ///< Current Link= Speed +#define V_PCIE_LSTS_CLS_GEN1 1 +#define V_PCIE_LSTS_CLS_GEN2 2 +#define V_PCIE_LSTS_CLS_GEN3 3 + +#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilit= ies Register (Offset 14h) +#define S_PCIE_SLCAP 4 +#define B_PCIE_SLCAP_PSN 0xFFF80000 ///< Physical= Slot Number +#define B_PCIE_SLCAP_SLS 0x00018000 ///< Slot Pow= er Limit Scale +#define B_PCIE_SLCAP_SLV 0x00007F80 ///< Slot Pow= er Limit Value +#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capab= le +#define B_PCIE_SLCAP_HPS BIT5 ///< Hot-Plug Surpr= ise + +#define R_PCIE_SLCTL_OFFSET 0x18 ///< Slot Control R= egister (Offset 18h) +#define S_PCIE_SLCTL 2 +#define B_PCIE_SLCTL_HPE BIT5 ///< Hot Plug Inter= rupt Enable +#define B_PCIE_SLCTL_PDE BIT3 ///< Presence Detec= t Changed Enable + +#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status Re= gister (Offset 1Ah) +#define S_PCIE_SLSTS 2 +#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detec= t State +#define B_PCIE_SLSTS_PDC BIT3 ///< Presence Detec= t Changed + +#define R_PCIE_RCTL_OFFSET 0x1C ///< Root Control R= egister (Offset 1Ch) +#define S_PCIE_RCTL 2 +#define B_PCIE_RCTL_PIE BIT3 ///< PME Interrupt = Enable +#define B_PCIE_RCTL_SFE BIT2 ///< System Error o= n Fatal Error Enable +#define B_PCIE_RCTL_SNE BIT1 ///< System Error o= n Non-Fatal Error Enable +#define B_PCIE_RCTL_SCE BIT0 ///< System Error o= n Correctable Error Enable + +#define R_PCIE_RSTS_OFFSET 0x20 ///< Root Status Re= gister (Offset 20h) +#define S_PCIE_RSTS 4 + +#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capabil= ities 2 Register (Offset 24h) +#define B_PCIE_DCAP2_OBFFS (BIT19 | BIT18) ///< OBF= F Supported +#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism= Supported + +#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control= 2 Register (Offset 28h) +#define B_PCIE_DCTL2_OBFFEN (BIT14 | BIT13) ///< OBF= F Enable +#define N_PCIE_DCTL2_OBFFEN 13 +#define V_PCIE_DCTL2_OBFFEN_DIS 0 ///< Disabled +#define V_PCIE_DCTL2_OBFFEN_WAKE 3 ///< Enabled using WAK= E# signaling +#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism= Enable +#define B_PCIE_DCTL2_CTD BIT4 ///< Completion Tim= eout Disable +#define B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BI= T0) ///< Completion Timeout Value +#define V_PCIE_DCTL2_CTV_DEFAULT 0x0 +#define V_PCIE_DCTL2_CTV_40MS_50MS 0x5 +#define V_PCIE_DCTL2_CTV_160MS_170MS 0x6 +#define V_PCIE_DCTL2_CTV_400MS_500MS 0x9 +#define V_PCIE_DCTL2_CTV_1P6S_1P7S 0xA + +#define R_PCIE_LCTL2_OFFSET 0x30 ///< Link Control 2= Register (Offset 30h) +#define B_PCIE_LCTL2_SD BIT6 ///< Selectable de-= emphasis (0 =3D -6dB, 1 =3D -3.5dB) +#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BI= T0) ///< Target Link Speed +#define V_PCIE_LCTL2_TLS_GEN1 1 +#define V_PCIE_LCTL2_TLS_GEN2 2 +#define V_PCIE_LCTL2_TLS_GEN3 3 + +#define R_PCIE_LSTS2_OFFSET 0x32 ///< Link Status 2 = Register (Offset 32h) +#define B_PCIE_LSTS2_LER BIT5 ///< Link Equalizat= ion Request +#define B_PCIE_LSTS2_EQP3S BIT4 ///< Equalization P= hase 3 Successful +#define B_PCIE_LSTS2_EQP2S BIT3 ///< Equalization P= hase 2 Successful +#define B_PCIE_LSTS2_EQP1S BIT2 ///< Equalization P= hase 1 Successful +#define B_PCIE_LSTS2_EC BIT1 ///< Equalization C= omplete +#define B_PCIE_LSTS2_CDL BIT0 ///< Current De-emp= hasis Level + +// +// PCI Power Management Capability (CAPID:01h) +// +#define R_PCIE_PMC_OFFSET 0x02 ///< Power Manageme= nt Capabilities Register +#define S_PCIE_PMC 2 +#define B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 |= BIT12 | BIT11) ///< PME Support +#define B_PCIE_PMC_PMEC BIT3 ///< PME Clock + +#define R_PCIE_PMCS_OFFST 0x04 ///< Power Manageme= nt Status/Control Register +#define S_PCIE_PMCS 4 +#define B_PCIE_PMCS_BPCE BIT23 ///< Bus Power/Clo= ck Control Enable +#define B_PCIE_PMCS_B23S BIT22 ///< B2/B3 Support +#define B_PCIE_PMCS_PMES BIT15 ///< PME_Status +#define B_PCIE_PMCS_PMEE BIT8 ///< PME Enable +#define B_PCIE_PMCS_NSR BIT3 ///< No Soft Reset +#define B_PCIE_PMCS_PS (BIT1 | BIT0) ///< Power= State +#define V_PCIE_PMCS_PS_D0 0 +#define V_PCIE_PMCS_PS_D3H 3 + +// +// PCIE Extension Capability Register +// +#define B_PCIE_EXCAP_NCO 0xFFF00000 ///< Next Cap= ability Offset +#define N_PCIE_EXCAP_NCO 20 +#define V_PCIE_EXCAP_NCO_LISTEND 0 +#define B_PCIE_EXCAP_CV 0x000F0000 ///< Capabili= ty Version +#define N_PCIE_EXCAP_CV 16 +#define B_PCIE_EXCAP_CID 0x0000FFFF ///< Capabili= ty ID + +// +// Advanced Error Reporting Capability (CAPID:0001h) +// +#define V_PCIE_EX_AEC_CID 0x0001 ///< Capability ID +#define R_PCIE_EX_UEM_OFFSET 0x08 ///< Uncorrectable = Error Mask Register +#define B_PCIE_EX_UEM_CT BIT14 ///< Completion Ti= meout Mask +#define B_PCIE_EX_UEM_UC BIT16 ///< Unexpected Co= mpletion + +// +// ACS Extended Capability (CAPID:000Dh) +// +#define V_PCIE_EX_ACS_CID 0x000D ///< Capability ID +#define R_PCIE_EX_ACSCAPR_OFFSET 0x04 ///< ACS Capability= Register +//#define R_PCIE_EX_ACSCTLR_OFFSET 0x08 ///< ACS Control = Register (NOTE: register size in PCIE spce is not match the PCH register si= ze) + +// +// Secondary PCI Express Extended Capability Header (CAPID:0019h) +// +#define V_PCIE_EX_SPE_CID 0x0019 ///< Capability ID +#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3= Register +#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform Equali= zation +#define R_PCIE_EX_LES_OFFSET 0x08 ///< Lane Error Sta= tus +#define R_PCIE_EX_L01EC_OFFSET 0x0C ///< Lane 0 and Lan= 1 Equalization Control Register (Offset 0Ch) +#define B_PCIE_EX_L01EC_UPL1TP 0x0F000000 ///< Upstream= Port Lane 1 Transmitter Preset +#define N_PCIE_EX_L01EC_UPL1TP 24 +#define B_PCIE_EX_L01EC_DPL1TP 0x000F0000 ///< Downstre= am Port Lane 1 Transmitter Preset +#define N_PCIE_EX_L01EC_DPL1TP 16 +#define B_PCIE_EX_L01EC_UPL0TP 0x00000F00 ///< Upstream= Port Transmitter Preset +#define N_PCIE_EX_L01EC_UPL0TP 8 +#define B_PCIE_EX_L01EC_DPL0TP 0x0000000F ///< Downstre= am Port Transmitter Preset +#define N_PCIE_EX_L01EC_DPL0TP 0 + +#define R_PCIE_EX_L23EC_OFFSET 0x10 ///< Lane 2 and Lan= e 3 Equalization Control Register (Offset 10h) +#define B_PCIE_EX_L23EC_UPL3TP 0x0F000000 ///< Upstream= Port Lane 3 Transmitter Preset +#define N_PCIE_EX_L23EC_UPL3TP 24 +#define B_PCIE_EX_L23EC_DPL3TP 0x000F0000 ///< Downstre= am Port Lane 3 Transmitter Preset +#define N_PCIE_EX_L23EC_DPL3TP 16 +#define B_PCIE_EX_L23EC_UPL2TP 0x00000F00 ///< Upstream= Port Lane 2 Transmitter Preset +#define N_PCIE_EX_L23EC_UPL2TP 8 +#define B_PCIE_EX_L23EC_DPL2TP 0x0000000F ///< Downstre= am Port Lane 2 Transmitter Preset +#define N_PCIE_EX_L23EC_DPL2TP 0 + + +// +// L1 Sub-States Extended Capability Register (CAPID:001Eh) +// +#define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID +#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States = Capabilities +#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States = Control 1 +#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States = Control 2 +#define N_PCIE_EX_L1SCTL2_POWT 3 + +// +// Base Address Offset +// +#define R_BASE_ADDRESS_OFFSET_0 0x0010 ///< Base Address= Register 0 +#define R_BASE_ADDRESS_OFFSET_1 0x0014 ///< Base Address= Register 1 +#define R_BASE_ADDRESS_OFFSET_2 0x0018 ///< Base Address= Register 2 +#define R_BASE_ADDRESS_OFFSET_3 0x001C ///< Base Address= Register 3 +#define R_BASE_ADDRESS_OFFSET_4 0x0020 ///< Base Address= Register 4 +#define R_BASE_ADDRESS_OFFSET_5 0x0024 ///< Base Address= Register 5 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/PchPcieD= eviceTable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/PchPci= eDeviceTable.h new file mode 100644 index 0000000000..ec389c6534 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/PchPcieDeviceTa= ble.h @@ -0,0 +1,124 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PCH_PCIE_DEVICE_TABLE_H_ +#define PCH_PCIE_DEVICE_TABLE_H_ + + +// +// PCIe device table PPI GUID. +// +extern EFI_GUID gPchPcieDeviceTablePpiGuid; + +typedef enum { + PchPcieOverrideDisabled =3D 0, + PchPcieL1L2Override =3D 0x01, + PchPcieL1SubstatesOverride =3D 0x02, + PchPcieL1L2AndL1SubstatesOverride =3D 0x03, + PchPcieLtrOverride =3D 0x04 +} PCH_PCIE_OVERRIDE_CONFIG; + +/** + PCIe device table entry entry + + The PCIe device table is being used to override PCIe device ASPM setting= s. + To take effect table consisting of such entries must be instelled as PPI + on gPchPcieDeviceTablePpiGuid. + Last entry VendorId must be 0. +**/ +typedef struct { + UINT16 VendorId; ///< The vendor Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Vendor ID + UINT16 DeviceId; ///< The Device Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Device ID + UINT8 RevId; ///< The Rev Id of Pci Express card= ASPM setting override, 0xFF means all steppings + UINT8 BaseClassCode; ///< The Base Class Code of Pci Exp= ress card ASPM setting override, 0xFF means all base class + UINT8 SubClassCode; ///< The Sub Class Code of Pci Expr= ess card ASPM setting override, 0xFF means all sub class + UINT8 EndPointAspm; ///< Override device ASPM (see: PCH= _PCIE_ASPM_CONTROL) + ///< Bit 1 must be set in OverrideC= onfig for this field to take effect + UINT16 OverrideConfig; ///< The override config bitmap (se= e: PCH_PCIE_OVERRIDE_CONFIG). + /** + The L1Substates Capability Offset Override. (applicable if bit 2 is se= t in OverrideConfig) + This field can be zero if only the L1 Substate value is going to be ov= erride. + **/ + UINT16 L1SubstatesCapOffset; + /** + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideCo= nfig) + Set to zero then the L1 Substate Capability [3:0] is ignored, and only= L1s values are override. + Only bit [3:0] are applicable. Other bits are ignored. + **/ + UINT8 L1SubstatesCapMask; + /** + L1 Substate Port Common Mode Restore Time Override. (applicable if bit= 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sCommonModeRestoreTime; + /** + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnScale; + /** + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnValue; + + /** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be mul= tiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 SnoopLatency; + /** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be= multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 NonSnoopLatency; + + UINT32 Reserved; +} PCH_PCIE_DEVICE_OVERRIDE; + +#endif // PCH_PCIE_DEVICE_TABLE_H_ + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/PchPolic= y.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/PchPolicy.h new file mode 100644 index 0000000000..553537b61a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/PchPolicy.h @@ -0,0 +1,19 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_POLICY_PPI_H_ +#define _PCH_POLICY_PPI_H_ + +#include +#include + +extern EFI_GUID gPchPlatformPolicyPpiGuid; + + +typedef struct _PCH_POLICY PCH_POLICY_PPI; + +#endif // PCH_POLICY_PPI_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/PchReset= .h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/PchReset.h new file mode 100644 index 0000000000..965c9ac1d7 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/PchReset.h @@ -0,0 +1,93 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_RESET_PPI_H_ +#define _PCH_RESET_PPI_H_ + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchResetPpiGuid; +extern EFI_GUID gPchResetCallbackPpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_RESET_PPI PCH_RESET_PPI; +typedef struct _PCH_RESET_CALLBACK_PPI PCH_RESET_CALLBACK_PPI; + +// +// Related Definitions +// +// +// PCH Reset Types +// +typedef enum { + ColdReset, + WarmReset, + ShutdownReset, + PowerCycleReset, + GlobalReset, + GlobalResetWithEc, + PchResetTypeMax +} PCH_RESET_TYPE; + +// +// Member functions +// +/** + Execute Pch Reset from the host controller. + + @param[in] This Pointer to the PCH_RESET_PPI instance. + @param[in] PchResetType Pch Reset Types which includes ColdReset= , WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalRese= tWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_PPI_API) ( + IN PCH_RESET_PPI *This, + IN PCH_RESET_TYPE PchResetType + ); + +/** + Execute call back function for Pch Reset. + + @param[in] PchResetType Pch Reset Types which includes PowerCycl= e, Globalreset. + + @retval EFI_SUCCESS The callback function has been done succ= essfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback ppi. O= r, none of + callback ppi is installed. + @retval Others Do not do any reset from PCH +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_CALLBACK) ( + IN PCH_RESET_TYPE PchResetType + ); + +/** + Interface structure to execute Pch Reset from the host controller. +**/ +struct _PCH_RESET_PPI { + PCH_RESET_PPI_API Reset; +}; + +/** + This ppi is used to execute PCH Reset from the host controller. + The PCH Reset protocol and PCH Reset PPI implement the Intel (R) PCH Res= et Interface + for DXE and PEI environments, respectively. If other drivers need to run= their + callback function right before issuing the reset, they can install PCH R= eset + Callback Protocol/PPI before PCH Reset DXE/PEI driver to achieve that. +**/ +struct _PCH_RESET_CALLBACK_PPI { + PCH_RESET_CALLBACK ResetCallback; +}; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/Spi.h b/= Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/Spi.h new file mode 100644 index 0000000000..b81df73b4b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Ppi/Spi.h @@ -0,0 +1,25 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_SPI_PPI_H_ +#define _PCH_SPI_PPI_H_ + +#include + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPeiSpiPpiGuid; + +/** + Reuse the PCH_SPI_PROTOCOL definitions + This is possible becaues the PPI implementation does not rely on a PeiSe= rvice pointer, + as it uses EDKII Glue Lib to do IO accesses +**/ +typedef EFI_SPI_PROTOCOL PCH_SPI_PPI; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Protocol/Pch= Reset.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Protocol/PchRes= et.h new file mode 100644 index 0000000000..5e875b6bf0 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Protocol/PchReset.h @@ -0,0 +1,112 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_RESET_H_ +#define _PCH_RESET_H_ + +#include + +#define EFI_CAPSULE_VARIABLE_NAME L"CapsuleUpdateData" +extern EFI_GUID gEfiCapsuleVendorGuid; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchResetProtocolGuid; +extern EFI_GUID gPchResetCallbackProtocolGuid; +extern EFI_GUID gPchPowerCycleResetGuid; +extern EFI_GUID gPchGlobalResetGuid; +extern EFI_GUID gPchGlobalResetWithEcGuid; +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL; + +typedef PCH_RESET_CALLBACK_PPI PCH_RESET_CALLBACK_PROTOCOL; + +// +// Related Definitions +// +// +// PCH Platform Specific ResetData +// +#define PCH_POWER_CYCLE_RESET_GUID \ + { \ + 0x8d8ee25b, 0x66dd, 0x4ed8, { 0x8a, 0xbd, 0x14, 0x16, 0xe8, 0x8e, 0x1d= , 0x24 } \ + } + +#define PCH_GLOBAL_RESET_GUID \ + { \ + 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18, 0x1f, 0x7e, 0x3a, 0x3e= , 0x40 } \ + } + +#define PCH_GLOBAL_RESET_WITH_EC_GUID \ + { \ + 0xd22e6b72, 0x53cd, 0x4158, { 0x83, 0x3f, 0x6f, 0xd8, 0x7e, 0xbe, 0xa9= , 0x93 } \ + } + +#define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET" +#define PCH_RESET_DATA_STRING_MAX_LENGTH sizeof (PCH_PLATFORM_SPECIFIC_R= ESET_STRING) + +typedef struct _RESET_DATA { + CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH]; + EFI_GUID Guid; +} PCH_RESET_DATA; + + +// +// Member functions +// +/** + Execute Pch Reset from the host controller. + + @param[in] This Pointer to the PCH_RESET_PROTOCOL instan= ce. + @param[in] ResetType UEFI defined reset type. + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a pla= tform specific reset. + The exact type of the reset is defined b= y the EFI_GUID that follows + the Null-terminated Unicode string. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET) ( + IN PCH_RESET_PROTOCOL *This, + IN PCH_RESET_TYPE ResetType, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ); + +/** + Retrieve PCH platform specific ResetData + + @param[in] Guid PCH platform specific reset GUID. + @param[out] DataSize The size of ResetData in bytes. + + @retval ResetData A platform specific reset that the exact type of + the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. + @retval NULL If Guid is not defined in PCH platform specific re= set. +**/ +typedef +VOID * +(EFIAPI *PCH_RESET_GET_RESET_DATA) ( + IN EFI_GUID *Guid, + OUT UINTN *DataSize + ); + +/** + Interface structure to execute Pch Reset from the host controller. +**/ +struct _PCH_RESET_PROTOCOL { + PCH_RESET Reset; + PCH_RESET_GET_RESET_DATA GetResetData; +}; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Protocol/Spi= .h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Protocol/Spi.h new file mode 100644 index 0000000000..b7472c31b3 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Protocol/Spi.h @@ -0,0 +1,306 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_SPI_PROTOCOL_H_ +#define _PCH_SPI_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiSpiProtocolGuid; +extern EFI_GUID gEfiSmmSpiProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SPI_PROTOCOL EFI_SPI_PROTOCOL; + +// +// SPI protocol data structures and definitions +// + +/** + Flash Region Type +**/ +typedef enum { + FlashRegionDescriptor, + FlashRegionBios, + FlashRegionMe, + FlashRegionGbE, + FlashRegionPlatformData, + FlashRegionDer, + FlashRegionSecondaryBios, + FlashRegionuCodePatch, + FlashRegionEC, + FlashRegionDeviceExpansion2, + FlashRegionIE, + FlashRegion10Gbe_A, + FlashRegion10Gbe_B, + FlashRegion13, + FlashRegion14, + FlashRegion15, + FlashRegionAll, + FlashRegionMax +} FLASH_REGION_TYPE; + +#define SPI_DESCR_ADDR_FLVALSIG 0x10 +#define SPI_DESCR_ADDR_FLMAP0 0x14 +#define SPI_DESCR_ADDR_FLMAP1 0x18 + +// +// Protocol member functions +// + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received. + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ) ( + IN EFI_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + Write data to the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE) ( + IN EFI_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ); + +/** + Erase some area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_ERASE) ( + IN EFI_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ); + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data = read. + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_SFDP) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ); + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ); + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ); + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_STATUS) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ); + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) ( + IN EFI_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ); + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining PCH Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining CPU Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + These protocols/PPI allows a platform module to perform SPI operations t= hrough the + Intel PCH SPI Host Controller Interface. +**/ +struct _PCH_SPI_PROTOCOL { + /** + This member specifies the revision of this structure. This field is us= ed to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + PCH_SPI_FLASH_READ FlashRead; ///< Read data fro= m the flash part. + PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to= the flash part. + PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some ar= ea on the flash part. + PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP dat= a from the flash part. + PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id= from the flash part. + PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the sta= tus register in the flash part. + PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status r= egister in the flash part. + PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI r= egion base and size + PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft= Strap Values + PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft= Strap Values +}; + +/** + PCH SPI PPI/PROTOCOL revision number + + Revision 1: Initial version +**/ +#define PCH_SPI_SERVICES_REVISION 1 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/SaRegs.h b/S= ilicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/SaRegs.h new file mode 100644 index 0000000000..20a36bea36 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/SaRegs.h @@ -0,0 +1,700 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SA_REGS_H_ +#define _SA_REGS_H_ + +// +// DEVICE 0 (Memory Controller Hub) +// +#define SA_MC_BUS 0x00 +#define SA_MC_DEV 0x00 +#define SA_MC_FUN 0x00 +#define V_SA_MC_VID 0x8086 +#define R_SA_MC_DEVICE_ID 0x02 +#define R_SA_MC_CAPID0_B 0xE8 + +// +// Macros that judge which type a device ID belongs to +// + +// +// CPU Mobile SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_SKL_MB_ULT_1 0x1904 ///< Skylake Ult (OPI) (2+1F/= 1.5F/2F/3/3E) Mobile SA DID +#define V_SA_DEVICE_ID_SKL_MB_ULX_2 0x190C ///< Skylake Ulx (OPI) (2+1F/= 1.5F/2) SA DID +#define V_SA_DEVICE_ID_SKL_MB_ULX_3 0x1924 ///< Skylake Ulx (OPI) +// +// CPU Halo SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_SKL_HALO_1 0x1900 ///< Skylake Halo (2+2/1) SA = DID +#define V_SA_DEVICE_ID_SKL_HALO_2 0x1910 ///< Skylake Halo (4+2/4E/3FE= ) SA DID +// +// CPU Desktop SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_SKL_DT_1 0x190F ///< Skylake Desktop (2+1F/1.= 5F/2) SA DID +#define V_SA_DEVICE_ID_SKL_DT_2 0x191F ///< Skylake Desktop (4+2/4) = SA DID +// +// CPU Server SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_SKL_SVR_1 0x1908 ///< Skylake Server (2+2/3E) = SA DID +#define V_SA_DEVICE_ID_SKL_SVR_2 0x1918 ///< Skylake Server (4+1/2/4E= ) SA DID + +/// +/// Device IDs that are Mobile specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_SKL_MB_ULT_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_SKL_MB_ULX_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_SKL_MB_ULX_3) \ + ) + +/// +/// Device IDs that are Desktop specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_SKL_DT_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_SKL_DT_2) \ + ) + +/// +/// Device IDS that are Server specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_SERVER(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_SKL_SVR_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_SKL_SVR_2) \ + ) + +/// +/// Device IDs that are Halo specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_HALO(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_SKL_HALO_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_SKL_HALO_2) \ + ) + +/** + Description: + This is the base address for the PCI Express Egress Port MMIO Configurat= ion space. There is no physical memory within this 4KB window that can be = addressed. The 4KB reserved by this register does not alias to any PCI 2.3= compliant memory mapped space. On reset, the EGRESS port MMIO configurati= on space is disabled and must be enabled by writing a 1 to PXPEPBAREN [Dev = 0, offset 40h, bit 0]. + All the bits in this register are locked in LT mode. +**/ +#define R_SA_PXPEPBAR (0x40) +// +// Description of PXPEPBAREN (0:0) +// - 0: PXPEPBAR is disabled and does not claim any memory +// - 1: PXPEPBAR memory mapped accesses are claimed and decoded appropria= tely +// - This register is locked by LT. +// +#define N_SA_PXPEPBAR_PXPEPBAREN_OFFSET (0x0) +#define S_SA_PXPEPBAR_PXPEPBAREN_WIDTH (0x1) +#define B_SA_PXPEPBAR_PXPEPBAREN_MASK (0x1) +#define V_SA_PXPEPBAR_PXPEPBAREN_DEFAULT (0x0) +// +// Description of PXPEPBAR (12:38) +// - This field corresponds to bits 38 to 12 of the base address PCI Expre= ss Egress Port MMIO configuration space. BIOS will program this register r= esulting in a base address for a 4KB block of contiguous memory address spa= ce. This register ensures that a naturally aligned 4KB space is allocated = within the first 512GB of addressable memory space. System Software uses t= his base address to program the PCI Express Egress Port MMIO register set. = All the bits in this register are locked in LT mode. +// +#define N_SA_PXPEPBAR_PXPEPBAR_OFFSET (0xc) +#define S_SA_PXPEPBAR_PXPEPBAR_WIDTH (0x1b) +#define B_SA_PXPEPBAR_PXPEPBAR_MASK (0x7ffffff000) +#define V_SA_PXPEPBAR_PXPEPBAR_DEFAULT (0x0) + +/** + Description: + - This is the base address for the Host Memory Mapped Configuration space= . There is no physical memory within this 32KB window that can be addresse= d. The 32KB reserved by this register does not alias to any PCI 2.3 compli= ant memory mapped space. On reset, the Host MMIO Memory Mapped Configuatio= n space is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, = offset48h, bit 0]. + - All the bits in this register are locked in LT mode. + - The register space contains memory control, initialization, timing, and= buffer strength registers; clocking registers; and power and thermal manag= ement registers. +**/ +#define R_SA_MCHBAR (0x48) +/** + Description of MCHBAREN (0:0) + - 0: MCHBAR is disabled and does not claim any memory + - 1: MCHBAR memory mapped accesses are claimed and decoded appropriately + - This register is locked by LT. +**/ +#define N_SA_MCHBAR_MCHBAREN_OFFSET (0x0) +#define S_SA_MCHBAR_MCHBAREN_WIDTH (0x1) +#define B_SA_MCHBAR_MCHBAREN_MASK (0x1) +#define V_SA_MCHBAR_MCHBAREN_DEFAULT (0x0) +/** + Description of MCHBAR (15:38) + - This field corresponds to bits 38 to 15 of the base address Host Memory= Mapped configuration space. BIOS will program this register resulting in = a base address for a 32KB block of contiguous memory address space. This r= egister ensures that a naturally aligned 32KB space is allocated within the= first 512GB of addressable memory space. System Software uses this base ad= dress to program the Host Memory Mapped register set. All the bits in this = register are locked in LT mode. +**/ +#define N_SA_MCHBAR_MCHBAR_OFFSET (0xf) +#define S_SA_MCHBAR_MCHBAR_WIDTH (0x18) +#define B_SA_MCHBAR_MCHBAR_MASK (0x7fffff8000ULL) +#define V_SA_MCHBAR_MCHBAR_DEFAULT (0x0) + +/** + Description: + - All the bits in this register are LT lockable. +**/ +#define R_SA_GGC (0x50) +/** + Description of GGCLCK (0:0) + - When set to 1b, this bit will lock all bits in this register. +**/ +#define N_SA_GGC_GGCLCK_OFFSET (0x0) +#define S_SA_GGC_GGCLCK_WIDTH (0x1) +#define B_SA_GGC_GGCLCK_MASK (0x1) +#define V_SA_GGC_GGCLCK_DEFAULT (0x0) +/** + Description of IVD (1:1) + - 0: Enable. Device 2 (IGD) claims VGA memory and IO cycles, the Sub-Cla= ss Code within Device 2 Class Code register is 00. + - 1: Disable. Device 2 (IGD) does not claim VGA cycles (Mem and IO), and= the Sub- Class Code field within Device 2 function 0 Class Code register i= s 80. + - BIOS Requirement: BIOS must not set this bit to 0 if the GMS field (bi= ts 7:3 of this register) pre-allocates no memory. + - This bit MUST be set to 1 if Device 2 is disabled either via a fuse or = fuse override (CAPID0[46] =3D 1) or via a register (DEVEN[3] =3D 0). + - This register is locked by LT lock. +**/ +#define N_SA_GGC_IVD_OFFSET (0x1) +#define S_SA_GGC_IVD_WIDTH (0x1) +#define B_SA_GGC_IVD_MASK (0x2) +#define V_SA_GGC_IVD_DEFAULT (0x0) +/** + For SKL + Description of GMS (8:15) + - This field is used to select the amount of Main Memory that is pre-allo= cated to support the Internal Graphics device in VGA (non-linear) and Nativ= e (linear) modes. The BIOS ensures that memory is pre-allocated only when = Internal graphics is enabled. + - This register is also LT lockable. + - Valid options are 0 (0x0) to 2048MB (0x40) in multiples of 32 MB + - Default is 64MB + - All other values are reserved + - Hardware does not clear or set any of these bits automatically based on= IGD being disabled/enabled. + - BIOS Requirement: BIOS must not set this field to 0h if IVD (bit 1 of t= his register) is 0. +**/ +#define N_SKL_SA_GGC_GMS_OFFSET (0x8) +#define S_SKL_SA_GGC_GMS_WIDTH (0x8) +#define B_SKL_SA_GGC_GMS_MASK (0xff00) +#define V_SKL_SA_GGC_GMS_DEFAULT (0x01) + +/** + For SKL + Description of GGMS (6:7) + - This field is used to select the amount of Main Memory that is pre-allo= cated to support the Internal Graphics Translation Table. The BIOS ensures= that memory is pre-allocated only when Internal graphics is enabled. + - GSM is assumed to be a contiguous physical DRAM space with DSM, and BIO= S needs to allocate a contiguous memory chunk. Hardware will derive the ba= se of GSM from DSM only using the GSM size programmed in the register. + - Valid options: + - 0h: 0 MB of memory pre-allocated for GTT. + - 1h: 2 MB of memory pre-allocated for GTT. + - 2h: 4 MB of memory pre-allocated for GTT. (default) + - 3h: 8 MB of memory pre-allocated for GTT. + - Others: Reserved + - Hardware functionality in case of programming this value to Reserved is= not guaranteed. +**/ +#define N_SKL_SA_GGC_GGMS_OFFSET (0x6) +#define S_SKL_SA_GGC_GGMS_WIDTH (0x2) +#define B_SKL_SA_GGC_GGMS_MASK (0xc0) +#define V_SKL_SA_GGC_GGMS_DEFAULT (2) +#define V_SKL_SA_GGC_GGMS_DIS 0 +#define V_SKL_SA_GGC_GGMS_2MB 1 +#define V_SKL_SA_GGC_GGMS_4MB 2 +#define V_SKL_SA_GGC_GGMS_8MB 3 + +/** + Description: + - Allows for enabling/disabling of PCI devices and functions that are wit= hin the CPU package. The table below the bit definitions describes the beha= vior of all combinations of transactions to devices controlled by this regi= ster. + All the bits in this register are LT Lockable. +**/ +#define R_SA_DEVEN (0x54) + +/** + Description + - Protected Audio Video Path Control + - All the bits in this register are locked by LT. When locked the R/W bi= ts are RO. +**/ +#define R_SA_PAVPC (0x58) +/** + Description of PCME (0:0) + - This field enables Protected Content Memory within Graphics Stolen Memo= ry. + - This register is locked (becomes read-only) when PAVPLCK =3D 1b. + - This register is read-only (stays at 0b) when PAVP fuse is set to "disa= bled" + - 0: Protected Content Memory is disabled + - 1: Protected Content Memory is enabled +**/ +#define N_SA_PAVPC_PCME_OFFSET (0x0) +#define S_SA_PAVPC_PCME_WIDTH (0x1) +#define B_SA_PAVPC_PCME_MASK (0x1) +#define V_SA_PAVPC_PCME_MASK (0x0) +/** + Description of PAVPE (1:1) + - 0: PAVP path is disabled + - 1: PAVP path is enabled + - This register is locked (becomes read-only) when PAVPLCK =3D 1b + - This register is read-only (stays at 0b) when PAVP capability is set to= "disabled" as defined by CAPID0_B[PAVPE]. +**/ +#define N_SA_PAVPC_PAVPE_OFFSET (0x1) +#define S_SA_PAVPC_PAVPE_WIDTH (0x1) +#define B_SA_PAVPC_PAVPE_MASK (0x2) +#define V_SA_PAVPC_PAVPE_DEFAULT (0x0) +/** + Description of PAVPLCK (2:2) + - This bit will lock all writeable contents in this register when set (in= cluding itself). + - This bit will be locked if PAVP is fused off. +**/ +#define N_SA_PAVPC_PAVPLCK_OFFSET (0x2) +#define S_SA_PAVPC_PAVPLCK_WIDTH (0x1) +#define B_SA_PAVPC_PAVPLCK_MASK (0x4) +#define V_SA_PAVPC_PAVPLCK_DEFAULT (0x0) +/** + Description of PCMBASE (20:31) + - This field is used to set the base of Protected Content Memory. + - This corresponds to bits 31:20 of the system memory address range, givi= ng a 1MB granularity. This value MUST be at least 1MB above the base and be= low the top of stolen memory. + - This register is locked (becomes read-only) when PAVPE =3D 1b. +**/ +#define N_SA_PAVPC_PCMBASE_OFFSET (0x14) +#define S_SA_PAVPC_PCMBASE_WIDTH (0xc) +#define B_SA_PAVPC_PCMBASE_MASK (0xfff00000) +#define V_SA_PAVPC_PCMBASE_DEFAULT (0x0) + +#define R_SA_DPR (0x5c) ///< DMA protected range register +/** + Description of LOCK (0:0) + - This bit will lock all writeable settings in this register, including i= tself. +**/ +#define N_SA_DPR_LOCK_OFFSET (0x0) +#define S_SA_DPR_LOCK_WIDTH (0x1) +#define B_SA_DPR_LOCK_MASK (0x1) +#define V_SA_DPR_LOCK_DEFAULT (0x0) +/** + Description of PRS (1:1) + - This field indicates the status of DPR. + - 0: DPR protection disabled + - 1: DPR protection enabled +**/ +#define N_SA_DPR_PRS_OFFSET (0x1) +#define S_SA_DPR_PRS_WIDTH (0x1) +#define B_SA_DPR_PRS_MASK (0x2) +#define V_SA_DPR_PRS_DEFAULT (0x0) +/** + Description of EPM (2:2) + - This field controls DMA accesses to the DMA Protected Range (DPR) regio= n. + - 0: DPR is disabled + - 1: DPR is enabled. All DMA requests accessing DPR region are blocked. + - HW reports the status of DPR enable/disable through the PRS field in th= is register. +**/ +#define N_SA_DPR_EPM_OFFSET (0x2) +#define S_SA_DPR_EPM_WIDTH (0x1) +#define B_SA_DPR_EPM_MASK (0x4) +#define V_SA_DPR_EPM_DEFAULT (0x0) +/** + Description of DPRSIZE (11:4) + - This field is used to specify the size of memory protected from DMA acc= ess in MB + - The maximum amount of memory that will be protected is 255MB + - The Top of protected range is the base of TSEG-1 +**/ +#define N_DPR_DPRSIZE_OFFSET (0x4) +#define V_DPR_DPRSIZE_WIDTH (0x8) +#define V_DPR_DPRSIZE_MASK (0xFF0) +#define V_DPR_DPRSIZE_DEFAULT (0x0) +/** + Description of TOPOFDPR (31:20) + - This is the Top address 1 of DPR - Base of TSEG +**/ +#define N_SA_DPR_TOPOFDPR_OFFSET (20) +#define S_SA_DPR_TOPOFDPR_WIDTH (0xC) +#define B_SA_DPR_TOPOFDPR_MASK (0xFFF00000) +#define V_SA_DPR_TOPOFDPR_DEFAULT (0x0) + +/** + This is the base address for the Root Complex configuration space. This w= indow of addresses contains the Root Complex Register set for the PCI Expre= ss Hierarchy associated with the Host Bridge. There is no physical memory w= ithin this 4KB window that can be addressed. The 4KB reserved by this regis= ter does not alias to any PCI 2.3 compliant memory mapped space. On reset, = the Root Complex configuration space is disabled and must be enabled by wri= ting a 1 to DMIBAREN [Dev 0, offset 68h, bit 0] All the bits in this regist= er are locked in LT mode. +**/ +#define R_SA_DMIBAR (0x68) +/** + Description of DMIBAREN (0:0) + - 0: DMIBAR is disabled and does not claim any memory + - 1: DMIBAR memory mapped accesses are claimed and decoded appropriately + - This register is locked by LT. +**/ +#define N_SA_DMIBAR_DMIBAREN_OFFSET (0x0) +#define S_SA_DMIBAR_DMIBAREN_WIDTH (0x1) +#define B_SA_DMIBAR_DMIBAREN_MASK (0x1) +#define V_SA_DMIBAR_DMIBAREN_DEFAULT (0x0) +/** + Description of DMIBAR (12:38) + - This field corresponds to bits 38 to 12 of the base address DMI configu= ration space. BIOS will program this register resulting in a base address f= or a 4KB block of contiguous memory address space. This register ensures th= at a naturally aligned 4KB space is allocated within the first 512GB of add= ressable memory space. System Software uses this base address to program th= e DMI register set. All the Bits in this register are locked in LT mode. +**/ +#define N_SA_DMIBAR_DMIBAR_OFFSET (0xc) +#define S_SA_DMIBAR_DMIBAR_WIDTH (0x1b) +#define B_SA_DMIBAR_DMIBAR_MASK (0x7ffffff000) +#define V_SA_DMIBAR_DMIBAR_DEFAULT (0x0) + +/** + Description: + - This register determines the Mask Address register of the memory range = that is pre-allocated to the Manageability Engine. Together with the MESEG= _BASE register it controls the amount of memory allocated to the ME. + - This register is locked by LT. +**/ +#define R_SA_MESEG_MASK (0x78) +/** + Description of MELCK (10:10) + - This field indicates whether all bits in the MESEG_BASE and MESEG_MASK = registers are locked. When locked, updates to any field for these register= s must be dropped. +**/ +#define N_SA_MESEG_MASK_MELCK_OFFSET (0xa) +#define S_SA_MESEG_MASK_MELCK_WIDTH (0x1) +#define B_SA_MESEG_MASK_MELCK_MASK (0x400) +#define V_SA_MESEG_MASK_MELCK_DEFAULT (0x0) +/** + Description of ME_STLEN_EN (11:11) + - Indicates whether the ME stolen Memory range is enabled or not. +**/ +#define N_SA_MESEG_MASK_ME_STLEN_EN_OFFSET (0xb) +#define S_SA_MESEG_MASK_ME_STLEN_EN_WIDTH (0x1) +#define B_SA_MESEG_MASK_ME_STLEN_EN_MASK (0x800) +#define V_SA_MESEG_MASK_ME_STLEN_EN_DEFAULT (0x0) +/** + Description of MEMASK (20:38) + - This field indicates the bits that must match MEBASE in order to qualif= y as an ME Memory Range access. + - For example, if the field is set to 7FFFFh, then ME Memory is 1MB in si= ze. + - Another example is that if the field is set to 7FFFEh, then ME Memory i= s 2MB in size. + - In other words, the size of ME Memory Range is limited to power of 2 ti= mes 1MB. +**/ +#define N_SA_MESEG_MASK_MEMASK_OFFSET (0x14) +#define S_SA_MESEG_MASK_MEMASK_WIDTH (0x13) +#define B_SA_MESEG_MASK_MEMASK_MASK (0x7ffff00000) +#define V_SA_MESEG_MASK_MEMASK_DEFAULT (0x0) + +/** + Description: + - This register controls the read, write and shadowing attributes of the = BIOS range from F_0000h to F_FFFFh. The Uncore allows programmable memory = attributes on 13 legacy memory segments of various sizes in the 768KB to 1M= B address range. Seven Programmable Attribute Map (PAM) registers are used= to support these features. Cacheability of these areas is controlled via = the MTRR register in the core. + - Two bits are used to specify memory attributes for each memory segment.= These bits apply to host accesses to the PAM areas. These attributes are: + - RE - Read Enable. When RE=3D1, the host read accesses to the correspon= ding memory segment are claimed by the Uncore and directed to main memory. = Conversely, when RE=3D0, the host read accesses are directed to DMI. + - WE - Write Enable. When WE=3D1, the host write accesses to the corresp= onding memory segment are claimed by the Uncore and directed to main memory= . Conversely, when WE=3D0, the host read accesses are directed to DMI. + - The RE and WE attributes permit a memory segment to be Read Only, Write= Only, Read/Write or Disabled. For example, if a memory segment has RE=3D1= and WE=3D0, the segment is Read Only. +**/ +#define R_SA_PAM0 (0x80) +/// +/// Description: +/// This register controls the read, write and shadowing attributes of th= e BIOS range from E_0000h to E_7FFFh. The Uncore allows programmable memor= y attributes on 13 legacy memory segments of various sizes in the 768KB to = 1MB address range. Seven Programmable Attribute Map (PAM) registers are us= ed to support these features. Cacheability of these areas is controlled vi= a the MTRR register in the core. +/// Two bits are used to specify memory attributes for each memory segmen= t. These bits apply to host accesses to the PAM areas. These attributes a= re: +/// RE - Read Enable. When RE=3D1, the host read accesses to the corresp= onding memory segment are claimed by the Uncore and directed to main memory= . Conversely, when RE=3D0, the host read accesses are directed to DMI. +/// WE - Write Enable. When WE=3D1, the host write accesses to the corre= sponding memory segment are claimed by the Uncore and directed to main memo= ry. Conversely, when WE=3D0, the host read accesses are directed to DMI. +/// The RE and WE attributes permit a memory segment to be Read Only, Wri= te Only, Read/Write or Disabled. For example, if a memory segment has RE= =3D1 and WE=3D0, the segment is Read Only. +/// +#define R_SA_PAM5 (0x85) +/// +/// Description: +/// This register controls the read, write and shadowing attributes of th= e BIOS range from E_8000h to E_FFFFh. The Uncore allows programmable memor= y attributes on 13 legacy memory segments of various sizes in the 768KB to = 1MB address range. Seven Programmable Attribute Map (PAM) registers are us= ed to support these features. Cacheability of these areas is controlled vi= a the MTRR register in the core. +/// Two bits are used to specify memory attributes for each memory segmen= t. These bits apply to host accesses to the PAM areas. These attributes a= re: +/// RE - Read Enable. When RE=3D1, the host read accesses to the corresp= onding memory segment are claimed by the Uncore and directed to main memory= . Conversely, when RE=3D0, the host read accesses are directed to DMI. +/// WE - Write Enable. When WE=3D1, the host write accesses to the corre= sponding memory segment are claimed by the Uncore and directed to main memo= ry. Conversely, when WE=3D0, the host read accesses are directed to DMI. +/// The RE and WE attributes permit a memory segment to be Read Only, Wri= te Only, Read/Write or Disabled. For example, if a memory segment has RE= =3D1 and WE=3D0, the segment is Read Only. +/// +#define R_SA_PAM6 (0x86) +/// +/// Description: +/// The SMRAMC register controls how accesses to Compatible SMRAM spaces = are treated. The Open, Close and Lock bits function only when G_SMRAME bit= is set to 1. Also, the Open bit must be reset before the Lock bit is set. +/// +#define R_SA_SMRAMC (0x88) + +/// +/// Description: +/// +#define R_SA_REMAPBASE (0x90) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including= itself. +/// +#define N_SA_REMAPBASE_LOCK_OFFSET (0x0) +#define S_SA_REMAPBASE_LOCK_WIDTH (0x1) +#define B_SA_REMAPBASE_LOCK_MASK (0x1) +#define V_SA_REMAPBASE_LOCK_DEFAULT (0x0) +/// +/// Description of REMAPBASE (20:35) +/// The value in this register defines the lower boundary of the Remap wi= ndow. The Remap window is inclusive of this address. In the decoder A[19:0]= of the Remap Base Address are assumed to be 0's. Thus the bottom of the de= fined memory range will be aligned to a 1MB boundary. +/// When the value in this register is greater than the value programmed = into the Remap Limit register, the Remap window is disabled. +/// These bits are LT lockable. +/// +#define N_SA_REMAPBASE_REMAPBASE_OFFSET (0x14) +#define S_SA_REMAPBASE_REMAPBASE_WIDTH (0x10) +#define B_SA_REMAPBASE_REMAPBASE_MASK (0xffff00000) +#define V_SA_REMAPBASE_REMAPBASE_DEFAULT (0xffff00000) + +/// +/// Description: +/// +#define R_SA_REMAPLIMIT (0x98) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including= itself. +/// +#define N_SA_REMAPLIMIT_LOCK_OFFSET (0x0) +#define S_SA_REMAPLIMIT_LOCK_WIDTH (0x1) +#define B_SA_REMAPLIMIT_LOCK_MASK (0x1) +#define V_SA_REMAPLIMIT_LOCK_DEFAULT (0x0) +/// +/// Description of REMAPLMT (20:35) +/// The value in this register defines the upper boundary of the Remap wi= ndow. The Remap window is inclusive of this address. In the decoder A[19:0]= of the remap limit address are assumed to be F's. Thus the top of the defi= ned range will be one byte less than a 1MB boundary. +/// When the value in this register is less than the value programmed int= o the Remap Base register, the Remap window is disabled. +/// These Bits are LT lockable. +/// +#define N_SA_REMAPLIMIT_REMAPLMT_OFFSET (0x14) +#define S_SA_REMAPLIMIT_REMAPLMT_WIDTH (0x10) +#define B_SA_REMAPLIMIT_REMAPLMT_MASK (0xffff00000) +#define V_SA_REMAPLIMIT_REMAPLMT_DEFAULT (0x0) + +/// +/// Description: +/// This Register contains the size of physical memory. BIOS determines = the memory size reported to the OS using this Register. +/// +#define R_SA_TOM (0xa0) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including= itself. +/// +#define N_SA_TOM_LOCK_OFFSET (0x0) +#define S_SA_TOM_LOCK_WIDTH (0x1) +#define B_SA_TOM_LOCK_MASK (0x1) +#define V_SA_TOM_LOCK_DEFAULT (0x0) + +/// +/// Description of TOM (20:38) +/// This register reflects the total amount of populated physical memory.= This is NOT necessarily the highest main memory address (holes may exist i= n main memory address map due to addresses allocated for memory mapped IO).= These bits correspond to address bits 38:20 (1MB granularity). Bits 19:0 a= re assumed to be 0. All the bits in this register are locked in LT mode. +/// +#define N_SA_TOM_TOM_OFFSET (0x14) +#define S_SA_TOM_TOM_WIDTH (0x13) +#define B_SA_TOM_TOM_MASK (0x7ffff00000) +#define V_SA_TOM_TOM_DEFAULT (0x7ffff00000) + +/// +/// Description: +/// This 64 bit register defines the Top of Upper Usable DRAM. +/// Configuration software must set this value to TOM minus all EP stolen= memory if reclaim is disabled. If reclaim is enabled, this value must be = set to reclaim limit + 1byte, 1MB aligned, since reclaim limit is 1MB align= ed. Address bits 19:0 are assumed to be 000_0000h for the purposes of addre= ss comparison. The Host interface positively decodes an address towards DRA= M if the incoming address is less than the value programmed in this registe= r and greater than or equal to 4GB. +/// BIOS Restriction: Minimum value for TOUUD is 4GB. +/// These bits are LT lockable. +/// +#define R_SA_TOUUD (0xa8) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including= itself. +/// +#define N_SA_TOUUD_LOCK_OFFSET (0x0) +#define S_SA_TOUUD_LOCK_WIDTH (0x1) +#define B_SA_TOUUD_LOCK_MASK (0x1) +#define V_SA_TOUUD_LOCK_DEFAULT (0x0) +/// +/// Description of TOUUD (20:38) +/// This register contains bits 38 to 20 of an address one byte above th= e maximum DRAM memory above 4G that is usable by the operating system. Conf= iguration software must set this value to TOM minus all EP stolen memory if= reclaim is disabled. If reclaim is enabled, this value must be set to recl= aim limit 1MB aligned since reclaim limit + 1byte is 1MB aligned. Address b= its 19:0 are assumed to be 000_0000h for the purposes of address comparison= . The Host interface positively decodes an address towards DRAM if the inco= ming address is less than the value programmed in this register and greater= than 4GB. +/// All the bits in this register are locked in LT mode. +/// +#define N_SA_TOUUD_TOUUD_OFFSET (0x14) +#define S_SA_TOUUD_TOUUD_WIDTH (0x13) +#define B_SA_TOUUD_TOUUD_MASK (0x7ffff00000ULL) +#define V_SA_TOUUD_TOUUD_DEFAULT (0x0) + +/// +/// Description: +/// This register contains the base address of graphics data stolen DRAM = memory. BIOS determines the base of graphics data stolen memory by subtract= ing the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) = from TOLUD (PCI Device 0 offset BC bits 31:20). +/// +#define R_SA_BDSM (0xb0) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including= itself. +/// +#define N_SA_BDSM_LOCK_OFFSET (0x0) +#define S_SA_BDSM_LOCK_WIDTH (0x1) +#define B_SA_BDSM_LOCK_MASK (0x1) +#define V_SA_BDSM_LOCK_DEFAULT (0x0) +/// +/// Description of BDSM (20:31) +/// This register contains bits 31 to 20 of the base address of stolen DR= AM memory. BIOS determines the base of graphics stolen memory by subtractin= g the graphics stolen memory size (PCI Device 0 offset 52 bits 6:4) from TO= LUD (PCI Device 0 offset BC bits 31:20). +/// +#define N_SA_BDSM_BDSM_OFFSET (0x14) +#define S_SA_BDSM_BDSM_WIDTH (0xc) +#define B_SA_BDSM_BDSM_MASK (0xfff00000) +#define V_SA_BDSM_BDSM_DEFAULT (0x0) + +/// +/// Description: +/// This register contains the base address of stolen DRAM memory for the= GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT = graphics stolen memory size (PCI Device 0 offset 52 bits 9:8) from the Grap= hics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20). +/// +#define R_SA_BGSM (0xb4) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including= itself. +/// +#define N_SA_BGSM_LOCK_OFFSET (0x0) +#define S_SA_BGSM_LOCK_WIDTH (0x1) +#define B_SA_BGSM_LOCK_MASK (0x1) +#define V_SA_BGSM_LOCK_DEFAULT (0x0) +/// +/// Description of BGSM (20:31) +/// This register contains the base address of stolen DRAM memory for the= GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT = graphics stolen memory size (PCI Device 0 offset 52 bits 11:8) from the Gra= phics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20). +/// +#define N_SA_BGSM_BGSM_OFFSET (0x14) +#define S_SA_BGSM_BGSM_WIDTH (0xc) +#define B_SA_BGSM_BGSM_MASK (0xfff00000) +#define V_SA_BGSM_BGSM_DEFAULT (0x0) + +/// +/// Description: +/// This register contains the base address of TSEG DRAM memory. BIOS det= ermines the base of TSEG memory which must be at or below Graphics Base of = GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20). +/// +#define R_SA_TSEGMB (0xb8) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including= itself. +/// +#define N_SA_TSEGMB_LOCK_OFFSET (0x0) +#define S_SA_TSEGMB_LOCK_WIDTH (0x1) +#define B_SA_TSEGMB_LOCK_MASK (0x1) +#define V_SA_TSEGMB_LOCK_DEFAULT (0x0) +/// +/// Description of TSEGMB (20:31) +/// This register contains the base address of TSEG DRAM memory. BIOS det= ermines the base of TSEG memory which must be at or below Graphics Base of = GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20). +/// +#define N_SA_TSEGMB_TSEGMB_OFFSET (0x14) +#define S_SA_TSEGMB_TSEGMB_WIDTH (0xc) +#define B_SA_TSEGMB_TSEGMB_MASK (0xfff00000) +#define V_SA_TSEGMB_TSEGMB_DEFAULT (0x0) + +/// +/// Description: +/// This register contains the Top of low memory address. +/// +#define R_SA_TOLUD (0xbc) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including= itself. +/// +#define N_SA_TOLUD_LOCK_OFFSET (0x0) +#define S_SA_TOLUD_LOCK_WIDTH (0x1) +#define B_SA_TOLUD_LOCK_MASK (0x1) +#define V_SA_TOLUD_LOCK_DEFAULT (0x0) +/// +/// Description of TOLUD (20:31) +/// This register contains bits 31 to 20 of an address one byte above the= maximum DRAM memory below 4G that is usable by the operating system. Addre= ss bits 31 down to 20 programmed to 01h implies a minimum memory size of 1M= B. Configuration software must set this value to the smaller of the followi= ng 2 choices: maximum amount memory in the system minus ME stolen memory pl= us one byte or the minimum address allocated for PCI memory. Address bits 1= 9:0 are assumed to be 0_0000h for the purposes of address comparison. The H= ost interface positively decodes an address towards DRAM if the incoming ad= dress is less than the value programmed in this register. +/// The Top of Low Usable DRAM is the lowest address above both Graphics = Stolen memory and Tseg. BIOS determines the base of Graphics Stolen Memory = by subtracting the Graphics Stolen Memory Size from TOLUD and further decre= ments by Tseg size to determine base of Tseg. All the Bits in this register= are locked in LT mode. +/// This register must be 1MB aligned when reclaim is enabled. +/// +#define N_SA_TOLUD_TOLUD_OFFSET (0x14) +#define S_SA_TOLUD_TOLUD_WIDTH (0xc) +#define B_SA_TOLUD_TOLUD_MASK (0xfff00000) +#define V_SA_TOLUD_TOLUD_DEFAULT (0x100000) + +#define R_SA_MC_CAPID0_A_OFFSET 0xE4 + +// +// Thermal Management Controls +// +/// +/// Device 2 Register Equates +// +// The following equates must be reviewed and revised when the specificati= on is ready. +// +#define SA_IGD_BUS 0x00 +#define SA_IGD_DEV 0x02 +#define SA_IGD_FUN_0 0x00 +#define SA_IGD_FUN_1 0x01 +#define SA_IGD_DEV_FUN (SA_IGD_DEV << 3) +#define SA_IGD_BUS_DEV_FUN (SA_MC_BUS << 8) + SA_IGD_DEV_FUN +#define V_SA_IGD_VID 0x8086 +#define V_SA_IGD_DID 0x2A42 +#define V_SA_IGD_DID_MB 0x0106 +#define V_SA_IGD_DID_MB_1 0x0116 +#define V_SA_IGD_DID_MB_2 0x0126 +#define V_SA_IGD_DID_DT 0x0102 +#define V_SA_IGD_DID_DT_1 0x0112 +#define V_SA_IGD_DID_DT_2 0x0122 +#define V_SA_IGD_DID_DT_3 0x010A + +/// +/// For SKL IGD +/// +#define V_SA_PCI_DEV_2_GT1_SULTM_ID 0x01906 ///< Dev2-SKL ULT GT1 (2+1F= ) Mobile +#define V_SA_PCI_DEV_2_GT15F_SULTM_ID 0x01913 ///< Dev2-SKL ULT GT1.5 (2+= 1.5F) Mobile +#define V_SA_PCI_DEV_2_GT2_SULTM_ID 0x01916 ///< Dev2-SKL ULT GT2 (2+2)= Mobile +#define V_SA_PCI_DEV_2_GT2F_SULTM_ID 0x01921 ///< Dev2-SKL ULT GT2 (2+2F= ) Mobile +#define V_SA_PCI_DEV_2_GT3_SULTM_ID 0x01926 ///< Dev2-SKL ULT GT3 (3+3/= 3E) Mobile +#define V_SA_PCI_DEV_2_GT1_SHALM_ID 0x0190B ///< Dev2-SKL Halo GT1 (2+1) +#define V_SA_PCI_DEV_2_GT2_SHALM_ID 0x0191B ///< Dev2-SKL Halo GT2 (4/2= +2) +#define V_SA_PCI_DEV_2_GT3_SHALM_ID 0x0192B ///< Dev2-SKL Halo GT3 (4+3= FE) +#define V_SA_PCI_DEV_2_GT4_SHALM_ID 0x0193B ///< Dev2-SKL Halo GT4 (4+4= E) +#define V_SA_PCI_DEV_2_GT1_SULXM_ID 0x0190E ///< Dev2-SKL ULX GT1(2+1F)= Mobile +#define V_SA_PCI_DEV_2_GT15_SULXM_ID 0x01915 ///< Dev2-SKL ULX GT1.5(2+1= .5F) Mobile +#define V_SA_PCI_DEV_2_GT2_SULXM_ID 0x0191E ///< Dev2-SKL ULX GT2 (2+2)= Mobile +#define V_SA_PCI_DEV_2_GT1_SSR_ID 0x0190A ///< Dev2-SKL GT1 (4+1F) Se= rver +#define V_SA_PCI_DEV_2_GT2_SSR_ID 0x0191A ///< Dev2-SKL GT2 (4/2+2) S= erver +#define V_SA_PCI_DEV_2_GT3_SSR_ID 0x0192A ///< Dev2-SKL GT3 (2+3E) Se= rver +#define V_SA_PCI_DEV_2_GT4_SSR_ID 0x0193A ///< Dev2-SKL GT4 (4+4E) Se= rver +#define V_SA_PCI_DEV_2_GT1_SDT_ID 0x01902 ///< Dev2-SKL GT1 (2+1F) De= sktop +#define V_SA_PCI_DEV_2_GT2_SDT_ID 0x01912 ///< Dev2-SKL GT2 (4/2+2) D= esktop +#define V_SA_PCI_DEV_2_GT15_SDT_ID 0x01917 ///< Dev2-SKL GT1.5 (2+1.5F= ) Desktop +#define V_SA_PCI_DEV_2_GT4_SDT_ID 0x01932 ///< Dev2-SKL GT4 (4+4) Des= ktop + +#define R_SA_IGD_VID 0x00 +#define R_SA_IGD_DID 0x02 +#define R_SA_IGD_CMD 0x04 +/// +/// GTTMMADR for SKL is 16MB alignment (Base address =3D [38:24]) +/// +#define R_SA_IGD_GTTMMADR 0x10 +#define R_SA_IGD_GMADR 0x18 +#define R_SA_IGD_IOBAR 0x20 +#define R_SA_IGD_BSM_OFFSET 0x005C ///< Base of Stolen Memory +#define R_SA_IGD_MSAC_OFFSET 0x0062 ///< Multisize Aperture Control +#define R_SA_IGD_SWSCI_OFFSET 0x00E8 +#define R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage +/// +/// Maximum number of SDRAM channels supported by the memory controller +/// +/// +/// Maximum number of SDRAM channels supported by the memory controller +/// +#define SA_MC_MAX_CHANNELS 2 +/// +/// Maximum number of DIMM sockets supported by each channel +/// +#define SA_MC_MAX_SLOTS 2 + +/// +/// Maximum number of sides supported per DIMM +/// +#define SA_MC_MAX_SIDES 2 + +/// +/// Maximum number of DIMM sockets supported by the memory controller +/// +#define SA_MC_MAX_SOCKETS (SA_MC_MAX_CHANNELS * SA_MC_MAX_SLOTS) + +/// +/// Maximum number of rows supported by the memory controller +/// +#define SA_MC_MAX_RANKS (SA_MC_MAX_SOCKETS * SA_MC_MAX_SIDES) + +/// +/// Maximum number of rows supported by the memory controller +/// +#define SA_MC_MAX_ROWS (SA_MC_MAX_SIDES * SA_MC_MAX_SOCKETS) + +/// +/// Maximum memory supported by the memory controller +/// 4 GB in terms of KB +/// +#define SA_MC_MAX_MEM_CAPACITY (4 * 1024 * 1024) + +/// +/// Define the SPD Address for DIMM 0 +/// +#define SA_MC_DIMM0_SPD_ADDRESS 0xA0 + +/// +/// Define the maximum number of data bytes on a system with no ECC memory= support. +/// +#define SA_MC_MAX_BYTES_NO_ECC (8) + +/// +/// Define the maximum number of SPD data bytes on a DIMM. +/// +#define SA_MC_MAX_SPD_SIZE (512) + +/// +/// Vt-d Engine base address. +/// +#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT2 for IGD +#define R_SA_MCHBAR_VTD2_OFFSET 0x5410 ///< HW UNIT3 for all other - PEG= , USB, SATA etc + +#endif --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Tue, 11 May 2021 02:48:44 -0700 IronPort-SDR: oqJa6PBfZysJ3GVZIahNSE0NkJVQV0GRZeCjJ1kLhoWrDtteEghlYKrLdieK0IUIntwXOsgzeV JyTF4r0vT07w== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="179664954" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="179664954" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:43 -0700 IronPort-SDR: 0nIyZP2bBhyxvcqgGeiu7WhaiZcS5Xx1NJj543ptqBiKyImOZ4OjUhDpCHdigM1ST6MKhHulKn 0A24uEuLrUDg== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436573934" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:43 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 04/18] PurleyRefreshSiliconPkg/Pch: Add Private Header Files Date: Tue, 11 May 2021 02:48:12 -0700 Message-Id: <20210511094826.12495-5-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: xZpIK7gZeMk12eZ4krhay3lrx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726527; bh=p5E2Yd2xU+j8QwBqFRCXogB9EuzELaelmtExdFWsA0I=; h=Cc:Date:From:Reply-To:Subject:To; b=RHC1ZYi3oQZCQkdo6UFcd7+LiAwSEZd6m29EvlvejVLhpD6gzFgBvI+6lb8mzdE94xV v45cfPEM3iu5x0ZLIPuNDh3J0NdCgGm/D2/3oGD+A7u/ocl/LQKqSdyX9LxUyWBUP1/ih od+myiTO42IBH8FjUUIZlwddvUUEvmcV00c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../Library/PchResetCommonLib.h | 59 +++++++ .../Pch/IncludePrivate/PchHHsioAx.h | 16 ++ .../Pch/IncludePrivate/PchHHsioBx.h | 16 ++ .../Pch/IncludePrivate/PchHHsioDx.h | 16 ++ .../Pch/IncludePrivate/PchHsio.h | 147 ++++++++++++++++++ .../Pch/IncludePrivate/PchLbgHsioAx.h | 16 ++ .../Pch/IncludePrivate/PchLbgHsioBx.h | 17 ++ .../Pch/IncludePrivate/PchLbgHsioBxD.h | 19 +++ .../Pch/IncludePrivate/PchLbgHsioBxD_Ext.h | 19 +++ .../Pch/IncludePrivate/PchLbgHsioBx_Ext.h | 17 ++ .../Pch/IncludePrivate/PchLbgHsioSx.h | 17 ++ .../Pch/IncludePrivate/PchLbgHsioSx_Ext.h | 17 ++ .../Pch/IncludePrivate/PchLpHsioBx.h | 16 ++ .../Pch/IncludePrivate/PchLpHsioCx.h | 16 ++ .../Pch/IncludePrivate/PchPolicyHob.h | 18 +++ 15 files changed, 426 insertions(+) create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/Library/PchResetCommonLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchHHsioAx.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchHHsioBx.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchHHsioDx.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchHsio.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchLbgHsioAx.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchLbgHsioBx.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchLbgHsioBxD.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchLbgHsioBxD_Ext.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchLbgHsioBx_Ext.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchLbgHsioSx.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchLbgHsioSx_Ext.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchLpHsioBx.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchLpHsioCx.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivat= e/PchPolicyHob.h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Libra= ry/PchResetCommonLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludeP= rivate/Library/PchResetCommonLib.h new file mode 100644 index 0000000000..a1d076c06c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Library/PchR= esetCommonLib.h @@ -0,0 +1,59 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_RESET_COMMON_LIB_H_ +#define _PCH_RESET_COMMON_LIB_H_ +#include +#include +/// +/// Private data structure definitions for the driver +/// +#define PCH_RESET_SIGNATURE SIGNATURE_32 ('I', 'E', 'R', 'S') + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + union { + PCH_RESET_PPI PchResetPpi; + PCH_RESET_PROTOCOL PchResetProtocol; + }PchResetInterface; + UINT32 PchPwrmBase; + UINT16 PchAcpiBase; + UINTN PchPmcBase; +} PCH_RESET_INSTANCE; + +// +// Function prototypes used by the Pch Reset ppi/protocol. +// +/** + Initialize an Pch Reset ppi/protocol instance. + + @param[in] PchResetInstance Pointer to PchResetInstance to initialize + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @exception EFI_UNSUPPORTED The PCH is not supported by this module +**/ +EFI_STATUS +PchResetConstructor ( + PCH_RESET_INSTANCE *PchResetInstance + ); + +/** + Execute Pch Reset from the host controller. + @param[in] PchResetInstance Pointer to PchResetInstance to initialize + @param[in] PchResetType Pch Reset Types which includes ColdReset= , WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalRese= tWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +EFI_STATUS +PchReset ( + IN PCH_RESET_INSTANCE *PchResetInstance, + IN PCH_RESET_TYPE PchResetType + ); +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHH= sioAx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsio= Ax.h new file mode 100644 index 0000000000..37adb642c6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioAx.h @@ -0,0 +1,16 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_H_HSIO_AX_H_ +#define _PCH_H_HSIO_AX_H_ + +#define PCH_H_HSIO_VER_AX 0x11 + +extern UINT8 PchHChipsetInitTable_Ax[1300]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchHHsio_Ax[136]; + +#endif //_PCH_H_HSIO_AX_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHH= sioBx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsio= Bx.h new file mode 100644 index 0000000000..abbe638ff7 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioBx.h @@ -0,0 +1,16 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_H_HSIO_BX_H_ +#define _PCH_H_HSIO_BX_H_ + +#define PCH_H_HSIO_VER_BX 0x3e + +extern UINT8 PchHChipsetInitTable_Bx[2060]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchHHsio_Bx[136]; + +#endif //_PCH_H_HSIO_BX_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHH= sioDx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsio= Dx.h new file mode 100644 index 0000000000..ea778f3855 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioDx.h @@ -0,0 +1,16 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_H_HSIO_DX_H_ +#define _PCH_H_HSIO_DX_H_ + +#define PCH_H_HSIO_VER_DX 0x34 + +extern UINT8 PchHChipsetInitTable_Dx[2180]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchHHsio_Dx[157]; + +#endif //_PCH_H_HSIO_DX_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHs= io.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHsio.h new file mode 100644 index 0000000000..584838fb83 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHsio.h @@ -0,0 +1,147 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_HSIO_H_ +#define _PCH_HSIO_H_ + +#define PCH_HSIO_SKU_SKL 0x01 + +#define PCH_LANE_OWN_COMMON 0x10 +#define PCH_LANE_BDCAST 0x11 + +#define PCH_HSIO_LANE_GROUP_NO 0x09 +#define PCH_HSIO_LANE_GROUP_COMMON_LANE 0x00 +#define PCH_HSIO_LANE_GROUP_PCIE 0x01 +#define PCH_HSIO_LANE_GROUP_DMI 0x02 +#define PCH_HSIO_LANE_GROUP_GBE 0x03 +#define PCH_HSIO_LANE_GROUP_USB3 0x04 +#define PCH_HSIO_LANE_GROUP_SATA 0x05 +#define PCH_HSIO_LANE_GROUP_SSIC 0x06 + +#define PCH_MODPHY0_LP_LOS1_LANE_START 0x00 +#define PCH_MODPHY0_LP_LOS1_LANE_END 0x05 +#define PCH_MODPHY1_LP_LOS1_LANE_START 0x06 +#define PCH_MODPHY1_LP_LOS1_LANE_END 0x07 +#define PCH_MODPHY1_LP_LOS2_LANE_START 0x00 +#define PCH_MODPHY1_LP_LOS2_LANE_END 0x01 +#define PCH_MODPHY2_LP_LOS2_LANE_START 0x02 +#define PCH_MODPHY2_LP_LOS2_LANE_END 0x07 + +#define PCH_MODPHY1_LOS1_LANE_START 0x00 +#define PCH_MODPHY1_LOS1_LANE_END 0x07 +#define PCH_MODPHY1_LOS2_LANE_START 0x00 +#define PCH_MODPHY1_LOS2_LANE_END 0x01 +#define PCH_MODPHY2_LOS2_LANE_START 0x02 +#define PCH_MODPHY2_LOS2_LANE_END 0x07 +#define PCH_MODPHY2_LOS3_LANE_START 0x00 +#define PCH_MODPHY2_LOS3_LANE_END 0x07 +#define PCH_MODPHY2_LOS4_LANE_START 0x00 +#define PCH_MODPHY2_LOS4_LANE_END 0x01 + +/** + PCH SBI HSIO table data structure +**/ +typedef struct { + UINT32 PortId; + UINT32 Value; + UINT16 Offset; + UINT8 LanePhyMode; +} PCH_SBI_HSIO_TABLE_STRUCT; + + +#define PMC_DATA_SBI_CMD_SIZE ((12/sizeof(UINT16))-1) +#define PMC_DATA_DELAY_CMD_SIZE ((4/sizeof(UINT16))-1) + +// Commands specified command table and processed by the PMC & it's HW acc= elerator +typedef enum { + SendSBIPosted =3D 0x0, // Perform a SBI Write & wait for result + SendSBINonPosted, // Perform a SBI Write & ignore return result (Not = Supported in HW) + DoDelay, // PMC Inserts Delay when command detected + EndStruct =3D 0x7 // No-op Command indicating end of list +} PHY_COMMANDS; + +/** +PCH HSIO PMC XRAM Header +**/ +typedef struct { + UINT16 Word0; + UINT16 Word1; + UINT16 Word2; + UINT16 Word3; + UINT16 Word4; + UINT16 Word5; + UINT16 Word6; + UINT16 Word7; + UINT16 Word8; + UINT16 Word9; + UINT16 Word10; + UINT16 Word11; + UINT16 Word12; + UINT16 Word13; + UINT16 Word14; + UINT16 Word15; +} PCH_SBI_HSIO_HDR_TBL; + +/** +PCH HSIO PMC XRAM Data +**/ +typedef struct { + UINT8 Command : 3; + UINT8 Size : 5; + UINT8 Pid; + UINT8 OpCode; //PrivateControlWrite + UINT8 Bar; //0 + UINT8 Fbe; //First Byte Enable : 0x0F + UINT8 Fid; //0 + UINT16 Offset; + UINT32 Value; +} PCH_SBI_HSIO_CMD_TBL; + +/** +PCH HSIO Delay XRAM Data +**/ +typedef struct { + UINT8 Command : 3; + UINT8 Size : 5; + UINT8 DelayPeriod; //(00h =3D 1us, 01h =3D 10us, 02h =3D 100us, ..., 07h= =3D 10s; others reserved) + UINT8 DelayCount; //(0 - 255); total delay =3D Delay period * Delay count + UINT8 Padding; +} PCH_DELAY_HSIO_CMD_TBL; + +typedef enum { + Delay1us =3D 0x0, + Delay10us, + Delay100us, + Delay1ms, + Delay10ms, + Delay100ms, + Delay1s, + Delay10s +} DELAY; + +/** +PCH PCIE PLL SSC Data +**/ +#define MAX_PCIE_PLL_SSC_PERCENT 20 + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#ifdef SKXD_EN +#include +#include +#endif // SKXD_EN + +#endif //_PCH_HSIO_H_ + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLb= gHsioAx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbg= HsioAx.h new file mode 100644 index 0000000000..5bd69194f8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioAx= .h @@ -0,0 +1,16 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_LBG_HSIO_AX_H_ +#define _PCH_LBG_HSIO_AX_H_ + +#define PCH_LBG_HSIO_VER_AX 0x19 + +extern UINT8 PchLbgChipsetInitTable_Ax[2988]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchLbgHsio_Ax[81]; + +#endif //_PCH_LBG_HSIO_AX_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLb= gHsioBx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbg= HsioBx.h new file mode 100644 index 0000000000..4cc1ff977d --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx= .h @@ -0,0 +1,17 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_LBG_HSIO_BX_H_ +#define _PCH_LBG_HSIO_BX_H_ + +#define PCH_LBG_HSIO_VER_BX 0x2f + +extern UINT8 PchLbgChipsetInitTable_Bx[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Bx_Ptr; +extern UINT16 PchLbgHsio_Bx_Size; + +#endif //_PCH_LBG_HSIO_BX_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLb= gHsioBxD.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLb= gHsioBxD.h new file mode 100644 index 0000000000..8ee7a664ec --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx= D.h @@ -0,0 +1,19 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifdef SKXD_EN +#ifndef _PCH_LBG_HSIO_BX_D_H_ +#define _PCH_LBG_HSIO_BX_D_H_ + +#define PCH_LBG_HSIO_VER_BX_D 0x2 + +extern UINT8 PchLbgChipsetInitTable_BxD[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_BxD_Ptr; +extern UINT16 PchLbgHsio_BxD_Size; + +#endif //_PCH_LBG_HSIO_BX_D_H_ +#endif // SKXD_EN diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLb= gHsioBxD_Ext.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/P= chLbgHsioBxD_Ext.h new file mode 100644 index 0000000000..4d13c2a1db --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx= D_Ext.h @@ -0,0 +1,19 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifdef SKXD_EN +#ifndef _PCH_LBG_HSIO_BX_D_EXT_H_ +#define _PCH_LBG_HSIO_BX_D_EXT_H_ + +#define PCH_LBG_HSIO_VER_BX_D_EXT 0x2 + +extern UINT8 PchLbgChipsetInitTable_BxD_Ext[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_BxD_Ext_Ptr; +extern UINT16 PchLbgHsio_BxD_Ext_Size; + +#endif //_PCH_LBG_HSIO_BX_D_EXT_H_ +#endif // SKXD_EN diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLb= gHsioBx_Ext.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Pc= hLbgHsioBx_Ext.h new file mode 100644 index 0000000000..4b228c6044 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx= _Ext.h @@ -0,0 +1,17 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_LBG_HSIO_BX_EXT_H_ +#define _PCH_LBG_HSIO_BX_EXT_H_ + +#define PCH_LBG_HSIO_VER_BX_EXT 0x2f + +extern UINT8 PchLbgChipsetInitTable_Bx_Ext[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Bx_Ext_Ptr; +extern UINT16 PchLbgHsio_Bx_Ext_Size; + +#endif //_PCH_LBG_HSIO_BX_EXT_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLb= gHsioSx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbg= HsioSx.h new file mode 100644 index 0000000000..3e3d10bd3e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx= .h @@ -0,0 +1,17 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_LBG_HSIO_SX_H_ +#define _PCH_LBG_HSIO_SX_H_ + +#define PCH_LBG_HSIO_VER_SX 0x8 + +extern UINT8 PchLbgChipsetInitTable_Sx[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Sx_Ptr; +extern UINT16 PchLbgHsio_Sx_Size; + +#endif //_PCH_LBG_HSIO_SX_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLb= gHsioSx_Ext.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Pc= hLbgHsioSx_Ext.h new file mode 100644 index 0000000000..616212f4b1 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx= _Ext.h @@ -0,0 +1,17 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_LBG_HSIO_SX_EXT_H_ +#define _PCH_LBG_HSIO_SX_EXT_H_ + +#define PCH_LBG_HSIO_VER_SX_EXT 0x8 + +extern UINT8 PchLbgChipsetInitTable_Sx_Ext[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Sx_Ext_Ptr; +extern UINT16 PchLbgHsio_Sx_Ext_Size; + +#endif //_PCH_LBG_HSIO_SX_EXT_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLp= HsioBx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHs= ioBx.h new file mode 100644 index 0000000000..774a0a09f5 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioBx.h @@ -0,0 +1,16 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_LP_HSIO_BX_H_ +#define _PCH_LP_HSIO_BX_H_ + +#define PCH_LP_HSIO_VER_BX 0x3e + +extern UINT8 PchLpChipsetInitTable_Bx[1492]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchLpHsio_Bx[109]; + +#endif //_PCH_LP_HSIO_BX_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLp= HsioCx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHs= ioCx.h new file mode 100644 index 0000000000..9740763098 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioCx.h @@ -0,0 +1,16 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_LP_HSIO_CX_H_ +#define _PCH_LP_HSIO_CX_H_ + +#define PCH_LP_HSIO_VER_CX 0x34 + +extern UINT8 PchLpChipsetInitTable_Cx[1548]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchLpHsio_Cx[120]; + +#endif //_PCH_LP_HSIO_CX_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchPo= licyHob.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchPol= icyHob.h new file mode 100644 index 0000000000..1fafaae47e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchPolicyHob= .h @@ -0,0 +1,18 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_POLICY_HOB_H_ +#define _PCH_POLICY_HOB_H_ + +#include + +typedef struct _PCH_POLICY PCH_POLICY_HOB; + +extern EFI_GUID gPchPolicyHobGuid; + +#endif // _PCH_POLICY_HOB_H_ + --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[66.175.222.108]) by mx.zohomail.com with SMTPS id 1620726534230576.7036149719676; Tue, 11 May 2021 02:48:54 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id la4KYY1788612xzYlJwZkwI9; Tue, 11 May 2021 02:48:53 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web08.10551.1620726526771786264 for ; Tue, 11 May 2021 02:48:47 -0700 IronPort-SDR: lcnhWXNsEsSv+ck9ISNRv37UouTeSl9pHffX/NQOBb3yOvO8rNjDikSmiWWcZhIXq0sHNpam5p GEf4VnbTdiPg== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="199469615" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="199469615" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:45 -0700 IronPort-SDR: 3KJigsazj4zXzuhSjOMucAdpPwT5b3FvoJY2prqKpHnSPv5IS6dZFwwQsk+xe4AtS4RquZfAC3 lNGhWwECf7cg== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436573942" X-Received: from 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Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726533; bh=YgP0MgVHb3kDRxZpMWmyybv51KcRftHUSp4THz5xYQ0=; h=Cc:Date:From:Reply-To:Subject:To; b=E4YoFi4+SCS7dd4JQVI7WXdzWL9D6YFe2vNUhn5apmuqYRlrxn5e2OtqlVFmeNDbOWk qMDFHZqasHIpjRQPcvLaAl/3riEAHMnCQfiqJT0tn84TGFa6x6QCId8L50zjjnJIbVjeu ECnaNVI0cgtcL3oRM7+oZbENCYktgOeCbT4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../DxeRuntimeResetSystemLib.inf | 63 + .../DxeRuntimeResetSystemLib/PchReset.c | 633 ++++ .../DxeRuntimeResetSystemLib/PchReset.h | 105 + .../Pch/Library/PeiDxeSmmGpioLib/GpioInit.c | 403 +++ .../Pch/Library/PeiDxeSmmGpioLib/GpioLib.c | 2738 +++++++++++++++++ .../Library/PeiDxeSmmGpioLib/GpioLibrary.h | 216 ++ .../Library/PeiDxeSmmGpioLib/GpioNativeLib.c | 448 +++ .../Library/PeiDxeSmmGpioLib/PchSklGpioData.c | 59 + .../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf | 48 + .../PchCycleDecodingLib.c | 1169 +++++++ .../PeiDxeSmmPchCycleDecodingLib.inf | 33 + .../Library/PeiDxeSmmPchGbeLib/PchGbeLib.c | 160 + .../PeiDxeSmmPchGbeLib/PeiDxeSmmPchGbeLib.inf | 37 + .../Library/PeiDxeSmmPchInfoLib/PchInfoLib.c | 505 +++ .../PeiDxeSmmPchInfoLib/PchInfoStrLib.c | 291 ++ .../PeiDxeSmmPchInfoLib.inf | 32 + .../Library/PeiDxeSmmPchP2sbLib/PchP2sbLib.c | 331 ++ .../PeiDxeSmmPchP2sbLib.inf | 30 + .../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c | 453 +++ .../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf | 31 + .../Library/PeiDxeSmmPchPmcLib/PchPmcLib.c | 153 + .../PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf | 31 + .../PchSbiAccessLib.c | 370 +++ .../PeiDxeSmmPchSbiAccessLib.inf | 31 + .../Library/PeiPchPolicyLib/PchPrintPolicy.c | 730 +++++ .../Library/PeiPchPolicyLib/PeiPchPolicyLib.c | 581 ++++ .../PeiPchPolicyLib/PeiPchPolicyLib.inf | 48 + .../PeiPchPolicyLib/PeiPchPolicyLibrary.h | 25 + .../Library/PeiPchPolicyLib/Rvp3PolicyLib.c | 205 ++ .../SmmSpiFlashCommonLib.inf | 50 + .../SmmSpiFlashCommonLib/SpiFlashCommon.c | 192 ++ .../SpiFlashCommonSmmLib.c | 53 + .../BasePchResetCommonLib.inf | 27 + .../BasePchResetCommonLib/PchResetCommon.c | 168 + 34 files changed, 10449 insertions(+) create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRu= ntimeResetSystemLib/DxeRuntimeResetSystemLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRu= ntimeResetSystemLib/PchReset.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRu= ntimeResetSystemLib/PchReset.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmGpioLib/GpioInit.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmGpioLib/GpioLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmGpioLib/GpioLibrary.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmGpioLib/GpioNativeLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmGpioLib/PchSklGpioData.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmGpioLib/PeiDxeSmmGpioLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchCycleDecodingLib/PchCycleDecodingLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchGbeLib/PchGbeLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchGbeLib/PeiDxeSmmPchGbeLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchInfoLib/PchInfoLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchInfoLib/PchInfoStrLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchInfoLib/PeiDxeSmmPchInfoLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchP2sbLib/PchP2sbLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchP2sbLib/PeiDxeSmmPchP2sbLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchPcrLib/PchPcrLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchPmcLib/PchPmcLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchSbiAccessLib/PchSbiAccessLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDx= eSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPc= hPolicyLib/PchPrintPolicy.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPc= hPolicyLib/PeiPchPolicyLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPc= hPolicyLib/PeiPchPolicyLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPc= hPolicyLib/PeiPchPolicyLibrary.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPc= hPolicyLib/Rvp3PolicyLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSp= iFlashCommonLib/SmmSpiFlashCommonLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSp= iFlashCommonLib/SpiFlashCommon.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSp= iFlashCommonLib/SpiFlashCommonSmmLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/LibraryPrivat= e/BasePchResetCommonLib/BasePchResetCommonLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/LibraryPrivat= e/BasePchResetCommonLib/PchResetCommon.c diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRuntimeRe= setSystemLib/DxeRuntimeResetSystemLib.inf b/Silicon/Intel/PurleyRefreshSili= conPkg/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf new file mode 100644 index 0000000000..01ca2c9e96 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRuntimeResetSyst= emLib/DxeRuntimeResetSystemLib.inf @@ -0,0 +1,63 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D DxeRuntimeResetSystemLib + FILE_GUID =3D 5602DBE0-2576-44CB-95FF-53D5A18C775F + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + LIBRARY_CLASS =3D ResetSystemLib + CONSTRUCTOR =3D InstallPchReset +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# + +[LibraryClasses] + IoLib + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + UefiDriverEntryPoint + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + UefiRuntimeLib + PchCycleDecodingLib + DxeServicesTableLib + PchResetCommonLib + HobLib + + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Sources] + PchReset.c + PchReset.h + + +[Protocols] + gPchResetCallbackProtocolGuid ## CONSUMES + +[Guids] + gEfiEventVirtualAddressChangeGuid + gEfiCapsuleVendorGuid + gPchPowerCycleResetGuid + gPchGlobalResetGuid + gPchGlobalResetWithEcGuid + gPchPolicyHobGuid + + +[Depex] + gEfiPciRootBridgeIoProtocolGuid AND # SERVER_BIOS_FLAG + TRUE \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRuntimeRe= setSystemLib/PchReset.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library= /DxeRuntimeResetSystemLib/PchReset.c new file mode 100644 index 0000000000..f34f98bcf0 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRuntimeResetSyst= emLib/PchReset.c @@ -0,0 +1,633 @@ +/** @file + +Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PchReset.h" + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_RESET_INSTANCE *mPchResetInstance; +STATIC UINT8 mDaysOfMonthInfo[12] =3D { 31, 28, 31, 30, 31, 30, 31, 31, 30= , 31, 30, 31 }; + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_RESET_DATA mPchPowerCycleReset =3D { + PCH_PLATFORM_SPECIFIC_RESET_STRING, + PCH_POWER_CYCLE_RESET_GUID +}; +GLOBAL_REMOVE_IF_UNREFERENCED PCH_RESET_DATA mPchGlobalReset =3D { + PCH_PLATFORM_SPECIFIC_RESET_STRING, + PCH_GLOBAL_RESET_GUID +}; +GLOBAL_REMOVE_IF_UNREFERENCED PCH_RESET_DATA mPchGlobalResetWithEc =3D { + PCH_PLATFORM_SPECIFIC_RESET_STRING, + PCH_GLOBAL_RESET_WITH_EC_GUID +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mCapsuleResetType =3D 0; + +/** + Check if it is leap year + + @param[in] Year year to be check + + @retval True year is leap year + @retval FALSE year is not a leap year +**/ +BOOLEAN +IsLeapYear ( + IN UINT16 Year + ) +{ + return (Year % 4 =3D=3D 0) && ((Year % 100 !=3D 0) || (Year % 400 =3D=3D= 0)); +} + +/** + Set System Wakeup Alarm. + + @param[in] WakeAfter Time offset in seconds to wake from S3 + + @retval EFI_SUCCESS Timer started successfully +**/ +STATIC +EFI_STATUS +SetSystemWakeupAlarm ( + IN UINT32 WakeAfter + ) +{ + EFI_STATUS Status; + EFI_TIME Time; + EFI_TIME_CAPABILITIES Capabilities; + UINT32 Reminder; + UINT16 ABase; + UINT8 DayOfMonth; + + /// + /// For an instant wake 2 seconds is a safe value + /// + if (WakeAfter < 2) { + WakeAfter =3D 2; + } + + Status =3D EfiGetTime (&Time, &Capabilities); + if (EFI_ERROR (Status)) { + return Status; + } + Reminder =3D WakeAfter + (UINT32) Time.Second; + Time.Second =3D Reminder % 60; + Reminder =3D Reminder / 60; + Reminder =3D Reminder + (UINT32) Time.Minute; + Time.Minute =3D Reminder % 60; + Reminder =3D Reminder / 60; + Reminder =3D Reminder + (UINT32) Time.Hour; + Time.Hour =3D Reminder % 24; + Reminder =3D Reminder / 24; + + if (Reminder > 0) { + Reminder =3D Reminder + (UINT32) Time.Day; + if ((Time.Month =3D=3D 2) && IsLeapYear (Time.Year)) { + DayOfMonth =3D 29; + } else { + DayOfMonth =3D mDaysOfMonthInfo[Time.Month - 1]; + } + if (Reminder > DayOfMonth) { + Time.Day =3D (UINT8)Reminder - DayOfMonth; + Reminder =3D 1; + } else { + Time.Day =3D (UINT8)Reminder; + Reminder =3D 0; + } + } + if (Reminder > 0) { + if (Time.Month =3D=3D 12) { + Time.Month =3D 1; + Time.Year =3D Time.Year + 1; + } else { + Time.Month =3D Time.Month + 1; + } + } + + Status =3D EfiSetWakeupTime (TRUE, &Time); + if (EFI_ERROR (Status)) { + return Status; + } + + ABase =3D mPchResetInstance->PchAcpiBase; + + + /// + /// Clear RTC PM1 status + /// + IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_RTC); + + /// + /// set RTC_EN bit in PM1_EN to wake up from the alarm + /// + IoWrite16 ( + ABase + R_PCH_ACPI_PM1_EN, + (IoRead16 (ABase + R_PCH_ACPI_PM1_EN) | B_PCH_ACPI_PM1_EN_RTC) + ); + return Status; +} + +/** + Retrieve PCH platform specific ResetData + + @param[in] Guid PCH platform specific reset GUID. + @param[out] DataSize The size of ResetData in bytes. + + @retval ResetData A platform specific reset that the exact type of + the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. + @retval NULL If Guid is not defined in PCH platform specific re= set. +**/ +VOID * +EFIAPI +GetResetData ( + IN EFI_GUID *Guid, + OUT UINTN *DataSize + ) +{ + *DataSize =3D 0; + if (CompareGuid (Guid, &gPchPowerCycleResetGuid)) { + *DataSize =3D sizeof (mPchPowerCycleReset); + return (VOID *)&mPchPowerCycleReset; + } else if (CompareGuid (Guid, &gPchGlobalResetGuid)) { + *DataSize =3D sizeof (mPchGlobalReset); + return (VOID *)&mPchGlobalReset; + } else if (CompareGuid (Guid, &gPchGlobalResetWithEcGuid)) { + *DataSize =3D sizeof (mPchGlobalResetWithEc); + return (VOID *)&mPchGlobalResetWithEc; + } + + return NULL; +} + +/** + Execute Pch Reset from the host controller. + + @param[in] This Pointer to the PCH_RESET_PROTOCOL instan= ce. + @param[in] ResetType UEFI defined reset type. + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a pla= tform specific reset. + The exact type of the reset is defined b= y the EFI_GUID that follows + the Null-terminated Unicode string. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +EFI_STATUS +EFIAPI +Reset ( + IN PCH_RESET_PROTOCOL *This, + IN EFI_RESET_TYPE ResetType, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + PCH_RESET_INSTANCE *PchResetInstance; + EFI_STATUS Status; + PCH_RESET_TYPE PchResetType; + + PchResetInstance =3D PCH_RESET_INSTANCE_FROM_THIS (This); + PchResetType =3D (PCH_RESET_TYPE)ResetType; + + Status =3D PchReset (PchResetInstance, PchResetType); + + return Status; +} + +/** + Calling this function causes a system-wide reset. This sets + all circuitry within the system to its initial state. This type of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + System reset should not return, if it returns, it means the system does + not support cold reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + PchReset (mPchResetInstance, (PCH_RESET_TYPE) EfiResetCold); +} + +/** + Calling this function causes a system-wide initialization. The processors + are set to their initial state, and pending cycles are not corrupted. + + System reset should not return, if it returns, it means the system does + not support warm reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + PchReset (mPchResetInstance, (PCH_RESET_TYPE) EfiResetWarm); +} + +/** + Calling this function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + System shutdown should not return, if it returns, it means the system do= es + not support shut down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + PchReset (mPchResetInstance, (PCH_RESET_TYPE) EfiResetShutdown); +} + +/** + Calling this function causes the system to enter a power state for platf= orm specific. + + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a pla= tform specific reset. + The exact type of the reset is defined b= y the EFI_GUID that follows + the Null-terminated Unicode string. + +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + EFI_GUID *GuidPtr; + + if (ResetData =3D=3D NULL) { + if (!EfiAtRuntime ()) { + DEBUG ((DEBUG_ERROR, "[DxeRuntimeResetSystemLib] ResetData is not av= ailable.\n")); + } + return; + } + GuidPtr =3D (EFI_GUID *) ((UINT8 *) ResetData + DataSize - sizeof (EFI_G= UID)); + if (CompareGuid (GuidPtr, &gPchPowerCycleResetGuid)) { + PchReset (mPchResetInstance, (PCH_RESET_TYPE) PowerCycleReset); + } else if (CompareGuid (GuidPtr, &gPchGlobalResetGuid)) { + PchReset (mPchResetInstance, (PCH_RESET_TYPE) GlobalReset); + } else if (CompareGuid (GuidPtr, &gPchGlobalResetWithEcGuid)) { + PchReset (mPchResetInstance, (PCH_RESET_TYPE) GlobalResetWithEc); + } else { + return; + } +} + +/** + Calling this function causes the system to enter a power state for capsu= le update. + + Reset update should not return, if it returns, it means the system does + not support capsule update. + +**/ +VOID +EFIAPI +EnterS3WithImmediateWake ( + VOID + ) +{ + PchReset (mPchResetInstance, (PCH_RESET_TYPE) EfiResetWarm); +} + +/** + The ResetSystem function resets the entire platform. + + @param[in] ResetType The type of reset to perform. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm,= or EfiResetShutdown + the data buffer starts with a Null-terminated = string, optionally + followed by additional binary data. The string= is a description + that the caller may use to further indicate th= e reason for the + system reset. +**/ +VOID +EFIAPI +ResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + switch (ResetType) { + case EfiResetWarm: + ResetWarm (); + break; + + case EfiResetCold: + ResetCold (); + break; + + case EfiResetShutdown: + ResetShutdown (); + return; + + case EfiResetPlatformSpecific: + ResetPlatformSpecific (DataSize, ResetData); + return; + + default: + return; + } +} + +/** + PchReset Runtime DXE Driver Entry Point\n + - Introduction\n + The PchReset Runtime DXE driver provide a standard way for other modul= es to + use the PCH Reset Interface in DXE/SMM/Runtime environments. It has no= longer + hooked ResetSystem() function of the runtime service table. + + - @pre + - If there is any driver which needs to run the callback function righ= t before + issuing the reset, PCH Reset Callback Protocol will need to be insta= lled + before PCH Reset Runtime DXE driver. If PchReset Runtime DXE driver = is run + before Status Code Runtime Protocol is installed and there is the ne= ed + to use Status code in the driver, it will be necessary to add EFI_ST= ATUS_CODE_RUNTIME_PROTOCOL_GUID + to the dependency file. + - @link _PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PROTOCOL @end= link + + - @result + The Reset driver produces @link _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL= @endlink + + @param[in] ImageHandle Image handle of the loaded driver + @param[in] SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the timer service +**/ +EFI_STATUS +EFIAPI +InstallPchReset ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT64 BaseAddress; + UINT64 Length; + UINT32 PwrmBaseAddress; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemorySpaceDescriptor; + UINT64 Attributes; + EFI_EVENT AddressChangeEvent; + EFI_PEI_HOB_POINTERS HobPtr; + PCH_POLICY_HOB *PchPolicyHob; + + DEBUG ((DEBUG_INFO, "InstallPchReset() Start\n")); + + // + // Set PMC PCI address space to RUNTIME MEMORY. + // + BaseAddress =3D MmPciBase( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + Length =3D 0x1000; // 4KB + + Status =3D gDS->GetMemorySpaceDescriptor (BaseAddress, &MemorySpaceDesc= riptor); + ASSERT_EFI_ERROR (Status); + + Attributes =3D MemorySpaceDescriptor.Attributes | EFI_MEMORY_RUNTIME; + + Status =3D gDS->SetMemorySpaceAttributes ( + BaseAddress, + Length, + Attributes + ); + ASSERT_EFI_ERROR (Status); + // + // Set PWRM MMIO address space to RUNTIME MEMORY. + // + PchPwrmBaseGet (&PwrmBaseAddress); + Length =3D 0x10000; // 64KB + + Status =3D gDS->GetMemorySpaceDescriptor (PwrmBaseAddress, &MemorySpace= Descriptor); + ASSERT_EFI_ERROR (Status); + + Attributes =3D MemorySpaceDescriptor.Attributes | EFI_MEMORY_RUNTIME; + + Status =3D gDS->SetMemorySpaceAttributes ( + PwrmBaseAddress, + Length, + Attributes + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Allocate Runtime memory for the PchReset protocol instance. + /// + mPchResetInstance =3D AllocateRuntimeZeroPool (sizeof (PCH_RESET_INSTANC= E)); + if (mPchResetInstance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status =3D PchResetConstructor (mPchResetInstance); + + /// + /// Create Address Change event + /// + /// + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + PchResetVirtualAddressChangeEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &AddressChangeEvent + ); + ASSERT_EFI_ERROR (Status); + + HobPtr.Guid =3D GetFirstGuidHob (&gPchPolicyHobGuid); + if (HobPtr.Guid !=3D NULL) { + PchPolicyHob =3D GET_GUID_HOB_DATA (HobPtr.Guid); + mCapsuleResetType =3D PchPolicyHob->PmConfig.CapsuleResetType; + } + /// + /// The Lib Deconstruct will automatically be called when entrypoint ret= urn error. + /// + DEBUG ((DEBUG_INFO, "InstallPchReset() End\n")); + + return Status; +} + +/** + If need be, do any special reset required for capsules. For this + implementation where we're called from the ResetSystem() api, + just set our capsule variable and return to let the caller + do a soft reset. +**/ +VOID +CapsuleS3Reset ( + VOID + ) +{ + UINT32 Data32; + UINT32 Eflags; + UINT16 ABase; + + DEBUG ((DEBUG_INFO, "Capsule Present: Will be issuing S3 reset.\n")); + + /// + /// Wake up system 2 seconds after putting system into S3 to complete th= e reset operation. + /// + SetSystemWakeupAlarm (2); + /// + /// Process capsules across a system reset. + /// + ABase =3D mPchResetInstance->PchAcpiBase; + ASSERT (ABase !=3D 0); + + Data32 =3D IoRead32 ((UINTN) (ABase + R_PCH_ACPI_PM1_CNT)); + + Data32 =3D (UINT32) ((Data32 & ~(B_PCH_ACPI_PM1_CNT_SLP_TYP + B_PCH_ACP= I_PM1_CNT_SLP_EN)) | V_PCH_ACPI_PM1_CNT_S3); + + Eflags =3D (UINT32) AsmReadEflags (); + + if ((Eflags & 0x200)) { + DisableInterrupts (); + } + + AsmWbinvd (); + AsmWriteCr0 (AsmReadCr0 () | 0x060000000); + + IoWrite32 ( + (UINTN) (ABase + R_PCH_ACPI_PM1_CNT), + (UINT32) Data32 + ); + + Data32 =3D Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN; + + IoWrite32 ( + (UINTN) (ABase + R_PCH_ACPI_PM1_CNT), + (UINT32) Data32 + ); + + if ((Eflags & 0x200)) { + EnableInterrupts (); + } + /// + /// Should not return + /// + CpuDeadLoop (); +} + +/** + Execute call back function for Pch Reset. + + @param[in] PchResetType Pch Reset Types which includes PowerCycl= e, Globalreset. + + @retval EFI_SUCCESS The callback function has been done succ= essfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback protoc= ol. Or, none of + callback protocol is installed. + @retval Others Do not do any reset from PCH +**/ +EFI_STATUS +EFIAPI +PchResetCallback ( + IN PCH_RESET_TYPE PchResetType + ) +{ + EFI_STATUS Status; + UINTN NumHandles; + EFI_HANDLE *HandleBuffer; + UINTN Index; + PCH_RESET_CALLBACK_PROTOCOL *PchResetCallback; + UINTN Size; + UINTN CapsuleDataPtr; + + if (EfiAtRuntime () =3D=3D FALSE) { + DEBUG((DEBUG_ERROR, "Not in Runtime")); + /// + /// Retrieve all instances of Pch Reset Callback protocol + /// + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gPchResetCallbackProtocolGuid, + NULL, + &NumHandles, + &HandleBuffer + ); + + if (EFI_ERROR (Status)) { + /// + /// Those drivers that need to install Pch Reset Callback protocol h= ave the responsibility + /// to make sure themselves execute before Pch Reset Runtime driver. + /// + if (Status =3D=3D EFI_NOT_FOUND) { + DEBUG ((DEBUG_ERROR | DEBUG_INFO, "Or, none of Pch Reset callback = protocol is installed.\n")); + } + + return Status; + } + + for (Index =3D 0; Index < NumHandles; Index++) { + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + &gPchResetCallbackProtocolGuid, + (VOID **) &PchResetCallback + ); + ASSERT_EFI_ERROR (Status); + + if (!EFI_ERROR (Status)) { + DEBUG((EFI_D_ERROR, "Calling PchResetCallback %d\n", Index)); + PchResetCallback->ResetCallback (PchResetType); + } else { + DEBUG ((DEBUG_ERROR | DEBUG_INFO, "Failed to locate Pch Reset Call= back protocol.\n")); + return Status; + } + } + } + DEBUG((EFI_D_ERROR, "PchResetCallback After Runtime Check\n")); + if(PchResetType =3D=3D WarmReset) { + /// + /// Check if there are pending capsules to process + /// + DEBUG((EFI_D_ERROR, "PchResetCallback Warmreset\n")); + Size =3D sizeof (CapsuleDataPtr); + Status =3D EfiGetVariable ( + EFI_CAPSULE_VARIABLE_NAME, + &gEfiCapsuleVendorGuid, + NULL, + &Size, + (VOID *) &CapsuleDataPtr + ); + if (Status =3D=3D EFI_SUCCESS) { + if (mCapsuleResetType =3D=3D CAPSULE_RESET_S3) { //default value S3 = resume + CapsuleS3Reset (); + } + AsmWbinvd (); + } + } + return EFI_SUCCESS; +} + +/** + Fixup internal data pointers so that the services can be called in virtu= al mode. + + @param[in] Event The event registered. + @param[in] Context Event context. Not used in this event ha= ndler. + +**/ +VOID +EFIAPI +PchResetVirtualAddressChangeEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mPchResetInstance-= >PchPmcBase)); + gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mPchResetInstance-= >PchPwrmBase)); + gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mPchResetInstance)= ); +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRuntimeRe= setSystemLib/PchReset.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library= /DxeRuntimeResetSystemLib/PchReset.h new file mode 100644 index 0000000000..742ca70498 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRuntimeResetSyst= emLib/PchReset.h @@ -0,0 +1,105 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCH_RESET_H +#define _PCH_RESET_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EFI_INTERNAL_POINTER 0x04 + +#define PCH_RESET_INSTANCE_FROM_THIS(a) \ + CR ( \ + a, \ + PCH_RESET_INSTANCE, \ + PchResetInterface.PchResetProtocol, \ + PCH_RESET_SIGNATURE \ + ) + +#define CAPSULE_RESET_S3 0 +#define CAPSULE_RESET_WARM 1 + +/** + PchReset Runtime DXE Driver Entry Point\n + - Introduction\n + The PchReset Runtime DXE driver provide a standard way for other modul= es to + use the PCH Reset Interface in DXE/SMM/Runtime environments. It has no= longer + hooked ResetSystem() function of the runtime service table. + + - @pre + - If there is any driver which needs to run the callback function righ= t before + issuing the reset, PCH Reset Callback Protocol will need to be install= ed + before PCH Reset Runtime DXE driver. If PchReset Runtime DXE driver is= run + before Status Code Runtime Protocol is installed and there is the need + to use Status code in the driver, it will be necessary to add EFI_STAT= US_CODE_RUNTIME_PROTOCOL_GUID + to the dependency file. + - @link _PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PROTOCOL @end= link + + - @result + The Reset driver produces @link _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL= @endlink + + @param[in] ImageHandle Image handle of the loaded driver + @param[in] SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the timer service +**/ +EFI_STATUS +EFIAPI +InstallPchReset ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + Execute call back function for Pch Reset. + + @param[in] PchResetType Pch Reset Types which includes PowerCycl= e, Globalreset. + + @retval EFI_SUCCESS The callback function has been done succ= essfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback protoc= ol. Or, none of + callback protocol is installed. + @retval Others Do not do any reset from PCH +**/ +EFI_STATUS +EFIAPI +PchResetCallback ( + IN PCH_RESET_TYPE PchResetType + ); + +/** + Fixup internal data pointers so that the services can be called in virtu= al mode. + + @param[in] Event The event registered. + @param[in] Context Event context. Not used in this event ha= ndler. + +**/ +VOID +EFIAPI +PchResetVirtualAddressChangeEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ); +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpi= oLib/GpioInit.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeS= mmGpioLib/GpioInit.c new file mode 100644 index 0000000000..89f601736a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/Gp= ioInit.c @@ -0,0 +1,403 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "GpioLibrary.h" + + +/** + This procedure will handle requirement on SATA DEVSLPx pins. + + @param[in] GpioPad GPIO pad + @param[in] PadMode GPIO PadMode value + @param[in out] Dw0Reg Value for PADCFG_DW0 register + @param[in out] Dw0RegMask Mask of bits which will change in PADCFG_D= WO register + + @retval None + +**/ +static +VOID +GpioHandleSataDevSlpPad ( + IN GPIO_PAD GpioPad, + IN UINT32 PadMode, + IN OUT UINT32 *Dw0Reg, + IN OUT UINT32 *Dw0RegMask + ) +{ + // + // For SATA DEVSLPx pins if used in native 1 mode then ensure that PadRs= tCfg + // is set to "00" - Powergood + // + if (GpioIsPadASataDevSlpPin (GpioPad, PadMode)) { + // + // Set PadRstCfg to Powergood + // + *Dw0RegMask |=3D B_PCH_GPIO_RST_CONF; + *Dw0Reg |=3D ((GpioResetPwrGood >> 1) << N_PCH_GPIO_RST_CONF); + } +} + +/** + This SKL PCH specific procedure will initialize multiple SKL PCH GPIO pi= ns + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +static +EFI_STATUS +GpioConfigureSklPch ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ) +{ + UINT32 Index; + UINT32 Dw0Reg; + UINT32 Dw0RegMask; + UINT32 Dw1Reg; + UINT32 Dw1RegMask; + UINT32 PadCfgReg; + UINT32 HostSoftOwnReg[V_PCH_GPIO_GROUP_MAX]; + UINT32 HostSoftOwnRegMask[V_PCH_GPIO_GROUP_MAX]; + UINT32 GpiGpeEnReg[V_PCH_GPIO_GROUP_MAX]; + UINT32 GpiGpeEnRegMask[V_PCH_GPIO_GROUP_MAX]; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + GPIO_GROUP GpioGroupOffset; + UINT32 NumberOfGroups; + GPIO_PAD_OWN PadOwnVal; + GPIO_INIT_CONFIG *GpioData; + GPIO_GROUP Group; + UINT32 GroupIndex; + UINT32 PadNumber; + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + PadOwnVal =3D GpioPadOwnHost; + + ZeroMem (HostSoftOwnReg, sizeof (HostSoftOwnReg)); + ZeroMem (HostSoftOwnRegMask, sizeof (HostSoftOwnRegMask)); + ZeroMem (GpiGpeEnReg, sizeof (GpiGpeEnReg)); + ZeroMem (GpiGpeEnRegMask, sizeof (GpiGpeEnRegMask)); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GpioGroupOffset =3D GpioGetLowestGroup (); + NumberOfGroups =3D GpioGetNumberOfGroups (); + + for (Index =3D 0; Index < NumberOfItems; Index ++) { + + Dw0RegMask =3D 0; + Dw0Reg =3D 0; + Dw1RegMask =3D 0; + Dw1Reg =3D 0; + + GpioData =3D &GpioInitTableAddress[Index]; + + Group =3D GpioGetGroupFromGpioPad (GpioData->GpioPad); + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioData->GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioData->GpioPad); + + if (GroupIndex >=3D V_PCH_GPIO_GROUP_MAX) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Invalid Group Index (GroupIndex=3D= %d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + continue; + } + +DEBUG_CODE_BEGIN(); + if (!(((PchSeries =3D=3D PchH) && (GPIO_GET_CHIPSET_ID(GpioData->GpioP= ad) =3D=3D GPIO_SKL_H_CHIPSET_ID)) || + ((PchSeries =3D=3D PchLp) && (GPIO_GET_CHIPSET_ID(GpioData->GpioPa= d) =3D=3D GPIO_SKL_LP_CHIPSET_ID)))) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on t= his chipset (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGroupOffset) || (Group >=3D NumberOfGroups + GpioGrou= pOffset)) { + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup){ + return EFI_INVALID_PARAMETER; + } + + if (GpioIsPadLocked (GroupIndex, PadNumber)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pad is locked (Group=3D%d, Pad=3D%= d)!\n", GroupIndex, PadNumber)); + continue; + } + + if (DebugCodeEnabled ()) { + + // + // Check if selected GPIO Pad is not owned by CSME/ISH + // + GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal); + + if (PadOwnVal !=3D GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (G= roup=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + DEBUG ((DEBUG_ERROR, "** Please make sure the GPIO usage in sync bet= ween CSME and BIOS configuration. \n")); + DEBUG ((DEBUG_ERROR, "** All the GPIO occupied by CSME should not do= any configuration by BIOS.\n")); + continue; + } + + } + + // + // Configure Reset Type (PadRstCfg) + // + Dw0RegMask |=3D ((((GpioData->GpioConfig.PowerConfig & GPIO_CONF_RESET= _MASK) >> GPIO_CONF_RESET_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_PC= H_GPIO_RST_CONF); + Dw0Reg |=3D (((GpioData->GpioConfig.PowerConfig & GPIO_CONF_RESET_MASK= ) >> (GPIO_CONF_RESET_BIT_POS + 1)) << N_PCH_GPIO_RST_CONF); + + // + // Configure how interrupt is triggered (RxEvCfg) + // + Dw0RegMask |=3D ((((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_I= NT_TRIG_MASK) >> GPIO_CONF_INT_TRIG_BIT_POS) =3D=3D GpioHardwareDefault) ? = 0x0 : B_PCH_GPIO_RX_LVL_EDG); + Dw0Reg |=3D (((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_INT_TR= IG_MASK) >> (GPIO_CONF_INT_TRIG_BIT_POS + 1)) << N_PCH_GPIO_RX_LVL_EDG); + + + // + // Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI) + // + Dw0RegMask |=3D ((((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_I= NT_ROUTE_MASK) >> GPIO_CONF_INT_ROUTE_BIT_POS) =3D=3D GpioHardwareDefault) = ? 0x0 : (B_PCH_GPIO_RX_NMI_ROUTE | B_PCH_GPIO_RX_SCI_ROUTE | B_PCH_GPIO_RX= _SMI_ROUTE | B_PCH_GPIO_RX_APIC_ROUTE)); + Dw0Reg |=3D (((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_INT_RO= UTE_MASK) >> (GPIO_CONF_INT_ROUTE_BIT_POS + 1)) << N_PCH_GPIO_RX_NMI_ROUTE); + + // + // Configure GPIO direction (GPIORxDis and GPIOTxDis) + // + Dw0RegMask |=3D ((((GpioData->GpioConfig.Direction & GPIO_CONF_DIR_MAS= K) >> GPIO_CONF_DIR_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : (B_PCH_GPI= O_RXDIS | B_PCH_GPIO_TXDIS)); + Dw0Reg |=3D (((GpioData->GpioConfig.Direction & GPIO_CONF_DIR_MASK) >>= (GPIO_CONF_DIR_BIT_POS + 1)) << N_PCH_GPIO_TXDIS); + + // + // Configure GPIO input inversion (RXINV) + // + Dw0RegMask |=3D ((((GpioData->GpioConfig.Direction & GPIO_CONF_INV_MAS= K) >> GPIO_CONF_INV_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_PCH_GPI= O_RXINV); + Dw0Reg |=3D (((GpioData->GpioConfig.Direction & GPIO_CONF_INV_MASK) >>= (GPIO_CONF_INV_BIT_POS + 1)) << N_PCH_GPIO_RXINV); + + // + // Configure GPIO output state (GPIOTxState) + // + Dw0RegMask |=3D ((((GpioData->GpioConfig.OutputState & GPIO_CONF_OUTPU= T_MASK) >> GPIO_CONF_OUTPUT_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_= PCH_GPIO_TX_STATE); + Dw0Reg |=3D (((GpioData->GpioConfig.OutputState & GPIO_CONF_OUTPUT_MAS= K) >> (GPIO_CONF_OUTPUT_BIT_POS + 1)) << N_PCH_GPIO_TX_STATE); + + // + // Configure GPIO RX raw override to '1' (RXRAW1) + // + Dw0RegMask |=3D ((((GpioData->GpioConfig.OtherSettings & GPIO_CONF_RXR= AW_MASK) >> GPIO_CONF_RXRAW_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_= PCH_GPIO_RX_RAW1); + Dw0Reg |=3D (((GpioData->GpioConfig.OtherSettings & GPIO_CONF_RXRAW_MA= SK) >> (GPIO_CONF_RXRAW_BIT_POS + 1)) << N_PCH_GPIO_RX_RAW1); + + // + // Configure GPIO Pad Mode (PMode) + // + if (((GpioData->GpioPad =3D=3D GPIO_SKL_H_GPP_B2) || + (GpioData->GpioPad =3D=3D GPIO_SKL_H_GPD7) || + (GpioData->GpioPad =3D=3D GPIO_SKL_H_GPD9)) && + (GpioData->GpioConfig.PadMode !=3D GpioPadModeGpio)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group/Index: %d/%d, Pad: %d cannot= be set as NATIVE. Force it to GPIO mode!\n", Group, GroupIndex, PadNumber)= ); + Dw0RegMask |=3D B_PCH_GPIO_PAD_MODE; + Dw0Reg |=3D ((GpioPadModeGpio >> (GPIO_CONF_PAD_MODE_BIT_POS + 1)) <= < N_PCH_GPIO_PAD_MODE); + } else { + Dw0RegMask |=3D ((((GpioData->GpioConfig.PadMode & GPIO_CONF_PAD_MOD= E_MASK) >> GPIO_CONF_PAD_MODE_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : = B_PCH_GPIO_PAD_MODE); + Dw0Reg |=3D (((GpioData->GpioConfig.PadMode & GPIO_CONF_PAD_MODE_MAS= K) >> (GPIO_CONF_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE); + } + + // + // Configure GPIO termination (Term) + // + Dw1RegMask |=3D ((((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_= TERM_MASK) >> GPIO_CONF_TERM_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B= _PCH_GPIO_TERM); + Dw1Reg |=3D (((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_TERM_= MASK) >> (GPIO_CONF_TERM_BIT_POS + 1)) << N_PCH_GPIO_TERM); + + // + // Configure GPIO pad tolerance (padtol) + // + Dw1RegMask |=3D ((((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_= PADTOL_MASK) >> GPIO_CONF_PADTOL_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0= : B_PCH_GPIO_PADTOL); + Dw1Reg |=3D (((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_PADTO= L_MASK) >> (GPIO_CONF_PADTOL_BIT_POS + 1)) << N_PCH_GPIO_PADTOL); + + // + // Check for additional requirements on setting PADCFG register + // + GpioHandleSataDevSlpPad (GpioData->GpioPad, GpioData->GpioConfig.PadMo= de, &Dw0Reg, &Dw0RegMask); + + // + // Create PADCFG register offset using group and pad number + // + PadCfgReg =3D 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + + // + // Write PADCFG DW0 register + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgR= eg), + ~(UINT32)Dw0RegMask, + (UINT32)Dw0Reg + ); + + // + // Write PADCFG DW1 register + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgR= eg + 0x4), + ~(UINT32)Dw1RegMask, + (UINT32)Dw1Reg + ); + // + // Update value to be programmed in HOSTSW_OWN register + // + HostSoftOwnRegMask[GroupIndex] |=3D (GpioData->GpioConfig.HostSoftPadO= wn & 0x1) << PadNumber; + HostSoftOwnReg[GroupIndex] |=3D (GpioData->GpioConfig.HostSoftPadOwn >= > 0x1) << PadNumber; + + // + // Update value to be programmed in GPI_GPE_EN register + // + GpiGpeEnRegMask[GroupIndex] |=3D (GpioData->GpioConfig.InterruptConfig= & 0x1) << PadNumber; + GpiGpeEnReg[GroupIndex] |=3D ((GpioData->GpioConfig.InterruptConfig & = GpioIntSci) >> 3) << PadNumber; + } + + for (Index =3D 0; Index < NumberOfGroups; Index++) { + // + // Write HOSTSW_OWN registers + // + if (GpioGroupInfo[Index].HostOwnOffset !=3D NO_REGISTER_FOR_PROPERTY) { + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[Index].Community, GpioGroupI= nfo[Index].HostOwnOffset), + ~(UINT32)HostSoftOwnRegMask[Index], + (UINT32)HostSoftOwnReg[Index] + ); + } + + // + // Write GPI_GPE_EN registers + // + if (GpioGroupInfo[Index].GpiGpeEnOffset !=3D NO_REGISTER_FOR_PROPERTY)= { + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[Index].Community, GpioGroupI= nfo[Index].GpiGpeEnOffset), + ~(UINT32)GpiGpeEnRegMask[Index], + (UINT32)GpiGpeEnReg[Index] + ); + } + } + + return EFI_SUCCESS; +} + +/** + This procedure will clear all status bits of any GPIO interrupts. + + @param[in] none + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +static +EFI_STATUS +GpioClearAllGpioInterrupts ( + VOID + ) +{ + GPIO_GROUP Group; + GPIO_GROUP_INFO *GpioGroupInfo; + GPIO_GROUP GpioGroupLowest; + GPIO_GROUP GpioGroupHighest; + UINT32 GroupIndex; + UINTN GpioGroupInfoLength; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GpioGroupLowest =3D GpioGetLowestGroup (); + GpioGroupHighest =3D GpioGetHighestGroup (); + + for (Group =3D GpioGroupLowest; Group <=3D GpioGroupHighest; Group++) { + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + // + // Check if group has GPI IS register + // + if (GpioGroupInfo[Group].GpiIsOffset !=3D NO_REGISTER_FOR_PROPERTY) { + // + // Clear all GPI_IS Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInf= o[GroupIndex].GpiIsOffset), + (UINT32)0xFFFFFFFF + ); + } + + // + // Check if group has GPI_GPE_STS register + // + if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset !=3D NO_REGISTER_FOR_PRO= PERTY) { + // + // Clear all GPI_GPE_STS Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInf= o[GroupIndex].GpiGpeStsOffset), + (UINT32)0xFFFFFFFF + ); + } + + // + // Check if group has SMI_STS register + // + if (GpioGroupInfo[GroupIndex].SmiStsOffset !=3D NO_REGISTER_FOR_PROPER= TY) { + // + // Clear all SMI_STS Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInf= o[GroupIndex].SmiStsOffset), + (UINT32)0xFFFFFFFF + ); + } + + // + // Check if group has NMI_STS register + // + if (GpioGroupInfo[GroupIndex].NmiStsOffset !=3D NO_REGISTER_FOR_PROPER= TY) { + // + // Clear all NMI_STS Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInf= o[GroupIndex].NmiStsOffset), + (UINT32)0xFFFFFFFF + ); + } + + } + return EFI_SUCCESS; +} + +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG = structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware def= ault values. + Separate fields could be set to hardware default if it does not matter, = except + GpioPad and PadMode. + Some GpioPads are configured and switched to native mode by RC, those in= clude: + SerialIo pins, ISH pins, ClkReq Pins + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ) +{ + EFI_STATUS Status; + Status =3D GpioConfigureSklPch (NumberOfItems, GpioInitTableAddress); + GpioClearAllGpioInterrupts (); + return Status; +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpi= oLib/GpioLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSm= mGpioLib/GpioLib.c new file mode 100644 index 0000000000..d94ff8a693 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/Gp= ioLib.c @@ -0,0 +1,2738 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "GpioLibrary.h" +#include +#include +#include + +// +// Possible registers to be accessed using GpioReadWriteReg() function +// +typedef enum { + GpioHostOwnershipRegister =3D 0, + GpioGpeEnableRegister, + GpioSmiEnableRegister, + GpioNmiEnableRegister, + GpioPadConfigLockRegister, + GpioPadLockOutputRegister +} GPIO_REG; + +/** + This procedure will write or read GPIO Pad Configuration register + + @param[in] GpioPad GPIO pad + @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1 + @param[in] Mask Mask + @param[in] Write Perform read(0) or write(1) + @param[in,out] ReadWriteValue Read/Write data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number + @retval EFI_UNSUPPORTED Host cannot access this pad +**/ +static +EFI_STATUS +GpioReadWritePadCfgReg ( + IN GPIO_PAD GpioPad, + IN UINT8 DwReg, + IN UINT32 Mask, + IN BOOLEAN Write, + IN OUT UINT32 *ReadWriteVal + ) +{ + UINT32 PadCfgReg; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 GroupIndex; + UINT32 PadNumber; + + + GPIO_PAD_OWN PadOwnVal; + + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on thi= s chipset (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >=3D GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO gro= up range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible ran= ge for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + + if (Write && (DwReg =3D=3D 1 || (Mask & ~B_PCH_GPIO_TX_STATE) !=3D 0) &&= GpioIsPadLocked (GroupIndex, PadNumber)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pad is locked (Group=3D%d, Pad=3D%d)= !\n", GroupIndex, PadNumber)); + return EFI_WRITE_PROTECTED; + } + +DEBUG_CODE_BEGIN(); + // + // Check if selected GPIO Pad is not owned by CSME/ISH + // If GPIO is not owned by Host all access to PadCfg will be dropped + // + GpioGetPadOwnership (GpioPad, &PadOwnVal); + if (PadOwnVal !=3D GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Gro= up=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } + + // +DEBUG_CODE_END(); + + // + // Create Pad Configuration register offset + // + PadCfgReg =3D 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + if(DwReg =3D=3D 1) { + PadCfgReg +=3D 0x4; + } + + if (Write) { + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgR= eg), + (UINT32)(~Mask), + (UINT32)(*ReadWriteVal & Mask) + ); + } else { + *ReadWriteVal =3D MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupInde= x].Community, PadCfgReg)); + *ReadWriteVal &=3D Mask; + } + + return EFI_SUCCESS; +} + +/** + This procedure will write or read GPIO register + + @param[in] RegType GPIO register type + @param[in] Group GPIO group + @param[in] DwNum Register number for current group (param= eter applicable in accessing whole register). + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] GpioPad GPIO pad + @param[in] Write Perform read(0) or write(1) + @param[in] OnePad Access whole register(0) or one pad(1) + @param[in,out] ReadWriteValue Read/Write data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group, pad or DwNum parameter nu= mber +**/ +static +EFI_STATUS +GpioReadWriteReg ( + IN GPIO_REG RegType, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN GPIO_PAD GpioPad, + IN BOOLEAN Write, + IN BOOLEAN OnePad, + IN OUT UINT32 *ReadWriteVal + ) +{ + UINT32 Mask; + UINT32 RegOffset; + UINT32 GroupIndex; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + RegOffset =3D 0; + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + if (OnePad) { + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on t= his chipset (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + } else { + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + PadNumber =3D 0; + } + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >=3D GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO gro= up range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + switch (RegType) { + case GpioHostOwnershipRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].HostOwnOffset; + break; + case GpioGpeEnableRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].GpiGpeEnOffset; + break; + case GpioSmiEnableRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].SmiEnOffset; + break; + case GpioNmiEnableRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].NmiEnOffset; + break; + case GpioPadConfigLockRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].PadCfgLockOffset; + break; + case GpioPadLockOutputRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].PadCfgLockTxOffset; + break; + default: + ASSERT (FALSE); + break; + } + + // + // Check if selected register exists + // + if (RegOffset =3D=3D NO_REGISTER_FOR_PROPERTY) { + return EFI_INVALID_PARAMETER; + } + + // + // Access one GPIO Pad + // + if (OnePad) { + // + // Check if legal pin number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup){ + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible r= ange for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + // + // For future use. If there are more then 32 pads per group then certa= in + // group information would be split into more then one DWord register. + // + RegOffset +=3D (PadNumber >> 5) * 0x4; + // + // Calculate pad bit position within DWord register + // + PadNumber %=3D 32; + Mask =3D BIT0 << PadNumber; + + if (Write) { + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, RegOf= fset), + (UINT32)(~Mask), + (UINT32)((*ReadWriteVal << PadNumber) & Mask) + ); + } else { + *ReadWriteVal =3D MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIn= dex].Community, RegOffset)); + *ReadWriteVal =3D (*ReadWriteVal & Mask) >> PadNumber; + } + // + // Access whole register + // + } else { + // + // Check if DwNum argument does not exceed number of DWord registers + // resulting from available pads for certain group + // + if (DwNum > ((GpioGroupInfo[GroupIndex].PadPerGroup - 1) >> 5)){ + return EFI_INVALID_PARAMETER; + } + // + // For future use. If there are more then 32 pads per group then certa= in + // group information would be split into more then one DWord register. + // For SKL PCH DwNum must be 0. + // + RegOffset +=3D DwNum *0x4; + + if (Write) { + MmioWrite32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, RegOf= fset), + (UINT32)(*ReadWriteVal) + ); + } else { + *ReadWriteVal =3D MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIn= dex].Community, RegOffset)); + } + } + + return EFI_SUCCESS; +} + +/** + This procedure will write GPIO Lock/LockTx register using SBI. + + @param[in] RegType GPIO register (Lock or LockTx) + @param[in] Unlock Lock pads(0) or unlock(1) + @param[in] Group GPIO group number + @param[in] DwNum Register number for current group (param= eter applicable in accessing whole register). + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToModify Bit mask for pads that are going to be m= odified + @param[in] GpioPad GPIO pad + @param[in] OnePad Access whole register(0) or one pad(1) + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group, pad or DwNum parameter nu= mber +**/ +static +EFI_STATUS +GpioLockPadsUsingSbi ( + IN GPIO_REG RegType, + IN BOOLEAN Unlock, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToModify, + IN GPIO_PAD GpioPad, + IN BOOLEAN OnePad + ) +{ + UINT8 Response; + EFI_STATUS Status; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 RegOffset; + UINT32 OldPadCfgLockRegVal; + UINT32 NewPadCfgLockRegVal; + UINT32 GroupIndex; + UINT32 PadNumber; + + RegOffset =3D 0; + OldPadCfgLockRegVal =3D 0; + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + if (OnePad) { + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + Group =3D GpioGetGroupFromGpioPad (GpioPad); +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on t= his chipset (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + } else { + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + PadNumber =3D 0; + } + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >=3D GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO gro= up range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + switch (RegType) { + case GpioPadConfigLockRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].PadCfgLockOffset; + break; + case GpioPadLockOutputRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].PadCfgLockTxOffset; + break; + default: + ASSERT (FALSE); + break; + } + + // + // Check if selected register exists + // + if (RegOffset =3D=3D NO_REGISTER_FOR_PROPERTY) { + return EFI_INVALID_PARAMETER; + } + + // + // Access one GPIO Pad + // + if (OnePad) { + // + // Check if legal pin number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup){ + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible r= ange for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + + // + // For future use. If there are more then 32 pads per group then certa= in + // group information would be split into more then one DWord register. + // + DwNum =3D (PadNumber >> 5); + RegOffset +=3D DwNum * 0x4; + // + // Calculate pad bit position within DWord register + // + PadNumber %=3D 32; + + switch (RegType) { + case GpioPadConfigLockRegister: + GpioGetPadCfgLockForGroupDw (Group, DwNum, &OldPadCfgLockRegVal); + break; + case GpioPadLockOutputRegister: + GpioGetPadCfgLockTxForGroupDw (Group, DwNum, &OldPadCfgLockRegVal); + break; + } + if (Unlock) { + NewPadCfgLockRegVal =3D OldPadCfgLockRegVal & (~(0x1 << PadNumber)); + } else { + NewPadCfgLockRegVal =3D OldPadCfgLockRegVal | (0x1 << PadNumber); + } + + } else { + // + // Access whole register + // + + // + // Check if DwNum argument does not exceed number of DWord registers + // resulting from available pads for certain group + // + if (DwNum > ((GpioGroupInfo[GroupIndex].PadPerGroup - 1) >> 5)){ + return EFI_INVALID_PARAMETER; + } + // + // For future use. If there are more then 32 pads per group then certa= in + // group information would be split into more then one DWord register. + // For SKL PCH DwNum must be 0. + // + RegOffset +=3D DwNum *0x4; + + switch (RegType) { + case GpioPadConfigLockRegister: + GpioGetPadCfgLockForGroupDw (Group, DwNum, &OldPadCfgLockRegVal); + break; + case GpioPadLockOutputRegister: + GpioGetPadCfgLockTxForGroupDw (Group, DwNum, &OldPadCfgLockRegVal); + break; + } + if (Unlock) { + NewPadCfgLockRegVal =3D OldPadCfgLockRegVal & (~PadsToModify); + } else { + NewPadCfgLockRegVal =3D OldPadCfgLockRegVal | PadsToModify; + } + } + + Status =3D PchSbiExecution ( + GpioGroupInfo[GroupIndex].Community, + RegOffset, + GpioLockUnlock, + FALSE, + &NewPadCfgLockRegVal, + &Response + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will read multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[out] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadConfig ( + IN GPIO_PAD GpioPad, + OUT GPIO_CONFIG *GpioData + ) +{ + UINT32 Dw0Reg; + UINT32 Dw1Reg; + UINT32 PadCfgReg; + UINT32 RegVal; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + GPIO_GROUP Group; + UINT32 GroupIndex; + UINT32 PadNumber; + + GPIO_PAD_OWN PadOwnVal; + + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on thi= s chipset (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + GpioGetPadOwnership (GpioPad, &PadOwnVal); + if (PadOwnVal !=3D GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Gro= up=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGetLowestGroup ()) || (Group > GpioGetHighestGroup ()))= { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO gro= up range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup){ + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible ran= ge for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + + // + // Create PADCFG register offset using group and pad number + // + PadCfgReg =3D 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + + // + // Read PADCFG DW0 register + // + Dw0Reg =3D MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex]= .Community, PadCfgReg)); + + // + // Read PADCFG DW1 register + // + Dw1Reg =3D MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex]= .Community, PadCfgReg + 0x4)); + + + // + // Get Reset Type (PadRstCfg) + // + GpioData->PowerConfig =3D ((Dw0Reg & B_PCH_GPIO_RST_CONF) >> (N_PCH_GPIO= _RST_CONF - (GPIO_CONF_RESET_BIT_POS + 1))) | (0x1 << GPIO_CONF_RESET_BIT_P= OS); + + // + // Get how interrupt is triggered (RxEvCfg) + // + GpioData->InterruptConfig =3D ((Dw0Reg & B_PCH_GPIO_RX_LVL_EDG) >> (N_PC= H_GPIO_RX_LVL_EDG - (GPIO_CONF_INT_TRIG_BIT_POS + 1))) | (0x1 << GPIO_CONF_= INT_TRIG_BIT_POS); + + // + // Get interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI) + // + GpioData->InterruptConfig |=3D ((Dw0Reg & (B_PCH_GPIO_RX_NMI_ROUTE | B_P= CH_GPIO_RX_SCI_ROUTE | B_PCH_GPIO_RX_SMI_ROUTE | B_PCH_GPIO_RX_APIC_ROUTE))= >> (N_PCH_GPIO_RX_NMI_ROUTE - (GPIO_CONF_INT_ROUTE_BIT_POS + 1))) | (0x1 <= < GPIO_CONF_INT_ROUTE_BIT_POS); + + // + // Get GPIO direction (GPIORxDis and GPIOTxDis) + // + GpioData->Direction =3D ((Dw0Reg & (B_PCH_GPIO_RXDIS | B_PCH_GPIO_TXDIS)= ) >> (N_PCH_GPIO_TXDIS - (GPIO_CONF_DIR_BIT_POS + 1))) | (0x1 << GPIO_CONF_= DIR_BIT_POS); + + // + // Get GPIO input inversion (RXINV) + // + GpioData->Direction |=3D ((Dw0Reg & B_PCH_GPIO_RXINV) >> (N_PCH_GPIO_RXI= NV - (GPIO_CONF_INV_BIT_POS + 1))) | (0x1 << GPIO_CONF_INV_BIT_POS); + + // + // Get GPIO output state (GPIOTxState) + // + GpioData->OutputState =3D ((Dw0Reg & B_PCH_GPIO_TX_STATE) << (N_PCH_GPIO= _TX_STATE + (GPIO_CONF_OUTPUT_BIT_POS + 1))) | (0x1 << GPIO_CONF_OUTPUT_BIT= _POS) ; + + // + // Configure GPIO RX raw override to '1' (RXRAW1) + // + GpioData->OtherSettings =3D ((Dw0Reg & B_PCH_GPIO_RX_RAW1) >> (N_PCH_GPI= O_RX_RAW1 - (GPIO_CONF_RXRAW_BIT_POS + 1))) | (0x1 << GPIO_CONF_RXRAW_BIT_P= OS) ; + + // + // Get GPIO Pad Mode (PMode) + // + GpioData->PadMode =3D ((Dw0Reg & B_PCH_GPIO_PAD_MODE) >> (N_PCH_GPIO_PAD= _MODE - (GPIO_CONF_PAD_MODE_BIT_POS + 1))) | (0x1 << GPIO_CONF_PAD_MODE_BIT= _POS); + + // + // Get GPIO termination (Term) + // + GpioData->ElectricalConfig =3D ((Dw1Reg & B_PCH_GPIO_TERM) >> (N_PCH_GPI= O_TERM - (GPIO_CONF_TERM_BIT_POS + 1))) | (0x1 << GPIO_CONF_TERM_BIT_POS) ; + + // + // Get GPIO pad tolerance (padtol) + // + GpioData->ElectricalConfig |=3D ((Dw1Reg & B_PCH_GPIO_PADTOL) >> (N_PCH_= GPIO_PADTOL - (GPIO_CONF_PADTOL_BIT_POS + 1))) | (0x1 << GPIO_CONF_PADTOL_B= IT_POS) ; + + // + // Read HOSTSW_OWN registers + // + RegVal =3D MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex]= .Community, GpioGroupInfo[GroupIndex].HostOwnOffset)); + + // + // Get Host Software Ownership + // + GpioData->HostSoftPadOwn =3D (((RegVal >> PadNumber) & 0x1) << (GPIO_CON= F_HOST_OWN_BIT_POS + 1)) | (0x1 << GPIO_CONF_HOST_OWN_BIT_POS); + + // + // Read PADCFGLOCK register + // + RegVal =3D MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex]= .Community, GpioGroupInfo[GroupIndex].PadCfgLockOffset)); + + // + // Get Pad Configuration Lock state + // + GpioData->LockConfig =3D (((RegVal >> PadNumber) & 0x1) << 1) | 0x1; + + // + // Read PADCFGLOCKTX register + // + RegVal =3D MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex]= .Community, GpioGroupInfo[GroupIndex].PadCfgLockTxOffset)); + + // + // Get Pad Configuration Lock Tx state + // + GpioData->LockConfig |=3D (((RegVal >> PadNumber) & 0x1) << 2) | 0x1; + + return EFI_SUCCESS; +} + +/** + This procedure will configure multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[in] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ) +{ + UINT32 Dw0Reg; + UINT32 Dw0RegMask; + UINT32 Dw1Reg; + UINT32 Dw1RegMask; + UINT32 PadCfgReg; + UINT32 HostSoftOwnReg; + UINT32 HostSoftOwnRegMask; + UINT32 GpiGpeEnReg; + UINT32 GpiGpeEnRegMask; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + GPIO_GROUP Group; + UINT32 GroupIndex; + UINT32 PadNumber; + + GPIO_PAD_OWN PadOwnVal; + + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + Dw0RegMask =3D 0; + Dw0Reg =3D 0; + Dw1RegMask =3D 0; + Dw1Reg =3D 0; + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on thi= s chipset (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + GpioGetPadOwnership (GpioPad, &PadOwnVal); + if (PadOwnVal !=3D GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Gro= up=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGetLowestGroup ()) || (Group > GpioGetHighestGroup ()))= { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO gro= up range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible ran= ge for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + + if (GpioIsPadLocked (GroupIndex, PadNumber)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pad is locked (Group=3D%d, Pad=3D%d)= !\n", GroupIndex, PadNumber)); + return EFI_WRITE_PROTECTED; + } + + // + // Configure Reset Type (PadRstCfg) + // + Dw0RegMask |=3D ((((GpioData->PowerConfig & GPIO_CONF_RESET_MASK) >> GPI= O_CONF_RESET_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RST_CO= NF); + Dw0Reg |=3D (((GpioData->PowerConfig & GPIO_CONF_RESET_MASK) >> (GPIO_CO= NF_RESET_BIT_POS + 1)) << N_PCH_GPIO_RST_CONF); + + // + // Configure how interrupt is triggered (RxEvCfg) + // + Dw0RegMask |=3D ((((GpioData->InterruptConfig & GPIO_CONF_INT_TRIG_MASK)= >> GPIO_CONF_INT_TRIG_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_PCH_G= PIO_RX_LVL_EDG); + Dw0Reg |=3D (((GpioData->InterruptConfig & GPIO_CONF_INT_TRIG_MASK) >> (= GPIO_CONF_INT_TRIG_BIT_POS + 1)) << N_PCH_GPIO_RX_LVL_EDG); + + // + // Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI) + // + Dw0RegMask |=3D ((((GpioData->InterruptConfig & GPIO_CONF_INT_ROUTE_MASK= ) >> GPIO_CONF_INT_ROUTE_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : (B_P= CH_GPIO_RX_NMI_ROUTE | B_PCH_GPIO_RX_SCI_ROUTE | B_PCH_GPIO_RX_SMI_ROUTE | = B_PCH_GPIO_RX_APIC_ROUTE)); + Dw0Reg |=3D (((GpioData->InterruptConfig & GPIO_CONF_INT_ROUTE_MASK) >> = (GPIO_CONF_INT_ROUTE_BIT_POS + 1)) << N_PCH_GPIO_RX_NMI_ROUTE); + + // + // Configure GPIO direction (GPIORxDis and GPIOTxDis) + // + Dw0RegMask |=3D ((((GpioData->Direction & GPIO_CONF_DIR_MASK) >> GPIO_CO= NF_DIR_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : (B_PCH_GPIO_RXDIS | B_P= CH_GPIO_TXDIS)); + Dw0Reg |=3D (((GpioData->Direction & GPIO_CONF_DIR_MASK) >> (GPIO_CONF_D= IR_BIT_POS + 1)) << N_PCH_GPIO_TXDIS); + + // + // Configure GPIO input inversion (RXINV) + // + Dw0RegMask |=3D ((((GpioData->Direction & GPIO_CONF_INV_MASK) >> GPIO_CO= NF_INV_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RXINV); + Dw0Reg |=3D (((GpioData->Direction & GPIO_CONF_INV_MASK) >> (GPIO_CONF_I= NV_BIT_POS + 1)) << N_PCH_GPIO_RXINV); + + // + // Configure GPIO output state (GPIOTxState) + // + Dw0RegMask |=3D ((((GpioData->OutputState & GPIO_CONF_OUTPUT_MASK) >> GP= IO_CONF_OUTPUT_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_TX_S= TATE); + Dw0Reg |=3D (((GpioData->OutputState & GPIO_CONF_OUTPUT_MASK) >> (GPIO_C= ONF_OUTPUT_BIT_POS + 1)) << N_PCH_GPIO_TX_STATE); + + // + // Configure GPIO RX raw override to '1' (RXRAW1) + // + Dw0RegMask |=3D ((((GpioData->OtherSettings & GPIO_CONF_RXRAW_MASK) >> G= PIO_CONF_RXRAW_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RX_R= AW1); + Dw0Reg |=3D (((GpioData->OtherSettings & GPIO_CONF_RXRAW_MASK) >> (GPIO_= CONF_RXRAW_BIT_POS + 1)) << N_PCH_GPIO_RX_RAW1); + + // + // Configure GPIO Pad Mode (PMode) + // + Dw0RegMask |=3D ((((GpioData->PadMode & GPIO_CONF_PAD_MODE_MASK) >> GPIO= _CONF_PAD_MODE_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_PAD_= MODE); + Dw0Reg |=3D (((GpioData->PadMode & GPIO_CONF_PAD_MODE_MASK) >> (GPIO_CON= F_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE); + + // + // Configure GPIO termination (Term) + // + Dw1RegMask |=3D ((((GpioData->ElectricalConfig & GPIO_CONF_TERM_MASK) >>= GPIO_CONF_TERM_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_TER= M); + Dw1Reg |=3D (((GpioData->ElectricalConfig & GPIO_CONF_TERM_MASK) >> (GPI= O_CONF_TERM_BIT_POS + 1)) << N_PCH_GPIO_TERM); + + // + // Configure GPIO pad tolerance (padtol) + // + Dw1RegMask |=3D ((((GpioData->ElectricalConfig & GPIO_CONF_PADTOL_MASK) = >> GPIO_CONF_PADTOL_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_PCH_GPIO= _PADTOL); + Dw1Reg |=3D (((GpioData->ElectricalConfig & GPIO_CONF_PADTOL_MASK) >> (G= PIO_CONF_PADTOL_BIT_POS + 1)) << N_PCH_GPIO_PADTOL); + + // + // Create PADCFG register offset using group and pad number + // + PadCfgReg =3D 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + + // + // Write PADCFG DW0 register + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg= ), + ~(UINT32)Dw0RegMask, + (UINT32)Dw0Reg + ); + + // + // Write PADCFG DW1 register + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg= + 0x4), + ~(UINT32)Dw1RegMask, + (UINT32)Dw1Reg + ); + + // + // Update value to be programmed in HOSTSW_OWN register + // + HostSoftOwnRegMask =3D (GpioData->HostSoftPadOwn & 0x1) << PadNumber; + HostSoftOwnReg =3D (GpioData->HostSoftPadOwn >> 0x1) << PadNumber; + + // + // Write HOSTSW_OWN registers + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroup= Info[GroupIndex].HostOwnOffset), + ~(UINT32)HostSoftOwnRegMask, + (UINT32)HostSoftOwnReg + ); + + // + // Update value to be programmed in GPI_GPE_EN register + // + GpiGpeEnRegMask =3D (GpioData->InterruptConfig & 0x1) << PadNumber; + GpiGpeEnReg =3D ((GpioData->InterruptConfig & GpioIntSci) >> 3) << PadNu= mber; + + // + // Write GPI_GPE_EN registers + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroup= Info[GroupIndex].GpiGpeEnOffset), + ~(UINT32)GpiGpeEnRegMask, + (UINT32)GpiGpeEnReg + ); + + // + // Program Pad Configuration Lock + // + if ((GpioData->LockConfig & GpioPadConfigLock) =3D=3D GpioPadConfigLock)= { + GpioLockPadsUsingSbi ( + GpioPadConfigLockRegister, + FALSE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + } + + // + // Program Pad Configuration Lock Tx + // + if ((GpioData->LockConfig & GpioOutputStateLock) =3D=3D GpioOutputStateL= ock) { + GpioLockPadsUsingSbi ( + GpioPadLockOutputRegister, + FALSE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + } + return EFI_SUCCESS; +} + +/** + This procedure will set GPIO output level + + @param[in] GpioPad GPIO pad + @param[in] Value Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetOutputValue ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_TX_STATE, + TRUE, + &Value + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will get GPIO output level + + @param[in] GpioPad GPIO pad + @param[out] OutputVal GPIO Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetOutputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *OutputVal + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_TX_STATE, + FALSE, + OutputVal + ); + ASSERT_EFI_ERROR (Status); + *OutputVal >>=3D N_PCH_GPIO_TX_STATE; + + return Status; +} + +/** + This procedure will get GPIO input level + + @param[in] GpioPad GPIO pad + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InpuHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RX_STATE, + FALSE, + InputVal + ); + ASSERT_EFI_ERROR (Status); + *InputVal >>=3D N_PCH_GPIO_RX_STATE; + + return Status; +} + +/** + This procedure will get GPIO IOxAPIC interrupt number + + @param[in] GpioPad GPIO pad + @param[out] IrqNum IRQ number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadIoApicIrqNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *IrqNum + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 1, + B_PCH_GPIO_INTSEL, + FALSE, + IrqNum + ); + ASSERT_EFI_ERROR (Status); + *IrqNum >>=3D N_PCH_GPIO_INTSEL; + + return Status; +} + +/** + This procedure will configure GPIO input inversion + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIO input inversion + 0: No input inversion, 1: Invert input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetInputInversion ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + Value <<=3D N_PCH_GPIO_RXINV; + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RXINV, + TRUE, + &Value + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will get GPIO pad input inversion value + + @param[in] GpioPad GPIO pad + @param[out] InvertState GPIO inversion state + 0: No input inversion, 1: Inverted input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputInversion ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InvertState + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RXINV, + FALSE, + InvertState + ); + ASSERT_EFI_ERROR (Status); + *InvertState >>=3D N_PCH_GPIO_RXINV; + + return Status; +} + +/** + This procedure will set GPIO interrupt settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Level/Edge + use GPIO_INT_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadInterruptConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_INT_CONFIG Value + ) +{ + EFI_STATUS Status; + UINT32 RxLvlEdgeValue; + UINT32 IntRouteValue; + UINT32 GpeEnable; + + Status =3D EFI_SUCCESS; + + if (((Value & GPIO_CONF_INT_TRIG_MASK) >> GPIO_CONF_INT_TRIG_BIT_POS) != =3D GpioHardwareDefault) { + RxLvlEdgeValue =3D ((Value & GPIO_CONF_INT_TRIG_MASK) >> (GPIO_CONF_IN= T_TRIG_BIT_POS + 1)) << N_PCH_GPIO_RX_LVL_EDG; + + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RX_LVL_EDG, + TRUE, + &RxLvlEdgeValue + ); + ASSERT_EFI_ERROR (Status); + } + + if (((Value & GPIO_CONF_INT_ROUTE_MASK) >> GPIO_CONF_INT_ROUTE_BIT_POS) = !=3D GpioHardwareDefault) { + + IntRouteValue =3D ((Value & GPIO_CONF_INT_ROUTE_MASK) >> (GPIO_CONF_IN= T_ROUTE_BIT_POS + 1)) << N_PCH_GPIO_RX_NMI_ROUTE; + + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 0, + (B_PCH_GPIO_RX_NMI_ROUTE | B_PCH_GPIO_RX_SCI_ROUTE | B_PCH_= GPIO_RX_SMI_ROUTE | B_PCH_GPIO_RX_APIC_ROUTE), + TRUE, + &IntRouteValue + ); + ASSERT_EFI_ERROR (Status); + + if ((Value & GpioIntSci) =3D=3D GpioIntSci) { + GpeEnable =3D 0x1; + } else { + GpeEnable =3D 0x0; + } + + Status =3D GpioReadWriteReg ( + GpioGpeEnableRegister, + 0, + 0, + GpioPad, + TRUE, + TRUE, + &GpeEnable + ); + ASSERT_EFI_ERROR (Status); + } + + return Status; +} + +/** + This procedure will set GPIO electrical settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of termination + use GPIO_ELECTRICAL_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadElectricalConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_ELECTRICAL_CONFIG Value + ) +{ + EFI_STATUS Status; + UINT32 TermValue; + UINT32 PadTolValue; + + Status =3D EFI_SUCCESS; + + if (((Value & GPIO_CONF_TERM_MASK) >> GPIO_CONF_TERM_BIT_POS) !=3D GpioH= ardwareDefault) { + TermValue =3D ((Value & GPIO_CONF_TERM_MASK) >> (GPIO_CONF_TERM_BIT_PO= S + 1)) << N_PCH_GPIO_TERM; + + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 1, + B_PCH_GPIO_TERM, + TRUE, + &TermValue + ); + ASSERT_EFI_ERROR (Status); + } + + if (((Value & GPIO_CONF_PADTOL_MASK) >> GPIO_CONF_PADTOL_BIT_POS) !=3D G= pioHardwareDefault) { + PadTolValue =3D ((Value & GPIO_CONF_PADTOL_MASK) >> (GPIO_CONF_PADTOL_= BIT_POS + 1)) << N_PCH_GPIO_PADTOL; + + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 1, + B_PCH_GPIO_PADTOL, + TRUE, + &PadTolValue + ); + ASSERT_EFI_ERROR (Status); + } + return Status; +} + +/** + This procedure will set GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value for Pad Reset Configuration + use GPIO_RESET_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG Value + ) +{ + EFI_STATUS Status; + UINT32 ResetValue; + + Status =3D EFI_SUCCESS; + + if (((Value & GPIO_CONF_RESET_MASK) >> GPIO_CONF_RESET_BIT_POS) !=3D Gpi= oHardwareDefault) { + ResetValue =3D ((Value & GPIO_CONF_RESET_MASK) >> (GPIO_CONF_RESET_BIT= _POS + 1)) << N_PCH_GPIO_RST_CONF; + + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RST_CONF, + TRUE, + &ResetValue + ); + ASSERT_EFI_ERROR (Status); + } + return Status; +} + +/** + This procedure will get GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Pad Reset Configuration + based on GPIO_RESET_CONFIG + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG *Value + ) +{ + EFI_STATUS Status; + UINT32 ResetValue; + + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RST_CONF, + FALSE, + &ResetValue + ); + ASSERT_EFI_ERROR (Status); + + // + // Get Reset Type (PadRstCfg) + // + *Value =3D (ResetValue >> (N_PCH_GPIO_RST_CONF - (GPIO_CONF_RESET_BIT_PO= S + 1))) | (0x1 << GPIO_CONF_RESET_BIT_POS); + + return Status; +} + +/** + This procedure will get GPIO Host Software Pad Ownership for certain gro= up + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for curre= nt group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] HostSwRegVal Value of Host Software Pad Ownership reg= ister + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver= mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *HostSwRegVal + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWriteReg ( + GpioHostOwnershipRegister, + Group, + DwNum, + 0, + FALSE, + FALSE, + HostSwRegVal + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will get GPIO Host Software Pad Ownership for certain gro= up + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for curre= nt group + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] HostSwRegVal Value of Host Software Pad Ownership reg= ister + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver= mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 HostSwRegVal + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWriteReg ( + GpioHostOwnershipRegister, + Group, + DwNum, + 0, + TRUE, + FALSE, + &HostSwRegVal + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will get Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadHostSwOwn Value of Host Software Pad Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadHostSwOwn + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWriteReg ( + GpioHostOwnershipRegister, + 0, + 0, + GpioPad, + FALSE, + TRUE, + PadHostSwOwn + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[in] PadHostSwOwn Pad Host Software Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + IN UINT32 PadHostSwOwn + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWriteReg ( + GpioHostOwnershipRegister, + 0, + 0, + GpioPad, + TRUE, + TRUE, + &PadHostSwOwn + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will get Gpio Pad Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadOwnVal Value of Pad Ownership + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadOwnership ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_OWN *PadOwnVal + ) +{ + UINT32 Mask; + UINT32 RegOffset; + UINT32 GroupIndex; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 PadOwnRegValue; + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >=3D GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO gro= up range\n", GroupIndex)); + ASSERT(FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible ran= ge for this group\n", PadNumber)); + ASSERT(FALSE); + return EFI_INVALID_PARAMETER; + } + // + // Calculate RegOffset using Pad Ownership offset and GPIO Pad number. + // One DWord register contains information for 8 pads. + // + RegOffset =3D GpioGroupInfo[GroupIndex].PadOwnOffset + (PadNumber >> 3) = * 0x4; + + // + // Calculate pad bit position within DWord register + // + PadNumber %=3D 8; + Mask =3D (BIT1 | BIT0) << (PadNumber * 4); + + PadOwnRegValue =3D MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex= ].Community, RegOffset)); + + *PadOwnVal =3D (GPIO_PAD_OWN)((PadOwnRegValue & Mask) >> (PadNumber * 4)= ); + + return EFI_SUCCESS; +} + +/** + This procedure will check state of Pad Config Lock for pads within one g= roup + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockRegVal Value of PadCfgLock register + Bit position - PadNumber + Bit value - 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockRegVal + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWriteReg ( + GpioPadConfigLockRegister, + Group, + DwNum, + 0, + FALSE, + FALSE, + PadCfgLockRegVal + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will check state of Pad Config Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLock for selected pad + 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLock ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLock + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWriteReg ( + GpioPadConfigLockRegister, + 0, + 0, + GpioPad, + FALSE, + TRUE, + PadCfgLock + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will check state of Pad Config Tx Lock for pads within on= e group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register + Bit position - PadNumber + Bit value - 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockTxRegVal + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWriteReg ( + GpioPadLockOutputRegister, + Group, + DwNum, + 0, + FALSE, + FALSE, + PadCfgLockTxRegVal + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will check state of Pad Config Tx Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLockTx for selected pad + 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLockTx ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLockTx + ) +{ + EFI_STATUS Status; + + Status =3D GpioReadWriteReg ( + GpioPadLockOutputRegister, + 0, + 0, + GpioPad, + FALSE, + TRUE, + PadCfgLockTx + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will clear PadCfgLock for selected pads within one group. + This function should be used only inside SMI. + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlock Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnlock, 1: Unlock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlock + ) +{ + EFI_STATUS Status; + + Status =3D GpioLockPadsUsingSbi ( + GpioPadConfigLockRegister, + TRUE, + Group, + DwNum, + PadsToUnlock, + 0, + FALSE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will clear PadCfgLock for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfg ( + IN GPIO_PAD GpioPad + ) +{ + EFI_STATUS Status; + + Status =3D GpioLockPadsUsingSbi ( + GpioPadConfigLockRegister, + TRUE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set PadCfgLock for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLock Bitmask for pads which are going to be l= ocked + Bit position - PadNumber + Bit value - 0: DoNotLock, 1: Lock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLock + ) +{ + EFI_STATUS Status; + + Status =3D GpioLockPadsUsingSbi ( + GpioPadConfigLockRegister, + FALSE, + Group, + DwNum, + PadsToLock, + 0, + FALSE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set PadCfgLock for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfg ( + IN GPIO_PAD GpioPad + ) +{ + EFI_STATUS Status; + + Status =3D GpioLockPadsUsingSbi ( + GpioPadConfigLockRegister, + FALSE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will clear PadCfgLockTx for selected pads within one grou= p. + This function should be used only inside SMI. + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlockTx Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlockTx + ) +{ + EFI_STATUS Status; + + Status =3D GpioLockPadsUsingSbi ( + GpioPadLockOutputRegister, + TRUE, + Group, + DwNum, + PadsToUnlockTx, + 0, + FALSE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will clear PadCfgLockTx for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTx ( + IN GPIO_PAD GpioPad + ) +{ + EFI_STATUS Status; + + Status =3D GpioLockPadsUsingSbi ( + GpioPadLockOutputRegister, + TRUE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set PadCfgLockTx for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLockTx Bitmask for pads which are going to be l= ocked, + Bit position - PadNumber + Bit value - 0: DoNotLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLockTx + ) +{ + EFI_STATUS Status; + + Status =3D GpioLockPadsUsingSbi ( + GpioPadLockOutputRegister, + FALSE, + Group, + DwNum, + PadsToLockTx, + 0, + FALSE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set PadCfgLockTx for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfgTx ( + IN GPIO_PAD GpioPad + ) +{ + EFI_STATUS Status; + + Status =3D GpioLockPadsUsingSbi ( + GpioPadLockOutputRegister, + FALSE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + + +/** + This procedure will get Group to GPE mapping. + + @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGroupToGpeDwX ( + IN GPIO_GROUP *GroupToGpeDw0, + IN GPIO_GROUP *GroupToGpeDw1, + IN GPIO_GROUP *GroupToGpeDw2 + ) +{ + UINT32 Data32; + UINT32 PchPwrmBase; + GPIO_GROUP GpioGroupOffset; + + GpioGroupOffset =3D GpioGetLowestGroup (); + + + PchPwrmBaseGet (&PchPwrmBase); + + Data32 =3D MmioRead32 ((UINTN) (PchPwrmBase + R_PCH_PWRM_GPIO_CFG)); + + *GroupToGpeDw0 =3D ((Data32 & B_PCH_PWRM_GPIO_CFG_GPE0_DW0) >> N_PCH_PWR= M_GPIO_CFG_GPE0_DW0) + GpioGroupOffset; + *GroupToGpeDw1 =3D ((Data32 & B_PCH_PWRM_GPIO_CFG_GPE0_DW1) >> N_PCH_PWR= M_GPIO_CFG_GPE0_DW1) + GpioGroupOffset; + *GroupToGpeDw2 =3D ((Data32 & B_PCH_PWRM_GPIO_CFG_GPE0_DW2) >> N_PCH_PWR= M_GPIO_CFG_GPE0_DW2) + GpioGroupOffset; + + return EFI_SUCCESS; +} + +/** + This procedure will set Group to GPE mapping. + + @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGroupToGpeDwX ( + IN GPIO_GROUP GroupToGpeDw0, + IN GPIO_GROUP GroupToGpeDw1, + IN GPIO_GROUP GroupToGpeDw2 + ) +{ + UINT32 Data32Or; + UINT32 Data32And; + UINT32 PchPwrmBase; + GPIO_GROUP GpioGroupLowest; + GPIO_GROUP GpioGroupHighest; + + GpioGroupLowest =3D GpioGetLowestGroup (); + GpioGroupHighest =3D GpioGetHighestGroup (); + + // + // Check if group argument exceeds GPIO group range + // + if (((UINT32)GroupToGpeDw0 < GpioGroupLowest) || ((UINT32)GroupToGpeDw0 = > GpioGroupHighest) || + ((UINT32)GroupToGpeDw1 < GpioGroupLowest) || ((UINT32)GroupToGpeDw1 > = GpioGroupHighest) || + ((UINT32)GroupToGpeDw2 < GpioGroupLowest) || ((UINT32)GroupToGpeDw2 > = GpioGroupHighest)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument exceeds GPIO group ra= nge\n")); + return EFI_INVALID_PARAMETER; + } + + // + // Check if each group number is unique + // + if ((GroupToGpeDw0 =3D=3D GroupToGpeDw1) || + (GroupToGpeDw0 =3D=3D GroupToGpeDw2) || + (GroupToGpeDw1 =3D=3D GroupToGpeDw2)) { + return EFI_INVALID_PARAMETER; + } + + // + // Values in GPE0_DWx registers are 0 based (GPP_A =3D 0h) + // + GroupToGpeDw0 =3D GpioGetGroupIndexFromGroup(GroupToGpeDw0); + GroupToGpeDw1 =3D GpioGetGroupIndexFromGroup(GroupToGpeDw1); + GroupToGpeDw2 =3D GpioGetGroupIndexFromGroup(GroupToGpeDw2); + + PchPwrmBaseGet (&PchPwrmBase); + + // + // Program GPIO_CFG (PMRMBASE + 120h) register + // + Data32And =3D (UINT32) ~(B_PCH_PWRM_GPIO_CFG_GPE0_DW2 | B_PCH_PWRM_GPIO_= CFG_GPE0_DW1 | B_PCH_PWRM_GPIO_CFG_GPE0_DW0); + Data32Or =3D (UINT32)((GroupToGpeDw2 << N_PCH_PWRM_GPIO_CFG_GPE0_DW2) | + (GroupToGpeDw1 << N_PCH_PWRM_GPIO_CFG_GPE0_DW1) | + (GroupToGpeDw0 << N_PCH_PWRM_GPIO_CFG_GPE0_DW0)); + + MmioAndThenOr32 ( + (UINTN) (PchPwrmBase + R_PCH_PWRM_GPIO_CFG), + Data32And, + Data32Or + ); + + Data32And =3D (UINT32) ~(B_PCH_PCR_GPIO_MISCCFG_GPE0_DW2 | B_PCH_PCR_GPI= O_MISCCFG_GPE0_DW1 | B_PCH_PCR_GPIO_MISCCFG_GPE0_DW0); + Data32Or =3D (UINT32)((GroupToGpeDw2 << N_PCH_PCR_GPIO_MISCCFG_GPE0_DW2)= | + (GroupToGpeDw1 << N_PCH_PCR_GPIO_MISCCFG_GPE0_DW1) | + (GroupToGpeDw0 << N_PCH_PCR_GPIO_MISCCFG_GPE0_DW0)); + // + // Program MISCCFG register for Community 0 + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (PID_GPIOCOM0, R_PCH_PCR_GPIO_MISCCFG), + Data32And, + Data32Or + ); + + // + // Program MISCCFG register for Community 1 + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (PID_GPIOCOM1, R_PCH_PCR_GPIO_MISCCFG), + Data32And, + Data32Or + ); + + // + // Program MISCCFG register for Community 2 + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (PID_GPIOCOM2, R_PCH_PCR_GPIO_MISCCFG), + Data32And, + Data32Or + ); + + // + // Program MISCCFG register for Community 3 + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (PID_GPIOCOM3, R_PCH_PCR_GPIO_MISCCFG), + Data32And, + Data32Or + ); + + return EFI_SUCCESS; +} + +/** + This procedure will get GPE number for provided GpioPad. + PCH allows to configure mapping between GPIO groups and related GPE (Gpi= oSetGroupToGpeDwX()) + what results in the fact that certain Pad can cause different General Pu= rpose Event. Only three + GPIO groups can be mapped to cause unique GPE (1-tier), all others group= s will be under one common + event (GPE_111 for 2-tier). + + 1-tier: + Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used + to determine what _LXX ACPI method would be called on event on selected = GPIO pad + + 2-tier: + Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to = 1-tier GPE + will be under one master GPE_111 which is linked to _L6F ACPI method. If= it is needed to determine + what Pad from 2-tier has caused the event, _L6F method should check GPI_= GPE_STS and GPI_GPE_EN + registers for all GPIO groups not mapped to 1-tier GPE. + + @param[in] GpioPad GPIO pad + @param[out] GpeNumber GPE number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpeNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *GpeNumber + ) +{ + GPIO_GROUP GroupToGpeDw0; + GPIO_GROUP GroupToGpeDw1; + GPIO_GROUP GroupToGpeDw2; + GPIO_GROUP GpioGroupLowest; + GPIO_GROUP GpioGroupHighest; + UINT32 GroupIndex; + GPIO_GROUP Group; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on thi= s chipset (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + GpioGroupLowest =3D GpioGetLowestGroup (); + GpioGroupHighest =3D GpioGetHighestGroup (); + + // + // Check if group argument exceeds GPIO group range + // + if ((GroupIndex < GpioGetGroupIndexFromGroup (GpioGroupLowest)) || (Grou= pIndex > GpioGetGroupIndexFromGroup (GpioGroupHighest))) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO gro= up range\n", GroupIndex)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pad number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible ran= ge for this group\n", PadNumber)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Get GPIO groups mapping to 1-tier GPE + // + GpioGetGroupToGpeDwX (&GroupToGpeDw0,&GroupToGpeDw1,&GroupToGpeDw2); + + if (Group =3D=3D GroupToGpeDw0) { + *GpeNumber =3D PadNumber; + } else if (Group=3D=3D GroupToGpeDw1) { + *GpeNumber =3D PadNumber + 32; + } else if (Group =3D=3D GroupToGpeDw2) { + *GpeNumber =3D PadNumber + 64; + } else { + // + // If Group number doesn't match any of above then + // it means than certain pad is routed to 2-tier GPE + // which all are under GPE_111 (0x6F) + // + *GpeNumber =3D PCH_GPIO_2_TIER_MASTER_GPE_NUMBER; + } + + return EFI_SUCCESS; +} + +/** + This procedure is used to clear SMI STS for a specified Pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiSmiSts ( + IN GPIO_PAD GpioPad + ) +{ + UINT32 GroupIndex; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on thi= s chipset (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >=3D GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO gro= up range\n", GroupIndex)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pad number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible ran= ge for this group\n", PadNumber)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if group has GPI SMI register + // + if (GpioGroupInfo[GroupIndex].SmiStsOffset =3D=3D NO_REGISTER_FOR_PROPER= TY) { + return EFI_INVALID_PARAMETER; + } + // + // Clear all GPI SMI Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[Gr= oupIndex].SmiStsOffset), + (UINT32)(BIT0 << PadNumber) + ); + + return EFI_SUCCESS; +} + +/** + This procedure is used by PchSmiDispatcher and will clear + all GPI SMI Status bits + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearAllGpiSmiSts ( + VOID + ) +{ + UINT32 GroupIndex; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + for (GroupIndex =3D 0; GroupIndex < GpioGroupInfoLength; GroupIndex++) { + // + // Check if group has GPI SMI register + // + if (GpioGroupInfo[GroupIndex].SmiStsOffset =3D=3D NO_REGISTER_FOR_PROP= ERTY) { + continue; + } + // + // Clear all GPI SMI Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[= GroupIndex].SmiStsOffset), + (UINT32)0xFFFFFFFF + ); + } + return EFI_SUCCESS; +} + +/** + This procedure is used to disable all GPI SMI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioDisableAllGpiSmi ( + VOID + ) +{ + GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GroupIndex; + UINTN GpioGroupInfoLength; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + for (GroupIndex =3D 0; GroupIndex < GpioGroupInfoLength; GroupIndex++) { + // + // Check if group has GPI SMI register + // + if (GpioGroupInfo[GroupIndex].SmiEnOffset =3D=3D NO_REGISTER_FOR_PROPE= RTY) { + continue; + } + + // + // Disable all GPI SMI + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[= GroupIndex].SmiEnOffset), + (UINT32)0x0 + ); + } + return EFI_SUCCESS; +} + +/** + This procedure is used to register GPI SMI dispatch function. + + @param[in] GpioPad GPIO pad + @param[out] GpiNum GPI number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiSmiNum ( + IN GPIO_PAD GpioPad, + OUT UINTN *GpiNum + ) +{ + UINT32 GroupIndex; + UINT32 Index; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on thi= s chipset (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >=3D GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO gro= up range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pad number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup){ + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible ran= ge for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + + *GpiNum =3D 0; + + for (Index =3D 0; Index < (UINT32)GroupIndex; Index++) { + *GpiNum +=3D (UINTN)(GpioGroupInfo[Index].PadPerGroup); + } + *GpiNum +=3D (UINTN)PadNumber; + + return EFI_SUCCESS; +} + +/** + This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier = architecture + + @param[in] GpioPad GPIO pad + + @retval Data 0 means 1-tier, 1 means 2-tier +**/ +BOOLEAN +GpioCheckFor2Tier ( + IN GPIO_PAD GpioPad + ) +{ + UINT32 Data32; + + GpioGetGpeNumber (GpioPad, &Data32); + if(Data32 =3D=3D PCH_GPIO_2_TIER_MASTER_GPE_NUMBER) { + return TRUE; + } + + return FALSE; +} + +/** + This procedure is used to clear GPE STS for a specified GpioPad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiGpeSts ( + IN GPIO_PAD GpioPad + ) +{ + UINT32 GroupIndex; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >=3D GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO gro= up range\n", GroupIndex)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pad number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible ran= ge for this group\n", PadNumber)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if group has GPI GPE register + // + if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset =3D=3D NO_REGISTER_FOR_PRO= PERTY) { + return EFI_INVALID_PARAMETER; + } + + // Check for 2-tier + if(!(GpioCheckFor2Tier (GpioPad))) { + return EFI_INVALID_PARAMETER; + } + + // + // Clear all GPI SMI Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[Gr= oupIndex].GpiGpeStsOffset), + (UINT32)(BIT0 << PadNumber) + ); + + return EFI_SUCCESS; +} + +/** + This procedure is used to read GPE STS for a specified Pad + + @param[in] GpioPad GPIO pad + @param[out] Data GPE STS data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiGpeSts ( + IN GPIO_PAD GpioPad, + OUT UINT32* Data + ) +{ + UINT32 Data32; + UINT32 Mask; + UINT32 GroupIndex; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + *Data =3D 0xFFFFFFFF; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >=3D GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO gro= up range\n", GroupIndex)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pad number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible ran= ge for this group\n", PadNumber)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if group has GPI GPE register + // + if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset =3D=3D NO_REGISTER_FOR_PRO= PERTY) { + return EFI_INVALID_PARAMETER; + } + + // Check for 2-tier + if(!(GpioCheckFor2Tier (GpioPad))) { + return EFI_INVALID_PARAMETER; + } + + // + // Read GPI GPE Status bits + // + Data32 =3D MmioRead32( + PCH_PCR_ADDRESS(GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[Gro= upIndex].GpiGpeStsOffset) + ); + + Mask =3D (UINT32)(BIT0 << PadNumber); + Data32 =3D (Data32 & Mask) >> PadNumber; + *Data =3D Data32; + + return EFI_SUCCESS; +} + +/** + This procedure will set GPIO Input Rout SCI + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIRoutSCI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiRoutSci ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + Value <<=3D N_PCH_GPIO_RX_SCI_ROUTE; + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RX_SCI_ROUTE, + TRUE, + &Value + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set GPIO Input Rout SMI + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIRoutSMI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiRoutSmi ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + Value <<=3D N_PCH_GPIO_RX_SMI_ROUTE; + Status =3D GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RX_SMI_ROUTE, + TRUE, + &Value + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set GPI SMI Enable setting for selected pad + + @param[in] GpioPad GPIO pad + @param[in] PadGpiSmiEn GPI SMI Enable setting for selected pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiSmiPadEn ( + IN GPIO_PAD GpioPad, + IN UINT32 PadGpiSmiEn + ) +{ + GPIO_GROUP Group; + GPIO_GROUP GpioGroupOffset; + UINT32 NumberOfGroups; + EFI_STATUS Status; + + GpioGroupOffset =3D GpioGetLowestGroup (); + NumberOfGroups =3D GpioGetNumberOfGroups (); + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGroupOffset) || (Group >=3D NumberOfGroups + GpioGroupO= ffset)) { + return EFI_INVALID_PARAMETER; + } + + Status =3D GpioReadWriteReg ( + GpioSmiEnableRegister, + Group, + 0, + GpioPad, + TRUE, + TRUE, + &PadGpiSmiEn + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set GPI General Purpose Event Enable setting for sel= ected pad + + @param[in] GpioPad GPIO pad + @param[in] PadGpiGpeEn GPI General Purpose Event Enable setting= for selected pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiGpePadEn ( + IN GPIO_PAD GpioPad, + IN UINT32 PadGpiGpeEn + ) +{ + GPIO_GROUP Group; + GPIO_GROUP GpioGroupOffset; + UINT32 NumberOfGroups; + EFI_STATUS Status; + + GpioGroupOffset =3D GpioGetLowestGroup (); + NumberOfGroups =3D GpioGetNumberOfGroups (); + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGroupOffset) || (Group >=3D NumberOfGroups + GpioGroupO= ffset)) { + return EFI_INVALID_PARAMETER; + } + + + Status =3D GpioReadWriteReg ( + GpioGpeEnableRegister, + Group, + 0, + GpioPad, + TRUE, + TRUE, + &PadGpiGpeEn + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + Check if given GPIO Pad is locked + + @param[in] GroupIndex GPIO group index + @param[in] PadNumber GPIO pad number + + @retval TRUE Pad is locked + @retval FALSE Pad is not locked +**/ +BOOLEAN +GpioIsPadLocked ( + IN UINT32 GroupIndex, + IN GPIO_PAD PadNumber + ) +{ + UINT32 RegVal; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + // Read PADCFGLOCK register + // + RegVal =3D MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex]= .Community, GpioGroupInfo[GroupIndex].PadCfgLockOffset)); + + return (((RegVal >> PadNumber) & 0x1) =3D=3D 1); +} + +/** + Locks multiple GPIO pads using GPIO_INIT_CONFIG array. + Only locking is applied and no other GPIO pad configuration is changed. + + @param[in] NumberOfItems Number of GPIO pads to be locked + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number + @retval EFI_UNSUPPORTED Incorrect GPIO pad definition +**/ +static +EFI_STATUS +GpioLockPads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ) +{ + UINT32 Index; + UINT32 PadsToLock[V_PCH_GPIO_GROUP_MAX]; + UINT32 PadsToLockTx[V_PCH_GPIO_GROUP_MAX]; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + GPIO_GROUP GpioGroupOffset; + UINT32 NumberOfGroups; + GPIO_PAD_OWN PadOwnVal; + GPIO_INIT_CONFIG *GpioData; + GPIO_GROUP Group; + UINT32 GroupIndex; + UINT32 PadNumber; + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + PadOwnVal =3D GpioPadOwnHost; + + ZeroMem (PadsToLock, sizeof (PadsToLock)); + ZeroMem (PadsToLockTx, sizeof (PadsToLockTx)); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GpioGroupOffset =3D GpioGetLowestGroup (); + NumberOfGroups =3D GpioGetNumberOfGroups (); + + for (Index =3D 0; Index < NumberOfItems; Index ++) { + + GpioData =3D &GpioInitTableAddress[Index]; + + Group =3D GpioGetGroupFromGpioPad (GpioData->GpioPad); + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioData->GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioData->GpioPad); + + // + // Checking GroupIndex to avoid Buffer Overflows or Array Out of Index + // + if (GroupIndex >=3D V_PCH_GPIO_GROUP_MAX) { + ASSERT (FALSE); + continue; + } + + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGroupOffset) || (Group >=3D NumberOfGroups + GpioGrou= pOffset)) { + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup){ + return EFI_INVALID_PARAMETER; + } + + // + // Check if selected GPIO Pad is not owned by CSME/ISH + // + GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal); + + if (PadOwnVal !=3D GpioPadOwnHost) { + continue; + } + + // + // Update information on Pad Configuration Lock + // + PadsToLock[GroupIndex] |=3D ((GpioData->GpioConfig.LockConfig >> 0x1) = & 0x1) << PadNumber; + + // + // Update information on Pad Configuration Lock Tx + // + PadsToLockTx[GroupIndex] |=3D ((GpioData->GpioConfig.LockConfig >> 0x2= ) & 0x1) << PadNumber; + } + + for (Index =3D 0; Index < NumberOfGroups; Index++) { + // + // Write Pad Configuration Lock + // + if (PadsToLock[Index] !=3D 0) { + GpioLockPadCfgForGroupDw (Index + GpioGroupOffset, 0, PadsToLock[Ind= ex]); + } + + // + // Write Pad Configuration Lock Tx + // + if (PadsToLockTx[Index] !=3D 0) { + GpioLockPadCfgTxForGroupDw (Index + GpioGroupOffset, 0, PadsToLockTx= [Index]); + } + } + + return EFI_SUCCESS; +} + +/** + Locks GPIO pads according to GPIO_INIT_CONFIG array from + gPlatformGpioConfigGuid HOB. Only locking is applied and no other GPIO p= ad + configuration is changed. + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_NOT_FOUND gPlatformGpioConfigGuid not found +**/ +EFI_STATUS +GpioLockGpios ( + VOID + ) +{ + EFI_HOB_GUID_TYPE *GpioConfigHob; + GPIO_INIT_CONFIG *GpioConfig; + UINT16 GpioConfigSize; + + GpioConfigHob =3D GetFirstGuidHob (&gPlatformGpioConfigGuid); + if (GpioConfigHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + ASSERT (GET_GUID_HOB_DATA_SIZE (GpioConfigHob) % sizeof (GpioConfig[0]) = =3D=3D 0); + GpioConfigSize =3D GET_GUID_HOB_DATA_SIZE (GpioConfigHob) / sizeof (Gpio= Config[0]); + GpioConfig =3D GET_GUID_HOB_DATA (GpioConfigHob); + GpioLockPads (GpioConfigSize, GpioConfig); + + return EFI_SUCCESS; +} + +/** + Unlocks all PCH GPIO pads + + @retval None +**/ +VOID +GpioUnlockAllGpios ( + VOID + ) +{ + GPIO_GROUP GpioGroupOffset; + UINT32 NumberOfGroups; + UINT32 Index; + + GpioGroupOffset =3D GpioGetLowestGroup (); + NumberOfGroups =3D GpioGetNumberOfGroups (); + + for (Index =3D 0; Index < NumberOfGroups; Index++) { + // + // Reset Pad Configuration Lock + // + GpioUnlockPadCfgForGroupDw (Index + GpioGroupOffset, 0, 0xFFFFFFFF); + + // + // Reset Pad Configuration Lock Tx + // + GpioUnlockPadCfgTxForGroupDw (Index + GpioGroupOffset, 0, 0xFFFFFFFF); + } +} + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpi= oLib/GpioLibrary.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiD= xeSmmGpioLib/GpioLibrary.h new file mode 100644 index 0000000000..6cb918fd38 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/Gp= ioLibrary.h @@ -0,0 +1,216 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _GPIO_LIBRARY_H_ +#define _GPIO_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + GPIO_PAD Pad; + GPIO_PAD_MODE Mode; +} GPIO_PAD_NATIVE_FUNCTION; + + +// BIT15-0 - pad number +// BIT31-16 - group info +// BIT23- 16 - group index +// BIT31- 24 - chipset ID +#define PAD_INFO_MASK 0x0000FFFF +#define GROUP_INFO_POSITION 16 +#define GROUP_INFO_MASK 0xFFFF0000 +#define GROUP_INDEX_MASK 0x00FF0000 +#define UNIQUE_ID_MASK 0xFF000000 +#define UNIQUE_ID_POSITION 24 + +#define GPIO_PAD_DEF(Group,Pad) (UINT32)((Group << 16) + Pad) +#define GPIO_GROUP_DEF(Index,ChipsetId) (Index | (ChipsetId << 8)) +#define GPIO_GET_GROUP_INDEX(Group) (Group & 0xFF) +#define GPIO_GET_GROUP_FROM_PAD(Pad) (Pad >> 16) +#define GPIO_GET_GROUP_INDEX_FROM_PAD(Pad) GPIO_GET_GROUP_INDEX ((Pad >= > 16)) +#define GPIO_GET_PAD_NUMBER(Pad) (Pad & 0xFFFF) +#define GPIO_GET_CHIPSET_ID(Pad) (Pad >> 24) + +// +// Unique ID used in GpioPad defines +// +#define GPIO_SKL_H_CHIPSET_ID 0x1 +#define GPIO_SKL_LP_CHIPSET_ID 0x2 + +// +// Below defines are based on GPIO_CONFIG structure fields +// +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 +#define GPIO_CONF_HOST_OWN_MASK 0x3 +#define GPIO_CONF_HOST_OWN_BIT_POS 0 +#define GPIO_CONF_DIR_MASK 0x7 +#define GPIO_CONF_DIR_BIT_POS 0 +#define GPIO_CONF_INV_MASK 0x18 +#define GPIO_CONF_INV_BIT_POS 3 +#define GPIO_CONF_OUTPUT_MASK 0x3 +#define GPIO_CONF_OUTPUT_BIT_POS 0 +#define GPIO_CONF_INT_ROUTE_MASK 0x1F +#define GPIO_CONF_INT_ROUTE_BIT_POS 0 +#define GPIO_CONF_INT_TRIG_MASK 0xE0 +#define GPIO_CONF_INT_TRIG_BIT_POS 5 +#define GPIO_CONF_RESET_MASK 0x7 +#define GPIO_CONF_RESET_BIT_POS 0 +#define GPIO_CONF_TERM_MASK 0x1F +#define GPIO_CONF_TERM_BIT_POS 0 +#define GPIO_CONF_PADTOL_MASK 0x60 +#define GPIO_CONF_PADTOL_BIT_POS 5 +#define GPIO_CONF_LOCK_MASK 0x7 +#define GPIO_CONF_LOCK_BIT_POS 0 +#define GPIO_CONF_RXRAW_MASK 0x3 +#define GPIO_CONF_RXRAW_BIT_POS 0 + +// +// Structure for storing information about registers offset, community, +// maximal pad number for available groups +// +typedef struct { + UINT32 Community; + UINT32 PadOwnOffset; + UINT32 HostOwnOffset; + UINT32 GpiIsOffset; + UINT32 GpiIeOffset; + UINT32 GpiGpeStsOffset; + UINT32 GpiGpeEnOffset; + UINT32 SmiStsOffset; + UINT32 SmiEnOffset; + UINT32 NmiStsOffset; + UINT32 NmiEnOffset; + UINT32 PadCfgLockOffset; + UINT32 PadCfgLockTxOffset; + UINT32 PadCfgOffset; + UINT32 PadPerGroup; +} GPIO_GROUP_INFO; + +// +// If in GPIO_GROUP_INFO structure certain register doesn't exist +// it will have value equal to NO_REGISTER_FOR_PROPERTY +// +#define NO_REGISTER_FOR_PROPERTY (~0u) + + +/** + This procedure is used to check if GpioPad is valid for certain chipset + + @param[in] GpioPad GPIO pad + + @retval TRUE This pin is valid on this chipset + FALSE Incorrect pin +**/ +BOOLEAN +GpioIsCorrectPadForThisChipset ( + IN GPIO_PAD GpioPad + ); + + +/** + This procedure will retrieve address and length of GPIO info table + + @param[out] GpioGroupInfoTableLength Length of GPIO group table + + @retval Pointer to GPIO group table + +**/ +GPIO_GROUP_INFO* +GpioGetGroupInfoTable ( + OUT UINTN *GpioGroupInfoTableLength + ); + +/** + This procedure will set GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +SetGpioPadMode ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadModeValue + ); + +/** + This procedure will get GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GetGpioPadMode ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_MODE *PadModeValue + ); + +/** + This function checks if GPIO pin is a GSPI chip select pin + + @param[in] GpioPad GPIO pad + @param[in] PadMode GPIO pad mode + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsGpioPadAGSpiCsbPin ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadMode + ); + +/** + This function checks if GPIO pin is a SataDevSlp pin + + @param[in] GpioPad GPIO pad + @param[in] PadMode GPIO pad mode + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsPadASataDevSlpPin ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadMode + ); + +/** + Check if given GPIO Pad is locked + + @param[in] GroupIndex GPIO group index + @param[in] PadNumber GPIO pad number + + @retval TRUE Pad is locked + @retval FALSE Pad is not locked +**/ +BOOLEAN +GpioIsPadLocked ( + IN UINT32 GroupIndex, + IN GPIO_PAD PadNumber + ); + +#endif // _GPIO_LIBRARY_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpi= oLib/GpioNativeLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/Pe= iDxeSmmGpioLib/GpioNativeLib.c new file mode 100644 index 0000000000..314e8d5c98 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/Gp= ioNativeLib.c @@ -0,0 +1,448 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "GpioLibrary.h" + +// +// Chipset specific data +// +//SATA +extern GPIO_PAD_NATIVE_FUNCTION mPchHSataPortResetToGpioMap[PCH_H_AHCI_MAX= _PORTS]; +extern GPIO_PAD_NATIVE_FUNCTION mPchHSataDevSlpPinToGpioMap[PCH_H_AHCI_MAX= _PORTS]; + +// +// SKX specific +// +extern GPIO_GROUP_INFO mPchGpioGroupInfo[V_PCH_GPIO_GROUP_MAX]; + +/** + This procedure will set GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +SetGpioPadMode ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadModeValue + ) +{ + GPIO_PAD_OWN PadOwnVal; + UINT32 PadCfgReg; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 PadNumber; + UINT32 GroupIndex; + UINT32 Dw0Reg; + UINT32 Dw0RegMask; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on thi= s chipset (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + GpioGetPadOwnership (GpioPad, &PadOwnVal); + + if (PadOwnVal !=3D GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Gro= up=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } + + if (GpioIsPadLocked (GroupIndex, PadNumber)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pad is locked (Group=3D%d, Pad=3D%d)= !\n", GroupIndex, PadNumber)); + return EFI_WRITE_PROTECTED; + } + + // + // Create Pad Configuration register offset + // + PadCfgReg =3D 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + + Dw0RegMask =3D ((((PadModeValue & GPIO_CONF_PAD_MODE_MASK) >> GPIO_CONF_= PAD_MODE_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_PAD_MODE); + Dw0Reg =3D (((PadModeValue & GPIO_CONF_PAD_MODE_MASK) >> (GPIO_CONF_PAD_= MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE); + + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg= ), + ~(UINT32)Dw0RegMask, + (UINT32)Dw0Reg + ); + + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GetGpioPadMode ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_MODE *PadModeValue + ) +{ + GPIO_PAD_OWN PadOwnVal; + UINT32 PadCfgReg; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 PadNumber; + UINT32 GroupIndex; + UINT32 Dw0Reg; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on thi= s chipset (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + GpioGetPadOwnership (GpioPad, &PadOwnVal); + + if (PadOwnVal !=3D GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Gro= up=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } + + // + // Create Pad Configuration register offset + // + PadCfgReg =3D 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + + Dw0Reg =3D MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex]= .Community, PadCfgReg)); + + *PadModeValue =3D ((Dw0Reg & B_PCH_GPIO_PAD_MODE) >> (N_PCH_GPIO_PAD_MOD= E - (GPIO_CONF_PAD_MODE_BIT_POS + 1))) | (0x1 << GPIO_CONF_PAD_MODE_BIT_POS= ); + + return EFI_SUCCESS; +} + + +/** + This procedure will retrieve address and length of GPIO info table + + @param[out] GpioGroupInfoTableLength Length of GPIO group table + + @retval Pointer to GPIO group table + +**/ +GPIO_GROUP_INFO* +GpioGetGroupInfoTable ( + OUT UINTN *GpioGroupInfoTableLength + ) +{ + if (GetPchGeneration () =3D=3D SklPch) { + *GpioGroupInfoTableLength =3D sizeof (mPchGpioGroupInfo) / sizeof (G= PIO_GROUP_INFO); + return mPchGpioGroupInfo; + } else { + *GpioGroupInfoTableLength =3D 0; + return NULL; + } +} + + +/** + This procedure is used to check if GpioPad is valid for certain chipset + + @param[in] GpioPad GPIO pad + + @retval TRUE This pin is valid on this chipset + FALSE Incorrect pin +**/ +BOOLEAN +GpioIsCorrectPadForThisChipset ( + IN GPIO_PAD GpioPad + ) +{ +DEBUG_CODE_BEGIN(); + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + + if ((PchSeries =3D=3D PchH) && (GPIO_GET_CHIPSET_ID(GpioPad) =3D=3D GPIO= _SKL_H_CHIPSET_ID)) { + return TRUE; + } else if ((PchSeries =3D=3D PchLp) && (GPIO_GET_CHIPSET_ID(GpioPad) =3D= =3D GPIO_SKL_LP_CHIPSET_ID)) { + return TRUE; + } + +DEBUG_CODE_END(); + return FALSE; +} + + +/** + This procedure will get number of pads for certain GPIO group + + @param[in] Group GPIO group number + + @retval Value Pad number for group + If illegal group number then return 0 +**/ +UINT32 +GpioGetPadPerGroup ( + IN GPIO_GROUP Group + ) +{ + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 GroupIndex; + // + // Check if group argument exceeds GPIO GROUP INFO array + // + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + + if ((UINTN)GroupIndex >=3D GpioGroupInfoLength) { + ASSERT(FALSE); + return 0; + } else { + return GpioGroupInfo[GroupIndex].PadPerGroup; + } +} + +/** + This procedure will get number of groups + + @param[in] none + + @retval Value Group number +**/ +UINT8 +GpioGetNumberOfGroups ( + VOID + ) +{ + return V_PCH_H_GPIO_GROUP_MAX; +} +/** + This procedure will get lowest group + + @param[in] none + + @retval Value Lowest Group +**/ +GPIO_GROUP +GpioGetLowestGroup ( + VOID + ) +{ + return (UINT32)GPIO_SKL_H_GROUP_GPP_A; +} +/** + This procedure will get highest group + + @param[in] none + + @retval Value Highest Group +**/ +GPIO_GROUP +GpioGetHighestGroup ( + VOID + ) +{ + return (UINT32)GPIO_SKL_H_GROUP_GPD; +} + +/** + This procedure will get group number + + @param[in] GpioPad Gpio Pad + + @retval Value Group number +**/ +GPIO_GROUP +GpioGetGroupFromGpioPad ( + IN GPIO_PAD GpioPad + ) +{ + return GPIO_GET_GROUP_FROM_PAD (GpioPad); +} + +/** + This procedure will get group index (0 based) + + @param[in] GpioPad Gpio Pad + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGpioPad ( + IN GPIO_PAD GpioPad + ) +{ + return (UINT32)GPIO_GET_GROUP_INDEX_FROM_PAD (GpioPad); +} + +/** + This procedure will get group index (0 based) from group + + @param[in] GpioGroup Gpio Group + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGroup ( + IN GPIO_GROUP GpioGroup + ) +{ + return (UINT32)GPIO_GET_GROUP_INDEX (GpioGroup); +} + +/** + This procedure will get pad number (0 based) from Gpio Pad + + @param[in] GpioPad Gpio Pad + + @retval Value Pad Number +**/ +UINT32 +GpioGetPadNumberFromGpioPad ( + IN GPIO_PAD GpioPad + ) +{ + return (UINT32)GPIO_GET_PAD_NUMBER (GpioPad); +} +/** + This procedure will return GpioPad from Group and PadNumber + + @param[in] Group GPIO group + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupAndPadNumber ( + IN GPIO_GROUP Group, + IN UINT32 PadNumber + ) +{ + return GPIO_PAD_DEF(Group,PadNumber); +} + + + +/** + This function checks if GPIO pin for SATA reset port is in GPIO MODE + + @param[in] SataPort SATA port number + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsSataResetPortInGpioMode ( + IN UINTN SataPort + ) +{ + EFI_STATUS Status; + UINT32 GpioPin; + GPIO_PAD_MODE GpioMode; + + + ASSERT (SataPort < PCH_H_AHCI_MAX_PORTS); + GpioPin =3D mPchHSataPortResetToGpioMap[SataPort].Pad; + + Status =3D GetGpioPadMode (GpioPin, &GpioMode); + if ((EFI_ERROR (Status)) || (GpioMode !=3D GpioPadModeGpio)) { + return FALSE; + } else { + return TRUE; + } +} + + +/** + This function checks if GPIO pin is a SataDevSlp pin + + @param[in] GpioPad GPIO pad + @param[in] PadMode GPIO pad mode + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsPadASataDevSlpPin ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadMode + ) +{ + UINT32 SataDevSlpPinMax; + UINT32 SataDevSlpPinIndex; + GPIO_PAD_OWN PadOwnership; + GPIO_PAD_NATIVE_FUNCTION *SataDevSlpPinToGpioMap; + + SataDevSlpPinToGpioMap =3D mPchHSataDevSlpPinToGpioMap; + SataDevSlpPinMax =3D sizeof(mPchHSataDevSlpPinToGpioMap)/sizeof(GPIO_P= AD_NATIVE_FUNCTION); + + for (SataDevSlpPinIndex =3D 0; SataDevSlpPinIndex < SataDevSlpPinMax; Sa= taDevSlpPinIndex++) { + if ((GpioPad =3D=3D SataDevSlpPinToGpioMap[SataDevSlpPinIndex].Pad) && + (PadMode =3D=3D SataDevSlpPinToGpioMap[SataDevSlpPinIndex].Mode)) { + GpioGetPadOwnership (SataDevSlpPinToGpioMap[SataDevSlpPinIndex].Pad = , &PadOwnership); + if (PadOwnership =3D=3D GpioPadOwnHost) { + return TRUE; + } else { + return FALSE; + } + } + } + return FALSE; +} + +/** + This function checks if SataDevSlp pin is in native mode + + @param[in] SataPort SATA port + @param[out] DevSlpPad DevSlpPad + + @retval TRUE DevSlp is in native mode + FALSE DevSlp is not in native mode +**/ +BOOLEAN +GpioIsSataDevSlpPinEnabled ( + IN UINTN SataPort, + OUT GPIO_PAD *DevSlpPad + ) +{ + GPIO_PAD_MODE DevSlpPadMode; + GPIO_PAD DevSlpGpioPad; + GPIO_PAD_MODE GpioMode; + EFI_STATUS Status; + + ASSERT (SataPort < PCH_H_AHCI_MAX_PORTS); + DevSlpGpioPad =3D mPchHSataDevSlpPinToGpioMap[SataPort].Pad; + DevSlpPadMode =3D mPchHSataDevSlpPinToGpioMap[SataPort].Mode; + + Status =3D GetGpioPadMode (DevSlpGpioPad, &GpioMode); + + if (EFI_ERROR (Status) || (GpioMode !=3D DevSlpPadMode)) { + *DevSlpPad =3D 0x0; + return FALSE; + } else { + *DevSlpPad =3D DevSlpGpioPad; + return TRUE; + } +} + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpi= oLib/PchSklGpioData.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/P= eiDxeSmmGpioLib/PchSklGpioData.c new file mode 100644 index 0000000000..f62e71b9de --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/Pc= hSklGpioData.c @@ -0,0 +1,59 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "GpioLibrary.h" + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_INFO mPchGpioGroupInfo[] =3D { + {PID_GPIOCOM0, R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN, R_PCH_PCR_GPIO_GPP_A_HOS= TSW_OWN, R_PCH_PCR_GPIO_GPP_A_GPI_IS, R_PCH_PCR_GPIO_GPP_A_GPI_IE, = R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_A_GPI_GPE_EN, NO= _REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_A_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_A_PADCFG_O= FFSET, V_PCH_GPIO_GPP_A_PAD_MAX}, //SKX PCH-Server GPP_A + {PID_GPIOCOM0, R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN, R_PCH_PCR_GPIO_GPP_B_HOS= TSW_OWN, R_PCH_PCR_GPIO_GPP_B_GPI_IS, R_PCH_PCR_GPIO_GPP_B_GPI_IE, = R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_B_GPI_GPE_EN, R_= PCH_PCR_GPIO_GPP_B_SMI_STS, R_PCH_PCR_GPIO_GPP_B_SMI_EN, R_PCH_PCR_GPIO_= GPP_B_NMI_STS, R_PCH_PCR_GPIO_GPP_B_NMI_EN, R_PCH_H_PCR_GPIO_GPP_B_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_B_PADCFG_O= FFSET, V_PCH_GPIO_GPP_B_PAD_MAX}, //SKX PCH-Server GPP_B + {PID_GPIOCOM1, R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN, R_PCH_PCR_GPIO_GPP_C_HOS= TSW_OWN, R_PCH_PCR_GPIO_GPP_C_GPI_IS, R_PCH_PCR_GPIO_GPP_C_GPI_IE, = R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_C_GPI_GPE_EN, R_= PCH_PCR_GPIO_GPP_C_SMI_STS, R_PCH_PCR_GPIO_GPP_C_SMI_EN, R_PCH_PCR_GPIO_= GPP_C_NMI_STS, R_PCH_PCR_GPIO_GPP_C_NMI_EN, R_PCH_H_PCR_GPIO_GPP_C_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_C_PADCFG_O= FFSET, V_PCH_GPIO_GPP_C_PAD_MAX}, //SKX PCH-Server GPP_C + {PID_GPIOCOM1, R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN, R_PCH_PCR_GPIO_GPP_D_HOS= TSW_OWN, R_PCH_PCR_GPIO_GPP_D_GPI_IS, R_PCH_PCR_GPIO_GPP_D_GPI_IE, = R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_D_GPI_GPE_EN, R_= PCH_PCR_GPIO_GPP_D_SMI_STS, R_PCH_PCR_GPIO_GPP_D_SMI_EN, R_PCH_PCR_GPIO_= GPP_D_NMI_STS, R_PCH_PCR_GPIO_GPP_D_NMI_EN, R_PCH_H_PCR_GPIO_GPP_D_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_D_PADCFG_O= FFSET, V_PCH_GPIO_GPP_D_PAD_MAX}, //SKX PCH-Server GPP_D + {PID_GPIOCOM1, R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN, R_PCH_PCR_GPIO_GPP_E_HOS= TSW_OWN, R_PCH_PCR_GPIO_GPP_E_GPI_IS, R_PCH_PCR_GPIO_GPP_E_GPI_IE, = R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_E_GPI_GPE_EN, R_= PCH_PCR_GPIO_GPP_E_SMI_STS, R_PCH_PCR_GPIO_GPP_E_SMI_EN, R_PCH_PCR_GPIO_= GPP_E_NMI_STS, R_PCH_PCR_GPIO_GPP_E_NMI_EN, R_PCH_H_PCR_GPIO_GPP_E_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_E_PADCFG_O= FFSET, V_PCH_H_GPIO_GPP_E_PAD_MAX}, //SKX PCH-Server GPP_E + {PID_GPIOCOM0, R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_F_H= OSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_F_GPI_IS, R_PCH_H_PCR_GPIO_GPP_F_GPI_IE, = R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_EN, NO= _REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_F_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_F_PADCFG= _OFFSET, V_PCH_GPIO_GPP_F_PAD_MAX}, //SKX PCH-Server GPP_F + {PID_GPIOCOM5, R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_G_H= OSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_G_GPI_IS, R_PCH_H_PCR_GPIO_GPP_G_GPI_IE, = R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_EN, NO= _REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_G_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_G_PADCFG= _OFFSET, V_PCH_H_GPIO_GPP_G_PAD_MAX}, //SKX PCH-Server GPP_G + {PID_GPIOCOM5, R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_H_H= OSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_H_GPI_IS, R_PCH_H_PCR_GPIO_GPP_H_GPI_IE, = R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_EN, NO= _REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_H_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_H_PADCFG= _OFFSET, V_PCH_H_GPIO_GPP_H_PAD_MAX}, //SKX PCH-Server GPP_H + {PID_GPIOCOM3, R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_I_H= OSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_I_GPI_IS, R_PCH_H_PCR_GPIO_GPP_I_GPI_IE, = R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_EN, R_= PCH_H_PCR_GPIO_GPP_I_SMI_STS,R_PCH_H_PCR_GPIO_GPP_I_SMI_EN, R_PCH_H_PCR_GPI= O_GPP_I_NMI_STS,R_PCH_H_PCR_GPIO_GPP_I_NMI_EN, R_PCH_H_PCR_GPIO_GPP_I_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_I_PADCFG= _OFFSET, V_PCH_H_GPIO_GPP_I_PAD_MAX}, //SKX PCH-Server GPP_I + {PID_GPIOCOM4, R_PCH_H_PCR_GPIO_GPP_J_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_J_H= OSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_J_GPI_IS, R_PCH_H_PCR_GPIO_GPP_J_GPI_IE, = R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_EN, NO= _REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_J_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_J_PADCFG= _OFFSET, V_PCH_H_GPIO_GPP_J_PAD_MAX}, //SKX PCH-Server GPP_J + {PID_GPIOCOM4, R_PCH_H_PCR_GPIO_GPP_K_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_K_H= OSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_K_GPI_IS, R_PCH_H_PCR_GPIO_GPP_K_GPI_IE, = R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_EN, NO= _REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_K_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_K_PADCFG= _OFFSET, V_PCH_H_GPIO_GPP_K_PAD_MAX}, //SKX PCH-Server GPP_K + {PID_GPIOCOM5, R_PCH_H_PCR_GPIO_GPP_L_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_L_H= OSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_L_GPI_IS, R_PCH_H_PCR_GPIO_GPP_L_GPI_IE, = R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_EN, NO= _REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_L_PADCF= GLOCK, R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_L_PADCFG= _OFFSET, V_PCH_H_GPIO_GPP_L_PAD_MAX}, //SKX PCH-Server GPP_L + {PID_GPIOCOM2, R_PCH_H_PCR_GPIO_GPD_PAD_OWN, R_PCH_PCR_GPIO_GPD_HOSTS= W_OWN, R_PCH_PCR_GPIO_GPD_GPI_IS, R_PCH_PCR_GPIO_GPD_GPI_IE, = R_PCH_PCR_GPIO_GPD_GPI_GPE_STS, R_PCH_PCR_GPIO_GPD_GPI_GPE_EN, NO= _REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPD_PADCFGL= OCK, R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPD_PADCFG_OFF= SET, V_PCH_GPIO_GPD_PAD_MAX} //SKX PCH-Server GPD +}; + + +// +// SATA reset port to GPIO pin mapping +// SATAGP_x -> GPIO pin y +// + +GPIO_PAD_NATIVE_FUNCTION mPchHSataPortResetToGpioMap[PCH_H_AHCI_MAX_PORTS]= =3D +{ + {GPIO_SKL_H_GPP_E0, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_E1, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_E2, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F0, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F1, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F2, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F3, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F4, GpioPadModeNative2} +}; + +// +// SATADevSlpPin to GPIO pin mapping +// SATA_DEVSLP_x -> GPIO pin y +// + +GPIO_PAD_NATIVE_FUNCTION mPchHSataDevSlpPinToGpioMap[PCH_H_AHCI_MAX_PORTS]= =3D +{ + {GPIO_SKL_H_GPP_E4, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_E5, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_E6, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F5, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F6, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F7, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F8, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F9, GpioPadModeNative1} +}; diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpi= oLib/PeiDxeSmmGpioLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Libra= ry/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf new file mode 100644 index 0000000000..c1e06f000e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/Pe= iDxeSmmGpioLib.inf @@ -0,0 +1,48 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiDxeSmmGpioLib + FILE_GUID =3D 16EC5CA8-8195-4847-B6CB-662BD7B763F2 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D GpioLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + + + +[LibraryClasses] + BaseLib + IoLib + DebugLib + MmPciLib + PchCycleDecodingLib + PchSbiAccessLib + PchPcrLib #SERVER_BIOS + HobLib + + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + + +[Sources] + GpioLib.c + GpioLibrary.h + GpioNativeLib.c + GpioInit.c + PchSklGpioData.c + +[Guids] + gPlatformGpioConfigGuid diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= CycleDecodingLib/PchCycleDecodingLib.c b/Silicon/Intel/PurleyRefreshSilicon= Pkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c new file mode 100644 index 0000000000..e91546aa1f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDe= codingLib/PchCycleDecodingLib.c @@ -0,0 +1,1169 @@ +/** @file + +Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Set PCH ACPI base address. + The Address should not be 0 and should be 256 bytes alignment, and it is= IO space, so must not exceed 0xFFFF. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. clear PMC PCI offset 44h [7] to diable ACPI base address first before= changing base address. + 2. program PMC PCI offset 40h [15:2] to ACPI base address. + 3. set PMC PCI offset 44h [7] to enable ACPI base address. + 4. program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] to [0x3F= , PMC PCI Offset 40h bit[15:2], 1]. + 5. Program "ACPI Base Destination ID" + For SPT-LP: Program PCR[DMI] + 27B8h[31:0] to 0x23A0 + For SPT-H: Program PCR[DMI] + 27B8h[31:0] to 0x23A8 + + @param[in] Address Address for ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchAcpiBaseSet ( + IN UINT16 Address + ) +{ + UINTN PmcBase; + UINT32 Dmic; + UINT32 Data32; + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + + if (((Address & 0x00FF) !=3D 0) || + (Address =3D=3D 0)) + { + DEBUG((DEBUG_ERROR, "PchAcpiBaseSet Error. Invalid Address: %x.\n", Ad= dress)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) !=3D 0) { + DEBUG((DEBUG_ERROR, "PchAcpiBaseSet Error. DMIC.SRL is set.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + PmcBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + if (MmioRead16 (PmcBase) =3D=3D 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + // + // Disable ABASE in PMC Device first before changing base address. + // + MmioAnd8 ( + PmcBase + R_PCH_PMC_ACPI_CNT, + (UINT8) ~B_PCH_PMC_ACPI_CNT_ACPI_EN + ); + // + // Program ABASE in PMC Device + // + MmioAndThenOr16 ( + PmcBase + R_PCH_PMC_ACPI_BASE, + (UINT16) (~B_PCH_PMC_ACPI_BASE_BAR), + Address + ); + // + // Enable ABASE in PMC Device + // + MmioOr8 ( + PmcBase + R_PCH_PMC_ACPI_CNT, + B_PCH_PMC_ACPI_CNT_ACPI_EN + ); + // + // Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] to [0x3F= , PMC PCI Offset 40h bit[15:2], 1] + // + PchPcrWrite32 ( + PID_DMI, R_PCH_PCR_DMI_ACPIBA, + (0x00FC0001 + Address) + ); + // + // Program "ACPI Base Destination ID" + // For SPT-LP: + // Program PCR[DMI] + 27B8h[31:0] to 0x23A0 + // For SPT-H: + // Program PCR[DMI] + 27B8h[31:0] to 0x23A8 + // + if(PchSeries =3D=3D PchLp){ + Data32 =3D 0x23A0; + } else { + Data32 =3D 0x23A8; + } + PchPcrWrite32 ( + PID_DMI, R_PCH_PCR_DMI_ACPIBDID, + Data32 + ); + return EFI_SUCCESS; +} + +/** + Get PCH ACPI base address. + + @param[out] Address Address of ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchAcpiBaseGet ( + OUT UINT16 *Address + ) +{ + UINTN PmcBase; + + if (Address =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "PchAcpiBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + PmcBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + if (MmioRead16 (PmcBase) =3D=3D 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + *Address =3D MmioRead16 (PmcBase + R_PCH_PMC_ACPI_BASE) & B_PCH_PMC_ACPI= _BASE_BAR; + return EFI_SUCCESS; +} + +/** + Set PCH PWRM base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. clear PMC PCI offset 44h [8] to diable PWRM base address first before= changing PWRM base address. + 2. program PMC PCI offset 48h [31:16] to PM base address. + 3. set PMC PCI offset 44h [8] to enable PWRM base address. + 4. program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to= the same value programmed in PMC PCI Offset 48h bit[31:16], this has an im= plication of making sure the PWRMBASE to be 64KB aligned. + program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] = to the value programmed in PMC PCI Offset 48h bit[31:16], this has an impli= cation of making sure the memory allocated to PWRMBASE to be 64KB in size. + 5. Program "PM Base Control" + For SPT-LP: Program PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A0] + For SPT-H: Program PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A8] + + @param[in] Address Address for PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchPwrmBaseSet ( + IN UINT32 Address + ) +{ + UINTN PmcBase; + UINT32 Dmic; + UINT32 Data32; + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + + if (((Address & (~B_PCH_PMC_PWRM_BASE_BAR)) !=3D 0) || + (Address =3D=3D 0)) + { + DEBUG((DEBUG_ERROR, "PchPwrmBaseSet Error. Invalid Address: %x.\n", Ad= dress)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) !=3D 0) { + DEBUG((DEBUG_ERROR, "PchPwrmBaseSet Error. DMIC.SRL is set.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + PmcBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + if (MmioRead16 (PmcBase) =3D=3D 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + // + // Disable PWRMBASE in PMC Device first before changing PWRM base addres= s. + // + MmioAnd16 ( + PmcBase + R_PCH_PMC_ACPI_CNT, + (UINT16) ~B_PCH_PMC_ACPI_CNT_PWRM_EN + ); + // + // Program PWRMBASE in PMC Device + // + MmioAndThenOr32 ( + PmcBase + R_PCH_PMC_PWRM_BASE, + (UINT32) (~B_PCH_PMC_PWRM_BASE_BAR), + Address + ); + // + // Enable PWRMBASE in PMC Device + // + MmioOr16 ( + PmcBase + R_PCH_PMC_ACPI_CNT, + B_PCH_PMC_ACPI_CNT_PWRM_EN + ); + // + // Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to= the same value programmed in PMC PCI Offset 48h bit[31:16], this has an im= plication of making sure the PWRMBASE to be 64KB aligned. + // Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] = to the value programmed in PMC PCI Offset 48h bit[31:16], this has an impli= cation of making sure the memory allocated to PWRMBASE to be 64KB in size. + // + PchPcrWrite32 ( + PID_DMI, R_PCH_PCR_DMI_PMBASEA, + ((Address & 0xFFFF0000) | (Address >> 16)) + ); + // + // Program "PM Base Control" + // For SPT-LP: + // Program PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A0] + // For SPT-H: + // Program PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A8] + // + if(PchSeries =3D=3D PchLp){ + Data32 =3D 0x800023A0; + } else { + Data32 =3D 0x800023A8; + } + PchPcrWrite32 ( + PID_DMI, R_PCH_PCR_DMI_PMBASEC, + Data32 + ); + return EFI_SUCCESS; +} + +/** + Get PCH PWRM base address. + + @param[out] Address Address of PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchPwrmBaseGet ( + OUT UINT32 *Address + ) +{ + UINTN PmcBase; + + if (Address =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "PchPwrmBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + PmcBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + if (MmioRead16 (PmcBase) =3D=3D 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + *Address =3D MmioRead32 (PmcBase + R_PCH_PMC_PWRM_BASE) & B_PCH_PMC_PWRM= _BASE_BAR; + return EFI_SUCCESS; +} + +/** + Set PCH TCO base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. set Smbus PCI offset 54h [8] to enable TCO base address. + 2. program Smbus PCI offset 50h [15:5] to TCO base address. + 3. set Smbus PCI offset 54h [8] to enable TCO base address. + 4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI of= fset 50h[15:5], 1]. + + @param[in] Address Address for TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchTcoBaseSet ( + IN UINT16 Address + ) +{ + UINTN SmbusBase; + UINT32 Dmic; + + if ((Address & ~B_PCH_SMBUS_TCOBASE_BAR) !=3D 0) { + DEBUG((DEBUG_ERROR, "PchTcoBaseSet Error. Invalid Address: %x.\n", Add= ress)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) !=3D 0) { + DEBUG((DEBUG_ERROR, "PchTcoBaseSet Error. DMIC.SRL is set.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + SmbusBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SMBUS, + PCI_FUNCTION_NUMBER_PCH_SMBUS + ); + if (MmioRead16 (SmbusBase) =3D=3D 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + // + // Verify TCO base is not locked. + // + if ((MmioRead8 (SmbusBase + R_PCH_SMBUS_TCOCTL) & B_PCH_SMBUS_TCOCTL_TCO= _BASE_LOCK) !=3D 0) { + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + // + // Disable TCO in SMBUS Device first before changing base address. + // + MmioAnd8 ( + SmbusBase + R_PCH_SMBUS_TCOCTL + 1, + (UINT8) ~(B_PCH_SMBUS_TCOCTL_TCO_BASE_EN >> 8) + ); + // + // Program TCO in SMBUS Device + // + MmioAndThenOr16 ( + SmbusBase + R_PCH_SMBUS_TCOBASE, + (UINT16) (~B_PCH_SMBUS_TCOBASE_BAR), + Address + ); + // + // Enable TCO in SMBUS Device + // + MmioOr8 ( + SmbusBase + R_PCH_SMBUS_TCOCTL + 1, + (B_PCH_SMBUS_TCOCTL_TCO_BASE_EN >> 8) + ); + // + // Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [SMBUS PCI of= fset 50h[15:5], 1]. + // + PchPcrWrite16 ( + PID_DMI, R_PCH_PCR_DMI_TCOBASE, + (Address | BIT1) + ); + + return EFI_SUCCESS; +} + +/** + Get PCH TCO base address. + + @param[out] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchTcoBaseGet ( + OUT UINT16 *Address + ) +{ + if (Address =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "PchTcoBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + // + // Read "TCO Base Address" PCR[DMI] + 2778h[15:5] + // Don't read TCO base address from SMBUS PCI register since SMBUS might= be disabled. + // + PchPcrRead16 ( + PID_DMI, R_PCH_PCR_DMI_TCOBASE, + Address + ); + *Address &=3D B_PCH_PCR_DMI_TCOBASE_TCOBA; + + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI generic IO range. + For generic IO range, the base address must align to 4 and less than 0xF= FFF, and the length must be power of 2 + and less than or equal to 256. Moreover, the address must be length alig= ned. + This function basically checks the address and length, which should not = overlap with all other generic ranges. + If no more generic range register available, it returns out of resource = error. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Some IO ranges below 0x100 have fixed target. The target might be ITSS,R= TC,LPC,PMC or terminated inside P2SB + but all predefined and can't be changed. IO range below 0x100 will be re= jected in this function except below ranges: + 0x00-0x1F, + 0x44-0x4B, + 0x54-0x5F, + 0x68-0x6F, + 0x80-0x8F, + 0xC0-0xFF + Steps of programming generic IO range: + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. + 2. Program LPC/eSPI Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the = same value programmed in LPC/eSPI PCI Offset 84h~93h. + + @param[in] Address Address for generic IO range base = address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeSet ( + IN UINT16 Address, + IN UINTN Length + , IN UINT8 SlaveDevice + ) +{ + EFI_STATUS Status; + PCH_LPC_GEN_IO_RANGE_LIST LpcGenIoRangeList; + UINTN LpcBase; + UINTN Index; + UINTN BaseAddr; + UINTN MaskLength; + UINTN TempMaxAddr; + UINT32 Data32; + UINTN ArraySize; + static struct EXCEPT_RANGE { + UINT8 Start; + UINT8 Length; + } ExceptRanges[] =3D { {0x00, 0x20}, {0x44, 0x08}, {0x54, 0x0C}, {0x68, = 0x08}, {0x80, 0x10}, {0xC0, 0x40} }; + + Index =3D 0; + // + // Note: Inside this function, don't use debug print since it's could us= ed before debug print ready. + // + + // + // For generic IO range, the base address must align to 4 and less than = 0xFFFF, + // the length must be power of 2 and less than or equal to 256, and the = address must be length aligned. + // IO range below 0x100 will be rejected in this function except below r= anges: + // 0x00-0x1F, + // 0x44-0x4B, + // 0x54-0x5F, + // 0x68-0x6F, + // 0x80-0x8F, + // 0xC0-0xFF + // + if (((Length & (Length - 1)) !=3D 0) || + ((Address & (UINT16)~B_PCH_LPC_GENX_DEC_IOBAR) !=3D 0) || + (Length > 256)) + { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + if (Address < 0x100) { + ArraySize =3D sizeof (ExceptRanges) / sizeof (struct EXCEPT_RANGE); + for (Index =3D 0; Index < ArraySize; Index++) { + if ((Address >=3D ExceptRanges[Index].Start) && + ((Address + Length) <=3D ((UINTN)ExceptRanges[Index].Start + (UI= NTN)ExceptRanges[Index].Length))) + { + break; + } + } + if (Index >=3D ArraySize) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + } + + // + // check if range overlap + // + Status =3D PchLpcGenIoRangeGet (&LpcGenIoRangeList, SlaveDevice); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + if (SlaveDevice =3D=3D LPC_ESPI_FIRST_SLAVE) { + for (Index =3D 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + BaseAddr =3D LpcGenIoRangeList.Range[Index].BaseAddr; + MaskLength =3D LpcGenIoRangeList.Range[Index].Length; + if (BaseAddr =3D=3D 0) { + continue; + } + if (((Address >=3D BaseAddr) && (Address < (BaseAddr + MaskLength)))= || + (((Address + Length) > BaseAddr) && ((Address + Length) <=3D (Ba= seAddr + MaskLength)))) + { + if ((Address >=3D BaseAddr) && (Length <=3D MaskLength)) { + // + // return SUCCESS while range is covered. + // + return EFI_SUCCESS; + } + + if ((Address + Length) > (BaseAddr + MaskLength)) { + TempMaxAddr =3D Address + Length; + } else { + TempMaxAddr =3D BaseAddr + MaskLength; + } + if (Address > BaseAddr) { + Address =3D (UINT16) BaseAddr; + } + Length =3D TempMaxAddr - Address; + break; + } + } + // + // If no range overlap + // + if (Index >=3D PCH_LPC_GEN_IO_RANGE_MAX) { + // + // Find a empty register + // + for (Index =3D 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + BaseAddr =3D LpcGenIoRangeList.Range[Index].BaseAddr; + if (BaseAddr =3D=3D 0) { + break; + } + } + if (Index >=3D PCH_LPC_GEN_IO_RANGE_MAX) { + return EFI_OUT_OF_RESOURCES; + } + } + } else { + BaseAddr =3D LpcGenIoRangeList.Range[0].BaseAddr; + MaskLength =3D LpcGenIoRangeList.Range[0].Length; + if (BaseAddr !=3D 0) { + if (((Address >=3D BaseAddr) && (Address < (BaseAddr + MaskLength)))= || + (((Address + Length) > BaseAddr) && ((Address + Length) <=3D (Ba= seAddr + MaskLength)))) + { + if ((Address >=3D BaseAddr) && (Length <=3D MaskLength)) { + // + // return SUCCESS while range is covered. + // + return EFI_SUCCESS; + } else { + return EFI_OUT_OF_RESOURCES; + } + } + } + } + // + // This cycle decoding is only allowed to set when DMIC.SRL is 0. + // + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Data32); + if ((Data32 & B_PCH_PCR_DMI_DMIC_SRL) !=3D 0) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // Program LPC/eSPI generic IO range register accordingly. + // + LpcBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + Data32 =3D (UINT32) (((Length - 1) << 16) & B_PCH_LPC_GENX_DEC_IODRA); + Data32 |=3D (UINT32) Address; + Data32 |=3D B_PCH_LPC_GENX_DEC_EN; + + if (SlaveDevice =3D=3D LPC_ESPI_FIRST_SLAVE) { + // + // Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. + // + MmioWrite32 ( + LpcBase + R_PCH_LPC_GEN1_DEC + Index * 4, + Data32 + ); + // + // Program LPC Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the sam= e value programmed in LPC/eSPI PCI Offset 84h~93h. + // + PchPcrWrite32 ( + PID_DMI, (UINT16) (R_PCH_PCR_DMI_LPCLGIR1 + Index * 4), + Data32 + ); + } else { + ASSERT(FALSE); + } + return EFI_SUCCESS; +} + +/** + Get PCH LPC/eSPI generic IO range list. + This function returns a list of base address, length, and enable for all= LPC/eSPI generic IO range regsiters. + + @param[out] LpcGenIoRangeList Return all LPC/eSPI generic IO ran= ge register status. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeGet ( + OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList + , IN UINT8 SlaveDevice + ) +{ + UINTN Index; + UINTN LpcBase; + UINT32 Data32; + + // + // Note: Inside this function, don't use debug print since it's could us= ed before debug print ready. + // + + if (LpcGenIoRangeList =3D=3D NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + LpcBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + if (SlaveDevice =3D=3D LPC_ESPI_FIRST_SLAVE) { + for (Index =3D 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + Data32 =3D MmioRead32 (LpcBase + R_PCH_LPC_GEN1_DEC + Index * 4); + LpcGenIoRangeList->Range[Index].BaseAddr =3D Data32 & B_PCH_LPC_GENX= _DEC_IOBAR; + LpcGenIoRangeList->Range[Index].Length =3D ((Data32 & B_PCH_LPC_GE= NX_DEC_IODRA) >> 16) + 4; + LpcGenIoRangeList->Range[Index].Enable =3D Data32 & B_PCH_LPC_GENX= _DEC_EN; + } + } else { + ASSERT(FALSE); + } + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI memory range decoding. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program LPC/eSPI PCI Offset 98h [0] to [0] to disable memory decoding= first before changing base address. + 2. Program LPC/eSPI PCI Offset 98h [31:16, 0] to [Address, 1]. + 3. Program LPC/eSPI Memory Range, PCR[DMI] + 2740h to the same value pro= grammed in LPC/eSPI PCI Offset 98h. + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeSet ( + IN UINT32 Address + , IN UINT8 SlaveDevice + ) +{ + UINTN LpcBase; + UINT32 Dmic; + UINTN LpcReg; + UINT16 DmiReg; + + if ((Address & (~B_PCH_LPC_LGMR_MA)) !=3D 0) { + DEBUG((DEBUG_ERROR, "PchLpcMemRangeSet Error. Invalid Address: %x.\n",= Address)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) !=3D 0) { + DEBUG((DEBUG_ERROR, "PchLpcMemRangeSet Error. DMIC.SRL is set.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + LpcBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + if (SlaveDevice =3D=3D ESPI_SECONDARY_SLAVE) { + ASSERT(FALSE); + } else { + LpcReg =3D LpcBase + R_PCH_LPC_LGMR; + DmiReg =3D R_PCH_PCR_DMI_LPCGMR; + } + // + // Program LPC/eSPI PCI Offset 98h [0] (LPC/ePSI first slave) or A8h [0]= (eSPI secondary slave) to [0] to disable memory decoding first before chan= ging base address. + // + MmioAnd32 ( + LpcReg, + (UINT32) ~B_PCH_LPC_LGMR_LMRD_EN + ); + // + // Program LPC/eSPI PCI Offset 98h [31:16, 0] (LPC/ eSPI first slave) or= A8h [31:16, 0] (eSPI secondary slave) to [Address, 1]. + // + MmioWrite32 ( + LpcReg, + (Address | B_PCH_LPC_LGMR_LMRD_EN) + ); + // + // Program LPC Memory Range, PCR[DMI] + 2740h (LPC/eSPI first slave) or = 27C0h (eSPI secondary slave) to the same value programmed in LPC/eSPI PCI O= ffset 98h. + // + PchPcrWrite32 ( + PID_DMI, DmiReg, + (Address | B_PCH_LPC_LGMR_LMRD_EN) + ); + return EFI_SUCCESS; +} + +/** + Get PCH LPC/eSPI memory range decoding address. + + @param[out] Address Address of LPC/eSPI memory decodin= g base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeGet ( + OUT UINT32 *Address + , IN UINT8 SlaveDevice + ) +{ + UINTN LpcBase; + + if (Address =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "PchLpcMemRangeGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + LpcBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + if (SlaveDevice =3D=3D LPC_ESPI_FIRST_SLAVE) { + *Address =3D MmioRead32 (LpcBase + R_PCH_LPC_LGMR) & B_PCH_LPC_LGMR_MA; + } else { + ASSERT(FALSE); + } + return EFI_SUCCESS; +} + +/** + Set PCH BIOS range deocding. + This will check General Control and Status bit 10 (GCS.BBS) to identify = SPI or LPC/eSPI and program BDE register accordingly. + Please check EDS for detail of BiosDecodeEnable bit definition. + bit 15: F8-FF Enable + bit 14: F0-F8 Enable + bit 13: E8-EF Enable + bit 12: E0-E8 Enable + bit 11: D8-DF Enable + bit 10: D0-D7 Enable + bit 9: C8-CF Enable + bit 8: C0-C7 Enable + bit 7: Legacy F Segment Enable + bit 6: Legacy E Segment Enable + bit 5: Reserved + bit 4: Reserved + bit 3: 70-7F Enable + bit 2: 60-6F Enable + bit 1: 50-5F Enable + bit 0: 40-4F Enable + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. if GCS.BBS is 0 (SPI), program SPI offset D8h to BiosDecodeEnable. + if GCS.BBS is 1 (LPC/eSPi), program LPC offset D8h to BiosDecodeEnabl= e. + 2. program LPC BIOS Decode Enable, PCR[DMI] + 2744h to the same value pr= ogrammed in LPC or SPI Offset D8h. + + @param[in] BiosDecodeEnable Bios decode enable setting. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchBiosDecodeEnableSet ( + IN UINT16 BiosDecodeEnable + ) +{ + UINTN BaseAddr; + UINT32 DmiGcsBbs; + UINT32 Dmic; + + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) !=3D 0) { + DEBUG((DEBUG_ERROR, "PchBiosDecodeEnableSet Error. DMIC.SRL is set.\n"= )); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_GCS, &DmiGcsBbs); + DmiGcsBbs &=3D B_PCH_PCR_DMI_BBS; + // + // Check General Control and Status (GCS) [10] + // '0': SPI + // '1': LPC/eSPI + // + if (DmiGcsBbs =3D=3D 0) { + BaseAddr =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI + ); + // + // if GCS.BBS is 0 (SPI), program SPI offset D8h to BiosDecodeEnable. + // + MmioWrite16 (BaseAddr + R_PCH_SPI_BDE, BiosDecodeEnable); + } else { + BaseAddr =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + // + // if GCS.BBS is 1 (LPC/eSPi), program LPC offset D8h to BiosDecodeEna= ble. + // + MmioWrite16 (BaseAddr + R_PCH_LPC_BDE, BiosDecodeEnable); + } + + // + // program LPC BIOS Decode Enable, PCR[DMI] + 2744h to the same value pr= ogrammed in LPC or SPI Offset D8h. + // + PchPcrWrite16 (PID_DMI, R_PCH_PCR_DMI_LPCBDE, BiosDecodeEnable); + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI IO decode ranges. + Program LPC/eSPI I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same v= alue programmed in LPC/eSPI PCI offset 80h. + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit sett= ings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ) +{ + UINTN LpcBaseAddr; + UINT32 Dmic; + + // + // Note: Inside this function, don't use debug print since it's could us= ed before debug print ready. + // + + LpcBaseAddr =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + // + // check if setting is identical + // + if (LpcIoDecodeRanges =3D=3D MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOD)) { + return EFI_SUCCESS; + } + + // + // This cycle decoding is only allowed to set when DMIC.SRL is 0. + // + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) !=3D 0) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // program LPC/eSPI PCI offset 80h. + // + MmioWrite16 (LpcBaseAddr + R_PCH_LPC_IOD, LpcIoDecodeRanges); + + // + // program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same val= ue programmed in LPC/eSPI PCI offset 80h. + // + PchPcrWrite16 (PID_DMI, R_PCH_PCR_DMI_LPCIOD, LpcIoDecodeRanges); + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI IO enable decoding. + Setup LPC/eSPI I/O Enables, PCR[DMI] + 2774h[15:0] to the same value pro= gram in LPC/eSPI PCI offset 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtract= ive agent for handling. + Please check EDS for detail of Lpc/eSPI IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit se= ttings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + , IN UINT8 SlaveDevice + ) +{ + UINTN LpcBaseAddr; + UINT32 Dmic; + UINTN LpcReg; + + if (SlaveDevice =3D=3D LPC_ESPI_FIRST_SLAVE) { + LpcReg =3D R_PCH_LPC_IOE; + } else { + ASSERT(FALSE); + } + + // + // Note: Inside this function, don't use debug print since it's could us= ed before debug print ready. + // + + LpcBaseAddr =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + if (LpcIoEnableDecoding =3D=3D MmioRead16 (LpcBaseAddr + LpcReg)) { + return EFI_SUCCESS; + } + // + // This cycle decoding is only allowed to set when DMIC.SRL is 0. + // + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) !=3D 0) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // program PCI offset 82h for LPC/eSPI CS#0 or offset A0h for eSPI CS#1. + // + MmioWrite16 (LpcBaseAddr + LpcReg, LpcIoEnableDecoding); + + if (SlaveDevice =3D=3D ESPI_SECONDARY_SLAVE) { + // + // For eSPI CS#1 device program PCI offset 82h respectively + // + MmioWrite16 (LpcBaseAddr + R_PCH_LPC_IOE, (LpcIoEnableDecoding | MmioR= ead16(LpcBaseAddr + R_PCH_LPC_IOE))); + } + + // + // program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same val= ue programmed in LPC/eSPI PCI offset 82h. + // + PchPcrWrite16 (PID_DMI, R_PCH_PCR_DMI_LPCIOE, LpcIoEnableDecoding); + return EFI_SUCCESS; +} + + +// +// PCH-LP RPR destination ID table +// +UINT16 PchLpRprDidTable[] =3D { + 0x2188, // Dest ID of RP1 + 0x2189, // Dest ID of RP2 + 0x218A, // Dest ID of RP3 + 0x218B, // Dest ID of RP4 + 0x2198, // Dest ID of RP5 + 0x2199, // Dest ID of RP6 + 0x219A, // Dest ID of RP7 + 0x219B, // Dest ID of RP8 + 0x21A8, // Dest ID of RP9 + 0x21A9, // Dest ID of RP10 + 0x21AA, // Dest ID of RP11 + 0x21AB // Dest ID of RP12 +}; + +// +// PCH-H RPR destination ID table +// +UINT16 PchHRprDidTable[] =3D { + 0x2180, // Dest ID of RP1 + 0x2181, // Dest ID of RP2 + 0x2182, // Dest ID of RP3 + 0x2183, // Dest ID of RP4 + 0x2188, // Dest ID of RP5 + 0x2189, // Dest ID of RP6 + 0x218A, // Dest ID of RP7 + 0x218B, // Dest ID of RP8 + 0x2198, // Dest ID of RP9 + 0x2199, // Dest ID of RP10 + 0x219A, // Dest ID of RP11 + 0x219B, // Dest ID of RP12 + 0x21A8, // Dest ID of RP13 + 0x21A9, // Dest ID of RP14 + 0x21AA, // Dest ID of RP15 + 0x21AB, // Dest ID of RP16 + 0x21B8, // Dest ID of RP17 + 0x21B9, // Dest ID of RP18 + 0x21BA, // Dest ID of RP19 + 0x21BB, // Dest ID of RP20 +}; + +/** + Set PCH IO port 80h cycle decoding to PCIE root port. + System BIOS is likely to do this very soon after reset before PCI bus en= umeration. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID = of RP. + 2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte = write on GCS+1 and leave the BILD bit which is RWO. + + @param[in] RpPhyNumber PCIE root port physical number. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +EFIAPI +PchIoPort80DecodeSet ( + IN UINTN RpPhyNumber + ) +{ + UINT32 Dmic; + UINT16 *PchRprDidTable; + + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) !=3D 0) { + DEBUG((DEBUG_ERROR, "PchIoPort80DecodeSet Error. DMIC.SRL is set.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + /// + /// IO port 80h is typically used by decoder/LED hardware for debug purp= oses. + /// By default PCH will forward IO port 80h cycles to LPC bus. The Reser= ved Page Route (RPR) bit + /// of General Control and Status register, located at PCR[DMI] + 274Ch[= 11] , allows software to + /// re-direct IO port 80h cycles to PCIe bus so that a target (for examp= le, a debug card) on + /// PCIe bus can receive and claim these cycles. + /// The "RPR Destination ID", PCR[DMI] + 274Ch[31:16] need to be set acc= ordingly to point + /// to the root port that decode this range. Reading from Port 80h may n= ot return valid values + /// if the POST-card itself do not shadow the writes. Unlike LPC, PCIe d= oes not shadow the Port 80 writes. + /// + + if (GetPchSeries () =3D=3D PchLp) { + PchRprDidTable =3D PchLpRprDidTable; + } else { + PchRprDidTable =3D PchHRprDidTable; + } + + // + // Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID = of RP. + // + PchPcrWrite16 (PID_DMI, R_PCH_PCR_DMI_GCS + 2, PchRprDidTable[RpPhyNumbe= r]); + // + // Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. + // Use byte write on GCS+1 and leave the BILD bit which is RWO. + // + PchPcrAndThenOr8 (PID_DMI, R_PCH_PCR_DMI_GCS + 1, 0xFF, (B_PCH_PCR_DMI_R= PR >> 8)); + + return EFI_SUCCESS; +} + +/** + Get IO APIC regsiters base address. + It returns IO APIC INDEX, DATA, and EOI regsiter address once the parame= ter is not NULL. + This function will be unavailable after P2SB is hidden by PSF. + + @param[out] IoApicIndex Buffer of IO APIC INDEX regsiter a= ddress + @param[out] IoApicData Buffer of IO APIC DATA regsiter ad= dress + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchIoApicBaseGet ( + OPTIONAL OUT UINT32 *IoApicIndex, + OPTIONAL OUT UINT32 *IoApicData + ) +{ + EFI_STATUS Status; + UINT16 RegIoac; + UINT32 RangeSelect; + + Status =3D PchP2sbCfgGet16 (R_PCH_P2SB_IOAC, &RegIoac); + if (EFI_ERROR (Status)) { + return Status; + } + + RangeSelect =3D (RegIoac & B_PCH_P2SB_IOAC_ASEL) << N_PCH_IO_APIC_ASEL; + + if (IoApicIndex !=3D NULL) { + *IoApicIndex =3D R_PCH_IO_APIC_INDEX + RangeSelect; + } + if (IoApicData !=3D NULL) { + *IoApicData =3D R_PCH_IO_APIC_DATA + RangeSelect; + } + + return EFI_SUCCESS; +} + +/** + Get HPET base address. + This function will be unavailable after P2SB is hidden by PSF. + + @param[out] HpetBase Buffer of HPET base address + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchHpetBaseGet ( + OUT UINT32 *HpetBase + ) +{ + EFI_STATUS Status; + UINT8 RegHptc; + + if (HpetBase =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "PchHpetBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Status =3D PchP2sbCfgGet8 (R_PCH_P2SB_HPTC, &RegHptc); + + switch (RegHptc & B_PCH_P2SB_HPTC_AS) { + case 0: + *HpetBase =3D V_PCH_HPET_BASE0; + break; + case 1: + *HpetBase =3D V_PCH_HPET_BASE1; + break; + case 2: + *HpetBase =3D V_PCH_HPET_BASE2; + break; + case 3: + *HpetBase =3D V_PCH_HPET_BASE3; + break; + default: + break; + } + + return Status; +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= CycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf b/Silicon/Intel/PurleyRef= reshSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDe= codingLib.inf new file mode 100644 index 0000000000..9e14d40365 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDe= codingLib/PeiDxeSmmPchCycleDecodingLib.inf @@ -0,0 +1,33 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiDxeSmmPchCycleDecodingLib + FILE_GUID =3D 676C749F-9CD1-46B7-BAFD-4B1BC36B4C8E + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PchCycleDecodingLib + + +[LibraryClasses] + BaseLib + IoLib + DebugLib + MmPciLib + PchInfoLib + PchPcrLib + PchP2sbLib + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + + +[Sources] + PchCycleDecodingLib.c diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= GbeLib/PchGbeLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiD= xeSmmPchGbeLib/PchGbeLib.c new file mode 100644 index 0000000000..181334cce9 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/= PchGbeLib.c @@ -0,0 +1,160 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +extern EFI_GUID gPeiSpiPpiGuid; +/** + Check whether GbE region is valid + Check SPI region directly since GbE might be disabled in SW. + + @retval TRUE Gbe Region is valid + @retval FALSE Gbe Region is invalid +**/ +BOOLEAN +PchIsGbeRegionValid ( + VOID + ) +{ + UINT32 SpiBar; + SpiBar =3D MmioRead32 (MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI) + + R_PCH_SPI_BAR0) & ~B_PCH_SPI_BAR0_MASK; + ASSERT (SpiBar !=3D 0); + if (MmioRead32 (SpiBar + R_PCH_SPI_FREG3_GBE) !=3D B_PCH_SPI_FREGX_BASE_= MASK) { + return TRUE; + } + return FALSE; +} + +/** + Returns GbE over PCIe port number based on a soft strap. + + @return Root port number (1-based) + @retval 0 GbE over PCIe disabled +**/ +UINT32 +PchGetGbePortNumber ( + VOID + ) +{ + UINT32 GbePortSel; + UINT32 PcieStrapFuse; + + PchPcrRead32 (PID_FIAWM26, R_PCH_PCR_FIA_STRPFUSECFG1_REG_BASE, &PcieStr= apFuse); + if ((PcieStrapFuse & B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIE_PEN) =3D=3D 0) { + return 0; // GbE disabled + } + GbePortSel =3D (PcieStrapFuse & B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTS= EL) >> N_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL; + + switch (GbePortSel) { + case 0: return 3 + 1; + case 1: return 4 + 1; + case 2: return 5 + 1; + case 3: return 8 + 1; + case 4: return 11 + 1; + } + + DEBUG((DEBUG_ERROR, "Invalid GbE port\n")); + ASSERT (FALSE); + return 0; +} + +/** + Check whether LAN controller is enabled in the platform. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbePresent ( + VOID + ) +{ + + UINT32 SoftstrapVal; + EFI_SPI_PROTOCOL *SpiProtocol =3D NULL; + EFI_STATUS Status; + UINTN GbePciBase; + + if (PchIsDwrFlow() =3D=3D TRUE) { + return FALSE; + } + + GbePciBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LAN, + PCI_FUNCTION_NUMBER_PCH_LAN + ); + + // + // Check GBE disable strap + // + Status =3D PeiServicesLocatePpi ( + &gPeiSpiPpiGuid, + 0, + NULL, + (VOID **) &SpiProtocol + ); + ASSERT_EFI_ERROR (Status); + + Status =3D SpiProtocol->ReadPchSoftStrap(SpiProtocol, 0x1DC, 4, &Softstr= apVal); + if (!EFI_ERROR(Status)) { + if ((SoftstrapVal & BIT14) =3D=3D BIT14) { + return FALSE; + } + } + // + // Check FIA strap/fuse + // + if (PchGetGbePortNumber () =3D=3D 0) { + return FALSE; + } + // + // Check GbE NVM + // + if (PchIsGbeRegionValid () =3D=3D FALSE) { + return FALSE; + } + if (MmioRead32 (GbePciBase) =3D=3D 0xFFFFFFFF) { + return FALSE; + } + return TRUE; +} + +/** + Check whether LAN controller is enabled in the platform. + + @deprecated Use PchIsGbePresent instead. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbeAvailable ( + VOID + ) +{ + return PchIsGbePresent (); +} + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= GbeLib/PeiDxeSmmPchGbeLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/L= ibrary/PeiDxeSmmPchGbeLib/PeiDxeSmmPchGbeLib.inf new file mode 100644 index 0000000000..93e31f8cf4 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/= PeiDxeSmmPchGbeLib.inf @@ -0,0 +1,37 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiDxeSmmPchGbeLib + FILE_GUID =3D FC022ED0-6EB3-43E1-A740-0BA27CBBD010 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PchGbeLib + + +[LibraryClasses] + BaseLib + IoLib + DebugLib + MmPciLib + PchInfoLib + PchPcrLib + PchCycleDecodingLib + PchPmcLib #SERVER_BIOS + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Sources] + PchGbeLib.c + +[Ppis] + gPeiSpiPpiGuid + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= InfoLib/PchInfoLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/Pe= iDxeSmmPchInfoLib/PchInfoLib.c new file mode 100644 index 0000000000..ef77a342d6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib= /PchInfoLib.c @@ -0,0 +1,505 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCH_DO_STRINGIFY(x) #x +#define PCH_STRINGIFY(x) PCH_DO_STRINGIFY(x) + +// +// This module variables are used for cache the static result. +// @note: please pay attention to the PEI phase, the module variables on R= OM +// and can't be modified. +// +GLOBAL_REMOVE_IF_UNREFERENCED UINTN mLpcBaseAddr =3D 0; +GLOBAL_REMOVE_IF_UNREFERENCED PCH_STEPPING mPchStepping =3D PchSt= eppingMax; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mIsPchSupported =3D 0xFF; +GLOBAL_REMOVE_IF_UNREFERENCED PCH_SERIES mPchSeries =3D PchUn= knownSeries; +GLOBAL_REMOVE_IF_UNREFERENCED PCH_GENERATION mPchGeneration =3D PchUn= knownGeneration; + +/** + Return Pch stepping type + + @retval PCH_STEPPING Pch stepping type +**/ +PCH_STEPPING +EFIAPI +PchStepping ( + VOID + ) +{ + UINT8 RevId; + UINT16 LpcDeviceId; + UINTN LpcBaseAddress; + + if (mPchStepping !=3D PchSteppingMax) { + return mPchStepping; + } + + LpcBaseAddress =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + RevId =3D MmioRead8 (LpcBaseAddress + PCI_REVISION_ID_OFFSET); + + LpcDeviceId =3D MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET); + + if (IS_PCH_H_LPC_DEVICE_ID (LpcDeviceId)) { + switch (RevId) { + case V_PCH_LPC_RID_0: + mPchStepping =3D PchHA0; + return PchHA0; + + case V_PCH_LPC_RID_10: + mPchStepping =3D PchHB0; + return PchHB0; + + case V_PCH_LPC_RID_20: + mPchStepping =3D PchHC0; + return PchHC0; + + case V_PCH_LPC_RID_30: + mPchStepping =3D PchHD0; + return PchHD0; + + case V_PCH_LPC_RID_31: + mPchStepping =3D PchHD1; + return PchHD1; + + default: + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH ste= pping starting from %a and above\n", PCH_STRINGIFY(PCH_H_MIN_SUPPORTED_STEP= PING))) ; + return PchSteppingMax; + } + } + + if (IS_PCH_LP_LPC_DEVICE_ID (LpcDeviceId)) { + switch (RevId) { +#ifdef SIMICS_FLAG + case V_PCH_LPC_RID_0: + mPchStepping =3D PchLpA0; + return PchLpA0; +#endif + + case V_PCH_LPC_RID_10: + mPchStepping =3D PchLpB0; + return PchLpB0; + + case V_PCH_LPC_RID_11: + mPchStepping =3D PchLpB1; + return PchLpB1; + + case V_PCH_LPC_RID_20: + mPchStepping =3D PchLpC0; + return PchLpC0; + + case V_PCH_LPC_RID_21: + mPchStepping =3D PchLpC1; + return PchLpC1; + + default: + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH ste= pping starting from %a and above\n", PCH_STRINGIFY(PCH_LP_MIN_SUPPORTED_STE= PPING))) ; + return PchSteppingMax; + } + } + +#ifdef SKXD_EN + if (IS_PCH_LBG_D_SSKU_LPC_DEVICE_ID (LpcDeviceId)) { + switch (RevId) { + case V_PCH_LBG_LPC_RID_3: + return LbgB1_D; + default: + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH ste= pping starting from %s and above\n", PCH_STRINGIFY(V_PCH_LBG_LPC_RID_3))); + return PchSteppingMax; + } + } +#endif // SKXD_EN + + if (IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId)) { + if (RevId =3D=3D 0) { + return LbgA0; + } else { + switch (RevId) { + case V_PCH_LBG_LPC_RID_0: + return LbgA0; + case V_PCH_LBG_LPC_RID_2: + return LbgB0; + case V_PCH_LBG_LPC_RID_3: + return LbgB1; + case V_PCH_LBG_LPC_RID_4: + return LbgB2; + case V_PCH_LBG_LPC_RID_8: + return LbgS0; + case V_PCH_LBG_LPC_RID_9: + return LbgS1; + default: + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH ste= pping starting from %s and above\n", PCH_STRINGIFY(PCH_LBG_MIN_SUPPORTED_ST= EPPING))); + ASSERT (FALSE); + return PchSteppingMax; + } + } + } + return PchSteppingMax; +} + +/** + Determine if PCH is supported + + @retval TRUE PCH is supported + @retval FALSE PCH is not supported +**/ +BOOLEAN +IsPchSupported ( + VOID + ) +{ + UINT16 LpcDeviceId; + UINT16 LpcVendorId; + UINTN LpcBaseAddress; + + if (mIsPchSupported !=3D 0xFF) { + return (BOOLEAN) mIsPchSupported; + } + + LpcBaseAddress =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + LpcDeviceId =3D MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET); + LpcVendorId =3D MmioRead16 (LpcBaseAddress + PCI_VENDOR_ID_OFFSET); + + /// + /// Verify that this is a supported chipset + /// + if ((LpcVendorId =3D=3D V_PCH_LPC_VENDOR_ID) && + (IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId))) + { + mIsPchSupported =3D TRUE; + return TRUE; + } else { + DEBUG ((DEBUG_ERROR, "PCH code doesn't support the LpcDeviceId: 0x%04x= !\n", LpcDeviceId)); + mIsPchSupported =3D FALSE; + return FALSE; + } +} + +/** + Return Pch Series + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +EFIAPI +GetPchSeries ( + VOID + ) +{ + UINT16 LpcDeviceId; + UINT32 PchSeries; + UINTN LpcBaseAddress; + + if (mPchSeries !=3D PchUnknownSeries) { + return mPchSeries; + } + + LpcBaseAddress =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + LpcDeviceId =3D MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET); + + if (IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId)) { + PchSeries =3D PchH; + } else if (IS_PCH_LP_LPC_DEVICE_ID (LpcDeviceId)) { + PchSeries =3D PchLp; + } else { + PchSeries =3D PchUnknownSeries; + DEBUG ((DEBUG_ERROR, "Unsupported PCH SKU, LpcDeviceId: 0x%04x!\n", Lp= cDeviceId)); + ASSERT (FALSE); + } + mPchSeries =3D PchSeries; + + return PchSeries; +} + +/** + Return Pch Generation + + @retval PCH_GENERATION Pch Generation +**/ +PCH_GENERATION +EFIAPI +GetPchGeneration ( + VOID + ) +{ + UINT16 LpcDeviceId; + UINT32 PchGen; + UINTN LpcBaseAddress; + + if (mPchGeneration !=3D PchUnknownGeneration) { + return mPchGeneration; + } + + LpcBaseAddress =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + LpcDeviceId =3D MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET); + + if (IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId)) { + PchGen =3D SklPch; + } else { + PchGen =3D PchUnknownGeneration; + DEBUG ((DEBUG_ERROR, "Unsupported PCH SKU, LpcDeviceId: 0x%04x!\n", Lp= cDeviceId)); + ASSERT (FALSE); + } + mPchGeneration =3D PchGen; + + return PchGen; +} + +/** + Get Pch Maximum Pcie Root Port Number + + @retval Pch Maximum Pcie Root Port Number +**/ +UINT8 +EFIAPI +GetPchMaxPciePortNum ( + VOID + ) +{ + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + switch (PchSeries) { + case PchLp: + return PCH_LP_PCIE_MAX_ROOT_PORTS; + + case PchH: + return PCH_H_PCIE_MAX_ROOT_PORTS; + + default: + return 0; + } +} + + +/** + Get Pch Maximum Sata Port Number + + @retval Pch Maximum Sata Port Number +**/ +UINT8 +EFIAPI +GetPchMaxSataPortNum ( + VOID + ) +{ + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + switch (PchSeries) { + case PchLp: + return PCH_LP_AHCI_MAX_PORTS; + + case PchH: + return PCH_H_AHCI_MAX_PORTS; + + default: + return 0; + } +} + +/** + Get Pch Usb Maximum Physical Port Number + + @retval Pch Usb Maximum Physical Port Number +**/ +UINT8 +EFIAPI +GetPchUsbMaxPhysicalPortNum ( + VOID + ) +{ + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + switch (PchSeries) { + case PchLp: + return PCH_LP_XHCI_MAX_USB2_PHYSICAL_PORTS; + + case PchH: + return PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS; + + default: + return 0; + } +} + +/** + Get Pch Maximum Usb2 Port Number of XHCI Controller + + @retval Pch Maximum Usb2 Port Number of XHCI Controller +**/ +UINT8 +EFIAPI +GetPchXhciMaxUsb2PortNum ( + VOID + ) +{ + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + switch (PchSeries) { + case PchLp: + return PCH_LP_XHCI_MAX_USB2_PORTS; + + case PchH: + return PCH_H_XHCI_MAX_USB2_PORTS; + + default: + return 0; + } +} + +/** + Get Pch Maximum Usb3 Port Number of XHCI Controller + + @retval Pch Maximum Usb3 Port Number of XHCI Controller +**/ +UINT8 +EFIAPI +GetPchXhciMaxUsb3PortNum ( + VOID + ) +{ + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + switch (PchSeries) { + case PchLp: + return PCH_LP_XHCI_MAX_USB3_PORTS; + + case PchH: + return PCH_H_XHCI_MAX_USB3_PORTS; + + default: + return 0; + } +} + +/** + Determine if sSata controller is present or not + + @param[in] None + + @retval TRUE or FALSE +**/ +BOOLEAN +EFIAPI +GetIsPchsSataPresent ( + VOID + ) +{ + UINT16 sSataDeviceId; + UINTN sSataBaseAddress; + + sSataBaseAddress =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_EVA, + PCI_FUNCTION_NUMBER_PCH_SSATA + ); + + sSataDeviceId =3D MmioRead16 ( sSataBaseAddress + PCI_DEVICE_ID_OFFSET); + + if (sSataDeviceId !=3D 0xffff){ + return TRUE; + } + + return FALSE; +} + + +/** + Get Pch Maximum sSata Controller Number + + @param[in] None + + @retval Pch Maximum sSata Controller Number +**/ + +UINT8 +EFIAPI +GetPchMaxsSataPortNum ( + VOID + ) +{ + return PCH_SSATA_MAX_PORTS; +} + +/** + + Get Pch Maximum Sata Controller Number + + @param[in] None + + @retval Pch Maximum Sata Controller Number + +**/ +UINT8 +EFIAPI +GetPchMaxsSataControllerNum ( + VOID + ) +{ + return PCH_SSATA_MAX_CONTROLLERS; +} + +/** + Return Pch Lpc Device Id + + @retval UINT16 Pch DeviceId +**/ +UINT16 +EFIAPI +GetPchLpcDeviceId ( + VOID + ) +{ + UINTN LpcBaseAddress; + + if (mPchSeries !=3D PchUnknownSeries) { + return mPchSeries; + } + + LpcBaseAddress =3D mLpcBaseAddr; + if (LpcBaseAddress =3D=3D 0) { + LpcBaseAddress =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + mLpcBaseAddr =3D LpcBaseAddress; + } + + return MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET); +} + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= InfoLib/PchInfoStrLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library= /PeiDxeSmmPchInfoLib/PchInfoStrLib.c new file mode 100644 index 0000000000..e13b7877af --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib= /PchInfoStrLib.c @@ -0,0 +1,291 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Structure for PCH stepping string mapping +**/ +struct PCH_STEPPING_STRING { + PCH_STEPPING Stepping; + CHAR8 *String; +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +struct PCH_STEPPING_STRING mSteppingStrs[] =3D { + {PchHA0, "A0"}, + {PchHB0, "B0"}, + {PchHC0, "C0"}, + {PchHD0, "D0"}, + {PchHD1, "D1"}, +#ifdef SIMICS_FLAG + {PchLpA0, "A0"}, +#endif + {PchLpB0, "B0"}, + {PchLpB1, "B1"}, + {PchLpC0, "C0"}, + {PchLpC1, "C1"}, + {LbgA0, "A0"}, + {LbgB0, "B0"}, + {LbgB1, "B1"}, + {LbgB2, "B2"}, + {LbgS0, "S0"}, + {LbgS1, "S1"}, + {PchSteppingMax, NULL} +}; + +/** + Structure for PCH series string mapping +**/ +struct PCH_SERIES_STRING { + PCH_SERIES Series; + CHAR8 *String; +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +struct PCH_SERIES_STRING mSeriesStrs[] =3D { + {PchH, "SKL PCH-H"}, + {PchLp, "SKL PCH-LP"}, + {PchUnknownSeries, NULL} +}; + +/** + Structure for PCH sku string mapping +**/ +struct PCH_SKU_STRING { + UINT16 Id; + CHAR8 *String; +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +struct PCH_SKU_STRING mSkuStrs[] =3D { + // + // SKL PCH H Desktop LPC Device IDs + // + {V_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU, "Super SKU"}, + {V_PCH_H_LPC_DEVICE_ID_DT_0, "Super SKU (locked)"}, + {V_PCH_H_LPC_DEVICE_ID_DT_1, "H110"}, + {V_PCH_H_LPC_DEVICE_ID_DT_2, "H170"}, + {V_PCH_H_LPC_DEVICE_ID_DT_3, "Z170"}, + {V_PCH_H_LPC_DEVICE_ID_DT_4, "Q170"}, + {V_PCH_H_LPC_DEVICE_ID_DT_5, "Q150"}, + {V_PCH_H_LPC_DEVICE_ID_DT_6, "B150"}, + {V_PCH_H_LPC_DEVICE_ID_UNFUSE, "Unfused SKU"}, + // + // SKL PCH H Server/WS LPC Device IDs + // + {V_PCH_H_LPC_DEVICE_ID_SVR_0, "C236"}, + {V_PCH_H_LPC_DEVICE_ID_SVR_1, "C232"}, + {V_PCH_H_LPC_DEVICE_ID_SVR_2, "CM236"}, + {V_PCH_H_LPC_DEVICE_ID_A14B, "Super SKU (Unlocked)"}, + {V_PCH_LBG_LPC_DEVICE_ID_UNFUSED, "LBG Unfused SKU"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_0, "LBG SuperSKU - 0"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_4_SD, "LBG SuperSKU - 4/SD"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_T80_NS, "LBG SuperSKU - T80/SD"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_1G, "LBG SuperSKU - 1G"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_T, "LBG SuperSKU - T"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_L, "LBG SuperSKU - L"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_0, "LBG QS/PRQ - 0"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_1G, "LBG QS/PRQ - 1G"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_2, "LBG QS/PRQ - 2"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_4, "LBG QS/PRQ - 4"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_E, "LBG QS/PRQ - E"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_M, "LBG QS/PRQ - M"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_T, "LBG QS/PRQ - T"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_LP, "LBG QS/PRQ - LP"}, + // + // SKL PCH H Mobile LPC Device IDs + // + {V_PCH_H_LPC_DEVICE_ID_MB_0, "QM170"}, + {V_PCH_H_LPC_DEVICE_ID_MB_1, "HM170"}, + {V_PCH_H_LPC_DEVICE_ID_MB_2, "QMS170"}, + {V_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU, "Super SKU"}, + // + // SKL PCH LP Mobile LPC Device IDs + // + {V_PCH_LP_LPC_DEVICE_ID_UNFUSE, "Unfused SKU"}, + {V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU, "Super SKU"}, + {V_PCH_LP_LPC_DEVICE_ID_MB_0, "Super SKU (locked)"}, + {V_PCH_LP_LPC_DEVICE_ID_MB_1, "(U) Base SKU"}, + {V_PCH_LP_LPC_DEVICE_ID_MB_2, "(Y) Premium SKU"}, + {V_PCH_LP_LPC_DEVICE_ID_MB_3, "(U) Premium SKU"}, + {0xFFFF, NULL} +}; + +/** + Get PCH stepping ASCII string + The return string is zero terminated. + + @param [in] PchStep Pch stepping + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size wh= en buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The stepping is not supported, or = parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSteppingStr ( + IN PCH_STEPPING PchStep, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ) +{ + UINTN Index; + UINT32 StrLength; + CHAR8 *Str; + EFI_STATUS Status; + + if ((Buffer =3D=3D NULL) || (BufferSize =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (*BufferSize > 0) { + Buffer[0] =3D 0; + } + + Str =3D NULL; + StrLength =3D 0; + for (Index =3D 0; mSteppingStrs[Index].Stepping !=3D PchSteppingMax; Ind= ex++) { + if (PchStep =3D=3D mSteppingStrs[Index].Stepping) { + StrLength =3D (UINT32) AsciiStrLen (mSteppingStrs[Index].String); + Str =3D mSteppingStrs[Index].String; + break; + } + } + if (StrLength =3D=3D 0) { + // Unsupported Stepping + // ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + if (*BufferSize <=3D StrLength) { + *BufferSize =3D StrLength + 1; + return EFI_BUFFER_TOO_SMALL; + } + Status =3D AsciiStrCpyS (Buffer, *BufferSize, Str); + ASSERT_EFI_ERROR(Status); + return Status; +} + +/** + Get PCH series ASCII string + The return string is zero terminated. + + @param [in] PchSeries Pch series + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size wh= en buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The series is not supported, or pa= rameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSeriesStr ( + IN PCH_SERIES PchSeries, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ) +{ + UINTN Index; + UINT32 StrLength; + CHAR8 *Str; + EFI_STATUS Status; + + if ((Buffer =3D=3D NULL) || (BufferSize =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (*BufferSize > 0) { + Buffer[0] =3D 0; + } + + Str =3D NULL; + StrLength =3D 0; + for (Index =3D 0; mSeriesStrs[Index].Series !=3D PchUnknownSeries; Index= ++) { + if (PchSeries =3D=3D mSeriesStrs[Index].Series) { + StrLength =3D (UINT32) AsciiStrLen (mSeriesStrs[Index].String); + Str =3D mSeriesStrs[Index].String; + break; + } + } + if (StrLength =3D=3D 0) { + // Unsupported Series + // ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + if (*BufferSize <=3D StrLength) { + *BufferSize =3D StrLength + 1; + return EFI_BUFFER_TOO_SMALL; + } + Status =3D AsciiStrCpyS (Buffer, *BufferSize, Str); + ASSERT_EFI_ERROR(Status); + return Status; +} + +/** + Get PCH Sku ASCII string + The return string is zero terminated. + + @param [in] LpcDid LPC device id + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size wh= en buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The series is not supported, or pa= rameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSkuStr ( + IN UINT16 LpcDid, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ) +{ + UINTN Index; + UINT32 StrLength; + CHAR8 *Str; + EFI_STATUS Status; + + if ((Buffer =3D=3D NULL) || (BufferSize =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (*BufferSize > 0) { + Buffer[0] =3D 0; + } + + Str =3D NULL; + StrLength =3D 0; + for (Index =3D 0; mSkuStrs[Index].Id !=3D 0xFFFF; Index++) { + if (LpcDid =3D=3D mSkuStrs[Index].Id) { + StrLength =3D (UINT32) AsciiStrLen (mSkuStrs[Index].String); + Str =3D mSkuStrs[Index].String; + } + } + if (StrLength =3D=3D 0) { + // Unsupported Sku + // ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + if (*BufferSize <=3D StrLength) { + *BufferSize =3D StrLength + 1; + return EFI_BUFFER_TOO_SMALL; + } + Status =3D AsciiStrCpyS (Buffer, *BufferSize, Str); + ASSERT_EFI_ERROR(Status); + return Status; +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= InfoLib/PeiDxeSmmPchInfoLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch= /Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLib.inf new file mode 100644 index 0000000000..0c00fb9258 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib= /PeiDxeSmmPchInfoLib.inf @@ -0,0 +1,32 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiDxeSmmPchInfoLib + FILE_GUID =3D D43F3086-1D7E-4FF5-AE6A-3B0E15B11329 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PchInfoLib + + +[LibraryClasses] + BaseLib + IoLib + DebugLib + MmPciLib + + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + + +[Sources] + PchInfoLib.c + PchInfoStrLib.c diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= P2sbLib/PchP2sbLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/Pe= iDxeSmmPchP2sbLib/PchP2sbLib.c new file mode 100644 index 0000000000..5e8af8915d --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchP2sbLib= /PchP2sbLib.c @@ -0,0 +1,331 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Get P2SB pci configuration register. (This is internal function) + It returns register at Offset of P2SB controller and size in 1byte/2byte= s/4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] Size Size for read. Must be 1 or 2 or 4. + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +STATIC +EFI_STATUS +PchP2sbCfgGet ( + IN UINTN Offset, + IN UINTN Size, + OUT UINT32 *OutData + ) +{ + UINTN P2sbBase; + BOOLEAN DevicePresent; + + if ((Offset > 255) || + ((Offset & (Size - 1)) !=3D 0)) + { + DEBUG ((DEBUG_ERROR, "PchP2sbCfgGet error. Invalid Offset: %x Size: %x= ", Offset, Size)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + P2sbBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + DevicePresent =3D (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) !=3D 0xF= FFF); + if (!DevicePresent) { + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, 0); + } + ASSERT (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) !=3D 0xFFFF); + + switch (Size) { + case 4: + *(UINT32*)OutData =3D MmioRead32 (P2sbBase + Offset); + break; + case 2: + *(UINT16*)OutData =3D MmioRead16 (P2sbBase + Offset); + break; + case 1: + *(UINT8*) OutData =3D MmioRead8 (P2sbBase + Offset); + break; + default: + break; + } + + if (!DevicePresent) { + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, BIT0); + } + return EFI_SUCCESS; +} + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet32 ( + IN UINTN Offset, + OUT UINT32 *OutData + ) +{ + return PchP2sbCfgGet (Offset, 4, (UINT32*) OutData); +} + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 2bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet16 ( + IN UINTN Offset, + OUT UINT16 *OutData + ) +{ + return PchP2sbCfgGet (Offset, 2, (UINT32*) OutData); +} + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 1byte. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet8 ( + IN UINTN Offset, + OUT UINT8 *OutData + ) +{ + return PchP2sbCfgGet (Offset, 1, (UINT32*) OutData); +} + +/** + Set P2SB pci configuration register. (This is internal function) + It programs register at Offset of P2SB controller and size in 1byte/2byt= es/4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] Size Size for read. Must be 1 or 2 or 4. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +STATIC +EFI_STATUS +PchP2sbCfgSet ( + IN UINTN Offset, + IN UINTN Size, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + UINTN P2sbBase; + BOOLEAN DevicePresent; + UINT32 Data32; + + if ((Offset > 255) || + ((Offset & (Size - 1)) !=3D 0)) + { + DEBUG ((DEBUG_ERROR, "PchP2sbCfgSet error. Invalid Offset: %x Size: %x= ", Offset, Size)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Data32 =3D 0; + + P2sbBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + DevicePresent =3D (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) !=3D 0xF= FFF); + if (!DevicePresent) { + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, 0); + } + ASSERT (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) !=3D 0xFFFF); + + switch (Size) { + case 4: + Data32 =3D MmioRead32 (P2sbBase + Offset); + Data32 &=3D AndData; + Data32 |=3D OrData; + MmioWrite32 (P2sbBase + Offset, (UINT32) Data32); + break; + case 2: + Data32 =3D MmioRead16 (P2sbBase + Offset); + Data32 &=3D AndData; + Data32 |=3D OrData; + MmioWrite16 (P2sbBase + Offset, (UINT16) Data32); + break; + case 1: + Data32 =3D MmioRead8 (P2sbBase + Offset); + Data32 &=3D AndData; + Data32 |=3D OrData; + MmioWrite8 (P2sbBase + Offset, (UINT8) Data32); + break; + default: + break; + } + + if (!DevicePresent) { + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, BIT0); + } + return EFI_SUCCESS; +} + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet32 ( + IN UINTN Offset, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PchP2sbCfgSet (Offset, 4, AndData, OrData); +} + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 2bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet16 ( + IN UINTN Offset, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PchP2sbCfgSet (Offset, 2, AndData, OrData); +} + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 1bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet8 ( + IN UINTN Offset, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PchP2sbCfgSet (Offset, 1, AndData, OrData); +} + +/** + Hide P2SB device. + + @param[in] P2sbBase Pci base address of P2SB controlle= r. + + @retval EFI_SUCCESS Always return success. +**/ +EFI_STATUS +PchHideP2sb ( + IN UINTN P2sbBase + ) +{ + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, BIT0); + return EFI_SUCCESS; +} + +/** + Reveal P2SB device. + Also return the original P2SB status which is for Hidding P2SB or not af= ter. + If OrgStatus is not NULL, then TRUE means P2SB is unhidden, + and FALSE means P2SB is hidden originally. + + @param[in] P2sbBase Pci base address of P2SB controlle= r. + @param[out] OrgStatus Original P2SB hidding/unhidden sta= tus + + @retval EFI_SUCCESS Always return success. +**/ +EFI_STATUS +PchRevealP2sb ( + IN UINTN P2sbBase, + OUT BOOLEAN *OrgStatus + ) +{ + BOOLEAN DevicePresent; + + DevicePresent =3D (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) !=3D 0xF= FFF); + if (OrgStatus !=3D NULL) { + *OrgStatus =3D DevicePresent; + } + if (!DevicePresent) { + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, 0); + } + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= P2sbLib/PeiDxeSmmPchP2sbLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch= /Library/PeiDxeSmmPchP2sbLib/PeiDxeSmmPchP2sbLib.inf new file mode 100644 index 0000000000..d659aed8dc --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchP2sbLib= /PeiDxeSmmPchP2sbLib.inf @@ -0,0 +1,30 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiDxeSmmPchP2sbLib + FILE_GUID =3D FB044F6F-5F9F-48AB-AE12-1C0B829C8AD7 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PchP2sbLib + + +[LibraryClasses] + BaseLib + IoLib + DebugLib + MmPciLib + + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Sources] + PchP2sbLib.c diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= PcrLib/PchPcrLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiD= xeSmmPchPcrLib/PchPcrLib.c new file mode 100644 index 0000000000..5bb0f13eeb --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/= PchPcrLib.c @@ -0,0 +1,453 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Read PCR register. (This is internal function) + It returns PCR register and size in 1byte/2bytes/4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[in] Size Size for read. Must be 1 or 2 or 4. + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +STATIC +EFI_STATUS +PchPcrRead ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINTN Size, + OUT UINT32 *OutData + ) +{ + if ((Offset & (Size - 1)) !=3D 0) { + DEBUG ((DEBUG_ERROR, "PchPcrRead error. Invalid Offset: %x Size: %x", = Offset, Size)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + // + // @todo SKL PCH: check PID that not expected to use this routine, such = as CAM_FLIS, CSME0 + // + + switch (Size) { + case 4: + *(UINT32*)OutData =3D MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset)); + break; + case 2: + *(UINT16*)OutData =3D MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset)); + break; + case 1: + *(UINT8*) OutData =3D MmioRead8 (PCH_PCR_ADDRESS (Pid, Offset)); + break; + default: + break; + } + return EFI_SUCCESS; +} + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT32 *OutData + ) +{ + return PchPcrRead (Pid, Offset, 4, (UINT32*) OutData); +} + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT16 *OutData + ) +{ + return PchPcrRead (Pid, Offset, 2, (UINT32*) OutData); +} + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the= same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT8 *OutData + ) +{ + return PchPcrRead (Pid, Offset, 1, (UINT32*) OutData); +} + +BOOLEAN +PchPcrWriteMmioCheck ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset + ) +{ +DEBUG_CODE_BEGIN(); + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + // + // 1. USB2 AFE register must use SBI method + // + + // + // 2. GPIO unlock register field must use SBI method + // + if (Pid =3D=3D PID_GPIOCOM0) { + if (((PchSeries =3D=3D PchLp) && + ((Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCK) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCKTX) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCK) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCKTX))) || + ((PchSeries =3D=3D PchH) && + ((Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCK) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCK) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX)))) + { + return FALSE; + } + } + if (Pid =3D=3D PID_GPIOCOM1) { + if (((PchSeries =3D=3D PchLp) && + ((Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCK) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCKTX) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCK) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCKTX) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCK) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCKTX))) || + ((PchSeries =3D=3D PchH) && + ((Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCK) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCK) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCK) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCK) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCK) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCK) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX)))) + { + return FALSE; + } + } + if (Pid =3D=3D PID_GPIOCOM2) { + if (((PchSeries =3D=3D PchLp) && + ((Offset =3D=3D R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCK) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCKTX))) || + ((PchSeries =3D=3D PchH) && + ((Offset =3D=3D R_PCH_H_PCR_GPIO_GPD_PADCFGLOCK) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX)))) + { + return FALSE; + } + } + if (Pid =3D=3D PID_GPIOCOM3) { + if (((PchSeries =3D=3D PchLp) && + ((Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCK) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCKTX) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCK) || + (Offset =3D=3D R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCKTX))) || + ((PchSeries =3D=3D PchH) && + ((Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCK) || + (Offset =3D=3D R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX)))) + { + return FALSE; + } + } + // + // 3. CIO2 FLIS regsiter must use SBI method + // + + // + // 4. CSME0 based PCR should use the SBI method due to the FID requireme= nt + // + if (Pid =3D=3D PID_CSME0) { + return FALSE; + } +DEBUG_CODE_END(); + return TRUE; + +} + +/** + Write PCR register. (This is internal function) + It programs PCR register and size in 1byte/2bytes/4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Size Size for read. Must be 1 or 2 or 4. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +STATIC +EFI_STATUS +PchPcrWrite ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINTN Size, + IN UINT32 InData + ) +{ + if ((Offset & (Size - 1)) !=3D 0) { + DEBUG ((DEBUG_ERROR, "PchPcrWrite error. Invalid Offset: %x Size: %x",= Offset, Size)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } +DEBUG_CODE_BEGIN(); + if (!PchPcrWriteMmioCheck (Pid, Offset)) { + DEBUG ((DEBUG_ERROR, "PchPcrWrite error. Pid: %x Offset: %x should acc= ess through SBI interface", Pid, Offset)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } +DEBUG_CODE_END(); + + // + // Write the PCR register with provided data + // Then read back PCR register to prevent from back to back write. + // + switch (Size) { + case 4: + MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), (UINT32)InData); + break; + case 2: + MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), (UINT16)InData); + break; + case 1: + MmioWrite8 (PCH_PCR_ADDRESS (Pid, Offset), (UINT8) InData); + break; + default: + break; + } + MmioRead32 (PCH_PCR_ADDRESS (PID_LPC, R_PCH_PCR_LPC_GCFD)); + + return EFI_SUCCESS; +} + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size = as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 InData + ) +{ + return PchPcrWrite (Pid, Offset, 4, InData); +} + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size = as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 InData + ) +{ + return PchPcrWrite (Pid, Offset, 2, InData); +} + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size = as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 InData + ) +{ + return PchPcrWrite (Pid, Offset, 1, InData); +} + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + EFI_STATUS Status; + UINT32 Data32; + + Data32 =3D 0x00; + Status =3D PchPcrRead (Pid, Offset, 4, &Data32); + if (EFI_ERROR (Status)) { + return Status; + } + Data32 &=3D AndData; + Data32 |=3D OrData; + Status =3D PchPcrWrite (Pid, Offset, 4, Data32); + return Status; +} + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + EFI_STATUS Status; + UINT16 Data16; + + Data16 =3D 0x00; + Status =3D PchPcrRead (Pid, Offset, 2, (UINT32*) &Data16); + if (EFI_ERROR (Status)) { + return Status; + } + Data16 &=3D AndData; + Data16 |=3D OrData; + Status =3D PchPcrWrite (Pid, Offset, 2, Data16); + return Status; +} + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as= Size parameter. + @param[in] OrData OR Data. Must be the same size as = Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + EFI_STATUS Status; + UINT8 Data8; + + Status =3D PchPcrRead (Pid, Offset, 1, (UINT32*) &Data8); + if (EFI_ERROR (Status)) { + return Status; + } + Data8 &=3D AndData; + Data8 |=3D OrData; + Status =3D PchPcrWrite (Pid, Offset, 1, Data8); + return Status; +} + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= PcrLib/PeiDxeSmmPchPcrLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/L= ibrary/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf new file mode 100644 index 0000000000..05da628164 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/= PeiDxeSmmPchPcrLib.inf @@ -0,0 +1,31 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiDxeSmmPchPcrLib + FILE_GUID =3D 117C8D19-445B-46BF-B624-109F63709375 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PchPcrLib + + +[LibraryClasses] + BaseLib + IoLib + DebugLib + MmPciLib + PchInfoLib + + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Sources] + PchPcrLib.c diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= PmcLib/PchPmcLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiD= xeSmmPchPmcLib/PchPmcLib.c new file mode 100644 index 0000000000..9ac1b1ee66 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/= PchPmcLib.c @@ -0,0 +1,153 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Query PCH to determine the Pm Status + NOTE: + It's matter when did platform code use this library, since some status c= ould be cleared by write one clear. + Therefore this funciton is not always return the same result in one boot. + It's suggested that platform code read this status in the beginning of p= ost. + For the ColdBoot case, this function only returns one case of the cold b= oot. Some cold boot case might + depends on the power cycle scenario and should check with different cond= tion. + + @param[in] PmStatus - The Pch Pm Status to be probed + + @retval Return TRUE if Status querried is Valid or FALSE if otherwise +**/ +BOOLEAN +GetPchPmStatus ( + PCH_PM_STATUS PmStatus + ) +{ + UINTN PmcRegBase; + UINT32 PchPwrmBase; + UINT32 PmConA; + UINT32 PmConB; + UINT32 GblRst0; + + PmcRegBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + PchPwrmBaseGet (&PchPwrmBase); + + PmConA =3D MmioRead32 (PmcRegBase + R_PCH_PMC_GEN_PMCON_A); + PmConB =3D MmioRead32 (PmcRegBase + R_PCH_PMC_GEN_PMCON_B); + GblRst0 =3D MmioRead32 (PchPwrmBase + R_PCH_PWRM_124); + + switch(PmStatus){ + case PchWarmBoot: + + if (PmConA & B_PCH_PMC_GEN_PMCON_A_MEM_SR) { + return TRUE; + } + break; + + case PwrFlr: + if (PmConB & B_PCH_PMC_GEN_PMCON_B_PWR_FLR) { + return TRUE; + } + break; + + case PwrFlrSys: + if (GblRst0 & BIT12) { + return TRUE; + } + break; + + case PwrFlrPch: + if (GblRst0 & BIT11) { + return TRUE; + } + break; + + case PchColdBoot: + /// + /// Check following conditions for cold boot. + /// + if ((GblRst0 & BIT11) && // PCHPWR_FLR + (GblRst0 & BIT12) && // SYSPWR_FLR + (!(PmConA & B_PCH_PMC_GEN_PMCON_A_MEM_SR))) { + return TRUE; + } + break; + + default: + break; + } + + return FALSE; +} + +/** + Funtion to check if Battery lost or CMOS cleared. + + @reval TRUE Battery is always present. + @reval FALSE CMOS is cleared. +**/ +BOOLEAN +EFIAPI +PchIsRtcBatteryGood ( + VOID + ) +{ + UINTN Data; + UINTN PmcBaseAddress; + + // + // Check if the CMOS battery is present + // Checks RTC_PWR_STS bit in the GEN_PMCON_3 register + // + PmcBaseAddress =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + + Data =3D MmioRead32 (PmcBaseAddress + R_PCH_PMC_GEN_PMCON_B); + if ((Data & B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS) =3D=3D 0) { + return TRUE; + } + return FALSE; +} + +/** + Funtion to check if DWR occurs + + @reval TRUE DWR occurs + @reval FALSE Normal boot flow +**/ +BOOLEAN +EFIAPI +PchIsDwrFlow ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 PchPwrmBase; + + Status =3D PchPwrmBaseGet (&PchPwrmBase); + ASSERT (PchPwrmBase !=3D 0); + + if ((PchPwrmBase !=3D 0) && + (MmioRead32 (PchPwrmBase + R_PCH_PWRM_HPR_CAUSE0) & B_PCH_PWRM_HPR_C= AUSE0_GBL_TO_HOST)) { + return TRUE; + } else { + return FALSE; + } +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= PmcLib/PeiDxeSmmPchPmcLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/L= ibrary/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf new file mode 100644 index 0000000000..c0ec7b70e4 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/= PeiDxeSmmPchPmcLib.inf @@ -0,0 +1,31 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiDxeSmmPchPmcLib + FILE_GUID =3D 9D60C364-5086-41E3-BC9D-C62AB7233DBF + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PchPmcLib + + +[LibraryClasses] + BaseLib + IoLib + DebugLib + MmPciLib + PchCycleDecodingLib + + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Sources] + PchPmcLib.c diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= SbiAccessLib/PchSbiAccessLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/= Library/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c new file mode 100644 index 0000000000..6f0030ac33 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchSbiAcce= ssLib/PchSbiAccessLib.c @@ -0,0 +1,370 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Execute PCH SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiE= xecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. = If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be= checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would = provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter +**/ +EFI_STATUS +EFIAPI +PchSbiExecution ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ) +{ + + + return PchSbiExecutionEx ( Pid, + Offset, + Opcode, + Posted, + 0x000F, + 0x0000, + 0x0000, + Data32, + Response + ); +} + +/** + Full function for executing PCH SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiE= xecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. = If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be= checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would = provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter +**/ +EFI_STATUS +EFIAPI +PchSbiExecutionEx ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ) +{ + EFI_STATUS Status; + UINTN P2sbBase; + BOOLEAN P2sbOrgStatus; + UINTN Timeout; + UINT16 SbiStat; + + // + // Check opcode valid + // + switch (Opcode) { + case PciConfigRead: + case PciConfigWrite: + case PrivateControlRead: + case PrivateControlWrite: + case GpioLockUnlock: + break; + default: + return EFI_INVALID_PARAMETER; + break; + } + + P2sbOrgStatus =3D FALSE; + P2sbBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + PchRevealP2sb (P2sbBase, &P2sbOrgStatus); + /// + /// BWG Section 2.2.1 + /// 1. Poll P2SB PCI offset D8h[0] =3D 0b + /// Make sure the previous opeartion is completed. + /// + Timeout =3D 0xFFFFFFF; + while (Timeout > 0){ + SbiStat =3D MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) =3D=3D 0) { + break; + } + Timeout--; + } + if (Timeout =3D=3D 0) { + Status =3D EFI_DEVICE_ERROR; + goto ExitPchSbiExecutionEx; + } + // + // Initial Response status + // + *Response =3D SBI_INVALID_RESPONSE; + Status =3D EFI_SUCCESS; + SbiStat =3D 0; + /// + /// 2. Write P2SB PCI offset D0h[31:0] with Address and Destination Port= ID + /// + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIADDR, (UINT32) ((Pid << 24) | (UIN= T16)Offset)); + /// + /// 3. Write P2SB PCI offset DCh[31:0] with extended address, which is e= xpected to be 0 in SKL PCH. + /// + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIEXTADDR, (UINT32) RShiftU64 (Offse= t, 16)); + /// + /// 5. Set P2SB PCI offset D8h[15:8] =3D 00000110b for read + /// Set P2SB PCI offset D8h[15:8] =3D 00000111b for write + // + // Set SBISTAT[15:8] to the opcode passed in + // Set SBISTAT[7] to the posted passed in + // + MmioAndThenOr16 ( + (P2sbBase + R_PCH_P2SB_SBISTAT), + (UINT16) ~(B_PCH_P2SB_SBISTAT_OPCODE | B_PCH_P2SB_SBISTAT_POSTED), + (UINT16) ((Opcode << 8) | (Posted << 7)) + ); + /// + /// 6. Write P2SB PCI offset DAh[15:0] =3D F000h + /// + // + // Set RID[15:0] =3D Fbe << 12 | Bar << 8 | Fid + // + MmioWrite16 ( + (P2sbBase + R_PCH_P2SB_SBIRID), + (((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF)) + ); + + switch (Opcode) { + case PciConfigWrite: + case PrivateControlWrite: + case GpioLockUnlock: + /// + /// 4. Write P2SB PCI offset D4h[31:0] with the intended data accord= ingly + /// + MmioWrite32 ((P2sbBase + R_PCH_P2SB_SBIDATA), *Data32); + break; + default: + /// + /// 4. Write P2SB PCI offset D4h[31:0] with dummy data such as 0, + /// because all D0-DFh register range must be touched in SKL PCH + /// for a successful SBI transaction. + /// + MmioWrite32 ((P2sbBase + R_PCH_P2SB_SBIDATA), 0); + break; + } + /// + /// 7. Set P2SB PCI offset D8h[0] =3D 1b, Poll P2SB PCI offset D8h[0] = =3D 0b + /// + // + // Set SBISTAT[0] =3D 1b, trigger the SBI operation + // + MmioOr16 (P2sbBase + R_PCH_P2SB_SBISTAT, (UINT16) B_PCH_P2SB_SBISTAT_INI= TRDY); + // + // Poll SBISTAT[0] =3D 0b, Polling for Busy bit + // + Timeout =3D 0xFFFFFFF; + while (Timeout > 0){ + SbiStat =3D MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) =3D=3D 0) { + break; + } + Timeout--; + } + if (Timeout =3D=3D 0) { + // + // If timeout, it's fatal error. + // + Status =3D EFI_DEVICE_ERROR; + } else { + /// + /// 8. Check if P2SB PCI offset D8h[2:1] =3D 00b for successful transa= ction + /// + *Response =3D (UINT8)((SbiStat & B_PCH_P2SB_SBISTAT_RESPONSE) >> N_PCH= _P2SB_SBISTAT_RESPONSE); + if (*Response =3D=3D SBI_SUCCESSFUL) { + switch (Opcode) { + case PciConfigRead: + case PrivateControlRead: + /// + /// 9. Read P2SB PCI offset D4h[31:0] for SBI data + /// + *Data32 =3D MmioRead32 (P2sbBase + R_PCH_P2SB_SBIDATA); + break; + default: + break; + } + Status =3D EFI_SUCCESS; + } else { + Status =3D EFI_DEVICE_ERROR; + } + } + +ExitPchSbiExecutionEx: + if (!P2sbOrgStatus) { + PchHideP2sb (P2sbBase); + } + return Status; +} + +/** + This function saves all PCH SBI registers. + The save and restore operations must be done while using the PchSbiExecu= tion inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POS= T and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in, out] PchSbiRegister Structure for saving the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterSave ( + IN OUT PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ) +{ + UINTN P2sbBase; + UINTN Timeout; + UINT16 SbiStat; + + P2sbBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + if (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFFF) { + return EFI_DEVICE_ERROR; + } + // + // Make sure it's not busy. + // Poll SBISTAT[0] =3D 0b + // + Timeout =3D 0xFFFFFFF; + while ((Timeout--) > 0){ + SbiStat =3D MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) =3D=3D 0) { + break; + } + } + if (Timeout =3D=3D 0) { + return EFI_DEVICE_ERROR; + } + // + // Save original SBI registers + // + PchSbiRegister->SbiAddr =3D MmioRead32 (P2sbBase + R_PCH_P2SB_SBIADDR= ); + PchSbiRegister->SbiExtAddr =3D MmioRead32 (P2sbBase + R_PCH_P2SB_SBIEXTA= DDR); + PchSbiRegister->SbiData =3D MmioRead32 (P2sbBase + R_PCH_P2SB_SBIDATA= ); + PchSbiRegister->SbiStat =3D MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT= ); + PchSbiRegister->SbiRid =3D MmioRead16 (P2sbBase + R_PCH_P2SB_SBIRID); + + return EFI_SUCCESS; +} + +/** + This function restores all PCH SBI registers + The save and restore operations must be done while using the PchSbiExecu= tion inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POS= T and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in] PchSbiRegister Structure for restoring the regist= ers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterRestore ( + IN PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ) +{ + UINTN P2sbBase; + UINTN Timeout; + UINT16 SbiStat; + + P2sbBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + if (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFFF) { + return EFI_DEVICE_ERROR; + } + // + // Make sure it's not busy. + // Poll SBISTAT[0] =3D 0b + // + Timeout =3D 0xFFFFFFF; + while ((Timeout--) > 0){ + SbiStat =3D MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) =3D=3D 0) { + break; + } + } + if (Timeout =3D=3D 0) { + return EFI_DEVICE_ERROR; + } + // + // Restore original SBI registers + // + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIADDR , PchSbiRegister->SbiAddr); + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIEXTADDR, PchSbiRegister->SbiExtAdd= r); + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIDATA , PchSbiRegister->SbiData); + MmioWrite16 (P2sbBase + R_PCH_P2SB_SBISTAT , PchSbiRegister->SbiStat); + MmioWrite16 (P2sbBase + R_PCH_P2SB_SBIRID , PchSbiRegister->SbiRid); + + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPch= SbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf b/Silicon/Intel/PurleyRefreshSili= conPkg/Pch/Library/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf new file mode 100644 index 0000000000..eaba8483ba --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchSbiAcce= ssLib/PeiDxeSmmPchSbiAccessLib.inf @@ -0,0 +1,31 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiDxeSmmPchSbiAccessLib + FILE_GUID =3D 96ECB0FB-A975-4DC8-B88A-D90C3378CE87 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PchSbiAccessLib + + +[LibraryClasses] + BaseLib + IoLib + DebugLib + MmPciLib + PchP2sbLib + + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Sources] + PchSbiAccessLib.c diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicy= Lib/PchPrintPolicy.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/Pe= iPchPolicyLib/PchPrintPolicy.c new file mode 100644 index 0000000000..33fa00b25f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/Pch= PrintPolicy.c @@ -0,0 +1,730 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiPchPolicyLibrary.h" + +/** + Print PCH_USB_CONFIG and serial out. + + @param[in] UsbConfig Pointer to a PCH_USB_CONFIG that provides t= he platform setting + +**/ +VOID +PchPrintUsbConfig ( + IN CONST PCH_USB_CONFIG *UsbConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH USB Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, " UsbPrecondition=3D %x\n", UsbConfig->UsbPreconditi= on)); + DEBUG ((DEBUG_INFO, " DisableComplianceMode=3D %x\n", UsbConfig->Disable= ComplianceMode)); + + for (i =3D 0; i < GetPchUsbMaxPhysicalPortNum (); i++) { + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Enabled=3D %x\n", i, UsbConfig->Po= rtUsb20[i].Enable)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].OverCurrentPin=3D OC%x\n", i, UsbC= onfig->PortUsb20[i].OverCurrentPin)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Petxiset=3D %x\n", i, UsbConfi= g->PortUsb20[i].Afe.Petxiset)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Txiset=3D %x\n", i, UsbConfig-= >PortUsb20[i].Afe.Txiset)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Predeemp=3D %x\n", i, UsbConfi= g->PortUsb20[i].Afe.Predeemp)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Pehalfbit=3D %x\n", i, UsbConf= ig->PortUsb20[i].Afe.Pehalfbit)); + } + + for (i =3D 0; i < GetPchXhciMaxUsb3PortNum (); i++) { + DEBUG ((DEBUG_INFO, " PortUsb30[%d] Enabled=3D %x\n", i, UsbConfig->Po= rtUsb30[i].Enable)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].OverCurrentPin=3D OC%x\n", i, UsbC= onfig->PortUsb30[i].OverCurrentPin)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDeEmph =3D %x\n", i,= UsbConfig->PortUsb30[i].HsioTxDeEmph)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDeEmphEnable =3D %x\n", i,= UsbConfig->PortUsb30[i].HsioTxDeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDownscaleAmp =3D %x= \n", i, UsbConfig->PortUsb30[i].HsioTxDownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDownscaleAmpEnable =3D %x= \n", i, UsbConfig->PortUsb30[i].HsioTxDownscaleAmpEnable)); + } + + DEBUG ((DEBUG_INFO, " XdciConfig.Enable=3D %x\n", UsbConfig->XdciConfig.= Enable)); + + for (i =3D 0; i < PCH_XHCI_MAX_SSIC_PORT_COUNT; i++) { + DEBUG ((DEBUG_INFO, " SsicPort[%d].Enable =3D %x\n", i, UsbConfig->= SsicConfig.SsicPort[i].Enable)); + } + +} + +/** + Print PCH_PCIE_CONFIG and serial out. + + @param[in] PcieConfig Pointer to a PCH_PCIE_CONFIG that provides= the platform setting + @param[in] HsioPcieConfig Pointer to a PCH_HSIO_PCIE_CONFIG that pro= vides the platform setting + +**/ +VOID +PchPrintPcieConfig ( + IN CONST PCH_PCIE_CONFIG *PcieConfig, + IN CONST PCH_HSIO_PCIE_CONFIG *HsioPcieConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH PCIE Config ----------------= --\n")); + for (i =3D 0; i < GetPchMaxPciePortNum (); i++) { + DEBUG ((DEBUG_INFO, " RootPort[%d] Enabled=3D %x\n", i, PcieConfig->Ro= otPort[i].Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HotPlug=3D %x\n", i, PcieConfig->Ro= otPort[i].HotPlug)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PmSci=3D %x\n", i, PcieConfig->Root= Port[i].PmSci)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ExtSync=3D %x\n", i, PcieConfig->Ro= otPort[i].ExtSync)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqSupported=3D %x\n", i, PcieCo= nfig->RootPort[i].ClkReqSupported)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqNumber=3D %x\n", i, PcieConfi= g->RootPort[i].ClkReqNumber)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqDetect=3D %x\n", i, PcieConfi= g->RootPort[i].ClkReqDetect)); + DEBUG ((DEBUG_INFO, " RootPort[%d] UnsupportedRequestReport=3D %x\n", = i, PcieConfig->RootPort[i].UnsupportedRequestReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] FatalErrorReport=3D %x\n", i, PcieC= onfig->RootPort[i].FatalErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NoFatalErrorReport=3D %x\n", i, Pci= eConfig->RootPort[i].NoFatalErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] CorrectableErrorReport=3D %x\n", i,= PcieConfig->RootPort[i].CorrectableErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnFatalError=3D %x\n", i= , PcieConfig->RootPort[i].SystemErrorOnFatalError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnNonFatalError=3D %x\n"= , i, PcieConfig->RootPort[i].SystemErrorOnNonFatalError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnCorrectableError=3D %x= \n", i, PcieConfig->RootPort[i].SystemErrorOnCorrectableError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] MaxPayload=3D %x\n", i, PcieConfig-= >RootPort[i].MaxPayload)); + DEBUG ((DEBUG_INFO, " RootPort[%d] AcsEnabled=3D %x\n", i, PcieConfig-= >RootPort[i].AcsEnabled)); + DEBUG ((DEBUG_INFO, " RootPort[%d] AdvancedErrorReporting=3D %x\n", i,= PcieConfig->RootPort[i].AdvancedErrorReporting)); + DEBUG ((DEBUG_INFO, " RootPort[%d] TransmitterHalfSwing=3D %x\n", i, P= cieConfig->RootPort[i].TransmitterHalfSwing)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PcieSpeed=3D %x\n", i, PcieConfig->= RootPort[i].PcieSpeed)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3EqPh3Method=3D %x\n", i, PcieCo= nfig->RootPort[i].Gen3EqPh3Method)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PhysicalSlotNumber=3D %x\n", i, Pci= eConfig->RootPort[i].PhysicalSlotNumber)); + DEBUG ((DEBUG_INFO, " RootPort[%d] CompletionTimeout=3D %x\n", i, Pcie= Config->RootPort[i].CompletionTimeout)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Aspm=3D %x\n", i, PcieConfig->RootP= ort[i].Aspm)); + DEBUG ((DEBUG_INFO, " RootPort[%d] L1Substates=3D %x\n", i, PcieConfig= ->RootPort[i].L1Substates)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrEnable=3D %x\n", i, PcieConfig->= RootPort[i].LtrEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrConfigLock=3D %x\n", i, PcieConf= ig->RootPort[i].LtrConfigLock)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxSnoopLatency=3D %x\n", i, Pci= eConfig->RootPort[i].LtrMaxSnoopLatency)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxNoSnoopLatency=3D %x\n", i, P= cieConfig->RootPort[i].LtrMaxNoSnoopLatency)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMode=3D %x\n", = i, PcieConfig->RootPort[i].SnoopLatencyOverrideMode)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMultiplier=3D %= x\n", i, PcieConfig->RootPort[i].SnoopLatencyOverrideMultiplier)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideValue=3D %x\n",= i, PcieConfig->RootPort[i].SnoopLatencyOverrideValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMode=3D %x\n= ", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideMode)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMultiplier= =3D %x\n", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideMultiplier)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideValue=3D %x\= n", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitScale=3D %x\n", i, Pc= ieConfig->RootPort[i].SlotPowerLimitScale)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitValue=3D %x\n", i, Pc= ieConfig->RootPort[i].SlotPowerLimitValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Uptp=3D %x\n", i, PcieConfig->RootP= ort[i].Uptp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Dptp=3D %x\n", i, PcieConfig->RootP= ort[i].Dptp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioRxSetCtleEnable=3D %x\n", i, Hs= ioPcieConfig->Lane[i].HsioRxSetCtleEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioRxSetCtle=3D %x\n", i, HsioPcie= Config->Lane[i].HsioRxSetCtle)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DownscaleAmpEnable=3D %x\= n", i, HsioPcieConfig->Lane[i].HsioTxGen1DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DownscaleAmp=3D %x\n", i,= HsioPcieConfig->Lane[i].HsioTxGen1DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DownscaleAmpEnable=3D %x\= n", i, HsioPcieConfig->Lane[i].HsioTxGen2DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DownscaleAmp=3D %x\n", i,= HsioPcieConfig->Lane[i].HsioTxGen2DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen3DownscaleAmpEnable=3D %x\= n", i, HsioPcieConfig->Lane[i].HsioTxGen3DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen3DownscaleAmp=3D %x\n", i,= HsioPcieConfig->Lane[i].HsioTxGen3DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DeEmphEnable=3D %x\n", i,= HsioPcieConfig->Lane[i].HsioTxGen1DeEmphEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DeEmph=3D %x\n", i, HsioP= cieConfig->Lane[i].HsioTxGen1DeEmph)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph3p5Enable=3D %x\n",= i, HsioPcieConfig->Lane[i].HsioTxGen2DeEmph3p5Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph3p5=3D %x\n", i, Hs= ioPcieConfig->Lane[i].HsioTxGen2DeEmph3p5)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph6p0Enable=3D %x\n",= i, HsioPcieConfig->Lane[i].HsioTxGen2DeEmph6p0Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph6p0=3D %x\n", i, Hs= ioPcieConfig->Lane[i].HsioTxGen2DeEmph6p0)); + + } + DEBUG ((DEBUG_INFO, " EnablePort8xhDecode=3D %x\n", PcieConfig->EnablePo= rt8xhDecode)); + DEBUG ((DEBUG_INFO, " PchPciePort8xhDecodePortIndex=3D %x\n", PcieConfig= ->PchPciePort8xhDecodePortIndex)); + DEBUG ((DEBUG_INFO, " DisableRootPortClockGating=3D %x\n", PcieConfig->D= isableRootPortClockGating)); + DEBUG ((DEBUG_INFO, " EnablePeerMemoryWrite=3D %x\n", PcieConfig->Enable= PeerMemoryWrite)); + DEBUG ((DEBUG_INFO, " AllowNoLtrIccPllShutdown=3D %x\n", PcieConfig->All= owNoLtrIccPllShutdown)); + DEBUG ((DEBUG_INFO, " ComplianceTestMode=3D %x\n", PcieConfig->Complianc= eTestMode)); + DEBUG ((DEBUG_INFO, " RpFunctionSwap=3D %x\n", PcieConfig->RpFunctionSwa= p)); +} + +/** + Print PCH_PCIE_CONFIG2 and serial out. + + @param[in] PcieConfig2 Pointer to a PCH_PCIE_CONFIG2 that provide= s the platform setting + +**/ +VOID +PchPrintPcieConfig2 ( + IN CONST PCH_PCIE_CONFIG2 *PcieConfig2 + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "------------------ PCH PCIE Config2 ---------------= --\n")); + for (Index =3D 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) { + DEBUG ((DEBUG_INFO, " SwEqCoeffCm[%d] =3D %x\n", Index, PcieConfig2->S= wEqCoeffList[Index].Cm)); + DEBUG ((DEBUG_INFO, " SwEqCoeffCp[%d] =3D %x\n", Index, PcieConfig2->S= wEqCoeffList[Index].Cp)); + } +} + +/** + Print PCH_SATA_CONFIG and serial out. + + @param[in] SataConfig Pointer to a PCH_SATA_CONFIG that provides= the platform setting + @param[in] HsioSataConfig Pointer to a PCH_HSIO_SATA_CONFIG that pro= vides the platform setting + +**/ +VOID +PchPrintSataConfig ( + IN CONST PCH_SATA_CONFIG *SataConfig, + IN VOID *HsioSataConfigPtr, + IN UINT8 SataControllerNo + ) +{ + UINT32 i; + + UINT32 MaxSataPortNum; + PCH_HSIO_SATA_CONFIG *HsioSataConfig; + + HsioSataConfig =3D HsioSataConfigPtr; + + if (SataControllerNo =3D=3D PCH_SATA_FIRST_CONTROLLER) { + DEBUG ((DEBUG_INFO, "------------------- PCH Primary SATA Config -----= -------------\n")); + MaxSataPortNum =3D GetPchMaxSataPortNum (); + } else { + DEBUG ((DEBUG_INFO, "------------------ PCH Secondary SATA Config ----= --------------\n")); + MaxSataPortNum =3D GetPchMaxsSataPortNum (); + } + DEBUG ((DEBUG_INFO, " Enable=3D %x\n", SataConfig->Enable)); + DEBUG ((DEBUG_INFO, " SataMode=3D %x\n", SataConfig->SataMode)); + + + for (i =3D 0; i < MaxSataPortNum; i++) { + DEBUG ((DEBUG_INFO, " PortSettings[%d] Enabled=3D %x\n", i, SataConfig= ->PortSettings[i].Enable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HotPlug=3D %x\n", i, SataConfig= ->PortSettings[i].HotPlug)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] InterlockSw=3D %x\n", i, SataCo= nfig->PortSettings[i].InterlockSw)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] External=3D %x\n", i, SataConfi= g->PortSettings[i].External)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] SpinUp=3D %x\n", i, SataConfig-= >PortSettings[i].SpinUp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] SolidStateDrive=3D %x\n", i, Sa= taConfig->PortSettings[i].SolidStateDrive)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DevSlp=3D %x\n", i, SataConfig-= >PortSettings[i].DevSlp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] EnableDitoConfig=3D %x\n", i, S= ataConfig->PortSettings[i].EnableDitoConfig)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DmVal=3D %x\n", i, SataConfig->= PortSettings[i].DmVal)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DitoVal=3D %x\n", i, SataConfig= ->PortSettings[i].DitoVal)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] ZpOdd=3D %x\n", i, SataConfig->= PortSettings[i].ZpOdd)); + + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMagEnable=3D %= x\n", i, HsioSataConfig->PortLane[i].HsioRxGen1EqBoostMagEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMag=3D %x\n", = i, HsioSataConfig->PortLane[i].HsioRxGen1EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMagEnable=3D %= x\n", i, HsioSataConfig->PortLane[i].HsioRxGen2EqBoostMagEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMag=3D %x\n", = i, HsioSataConfig->PortLane[i].HsioRxGen2EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMagEnable=3D %= x\n", i, HsioSataConfig->PortLane[i].HsioRxGen3EqBoostMagEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMag=3D %x\n", = i, HsioSataConfig->PortLane[i].HsioRxGen3EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmpEnable=3D= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen1DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmp=3D %x\n"= , i, HsioSataConfig->PortLane[i].HsioTxGen1DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmpEnable=3D= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen2DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmp=3D %x\n"= , i, HsioSataConfig->PortLane[i].HsioTxGen2DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmpEnable=3D= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen3DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmp=3D %x\n"= , i, HsioSataConfig->PortLane[i].HsioTxGen3DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmphEnable=3D %x\n"= , i, HsioSataConfig->PortLane[i].HsioTxGen1DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmph=3D %x\n", i, H= sioSataConfig->PortLane[i].HsioTxGen1DeEmph)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmphEnable=3D %x\n"= , i, HsioSataConfig->PortLane[i].HsioTxGen2DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmph=3D %x\n", i, H= sioSataConfig->PortLane[i].HsioTxGen2DeEmph)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmphEnable=3D %x\n"= , i, HsioSataConfig->PortLane[i].HsioTxGen3DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmph=3D %x\n", i, H= sioSataConfig->PortLane[i].HsioTxGen3DeEmph)); + } + + DEBUG ((DEBUG_INFO, " RaidAlternateId=3D %x\n", SataConfig->Rst.RaidAlte= rnateId)); + DEBUG ((DEBUG_INFO, " Raid0=3D %x\n", SataConfig->Rst.Raid0)); + DEBUG ((DEBUG_INFO, " Raid1=3D %x\n", SataConfig->Rst.Raid1)); + DEBUG ((DEBUG_INFO, " Raid10=3D %x\n", SataConfig->Rst.Raid10)); + DEBUG ((DEBUG_INFO, " Raid5=3D %x\n", SataConfig->Rst.Raid5)); + DEBUG ((DEBUG_INFO, " Irrt=3D %x\n", SataConfig->Rst.Irrt)); + DEBUG ((DEBUG_INFO, " OromUiBanner=3D %x\n", SataConfig->Rst.OromUiBanne= r)); + DEBUG ((DEBUG_INFO, " OromUiDelay=3D %x\n", SataConfig->Rst.OromUiDelay)= ); + DEBUG ((DEBUG_INFO, " HddUnlock=3D %x\n", SataConfig->Rst.HddUnlock)); + DEBUG ((DEBUG_INFO, " LedLocate=3D %x\n", SataConfig->Rst.LedLocate)); + DEBUG ((DEBUG_INFO, " IrrtOnly=3D %x\n", SataConfig->Rst.IrrtOnly)); + DEBUG ((DEBUG_INFO, " SmartStorage=3D %x\n", SataConfig->Rst.SmartStorag= e)); + + DEBUG ((DEBUG_INFO, " SpeedSupport=3D %x\n", SataConfig->SpeedLimit)); + DEBUG ((DEBUG_INFO, " eSATASpeedLimit=3D %x\n", SataConfig->eSATASpeedLi= mit)); + DEBUG ((DEBUG_INFO, " TestMode=3D %x\n", SataConfig->TestMode)); + DEBUG ((DEBUG_INFO, " SalpSupport=3D %x\n", SataConfig->SalpSupport)); + DEBUG ((DEBUG_INFO, " PwrOptEnable=3D %x\n", SataConfig->PwrOptEnable)); + + for (i =3D 0; i < PCH_MAX_RST_PCIE_STORAGE_CR; i++) { + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].Enable = =3D %x\n", i, SataConfig->RstPcieStorageRemap[i].Enable)); + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].RstPcieStoragePort = =3D %x\n", i, SataConfig->RstPcieStorageRemap[i].RstPcieStoragePort)); + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].DeviceResetDelay = =3D %x\n", i, SataConfig->RstPcieStorageRemap[i].DeviceResetDelay)); + } +} + +/** + Print PCH_IOAPIC_CONFIG and serial out. + + @param[in] IoApicConfig Pointer to a PCH_IOAPIC_CONFIG that prov= ides the platform setting + +**/ +VOID +PchPrintIoApicConfig ( + IN CONST PCH_IOAPIC_CONFIG *IoApicConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH IOAPIC Config --------------= ----\n")); + DEBUG ((DEBUG_INFO, " BdfValid=3D %x\n", IoApicConfig->BdfValid)); + DEBUG ((DEBUG_INFO, " BusNumber=3D %x\n", IoApicConfig->BusNumber)); + DEBUG ((DEBUG_INFO, " DeviceNumber=3D %x\n", IoApicConfig->DeviceNumber)= ); + DEBUG ((DEBUG_INFO, " FunctionNumber=3D %x\n", IoApicConfig->FunctionNum= ber)); + DEBUG ((DEBUG_INFO, " IoApicId=3D %x\n", IoApicConfig->IoApicId)); + DEBUG ((DEBUG_INFO, " ApicRangeSelect=3D %x\n", IoApicConfig->ApicRangeS= elect)); + DEBUG ((DEBUG_INFO, " IoApicEntry24_119=3D %x\n", IoApicConfig->IoApicEn= try24_119)); +} + +/** + Print PCH_HPET_CONFIG and serial out. + + @param[in] HpetConfig Pointer to a PCH_HPET_CONFIG that provides= the platform setting + +**/ +VOID +PchPrintHpetConfig ( + IN CONST PCH_HPET_CONFIG *HpetConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH HPET Config ----------------= --\n")); + DEBUG ((DEBUG_INFO, " Enable %x\n", HpetConfig->Enable)); + DEBUG ((DEBUG_INFO, " BdfValid %x\n", HpetConfig->BdfValid)); + DEBUG ((DEBUG_INFO, " BusNumber %x\n", HpetConfig->BusNumber)); + DEBUG ((DEBUG_INFO, " DeviceNumber %x\n", HpetConfig->DeviceNumber)); + DEBUG ((DEBUG_INFO, " FunctionNumber %x\n", HpetConfig->FunctionNumber)); + DEBUG ((DEBUG_INFO, " Base %x\n", HpetConfig->Base)); +} + +/** + Print PCH_LOCK_DOWN_CONFIG and serial out. + + @param[in] LockDownConfig Pointer to a PCH_LOCK_DOWN_CONFIG that= provides the platform setting + +**/ +VOID +PchPrintLockDownConfig ( + IN CONST PCH_LOCK_DOWN_CONFIG *LockDownConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH Lock Down Config -----------= -------\n")); + DEBUG ((DEBUG_INFO, " GlobalSmi=3D %x\n", LockDownConfig->GlobalSmi)); + DEBUG ((DEBUG_INFO, " BiosInterface=3D %x\n", LockDownConfig->BiosInterf= ace)); + DEBUG ((DEBUG_INFO, " RtcLock=3D %x\n", LockDownConfig->RtcLock)); + DEBUG ((DEBUG_INFO, " BiosLock=3D %x\n", LockDownConfig->BiosLock)); + DEBUG ((DEBUG_INFO, " SpiEiss=3D %x\n", LockDownConfig->SpiEiss)); +} + +/** + Print PCH_SMBUS_CONFIG and serial out. + + @param[in] SmbusConfig Pointer to a PCH_SMBUS_CONFIG that provid= es the platform setting + +**/ +VOID +PchPrintSmbusConfig ( + IN CONST PCH_SMBUS_CONFIG *SmbusConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH SMBUS Config ---------------= ---\n")); + DEBUG ((DEBUG_INFO, " Enable=3D %x\n", SmbusConfig->Enable)); + DEBUG ((DEBUG_INFO, " ArpEnable=3D %x\n", SmbusConfig->ArpEnable)); + DEBUG ((DEBUG_INFO, " DynamicPowerGating=3D %x\n", SmbusConfig->DynamicP= owerGating)); + DEBUG ((DEBUG_INFO, " SmbusIoBase=3D %x\n", SmbusConfig->SmbusIoBase)); + DEBUG ((DEBUG_INFO, " NumRsvdSmbusAddresses=3D %x\n", SmbusConfig->NumRs= vdSmbusAddresses)); + DEBUG ((DEBUG_INFO, " RsvdSmbusAddressTable=3D {")); + for (i =3D 0; i < SmbusConfig->NumRsvdSmbusAddresses; ++i) { + DEBUG ((DEBUG_INFO, " %02xh", SmbusConfig->RsvdSmbusAddressTable[i])); + } + DEBUG ((DEBUG_INFO, " }\n")); +} + +/** + Print PCH_HDAUDIO_CONFIG and serial out. + + @param[in] HdaConfig Pointer to a PCH_HDAUDIO_CONFIG that provid= es the platform setting + +**/ +VOID +PchPrintHdAudioConfig ( + IN CONST PCH_HDAUDIO_CONFIG *HdaConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH HD-Audio Config ------------= ------\n")); + DEBUG ((DEBUG_INFO, " HDA Enable =3D %x\n", HdaConfig->Enabl= e)); + DEBUG ((DEBUG_INFO, " DSP Enable =3D %x\n", HdaConfig->DspEn= able)); + DEBUG ((DEBUG_INFO, " DSP UAA Compliance =3D %x\n", HdaConfig->DspUa= aCompliance)); + DEBUG ((DEBUG_INFO, " iDisp Codec Disconnect =3D %x\n", HdaConfig->IDisp= CodecDisconnect)); + DEBUG ((DEBUG_INFO, " Pme =3D %x\n", HdaConfig->Pme)); + DEBUG ((DEBUG_INFO, " I/O Buffer Ownership =3D %x\n", HdaConfig->IoBuf= ferOwnership)); + DEBUG ((DEBUG_INFO, " I/O Buffer Voltage =3D %x\n", HdaConfig->IoBuf= ferVoltage)); + DEBUG ((DEBUG_INFO, " VC Type =3D %x\n", HdaConfig->VcTyp= e)); + DEBUG ((DEBUG_INFO, " HD-A Link Frequency =3D %x\n", HdaConfig->HdAud= ioLinkFrequency)); + DEBUG ((DEBUG_INFO, " iDisp Link Frequency =3D %x\n", HdaConfig->IDisp= LinkFrequency)); + DEBUG ((DEBUG_INFO, " iDisp Link T-Mode =3D %x\n", HdaConfig->IDisp= LinkTmode)); + DEBUG ((DEBUG_INFO, " DSP Endpoint DMIC =3D %x\n", HdaConfig->DspEn= dpointDmic)); + DEBUG ((DEBUG_INFO, " DSP Endpoint I2S =3D %x\n", HdaConfig->DspEn= dpointI2s)); + DEBUG ((DEBUG_INFO, " DSP Endpoint BT =3D %x\n", HdaConfig->DspEn= dpointBluetooth)); + DEBUG ((DEBUG_INFO, " DSP Feature Mask =3D %x\n", HdaConfig->DspFe= atureMask)); + DEBUG ((DEBUG_INFO, " DSP PP Module Mask =3D %x\n", HdaConfig->DspPp= ModuleMask)); + DEBUG ((DEBUG_INFO, " ResetWaitTimer =3D %x\n", HdaConfig->Reset= WaitTimer)); +} + +/** + Print PCH_PM_CONFIG and serial out. + + @param[in] PmConfig Pointer to a PCH_PM_CONFIG that provides the= platform setting + +**/ +VOID +PchPrintPmConfig ( + IN CONST PCH_PM_CONFIG *PmConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH PM Config ------------------= \n")); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeWakeSts =3D %x\n", PmC= onfig->PowerResetStatusClear.MeWakeSts)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeHrstColdSts =3D %x\n", PmC= onfig->PowerResetStatusClear.MeHrstColdSts)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeHrstWarmSts =3D %x\n", PmC= onfig->PowerResetStatusClear.MeHrstWarmSts)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeHostPowerDn =3D %x\n", PmC= onfig->PowerResetStatusClear.MeHostPowerDn)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear WolOvrWkSts =3D %x\n", PmC= onfig->PowerResetStatusClear.WolOvrWkSts)); + + DEBUG ((DEBUG_INFO, " WakeConfig PmeB0S5Dis =3D %x\n", PmC= onfig->WakeConfig.PmeB0S5Dis)); + DEBUG ((DEBUG_INFO, " WakeConfig WolEnableOverride =3D %x\n", PmC= onfig->WakeConfig.WolEnableOverride)); + DEBUG ((DEBUG_INFO, " WakeConfig LanWakeFromDeepSx =3D %x\n", PmC= onfig->WakeConfig.LanWakeFromDeepSx)); + DEBUG ((DEBUG_INFO, " WakeConfig PcieWakeFromDeepSx =3D %x\n", PmC= onfig->WakeConfig.PcieWakeFromDeepSx)); + DEBUG ((DEBUG_INFO, " WakeConfig WoWlanEnable =3D %x\n", PmC= onfig->WakeConfig.WoWlanEnable)); + DEBUG ((DEBUG_INFO, " WakeConfig WoWlanDeepSxEnable =3D %x\n", PmC= onfig->WakeConfig.WoWlanDeepSxEnable)); + + DEBUG ((DEBUG_INFO, " PchDeepSxPol =3D %x\n", PmC= onfig->PchDeepSxPol)); + DEBUG ((DEBUG_INFO, " PchSlpS3MinAssert =3D %x\n", PmC= onfig->PchSlpS3MinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpS4MinAssert =3D %x\n", PmC= onfig->PchSlpS4MinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpSusMinAssert =3D %x\n", PmC= onfig->PchSlpSusMinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpAMinAssert =3D %x\n", PmC= onfig->PchSlpAMinAssert)); + DEBUG ((DEBUG_INFO, " PciClockRun =3D %x\n", PmC= onfig->PciClockRun)); + DEBUG ((DEBUG_INFO, " SlpStrchSusUp =3D %x\n", PmC= onfig->SlpStrchSusUp)); + DEBUG ((DEBUG_INFO, " SlpLanLowDc =3D %x\n", PmC= onfig->SlpLanLowDc)); + DEBUG ((DEBUG_INFO, " PwrBtnOverridePeriod =3D %x\n", PmC= onfig->PwrBtnOverridePeriod)); + DEBUG ((DEBUG_INFO, " DisableEnergyReport =3D %x\n", PmC= onfig->DisableEnergyReport)); + DEBUG ((DEBUG_INFO, " DisableDsxAcPresentPulldown =3D %x\n", PmC= onfig->DisableDsxAcPresentPulldown)); + DEBUG ((DEBUG_INFO, " PmcReadDisable =3D %x\n", PmC= onfig->PmcReadDisable)); + DEBUG ((DEBUG_INFO, " PchPwrCycDur =3D %x\n", PmC= onfig->PchPwrCycDur)); + DEBUG ((DEBUG_INFO, " PciePllSsc =3D %x\n", PmC= onfig->PciePllSsc)); + DEBUG ((DEBUG_INFO, " CapsuleResetType =3D %x\n", PmC= onfig->CapsuleResetType)); + DEBUG ((DEBUG_INFO, " DisableNativePowerButton =3D %x\n", PmC= onfig->DisableNativePowerButton)); + DEBUG ((DEBUG_INFO, " SlpS0Enabled =3D %x\n", PmC= onfig->SlpS0Enable)); +} + +/** + Print PCH_DMI_CONFIG and serial out. + + @param[in] DmiConfig Pointer to a PCH_DMI_CONFIG that provides t= he platform setting + +**/ +VOID +PchPrintDmiConfig ( + IN CONST PCH_DMI_CONFIG *DmiConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH DMI Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, " DmiAspm=3D %x\n", DmiConfig->DmiAspm)); + DEBUG ((DEBUG_INFO, " PwrOptEnable=3D %x\n", DmiConfig->PwrOptEnable)); + +} + +/** + Print PCH_LPC_SIRQ_CONFIG and serial out. + + @param[in] SerialIrqConfig Pointer to a PCH_LPC_SIRQ_CONFIG that= provides the platform setting + +**/ +VOID +PchPrintSerialIrqConfig ( + IN CONST PCH_LPC_SIRQ_CONFIG *SerialIrqConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LPC SIRQ Config ------------= ------\n")); + DEBUG ((DEBUG_INFO, " SirqEnable=3D %x\n", SerialIrqConfig->SirqEnable)); + DEBUG ((DEBUG_INFO, " SirqMode=3D %x\n", SerialIrqConfig->SirqMode)); + DEBUG ((DEBUG_INFO, " StartFramePulse=3D %x\n", SerialIrqConfig->StartFr= amePulse)); +} + +/** + Print PCH_THERMAL_CONFIG and serial out. + + @param[in] ThermalConfig Pointer to a PCH_THERMAL_CONFIG that pr= ovides the platform setting + +**/ +VOID +PchPrintThermalConfig ( + IN CONST PCH_THERMAL_CONFIG *ThermalConfig + ) +{ + UINTN i; + + DEBUG ((DEBUG_INFO, "------------------ PCH Thermal Config -------------= -----\n")); + DEBUG ((DEBUG_INFO, " TsmicLock=3D %x\n", ThermalConfig->TsmicLock)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels T0Level %x centigrade d= egree\n", ThermalConfig->ThermalThrottling.TTLevels.T0Level)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels T1Level %x centigrade d= egree\n", ThermalConfig->ThermalThrottling.TTLevels.T1Level)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels T2Level %x centigrade d= egree\n", ThermalConfig->ThermalThrottling.TTLevels.T2Level)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels TTEnable %x\n", Thermal= Config->ThermalThrottling.TTLevels.TTEnable)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels TTState13Enable %x\n", = ThermalConfig->ThermalThrottling.TTLevels.TTState13Enable)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels TTLock %x\n", ThermalCo= nfig->ThermalThrottling.TTLevels.TTLock)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels SuggestedSetting %x\n",= ThermalConfig->ThermalThrottling.TTLevels.SuggestedSetting)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels PchCrossThrottling %x\n= ", ThermalConfig->ThermalThrottling.TTLevels.PchCrossThrottling)); + + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC DmiTsawEn %x\n", Therma= lConfig->ThermalThrottling.DmiHaAWC.DmiTsawEn)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS0TW %x\n", ThermalCon= fig->ThermalThrottling.DmiHaAWC.TS0TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS1TW %x\n", ThermalCon= fig->ThermalThrottling.DmiHaAWC.TS1TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS2TW %x\n", ThermalCon= fig->ThermalThrottling.DmiHaAWC.TS2TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS3TW %x\n", ThermalCon= fig->ThermalThrottling.DmiHaAWC.TS3TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC SuggestedSetting %x\n",= ThermalConfig->ThermalThrottling.DmiHaAWC.SuggestedSetting)); + + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0T1M %x\n", ThermalConfi= g->ThermalThrottling.SataTT.P0T1M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0T2M %x\n", ThermalConfi= g->ThermalThrottling.SataTT.P0T2M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0T3M %x\n", ThermalConfi= g->ThermalThrottling.SataTT.P0T3M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0TDisp %x\n", ThermalCon= fig->ThermalThrottling.SataTT.P0TDisp)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0Tinact %x\n", ThermalCo= nfig->ThermalThrottling.SataTT.P0Tinact)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0TDispFinit %x\n", Therm= alConfig->ThermalThrottling.SataTT.P0TDispFinit)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1T1M %x\n", ThermalConfi= g->ThermalThrottling.SataTT.P1T1M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1T2M %x\n", ThermalConfi= g->ThermalThrottling.SataTT.P1T2M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1T3M %x\n", ThermalConfi= g->ThermalThrottling.SataTT.P1T3M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1TDisp %x\n", ThermalCon= fig->ThermalThrottling.SataTT.P1TDisp)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1Tinact %x\n", ThermalCo= nfig->ThermalThrottling.SataTT.P1Tinact)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1TDispFinit %x\n", Therm= alConfig->ThermalThrottling.SataTT.P1TDispFinit)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT SuggestedSetting %x\n", T= hermalConfig->ThermalThrottling.SataTT.SuggestedSetting)); + + DEBUG ((DEBUG_INFO, " MemoryThrottling Enable=3D %x\n", ThermalConfig->M= emoryThrottling.Enable)); + for (i =3D 0; i < MaxTsGpioPin; i++) { + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting PmsyncEnable= =3D %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[i].PmsyncEnable= )); + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting C0TransmitEnab= le=3D %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[i].C0Transmit= Enable)); + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting PinSelection= =3D %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[i].PinSelection= )); + } + DEBUG ((DEBUG_INFO, " PchHotLevel =3D %x\n", ThermalConfig->PchHotLevel)= ); + DEBUG ((DEBUG_INFO, " ThermalDeviceEnable %x\n", ThermalConfig->ThermalD= eviceEnable)); +} + +/** + Print PCH_GENERAL_CONFIG and serial out. + + @param[in] PchConfig Pointer to a PCH_GENERAL_CONFIG that provid= es the platform setting + +**/ +VOID +PchPrintGeneralConfig ( + IN CONST PCH_GENERAL_CONFIG *PchConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH General Config -------------= -----\n")); + DEBUG ((DEBUG_INFO, " SubSystemVendorId=3D %x\n", PchConfig->SubSystemVe= ndorId)); + DEBUG ((DEBUG_INFO, " SubSystemId=3D %x\n", PchConfig->SubSystemId)); + DEBUG ((DEBUG_INFO, " Crid=3D %x\n", PchConfig->Crid)); +} + +/** + Print PCH_LAN_CONFIG and serial out. + + @param[in] LanConfig Pointer to a PCH_LAN_CONFIG that provides t= he platform setting + +**/ +VOID +PchPrintLanConfig ( + IN CONST PCH_LAN_CONFIG *LanConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LAN Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, " Enable=3D %x\n", LanConfig->Enable)); + DEBUG ((DEBUG_INFO, " K1OffEnable=3D %x\n", LanConfig->K1OffEnable)); + DEBUG ((DEBUG_INFO, " ClkReqSupported=3D %d\n", LanConfig->ClkReqSupport= ed)); + DEBUG ((DEBUG_INFO, " ClkReqNumber=3D %d\n", LanConfig->ClkReqNumber)); +} + + +/** + Print PCH_INTERRUPT_CONFIG and serial out + + @param[in] InterruptConfig Pointer to Interrupt Configuration str= ucture + +**/ +VOID +PchPrintInterruptConfig ( + IN CONST PCH_INTERRUPT_CONFIG *InterruptConfig + ) +{ + UINTN i; + // + // Print interrupt information + // + DEBUG ((DEBUG_INFO, "------------------ PCH Interrupt Config -----------= -------\n")); + DEBUG ((DEBUG_INFO, " Interrupt assignment:\n")); + DEBUG ((DEBUG_INFO, " Dxx:Fx INTx IRQ\n")); + for (i =3D 0; i < InterruptConfig->NumOfDevIntConfig; i++) { + DEBUG ((DEBUG_INFO, " D%02d:F%d %d %03d\n", + InterruptConfig->DevIntConfig[i].Device, + InterruptConfig->DevIntConfig[i].Function, + InterruptConfig->DevIntConfig[i].IntX, + InterruptConfig->DevIntConfig[i].Irq)); + } + DEBUG ((DEBUG_INFO, " Legacy PIC interrupt routing:\n")); + DEBUG ((DEBUG_INFO, " PIRQx IRQx\n")); + for (i =3D 0; i < PCH_MAX_PXRC_CONFIG; i++) { + DEBUG ((DEBUG_INFO, " PIRQ%c -> IRQ%d\n", i + 65, InterruptConfig->Px= RcConfig[i])); + } + DEBUG ((DEBUG_INFO, " Other interrupt configuration:\n")); + DEBUG ((DEBUG_INFO, " GpioIrqRoute=3D %d\n", InterruptConfig->GpioIrqRo= ute)); + DEBUG ((DEBUG_INFO, " SciIrqSelect=3D %d\n", InterruptConfig->SciIrqSel= ect)); + DEBUG ((DEBUG_INFO, " TcoIrqEnable=3D %d\n", InterruptConfig->TcoIrqEna= ble)); + DEBUG ((DEBUG_INFO, " TcoIrqSelect=3D %d\n", InterruptConfig->TcoIrqSel= ect)); +} + + +/** + Print PCH_FLASH_PROTECTION_CONFIG and serial out. + + @param[in] FlashProtectConfig Pointer to a PCH_FLASH_PROTECTION_CONFIG = that provides the platform setting + +**/ +VOID +PchPrintFlashProtectionConfig ( + IN CONST PCH_FLASH_PROTECTION_CONFIG *FlashProtectConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH Flash Protection Config ----= --------------\n")); + for (i =3D 0; i < PCH_FLASH_PROTECTED_RANGES; ++i) { + DEBUG ((DEBUG_INFO, " WriteProtectionEnable[%d]=3D %x\n", i, FlashProt= ectConfig->ProtectRange[i].WriteProtectionEnable)); + DEBUG ((DEBUG_INFO, " ReadProtectionEnable[%d]=3D %x\n", i, FlashProte= ctConfig->ProtectRange[i].ReadProtectionEnable)); + DEBUG ((DEBUG_INFO, " ProtectedRangeLimit[%d]=3D %x\n", i, FlashProtec= tConfig->ProtectRange[i].ProtectedRangeLimit)); + DEBUG ((DEBUG_INFO, " ProtectedRangeBase[%d]=3D %x\n", i, FlashProtect= Config->ProtectRange[i].ProtectedRangeBase)); + } +} + +/** + Print PCH_WDT_CONFIG and serial out. + + @param[in] WdtConfig Pointer to a PCH_WDT_CONFIG that p= rovides the platform setting + +**/ +VOID +PchPrintWdtConfig ( + IN CONST PCH_WDT_CONFIG *WdtConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH WDT Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, "DisableAndLock=3D %x\n", WdtConfig->DisableAndLock)= ); +} + +/** + Print PCH_P2SB_CONFIG and serial out. + + @param[in] P2sbConfig Pointer to a PCH_P2SB_CONFIG that = provides the platform setting + +**/ +VOID +PchPrintP2sbConfig ( + IN CONST PCH_P2SB_CONFIG *P2sbConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH P2SB Config ----------------= --\n")); + DEBUG ((DEBUG_INFO, "SbiUnlock=3D %x\n", P2sbConfig->SbiUnlock)); + DEBUG ((DEBUG_INFO, "PsfUnlock=3D %x\n", P2sbConfig->PsfUnlock)); +} + +/** + Print PCH_DCI_CONFIG and serial out. + + @param[in] DciConfig Pointer to a PCH_DCI_CONFIG that p= rovides the platform setting + +**/ +VOID +PchPrintDciConfig ( + IN CONST PCH_DCI_CONFIG *DciConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH DCI Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, "DciEn=3D %x\n", DciConfig->DciEn)); + DEBUG ((DEBUG_INFO, "DciAutoDetect=3D %x\n", DciConfig->DciAutoDetect)); +} + +/** + Print PCH_LPC_CONFIG and serial out. + + @param[in] LpcConfig Pointer to a PCH_LPC_CONFIG that p= rovides the platform setting + +**/ +VOID +PchPrintLpcConfig ( + IN CONST PCH_LPC_CONFIG *LpcConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LPC Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, "EnhancePort8xhDecoding=3D %x\n", LpcConfig->Enhance= Port8xhDecoding)); +} + +/** + Print PCH_SPI_CONFIG and serial out. + + @param[in] SpiConfig Pointer to a PCH_SPI_CONFIG that p= rovides the platform setting + +**/ +VOID +PchPrintSpiConfig ( + IN CONST PCH_SPI_CONFIG *SpiConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH SPI Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, "ShowSpiController=3D %x\n", SpiConfig->ShowSpiContr= oller)); +} + +/** + Print whole PCH_POLICY_PPI and serial out. + + @param[in] PchPolicyPpi The RC Policy PPI instance + +**/ +VOID +PchPrintPolicyPpi ( + IN PCH_POLICY_PPI *PchPolicyPpi + ) +{ +DEBUG_CODE_BEGIN(); + DEBUG ((DEBUG_INFO, "------------------------ PCH Print Platform Protoco= l Start ------------------------\n")); + DEBUG ((DEBUG_INFO, " Revision=3D %x\n", PchPolicyPpi->Revision)); + DEBUG ((DEBUG_INFO, " Port80Route=3D %x\n", PchPolicyPpi->Port80Route)); + DEBUG ((DEBUG_INFO, " AcpiBase=3D %x\n", PchPolicyPpi->AcpiBase)); + + PchPrintGeneralConfig (&PchPolicyPpi->PchConfig); + + PchPrintPcieConfig (&PchPolicyPpi->PcieConfig, &PchPolicyPpi->HsioPcieCo= nfig); + + PchPrintPcieConfig2 (&PchPolicyPpi->PcieConfig2); + + PchPrintSataConfig (&PchPolicyPpi->SataConfig, &PchPolicyPpi->HsioSataC= onfig, PCH_SATA_FIRST_CONTROLLER); + PchPrintSataConfig (&PchPolicyPpi->sSataConfig, &PchPolicyPpi->HsiosSata= Config, PCH_SATA_SECOND_CONTROLLER); + PchPrintUsbConfig (&PchPolicyPpi->UsbConfig); + + PchPrintIoApicConfig (&PchPolicyPpi->IoApicConfig); + + PchPrintHpetConfig (&PchPolicyPpi->HpetConfig); + + PchPrintHdAudioConfig (&PchPolicyPpi->HdAudioConfig); + + PchPrintLanConfig (&PchPolicyPpi->LanConfig); + + PchPrintSmbusConfig (&PchPolicyPpi->SmbusConfig); + + PchPrintLockDownConfig (&PchPolicyPpi->LockDownConfig); + + PchPrintThermalConfig (&PchPolicyPpi->ThermalConfig); + + PchPrintPmConfig (&PchPolicyPpi->PmConfig); + + PchPrintDmiConfig (&PchPolicyPpi->DmiConfig); + + PchPrintSerialIrqConfig (&PchPolicyPpi->SerialIrqConfig); + + + PchPrintFlashProtectionConfig (&PchPolicyPpi->FlashProtectConfig); + + PchPrintWdtConfig (&PchPolicyPpi->WdtConfig); + + PchPrintP2sbConfig (&PchPolicyPpi->P2sbConfig); + + PchPrintDciConfig (&PchPolicyPpi->DciConfig); + + PchPrintLpcConfig (&PchPolicyPpi->LpcConfig); + + PchPrintSpiConfig (&PchPolicyPpi->SpiConfig); + + DEBUG ((DEBUG_INFO, "------------------------ PCH Print Platform Protoco= l End --------------------------\n")); +DEBUG_CODE_END(); +} + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicy= Lib/PeiPchPolicyLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/P= eiPchPolicyLib/PeiPchPolicyLib.c new file mode 100644 index 0000000000..c5f9c39265 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/Pei= PchPolicyLib.c @@ -0,0 +1,581 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiPchPolicyLibrary.h" +#include + +/** + mDevIntConfig[] table contains data on INTx and IRQ for each device. + IRQ value for devices which use ITSS INTx->PIRQx mapping need to be set = in a way + that for each multifunctional Dxx:Fy same interrupt pins must map to the= same IRQ. + Those IRQ values will be used to update ITSS.PIRx register. + In APIC relationship between PIRQs and IRQs is: + PIRQA -> IRQ16 + PIRQB -> IRQ17 + PIRQC -> IRQ18 + PIRQD -> IRQ19 + PIRQE -> IRQ20 + PIRQF -> IRQ21 + PIRQG -> IRQ22 + PIRQH -> IRQ23 + + Devices which use INTx->PIRQy mapping are: cAVS(in PCI mode), SMBus, GbE= , TraceHub, PCIe, + SATA, HECI, IDE-R, KT Redirection, xHCI, Thermal Subsystem, Camera IO Ho= st Controller + + PCI Express Root Ports mapping should be programmed only with values as = in below table (D27/28/29) + otherwise _PRT methods in ACPI for RootPorts would require additional pa= tching as + PCIe Endpoint Device Interrupt is further subjected to INTx to PIRQy Map= ping + + Configured IRQ values are not used if an OS chooses to be in PIC instead= of APIC mode +**/ +GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mDevIntConfig[] = =3D { +// {31, 0, PchNoInt, 0}, // LPC/eSPI Interface, doesn't use interrupts +// {31, 1, PchNoInt, 0}, // P2SB, doesn't use interrupts +// {31, 2, PchNoInt, 0}, // PMC , doesn't use interrupts + {31, 3, PchIntA, 16}, // cAVS(Audio, Voice, Speach), INTA is default, pr= ogrammed in PciCfgSpace 3Dh + {31, 4, PchIntA, 16}, // SMBus Controller, no default value, programmed = in PciCfgSpace 3Dh +// {31, 5, PchNoInt, 0}, // SPI , doesn't use interrupts + {31, 6, PchIntA, 16}, // GbE Controller, INTA is default, programmed in = PciCfgSpace 3Dh + {31, 7, PchIntA, 16}, // TraceHub, INTA is default, RO register + {29, 0, PchIntA, 16}, // PCI Express Port 9, INT is default, programmed = in PciCfgSpace + FCh + {29, 1, PchIntB, 17}, // PCI Express Port 10, INT is default, programmed= in PciCfgSpace + FCh + {29, 2, PchIntC, 18}, // PCI Express Port 11, INT is default, programmed= in PciCfgSpace + FCh + {29, 3, PchIntD, 19}, // PCI Express Port 12, INT is default, programmed= in PciCfgSpace + FCh + {29, 4, PchIntA, 16}, // PCI Express Port 13 (SKL PCH-H Only), INT is de= fault, programmed in PciCfgSpace + FCh + {29, 5, PchIntB, 17}, // PCI Express Port 14 (SKL PCH-H Only), INT is de= fault, programmed in PciCfgSpace + FCh + {29, 6, PchIntC, 18}, // PCI Express Port 15 (SKL PCH-H Only), INT is de= fault, programmed in PciCfgSpace + FCh + {29, 7, PchIntD, 19}, // PCI Express Port 16 (SKL PCH-H Only), INT is de= fault, programmed in PciCfgSpace + FCh + {28, 0, PchIntA, 16}, // PCI Express Port 1, INT is default, programmed = in PciCfgSpace + FCh + {28, 1, PchIntB, 17}, // PCI Express Port 2, INT is default, programmed = in PciCfgSpace + FCh + {28, 2, PchIntC, 18}, // PCI Express Port 3, INT is default, programmed = in PciCfgSpace + FCh + {28, 3, PchIntD, 19}, // PCI Express Port 4, INT is default, programmed = in PciCfgSpace + FCh + {28, 4, PchIntA, 16}, // PCI Express Port 5, INT is default, programmed = in PciCfgSpace + FCh + {28, 5, PchIntB, 17}, // PCI Express Port 6, INT is default, programmed = in PciCfgSpace + FCh + {28, 6, PchIntC, 18}, // PCI Express Port 7, INT is default, programmed = in PciCfgSpace + FCh + {28, 7, PchIntD, 19}, // PCI Express Port 8, INT is default, programmed = in PciCfgSpace + FCh + {27, 0, PchIntA, 16}, // PCI Express Port 17 (SKL PCH-H Only), INT is de= fault, programmed in PciCfgSpace + FCh + {27, 1, PchIntB, 17}, // PCI Express Port 18 (SKL PCH-H Only), INT is de= fault, programmed in PciCfgSpace + FCh + {27, 2, PchIntC, 18}, // PCI Express Port 19 (SKL PCH-H Only), INT is de= fault, programmed in PciCfgSpace + FCh + {27, 3, PchIntD, 19}, // PCI Express Port 20 (SKL PCH-H Only), INT is de= fault, programmed in PciCfgSpace + FCh +// {24, 0, 0, 0}, // Reserved (used by RST PCIe Storage Cycle Router) + {23, 0, PchIntA, 16}, // SATA Controller, INTA is default, programmed in= PciCfgSpace + 3Dh + {22, 0, PchIntA, 16}, // CSME: HECI #1 + {22, 1, PchIntB, 17}, // CSME: HECI #2 + {22, 2, PchIntC, 18}, // CSME: IDE-Redirection (IDE-R) + {22, 3, PchIntD, 19}, // CSME: Keyboard and Text (KT) Redirection + {22, 4, PchIntA, 16}, // CSME: HECI #3 +// {22, 7, PchNoInt, 0}, // CSME: WLAN + {20, 0, PchIntA, 16}, // USB 3.0 xHCI Controller, no default value, prog= rammed in PciCfgSpace 3Dh + {20, 2, PchIntC, 18}, // Thermal Subsystem +// {20, 4, 0, 0}, // TraceHub Phantom (ACPI) Function +// {18, 0, PchNoInt, 0}, // CSME: KVMcc, doesn't use interrupts +// {18, 1, PchNoInt, 0}, // CSME: Clink, doesn't use interrupts +// {18, 2, PchNoInt, 0}, // CSME: PMT, doesn't use interrupts +// {18, 3, 0, 0}, // CSME: CSE UMA +// {18, 4, 0, 0} // CSME: fTPM DMA + {17, 5, PchIntA, 16} // SSATA controller. +#ifdef IE_SUPPORT + , +// {16, 0, PchIntA, 16}, // IE: HECI #1 +// {16, 1, PchIntB, 17}, // IE: HECI #2 +// {16, 2, PchIntC, 18}, // IE: IDE-Redirection (IDE-R) + {16, 3, PchIntD, 19} // IE: Keyboard and Text (KT) Redirection +// {16, 4, PchIntA, 16} // IE: HECI #3 +#endif // IE_SUPPORT +}; + +// +// mLpOnlyDevIntConfig[] table contains data on INTx and IRQ for devices t= hat exist on SPT-LP but not on SPT-H. +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mLpOnlyDevIntCon= fig[] =3D { + {25, 1, PchIntB, 33}, // SerialIo I2C Controller #5, INTA is default, pr= ogrammed in PCR[SERIALIO] + PCICFGCTRL[6] + {25, 2, PchIntC, 34} // SerialIo I2C Controller #4, INTA is default, pr= ogrammed in PCR[SERIALIO] + PCICFGCTRL[5] +}; +/** + mPxRcConfig[] table contains data for 8259 routing (how PIRQx is mapped = to IRQy). + This information is used by systems which choose to use legacy PIC + interrupt controller. Only IRQ3-7,9-12,14,15 are valid. Values from this= table + will be programmed into ITSS.PxRC registers. +**/ +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPxRcConfig[] =3D { + 11, // PARC: PIRQA -> IRQ11 + 10, // PBRC: PIRQB -> IRQ10 + 11, // PCRC: PIRQC -> IRQ11 + 11, // PDRC: PIRQD -> IRQ11 + 11, // PERC: PIRQE -> IRQ11 + 11, // PFRC: PIRQF -> IRQ11 + 11, // PGRC: PIRQG -> IRQ11 + 11 // PHRC: PIRQH -> IRQ11 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusRsvdAddresses[] =3D { + 0xA0, + 0xA2, + 0xA4, + 0xA6 +}; + +/** + PchCreatePolicyDefaults creates the default setting of PCH Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] PchPolicyPpi The pointer to get PCH Policy PPI instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +PchCreatePolicyDefaults ( + OUT PCH_POLICY_PPI **PchPolicyPpi + ) +{ + PCH_POLICY_PPI *PchPolicy; + PCH_SERIES PchSeries; + UINT32 PortIndex; + UINT32 Index; + UINT8 IntConfigTableEntries; + + PchSeries =3D GetPchSeries (); + + PchPolicy =3D (PCH_POLICY_PPI *) AllocateZeroPool (sizeof (PCH_POLICY_PP= I)); + if (PchPolicy =3D=3D NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + // + // Policy not listed here are set to 0/FALSE as default. + // + + /******************************** + General initialization + ********************************/ + PchPolicy->Revision =3D PCH_POLICY_REVISION; + PchPolicy->AcpiBase =3D PcdGet16 (PcdPchAcpiIoPortBaseAdd= ress); + PchPolicy->TempMemBaseAddr =3D PCH_TEMP_BASE_ADDRESS; + + /******************************** + PCH general configuration + ********************************/ + // + // Default Svid Sdid configuration + // + PchPolicy->PchConfig.SubSystemVendorId =3D V_PCH_INTEL_VENDOR_ID; + PchPolicy->PchConfig.SubSystemId =3D V_PCH_DEFAULT_SID; + + /******************************** + PCI Express related settings + ********************************/ + + PchPolicy->TempPciBusMin =3D 2; + PchPolicy->TempPciBusMax =3D 10; + + PchPolicy->PcieConfig.RpFunctionSwap =3D TRUE; + + for (PortIndex =3D 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { + PchPolicy->PcieConfig.RootPort[PortIndex].Aspm =3D Pch= PcieAspmAutoConfig; + PchPolicy->PcieConfig.RootPort[PortIndex].Enable =3D TRU= E; + PchPolicy->PcieConfig.RootPort[PortIndex].PmSci =3D TRU= E; + PchPolicy->PcieConfig.RootPort[PortIndex].AcsEnabled =3D TRU= E; + + PchPolicy->PcieConfig.RootPort[PortIndex].MaxPayload =3D Pch= PcieMaxPayload256; + + PchPolicy->PcieConfig.RootPort[PortIndex].PhysicalSlotNumber =3D (UI= NT8) PortIndex; + + PchPolicy->PcieConfig.RootPort[PortIndex].L1Substates =3D Pch= PcieL1SubstatesL1_1_2; + + // + // PCIe LTR Configuration. + // + PchPolicy->PcieConfig.RootPort[PortIndex].LtrEnable =3D TR= UE; + if (PchSeries =3D=3D PchLp) { + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxSnoopLatency = =3D 0x1003; + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxNoSnoopLatency = =3D 0x1003; + } + if (PchSeries =3D=3D PchH) { + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxSnoopLatency = =3D 0x0846; + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxNoSnoopLatency = =3D 0x0846; + } + PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideMode = =3D 2; + PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideMultipli= er =3D 2; + PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideValue = =3D 60; + PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideMode = =3D 2; + PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideMulti= plier =3D 2; + PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideValue= =3D 60; + + PchPolicy->PcieConfig.RootPort[PortIndex].Uptp = =3D 5; + PchPolicy->PcieConfig.RootPort[PortIndex].Dptp = =3D 7; + } + + for (Index =3D 0; Index < GetPchMaxPciePortNum (); ++Index) { + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm =3D 6; + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp =3D 6; + } + + PchPolicy->PcieConfig2.SwEqCoeffList[0].Cm =3D 6; + PchPolicy->PcieConfig2.SwEqCoeffList[0].Cp =3D 8; + PchPolicy->PcieConfig2.SwEqCoeffList[1].Cm =3D 8; + PchPolicy->PcieConfig2.SwEqCoeffList[1].Cp =3D 2; + PchPolicy->PcieConfig2.SwEqCoeffList[2].Cm =3D 10; + PchPolicy->PcieConfig2.SwEqCoeffList[2].Cp =3D 6; + PchPolicy->PcieConfig2.SwEqCoeffList[3].Cm =3D 12; + PchPolicy->PcieConfig2.SwEqCoeffList[3].Cp =3D 8; + PchPolicy->PcieConfig2.SwEqCoeffList[4].Cm =3D 14; + PchPolicy->PcieConfig2.SwEqCoeffList[4].Cp =3D 2; + + /******************************** + SATA related settings + ********************************/ + PchPolicy->SataConfig.Enable =3D TRUE; + PchPolicy->SataConfig.SalpSupport =3D TRUE; + PchPolicy->SataConfig.SataMode =3D PchSataModeAhci; + + for (PortIndex =3D 0; PortIndex < GetPchMaxSataPortNum (); PortIndex++) { + PchPolicy->SataConfig.PortSettings[PortIndex].Enable =3D TRU= E; + PchPolicy->SataConfig.PortSettings[PortIndex].DmVal =3D 15; + PchPolicy->SataConfig.PortSettings[PortIndex].DitoVal =3D 625; + } + + PchPolicy->SataConfig.Rst.Raid0 =3D TRUE; + PchPolicy->SataConfig.Rst.Raid1 =3D TRUE; + PchPolicy->SataConfig.Rst.Raid10 =3D TRUE; + PchPolicy->SataConfig.Rst.Raid5 =3D TRUE; + PchPolicy->SataConfig.Rst.Irrt =3D TRUE; + PchPolicy->SataConfig.Rst.OromUiBanner =3D TRUE; + PchPolicy->SataConfig.Rst.OromUiDelay =3D PchSataOromDelay2sec; + PchPolicy->SataConfig.Rst.HddUnlock =3D TRUE; + PchPolicy->SataConfig.Rst.LedLocate =3D TRUE; + PchPolicy->SataConfig.Rst.IrrtOnly =3D TRUE; + PchPolicy->SataConfig.Rst.SmartStorage =3D TRUE; + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].DeviceResetDelay = =3D 100; + } + /******************************** + sSATA related settings + ********************************/ + PchPolicy->sSataConfig.Enable =3D TRUE; + // PchPolicy->sSataConfig.TestMode =3D FALSE; + // PchPolicy->sSataConfig.LegacyMode =3D FALSE; + PchPolicy->sSataConfig.SalpSupport =3D TRUE; + // PchPolicy->sSataConfig.eSATASpeedLimit =3D FALSE; + PchPolicy->sSataConfig.SataMode =3D PchSataModeAhci; + // PchPolicy->sSataConfig.SpeedLimit =3D PchsSataSpeedDefault; + + for (PortIndex =3D 0; PortIndex < GetPchMaxsSataPortNum (); PortIndex++)= { + PchPolicy->sSataConfig.PortSettings[PortIndex].Enable =3D = TRUE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].HotPlug = =3D FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].InterlockSw = =3D FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].External = =3D FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].SpinUp = =3D FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].SolidStateDrive = =3D FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].DevSlp = =3D FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].EnableDitoConfig = =3D FALSE; + PchPolicy->sSataConfig.PortSettings[PortIndex].DmVal =3D = 15; + PchPolicy->sSataConfig.PortSettings[PortIndex].DitoVal =3D = 625; + } + + // PchPolicy->sSataConfig.Rst.RaidAlternateId =3D FALSE; + PchPolicy->sSataConfig.Rst.Raid0 =3D TRUE; + PchPolicy->sSataConfig.Rst.Raid1 =3D TRUE; + PchPolicy->sSataConfig.Rst.Raid10 =3D TRUE; + PchPolicy->sSataConfig.Rst.Raid5 =3D TRUE; + PchPolicy->sSataConfig.Rst.Irrt =3D TRUE; + PchPolicy->sSataConfig.Rst.OromUiBanner =3D TRUE; + PchPolicy->sSataConfig.Rst.OromUiDelay =3D PchSataOromDelay2sec; + PchPolicy->sSataConfig.Rst.HddUnlock =3D TRUE; + PchPolicy->sSataConfig.Rst.LedLocate =3D TRUE; + PchPolicy->sSataConfig.Rst.IrrtOnly =3D TRUE; + PchPolicy->sSataConfig.Rst.SmartStorage =3D TRUE; + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + //PchPolicy->sSataConfig.RstPcieStorageRemap[Index].Enable = =3D 0; + //PchPolicy->sSataConfig.RstPcieStorageRemap[Index].RstPcieStoragePo= rt =3D 0; + PchPolicy->sSataConfig.RstPcieStorageRemap[Index].DeviceResetDelay = =3D 100; + } + + /******************************** + USB related configuration + ********************************/ + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex= ++) { + PchPolicy->UsbConfig.PortUsb20[PortIndex].Enable =3D TRUE; + } + + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex= ++) { + PchPolicy->UsbConfig.PortUsb30[PortIndex].Enable =3D TRUE; + } + // + //XHCI Wake On USB Disabled + // + PchPolicy->UsbConfig.XhciWakeOnUsb =3D FALSE; + // + // USB Port Over Current Pins mapping, please set as per board layout. + // Default is PchUsbOverCurrentPin0(0) + // + PchPolicy->UsbConfig.PortUsb20[ 2].OverCurrentPin =3D PchUsbOverCurrentP= in1; + PchPolicy->UsbConfig.PortUsb20[ 3].OverCurrentPin =3D PchUsbOverCurrentP= in1; + PchPolicy->UsbConfig.PortUsb20[ 4].OverCurrentPin =3D PchUsbOverCurrentP= in2; + PchPolicy->UsbConfig.PortUsb20[ 5].OverCurrentPin =3D PchUsbOverCurrentP= in2; + PchPolicy->UsbConfig.PortUsb20[ 6].OverCurrentPin =3D PchUsbOverCurrentP= in3; + PchPolicy->UsbConfig.PortUsb20[ 7].OverCurrentPin =3D PchUsbOverCurrentP= in3; + PchPolicy->UsbConfig.PortUsb20[ 8].OverCurrentPin =3D PchUsbOverCurrentP= in4; + PchPolicy->UsbConfig.PortUsb20[ 9].OverCurrentPin =3D PchUsbOverCurrentP= in4; + PchPolicy->UsbConfig.PortUsb20[10].OverCurrentPin =3D PchUsbOverCurrentP= in5; + PchPolicy->UsbConfig.PortUsb20[11].OverCurrentPin =3D PchUsbOverCurrentP= in5; + PchPolicy->UsbConfig.PortUsb20[12].OverCurrentPin =3D PchUsbOverCurrentP= in6; + PchPolicy->UsbConfig.PortUsb20[13].OverCurrentPin =3D PchUsbOverCurrentP= in6; + PchPolicy->UsbConfig.PortUsb20[14].OverCurrentPin =3D PchUsbOverCurrentP= in7; + PchPolicy->UsbConfig.PortUsb20[15].OverCurrentPin =3D PchUsbOverCurrentP= in7; + + PchPolicy->UsbConfig.PortUsb30[2].OverCurrentPin =3D PchUsbOverCurrentP= in1; + PchPolicy->UsbConfig.PortUsb30[3].OverCurrentPin =3D PchUsbOverCurrentP= in1; + PchPolicy->UsbConfig.PortUsb30[4].OverCurrentPin =3D PchUsbOverCurrentP= in2; + PchPolicy->UsbConfig.PortUsb30[5].OverCurrentPin =3D PchUsbOverCurrentP= in2; + PchPolicy->UsbConfig.PortUsb30[6].OverCurrentPin =3D PchUsbOverCurrentP= in3; + PchPolicy->UsbConfig.PortUsb30[7].OverCurrentPin =3D PchUsbOverCurrentP= in3; + PchPolicy->UsbConfig.PortUsb30[8].OverCurrentPin =3D PchUsbOverCurrentP= in4; + PchPolicy->UsbConfig.PortUsb30[9].OverCurrentPin =3D PchUsbOverCurrentP= in4; + + // + // Default values of USB2 AFE settings. + // + for (Index =3D 0; Index < PCH_H_XHCI_MAX_USB2_PORTS; Index++) { + + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Petxiset =3D 7; + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Txiset =3D 0; + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Predeemp =3D 2; + + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Pehalfbit =3D 1; + } + + // + // Enable/Disable SSIC support in the setup menu + // + for (PortIndex =3D 0; PortIndex < PCH_XHCI_MAX_SSIC_PORT_COUNT; PortInde= x++) { + PchPolicy->UsbConfig.SsicConfig.SsicPort[PortIndex].Enable =3D FALSE; + } + + // + // xDCI configuration + // + PchPolicy->UsbConfig.XdciConfig.Enable =3D FALSE; + + + /******************************** + Io Apic configuration + ********************************/ + PchPolicy->IoApicConfig.IoApicId =3D 0x02; + PchPolicy->IoApicConfig.IoApicEntry24_119 =3D FALSE; + + /******************************** + HPET Configuration + ********************************/ + PchPolicy->HpetConfig.Enable =3D TRUE; + PchPolicy->HpetConfig.Base =3D PCH_HPET_BASE_ADDRESS; + + /******************************** + HD-Audio configuration + ********************************/ + PchPolicy->HdAudioConfig.Enable =3D PCH_HDAUDIO_AUTO; + PchPolicy->HdAudioConfig.DspEnable =3D TRUE; + PchPolicy->HdAudioConfig.HdAudioLinkFrequency =3D PchHdaLinkFreq24MHz; + PchPolicy->HdAudioConfig.IDispLinkFrequency =3D PchHdaLinkFreq96MHz; + PchPolicy->HdAudioConfig.ResetWaitTimer =3D 600; // Must be at lea= st 521us (25 frames) + PchPolicy->HdAudioConfig.DspEndpointDmic =3D PchHdaDmic4chArray; + + /******************************** + Lan configuration + ********************************/ + PchPolicy->LanConfig.Enable =3D TRUE; + /******************************** + SMBus configuration + ********************************/ + PchPolicy->SmbusConfig.Enable =3D TRUE; + PchPolicy->SmbusConfig.SmbusIoBase =3D PcdGet16 (PcdSmbusBaseA= ddress); + ASSERT (sizeof (mSmbusRsvdAddresses) <=3D PCH_MAX_SMBUS_RESERVED_ADDRESS= ); + PchPolicy->SmbusConfig.NumRsvdSmbusAddresses =3D sizeof (mSmbusRsvdAddre= sses); + CopyMem ( + PchPolicy->SmbusConfig.RsvdSmbusAddressTable, + mSmbusRsvdAddresses, + sizeof (mSmbusRsvdAddresses) + ); + + /******************************** + Lockdown configuration + ********************************/ + PchPolicy->LockDownConfig.GlobalSmi =3D TRUE; + // + // PCH BIOS Spec Flash Security Recommendations, + // Intel strongly recommends that BIOS sets the BIOS Interface Lock Down= bit. Enabling this bit + // will mitigate malicious software attempts to replace the system BIOS = option ROM with its own code. + // Here we always enable this as a Policy. + // + PchPolicy->LockDownConfig.BiosInterface =3D TRUE; + PchPolicy->LockDownConfig.RtcLock =3D TRUE; + + /******************************** + Thermal configuration. + ********************************/ + PchPolicy->ThermalConfig.ThermalDeviceEnable = =3D 0; + PchPolicy->ThermalConfig.TsmicLock = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].Pmsy= ncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0Tr= ansmitEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].Pmsy= ncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0Tr= ansmitEnable =3D TRUE; + + /******************************** + MiscPm Configuration + ********************************/ + PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.WolOvrWkSts =3D TRUE; + + PchPolicy->PmConfig.WakeConfig.WolEnableOverride =3D TRUE; + PchPolicy->PmConfig.WakeConfig.LanWakeFromDeepSx =3D TRUE; + + PchPolicy->PmConfig.PchSlpS3MinAssert =3D PchSlpS350m= s; + PchPolicy->PmConfig.PchSlpS4MinAssert =3D PchSlpS44s; + PchPolicy->PmConfig.PchSlpSusMinAssert =3D PchSlpSus4s; + PchPolicy->PmConfig.PchSlpAMinAssert =3D PchSlpA2s; + + PchPolicy->PmConfig.PmcReadDisable =3D TRUE; + PchPolicy->PmConfig.SlpLanLowDc =3D TRUE; + PchPolicy->PmConfig.PciePllSsc =3D 0xFF; + + PchPolicy->PmConfig.SlpS0Enable =3D TRUE; + + PchPolicy->PmConfig.GrPfetDurOnDef =3D PchPmGrPfet= Dur5us; + + /******************************** + DMI related settings + ********************************/ + PchPolicy->DmiConfig.DmiAspm =3D TRUE; + PchPolicy->DmiConfig.DmiStopAndScreamEnable =3D FALSE; + + /******************************** + Serial IRQ Configuration + ********************************/ + PchPolicy->SerialIrqConfig.SirqEnable =3D TRUE; + PchPolicy->SerialIrqConfig.SirqMode =3D PchQuietMode; + PchPolicy->SerialIrqConfig.StartFramePulse =3D PchSfpw4Clk; + + + /******************************** + Interrupt Configuration + ********************************/ + IntConfigTableEntries =3D sizeof (mDevIntConfig) / sizeof (PCH_DEVICE_IN= TERRUPT_CONFIG); + ASSERT (IntConfigTableEntries <=3D PCH_MAX_DEVICE_INTERRUPT_CONFIG); + PchPolicy->PchInterruptConfig.NumOfDevIntConfig =3D IntConfigTableEntrie= s; + CopyMem ( + PchPolicy->PchInterruptConfig.DevIntConfig, + mDevIntConfig, + sizeof (mDevIntConfig) + ); + if (GetPchSeries () =3D=3D PchLp) { + CopyMem ( + &(PchPolicy->PchInterruptConfig.DevIntConfig[IntConfigTableEntries]), + mLpOnlyDevIntConfig, + sizeof (mLpOnlyDevIntConfig) + ); + PchPolicy->PchInterruptConfig.NumOfDevIntConfig +=3D (sizeof (mLpOnlyD= evIntConfig) / sizeof (PCH_DEVICE_INTERRUPT_CONFIG)); + } + + ASSERT ((sizeof (mPxRcConfig) / sizeof (UINT8)) <=3D PCH_MAX_PXRC_CONFIG= ); + CopyMem ( + PchPolicy->PchInterruptConfig.PxRcConfig, + mPxRcConfig, + sizeof (mPxRcConfig) + ); + + PchPolicy->PchInterruptConfig.GpioIrqRoute =3D 14; + PchPolicy->PchInterruptConfig.SciIrqSelect =3D 9; + PchPolicy->PchInterruptConfig.TcoIrqSelect =3D 9; + + + /******************************** + Port 61h emulation + ********************************/ + PchPolicy->Port61hSmmConfig.Enable =3D TRUE; + + + /******************************** + DCI Configuration + ********************************/ + PchPolicy->DciConfig.DciAutoDetect =3D TRUE; + + /******************************** + LPC Configuration + ********************************/ + PchPolicy->LpcConfig.EnhancePort8xhDecoding =3D TRUE; + + /******************************** + Power Optimizer related settings + ********************************/ + PchPolicy->SataConfig.PwrOptEnable =3D TRUE; + PchPolicy->sSataConfig.PwrOptEnable =3D TRUE; + + + PchPolicy->AdrConfig.PchAdrEn =3D FORCE_ENABLE; + PchPolicy->AdrConfig.AdrGpioSel =3D PM_SYNC_GPIO_B; + PchPolicy->AdrConfig.AdrHostPartitionReset =3D FORCE_DISABLE; + PchPolicy->AdrConfig.AdrTimerEn =3D FORCE_ENABLE; + PchPolicy->AdrConfig.AdrTimerVal =3D V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR= _100US; + PchPolicy->AdrConfig.AdrMultiplierVal =3D V_PCH_LBG_MROM_ADRTIMERCTRL_AD= R_MULT_1; + + *PchPolicyPpi =3D PchPolicy; + return EFI_SUCCESS; +} + +/** + PchInstallPolicyPpi installs PchPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] PchPolicyPpi The pointer to PCH Policy PPI instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +PchInstallPolicyPpi ( + IN PCH_POLICY_PPI *PchPolicyPpi + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PchPolicyPpiDesc; + + PchPolicyPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof= (EFI_PEI_PPI_DESCRIPTOR)); + if (PchPolicyPpiDesc =3D=3D NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + PchPolicyPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DES= CRIPTOR_TERMINATE_LIST; + PchPolicyPpiDesc->Guid =3D &gPchPlatformPolicyPpiGuid; + PchPolicyPpiDesc->Ppi =3D PchPolicyPpi; + + // + // Print whole PCH_POLICY_PPI and serial out. + // + if (PchIsDwrFlow() =3D=3D FALSE) { + PchPrintPolicyPpi (PchPolicyPpi); + } + + // + // Install PCH Policy PPI + // + Status =3D PeiServicesInstallPpi (PchPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicy= Lib/PeiPchPolicyLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library= /PeiPchPolicyLib/PeiPchPolicyLib.inf new file mode 100644 index 0000000000..f11ba239b1 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/Pei= PchPolicyLib.inf @@ -0,0 +1,48 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiPchPolicyLib + FILE_GUID =3D BB1AC992-B2CA-4744-84B7-915C185576C5 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PchPolicyLib + + +[LibraryClasses] + DebugLib + IoLib + PcdLib + PeiServicesLib + BaseMemoryLib + MemoryAllocationLib + PchInfoLib + PchPmcLib #SERVER_BIOS + + +[Packages] + PurleyRefreshSiliconPkg/SiPkg.dec + + +[Pcd] + gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress #SERVER_BIOS + gEfiPchTokenSpaceGuid.PcdSmbusBaseAddress #SERVER_BIOS + gEfiPchTokenSpaceGuid.PcdSerialIoUartDebugEnable + gEfiPchTokenSpaceGuid.PcdSerialIoUartNumber + + +[Sources] + PeiPchPolicyLib.c + PeiPchPolicyLibrary.h + PchPrintPolicy.c + Rvp3PolicyLib.c + + +[Ppis] + gPchPlatformPolicyPpiGuid ## PRODUCES # SERVER_BIOS diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicy= Lib/PeiPchPolicyLibrary.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Libra= ry/PeiPchPolicyLib/PeiPchPolicyLibrary.h new file mode 100644 index 0000000000..5a35f0ba47 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/Pei= PchPolicyLibrary.h @@ -0,0 +1,25 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_PCH_POLICY_LIBRARY_H_ +#define _PEI_PCH_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCH_HPET_BASE_ADDRESS 0xFED00000 + + +#endif // _PEI_PCH_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicy= Lib/Rvp3PolicyLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/Pei= PchPolicyLib/Rvp3PolicyLib.c new file mode 100644 index 0000000000..092bda717d --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/Rvp= 3PolicyLib.c @@ -0,0 +1,205 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiPchPolicyLibrary.h" + +/* + Apply RVP3 PCH specific default settings + + @param[in] PchPolicyPpi The pointer to PCH Policy PPI instance +*/ +VOID +EFIAPI +PchRvp3DefaultPolicy ( + IN PCH_POLICY_PPI *PchPolicy + ) +{ + UINTN Index; + + // + // PCIE RP + // + for (Index =3D 0; Index < GetPchMaxPciePortNum (); Index++) { + PchPolicy->PcieConfig.RootPort[Index].ClkReqDetect = =3D TRUE; + PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = =3D TRUE; + } + + PchPolicy->PcieConfig.RootPort[0].ClkReqSupported =3D TRUE; + PchPolicy->PcieConfig.RootPort[0].ClkReqNumber =3D 2; + PchPolicy->HsioPcieConfig.Lane[0].HsioRxSetCtleEnable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[0].HsioRxSetCtle =3D 6; + + PchPolicy->HsioPcieConfig.Lane[1].HsioRxSetCtleEnable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[1].HsioRxSetCtle =3D 6; + + PchPolicy->HsioPcieConfig.Lane[2].HsioRxSetCtleEnable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[2].HsioRxSetCtle =3D 6; + + PchPolicy->HsioPcieConfig.Lane[3].HsioRxSetCtleEnable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[3].HsioRxSetCtle =3D 6; + + PchPolicy->PcieConfig.RootPort[4].ClkReqSupported =3D TRUE; + PchPolicy->PcieConfig.RootPort[4].ClkReqNumber =3D 3; + + PchPolicy->PcieConfig.RootPort[5].ClkReqSupported =3D TRUE; + PchPolicy->PcieConfig.RootPort[5].ClkReqNumber =3D 1; + PchPolicy->HsioPcieConfig.Lane[5].HsioRxSetCtleEnable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[5].HsioRxSetCtle =3D 8; + + PchPolicy->HsioPcieConfig.Lane[7].HsioRxSetCtleEnable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[7].HsioRxSetCtle =3D 8; + + PchPolicy->PcieConfig.RootPort[8].ClkReqSupported =3D TRUE; + PchPolicy->PcieConfig.RootPort[8].ClkReqNumber =3D 5; + PchPolicy->HsioPcieConfig.Lane[8].HsioRxSetCtleEnable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[8].HsioRxSetCtle =3D 8; + + PchPolicy->PcieConfig.RootPort[9].ClkReqSupported =3D TRUE; + PchPolicy->PcieConfig.RootPort[9].ClkReqNumber =3D 4; + PchPolicy->HsioPcieConfig.Lane[9].HsioRxSetCtleEnable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[9].HsioRxSetCtle =3D 8; + + PchPolicy->HsioPcieConfig.Lane[10].HsioRxSetCtleEnable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[10].HsioRxSetCtle =3D 8; + + PchPolicy->HsioPcieConfig.Lane[11].HsioRxSetCtleEnable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[11].HsioRxSetCtle =3D 8; + + // + // SATA + // + PchPolicy->HsioSataConfig.PortLane[0].HsioRxGen3EqBoostMagEnable =3D TRU= E; + PchPolicy->HsioSataConfig.PortLane[0].HsioRxGen3EqBoostMag =3D 4; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen1DownscaleAmpEnable =3D T= RUE; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen1DownscaleAmp =3D 0x2C; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen2DownscaleAmpEnable =3D 0; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen2DownscaleAmp =3D 0; + + // + // USB + // + PchPolicy->UsbConfig.PortUsb20[0].Afe.Petxiset =3D 7; + PchPolicy->UsbConfig.PortUsb20[0].Afe.Txiset =3D 0; + PchPolicy->UsbConfig.PortUsb20[0].Afe.Predeemp =3D 2; + PchPolicy->UsbConfig.PortUsb20[0].Afe.Pehalfbit =3D 1; + + PchPolicy->UsbConfig.PortUsb20[1].Afe.Petxiset =3D 7; + PchPolicy->UsbConfig.PortUsb20[1].Afe.Txiset =3D 0; + PchPolicy->UsbConfig.PortUsb20[1].Afe.Predeemp =3D 2; + PchPolicy->UsbConfig.PortUsb20[1].Afe.Pehalfbit =3D 1; + + PchPolicy->UsbConfig.PortUsb20[2].Afe.Petxiset =3D 7; + PchPolicy->UsbConfig.PortUsb20[2].Afe.Txiset =3D 0; + PchPolicy->UsbConfig.PortUsb20[2].Afe.Predeemp =3D 2; + PchPolicy->UsbConfig.PortUsb20[2].Afe.Pehalfbit =3D 1; + + PchPolicy->UsbConfig.PortUsb20[3].Afe.Petxiset =3D 7; + PchPolicy->UsbConfig.PortUsb20[3].Afe.Txiset =3D 0; + PchPolicy->UsbConfig.PortUsb20[3].Afe.Predeemp =3D 2; + PchPolicy->UsbConfig.PortUsb20[3].Afe.Pehalfbit =3D 1; + + PchPolicy->UsbConfig.PortUsb20[4].Afe.Petxiset =3D 7; + PchPolicy->UsbConfig.PortUsb20[4].Afe.Txiset =3D 0; + PchPolicy->UsbConfig.PortUsb20[4].Afe.Predeemp =3D 2; + PchPolicy->UsbConfig.PortUsb20[4].Afe.Pehalfbit =3D 1; + + PchPolicy->UsbConfig.PortUsb20[5].Afe.Petxiset =3D 7; + PchPolicy->UsbConfig.PortUsb20[5].Afe.Txiset =3D 0; + PchPolicy->UsbConfig.PortUsb20[5].Afe.Predeemp =3D 2; + PchPolicy->UsbConfig.PortUsb20[5].Afe.Pehalfbit =3D 1; + + PchPolicy->UsbConfig.PortUsb20[6].Afe.Petxiset =3D 7; + PchPolicy->UsbConfig.PortUsb20[6].Afe.Txiset =3D 0; + PchPolicy->UsbConfig.PortUsb20[6].Afe.Predeemp =3D 2; + PchPolicy->UsbConfig.PortUsb20[6].Afe.Pehalfbit =3D 1; + + PchPolicy->UsbConfig.PortUsb20[7].Afe.Petxiset =3D 7; + PchPolicy->UsbConfig.PortUsb20[7].Afe.Txiset =3D 0; + PchPolicy->UsbConfig.PortUsb20[7].Afe.Predeemp =3D 2; + PchPolicy->UsbConfig.PortUsb20[7].Afe.Pehalfbit =3D 1; + + PchPolicy->UsbConfig.PortUsb20[8].Afe.Petxiset =3D 7; + PchPolicy->UsbConfig.PortUsb20[8].Afe.Txiset =3D 5; + PchPolicy->UsbConfig.PortUsb20[8].Afe.Predeemp =3D 2; + PchPolicy->UsbConfig.PortUsb20[8].Afe.Pehalfbit =3D 1; + + PchPolicy->UsbConfig.PortUsb20[9].Afe.Petxiset =3D 7; + PchPolicy->UsbConfig.PortUsb20[9].Afe.Txiset =3D 0; + PchPolicy->UsbConfig.PortUsb20[9].Afe.Predeemp =3D 2; + PchPolicy->UsbConfig.PortUsb20[9].Afe.Pehalfbit =3D 1; + + // OC Map for USB2 Ports + PchPolicy->UsbConfig.PortUsb20[ 0].OverCurrentPin =3D PchUsbOverCurrentP= in0; + PchPolicy->UsbConfig.PortUsb20[ 1].OverCurrentPin =3D PchUsbOverCurrentP= in2; + PchPolicy->UsbConfig.PortUsb20[ 2].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb20[ 3].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb20[ 4].OverCurrentPin =3D PchUsbOverCurrentP= in2; + PchPolicy->UsbConfig.PortUsb20[ 5].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb20[ 6].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb20[ 7].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb20[ 8].OverCurrentPin =3D PchUsbOverCurrentP= in1; + PchPolicy->UsbConfig.PortUsb20[ 9].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb20[10].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb20[11].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb20[12].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb20[13].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + + // OC Map for USB3 Ports + PchPolicy->UsbConfig.PortUsb30[0].OverCurrentPin =3D PchUsbOverCurrentP= in0; + PchPolicy->UsbConfig.PortUsb30[1].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb30[2].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb30[3].OverCurrentPin =3D PchUsbOverCurrentP= in1; + PchPolicy->UsbConfig.PortUsb30[4].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + PchPolicy->UsbConfig.PortUsb30[5].OverCurrentPin =3D PchUsbOverCurrentP= inSkip; + + PchPolicy->UsbConfig.SsicConfig.SsicPort[0].Enable =3D TRUE; + PchPolicy->UsbConfig.SsicConfig.SsicPort[1].Enable =3D TRUE; + + // + // IOAPIC + // + PchPolicy->IoApicConfig.BdfValid =3D 1; + PchPolicy->IoApicConfig.BusNumber =3D 0xF0; + PchPolicy->IoApicConfig.DeviceNumber =3D 0x1F; + PchPolicy->IoApicConfig.FunctionNumber =3D 0; + + // + // LAN + // + PchPolicy->LanConfig.K1OffEnable =3D TRUE; + PchPolicy->LanConfig.ClkReqSupported =3D TRUE; + PchPolicy->LanConfig.ClkReqNumber =3D 3; + + // + // LOCK DOWN + // + PchPolicy->LockDownConfig.SpiEiss =3D TRUE; + PchPolicy->LockDownConfig.BiosLock =3D TRUE; + + // + // THERMAL + // + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = =3D FALSE; + + // + // PM CONFIG + // + PchPolicy->PmConfig.PciClockRun =3D TRUE; + + // + // DMI + // + PchPolicy->DmiConfig.PwrOptEnable =3D TRUE; + + + // + // TRACEHUB + // + PchPolicy->PchTraceHubConfig.MemReg0Size =3D 0x100000; // 1MB + PchPolicy->PchTraceHubConfig.MemReg1Size =3D 0x100000; // 1MB + +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSpiFlashC= ommonLib/SmmSpiFlashCommonLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/P= ch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf new file mode 100644 index 0000000000..00f5e92189 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSpiFlashCommonLi= b/SmmSpiFlashCommonLib.inf @@ -0,0 +1,50 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmSpiFlashCommonLib + FILE_GUID =3D 9632D96E-E849-4217-9217-DC500B8AAE47 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_SMM_DRIVER + LIBRARY_CLASS =3D SpiFlashCommonLib|DXE_SMM_DRIVER + CONSTRUCTOR =3D SmmSpiFlashCommonLibConstructor +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + PciLib + IoLib + MemoryAllocationLib + BaseLib + UefiLib + SmmServicesTableLib + BaseMemoryLib + DebugLib + MmPciLib + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Pcd] + gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gEfiPchTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + +[Sources] + SpiFlashCommonSmmLib.c + SpiFlashCommon.c + +[Protocols] + gEfiSmmSpiProtocolGuid ## CONSUMES + +[Depex.X64.DXE_SMM_DRIVER] + gEfiSmmSpiProtocolGuid diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSpiFlashC= ommonLib/SpiFlashCommon.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Libra= ry/SmmSpiFlashCommonLib/SpiFlashCommon.c new file mode 100644 index 0000000000..a079e471bb --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSpiFlashCommonLi= b/SpiFlashCommon.c @@ -0,0 +1,192 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + + +EFI_SPI_PROTOCOL *mSpiProtocol; + +// +// FlashAreaBaseAddress and Size for boottime and runtime usage. +// +UINTN mFlashAreaBaseAddress =3D 0; +UINTN mFlashAreaSize =3D 0; + +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ) +{ + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // This function is implemented specifically for those platforms + // at which the SPI device is memory mapped for read. So this + // function just do a memory copy for Spi Flash Read. + // + CopyMem (Buffer, (VOID *) Address, *NumBytes); + + return EFI_SUCCESS; +} + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the wri= te. + @param[in,out] NumBytes On input, the number of bytes to write. = On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINT32 Length; + UINT32 RemainingBytes; + + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mFlashAreaBaseAddress); + + Offset =3D Address - mFlashAreaBaseAddress; + + ASSERT ((*NumBytes + Offset) <=3D mFlashAreaSize); + + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + + while (RemainingBytes > 0) { + if (RemainingBytes > SECTOR_SIZE_4KB) { + Length =3D SECTOR_SIZE_4KB; + } else { + Length =3D RemainingBytes; + } + Status =3D mSpiProtocol->FlashWrite ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + Length, + Buffer + ); + if (EFI_ERROR (Status)) { + break; + } + RemainingBytes -=3D Length; + Offset +=3D Length; + Buffer +=3D Length; + } + + // + // Actual number of bytes written + // + *NumBytes -=3D RemainingBytes; + + return Status; +} + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block t= o be erased. + This library assume that caller garantee tha= t the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical= block to be erased. + On output, the actual number of bytes erased. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINTN RemainingBytes; + + ASSERT (NumBytes !=3D NULL); + if (NumBytes =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mFlashAreaBaseAddress); + + Offset =3D Address - mFlashAreaBaseAddress; + + ASSERT ((*NumBytes % SECTOR_SIZE_4KB) =3D=3D 0); + ASSERT ((*NumBytes + Offset) <=3D mFlashAreaSize); + + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + + Status =3D mSpiProtocol->FlashErase ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + (UINT32) RemainingBytes + ); + return Status; +} + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSpiFlashC= ommonLib/SpiFlashCommonSmmLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch= /Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c new file mode 100644 index 0000000000..81cb0a16e8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSpiFlashCommonLi= b/SpiFlashCommonSmmLib.c @@ -0,0 +1,53 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +extern EFI_SPI_PROTOCOL *mSpiProtocol; + +extern UINTN mFlashAreaBaseAddress; +extern UINTN mFlashAreaSize; + +/** + The library constructuor. + + The function does the necessary initialization work for this library + instance. + + @param[in] ImageHandle The firmware allocated handle for the UEFI= image. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. + It will ASSERT on error for debug version. + @retval EFI_ERROR Please reference LocateProtocol for error = code details. +**/ +EFI_STATUS +EFIAPI +SmmSpiFlashCommonLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mFlashAreaBaseAddress =3D (UINTN)PcdGet32 (PcdFlashAreaBaseAddress); + mFlashAreaSize =3D (UINTN)PcdGet32 (PcdFlashAreaSize); + + // + // Locate the SMM SPI protocol. + // + Status =3D gSmst->SmmLocateProtocol ( + &gEfiSmmSpiProtocolGuid, + NULL, + (VOID **) &mSpiProtocol + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/LibraryPrivate/BaseP= chResetCommonLib/BasePchResetCommonLib.inf b/Silicon/Intel/PurleyRefreshSil= iconPkg/Pch/LibraryPrivate/BasePchResetCommonLib/BasePchResetCommonLib.inf new file mode 100644 index 0000000000..9fcd02243b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/LibraryPrivate/BasePchReset= CommonLib/BasePchResetCommonLib.inf @@ -0,0 +1,27 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BasePchResetCommonLib + FILE_GUID =3D 1E6151B2-6306-4C9C-B9AC-794A13BEBC3F + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PchResetCommonLib + +[Sources] + PchResetCommon.c + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[LibraryClasses] + IoLib + DebugLib + PchCycleDecodingLib diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/LibraryPrivate/BaseP= chResetCommonLib/PchResetCommon.c b/Silicon/Intel/PurleyRefreshSiliconPkg/P= ch/LibraryPrivate/BasePchResetCommonLib/PchResetCommon.c new file mode 100644 index 0000000000..0c33e9a9d9 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/LibraryPrivate/BasePchReset= CommonLib/PchResetCommon.c @@ -0,0 +1,168 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +EFI_STATUS +EFIAPI +PchResetCallback ( + IN PCH_RESET_TYPE PchResetType + ); + +/** + Initialize an Pch Reset ppi/protocol instance. + + @param[in] PchResetInstance Pointer to PchResetInstance to initialize + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @exception EFI_UNSUPPORTED The PCH is not supported by this module +**/ +EFI_STATUS +PchResetConstructor ( + PCH_RESET_INSTANCE *PchResetInstance + ) +{ + UINTN PmcBaseAddress; + + /// + /// Initialize the Reset protocol instance + /// + PchResetInstance->Signature =3D PCH_RESET_SIGNATURE; + PchResetInstance->Handle =3D NULL; + + /// + /// Sanity check to ensure PMC ACPI/PM BASE initialization has occurred = previously. + /// + PmcBaseAddress =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + PchResetInstance->PchPmcBase =3D PmcBaseAddress; + PchPwrmBaseGet (&(PchResetInstance->PchPwrmBase)); + ASSERT (PchResetInstance->PchPwrmBase !=3D 0); + PchAcpiBaseGet (&(PchResetInstance->PchAcpiBase)); + ASSERT (PchResetInstance->PchAcpiBase !=3D 0); + + + return EFI_SUCCESS; +} + +/** + Execute Pch Reset from the host controller. + @param[in] PchResetInstance Pointer to PchResetInstance to initialize + @param[in] PchResetType Pch Reset Types which includes ColdReset= , WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalRese= tWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +EFI_STATUS +PchReset ( + IN PCH_RESET_INSTANCE *PchResetInstance, + IN PCH_RESET_TYPE PchResetType + ) +{ + UINTN PmcBaseAddress; + UINT16 ABase; + UINT8 OutputData; + UINT32 Data32; + UINT16 Data16; + EFI_STATUS Status; + + PmcBaseAddress =3D PchResetInstance->PchPmcBase; + ABase =3D PchResetInstance->PchAcpiBase; + switch (PchResetType) { + case ColdReset: + IoWrite8 ((UINTN) R_PCH_RST_CNT, (UINT8) V_PCH_RST_CNT_HARDSTARTSTAT= E); + OutputData =3D V_PCH_RST_CNT_FULLRESET; + break; + + case WarmReset: + IoWrite8 ((UINTN) R_PCH_RST_CNT, (UINT8) V_PCH_RST_CNT_SOFTSTARTSTAT= E); + OutputData =3D V_PCH_RST_CNT_HARDRESET; + break; + + case ShutdownReset: + /// + /// Firstly, ACPI decode must be enabled + /// + MmioOr8 ( + PmcBaseAddress + R_PCH_PMC_ACPI_CNT, + (UINT8) (B_PCH_PMC_ACPI_CNT_ACPI_EN) + ); + + /// + /// Then, GPE0_EN should be disabled to avoid any GPI waking up the = system from S5 + /// + IoWrite32 ((UINTN) (ABase + R_PCH_ACPI_GPE0_EN_127_96), 0); + + /// + /// Secondly, PwrSts register must be cleared + /// + /// Write a "1" to bit[8] of power button status register at + /// (PM_BASE + PM1_STS_OFFSET) to clear this bit + /// + Data16 =3D B_PCH_SMI_STS_PM1_STS_REG; + IoWrite16 ((UINTN) (ABase + R_PCH_SMI_STS), Data16); + + /// + /// Finally, transform system into S5 sleep state + /// + Data32 =3D IoRead32 ((UINTN) (ABase + R_PCH_ACPI_PM1_CNT)); + + Data32 =3D (UINT32) ((Data32 &~(B_PCH_ACPI_PM1_CNT_SLP_TYP + B_PCH_= ACPI_PM1_CNT_SLP_EN)) | V_PCH_ACPI_PM1_CNT_S5); + + IoWrite32 ((UINTN) (ABase + R_PCH_ACPI_PM1_CNT), Data32); + + Data32 =3D Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN; + + IoWrite32 ((UINTN) (ABase + R_PCH_ACPI_PM1_CNT), Data32); + return EFI_SUCCESS; + + case PowerCycleReset: + case GlobalReset: + case GlobalResetWithEc: + /// + /// PCH BIOS Spec Section 4.6 GPIO Reset Requirement + /// + + if ((PchResetType =3D=3D GlobalReset) || (PchResetType =3D=3D Global= ResetWithEc)) { + MmioOr32 ( + PmcBaseAddress + R_PCH_PMC_ETR3, + (UINT32) (B_PCH_PMC_ETR3_CF9GR) + ); + } + OutputData =3D V_PCH_RST_CNT_FULLRESET; + break; + + default: + return EFI_INVALID_PARAMETER; + } + + DEBUG ((DEBUG_ERROR, "Resetting the platform (%02x)...\n", OutputData)); + + Status =3D PchResetCallback (PchResetType); + + if ((Status =3D=3D EFI_SUCCESS) || (Status =3D=3D EFI_NOT_FOUND)) { + IoWrite8 ((UINTN) R_PCH_RST_CNT, OutputData); + /// + /// Waiting for system reset + /// + CpuDeadLoop (); + } + + return Status; +} --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726534; bh=PZLeJFxATTs/z06N64PHg3xQ0ytbAZSUdUOXj7NCNYQ=; h=Cc:Date:From:Reply-To:Subject:To; b=ZkEd+1KX4FjXPwgeQJmiaFv7nRWtlmmTE6ap3dY6CuHajdKQDfMhVw9PA7/ZJpugVEt QSpkAxk956dhPVAAu5ynpoi/SXHBCHJgwDVrrdYwk/cazHXMisxtRsMS8beOFiK8eUilr jOfsKtzGBK8fdDdUjMYVW3HkQMIHtDAzpmo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../Pch/AcpiTables/Dsdt/GpioDefine.asl | 784 +++++++++++++ .../Pch/AcpiTables/Dsdt/GpioLib.asl | 1024 +++++++++++++++++ .../Pch/AcpiTables/Dsdt/IrqLink.asl | 607 ++++++++++ .../Pch/AcpiTables/Dsdt/Pch.asl | 833 ++++++++++++++ .../Pch/AcpiTables/Dsdt/PchAcpiTables.inf | 34 + .../Pch/AcpiTables/Dsdt/PchHda.asl | 306 +++++ .../Pch/AcpiTables/Dsdt/PchHeci.asl | 22 + .../Pch/AcpiTables/Dsdt/PchIsh.asl | 21 + .../Pch/AcpiTables/Dsdt/PchNvs.asl | 270 +++++ .../Pch/AcpiTables/Dsdt/PchPcie.asl | 202 ++++ .../Pch/AcpiTables/Dsdt/PchRstPcieStorage.asl | 216 ++++ .../Pch/AcpiTables/Dsdt/PchSata.asl | 221 ++++ .../Pch/AcpiTables/Dsdt/PchScs.asl | 8 + .../Pch/AcpiTables/Dsdt/PchSerialIo.asl | 7 + .../Pch/AcpiTables/Dsdt/PchXdci.asl | 8 + .../Pch/AcpiTables/Dsdt/PchXhci.asl | 557 +++++++++ .../Pch/AcpiTables/Dsdt/RP01_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP02_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP03_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP04_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP05_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP06_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP07_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP08_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP09_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP10_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP11_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP12_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP13_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP14_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP15_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP16_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP17_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP18_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP19_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/RP20_ADR.asl | 14 + .../Pch/AcpiTables/Dsdt/TraceHubDebug.asl | 142 +++ .../Pch/AcpiTables/Dsdt/usbsbd.asl | 63 + 38 files changed, 5605 insertions(+) create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/GpioDefine.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/GpioLib.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/IrqLink.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/Pch.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchAcpiTables.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchHda.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchHeci.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchIsh.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchNvs.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchPcie.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchRstPcieStorage.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchSata.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchScs.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchSerialIo.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchXdci.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchXhci.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP01_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP02_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP03_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP04_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP05_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP06_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP07_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP08_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP09_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP10_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP11_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP12_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP13_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP14_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP15_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP16_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP17_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP18_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP19_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/RP20_ADR.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/TraceHubDebug.asl create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/usbsbd.asl diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/Gpio= Define.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/Gpio= Define.asl new file mode 100644 index 0000000000..0116b9ac39 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/GpioDefine.= asl @@ -0,0 +1,784 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Definition for GPIO groups and pads +// +#ifndef GPIO_DEFINE_ASL +#define GPIO_DEFINE_ASL + +#include "GpioPinsSklLp.h" +#include "GpioPinsSklH.h" +#include "Register/PchRegsGpio.h" + +// +// SKL-PCH GPIO Community address +// +#define PCH_GPIO_COM0 0x00af0000 // PID_GPIOCOM0 =3D 0xAF +#define PCH_GPIO_COM1 0x00ae0000 // PID_GPIOCOM1 =3D 0xAE +#define PCH_GPIO_COM2 0x00ad0000 // PID_GPIOCOM2 =3D 0xAD +#define PCH_GPIO_COM3 0x00ac0000 // PID_GPIOCOM3 =3D 0xAC + +// +// SKL-PCH-LP GPIO pin list for driver usage +// +#define GPIO_SKL_LP_DRIVER_GPP_A_00 0 +#define GPIO_SKL_LP_DRIVER_GPP_A_01 1 +#define GPIO_SKL_LP_DRIVER_GPP_A_02 2 +#define GPIO_SKL_LP_DRIVER_GPP_A_03 3 +#define GPIO_SKL_LP_DRIVER_GPP_A_04 4 +#define GPIO_SKL_LP_DRIVER_GPP_A_05 5 +#define GPIO_SKL_LP_DRIVER_GPP_A_06 6 +#define GPIO_SKL_LP_DRIVER_GPP_A_07 7 +#define GPIO_SKL_LP_DRIVER_GPP_A_08 8 +#define GPIO_SKL_LP_DRIVER_GPP_A_09 9 +#define GPIO_SKL_LP_DRIVER_GPP_A_10 10 +#define GPIO_SKL_LP_DRIVER_GPP_A_11 11 +#define GPIO_SKL_LP_DRIVER_GPP_A_12 12 +#define GPIO_SKL_LP_DRIVER_GPP_A_13 13 +#define GPIO_SKL_LP_DRIVER_GPP_A_14 14 +#define GPIO_SKL_LP_DRIVER_GPP_A_15 15 +#define GPIO_SKL_LP_DRIVER_GPP_A_16 16 +#define GPIO_SKL_LP_DRIVER_GPP_A_17 17 +#define GPIO_SKL_LP_DRIVER_GPP_A_18 18 +#define GPIO_SKL_LP_DRIVER_GPP_A_19 19 +#define GPIO_SKL_LP_DRIVER_GPP_A_20 20 +#define GPIO_SKL_LP_DRIVER_GPP_A_21 21 +#define GPIO_SKL_LP_DRIVER_GPP_A_22 22 +#define GPIO_SKL_LP_DRIVER_GPP_A_23 23 + +#define GPIO_SKL_LP_DRIVER_GPP_B_00 24 +#define GPIO_SKL_LP_DRIVER_GPP_B_01 25 +#define GPIO_SKL_LP_DRIVER_GPP_B_02 26 +#define GPIO_SKL_LP_DRIVER_GPP_B_03 27 +#define GPIO_SKL_LP_DRIVER_GPP_B_04 28 +#define GPIO_SKL_LP_DRIVER_GPP_B_05 29 +#define GPIO_SKL_LP_DRIVER_GPP_B_06 30 +#define GPIO_SKL_LP_DRIVER_GPP_B_07 31 +#define GPIO_SKL_LP_DRIVER_GPP_B_08 32 +#define GPIO_SKL_LP_DRIVER_GPP_B_09 33 +#define GPIO_SKL_LP_DRIVER_GPP_B_10 34 +#define GPIO_SKL_LP_DRIVER_GPP_B_11 35 +#define GPIO_SKL_LP_DRIVER_GPP_B_12 36 +#define GPIO_SKL_LP_DRIVER_GPP_B_13 37 +#define GPIO_SKL_LP_DRIVER_GPP_B_14 38 +#define GPIO_SKL_LP_DRIVER_GPP_B_15 39 +#define GPIO_SKL_LP_DRIVER_GPP_B_16 40 +#define GPIO_SKL_LP_DRIVER_GPP_B_17 41 +#define GPIO_SKL_LP_DRIVER_GPP_B_18 42 +#define GPIO_SKL_LP_DRIVER_GPP_B_19 43 +#define GPIO_SKL_LP_DRIVER_GPP_B_20 44 +#define GPIO_SKL_LP_DRIVER_GPP_B_21 45 +#define GPIO_SKL_LP_DRIVER_GPP_B_22 46 +#define GPIO_SKL_LP_DRIVER_GPP_B_23 47 + +#define GPIO_SKL_LP_DRIVER_GPP_C_00 48 +#define GPIO_SKL_LP_DRIVER_GPP_C_01 49 +#define GPIO_SKL_LP_DRIVER_GPP_C_02 50 +#define GPIO_SKL_LP_DRIVER_GPP_C_03 51 +#define GPIO_SKL_LP_DRIVER_GPP_C_04 52 +#define GPIO_SKL_LP_DRIVER_GPP_C_05 53 +#define GPIO_SKL_LP_DRIVER_GPP_C_06 54 +#define GPIO_SKL_LP_DRIVER_GPP_C_07 55 +#define GPIO_SKL_LP_DRIVER_GPP_C_08 56 +#define GPIO_SKL_LP_DRIVER_GPP_C_09 57 +#define GPIO_SKL_LP_DRIVER_GPP_C_10 58 +#define GPIO_SKL_LP_DRIVER_GPP_C_11 59 +#define GPIO_SKL_LP_DRIVER_GPP_C_12 60 +#define GPIO_SKL_LP_DRIVER_GPP_C_13 61 +#define GPIO_SKL_LP_DRIVER_GPP_C_14 62 +#define GPIO_SKL_LP_DRIVER_GPP_C_15 63 +#define GPIO_SKL_LP_DRIVER_GPP_C_16 64 +#define GPIO_SKL_LP_DRIVER_GPP_C_17 65 +#define GPIO_SKL_LP_DRIVER_GPP_C_18 66 +#define GPIO_SKL_LP_DRIVER_GPP_C_19 67 +#define GPIO_SKL_LP_DRIVER_GPP_C_20 68 +#define GPIO_SKL_LP_DRIVER_GPP_C_21 69 +#define GPIO_SKL_LP_DRIVER_GPP_C_22 70 +#define GPIO_SKL_LP_DRIVER_GPP_C_23 71 + +#define GPIO_SKL_LP_DRIVER_GPP_D_00 72 +#define GPIO_SKL_LP_DRIVER_GPP_D_01 73 +#define GPIO_SKL_LP_DRIVER_GPP_D_02 74 +#define GPIO_SKL_LP_DRIVER_GPP_D_03 75 +#define GPIO_SKL_LP_DRIVER_GPP_D_04 76 +#define GPIO_SKL_LP_DRIVER_GPP_D_05 77 +#define GPIO_SKL_LP_DRIVER_GPP_D_06 78 +#define GPIO_SKL_LP_DRIVER_GPP_D_07 79 +#define GPIO_SKL_LP_DRIVER_GPP_D_08 80 +#define GPIO_SKL_LP_DRIVER_GPP_D_09 81 +#define GPIO_SKL_LP_DRIVER_GPP_D_10 82 +#define GPIO_SKL_LP_DRIVER_GPP_D_11 83 +#define GPIO_SKL_LP_DRIVER_GPP_D_12 84 +#define GPIO_SKL_LP_DRIVER_GPP_D_13 85 +#define GPIO_SKL_LP_DRIVER_GPP_D_14 86 +#define GPIO_SKL_LP_DRIVER_GPP_D_15 87 +#define GPIO_SKL_LP_DRIVER_GPP_D_16 88 +#define GPIO_SKL_LP_DRIVER_GPP_D_17 89 +#define GPIO_SKL_LP_DRIVER_GPP_D_18 90 +#define GPIO_SKL_LP_DRIVER_GPP_D_19 91 +#define GPIO_SKL_LP_DRIVER_GPP_D_20 92 +#define GPIO_SKL_LP_DRIVER_GPP_D_21 93 +#define GPIO_SKL_LP_DRIVER_GPP_D_22 94 +#define GPIO_SKL_LP_DRIVER_GPP_D_23 95 + +#define GPIO_SKL_LP_DRIVER_GPP_E_00 96 +#define GPIO_SKL_LP_DRIVER_GPP_E_01 97 +#define GPIO_SKL_LP_DRIVER_GPP_E_02 98 +#define GPIO_SKL_LP_DRIVER_GPP_E_03 99 +#define GPIO_SKL_LP_DRIVER_GPP_E_04 100 +#define GPIO_SKL_LP_DRIVER_GPP_E_05 101 +#define GPIO_SKL_LP_DRIVER_GPP_E_06 102 +#define GPIO_SKL_LP_DRIVER_GPP_E_07 103 +#define GPIO_SKL_LP_DRIVER_GPP_E_08 104 +#define GPIO_SKL_LP_DRIVER_GPP_E_09 105 +#define GPIO_SKL_LP_DRIVER_GPP_E_10 106 +#define GPIO_SKL_LP_DRIVER_GPP_E_11 107 +#define GPIO_SKL_LP_DRIVER_GPP_E_12 108 +#define GPIO_SKL_LP_DRIVER_GPP_E_13 109 +#define GPIO_SKL_LP_DRIVER_GPP_E_14 110 +#define GPIO_SKL_LP_DRIVER_GPP_E_15 111 +#define GPIO_SKL_LP_DRIVER_GPP_E_16 112 +#define GPIO_SKL_LP_DRIVER_GPP_E_17 113 +#define GPIO_SKL_LP_DRIVER_GPP_E_18 114 +#define GPIO_SKL_LP_DRIVER_GPP_E_19 115 +#define GPIO_SKL_LP_DRIVER_GPP_E_20 116 +#define GPIO_SKL_LP_DRIVER_GPP_E_21 117 +#define GPIO_SKL_LP_DRIVER_GPP_E_22 118 +#define GPIO_SKL_LP_DRIVER_GPP_E_23 119 + +#define GPIO_SKL_LP_DRIVER_GPP_F_00 120 +#define GPIO_SKL_LP_DRIVER_GPP_F_01 121 +#define GPIO_SKL_LP_DRIVER_GPP_F_02 122 +#define GPIO_SKL_LP_DRIVER_GPP_F_03 123 +#define GPIO_SKL_LP_DRIVER_GPP_F_04 124 +#define GPIO_SKL_LP_DRIVER_GPP_F_05 125 +#define GPIO_SKL_LP_DRIVER_GPP_F_06 126 +#define GPIO_SKL_LP_DRIVER_GPP_F_07 127 +#define GPIO_SKL_LP_DRIVER_GPP_F_08 128 +#define GPIO_SKL_LP_DRIVER_GPP_F_09 129 +#define GPIO_SKL_LP_DRIVER_GPP_F_10 130 +#define GPIO_SKL_LP_DRIVER_GPP_F_11 131 +#define GPIO_SKL_LP_DRIVER_GPP_F_12 132 +#define GPIO_SKL_LP_DRIVER_GPP_F_13 133 +#define GPIO_SKL_LP_DRIVER_GPP_F_14 134 +#define GPIO_SKL_LP_DRIVER_GPP_F_15 135 +#define GPIO_SKL_LP_DRIVER_GPP_F_16 136 +#define GPIO_SKL_LP_DRIVER_GPP_F_17 137 +#define GPIO_SKL_LP_DRIVER_GPP_F_18 138 +#define GPIO_SKL_LP_DRIVER_GPP_F_19 139 +#define GPIO_SKL_LP_DRIVER_GPP_F_20 140 +#define GPIO_SKL_LP_DRIVER_GPP_F_21 141 +#define GPIO_SKL_LP_DRIVER_GPP_F_22 142 +#define GPIO_SKL_LP_DRIVER_GPP_F_23 143 + +#define GPIO_SKL_LP_DRIVER_GPP_G_00 144 +#define GPIO_SKL_LP_DRIVER_GPP_G_01 145 +#define GPIO_SKL_LP_DRIVER_GPP_G_02 146 +#define GPIO_SKL_LP_DRIVER_GPP_G_03 147 +#define GPIO_SKL_LP_DRIVER_GPP_G_04 148 +#define GPIO_SKL_LP_DRIVER_GPP_G_05 149 +#define GPIO_SKL_LP_DRIVER_GPP_G_06 150 +#define GPIO_SKL_LP_DRIVER_GPP_G_07 151 + +// +// SPT H GPIO pin list for driver usage +// +#define GPIO_SKL_H_DRIVER_GPP_A_00 0 +#define GPIO_SKL_H_DRIVER_GPP_A_01 1 +#define GPIO_SKL_H_DRIVER_GPP_A_02 2 +#define GPIO_SKL_H_DRIVER_GPP_A_03 3 +#define GPIO_SKL_H_DRIVER_GPP_A_04 4 +#define GPIO_SKL_H_DRIVER_GPP_A_05 5 +#define GPIO_SKL_H_DRIVER_GPP_A_06 6 +#define GPIO_SKL_H_DRIVER_GPP_A_07 7 +#define GPIO_SKL_H_DRIVER_GPP_A_08 8 +#define GPIO_SKL_H_DRIVER_GPP_A_09 9 +#define GPIO_SKL_H_DRIVER_GPP_A_10 10 +#define GPIO_SKL_H_DRIVER_GPP_A_11 11 +#define GPIO_SKL_H_DRIVER_GPP_A_12 12 +#define GPIO_SKL_H_DRIVER_GPP_A_13 13 +#define GPIO_SKL_H_DRIVER_GPP_A_14 14 +#define GPIO_SKL_H_DRIVER_GPP_A_15 15 +#define GPIO_SKL_H_DRIVER_GPP_A_16 16 +#define GPIO_SKL_H_DRIVER_GPP_A_17 17 +#define GPIO_SKL_H_DRIVER_GPP_A_18 18 +#define GPIO_SKL_H_DRIVER_GPP_A_19 19 +#define GPIO_SKL_H_DRIVER_GPP_A_20 20 +#define GPIO_SKL_H_DRIVER_GPP_A_21 21 +#define GPIO_SKL_H_DRIVER_GPP_A_22 22 +#define GPIO_SKL_H_DRIVER_GPP_A_23 23 + +#define GPIO_SKL_H_DRIVER_GPP_B_00 24 +#define GPIO_SKL_H_DRIVER_GPP_B_01 25 +#define GPIO_SKL_H_DRIVER_GPP_B_02 26 +#define GPIO_SKL_H_DRIVER_GPP_B_03 27 +#define GPIO_SKL_H_DRIVER_GPP_B_04 28 +#define GPIO_SKL_H_DRIVER_GPP_B_05 29 +#define GPIO_SKL_H_DRIVER_GPP_B_06 30 +#define GPIO_SKL_H_DRIVER_GPP_B_07 31 +#define GPIO_SKL_H_DRIVER_GPP_B_08 32 +#define GPIO_SKL_H_DRIVER_GPP_B_09 33 +#define GPIO_SKL_H_DRIVER_GPP_B_10 34 +#define GPIO_SKL_H_DRIVER_GPP_B_11 35 +#define GPIO_SKL_H_DRIVER_GPP_B_12 36 +#define GPIO_SKL_H_DRIVER_GPP_B_13 37 +#define GPIO_SKL_H_DRIVER_GPP_B_14 38 +#define GPIO_SKL_H_DRIVER_GPP_B_15 39 +#define GPIO_SKL_H_DRIVER_GPP_B_16 40 +#define GPIO_SKL_H_DRIVER_GPP_B_17 41 +#define GPIO_SKL_H_DRIVER_GPP_B_18 42 +#define GPIO_SKL_H_DRIVER_GPP_B_19 43 +#define GPIO_SKL_H_DRIVER_GPP_B_20 44 +#define GPIO_SKL_H_DRIVER_GPP_B_21 45 +#define GPIO_SKL_H_DRIVER_GPP_B_22 46 +#define GPIO_SKL_H_DRIVER_GPP_B_23 47 + +#define GPIO_SKL_H_DRIVER_GPP_C_00 48 +#define GPIO_SKL_H_DRIVER_GPP_C_01 49 +#define GPIO_SKL_H_DRIVER_GPP_C_02 50 +#define GPIO_SKL_H_DRIVER_GPP_C_03 51 +#define GPIO_SKL_H_DRIVER_GPP_C_04 52 +#define GPIO_SKL_H_DRIVER_GPP_C_05 53 +#define GPIO_SKL_H_DRIVER_GPP_C_06 54 +#define GPIO_SKL_H_DRIVER_GPP_C_07 55 +#define GPIO_SKL_H_DRIVER_GPP_C_08 56 +#define GPIO_SKL_H_DRIVER_GPP_C_09 57 +#define GPIO_SKL_H_DRIVER_GPP_C_10 58 +#define GPIO_SKL_H_DRIVER_GPP_C_11 59 +#define GPIO_SKL_H_DRIVER_GPP_C_12 60 +#define GPIO_SKL_H_DRIVER_GPP_C_13 61 +#define GPIO_SKL_H_DRIVER_GPP_C_14 62 +#define GPIO_SKL_H_DRIVER_GPP_C_15 63 +#define GPIO_SKL_H_DRIVER_GPP_C_16 64 +#define GPIO_SKL_H_DRIVER_GPP_C_17 65 +#define GPIO_SKL_H_DRIVER_GPP_C_18 66 +#define GPIO_SKL_H_DRIVER_GPP_C_19 67 +#define GPIO_SKL_H_DRIVER_GPP_C_20 68 +#define GPIO_SKL_H_DRIVER_GPP_C_21 69 +#define GPIO_SKL_H_DRIVER_GPP_C_22 70 +#define GPIO_SKL_H_DRIVER_GPP_C_23 71 + +#define GPIO_SKL_H_DRIVER_GPP_D_00 72 +#define GPIO_SKL_H_DRIVER_GPP_D_01 73 +#define GPIO_SKL_H_DRIVER_GPP_D_02 74 +#define GPIO_SKL_H_DRIVER_GPP_D_03 75 +#define GPIO_SKL_H_DRIVER_GPP_D_04 76 +#define GPIO_SKL_H_DRIVER_GPP_D_05 77 +#define GPIO_SKL_H_DRIVER_GPP_D_06 78 +#define GPIO_SKL_H_DRIVER_GPP_D_07 79 +#define GPIO_SKL_H_DRIVER_GPP_D_08 80 +#define GPIO_SKL_H_DRIVER_GPP_D_09 81 +#define GPIO_SKL_H_DRIVER_GPP_D_10 82 +#define GPIO_SKL_H_DRIVER_GPP_D_11 83 +#define GPIO_SKL_H_DRIVER_GPP_D_12 84 +#define GPIO_SKL_H_DRIVER_GPP_D_13 85 +#define GPIO_SKL_H_DRIVER_GPP_D_14 86 +#define GPIO_SKL_H_DRIVER_GPP_D_15 87 +#define GPIO_SKL_H_DRIVER_GPP_D_16 88 +#define GPIO_SKL_H_DRIVER_GPP_D_17 89 +#define GPIO_SKL_H_DRIVER_GPP_D_18 90 +#define GPIO_SKL_H_DRIVER_GPP_D_19 91 +#define GPIO_SKL_H_DRIVER_GPP_D_20 92 +#define GPIO_SKL_H_DRIVER_GPP_D_21 93 +#define GPIO_SKL_H_DRIVER_GPP_D_22 94 +#define GPIO_SKL_H_DRIVER_GPP_D_23 95 + +#define GPIO_SKL_H_DRIVER_GPP_E_00 96 +#define GPIO_SKL_H_DRIVER_GPP_E_01 97 +#define GPIO_SKL_H_DRIVER_GPP_E_02 98 +#define GPIO_SKL_H_DRIVER_GPP_E_03 99 +#define GPIO_SKL_H_DRIVER_GPP_E_04 100 +#define GPIO_SKL_H_DRIVER_GPP_E_05 101 +#define GPIO_SKL_H_DRIVER_GPP_E_06 102 +#define GPIO_SKL_H_DRIVER_GPP_E_07 103 +#define GPIO_SKL_H_DRIVER_GPP_E_08 104 +#define GPIO_SKL_H_DRIVER_GPP_E_09 105 +#define GPIO_SKL_H_DRIVER_GPP_E_10 106 +#define GPIO_SKL_H_DRIVER_GPP_E_11 107 +#define GPIO_SKL_H_DRIVER_GPP_E_12 108 +#define GPIO_SKL_H_DRIVER_GPP_E_13 109 + +#define GPIO_SKL_H_DRIVER_GPP_F_00 120 +#define GPIO_SKL_H_DRIVER_GPP_F_01 121 +#define GPIO_SKL_H_DRIVER_GPP_F_02 122 +#define GPIO_SKL_H_DRIVER_GPP_F_03 123 +#define GPIO_SKL_H_DRIVER_GPP_F_04 124 +#define GPIO_SKL_H_DRIVER_GPP_F_05 125 +#define GPIO_SKL_H_DRIVER_GPP_F_06 126 +#define GPIO_SKL_H_DRIVER_GPP_F_07 127 +#define GPIO_SKL_H_DRIVER_GPP_F_08 128 +#define GPIO_SKL_H_DRIVER_GPP_F_09 129 +#define GPIO_SKL_H_DRIVER_GPP_F_10 130 +#define GPIO_SKL_H_DRIVER_GPP_F_11 131 +#define GPIO_SKL_H_DRIVER_GPP_F_12 132 +#define GPIO_SKL_H_DRIVER_GPP_F_13 133 +#define GPIO_SKL_H_DRIVER_GPP_F_14 134 +#define GPIO_SKL_H_DRIVER_GPP_F_15 135 +#define GPIO_SKL_H_DRIVER_GPP_F_16 136 +#define GPIO_SKL_H_DRIVER_GPP_F_17 137 +#define GPIO_SKL_H_DRIVER_GPP_F_18 138 +#define GPIO_SKL_H_DRIVER_GPP_F_19 139 +#define GPIO_SKL_H_DRIVER_GPP_F_20 140 +#define GPIO_SKL_H_DRIVER_GPP_F_21 141 +#define GPIO_SKL_H_DRIVER_GPP_F_22 142 +#define GPIO_SKL_H_DRIVER_GPP_F_23 143 + +#define GPIO_SKL_H_DRIVER_GPP_G_00 144 +#define GPIO_SKL_H_DRIVER_GPP_G_01 145 +#define GPIO_SKL_H_DRIVER_GPP_G_02 146 +#define GPIO_SKL_H_DRIVER_GPP_G_03 147 +#define GPIO_SKL_H_DRIVER_GPP_G_04 148 +#define GPIO_SKL_H_DRIVER_GPP_G_05 149 +#define GPIO_SKL_H_DRIVER_GPP_G_06 150 +#define GPIO_SKL_H_DRIVER_GPP_G_07 151 +#define GPIO_SKL_H_DRIVER_GPP_G_08 152 +#define GPIO_SKL_H_DRIVER_GPP_G_09 153 +#define GPIO_SKL_H_DRIVER_GPP_G_10 154 +#define GPIO_SKL_H_DRIVER_GPP_G_11 155 +#define GPIO_SKL_H_DRIVER_GPP_G_12 156 +#define GPIO_SKL_H_DRIVER_GPP_G_13 157 +#define GPIO_SKL_H_DRIVER_GPP_G_14 158 +#define GPIO_SKL_H_DRIVER_GPP_G_15 159 +#define GPIO_SKL_H_DRIVER_GPP_G_16 160 +#define GPIO_SKL_H_DRIVER_GPP_G_17 161 +#define GPIO_SKL_H_DRIVER_GPP_G_18 162 +#define GPIO_SKL_H_DRIVER_GPP_G_19 163 +#define GPIO_SKL_H_DRIVER_GPP_G_20 164 +#define GPIO_SKL_H_DRIVER_GPP_G_21 165 +#define GPIO_SKL_H_DRIVER_GPP_G_22 166 +#define GPIO_SKL_H_DRIVER_GPP_G_23 167 + +#define GPIO_SKL_H_DRIVER_GPP_H_00 168 +#define GPIO_SKL_H_DRIVER_GPP_H_01 169 +#define GPIO_SKL_H_DRIVER_GPP_H_02 170 +#define GPIO_SKL_H_DRIVER_GPP_H_03 171 +#define GPIO_SKL_H_DRIVER_GPP_H_04 172 +#define GPIO_SKL_H_DRIVER_GPP_H_05 173 +#define GPIO_SKL_H_DRIVER_GPP_H_06 174 +#define GPIO_SKL_H_DRIVER_GPP_H_07 175 +#define GPIO_SKL_H_DRIVER_GPP_H_08 176 +#define GPIO_SKL_H_DRIVER_GPP_H_09 177 +#define GPIO_SKL_H_DRIVER_GPP_H_10 178 +#define GPIO_SKL_H_DRIVER_GPP_H_11 179 +#define GPIO_SKL_H_DRIVER_GPP_H_12 180 +#define GPIO_SKL_H_DRIVER_GPP_H_13 181 +#define GPIO_SKL_H_DRIVER_GPP_H_14 182 +#define GPIO_SKL_H_DRIVER_GPP_H_15 183 +#define GPIO_SKL_H_DRIVER_GPP_H_16 184 +#define GPIO_SKL_H_DRIVER_GPP_H_17 185 +#define GPIO_SKL_H_DRIVER_GPP_H_18 186 +#define GPIO_SKL_H_DRIVER_GPP_H_19 187 +#define GPIO_SKL_H_DRIVER_GPP_H_20 188 +#define GPIO_SKL_H_DRIVER_GPP_H_21 189 +#define GPIO_SKL_H_DRIVER_GPP_H_22 190 +#define GPIO_SKL_H_DRIVER_GPP_H_23 191 + +#define PCH_I_GPIO_DRIVER_GPP_I_00 192 +#define PCH_I_GPIO_DRIVER_GPP_I_01 193 +#define PCH_I_GPIO_DRIVER_GPP_I_02 194 +#define PCH_I_GPIO_DRIVER_GPP_I_03 195 +#define PCH_I_GPIO_DRIVER_GPP_I_04 196 +#define PCH_I_GPIO_DRIVER_GPP_I_05 197 +#define PCH_I_GPIO_DRIVER_GPP_I_06 198 +#define PCH_I_GPIO_DRIVER_GPP_I_07 199 +#define PCH_I_GPIO_DRIVER_GPP_I_08 200 +#define PCH_I_GPIO_DRIVER_GPP_I_09 201 +#define PCH_I_GPIO_DRIVER_GPP_I_10 202 + +// +// SPT GPIO IOxAPIC interrupts +// +// SPT-LP: +#define GPIO_SKL_LP_IOAPIC_GPP_A_00 0x18 +#define GPIO_SKL_LP_IOAPIC_GPP_A_01 0x19 +#define GPIO_SKL_LP_IOAPIC_GPP_A_02 0x1a +#define GPIO_SKL_LP_IOAPIC_GPP_A_03 0x1b +#define GPIO_SKL_LP_IOAPIC_GPP_A_04 0x1c +#define GPIO_SKL_LP_IOAPIC_GPP_A_05 0x1d +#define GPIO_SKL_LP_IOAPIC_GPP_A_06 0x1e +#define GPIO_SKL_LP_IOAPIC_GPP_A_07 0x1f +#define GPIO_SKL_LP_IOAPIC_GPP_A_08 0x20 +#define GPIO_SKL_LP_IOAPIC_GPP_A_09 0x21 +#define GPIO_SKL_LP_IOAPIC_GPP_A_10 0x22 +#define GPIO_SKL_LP_IOAPIC_GPP_A_11 0x23 +#define GPIO_SKL_LP_IOAPIC_GPP_A_12 0x24 +#define GPIO_SKL_LP_IOAPIC_GPP_A_13 0x25 +#define GPIO_SKL_LP_IOAPIC_GPP_A_14 0x26 +#define GPIO_SKL_LP_IOAPIC_GPP_A_15 0x27 +#define GPIO_SKL_LP_IOAPIC_GPP_A_16 0x28 +#define GPIO_SKL_LP_IOAPIC_GPP_A_17 0x29 +#define GPIO_SKL_LP_IOAPIC_GPP_A_18 0x2a +#define GPIO_SKL_LP_IOAPIC_GPP_A_19 0x2b +#define GPIO_SKL_LP_IOAPIC_GPP_A_20 0x2c +#define GPIO_SKL_LP_IOAPIC_GPP_A_21 0x2d +#define GPIO_SKL_LP_IOAPIC_GPP_A_22 0x2e +#define GPIO_SKL_LP_IOAPIC_GPP_A_23 0x2f + +#define GPIO_SKL_LP_IOAPIC_GPP_B_00 0x30 +#define GPIO_SKL_LP_IOAPIC_GPP_B_01 0x31 +#define GPIO_SKL_LP_IOAPIC_GPP_B_02 0x32 +#define GPIO_SKL_LP_IOAPIC_GPP_B_03 0x33 +#define GPIO_SKL_LP_IOAPIC_GPP_B_04 0x34 +#define GPIO_SKL_LP_IOAPIC_GPP_B_05 0x35 +#define GPIO_SKL_LP_IOAPIC_GPP_B_06 0x36 +#define GPIO_SKL_LP_IOAPIC_GPP_B_07 0x37 +#define GPIO_SKL_LP_IOAPIC_GPP_B_08 0x38 +#define GPIO_SKL_LP_IOAPIC_GPP_B_09 0x39 +#define GPIO_SKL_LP_IOAPIC_GPP_B_10 0x3a +#define GPIO_SKL_LP_IOAPIC_GPP_B_11 0x3b +#define GPIO_SKL_LP_IOAPIC_GPP_B_12 0x3c +#define GPIO_SKL_LP_IOAPIC_GPP_B_13 0x3d +#define GPIO_SKL_LP_IOAPIC_GPP_B_14 0x3e +#define GPIO_SKL_LP_IOAPIC_GPP_B_15 0x3f +#define GPIO_SKL_LP_IOAPIC_GPP_B_16 0x40 +#define GPIO_SKL_LP_IOAPIC_GPP_B_17 0x41 +#define GPIO_SKL_LP_IOAPIC_GPP_B_18 0x42 +#define GPIO_SKL_LP_IOAPIC_GPP_B_19 0x43 +#define GPIO_SKL_LP_IOAPIC_GPP_B_20 0x44 +#define GPIO_SKL_LP_IOAPIC_GPP_B_21 0x45 +#define GPIO_SKL_LP_IOAPIC_GPP_B_22 0x46 +#define GPIO_SKL_LP_IOAPIC_GPP_B_23 0x47 + +#define GPIO_SKL_LP_IOAPIC_GPP_C_00 0x48 +#define GPIO_SKL_LP_IOAPIC_GPP_C_01 0x49 +#define GPIO_SKL_LP_IOAPIC_GPP_C_02 0x4a +#define GPIO_SKL_LP_IOAPIC_GPP_C_03 0x4b +#define GPIO_SKL_LP_IOAPIC_GPP_C_04 0x4c +#define GPIO_SKL_LP_IOAPIC_GPP_C_05 0x4d +#define GPIO_SKL_LP_IOAPIC_GPP_C_06 0x4e +#define GPIO_SKL_LP_IOAPIC_GPP_C_07 0x4f +#define GPIO_SKL_LP_IOAPIC_GPP_C_08 0x50 +#define GPIO_SKL_LP_IOAPIC_GPP_C_09 0x51 +#define GPIO_SKL_LP_IOAPIC_GPP_C_10 0x52 +#define GPIO_SKL_LP_IOAPIC_GPP_C_11 0x53 +#define GPIO_SKL_LP_IOAPIC_GPP_C_12 0x54 +#define GPIO_SKL_LP_IOAPIC_GPP_C_13 0x55 +#define GPIO_SKL_LP_IOAPIC_GPP_C_14 0x56 +#define GPIO_SKL_LP_IOAPIC_GPP_C_15 0x57 +#define GPIO_SKL_LP_IOAPIC_GPP_C_16 0x58 +#define GPIO_SKL_LP_IOAPIC_GPP_C_17 0x59 +#define GPIO_SKL_LP_IOAPIC_GPP_C_18 0x5a +#define GPIO_SKL_LP_IOAPIC_GPP_C_19 0x5b +#define GPIO_SKL_LP_IOAPIC_GPP_C_20 0x5c +#define GPIO_SKL_LP_IOAPIC_GPP_C_21 0x5d +#define GPIO_SKL_LP_IOAPIC_GPP_C_22 0x5e +#define GPIO_SKL_LP_IOAPIC_GPP_C_23 0x5f + +#define GPIO_SKL_LP_IOAPIC_GPP_D_00 0x60 +#define GPIO_SKL_LP_IOAPIC_GPP_D_01 0x61 +#define GPIO_SKL_LP_IOAPIC_GPP_D_02 0x62 +#define GPIO_SKL_LP_IOAPIC_GPP_D_03 0x63 +#define GPIO_SKL_LP_IOAPIC_GPP_D_04 0x64 +#define GPIO_SKL_LP_IOAPIC_GPP_D_05 0x65 +#define GPIO_SKL_LP_IOAPIC_GPP_D_06 0x66 +#define GPIO_SKL_LP_IOAPIC_GPP_D_07 0x67 +#define GPIO_SKL_LP_IOAPIC_GPP_D_08 0x68 +#define GPIO_SKL_LP_IOAPIC_GPP_D_09 0x69 +#define GPIO_SKL_LP_IOAPIC_GPP_D_10 0x6a +#define GPIO_SKL_LP_IOAPIC_GPP_D_11 0x6b +#define GPIO_SKL_LP_IOAPIC_GPP_D_12 0x6c +#define GPIO_SKL_LP_IOAPIC_GPP_D_13 0x6d +#define GPIO_SKL_LP_IOAPIC_GPP_D_14 0x6e +#define GPIO_SKL_LP_IOAPIC_GPP_D_15 0x6f +#define GPIO_SKL_LP_IOAPIC_GPP_D_16 0x70 +#define GPIO_SKL_LP_IOAPIC_GPP_D_17 0x71 +#define GPIO_SKL_LP_IOAPIC_GPP_D_18 0x72 +#define GPIO_SKL_LP_IOAPIC_GPP_D_19 0x73 +#define GPIO_SKL_LP_IOAPIC_GPP_D_20 0x74 +#define GPIO_SKL_LP_IOAPIC_GPP_D_21 0x75 +#define GPIO_SKL_LP_IOAPIC_GPP_D_22 0x76 +#define GPIO_SKL_LP_IOAPIC_GPP_D_23 0x77 + +#define GPIO_SKL_LP_IOAPIC_GPP_E_00 0x18 +#define GPIO_SKL_LP_IOAPIC_GPP_E_01 0x19 +#define GPIO_SKL_LP_IOAPIC_GPP_E_02 0x1a +#define GPIO_SKL_LP_IOAPIC_GPP_E_03 0x1b +#define GPIO_SKL_LP_IOAPIC_GPP_E_04 0x1c +#define GPIO_SKL_LP_IOAPIC_GPP_E_05 0x1d +#define GPIO_SKL_LP_IOAPIC_GPP_E_06 0x1e +#define GPIO_SKL_LP_IOAPIC_GPP_E_07 0x1f +#define GPIO_SKL_LP_IOAPIC_GPP_E_08 0x20 +#define GPIO_SKL_LP_IOAPIC_GPP_E_09 0x21 +#define GPIO_SKL_LP_IOAPIC_GPP_E_10 0x22 +#define GPIO_SKL_LP_IOAPIC_GPP_E_11 0x23 +#define GPIO_SKL_LP_IOAPIC_GPP_E_12 0x24 +#define GPIO_SKL_LP_IOAPIC_GPP_E_13 0x25 +#define GPIO_SKL_LP_IOAPIC_GPP_E_14 0x26 +#define GPIO_SKL_LP_IOAPIC_GPP_E_15 0x27 +#define GPIO_SKL_LP_IOAPIC_GPP_E_16 0x28 +#define GPIO_SKL_LP_IOAPIC_GPP_E_17 0x29 +#define GPIO_SKL_LP_IOAPIC_GPP_E_18 0x2a +#define GPIO_SKL_LP_IOAPIC_GPP_E_19 0x2b +#define GPIO_SKL_LP_IOAPIC_GPP_E_20 0x2c +#define GPIO_SKL_LP_IOAPIC_GPP_E_21 0x2d +#define GPIO_SKL_LP_IOAPIC_GPP_E_22 0x2e +#define GPIO_SKL_LP_IOAPIC_GPP_E_23 0x2f + +#define GPIO_SKL_LP_IOAPIC_GPP_F_00 0x30 +#define GPIO_SKL_LP_IOAPIC_GPP_F_01 0x31 +#define GPIO_SKL_LP_IOAPIC_GPP_F_02 0x32 +#define GPIO_SKL_LP_IOAPIC_GPP_F_03 0x33 +#define GPIO_SKL_LP_IOAPIC_GPP_F_04 0x34 +#define GPIO_SKL_LP_IOAPIC_GPP_F_05 0x35 +#define GPIO_SKL_LP_IOAPIC_GPP_F_06 0x36 +#define GPIO_SKL_LP_IOAPIC_GPP_F_07 0x37 +#define GPIO_SKL_LP_IOAPIC_GPP_F_08 0x38 +#define GPIO_SKL_LP_IOAPIC_GPP_F_09 0x39 +#define GPIO_SKL_LP_IOAPIC_GPP_F_10 0x3a +#define GPIO_SKL_LP_IOAPIC_GPP_F_11 0x3b +#define GPIO_SKL_LP_IOAPIC_GPP_F_12 0x3c +#define GPIO_SKL_LP_IOAPIC_GPP_F_13 0x3d +#define GPIO_SKL_LP_IOAPIC_GPP_F_14 0x3e +#define GPIO_SKL_LP_IOAPIC_GPP_F_15 0x3f +#define GPIO_SKL_LP_IOAPIC_GPP_F_16 0x40 +#define GPIO_SKL_LP_IOAPIC_GPP_F_17 0x41 +#define GPIO_SKL_LP_IOAPIC_GPP_F_18 0x42 +#define GPIO_SKL_LP_IOAPIC_GPP_F_19 0x43 +#define GPIO_SKL_LP_IOAPIC_GPP_F_20 0x44 +#define GPIO_SKL_LP_IOAPIC_GPP_F_21 0x45 +#define GPIO_SKL_LP_IOAPIC_GPP_F_22 0x46 +#define GPIO_SKL_LP_IOAPIC_GPP_F_23 0x47 + +#define GPIO_SKL_LP_IOAPIC_GPP_G_00 0x48 +#define GPIO_SKL_LP_IOAPIC_GPP_G_01 0x49 +#define GPIO_SKL_LP_IOAPIC_GPP_G_02 0x4a +#define GPIO_SKL_LP_IOAPIC_GPP_G_03 0x4b +#define GPIO_SKL_LP_IOAPIC_GPP_G_04 0x4c +#define GPIO_SKL_LP_IOAPIC_GPP_G_05 0x4d +#define GPIO_SKL_LP_IOAPIC_GPP_G_06 0x4e +#define GPIO_SKL_LP_IOAPIC_GPP_G_07 0x4f + +#define GPIO_SKL_LP_IOAPIC_GPD_00 0x50 +#define GPIO_SKL_LP_IOAPIC_GPD_01 0x51 +#define GPIO_SKL_LP_IOAPIC_GPD_02 0x52 +#define GPIO_SKL_LP_IOAPIC_GPD_03 0x53 +#define GPIO_SKL_LP_IOAPIC_GPD_04 0x54 +#define GPIO_SKL_LP_IOAPIC_GPD_05 0x55 +#define GPIO_SKL_LP_IOAPIC_GPD_06 0x56 +#define GPIO_SKL_LP_IOAPIC_GPD_07 0x57 +#define GPIO_SKL_LP_IOAPIC_GPD_08 0x58 +#define GPIO_SKL_LP_IOAPIC_GPD_09 0x59 +#define GPIO_SKL_LP_IOAPIC_GPD_10 0x5a +#define GPIO_SKL_LP_IOAPIC_GPD_11 0x5b + +//SPT-H: +#define GPIO_SKL_H_IOAPIC_GPP_A_00 0x18 +#define GPIO_SKL_H_IOAPIC_GPP_A_01 0x19 +#define GPIO_SKL_H_IOAPIC_GPP_A_02 0x1a +#define GPIO_SKL_H_IOAPIC_GPP_A_03 0x1b +#define GPIO_SKL_H_IOAPIC_GPP_A_04 0x1c +#define GPIO_SKL_H_IOAPIC_GPP_A_05 0x1d +#define GPIO_SKL_H_IOAPIC_GPP_A_06 0x1e +#define GPIO_SKL_H_IOAPIC_GPP_A_07 0x1f +#define GPIO_SKL_H_IOAPIC_GPP_A_08 0x20 +#define GPIO_SKL_H_IOAPIC_GPP_A_09 0x21 +#define GPIO_SKL_H_IOAPIC_GPP_A_10 0x22 +#define GPIO_SKL_H_IOAPIC_GPP_A_11 0x23 +#define GPIO_SKL_H_IOAPIC_GPP_A_12 0x24 +#define GPIO_SKL_H_IOAPIC_GPP_A_13 0x25 +#define GPIO_SKL_H_IOAPIC_GPP_A_14 0x26 +#define GPIO_SKL_H_IOAPIC_GPP_A_15 0x27 +#define GPIO_SKL_H_IOAPIC_GPP_A_16 0x28 +#define GPIO_SKL_H_IOAPIC_GPP_A_17 0x29 +#define GPIO_SKL_H_IOAPIC_GPP_A_18 0x2a +#define GPIO_SKL_H_IOAPIC_GPP_A_19 0x2b +#define GPIO_SKL_H_IOAPIC_GPP_A_20 0x2c +#define GPIO_SKL_H_IOAPIC_GPP_A_21 0x2d +#define GPIO_SKL_H_IOAPIC_GPP_A_22 0x2e +#define GPIO_SKL_H_IOAPIC_GPP_A_23 0x2f + +#define GPIO_SKL_H_IOAPIC_GPP_B_00 0x30 +#define GPIO_SKL_H_IOAPIC_GPP_B_01 0x31 +#define GPIO_SKL_H_IOAPIC_GPP_B_02 0x32 +#define GPIO_SKL_H_IOAPIC_GPP_B_03 0x33 +#define GPIO_SKL_H_IOAPIC_GPP_B_04 0x34 +#define GPIO_SKL_H_IOAPIC_GPP_B_05 0x35 +#define GPIO_SKL_H_IOAPIC_GPP_B_06 0x36 +#define GPIO_SKL_H_IOAPIC_GPP_B_07 0x37 +#define GPIO_SKL_H_IOAPIC_GPP_B_08 0x38 +#define GPIO_SKL_H_IOAPIC_GPP_B_09 0x39 +#define GPIO_SKL_H_IOAPIC_GPP_B_10 0x3a +#define GPIO_SKL_H_IOAPIC_GPP_B_11 0x3b +#define GPIO_SKL_H_IOAPIC_GPP_B_12 0x3c +#define GPIO_SKL_H_IOAPIC_GPP_B_13 0x3d +#define GPIO_SKL_H_IOAPIC_GPP_B_14 0x3e +#define GPIO_SKL_H_IOAPIC_GPP_B_15 0x3f +#define GPIO_SKL_H_IOAPIC_GPP_B_16 0x40 +#define GPIO_SKL_H_IOAPIC_GPP_B_17 0x41 +#define GPIO_SKL_H_IOAPIC_GPP_B_18 0x42 +#define GPIO_SKL_H_IOAPIC_GPP_B_19 0x43 +#define GPIO_SKL_H_IOAPIC_GPP_B_20 0x44 +#define GPIO_SKL_H_IOAPIC_GPP_B_21 0x45 +#define GPIO_SKL_H_IOAPIC_GPP_B_22 0x46 +#define GPIO_SKL_H_IOAPIC_GPP_B_23 0x47 + +#define GPIO_SKL_H_IOAPIC_GPP_C_00 0x48 +#define GPIO_SKL_H_IOAPIC_GPP_C_01 0x49 +#define GPIO_SKL_H_IOAPIC_GPP_C_02 0x4a +#define GPIO_SKL_H_IOAPIC_GPP_C_03 0x4b +#define GPIO_SKL_H_IOAPIC_GPP_C_04 0x4c +#define GPIO_SKL_H_IOAPIC_GPP_C_05 0x4d +#define GPIO_SKL_H_IOAPIC_GPP_C_06 0x4e +#define GPIO_SKL_H_IOAPIC_GPP_C_07 0x4f +#define GPIO_SKL_H_IOAPIC_GPP_C_08 0x50 +#define GPIO_SKL_H_IOAPIC_GPP_C_09 0x51 +#define GPIO_SKL_H_IOAPIC_GPP_C_10 0x52 +#define GPIO_SKL_H_IOAPIC_GPP_C_11 0x53 +#define GPIO_SKL_H_IOAPIC_GPP_C_12 0x54 +#define GPIO_SKL_H_IOAPIC_GPP_C_13 0x55 +#define GPIO_SKL_H_IOAPIC_GPP_C_14 0x56 +#define GPIO_SKL_H_IOAPIC_GPP_C_15 0x57 +#define GPIO_SKL_H_IOAPIC_GPP_C_16 0x58 +#define GPIO_SKL_H_IOAPIC_GPP_C_17 0x59 +#define GPIO_SKL_H_IOAPIC_GPP_C_18 0x5a +#define GPIO_SKL_H_IOAPIC_GPP_C_19 0x5b +#define GPIO_SKL_H_IOAPIC_GPP_C_20 0x5c +#define GPIO_SKL_H_IOAPIC_GPP_C_21 0x5d +#define GPIO_SKL_H_IOAPIC_GPP_C_22 0x5e +#define GPIO_SKL_H_IOAPIC_GPP_C_23 0x5f + +#define GPIO_SKL_H_IOAPIC_GPP_D_00 0x60 +#define GPIO_SKL_H_IOAPIC_GPP_D_01 0x61 +#define GPIO_SKL_H_IOAPIC_GPP_D_02 0x62 +#define GPIO_SKL_H_IOAPIC_GPP_D_03 0x63 +#define GPIO_SKL_H_IOAPIC_GPP_D_04 0x64 +#define GPIO_SKL_H_IOAPIC_GPP_D_05 0x65 +#define GPIO_SKL_H_IOAPIC_GPP_D_06 0x66 +#define GPIO_SKL_H_IOAPIC_GPP_D_07 0x67 +#define GPIO_SKL_H_IOAPIC_GPP_D_08 0x68 +#define GPIO_SKL_H_IOAPIC_GPP_D_09 0x69 +#define GPIO_SKL_H_IOAPIC_GPP_D_10 0x6a +#define GPIO_SKL_H_IOAPIC_GPP_D_11 0x6b +#define GPIO_SKL_H_IOAPIC_GPP_D_12 0x6c +#define GPIO_SKL_H_IOAPIC_GPP_D_13 0x6d +#define GPIO_SKL_H_IOAPIC_GPP_D_14 0x6e +#define GPIO_SKL_H_IOAPIC_GPP_D_15 0x6f +#define GPIO_SKL_H_IOAPIC_GPP_D_16 0x70 +#define GPIO_SKL_H_IOAPIC_GPP_D_17 0x71 +#define GPIO_SKL_H_IOAPIC_GPP_D_18 0x72 +#define GPIO_SKL_H_IOAPIC_GPP_D_19 0x73 +#define GPIO_SKL_H_IOAPIC_GPP_D_20 0x74 +#define GPIO_SKL_H_IOAPIC_GPP_D_21 0x75 +#define GPIO_SKL_H_IOAPIC_GPP_D_22 0x76 +#define GPIO_SKL_H_IOAPIC_GPP_D_23 0x77 + +#define GPIO_SKL_H_IOAPIC_GPP_E_00 0x18 +#define GPIO_SKL_H_IOAPIC_GPP_E_01 0x19 +#define GPIO_SKL_H_IOAPIC_GPP_E_02 0x1a +#define GPIO_SKL_H_IOAPIC_GPP_E_03 0x1b +#define GPIO_SKL_H_IOAPIC_GPP_E_04 0x1c +#define GPIO_SKL_H_IOAPIC_GPP_E_05 0x1d +#define GPIO_SKL_H_IOAPIC_GPP_E_06 0x1e +#define GPIO_SKL_H_IOAPIC_GPP_E_07 0x1f +#define GPIO_SKL_H_IOAPIC_GPP_E_08 0x20 +#define GPIO_SKL_H_IOAPIC_GPP_E_09 0x21 +#define GPIO_SKL_H_IOAPIC_GPP_E_10 0x22 +#define GPIO_SKL_H_IOAPIC_GPP_E_11 0x23 +#define GPIO_SKL_H_IOAPIC_GPP_E_12 0x24 + +#define GPIO_SKL_H_IOAPIC_GPP_F_00 0x25 +#define GPIO_SKL_H_IOAPIC_GPP_F_01 0x26 +#define GPIO_SKL_H_IOAPIC_GPP_F_02 0x27 +#define GPIO_SKL_H_IOAPIC_GPP_F_03 0x28 +#define GPIO_SKL_H_IOAPIC_GPP_F_04 0x29 +#define GPIO_SKL_H_IOAPIC_GPP_F_05 0x2a +#define GPIO_SKL_H_IOAPIC_GPP_F_06 0x2b +#define GPIO_SKL_H_IOAPIC_GPP_F_07 0x2c +#define GPIO_SKL_H_IOAPIC_GPP_F_08 0x2d +#define GPIO_SKL_H_IOAPIC_GPP_F_09 0x2e +#define GPIO_SKL_H_IOAPIC_GPP_F_10 0x2f +#define GPIO_SKL_H_IOAPIC_GPP_F_11 0x30 +#define GPIO_SKL_H_IOAPIC_GPP_F_12 0x31 +#define GPIO_SKL_H_IOAPIC_GPP_F_13 0x32 +#define GPIO_SKL_H_IOAPIC_GPP_F_14 0x33 +#define GPIO_SKL_H_IOAPIC_GPP_F_15 0x34 +#define GPIO_SKL_H_IOAPIC_GPP_F_16 0x35 +#define GPIO_SKL_H_IOAPIC_GPP_F_17 0x36 +#define GPIO_SKL_H_IOAPIC_GPP_F_18 0x37 +#define GPIO_SKL_H_IOAPIC_GPP_F_19 0x38 +#define GPIO_SKL_H_IOAPIC_GPP_F_20 0x39 +#define GPIO_SKL_H_IOAPIC_GPP_F_21 0x3a +#define GPIO_SKL_H_IOAPIC_GPP_F_22 0x3b +#define GPIO_SKL_H_IOAPIC_GPP_F_23 0x3c + +#define GPIO_SKL_H_IOAPIC_GPP_G_00 0x3d +#define GPIO_SKL_H_IOAPIC_GPP_G_01 0x3e +#define GPIO_SKL_H_IOAPIC_GPP_G_02 0x3f +#define GPIO_SKL_H_IOAPIC_GPP_G_03 0x40 +#define GPIO_SKL_H_IOAPIC_GPP_G_04 0x41 +#define GPIO_SKL_H_IOAPIC_GPP_G_05 0x42 +#define GPIO_SKL_H_IOAPIC_GPP_G_06 0x43 +#define GPIO_SKL_H_IOAPIC_GPP_G_07 0x44 +#define GPIO_SKL_H_IOAPIC_GPP_G_08 0x45 +#define GPIO_SKL_H_IOAPIC_GPP_G_09 0x46 +#define GPIO_SKL_H_IOAPIC_GPP_G_10 0x47 +#define GPIO_SKL_H_IOAPIC_GPP_G_11 0x48 +#define GPIO_SKL_H_IOAPIC_GPP_G_12 0x49 +#define GPIO_SKL_H_IOAPIC_GPP_G_13 0x4a +#define GPIO_SKL_H_IOAPIC_GPP_G_14 0x4b +#define GPIO_SKL_H_IOAPIC_GPP_G_15 0x4c +#define GPIO_SKL_H_IOAPIC_GPP_G_16 0x4d +#define GPIO_SKL_H_IOAPIC_GPP_G_17 0x4e +#define GPIO_SKL_H_IOAPIC_GPP_G_18 0x4f +#define GPIO_SKL_H_IOAPIC_GPP_G_19 0x50 +#define GPIO_SKL_H_IOAPIC_GPP_G_20 0x51 +#define GPIO_SKL_H_IOAPIC_GPP_G_21 0x52 +#define GPIO_SKL_H_IOAPIC_GPP_G_22 0x53 +#define GPIO_SKL_H_IOAPIC_GPP_G_23 0x54 + +#define GPIO_SKL_H_IOAPIC_GPP_H_00 0x55 +#define GPIO_SKL_H_IOAPIC_GPP_H_01 0x56 +#define GPIO_SKL_H_IOAPIC_GPP_H_02 0x57 +#define GPIO_SKL_H_IOAPIC_GPP_H_03 0x58 +#define GPIO_SKL_H_IOAPIC_GPP_H_04 0x59 +#define GPIO_SKL_H_IOAPIC_GPP_H_05 0x5a +#define GPIO_SKL_H_IOAPIC_GPP_H_06 0x5b +#define GPIO_SKL_H_IOAPIC_GPP_H_07 0x5c +#define GPIO_SKL_H_IOAPIC_GPP_H_08 0x5d +#define GPIO_SKL_H_IOAPIC_GPP_H_09 0x5e +#define GPIO_SKL_H_IOAPIC_GPP_H_10 0x5f +#define GPIO_SKL_H_IOAPIC_GPP_H_11 0x60 +#define GPIO_SKL_H_IOAPIC_GPP_H_12 0x61 +#define GPIO_SKL_H_IOAPIC_GPP_H_13 0x62 +#define GPIO_SKL_H_IOAPIC_GPP_H_14 0x63 +#define GPIO_SKL_H_IOAPIC_GPP_H_15 0x64 +#define GPIO_SKL_H_IOAPIC_GPP_H_16 0x65 +#define GPIO_SKL_H_IOAPIC_GPP_H_17 0x66 +#define GPIO_SKL_H_IOAPIC_GPP_H_18 0x67 +#define GPIO_SKL_H_IOAPIC_GPP_H_19 0x68 +#define GPIO_SKL_H_IOAPIC_GPP_H_20 0x69 +#define GPIO_SKL_H_IOAPIC_GPP_H_21 0x6a +#define GPIO_SKL_H_IOAPIC_GPP_H_22 0x6b +#define GPIO_SKL_H_IOAPIC_GPP_H_23 0x6c + +#define GPIO_SKL_H_IOAPIC_GPP_I_00 0x6d +#define GPIO_SKL_H_IOAPIC_GPP_I_01 0x6e +#define GPIO_SKL_H_IOAPIC_GPP_I_02 0x6f +#define GPIO_SKL_H_IOAPIC_GPP_I_03 0x70 +#define GPIO_SKL_H_IOAPIC_GPP_I_04 0x71 +#define GPIO_SKL_H_IOAPIC_GPP_I_05 0x72 +#define GPIO_SKL_H_IOAPIC_GPP_I_06 0x73 +#define GPIO_SKL_H_IOAPIC_GPP_I_07 0x74 +#define GPIO_SKL_H_IOAPIC_GPP_I_08 0x75 +#define GPIO_SKL_H_IOAPIC_GPP_I_09 0x76 +#define GPIO_SKL_H_IOAPIC_GPP_I_10 0x77 + +#define GPIO_SKL_H_IOAPIC_GPD_00 0x18 +#define GPIO_SKL_H_IOAPIC_GPD_01 0x19 +#define GPIO_SKL_H_IOAPIC_GPD_02 0x1a +#define GPIO_SKL_H_IOAPIC_GPD_03 0x1b +#define GPIO_SKL_H_IOAPIC_GPD_04 0x1c +#define GPIO_SKL_H_IOAPIC_GPD_05 0x1d +#define GPIO_SKL_H_IOAPIC_GPD_06 0x1e +#define GPIO_SKL_H_IOAPIC_GPD_07 0x1f +#define GPIO_SKL_H_IOAPIC_GPD_08 0x20 +#define GPIO_SKL_H_IOAPIC_GPD_09 0x21 +#define GPIO_SKL_H_IOAPIC_GPD_10 0x22 +#define GPIO_SKL_H_IOAPIC_GPD_11 0x23 + +#endif // GPIO_DEFINE_ASL diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/Gpio= Lib.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/GpioLib= .asl new file mode 100644 index 0000000000..cab6f209c8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/GpioLib.asl @@ -0,0 +1,1024 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// GPIO Access Library +// +Scope(\_SB) +{ + +#define PCH_LP_PKG_INDEX 0 +#define PCH_H_PKG_INDEX 1 + + // + // GPIO Community address for each group + // + Name(GCOM, Package(){ + Package(){ //SPT-LP + PCH_GPIO_COM0, //SPT-LP GPP_A + PCH_GPIO_COM0, //SPT-LP GPP_B + PCH_GPIO_COM1, //SPT-LP GPP_C + PCH_GPIO_COM1, //SPT-LP GPP_D + PCH_GPIO_COM1, //SPT-LP GPP_E + PCH_GPIO_COM3, //SPT-LP GPP_F + PCH_GPIO_COM3, //SPT-LP GPP_G + PCH_GPIO_COM2, //SPT-LP GPD + }, + Package(){ //SPT-H + PCH_GPIO_COM0, //SPT-H GPP_A + PCH_GPIO_COM0, //SPT-H GPP_B + PCH_GPIO_COM1, //SPT-H GPP_C + PCH_GPIO_COM1, //SPT-H GPP_D + PCH_GPIO_COM1, //SPT-H GPP_E + PCH_GPIO_COM1, //SPT-H GPP_F + PCH_GPIO_COM1, //SPT-H GPP_G + PCH_GPIO_COM1, //SPT-H GPP_H + PCH_GPIO_COM3, //SPT-H GPP_I + PCH_GPIO_COM2 //SPT-H GPD + } + }) + + // + // Number of GPIO pads per group + // + Name(GPPG, Package(){ + Package(){ //SPT-LP + V_PCH_GPIO_GPP_A_PAD_MAX, // SPT-LP GPP_A + V_PCH_GPIO_GPP_B_PAD_MAX, // SPT-LP GPP_B + V_PCH_GPIO_GPP_C_PAD_MAX, // SPT-LP GPP_C + V_PCH_GPIO_GPP_D_PAD_MAX, // SPT-LP GPP_D + V_PCH_LP_GPIO_GPP_E_PAD_MAX, // SPT-LP GPP_E + V_PCH_GPIO_GPP_F_PAD_MAX, // SPT-LP GPP_F + V_PCH_LP_GPIO_GPP_G_PAD_MAX, // SPT-LP GPP_G + V_PCH_GPIO_GPD_PAD_MAX // SPT-LP GPD + }, + Package(){ //SPT-H + V_PCH_GPIO_GPP_A_PAD_MAX, // SPT-H GPP_A + V_PCH_GPIO_GPP_B_PAD_MAX, // SPT-H GPP_B + V_PCH_GPIO_GPP_C_PAD_MAX, // SPT-H GPP_C + V_PCH_GPIO_GPP_D_PAD_MAX, // SPT-H GPP_D + V_PCH_H_GPIO_GPP_E_PAD_MAX, // SPT-H GPP_E + V_PCH_GPIO_GPP_F_PAD_MAX, // SPT-H GPP_F + V_PCH_H_GPIO_GPP_G_PAD_MAX, // SPT-H GPP_G + V_PCH_H_GPIO_GPP_H_PAD_MAX, // SPT_H GPP_H + V_PCH_H_GPIO_GPP_I_PAD_MAX, // SPT_H GPP_I + V_PCH_GPIO_GPD_PAD_MAX // SPT-H GPD + } + }) + + // + // GPIO Pad Configuration offset + // + Name(PCFG, Package(){ + Package(){ //SPT-LP + R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET, // SPT-LP GPP_A + R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET, // SPT-LP GPP_B + R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET, // SPT-LP GPP_C + R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET, // SPT-LP GPP_D + R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET, // SPT-LP GPP_E + R_PCH_LP_PCR_GPIO_GPP_F_PADCFG_OFFSET, // SPT-LP GPP_F + R_PCH_LP_PCR_GPIO_GPP_G_PADCFG_OFFSET, // SPT-LP GPP_G + R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET // SPT-LP GPD + }, + Package(){ //SPT-H + R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET, // SPT-H GPP_A + R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET, // SPT-H GPP_B + R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET, // SPT-H GPP_C + R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET, // SPT-H GPP_D + R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET, // SPT-H GPP_E + R_PCH_H_PCR_GPIO_GPP_F_PADCFG_OFFSET, // SPT-H GPP_F + R_PCH_H_PCR_GPIO_GPP_G_PADCFG_OFFSET, // SPT-H GPP_G + R_PCH_H_PCR_GPIO_GPP_H_PADCFG_OFFSET, // SPT_H GPP_H + R_PCH_H_PCR_GPIO_GPP_I_PADCFG_OFFSET, // SPT_H GPP_I + R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET // SPT-H GPD + } + }) + + // + // GPIO Host Software Pad Ownership offset + // + Name(HOWN, Package(){ + Package(){ //SPT-LP + R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN, // SPT-LP GPP_A + R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN, // SPT-LP GPP_B + R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN, // SPT-LP GPP_C + R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN, // SPT-LP GPP_D + R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN, // SPT-LP GPP_E + R_PCH_LP_PCR_GPIO_GPP_F_HOSTSW_OWN, // SPT-LP GPP_F + R_PCH_LP_PCR_GPIO_GPP_G_HOSTSW_OWN, // SPT-LP GPP_G + R_PCH_PCR_GPIO_GPD_HOSTSW_OWN // SPT-LP GPD + }, + Package(){ //SPT-H + R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN, // SPT-H GPP_A + R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN, // SPT-H GPP_B + R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN, // SPT-H GPP_C + R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN, // SPT-H GPP_D + R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN, // SPT-H GPP_E + R_PCH_H_PCR_GPIO_GPP_F_HOSTSW_OWN, // SPT-H GPP_F + R_PCH_H_PCR_GPIO_GPP_G_HOSTSW_OWN, // SPT-H GPP_G + R_PCH_H_PCR_GPIO_GPP_H_HOSTSW_OWN, // SPT-H GPP_H + R_PCH_H_PCR_GPIO_GPP_I_HOSTSW_OWN, // SPT-H GPP_I + R_PCH_PCR_GPIO_GPD_HOSTSW_OWN // SPT-H GPD + } + }) + + // + // GPIO Pad Ownership offset + // + Name(POWN, Package(){ + Package(){ //SPT-LP + R_PCH_LP_PCR_GPIO_GPP_A_PAD_OWN, // SPT-LP GPP_A + R_PCH_LP_PCR_GPIO_GPP_B_PAD_OWN, // SPT-LP GPP_B + R_PCH_LP_PCR_GPIO_GPP_C_PAD_OWN, // SPT-LP GPP_C + R_PCH_LP_PCR_GPIO_GPP_D_PAD_OWN, // SPT-LP GPP_D + R_PCH_LP_PCR_GPIO_GPP_E_PAD_OWN, // SPT-LP GPP_E + R_PCH_LP_PCR_GPIO_GPP_F_PAD_OWN, // SPT-LP GPP_F + R_PCH_LP_PCR_GPIO_GPP_G_PAD_OWN, // SPT-LP GPP_G + R_PCH_LP_PCR_GPIO_GPD_PAD_OWN // SPT-LP GPD + }, + Package(){ //SPT-H + R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN, // SPT-H GPP_A + R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN, // SPT-H GPP_B + R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN, // SPT-H GPP_C + R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN, // SPT-H GPP_D + R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN, // SPT-H GPP_E + R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN, // SPT-H GPP_F + R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN, // SPT-H GPP_G + R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN, // SPT-H GPP_H + R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN, // SPT-H GPP_I + R_PCH_H_PCR_GPIO_GPD_PAD_OWN // SPT-H GPD + } + }) + + // + // GPIO GPI_GPE_STS Offset + // + Name(GPEO, Package(){ + Package(){ //SPT-LP + R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS, // SPT-LP GPP_A + R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS, // SPT-LP GPP_B + R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS, // SPT-LP GPP_C + R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS, // SPT-LP GPP_D + R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS, // SPT-LP GPP_E + R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_STS, // SPT-LP GPP_F + R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_STS, // SPT-LP GPP_G + R_PCH_PCR_GPIO_GPD_GPI_GPE_STS // SPT-LP GPD + }, + Package(){ //SPT-H + R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS, // SPT-H GPP_A + R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS, // SPT-H GPP_B + R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS, // SPT-H GPP_C + R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS, // SPT-H GPP_D + R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS, // SPT-H GPP_E + R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS, // SPT-H GPP_F + R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS, // SPT-H GPP_G + R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS, // SPT-H GPP_H + R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS, // SPT-H GPP_I + R_PCH_PCR_GPIO_GPD_GPI_GPE_STS // SPT-H GPD + } + }) + + // + // GPE Enable and Status object. Each bit within one value + // equals to 0 (1-tier) or And(GPE_EN,GPE_STS) (2-tier) and represents + // one pad in selected group. + // + Name(GPES, Package(){ + 0x00000000, // GPP_A + 0x00000000, // GPP_B + 0x00000000, // GPP_C + 0x00000000, // GPP_D + 0x00000000, // GPP_E + 0x00000000, // GPP_F + 0x00000000, // GPP_G + 0x00000000, // GPP_H + 0x00000000, // GPP_I + 0x00000000 // GPD + }) + + // + // Object for storing RX Level/Edge Configuration for all pads. + // Each pad needs 2-bits. + // 00b =3D Level + // 01b =3D Edge (RxInv=3D0 for rising edge; 1 for falling edge) + // 10b =3D Disabled + // 11b =3D Either rising edge or falling edge + // + Name(RXEV, Package(){ + 0xFFFFFFFFFFFFFFFF, // GPP_A + 0xFFFFFFFFFFFFFFFF, // GPP_B + 0xFFFFFFFFFFFFFFFF, // GPP_C + 0xFFFFFFFFFFFFFFFF, // GPP_D + 0xFFFFFFFFFFFFFFFF, // GPP_E + 0xFFFFFFFFFFFFFFFF, // GPP_F + 0xFFFFFFFFFFFFFFFF, // GPP_G + 0xFFFFFFFFFFFFFFFF, // GPP_H + 0xFFFFFFFFFFFFFFFF, // GPP_I + 0xFFFFFFFFFFFFFFFF // GPD + }) + + // + // Get GPIO absolute number for selected GpioPad + // + Method(GNUM, 0x1, NotSerialized) + { + // + // Arg0 - GpioPad + // + + // Local1 - Gpio pad number + Store (GNMB(Arg0), Local1) + // Local2 - Gpio group index for GpioPad + Store (GGRP(Arg0), Local2) + + Return (Add(Local1,Multiply(Local2, 24))) + } + + // + // Get interrupt number for for selected GpioPad + // + Method(INUM, 0x1, NotSerialized) + { + // + // Arg0 - GpioPad + // + + If(LEqual(PCHS, 0x2)) { // SPT-LP + Store(PCH_LP_PKG_INDEX, Local0) + } Else { //SPT-H + Store(PCH_H_PKG_INDEX,Local0) + } + // Local1 - Gpio pad number + Store (GNMB(Arg0), Local1) + // Local2 - Gpio group index for GpioPad + Store (GGRP(Arg0), Local2) + // Local3 - Group index used in a loop + Store (0 , Local3) + + While(LLess (Local3, Local2)) { + Add( DeRefOf( Index (DeRefOf(Index (GPPG, Local0)),Local3)),Local1,L= ocal1) + Increment(Local3) + } + + return(Add(24,Mod(Local1,96))) + } + + // + // Get GPIO group index for GpioPad + // + Method(GGRP,1,serialized) { + // + // Arg0 - GpioPad + // + ShiftRight( And(Arg0,0x00FF0000), 16, Local0) + return (Local0) + } + + // + // Get GPIO pin number for GpioPad + // + Method(GNMB,1,serialized) { + // + // Arg0 - GpioPad + // + return (And(Arg0,0x0000FFFF)) + } + + // + // GPEM (part of PCH NVS) is an object for informing how GPIO groups are= mapped to GPE. + // Mapping for GPP_x is evaluated from (GPEM >> (GroupNumber*2)) & 0x3 + // Possible values for each group: + // 00b - 2-tier + // 01b - 1-tier, GPE_DW0 + // 10b - 1-tier, GPE_DW1 + // 11b - 1-tier, GPE_DW2 + // + + // + // Get GPE number for selected GpioPad + // + Method(GGPE, 0x1, NotSerialized) + { + // + // Arg0 - GPIO pad + // + + //Local0 - GPIO group index (GPP_A - 0, GPP_B - 1 ... ) + Store (GGRP(Arg0), Local0) + //Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // + // Get mapping for certain group + // Local2 =3D (GPEM >> (Local0*2)) & 0x3 + // + Store(And(ShiftRight(GPEM,Multiply(Local0,2)),0x3),Local2) + + If (LEqual(Local2,0x0)) { + // + // Pads mapped to 2-tier GPE will all generate GPE_111 + // + Return (0x6F) + } Else { + // + // For 1-tier GPE calculate GPE number + // GPE number =3D (Local2 - 1)*32 + Local1 + // + Return (Add(Multiply(Subtract(Local2,1),32),Local1)) + } + } + + // + // Get GPIO register address + // + Method(GADR, 0x2, NotSerialized) + { + // + // Arg0 - GPIO Group index + // Arg1 - Package with registers offsets for GPIO groups + // + + If(LEqual(PCHS, 0x2)) { // SPT-LP + Store(PCH_LP_PKG_INDEX, Local0) + } Else { //SPT-H + Store(PCH_H_PKG_INDEX, Local0) + } + //Local1 =3D GpioCommunityAddress + Store( Add( DeRefOf(Index (DeRefOf( Index(GCOM,Local0)),Arg0)),SBRG),L= ocal1) + + //Local2 =3D Register Offset + Store( DeRefOf(Index (DeRefOf( Index(Arg1,Local0)),Arg0)),Local2) + + Return( Add (Local1, Local2)) + } + + // + // Get Pad Configuration DW0 register value + // + Method(GPC0, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG), Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Return(TEMP) + } + + // + // Set Pad Configuration DW0 register value + // + Method(SPC0, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for DW0 register + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG), Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Store(Arg1,TEMP) + } + + // + // Get Pad Configuration DW1 register value + // + Method(GPC1, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + = 0x4 + Store( Add( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),0x4),Local= 2) + OperationRegion(PDW1, SystemMemory, Local2, 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Return(TEMP) + } + + // + // Set Pad Configuration DW1 register value + // + Method(SPC1, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for DW1 register + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local0 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + = 0x4 + Store( Add( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),0x4),Local= 2) + OperationRegion(PDW1, SystemMemory, Local2, 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Store(Arg1,TEMP) + } + + // + // Set RX Override + // + Method(SRXO, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - 0=3Dno override, 1=3Ddrive RX to 1 internally + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + ,28, + TEMP,1, + ,3 + } + Store(Arg1,TEMP) + } + + // + // Get GPI Input Value + // + Method(GGIV, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 1, + TEMP,1, + , 30 + } + Return(TEMP) + } + + // + // Get GPO Output Value + // + Method(GGOV, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,1, + , 31 + } + Return(TEMP) + } + + // + // Set GPO Output Value + // + Method(SGOV, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value of GPIO Tx State + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,1, + , 31 + } + Store(Arg1,TEMP) + } + + // + // Get GPI Input Invert Bit + // + Method(GGII, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 23, + TEMP,1, + , 8 + } + Return(TEMP) + } + + // + // Set GPI Input Invert Bit + // + Method(SGII, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value of RXINV bit for selected pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 23, + TEMP,1, + , 8 + } + Store(Arg1,TEMP) + } + + // + // Get GPIO Pad Mode + // + Method(GPMV, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 10, + TEMP,3, + , 19 + } + Return(TEMP) + } + + // + // Set GPIO Pad Mode + // + Method(SPMV, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for Pad Mode for selected pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 10, + TEMP,3, + , 19 + } + Store(Arg1,TEMP) + } + + // + // Get GPIO Host Software Pad Ownership + // + Method(GHPO, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + OperationRegion(PREG, SystemMemory, GADR(Local0,HOWN), 4) + Field(PREG, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + // HostSwOwnValue =3D (TEMP >> Local1) & 0x1 + Return( And( ShiftRight(TEMP,Local1),0x1)) + } + + // + // Set GPIO Host Software Pad Ownership + // + Method(SHPO, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for GPIO Host Software Pad Ownership + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + OperationRegion(PREG, SystemMemory, GADR(Local0,HOWN), 4) + Field(PREG, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + // TEMP =3D (TEMP & (~(1 << PadNumber))) | (HostSwOwnValue << PadNumbe= r) + Or(And(TEMP, Not(ShiftLeft(1,Local1))),ShiftLeft(Arg1,Local1),TEMP) + } + + // + // Get GPIO Pad Ownership + // + Method(GGPO, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D GpioCommunityAddress + PadOwnOffset + (PadNumber >> 3) *= 0x4 + Store( Add( GADR(Local0,POWN) , Multiply( ShiftRight(Local1,3),0x4)),L= ocal2) + OperationRegion(PREG, SystemMemory, Local2, 4) + Field(PREG, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + // PadOwnValue =3D (TEMP >> ((Local1 & 0x7) * 4)) & 0x3 + Return( And( ShiftRight(TEMP,Multiply(And(Local1,0x7),0x4)),0x3)) + } + + // + // Set GPIO GPIRoutIOxAPIC value + // + Method(SGRA, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for GPIRoutIOxAPIC + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 20, + TEMP,1, + , 11 + } + Store(Arg1,TEMP) + } + + // + // Set GPIO weak pull-up/down value + // + Method(SGWP, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for weak pull-up/down + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + 0x4 + (GPIn * 0x= 08) + Store( Add( Add( GADR(Local0,PCFG), Multiply(Local1,0x08)),0x4),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 10, + TEMP,4, + , 18 + } + Store(Arg1,TEMP) + } + + // + // UGPS, ISME and CGPS methods are used to properly handle 2-tier GPE + // Example: + /* + Method(_L6F, 0) // Method which is called for all 2-tier GPE, must be = within _GPE scope + { + \_SB.UGPS() // Update information on GPIO mapping to 1 and 2 tier GPE + If (\_SB.ISME(GpioPad)) + { + \_SB.DeviceXYZ.GPEH() // Custom function to handle GPE for certa= in GPIO pad + } + \_SB.CGPS() //Clear STS here + } + */ + + // + // Update one group entry in GPES object + // This method is used by UGPS() + // + Method(UGP1, 0x1, Serialized) + { + // + // Arg0 - GPIO group index + // + OperationRegion(GPPX, SystemMemory, GADR(Arg0,GPEO), 36) + Field(GPPX, AnyAcc, NoLock, Preserve) { + Offset(0x0), + STSX,32, + Offset(0x20), + GENX,32 + } + //Check if 2-tier + If(LEqual(And(ShiftRight(GPEM,Multiply(Arg0,2)),0x3),0x0)) { + //Store result of GPI_GPE_EN&GPI_GPE_STS in GPES object + Store ( And(STSX,GENX), Index (GPES, Arg0)) + } Else { + // If 1-tier store 0 in GPES object + Store ( 0x0, Index (GPES, Arg0)) + } + } + + // + // Update GPES object + // + Method(UGPS, 0x0, Serialized) + { + //Local0 - GPIO group index + If(LEqual(PCHS, 0x1)) { // SPT-H + Store(V_PCH_H_GPIO_GROUP_MAX,Local0) + } Else { //SPT-LP + Store(V_PCH_LP_GPIO_GROUP_MAX,Local0) + } + + While(Local0) { + Decrement(Local0) + UGP1(Local0) + } + } + + // + // Clear GPE status for one group from 2-tier + // This method is used by CGPS() + // + Method(CGP1, 0x2, Serialized) { + // + // Arg0 - GPIO group index + // Arg1 - Mask of bits (GpioPads) for which status should be cleared + // + //Check if 2-tier + If(LEqual(And(ShiftRight(GPEM,Multiply(Arg0,2)),0x3),0x0)) { + //Get GPI_GPE_STS for GPP_x + OperationRegion(GPPX, SystemMemory, GADR(Arg0,GPEO), 4) + Field(GPPX, AnyAcc, NoLock, Preserve) { + Offset(0x0), + STSX,32, + } + //Clear status + Store (Arg1, STSX) + } + } + + // + // Clear all GPE status for 2-tier + // + Method(CGPS, 0x0, Serialized) { + //Local0 - GPIO group index + If(LEqual(PCHS, 0x1)) { // SPT-H + Store(V_PCH_H_GPIO_GROUP_MAX,Local0) + } Else { //SPT-LP + Store(V_PCH_LP_GPIO_GROUP_MAX,Local0) + } + + While(Local0) { + Decrement(Local0) + CGP1(Local0, 0xFFFFFFFF) + } + } + + // + // Clear all GPE status for 2-tier which are level sensitive + // + Method(CGLS, 0x0, Serialized) { + //Local0 - GPIO group index + If(LEqual(PCHS, 0x1)) { // SPT-H + Store(V_PCH_H_GPIO_GROUP_MAX,Local0) + } Else { //SPT-LP + Store(V_PCH_LP_GPIO_GROUP_MAX,Local0) + } + + While(Local0) { + Decrement(Local0) + + If(LEqual(Local0,9)){Store(G2L9,Local1);} + ElseIf(LEqual(Local0,8)){Store(G2L8,Local1);} + ElseIf(LEqual(Local0,7)){Store(G2L7,Local1);} + ElseIf(LEqual(Local0,6)){Store(G2L6,Local1);} + ElseIf(LEqual(Local0,5)){Store(G2L5,Local1);} + ElseIf(LEqual(Local0,4)){Store(G2L4,Local1);} + ElseIf(LEqual(Local0,3)){Store(G2L3,Local1);} + ElseIf(LEqual(Local0,2)){Store(G2L2,Local1);} + ElseIf(LEqual(Local0,1)){Store(G2L1,Local1);} + ElseIf(LEqual(Local0,0)){Store(G2L0,Local1);} + Else {continue} + + CGP1(Local0,Local1) + } + } + + // + // Clear a particular GPE status for 2-tier + // + Method(CAGS, 0x1, Serialized) { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + //Check if 2-tier + If(LEqual(And(ShiftRight(GPEM,Multiply(Local0,2)),0x3),0x0)) { + //Get GPI_GPE_STS for GPP_x + OperationRegion(GPPX, SystemMemory, GADR(Local0,GPEO), 4) + Field(GPPX, AnyAcc, NoLock, Preserve) { + Offset(0x0), + STSX,32, + } + //Clear status + Store (STSX, Local3) + ShiftLeft(1, Local1, Local2) + Or(STSX, Local2, STSX) // Clear GPIO status + } + } + + // + // Check GPES buffer + // + Method(ISME, 0x1, NotSerialized) { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // return (GPES[Group]>>PadNumber) & 0x1 + Return( And( ShiftRight(DeRefOf( Index(GPES,Local0)),Local1),0x1)) + } + + // + // Do Interrupt Pin Isolation + // This method should be called before power gating external device + // + Method(DIPI, 0x1, Serialized) { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 9, + RDIS,1, + , 15, + RCFG,2, + , 5 + } + If(LNotEqual(RCFG,2)) { + // Save RxEvCfg state in RXEV object: + // Local3 =3D RXEV[Group] + // Local3 &=3D ~(0x3 << (PadNr*2)) + // RXEV[Group] =3D Local3 + Store(DeRefOf(Index (RXEV, Local0)),Local3) + And(Local3,Not(ShiftLeft(0x3,Multiply(Local1,2))),Local3) + Or(Local3,ShiftLeft(RCFG,Multiply(Local1,2)),Index(RXEV,Local0)) + // Set RxEvCfg to 2 + Store(2,RCFG) + // Set GPIORxDis to 1 + Store(1,RDIS) + } + } + + // + // Undo Interrupt Pin Isolation + // This method should be called after un-power gating external device + // + Method(UIPI, 0x1, Serialized) { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 =3D (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG), Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 9, + RDIS,1, + , 15, + RCFG,2, + , 5 + } + // Get RxEvCfg original value from RXEV object + // Local3 =3D (RXEV[Group] >> (PadNr*2)) & 0x3 + Store(And(ShiftRight(DeRefOf(Index (RXEV, Local0)),Multiply(Local1,2))= ,0x3),Local3) + + If(LNotEqual(Local3,2)) { + // Set GPIORxDis to 0 + Store(0,RDIS) + // Set RxEvCfg to original value + Store(Local3,RCFG) + } + } + +} // \_SB Scope + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/IrqL= ink.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/IrqLink= .asl new file mode 100644 index 0000000000..155da2d21f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/IrqLink.asl @@ -0,0 +1,607 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// Use this information when determining the Possible IRQs that can be +// used in a given system. +// +// The following IRQs are always in use by legacy devices: +// 0 =3D System Timer +// 2 =3D 8259 PIC +// 8 =3D RTC +// 9 =3D SCI Interrupt (It may be used, we choose not to) +// 13 =3D Co-processor Error +// +// The following may be in use by legacy devices: +// 1 =3D If using PS/2 Keyboard +// 3 =3D If COMx Port Enabled and IRQ =3D 3 +// 4 =3D If COMx Port Enabled and IRQ =3D 4 +// 5 =3D If LPT Port Enabled and IRQ =3D 5 +// 6 =3D If FDC Enabled +// 7 =3D If LPT Port Enabled and IRQ =3D 7 +// 12 =3D If using PS/2 Mouse +// 14 =3D Primary IDE (If populated and in Compatibility Mode) +// 15 =3D Secondary IDE (If populated and in Compatibility Mode) +// +// The following will never be in use by legacy devices: +// 10 =3D Assign to PARC, PCRC, PERC, PGRC +// 11 =3D Assign to PBRC, PDRC, PFRC, PHRC + +Device(LNKA) // PARC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) // PCI Interrupt Link Device + + Name(_UID,1) // Unique to other Link Devices + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PARC,0x80,\_SB.PARC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSA) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLA,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLA,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PARC,0x0F),IRQ0) + + Return(RTLA) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PARC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PARC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKB) // PBRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,2) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PBRC,0x80,\_SB.PBRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSB) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLB,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLB,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PBRC,0x0F),IRQ0) + + Return(RTLB) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PBRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PBRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKC) // PCRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,3) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PCRC,0x80,\_SB.PCRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSC) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLC,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLC,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PCRC,0x0F),IRQ0) + + Return(RTLC) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PCRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PCRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKD) // PDRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,4) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PDRC,0x80,\_SB.PDRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSD) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLD,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLD,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PDRC,0x0F),IRQ0) + + Return(RTLD) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PDRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PDRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKE) // PERC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,5) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PERC,0x80,\_SB.PERC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSE) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLE,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLE,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PERC,0x0F),IRQ0) + + Return(RTLE) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PERC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PERC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKF) // PFRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,6) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PFRC,0x80,\_SB.PFRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSF) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLF,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLF,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PFRC,0x0F),IRQ0) + + Return(RTLF) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PFRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PFRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKG) // PGRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,7) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PGRC,0x80,\_SB.PGRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSG) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLG,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLG,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PGRC,0x0F),IRQ0) + + Return(RTLG) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PGRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PGRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKH) // PHRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,8) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PHRC,0x80,\_SB.PHRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSH) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLH,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLH,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PHRC,0x0F),IRQ0) + + Return(RTLH) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PHRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PHRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/Pch.= asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/Pch.asl new file mode 100644 index 0000000000..0c550b528c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/Pch.asl @@ -0,0 +1,833 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Name (PNVB, 0xFFFF0000) // PCH NVS Base address +Name (PNVL, 0xAA55) // PCH NVS Length +Include ("PchNvs.asl") + + +// +// Trace Hub debug library +// Include it earlier so the debug function can be used as soon as possible +// +Include ("TraceHubDebug.asl") + +Name(SPTH,1) +Name(SPTL,2) +Method(PCHV) { + If(LEqual(PCHS, 1)) { Return (SPTH) } // series=3DH -> SPT-H + If(LEqual(PCHS, 2)) { Return (SPTL) } // series=3DLP -> SPT-LP + Return (0) +} + +// +// This PME event (PCH's GPE 6Dh) is received when any PCH internal device= with +// PCI Power Management capabilities on bus 0 asserts the equivalent of th= e PME# signal. +// +Scope(\_GPE) { + Method(_L6D, 0, Serialized) { + \_SB.PC00.XHCI.GPEH() + \_SB.PC00.CAVS.GPEH() + \_SB.PC00.GBE1.GPEH() + } +} + +Scope (\_SB.PC00) { + + // + // PCH reserved resource + // + Device(PRRE) { + Name(_HID,EISAID("PNP0C02")) // motherboard resource + Name(_UID,"PCHRESV") + Name(_STA,0x3) // device present and decodes its resources, but not to= be displayed in OSPM + + Method(_CRS,0,Serialized) + { + Name(BUF0,ResourceTemplate(){ + // + // PCH RESERVED MMIO RANGE + // 0xFD000000 to 0xFE7FFFFF + // to skip over address range that might be claimed by the GPIO, I= ntel Serial IO, Thermal, TraceHub and CIO2 devices + // need to split this into 5 ranges + // The GPIO COMM0,1,3 and SerialIO ranges will be handled by SIRC = device. + // + Memory32Fixed(ReadWrite,0xFD000000,0x00AC0000) // 0xFD000000 - 0xF= DABFFFF + // Skip 0xFDAC0000 - 0xFDACFFFF for GPIO_COMM3 + Memory32Fixed(ReadWrite,0xFDAD0000,0x00010000) // 0xFDAD0000 - 0xF= DADFFFF, only cover GPIO_COMM2 range + // Skip 0xFDAE0000 - 0xFDAFFFFF for GPIO_COMM0 and GPIO_COMM1 + Memory32Fixed(ReadWrite,0xFDB00000,0x00500000) // 0xFDB00000 - 0xF= DFFFFFF + Memory32Fixed(ReadWrite,0xFE000000,0x00010000) // 0xFE000000 - 0xF= E00FFFF + Memory32Fixed(ReadWrite,0xFE011000,0x0000f000) // 0xFE011000 - 0xF= E01FFFF + // Skip 0xFE020000 - 0xFE035FFF for Serial IO + Memory32Fixed(ReadWrite,0xFE036000,0x00006000) // 0xFE036000 - 0xF= E03BFFF + // Skip 0xFE03C000 - 0xFE03CFFF for Thermal Device in ACPI mode + Memory32Fixed(ReadWrite,0xFE03D000,0x003C3000) // 0xFE03D000 - 0xF= E3FFFFF + // Skip 0xFE400000 - 0xFE40FFFF for CIO2 in ACPI mode + Memory32Fixed(ReadWrite,0xFE410000,0x003F0000) // 0xFE410000 - 0xF= E7FFFFF + }) + Return(BUF0) + } + } + Device(IOTR) { + // + // This device claims IO range reserved for IO traps + // to prevent OS from reusing it for other purposes + // + Name(_HID,EISAID("PNP0C02")) + Name(_UID,"IoTraps") + Name(BUF0,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG0) }) + Name(BUF1,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG1) }) + Name(BUF2,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG2) }) + Name(BUF3,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG3) }) + CreateWordField(BUF0,TAG0._MIN,AMI0) + CreateWordField(BUF0,TAG0._MAX,AMA0) + CreateWordField(BUF1,TAG1._MIN,AMI1) + CreateWordField(BUF1,TAG1._MAX,AMA1) + CreateWordField(BUF2,TAG2._MIN,AMI2) + CreateWordField(BUF2,TAG2._MAX,AMA2) + CreateWordField(BUF3,TAG3._MIN,AMI3) + CreateWordField(BUF3,TAG3._MAX,AMA3) + Method(_CRS) { + Store(ResourceTemplate() { }, Local0) + Store(ITA0,AMI0);Store(ITA0,AMA0) + Store(ITA1,AMI1);Store(ITA1,AMA1) + Store(ITA2,AMI2);Store(ITA2,AMA2) + Store(ITA3,AMI3);Store(ITA3,AMA3) + if(LEqual(ITS0,1)) { ConcatenateResTemplate(Local0, BUF0, Local0) } + if(LEqual(ITS1,1)) { ConcatenateResTemplate(Local0, BUF1, Local0) } + if(LEqual(ITS2,1)) { ConcatenateResTemplate(Local0, BUF2, Local0) } + if(LEqual(ITS3,1)) { ConcatenateResTemplate(Local0, BUF3, Local0) } + return (Local0) + } + } + + + // + // LPC Bridge - Device 31, Function 0, this is only for PCH register Mem= ory Region declare, + // it's better to be declared as early as possible since it's widely use= d in whole ACPI name space. + // Please add any code which needs to reference any register of it after= this + // + Scope (\_SB.PC00.LPC0) { + Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,= Arg3)) }; return(0)} + + OperationRegion(LPC, PCI_Config, 0x00, 0x100) + Field(LPC, AnyAcc, NoLock, Preserve) + { + Offset(0x02), + CDID, 16, + Offset(0x08), + CRID, 8, + Offset(0x80), + IOD0, 8, + IOD1, 8, + Offset(0xA0), + , 9, + PRBL, 1, + Offset(0xAC), + , 8, + , 8, + XUSB, 1, + Offset(0xB8), + , 22, + GR0B, 2, + , 8, + Offset(0xBC), + , 2, + GR19, 2, + , 28, + Offset(0xDC), + , 2, + ESPI, 1, + } + } + + // + // PCH Power Management Controller + // + Scope(\_SB.PC00.PMC1) { + Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,= Arg3)) }; return(0)} + + OperationRegion(PMCB, PCI_Config, 0x00, 0x100) + Field(PMCB, AnyAcc, NoLock, Preserve) { + VDID, 32, + Offset(0x40), + , 8, + ACBA, 8, + Offset(0x48), + , 12, + PWBA, 20, + } + } + + // + // SMBus Controller - Device 31, Function 4 + // + Device(SBUS) { + Name(_ADR,0x001F0004) + Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,= Arg3)) }; return(0)} + } +} + + +Scope(\) +{ + // + // PCR Register Access Methods + // + // PCR Dword Read + // arg0: PID + // arg1: Offset + // + Method (PCRR, 2, Serialized) { + Add (ShiftLeft (arg0, 16), arg1, Local0) + Add (SBRG, Local0, Local0) + OperationRegion (PCR0, SystemMemory, Local0, 0x4) + Field(PCR0,DWordAcc,Lock,Preserve) { + Offset(0x00), + DAT0, 32 + } // End Field PCR0 + Return (DAT0) + } // End Method PCRR + + // + // PCR Dword Write + // arg0: PID + // arg1: Offset + // arg2: write data + // + Method (PCRW, 3, Serialized) { + Add (ShiftLeft (arg0, 16), arg1, Local0) + Add (SBRG, Local0, Local0) + OperationRegion (PCR0, SystemMemory, Local0, 0x4) + Field(PCR0,DWordAcc,Lock,Preserve) { + Offset(0x00), + DAT0, 32 + } // End Field PCR0 + Store (arg2, DAT0) + + // read back for PCR back to back limitation + OperationRegion (PCR1, SystemMemory, ADD (SBRG, 0x00C73418), 0x4) + Field(PCR1,DWordAcc,Lock,Preserve) { + Offset(0x00), + DAT1, 32 + } // End Field PCR1 + } // End Method PCRW + + // + // PCR Dword Or + // arg0: PID + // arg1: Offset + // arg2: Or data + // + Method (PCRO, 3, Serialized) { + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0 + Store(Or(Local0,arg2),Local1) // Or data + PCRW(arg0,arg1,Local1) // Write data back + } + + // + // PCR Dword And + // arg0: PID + // arg1: Offset + // arg2: And data + // + Method (PCRA, 3, Serialized) { + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0 + Store(And(Local0,arg2),Local1) // And data + PCRW(arg0,arg1,Local1) // Write data back + } + + // + // PCR Dword AndThenOr + // arg0: PID + // arg1: Offset + // arg2: And data + // arg3: Or data + // + Method (PCAO, 4, Serialized) { + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Loca= l0 + Store(Or(And(Local0,arg2),arg3),Local1) // AndThenOr + PCRW(arg0,arg1,Local1) // Write data back + } + + Name (PMBV, 0) // ACPI I/O base address value + Method (PMB1, 0) { + If (LEqual(PMBV, 0)) { + Store (ShiftLeft (\_SB.PC00.PMC1.ACBA, 8), PMBV) + } + Return (PMBV) + } + + Name (PWRV, 0) // PWRM base address value + Method (PWRM, 0) { + If (LEqual(PWRV, 0)) { + Store (ShiftLeft (\_SB.PC00.PMC1.PWBA, 12), PWRV) + } + Return (PWRV) + } + + + // + // Define PCH ACPIBASE I/O as an ACPI operating region. The base address + // can be found in Device 31, Function 2, Offset 40h. + // + OperationRegion(PMIO, SystemIo, PMB1, 0x80) + Field(PMIO, ByteAcc, NoLock, Preserve) { + , 8, + PBSS, 1, // Power Button Status + Offset(0x40), // General Purpose Event Control + , 17, + GPEC, 1 // Software GPE Control + } + OperationRegion(PMLP, SystemIo, Add(\PMB1,0x80), 0x20) + Field(PMLP, ByteAcc, NoLock, Preserve) { + Offset(0x10), // GPE0 Enable + , 8, + GE08, 1, + , 8, + GE17, 1, + , 17, + GE35, 1, + , 9, + GE45, 1, + , 2, + GE48, 1, + , 2, + GE51, 1, + , 76, + } + Field(PMLP, ByteAcc, NoLock, WriteAsZeros) { + Offset(0x00), // GPE0 Status + , 8, + GS08, 1, + , 8, + GS17, 1, + , 17, + GS35, 1, + , 9, + GS45, 1, + , 2, + GS48, 1, + , 2, + GS51, 1, + , 2, + GS54, 1, + GS55, 1, + , 72, + } + + + + // + // PWRM register definitions + // + OperationRegion(PWMR, SystemMemory, \PWRM, 0x800) + Field(PWMR, AnyAcc, NoLock, Preserve) { + Offset(0x0E0), + , 16, + DWLE, 1, // Deep-Sx WLAN Phy Power Enable + HWLE, 1, // Host Wireless LAN Phy Power Enable + } + + // + // + OperationRegion(PMST, SystemMemory, PWRV, 0x80) + Field(PMST, DWordAcc, NoLock, Preserve) { + Offset(0x18), // Power Management Configuration Reg 1 (PM_CFG) + , 25, // + USBP, 1, // Allow USB2 PHY Core Power Gating (ALLOW_USB2_CORE_PG) + Offset(0x1C), // PCH Power Management Status (PCH_PM_STS) + , 24, // + PMFS, 1, // PMC Message Full Status (PMC_MSG_FULL_STS) + Offset(0x20), // Message to PMC (MTPMC) + MPMC, 32, // Message to PMC (MTPMC) + Offset(0x24), // PCH Power Management Status (PCH_PM_STS2) + , 20, // + UWAB, 1, // USB2 Workaround Available Bit + } + +} //end Scope(\) + +Scope (\_SB.PC00) { + Name(LTRN, 0) + Name(OBFN, 0) + + Name(LMSL, 0) + Name(LNSL, 0) + + // + // LAN Controller - Device 31, Function 6 + // + Scope(\_SB.PC00.GBE1) { + Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,= Arg3)) }; return(0)} + OperationRegion(GLBA, PCI_Config, 0,0x100) + Field(GLBA,AnyAcc,NoLock,Preserve) + { + DVID, 16, + Offset(0xCC), + , 8, + PMEE, 1, // PME Enable + , 6, + PMES, 1, // PME Status + } + + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // can wakeup from S4 state + + Method(_DSW, 3) + { + Store(Arg0, PMEE) + } + + // + // GPE handler for GbE, this is part of _Lxx handler for bus 0 PME + // + Method(GPEH) + { + If(LEqual(DVID, 0xFFFF)) { + Return() + } + If(LAnd(PMEE, PMES)) { + Store(1, PMES) // clear PME Status + Notify(GBE1, 0x02) + } + } + } // end "GbE Controller" + +} //scope + +// +// xHCI Controller - Device 20, Function 0 +// +Include("PchXhci.asl") + +// xDCI (OTG) Controller is not used in Server +// Comment out as ifdefs don't work at Trim stage of ASL preparation + +Scope(\_SB_.PC00) { + // + // High Definition Audio Controller - Device 31, Function 3 + // + include("PchHda.asl") + + // + // PCIE Root Port #01 + // + Scope(\_SB.PC00.RP01) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR1, LTRN) + Store (PML1, LMSL) + Store (PNL1, LNSL) + Store (OBF1, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #01" + + // + // PCIE Root Port #02 + // + Scope(\_SB.PC00.RP02) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR2, LTRN) + Store (PML2, LMSL) + Store (PNL2, LNSL) + Store (OBF2, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #02" + + // + // PCIE Root Port #03 + // + Scope(\_SB.PC00.RP03) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR3, LTRN) + Store (PML3, LMSL) + Store (PNL3, LNSL) + Store (OBF3, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #03" + + // + // PCIE Root Port #04 + // + Scope(\_SB.PC00.RP04) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR4, LTRN) + Store (PML4, LMSL) + Store (PNL4, LNSL) + Store (OBF4, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #04" + + // + // PCIE Root Port #05 + // + Scope(\_SB.PC00.RP05) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR5, LTRN) + Store (PML5, LMSL) + Store (PNL5, LNSL) + Store (OBF5, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #05" + + // + // PCIE Root Port #06 + // + Scope(\_SB.PC00.RP06) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR6, LTRN) + Store (PML6, LMSL) + Store (PNL6, LNSL) + Store (OBF6, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #06" + + // + // PCIE Root Port #07 + // + Scope(\_SB.PC00.RP07) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR7, LTRN) + Store (PML7, LMSL) + Store (PNL7, LNSL) + Store (OBF7, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #07" + + // + // PCIE Root Port #08 + // + Scope(\_SB.PC00.RP08) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR8, LTRN) + Store (PML8, LMSL) + Store (PNL8, LNSL) + Store (OBF8, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #08" + + // + // PCIE Root Port #09 + // + Scope(\_SB.PC00.RP09) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR9, LTRN) + Store (PML9, LMSL) + Store (PNL9, LNSL) + Store (OBF9, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #09" + + // + // PCIE Root Port #10 + // + Scope(\_SB.PC00.RP10) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRA, LTRN) + Store (PMLA, LMSL) + Store (PNLA, LNSL) + Store (OBFA, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #10" + + // + // PCIE Root Port #11 + // + Scope(\_SB.PC00.RP11) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRB, LTRN) + Store (PMLB, LMSL) + Store (PNLB, LNSL) + Store (OBFB, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #11" + + // + // PCIE Root Port #12 + // + Scope(\_SB.PC00.RP12) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRC, LTRN) + Store (PMLC, LMSL) + Store (PNLC, LNSL) + Store (OBFC, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #12" + + // + // PCIE Root Port #13 + // + Scope(\_SB.PC00.RP13) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRD, LTRN) + Store (PMLD, LMSL) + Store (PNLD, LNSL) + Store (OBFD, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #13" + + // + // PCIE Root Port #14 + // + Scope(\_SB.PC00.RP14) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRE, LTRN) + Store (PMLE, LMSL) + Store (PNLE, LNSL) + Store (OBFE, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #14" + + // + // PCIE Root Port #15 + // + Scope(\_SB.PC00.RP15) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRF, LTRN) + Store (PMLF, LMSL) + Store (PNLF, LNSL) + Store (OBFF, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #15" + + // + // PCIE Root Port #16 + // + Scope(\_SB.PC00.RP16) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRG, LTRN) + Store (PMLG, LMSL) + Store (PNLG, LNSL) + Store (OBFG, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #16" + + // + // PCIE Root Port #17 + // + Scope(\_SB.PC00.RP17) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRH, LTRN) + Store (PMLH, LMSL) + Store (PNLH, LNSL) + Store (OBFH, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #17" + + // + // PCIE Root Port #18 + // + Scope(\_SB.PC00.RP18) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRI, LTRN) + Store (PMLI, LMSL) + Store (PNLI, LNSL) + Store (OBFI, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #18" + + // + // PCIE Root Port #19 + // + Scope(\_SB.PC00.RP19) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRJ, LTRN) + Store (PMLJ, LMSL) + Store (PNLJ, LNSL) + Store (OBFJ, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #19" + + // + // PCIE Root Port #20 + // + Scope(\_SB.PC00.RP20) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRK, LTRN) + Store (PMLK, LMSL) + Store (PNLK, LNSL) + Store (OBFK, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #20" + + // + // Serial ATA Host Controller - Device 31, Function 2 + // +External(\_SB.PC00.SAT0.SDSM, MethodObj) + +Scope (\_SB.PC00.SAT1) { + Include ("PchSata.asl") + Device(PRT6) + { + Name(_ADR,0x0006FFFF) // Port 6 + } + Device(PRT7) + { + Name(_ADR,0x0007FFFF) // Port 7 + } +} +Scope (\_SB.PC00.SAT2) { + Include ("PchSata.asl") +} + //Server does not support CIO Camera I/O + + // + // Thermal Device + // + Scope(\_SB.PC00.TERM) { + Name (_HID, "INT343D") + Name (_UID, 1) + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFE03C000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) { = 18 } + }) + + CreateDWordField(RBUF,IRQ._INT,IRQN) + Method (_CRS, 0x0, NotSerialized) { + Store(TIRQ, IRQN) + + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(TAEN, 0)) { Return(0x0) } // device not enabled in ACPI = mode + If(LEqual(TIRQ, 0)) { Return(0x0) } // IRQ number not updated + Return(0xF) + } + } +} + +// Comment out as ifdefs don't work at Trim stage of ASL preparation + +// +// Storage and Communication Subsystems definitions +// +Include ("PchScs.asl") + + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchA= cpiTables.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/P= chAcpiTables.inf new file mode 100644 index 0000000000..85500e7f64 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchAcpiTabl= es.inf @@ -0,0 +1,34 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010005 +BASE_NAME =3D PchAcpiTables +FILE_GUID =3D 31401EE7-1600-437c-A11C-B1035D8E6070 +MODULE_TYPE =3D USER_DEFINED +VERSION_STRING =3D 1.0 + +[Sources] + Pch.asl + PchNvs.asl + PchHda.asl + PchSerialIo.asl + PchPcie.asl + PchSata.asl + PchRstPcieStorage.asl + UsbSbd.asl + PchXhci.asl + PchXdci.asl + IrqLink.asl + PchGpioDefine.asl + PchGpioLib.asl + TraceHubDebug.asl + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchH= da.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchHda.a= sl new file mode 100644 index 0000000000..69f7b5992b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchHda.asl @@ -0,0 +1,306 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Bit Difinitions +// +#ifndef BIT0 +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#endif //BIT0 + +// +// High Definition Audio Controller - Device 31, Function 3 +// +Scope(\_SB.PC00.CAVS) { + +#ifndef BIT0 +#define BIT0 0x00000001 +#endif +#ifndef BIT1 +#define BIT1 0x00000002 +#endif +#ifndef BIT2 +#define BIT2 0x00000004 +#endif +#ifndef BIT3 +#define BIT3 0x00000008 +#endif +#ifndef BIT4 +#define BIT4 0x00000010 +#endif +#ifndef BIT5 +#define BIT5 0x00000020 +#endif +#ifndef BIT6 +#define BIT6 0x00000040 +#endif +#ifndef BIT7 +#define BIT7 0x00000080 +#endif +#ifndef BIT8 +#define BIT8 0x00000100 +#endif +#ifndef BIT9 +#define BIT9 0x00000200 +#endif +#ifndef BIT10 +#define BIT10 0x00000400 +#endif +#ifndef BIT11 +#define BIT11 0x00000800 +#endif +#ifndef BIT12 +#define BIT12 0x00001000 +#endif +#ifndef BIT13 +#define BIT13 0x00002000 +#endif +#ifndef BIT14 +#define BIT14 0x00004000 +#endif +#ifndef BIT15 +#define BIT15 0x00008000 +#endif +#ifndef BIT16 +#define BIT16 0x00010000 +#endif +#ifndef BIT17 +#define BIT17 0x00020000 +#endif +#ifndef BIT18 +#define BIT18 0x00040000 +#endif +#ifndef BIT19 +#define BIT19 0x00080000 +#endif +#ifndef BIT20 +#define BIT20 0x00100000 +#endif +#ifndef BIT21 +#define BIT21 0x00200000 +#endif +#ifndef BIT22 +#define BIT22 0x00400000 +#endif +#ifndef BIT23 +#define BIT23 0x00800000 +#endif +#ifndef BIT24 +#define BIT24 0x01000000 +#endif +#ifndef BIT25 +#define BIT25 0x02000000 +#endif +#ifndef BIT26 +#define BIT26 0x04000000 +#endif +#ifndef BIT27 +#define BIT27 0x08000000 +#endif +#ifndef BIT28 +#define BIT28 0x10000000 +#endif +#ifndef BIT29 +#define BIT29 0x20000000 +#endif +#ifndef BIT30 +#define BIT30 0x40000000 +#endif +#ifndef BIT31 +#define BIT31 0x80000000 +#endif + + // + // Define a Memory Region that will allow access to the HDA PCI Configur= ation Space + // + OperationRegion(HDAR, PCI_Config, 0x00, 0x100) + Field(HDAR,WordAcc,NoLock,Preserve) { + VDID,32, // 0x00, VID DID + Offset(0x48), // 0x48, CGCTL - Clock Gating Control + ,6, + MBCG,1, // MISCBDCGE [BIT6] + Offset(0x54), // 0x54, Power Management Control and Status Register + ,8, + PMEE,1, + ,6, + PMES,1 // PME Status + } + + Name(_S0W, 3) // Device can wake itself from D3 in S0 + + Method(_DSW, 3) { Store(Arg0, PMEE) } // Device wake enable + + + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // Can wakeup from S4 state + + // GPE handler for HDA, this is part of _Lxx handler for bus 0 PME + Method(GPEH) { + If(LEqual(VDID, 0xFFFFFFFF)) { + Return() + } + + If(LAnd(PMEE, PMES)) { + ADBG("HDAS GPEH") + Store(1, PMES) // clear PME Status + Notify(CAVS, 0x02) + } + } + + // NHLT Table memory descriptor, returned from _DSM + Name(NBUF, ResourceTemplate () { + // NHLT table address (_MIN =3D NHLT 64bit pointer, _MAX =3D _MIN + _L= EN - 1) and length (_LEN) + QWordMemory (ResourceConsumer, , MinNotFixed, MaxNotFixed, NonCacheabl= e, ReadOnly, + 0x1, // AddressGranularity + 0x0000000000000000, // AddressMinimum _MIN + 0x0000000000000000, // AddressMaximum _MAX + 0x0, + 0x0, // RangeLength _LEN + , , NHLT, AddressRangeACPI,) + }) + + Method(AUWA,0,Serialized) + { + If(LEqual(PCHS, 1)) { + If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-= H A0 stepping (RevID =3D 0x0) + } else { + If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-LP= A0 stepping (RevID =3D 0x0) + If(LEqual(\_SB.PC00.LPC0.CRID, 0x1)) { Return (1) } // Apply to SPT-LP= A1 stepping (RevID =3D 0x1) + If(LEqual(\_SB.PC00.LPC0.CRID, 0x9)) { Return (1) } // Apply to SPT-LP= A2 stepping (RevID =3D 0x9) + } + Return (0) + } + + Method(_INI) { + // Update resource according to NVS + ADBG("HDAS _INI") + + // Set NHLT base address and length + CreateQWordField(NBUF, ^NHLT._MIN, NBAS) + CreateQWordField(NBUF, ^NHLT._MAX, NMAS) + CreateQWordField(NBUF, ^NHLT._LEN, NLEN) + Store(NHLA, NBAS) + Add(NHLA, Subtract(NHLL, 1), NMAS) + Store(NHLL, NLEN) + + If(LEqual(AUWA(), 1)) { + Store(0, \_SB.PC00.CAVS.MBCG) + } + } + + Method(_DSM, 0x4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, P= kgObj}) { + // Arg0 - UUID: A69F886E-6CEB-4594-A41F-7B5DCE24C553 (Buffer) + // Arg1 - Revision ID: 0x01 (Integer) + // Arg2 - Function Index: 0x0 - 0x3 (Integer) - See below for details. + // Arg3 - Depends on Function Index - See below for details. + // Return - Depends on Function Index - See below for details. + + ADBG("HDAS _DSM") + + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } + + // Verify UUID + If (LEqual(Arg0, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))) { + + Switch(ToInteger(Arg2)) { + + // Function 0: Function Support Query + // Arg2 - Function Index: 0x00 (Integer) + // Arg3: Unused + // Return: Bitmask of functions supported. (Buffer) + Case(0) { + // Supports function 0 - 3 + Return(Buffer(One) { 0x0F }) + } + + // Function 1: Query Non HD Audio Descriptor Table + // Used by the Intel Offload Engine Driver = to discover the + // non HD Audio devices supported by the Au= dio DSP. + // Arg2 - Function Index: 0x01 (Integer) + // Arg3 - Unused + // Return - ACPI Table describing the non HD Audio links and d= evices supported by the ADSP (ResourceBuffer) + Case(1) { + ADBG("_DSM Fun 1 NHLT") + // NBUF - Memory Resource Descriptor buffer with address and= length of NHLT + Return(NBUF) + } + + // Function 2: Query Feature Mask + // Used by the Intel Offload Engine Driver = to retrieve a bitmask + // of features allowable on this platform. + // Arg2 - Function Index: 0x02 (Integer) + // Arg3: Unused + // Return: Bitmask of supported features. + Case (2) { + ADBG("_DSM Fun 2 FMSK") + // Bit 0 =3D=3D '1', WoV is supported, Bit 0 =3D=3D '0', WoV= not supported + // Bit 1 =3D=3D '1', BT Sideband is supported, Bit 1 =3D=3D = '0', BT not supported + // Bit 2 =3D=3D '1', codec based VAD support allowable + // Bit 3 - 4 Reserved + // Bit 5 =3D=3D '1', BT Intel HFP SCO is supported + // Bit 6 =3D=3D '1', BT Intel A2DP is supported + // Bit 7 =3D=3D '1', DSP based speech pre-processing disabled + // Bit 8 =3D=3D '1', Windows Voice Activation, Bit 8 =3D=3D = '0', Intel Wake on Voice + // Bit 9 - 31 Reserved, shall be set to '0' + // ADFM - NVS AudioDSP Feature Bit Mask updated from PchPoli= cy + Return(ADFM) + } + + // Function 3: Query Pre/Post Processing Module Support + // Used by the Intel Offload Engine Driver = to determine if a + // specified PP Module is allowed to be sup= ported on this platform + // Arg2 - Function Index: 0x03 (Integer) + // Arg3 - UUID: Specifies the UUID of the PP module to check (= Buffer) + // Return - TRUE if PP Module supported, else FALSE. + Case (3) { + ADBG("_DSM Fun 3 PPMS") + // ADPM - NVS AudioDSP Post-Processing Module Bit Mask updat= ed from PchPolicy: HdaConfig->DspPpModuleMask + + // + // Example (to be updated with real GUIDs of supported 3rd p= arty IP): + // + // 3rd Party DSP Processing Module 1 placeholder (enabled by= policy HdaConfig->DspPpModuleMask |=3D BIT0) + // Check PP module with GUID AABBCCDD-EEFF-1122-3344-5566778= 89900 + // If (LEqual(Arg3, ToUUID ("AABBCCDD-EEFF-1122-3344-5566778= 89900"))){ + // Return(And(ADPM, 0x1)) // DspPpModuleMask[BIT0] / ADPM[= BIT0] set - supported 3rd Party Processing Module 1(return true) + // } + // + // 3rd Party DSP Processing Module 5 placeholder (enabled by= policy HdaConfig->DspPpModuleMask |=3D BIT5) + // Check PP module with GUID 11111111-2222-3333-4444-AABBCCD= DEEFF + // If (LEqual(Arg3, ToUUID ("11111111-2222-3333-4444-AABBCCD= DEEFF"))){ + // Return(And(ADPM, 0x20)) // DspPpModuleMask[BIT5] / ADPM= [BIT5] set - supported 3rd Party Processing Module 5(return true) + // } + // + // Implement for all supported PP modules + // + Return(0) // Is not supported + } + + Default { + // Function not supported (Arg2) + ADBG("_DSM Fun NOK") + Return(Buffer(One) { 0x00 }) + } + } // Switch(Arg2) End + } // If(Arg0, UUID) End + + + // UUID not supported (Arg0) + ADBG("_DSM UUID NOK") + //Fix warning: not all control paths return a value + Return(0) + } // _DSM End + +} // end "High Definition Audio Controller" diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchH= eci.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchHeci= .asl new file mode 100644 index 0000000000..e428b964f3 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchHeci.asl @@ -0,0 +1,22 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope(\_SB.PCI0) { + // + // Management Engine Interface 1 - Device 22, Function 0 + // + Device(HECI) { + Name(_ADR, 0x00160000) + + Method(_DSM, 0x4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntO= bj, PkgObj}) { + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } + //Fix warning: not all control paths return a value + Return(0) + } // End _DSM + } // Device(HECI) +} + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchI= sh.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchIsh.a= sl new file mode 100644 index 0000000000..6786b0b6e0 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchIsh.asl @@ -0,0 +1,21 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope(\_SB.PCI0) { + // + // Integrated Sensor Hub (PCI Mode) - Device 19, Function 0 + // + Device(ISHD) { + Name(_ADR, 0x00130000) + + Method(_DSM, 0x4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntO= bj, PkgObj}) { + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } + //Fix warning: not all control paths return a value + Return(0) + } // End _DSM + } // Device(ISHD) +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchN= vs.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchNvs.a= sl new file mode 100644 index 0000000000..f9803f328f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchNvs.asl @@ -0,0 +1,270 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // + // Define PCH NVS Area operatino region. + // + + + + OperationRegion(PNVA,SystemMemory,PNVB,PNVL) + Field(PNVA,AnyAcc,Lock,Preserve) + { + Offset(0), RCRV, 32, // Offset(0), RC Revision + Offset(4), PCHS, 16, // Offset(4), PCH Series + Offset(6), PCHG, 16, // Offset(6), PCH Generation + Offset(8), RPA1, 32, // Offset(8), Root Port address 1 + Offset(12), RPA2, 32, // Offset(12), Root Port address 2 + Offset(16), RPA3, 32, // Offset(16), Root Port address 3 + Offset(20), RPA4, 32, // Offset(20), Root Port address 4 + Offset(24), RPA5, 32, // Offset(24), Root Port address 5 + Offset(28), RPA6, 32, // Offset(28), Root Port address 6 + Offset(32), RPA7, 32, // Offset(32), Root Port address 7 + Offset(36), RPA8, 32, // Offset(36), Root Port address 8 + Offset(40), RPA9, 32, // Offset(40), Root Port address 9 + Offset(44), RPAA, 32, // Offset(44), Root Port address 10 + Offset(48), RPAB, 32, // Offset(48), Root Port address 11 + Offset(52), RPAC, 32, // Offset(52), Root Port address 12 + Offset(56), RPAD, 32, // Offset(56), Root Port address 13 + Offset(60), RPAE, 32, // Offset(60), Root Port address 14 + Offset(64), RPAF, 32, // Offset(64), Root Port address 15 + Offset(68), RPAG, 32, // Offset(68), Root Port address 16 + Offset(72), RPAH, 32, // Offset(72), Root Port address 17 + Offset(76), RPAI, 32, // Offset(76), Root Port address 18 + Offset(80), RPAJ, 32, // Offset(80), Root Port address 19 + Offset(84), RPAK, 32, // Offset(84), Root Port address 20 + Offset(88), NHLA, 64, // Offset(88), HD-Audio NHLT ACPI address + Offset(96), NHLL, 32, // Offset(96), HD-Audio NHLT ACPI length + Offset(100), ADFM, 32, // Offset(100), HD-Audio DSP Feature Mask + Offset(104), SBRG, 32, // Offset(104), SBREG_BAR + Offset(108), GPEM, 32, // Offset(108), GPP_X to GPE_DWX mapping + Offset(112), G2L0, 32, // Offset(112), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 0) + Offset(116), G2L1, 32, // Offset(116), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 1) + Offset(120), G2L2, 32, // Offset(120), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 2) + Offset(124), G2L3, 32, // Offset(124), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 3) + Offset(128), G2L4, 32, // Offset(128), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 4) + Offset(132), G2L5, 32, // Offset(132), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 5) + Offset(136), G2L6, 32, // Offset(136), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 6) + Offset(140), G2L7, 32, // Offset(140), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 7) + Offset(144), G2L8, 32, // Offset(144), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 8) + Offset(148), G2L9, 32, // Offset(148), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 9) + Offset(152), G2LA, 32, // Offset(152), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 10) + Offset(156), G2LB, 32, // Offset(156), GPE 2-tier level edged enabl= ed Gpio pads (Group Index 11) + Offset(160), G2LC, 32, // Offset(160), GPE 2-tier level edged enabl= ed Gpio pads (Groip Index 12) + + Offset(164), PML1, 16, // Offset(164), PCIE LTR max snoop Latency 1 + Offset(166), PML2, 16, // Offset(166), PCIE LTR max snoop Latency 2 + Offset(168), PML3, 16, // Offset(168), PCIE LTR max snoop Latency 3 + Offset(170), PML4, 16, // Offset(170), PCIE LTR max snoop Latency 4 + Offset(172), PML5, 16, // Offset(172), PCIE LTR max snoop Latency 5 + Offset(174), PML6, 16, // Offset(174), PCIE LTR max snoop Latency 6 + Offset(176), PML7, 16, // Offset(176), PCIE LTR max snoop Latency 7 + Offset(178), PML8, 16, // Offset(178), PCIE LTR max snoop Latency 8 + Offset(180), PML9, 16, // Offset(180), PCIE LTR max snoop Latency 9 + Offset(182), PMLA, 16, // Offset(182), PCIE LTR max snoop Latency 10 + Offset(184), PMLB, 16, // Offset(184), PCIE LTR max snoop Latency 11 + Offset(186), PMLC, 16, // Offset(186), PCIE LTR max snoop Latency 12 + Offset(188), PMLD, 16, // Offset(188), PCIE LTR max snoop Latency 13 + Offset(190), PMLE, 16, // Offset(190), PCIE LTR max snoop Latency 14 + Offset(192), PMLF, 16, // Offset(192), PCIE LTR max snoop Latency 15 + Offset(194), PMLG, 16, // Offset(194), PCIE LTR max snoop Latency 16 + Offset(196), PMLH, 16, // Offset(196), PCIE LTR max snoop Latency 17 + Offset(198), PMLI, 16, // Offset(198), PCIE LTR max snoop Latency 18 + Offset(200), PMLJ, 16, // Offset(200), PCIE LTR max snoop Latency 19 + Offset(202), PMLK, 16, // Offset(202), PCIE LTR max snoop Latency 20 + Offset(204), PNL1, 16, // Offset(204), PCIE LTR max no snoop Latenc= y 1 + Offset(206), PNL2, 16, // Offset(206), PCIE LTR max no snoop Latenc= y 2 + Offset(208), PNL3, 16, // Offset(208), PCIE LTR max no snoop Latenc= y 3 + Offset(210), PNL4, 16, // Offset(210), PCIE LTR max no snoop Latenc= y 4 + Offset(212), PNL5, 16, // Offset(212), PCIE LTR max no snoop Latenc= y 5 + Offset(214), PNL6, 16, // Offset(214), PCIE LTR max no snoop Latenc= y 6 + Offset(216), PNL7, 16, // Offset(216), PCIE LTR max no snoop Latenc= y 7 + Offset(218), PNL8, 16, // Offset(218), PCIE LTR max no snoop Latenc= y 8 + Offset(220), PNL9, 16, // Offset(220), PCIE LTR max no snoop Latenc= y 9 + Offset(222), PNLA, 16, // Offset(222), PCIE LTR max no snoop Latenc= y 10 + Offset(224), PNLB, 16, // Offset(224), PCIE LTR max no snoop Latenc= y 11 + Offset(226), PNLC, 16, // Offset(226), PCIE LTR max no snoop Latenc= y 12 + Offset(228), PNLD, 16, // Offset(228), PCIE LTR max no snoop Latenc= y 13 + Offset(230), PNLE, 16, // Offset(230), PCIE LTR max no snoop Latenc= y 14 + Offset(232), PNLF, 16, // Offset(232), PCIE LTR max no snoop Latenc= y 15 + Offset(234), PNLG, 16, // Offset(234), PCIE LTR max no snoop Latenc= y 16 + Offset(236), PNLH, 16, // Offset(236), PCIE LTR max no snoop Latenc= y 17 + Offset(238), PNLI, 16, // Offset(238), PCIE LTR max no snoop Latenc= y 18 + Offset(240), PNLJ, 16, // Offset(240), PCIE LTR max no snoop Latenc= y 19 + Offset(242), PNLK, 16, // Offset(242), PCIE LTR max no snoop Latenc= y 20 + Offset(244), U0C0, 32, // Offset(244), SerialIo Hidden UART0 BAR 0 + Offset(248), U1C0, 32, // Offset(248), SerialIo Hidden UART1 BAR 0 + Offset(252), ADPM, 32, // Offset(252), HD-Audio DSP Post-Processing= Module Mask + Offset(256), XHPC, 8, // Offset(256), Number of HighSpeed ports im= plemented in XHCI controller + Offset(257), XRPC, 8, // Offset(257), Number of USBR ports impleme= nted in XHCI controller + Offset(258), XSPC, 8, // Offset(258), Number of SuperSpeed ports i= mplemented in XHCI controller + Offset(259), XSPA, 8, // Offset(259), Address of 1st SuperSpeed po= rt + Offset(260), HPTB, 32, // Offset(260), HPET base address + Offset(264), HPTE, 8, // Offset(264), HPET enable + //110-bytes large SerialIo block + Offset(265), SMD0, 8, // Offset(265), SerialIo controller 0 (sdma)= mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(266), SMD1, 8, // Offset(266), SerialIo controller 1 (i2c0)= mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(267), SMD2, 8, // Offset(267), SerialIo controller 2 (i2c1)= mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(268), SMD3, 8, // Offset(268), SerialIo controller 3 (spi0)= mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(269), SMD4, 8, // Offset(269), SerialIo controller 4 (spi1)= mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(270), SMD5, 8, // Offset(270), SerialIo controller 5 (ua00)= mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(271), SMD6, 8, // Offset(271), SerialIo controller 6 (ua01)= mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(272), SMD7, 8, // Offset(272), SerialIo controller 7 (shdc)= mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(273), SMD8, 8, // Offset(273), SerialIo controller 8 (shdc)= mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(274), SMD9, 8, // Offset(274), SerialIo controller 9 (shdc)= mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(275), SMDA, 8, // Offset(275), SerialIo controller A (shdc)= mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(276), SIR0, 8, // Offset(276), SerialIo controller 0 (sdma)= irq number + Offset(277), SIR1, 8, // Offset(277), SerialIo controller 1 (i2c0)= irq number + Offset(278), SIR2, 8, // Offset(278), SerialIo controller 2 (i2c1)= irq number + Offset(279), SIR3, 8, // Offset(279), SerialIo controller 3 (spi0)= irq number + Offset(280), SIR4, 8, // Offset(280), SerialIo controller 4 (spi1)= irq number + Offset(281), SIR5, 8, // Offset(281), SerialIo controller 5 (ua00)= irq number + Offset(282), SIR6, 8, // Offset(282), SerialIo controller 6 (ua01)= irq number + Offset(283), SIR7, 8, // Offset(283), SerialIo controller 7 (shdc)= irq number + Offset(284), SIR8, 8, // Offset(284), SerialIo controller 8 (shdc)= irq number + Offset(285), SIR9, 8, // Offset(285), SerialIo controller 9 (shdc)= irq number + Offset(286), SIRA, 8, // Offset(286), SerialIo controller A (shdc)= irq number + Offset(287), SB00, 32, // Offset(287), SerialIo controller 0 (sdma)= BAR0 + Offset(291), SB01, 32, // Offset(291), SerialIo controller 1 (i2c0)= BAR0 + Offset(295), SB02, 32, // Offset(295), SerialIo controller 2 (i2c1)= BAR0 + Offset(299), SB03, 32, // Offset(299), SerialIo controller 3 (spi0)= BAR0 + Offset(303), SB04, 32, // Offset(303), SerialIo controller 4 (spi1)= BAR0 + Offset(307), SB05, 32, // Offset(307), SerialIo controller 5 (ua00)= BAR0 + Offset(311), SB06, 32, // Offset(311), SerialIo controller 6 (ua01)= BAR0 + Offset(315), SB07, 32, // Offset(315), SerialIo controller 7 (shdc)= BAR0 + Offset(319), SB08, 32, // Offset(319), SerialIo controller 8 (shdc)= BAR0 + Offset(323), SB09, 32, // Offset(323), SerialIo controller 9 (shdc)= BAR0 + Offset(327), SB0A, 32, // Offset(327), SerialIo controller A (shdc)= BAR0 + Offset(331), SB10, 32, // Offset(331), SerialIo controller 0 (sdma)= BAR1 + Offset(335), SB11, 32, // Offset(335), SerialIo controller 1 (i2c0)= BAR1 + Offset(339), SB12, 32, // Offset(339), SerialIo controller 2 (i2c1)= BAR1 + Offset(343), SB13, 32, // Offset(343), SerialIo controller 3 (spi0)= BAR1 + Offset(347), SB14, 32, // Offset(347), SerialIo controller 4 (spi1)= BAR1 + Offset(351), SB15, 32, // Offset(351), SerialIo controller 5 (ua00)= BAR1 + Offset(355), SB16, 32, // Offset(355), SerialIo controller 6 (ua01)= BAR1 + Offset(359), SB17, 32, // Offset(359), SerialIo controller 7 (shdc)= BAR1 + Offset(363), SB18, 32, // Offset(363), SerialIo controller 8 (shdc)= BAR1 + Offset(367), SB19, 32, // Offset(367), SerialIo controller 9 (shdc)= BAR1 + Offset(371), SB1A, 32, // Offset(371), SerialIo controller A (shdc)= BAR1 + //end of SerialIo block + Offset(375), GPEN, 8, // Offset(375), GPIO enabled + Offset(376), SGIR, 8, // Offset(376), GPIO IRQ + Offset(377), NIT1, 8, // Offset(377), RST PCIe Storage Cycle Route= r#1 Interface Type + Offset(378), NIT2, 8, // Offset(378), RST PCIe Storage Cycle Route= r#2 Interface Type + Offset(379), NIT3, 8, // Offset(379), RST PCIe Storage Cycle Route= r#3 Interface Type + Offset(380), NPM1, 8, // Offset(380), RST PCIe Storage Cycle Route= r#1 Power Management Capability Pointer + Offset(381), NPM2, 8, // Offset(381), RST PCIe Storage Cycle Route= r#2 Power Management Capability Pointer + Offset(382), NPM3, 8, // Offset(382), RST PCIe Storage Cycle Route= r#3 Power Management Capability Pointer + Offset(383), NPC1, 8, // Offset(383), RST PCIe Storage Cycle Route= r#1 PCIe Capabilities Pointer + Offset(384), NPC2, 8, // Offset(384), RST PCIe Storage Cycle Route= r#2 PCIe Capabilities Pointer + Offset(385), NPC3, 8, // Offset(385), RST PCIe Storage Cycle Route= r#3 PCIe Capabilities Pointer + Offset(386), NL11, 16, // Offset(386), RST PCIe Storage Cycle Route= r#1 L1SS Capability Pointer + Offset(388), NL12, 16, // Offset(388), RST PCIe Storage Cycle Route= r#2 L1SS Capability Pointer + Offset(390), NL13, 16, // Offset(390), RST PCIe Storage Cycle Route= r#3 L1SS Capability Pointer + Offset(392), ND21, 8, // Offset(392), RST PCIe Storage Cycle Route= r#1 Endpoint L1SS Control Data2 + Offset(393), ND22, 8, // Offset(393), RST PCIe Storage Cycle Route= r#2 Endpoint L1SS Control Data2 + Offset(394), ND23, 8, // Offset(394), RST PCIe Storage Cycle Route= r#3 Endpoint L1SS Control Data2 + Offset(395), ND11, 32, // Offset(395), RST PCIe Storage Cycle Route= r#1 Endpoint L1SS Control Data1 + Offset(399), ND12, 32, // Offset(399), RST PCIe Storage Cycle Route= r#2 Endpoint L1SS Control Data1 + Offset(403), ND13, 32, // Offset(403), RST PCIe Storage Cycle Route= r#3 Endpoint L1SS Control Data1 + Offset(407), NLR1, 16, // Offset(407), RST PCIe Storage Cycle Route= r#1 LTR Capability Pointer + Offset(409), NLR2, 16, // Offset(409), RST PCIe Storage Cycle Route= r#2 LTR Capability Pointer + Offset(411), NLR3, 16, // Offset(411), RST PCIe Storage Cycle Route= r#3 LTR Capability Pointer + Offset(413), NLD1, 32, // Offset(413), RST PCIe Storage Cycle Route= r#1 Endpoint LTR Data + Offset(417), NLD2, 32, // Offset(417), RST PCIe Storage Cycle Route= r#2 Endpoint LTR Data + Offset(421), NLD3, 32, // Offset(421), RST PCIe Storage Cycle Route= r#3 Endpoint LTR Data + Offset(425), NEA1, 16, // Offset(425), RST PCIe Storage Cycle Route= r#1 Endpoint LCTL Data + Offset(427), NEA2, 16, // Offset(427), RST PCIe Storage Cycle Route= r#2 Endpoint LCTL Data + Offset(429), NEA3, 16, // Offset(429), RST PCIe Storage Cycle Route= r#3 Endpoint LCTL Data + Offset(431), NEB1, 16, // Offset(431), RST PCIe Storage Cycle Route= r#1 Endpoint DCTL Data + Offset(433), NEB2, 16, // Offset(433), RST PCIe Storage Cycle Route= r#2 Endpoint DCTL Data + Offset(435), NEB3, 16, // Offset(435), RST PCIe Storage Cycle Route= r#3 Endpoint DCTL Data + Offset(437), NEC1, 16, // Offset(437), RST PCIe Storage Cycle Route= r#1 Endpoint DCTL2 Data + Offset(439), NEC2, 16, // Offset(439), RST PCIe Storage Cycle Route= r#2 Endpoint DCTL2 Data + Offset(441), NEC3, 16, // Offset(441), RST PCIe Storage Cycle Route= r#3 Endpoint DCTL2 Data + Offset(443), NRA1, 16, // Offset(443), RST PCIe Storage Cycle Route= r#1 RootPort DCTL2 Data + Offset(445), NRA2, 16, // Offset(445), RST PCIe Storage Cycle Route= r#2 RootPort DCTL2 Data + Offset(447), NRA3, 16, // Offset(447), RST PCIe Storage Cycle Route= r#3 RootPort DCTL2 Data + Offset(449), NMB1, 32, // Offset(449), RST PCIe Storage Cycle Route= r#1 Endpoint unique MSI-X Table BAR + Offset(453), NMB2, 32, // Offset(453), RST PCIe Storage Cycle Route= r#2 Endpoint unique MSI-X Table BAR + Offset(457), NMB3, 32, // Offset(457), RST PCIe Storage Cycle Route= r#3 Endpoint unique MSI-X Table BAR + Offset(461), NMV1, 32, // Offset(461), RST PCIe Storage Cycle Route= r#1 Endpoint unique MSI-X Table BAR value + Offset(465), NMV2, 32, // Offset(465), RST PCIe Storage Cycle Route= r#2 Endpoint unique MSI-X Table BAR value + Offset(469), NMV3, 32, // Offset(469), RST PCIe Storage Cycle Route= r#3 Endpoint unique MSI-X Table BAR value + Offset(473), NPB1, 32, // Offset(473), RST PCIe Storage Cycle Route= r#1 Endpoint unique MSI-X PBA BAR + Offset(477), NPB2, 32, // Offset(477), RST PCIe Storage Cycle Route= r#2 Endpoint unique MSI-X PBA BAR + Offset(481), NPB3, 32, // Offset(481), RST PCIe Storage Cycle Route= r#3 Endpoint unique MSI-X PBA BAR + Offset(485), NPV1, 32, // Offset(485), RST PCIe Storage Cycle Route= r#1 Endpoint unique MSI-X PBA BAR value + Offset(489), NPV2, 32, // Offset(489), RST PCIe Storage Cycle Route= r#2 Endpoint unique MSI-X PBA BAR value + Offset(493), NPV3, 32, // Offset(493), RST PCIe Storage Cycle Route= r#3 Endpoint unique MSI-X PBA BAR value + Offset(497), , 8, // Offset(497), Flag indicating Exit Boot Se= rvice, to inform SMM + Offset(498), SXRB, 32, // Offset(498), Sx handler reserved MMIO base + Offset(502), SXRS, 32, // Offset(502), Sx handler reserved MMIO size + Offset(506), CIOE, 8, // Offset(506), Cio2 Device Enabled as ACPI = device + Offset(507), CIOI, 8, // Offset(507), Cio2 Interrupt Number + Offset(508), TAEN, 8, // Offset(508), Thermal Device Acpi mode ena= bled + Offset(509), TIRQ, 8, // Offset(509), Thermal Device IRQ number + Offset(510), XWMB, 32, // Offset(510), XHCI memory base address + Offset(514), EMH4, 8, // Offset(514), eMMC HS400 mode enabled + Offset(515), CSKU, 8, // Offset(515), CPU SKU + Offset(516), ITA0, 16, // Offset(516), + Offset(518), ITA1, 16, // Offset(518), + Offset(520), ITA2, 16, // Offset(520), + Offset(522), ITA3, 16, // Offset(522), + Offset(524), ITS0, 8, // Offset(524), + Offset(525), ITS1, 8, // Offset(525), + Offset(526), ITS2, 8, // Offset(526), + Offset(527), ITS3, 8, // Offset(527), + Offset(528), LTR1, 8, // Offset(528), Latency Tolerance Reporting = Enable + Offset(529), LTR2, 8, // Offset(529), Latency Tolerance Reporting = Enable + Offset(530), LTR3, 8, // Offset(530), Latency Tolerance Reporting = Enable + Offset(531), LTR4, 8, // Offset(531), Latency Tolerance Reporting = Enable + Offset(532), LTR5, 8, // Offset(532), Latency Tolerance Reporting = Enable + Offset(533), LTR6, 8, // Offset(533), Latency Tolerance Reporting = Enable + Offset(534), LTR7, 8, // Offset(534), Latency Tolerance Reporting = Enable + Offset(535), LTR8, 8, // Offset(535), Latency Tolerance Reporting = Enable + Offset(536), LTR9, 8, // Offset(536), Latency Tolerance Reporting = Enable + Offset(537), LTRA, 8, // Offset(537), Latency Tolerance Reporting = Enable + Offset(538), LTRB, 8, // Offset(538), Latency Tolerance Reporting = Enable + Offset(539), LTRC, 8, // Offset(539), Latency Tolerance Reporting = Enable + Offset(540), LTRD, 8, // Offset(540), Latency Tolerance Reporting = Enable + Offset(541), LTRE, 8, // Offset(541), Latency Tolerance Reporting = Enable + Offset(542), LTRF, 8, // Offset(542), Latency Tolerance Reporting = Enable + Offset(543), LTRG, 8, // Offset(543), Latency Tolerance Reporting = Enable + Offset(544), LTRH, 8, // Offset(544), Latency Tolerance Reporting = Enable + Offset(545), LTRI, 8, // Offset(545), Latency Tolerance Reporting = Enable + Offset(546), LTRJ, 8, // Offset(546), Latency Tolerance Reporting = Enable + Offset(547), LTRK, 8, // Offset(547), Latency Tolerance Reporting = Enable + Offset(548), OBF1, 8, // Offset(548), Optimized Buffer Flush and F= ill + Offset(549), OBF2, 8, // Offset(549), Optimized Buffer Flush and F= ill + Offset(550), OBF3, 8, // Offset(550), Optimized Buffer Flush and F= ill + Offset(551), OBF4, 8, // Offset(551), Optimized Buffer Flush and F= ill + Offset(552), OBF5, 8, // Offset(552), Optimized Buffer Flush and F= ill + Offset(553), OBF6, 8, // Offset(553), Optimized Buffer Flush and F= ill + Offset(554), OBF7, 8, // Offset(554), Optimized Buffer Flush and F= ill + Offset(555), OBF8, 8, // Offset(555), Optimized Buffer Flush and F= ill + Offset(556), OBF9, 8, // Offset(556), Optimized Buffer Flush and F= ill + Offset(557), OBFA, 8, // Offset(557), Optimized Buffer Flush and F= ill + Offset(558), OBFB, 8, // Offset(558), Optimized Buffer Flush and F= ill + Offset(559), OBFC, 8, // Offset(559), Optimized Buffer Flush and F= ill + Offset(560), OBFD, 8, // Offset(560), Optimized Buffer Flush and F= ill + Offset(561), OBFE, 8, // Offset(561), Optimized Buffer Flush and F= ill + Offset(562), OBFF, 8, // Offset(562), Optimized Buffer Flush and F= ill + Offset(563), OBFG, 8, // Offset(563), Optimized Buffer Flush and F= ill + Offset(564), OBFH, 8, // Offset(564), Optimized Buffer Flush and F= ill + Offset(565), OBFI, 8, // Offset(565), Optimized Buffer Flush and F= ill + Offset(566), OBFJ, 8, // Offset(566), Optimized Buffer Flush and F= ill + Offset(567), OBFK, 8, // Offset(567), Optimized Buffer Flush and F= ill + Offset(568), ECR1, 8, // Offset(568), External Change Request + Offset(569), AG1L, 64, // Offset(569), HDA PP module custom GUID 1 = - first 64bit [0-63] + Offset(577), AG1H, 64, // Offset(577), HDA PP module custom GUID 1 = - second 64bit [64-127] + Offset(585), AG2L, 64, // Offset(585), HDA PP module custom GUID 2 = - first 64bit [0-63] + Offset(593), AG2H, 64, // Offset(593), HDA PP module custom GUID 2 = - second 64bit [64-127] + Offset(601), AG3L, 64, // Offset(601), HDA PP module custom GUID 3 = - first 64bit [0-63] + Offset(609), AG3H, 64, // Offset(609), HDA PP module custom GUID 3 = - second 64bit [64-127] + Offset(617), MCFG, 32 // Offset(617), PcieMmCfgBaseAddress + } diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchP= cie.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchPcie= .asl new file mode 100644 index 0000000000..dc5454ab45 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchPcie.asl @@ -0,0 +1,202 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + OperationRegion(PXCS,PCI_Config,0x00,0x480) + Field(PXCS,AnyAcc, NoLock, Preserve) + { + Offset(0), + VDID, 32, + Offset(0x50), // LCTL - Link Control Register + L0SE, 1, // 0, L0s Entry Enabled + , 3, + LDIS, 1, + , 3, + Offset(0x52), // LSTS - Link Status Register + , 13, + LASX, 1, // 0, Link Active Status + Offset(0x5A), // SLSTS[7:0] - Slot Status Register + ABPX, 1, // 0, Attention Button Pressed + , 2, + PDCX, 1, // 3, Presence Detect Changed + , 2, + PDSX, 1, // 6, Presence Detect State + , 1, + Offset(0x60), // RSTS - Root Status Register + , 16, + PSPX, 1, // 16, PME Status + Offset(0xA4), + D3HT, 2, // Power State + Offset(0xD8), // MPC - Miscellaneous Port Configuration Register + , 30, + HPEX, 1, // 30, Hot Plug SCI Enable + PMEX, 1, // 31, Power Management SCI Enable + Offset(0xE2), // RPPGEN - Root Port Power Gating Enable + , 2, + L23E, 1, // 2, L23_Rdy Entry Request (L23ER) + L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT) + Offset(0x324), + , 3, + LEDM, 1, // PCIEDBG.DMIL1EDM + Offset(0x420), // Offset 420h: PCIEPMECTL - PCIe PM Extension Control + , 30, + DPGE, 1, // PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State P= HY Lane Power Gating Enable (DLSULPPGE): + } + Field(PXCS,AnyAcc, NoLock, WriteAsZeros) + { + Offset(0xDC), // SMSCS - SMI/SCI Status Register + , 30, + HPSX, 1, // 30, Hot Plug SCI Status + PMSX, 1 // 31, Power Management SCI Status + } + + + Name(LTRV, Package(){0,0,0,0}) + + // + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index (0 =3D Return Supported Functions) + // Arg3: Package Parameters + Method(_DSM, 4, Serialized) { + // + // Switch based on which unique function identifier was passed in + // + If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + // + // _DSM Definitions for Latency Tolerance Reporting + // + // Arguments: + // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D + // Arg1: Revision ID: 2 + // Arg2: Function Index: 1, 4 or 6 + // Arg3: Empty Package + // + // Return: + // A Package of four integers corresponding with the LTR encoding de= fined + // in the PCI Express Base Specification, as follows: + // Integer 0: Maximum Snoop Latency Scale + // Integer 1: Maximum Snoop Latency Value + // Integer 2: Maximum No-Snoop Latency Scale + // Integer 3: Maximum No-Snoop Latency Value + // These values correspond directly to the LTR Extended Capability S= tructure + // fields described in the PCI Express Base Specification. + // + // + // Switch by function index + // + Switch(ToInteger(Arg2)) { + // + // Function Index:0 + // Standard query - A bitmask of functions supported + // + Case (0) { + Name(OPTS,Buffer(2){0,0}) + CreateBitField(OPTS,0,FUN0) + CreateBitField(OPTS,4,FUN4) + CreateBitField(OPTS,6,FUN6) + CreateBitField(OPTS,8,FUN8) + CreateBitField(OPTS,9,FUN9) + + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + Store(1,FUN0) + if (LTRE){ + Store(1,Fun6) + } + if (OBFF){ + Store(1,Fun4) + } + if(LEqual(ECR1,1)){ + if (LGreaterEqual(Arg1, 3)){ // test Arg1 for Revision ID: 3 + Store(1,Fun8) + Store(1,Fun9) + } + } + } + Return (OPTS) + } + // + // Function Index: 4 + // + Case(4) { + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + if (OBFN){ + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,8,0,0,0,0}) // OBFF= capable, offset 4[08h] + } else { + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}) + } + } + } + // + // Function Index: 6 + // LTR Extended Capability Structure + // + Case(6) { + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + if (LTRN){ + if (LOr(LEqual(LMSL, 0),LEqual(LNSL, 0))) + { + if (LEqual (PCHS, SPTH)) { + Store (0x0846, LMSL) + Store (0x0846, LNSL) + } elseif (LEqual (PCHS, SPTL)) { + Store (0x1003, LMSL) + Store (0x1003, LNSL) + } + } + Store(And(ShiftRight(LMSL,10),7), Index(LTRV, 0)) + Store(And(LMSL,0x3FF), Index(LTRV, 1)) + Store(And(ShiftRight(LNSL,10),7), Index(LTRV, 2)) + Store(And(LNSL,0x3FF), Index(LTRV, 3)) + + Return (LTRV) + } else { + Return (0) + } + } + } + Case(8) { //ECR ACPI additions for FW latency optimizations, DSM f= or Avoiding Power-On Reset Delay Duplication on Sx Resume + if(LEqual(ECR1,1)){ + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3 + return (1) + } + } + } + Case(9) { //ECR ACPI additions for FW latency optimizations, DSM f= or Specifying Device Readiness Durations + if(LEqual(ECR1,1)){ + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3 + return(Package(5){50000,Ones,Ones,50000,Ones}) + } + } + } + } // End of switch(Arg2) + } // End of if + return (Buffer() {0x00}) + } // End of _DSM + + Device(PXSX) + { + Name(_ADR, 0x00000000) + + // NOTE: Any PCIE Hot-Plug dependency for this port is + // specific to the CRB. Please modify the code based on + // your platform requirements. + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } + + // + // PCI_EXP_STS Handler for PCIE Root Port + // + Method(HPME,0,Serialized) { + If(LAnd(LNotEqual(VDID,0xFFFFFFFF), LEqual(PMSX,1))) { //if port exist= s and has PME SCI Status set... + Notify (PXSX, 0x2) //notify child device; this will cause its driver= to clear PME_Status from device + Store(1,PMSX) // clear rootport's PME SCI status + Store(1,PSPX) // consume one pending PME notification to prevent it = from blocking the queue + } + } + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchR= stPcieStorage.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Ds= dt/PchRstPcieStorage.asl new file mode 100644 index 0000000000..fd8b5f33ba --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchRstPcieS= torage.asl @@ -0,0 +1,216 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define PCI_CARD_BASE_ADDR0 0x10 +#define PCI_CARD_BASE_ADDR1 0x14 +#define PCI_CARD_BASE_ADDR2 0x18 +#define PCI_CARD_BASE_ADDR3 0x1C +#define PCI_CARD_BASE_ADDR4 0x20 +#define PCI_CARD_BASE_ADDR5 0x24 + + //RST Pcie Storage Remapped Base Address Index Value + Name(PRBI, 0) + + //RST Pcie Storage Remapped Base Address Data Value + Name(PRBD, 0) + + //RST Pcie Storage Endpoint Command Data + Name(PCMD, 0) + + //RST Pcie Storage Cycle Router + Name(NCRN, 0) + + // + // Variables list to store corresponding value for different NVM device + // + Name(NITV, 0) // Interface Type + Name(NPMV, 0) // Power Management Capability Pointer + Name(NPCV, 0) // PCIe Capabilities Pointer + Name(NL1V, 0) // L1SS Capability Pointer + Name(ND2V, 0) // Endpoint L1SS Control Data2 + Name(ND1V, 0) // Endpoint L1SS Control Data1 + Name(NLRV, 0) // LTR Capability Pointer + Name(NLDV, 0) // Endpoint LTR Data + Name(NEAV, 0) // Endpoint LCTL Data + Name(NEBV, 0) // Endpoint DCTL Data + Name(NECV, 0) // Endpoint DCTL2 Data + Name(NRAV, 0) // RootPort DCTL2 Data + Name(NMBV, 0) // Endpoint unique MSI-X Table BAR + Name(NMVV, 0) // Endpoint unique MSI-X Table BAR value + Name(NPBV, 0) // Endpoint unique MSI-X PBA BAR + Name(NPVV, 0) // Endpoint unique MSI-X PBA BAR value + + Method(EPD0, 0, Serialized) // Put Remapped Device into D0 state + { + RDCA(NCRN,Add(NPMV,0x04),0xFFFFFFFC,0x0,ENDPOINT_WRITE) + } + + Method(EPD3, 0, Serialized) // Put Remapped Device into D3 state + { + RDCA(NCRN,Add(NPMV,0x04),0xFFFFFFFC,0x3,ENDPOINT_WRITE) + } + + // + // Restore of Remapped Device and Hidden Root Port + // This method is called after the endpoint is to be power ungated (D3-c= old to D0 unitialized) + // + Method(CNRS, 0, Serialized) + { + // + // Return if RST Pcie Storage Remapping is disabled + // + If(LEqual(NITV,0)) + { + Return(0) + } + + // + // Clear all BARs in Remapped Device + // + RDCA(NCRN,PCI_CARD_BASE_ADDR0,0x0,0x0,ENDPOINT_WRITE) + RDCA(NCRN,PCI_CARD_BASE_ADDR1,0x0,0x0,ENDPOINT_WRITE) + RDCA(NCRN,PCI_CARD_BASE_ADDR2,0x0,0x0,ENDPOINT_WRITE) + RDCA(NCRN,PCI_CARD_BASE_ADDR3,0x0,0x0,ENDPOINT_WRITE) + RDCA(NCRN,PCI_CARD_BASE_ADDR4,0x0,0x0,ENDPOINT_WRITE) + RDCA(NCRN,PCI_CARD_BASE_ADDR5,0x0,0x0,ENDPOINT_WRITE) + + // + // Restore Endpoint CMD and remapped BAR + // + RDCA(NCRN,0x4,0xFFFFFFF8,PCMD,ENDPOINT_WRITE) + RDCA(NCRN,PRBI,0x0,PRBD,ENDPOINT_WRITE) + + // + // Restore of Remapped Device L1 Substate if this Capability is suppor= ted + // + If(LNotEqual(NL1V,0)) + { + RDCA(NCRN,Add(NL1V,0x0C),0xFFFFFF00,ND2V,ENDPOINT_WRITE) + RDCA(NCRN,Add(NL1V,0x08),0x0000000F,And(ND1V,0xFFFFFFF0),ENDPOINT_WR= ITE) + RDCA(NCRN,Add(NL1V,0x08),0xFFFFFFFF,ND1V,ENDPOINT_WRITE) + } + + // + // Restore of Remapped Device LTR if this Capability is supported + // + If(LNotEqual(NLRV,0)) + { + RDCA(NCRN,Add(NLRV,0x04),0xFFFFFFFF,NLDV,ENDPOINT_WRITE) + } + + // + // Restore of Remapped Device Link Control's "Enable Clock Power Manag= ement" field and "Common Clock Configuration" field + // + RDCA(NCRN,Add(NPCV,0x10),0xFFFFFEBF,And(NEAV,0xFFFC),ENDPOINT_WRITE) + + // + // Restore of Remapped Device Device Control 2 field + // + RDCA(NCRN,Add(NPCV,0x28),0xFFFFFBFF,NECV,ENDPOINT_WRITE) + + // + // Restore of Remapped Device Device Control field + // + RDCA(NCRN,Add(NPCV,0x8),0xFFFFFF1F,NEBV,ENDPOINT_WRITE) + + // + // Restore of Hidden Root Port field + // + RDCA(NCRN,0x68,0xFFFFFBFF,NRAV,ROOTPORT_WRITE) + + // + // Check CCC bit + // If this bit is 1, perform link retrain by setting the "Retrain Link= " bit + // + If(LEqual(And(NEAV,0x40),0x40)) + { + RDCA(NCRN,0x50,0xFFFFFFDF,0x20,ROOTPORT_WRITE) + // + // Poll PCIe Link Active status till it is active + // + while(LEqual(And(RDCA(NCRN,0x52,0x0,0x0,ROOTPORT_READ),0x2000),0)) + { + Stall(10) + } + } + + // + // Restore of Remapped Device Link Control's "Active State Link PM Con= trol" field + // + RDCA(NCRN,Add(NPCV,0x10),0xFFFFFFFC,And(NEAV,0x0003),ENDPOINT_WRITE) + + // + // Restore of Remapped Device related device BAR for the MSI-X Table B= AR if the device supports unique MSI-X Table BAR + // + If(LNotEqual(NMVV,0)) + { + RDCA(NCRN,NMBV,0x0,NMVV,ENDPOINT_WRITE) + } + + // + // Restore of Remapped Device related device BAR for the MSI-X PBA BAR= if the device supports unique MSI-X PBA BAR + // + If(LNotEqual(NPVV,0)) + { + RDCA(NCRN,NPBV,0x0,NPVV,ENDPOINT_WRITE) + } + //Fix warning: not all control paths return a value + Return(0) + } + + Method(_PS3,0,Serialized) + { + // + // Return if RST Pcie Storage Remapping is disabled + // + If(LEqual(NITV,0)) + { + //Fix warning: restricted method should not return a value + + } + + // + // Store Endpoint CMD and remapped BAR for CNRS() restoration + // + Store(RDCA(NCRN,0x4,0x0,0x0,ENDPOINT_READ),PCMD) + If(LEqual(NITV,1)) // Store BAR5 if Endpoint is AHCI Interface + { + Store(0x24,PRBI) + Store(RDCA(NCRN,0x24,0x0,0x0,ENDPOINT_READ),PRBD) + } + ElseIf(LEqual(NITV,2)) // Store BAR0 if Endpoint is NVMe Interface + { + Store(0x10,PRBI) + Store(RDCA(NCRN,0x10,0x0,0x0,ENDPOINT_READ),PRBD) + } + + EPD3() + RPD3(NCRN) + } + + Method(_PS0,0,Serialized) + { + // + // Return if RST Pcie Storage Remapping is disabled + // + If(LEqual(NITV,0)) + { + //Fix warning: restricted method should not return a value + } + RPD0(NCRN) + EPD0() + + // + // Check NSR bit in PMCS + // If this bit is 0, invoke CNRS() to perform restoration on the remap= ped device and hidden root port + // + Store(RDCA(NCRN,Add(NPMV,0x04),0x0,0x0,ENDPOINT_READ),Local0) + If(LEqual(And(Local0,0x8),0)) + { + CNRS() + } + } diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchS= ata.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchSata= .asl new file mode 100644 index 0000000000..de60a98c01 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchSata.asl @@ -0,0 +1,221 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define ROOTPORT_READ 0 +#define ROOTPORT_WRITE 1 +#define ENDPOINT_READ 2 +#define ENDPOINT_WRITE 3 + +// +// SDSM is Device Specific Method supporting AHCI DEVSLP +// It is not guaranteed to be available on every boot +// +// move one level up to Pch.asl + + Method(_DSM,4,serialized){ + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; + if(CondRefOf(\_SB.PC00.SAT0.SDSM)) { return (\_SB.PC00.SAT0.SDSM(Arg= 0,Arg1,Arg2,Arg3)) }; + return(0) + } + + Device(PRT0) + { + Name(_ADR,0x0000FFFF) // Port 0 + } + Device(PRT1) + { + Name(_ADR,0x0001FFFF) // Port 1 + } + Device(PRT2) + { + Name(_ADR,0x0002FFFF) // Port 2 + } + Device(PRT3) + { + Name(_ADR,0x0003FFFF) // Port 3 + } + Device(PRT4) + { + Name(_ADR,0x0004FFFF) // Port 4 + } + Device(PRT5) + { + Name(_ADR,0x0005FFFF) // Port 5 + } + + // + // Method to perform RST PCIe Storage Remapping read or write access t= o the remapped device / hidden root port configuration space + // This method takes 5 parameters as below: + // Arg0 - RST PCIe Storage Cycle Router# + // Arg1 - PCI Offset + // Arg2 - WriteData (AndMask) + // Arg3 - WriteData (OrMask) + // Arg4 - Access Methods: ROOTPORT_READ, ROOTPORT_WRITE, ENDPOINT_READ= , ENDPOINT_WRITE + // + Method(RDCA, 5, Serialized) + { + // + // Operation Region for Sata Extended Config Space for Hidden Root P= ort Access + // + OperationRegion(RPAL, SystemMemory, Add(\_SB.PC00.GPCB(), Add(0xB810= 0,Arg1)), 0x4) + Field(RPAL,DWordAcc,Lock,Preserve) + { + RPCD, 32, + } + + // + // Operation Region for Endpoint Index-Data Pair for Remapped Device= Access + // + OperationRegion(EPAC, SystemMemory, Add(\_SB.PC00.GPCB(),0xB8308), 0= x8) + Field(EPAC,DWordAcc,Lock,Preserve) + { + CAIR, 32, + CADR, 32, + } + + // + // Operation Region for RST PCIe Storage Cycle Router Global configu= ration registers + // + OperationRegion(NCRG, SystemMemory, Add(\_SB.PC00.GPCB(),0xB8FC0), 0= x4) + Field(NCRG,DWordAcc,Lock,Preserve) + { + CRGC, 32, + } + + If (LGreater(Arg0, 2)) // Return if RST PCIe Storage Cycle Route= r# is invalid + { + Return(0) + } + Else // Set RST PCIe Storage Cycle Router Acce= ssibility based on Arg0 - RST PCIe Storage Cycle Router# + { + Store(Arg0,CRGC) + } + + Switch(ToInteger(Arg4)) + { + Case(ROOTPORT_READ) // Read access to the Hidden Root Port + { + Return(RPCD) + } + Case(ENDPOINT_READ) // Read access to the Remapped Device + { + Store(Arg1,CAIR) + Return(CADR) + } + Case(ROOTPORT_WRITE) // Write access to the Hidden Root Port + { + And(Arg2,RPCD,Local0) + Or(Arg3,Local0,Local0) + Store(Local0,RPCD) + } + Case(ENDPOINT_WRITE) // Write access to the Remapped Device + { + Store(Arg1,CAIR) + And(Arg2,CADR,Local0) + Or(Arg3,Local0,Local0) + Store(Local0,CADR) + } + Default + { + Return(0) + } + } + //Fix warning: not all control paths return a value + Return(0) + } + + Method(RPD0, 1, Serialized) // Put Hidden Root Port into D0 state + { + RDCA(Arg0,0xA4,0xFFFFFFFC,0x0,ROOTPORT_WRITE) + } + + Method(RPD3, 1, Serialized) // Put Hidden Root Port into D3 state + { + RDCA(Arg0,0xA4,0xFFFFFFFC,0x3,ROOTPORT_WRITE) + } + + Device(NVM1) + { + Name(_ADR,0x00C1FFFF) + + Include("PchRstPcieStorage.asl") + Method(_INI) + { + Store (NIT1, NITV) + Store (NPM1, NPMV) + Store (NPC1, NPCV) + Store (NL11, NL1V) + Store (ND21, ND2V) + Store (ND11, ND1V) + Store (NLR1, NLRV) + Store (NLD1, NLDV) + Store (NEA1, NEAV) + Store (NEB1, NEBV) + Store (NEC1, NECV) + Store (NRA1, NRAV) + Store (NMB1, NMBV) + Store (NMV1, NMVV) + Store (NPB1, NPBV) + Store (NPV1, NPVV) + Store (0, NCRN) + } + } + + Device(NVM2) + { + Name(_ADR,0x00C2FFFF) + + Include("PchRstPcieStorage.asl") + Method(_INI) + { + Store (NIT2, NITV) + Store (NPM2, NPMV) + Store (NPC2, NPCV) + Store (NL12, NL1V) + Store (ND22, ND2V) + Store (ND12, ND1V) + Store (NLR2, NLRV) + Store (NLD2, NLDV) + Store (NEA2, NEAV) + Store (NEB2, NEBV) + Store (NEC2, NECV) + Store (NRA2, NRAV) + Store (NMB2, NMBV) + Store (NMV2, NMVV) + Store (NPB2, NPBV) + Store (NPV2, NPVV) + Store (1, NCRN) + } + } + + Device(NVM3) + { + Name(_ADR,0x00C3FFFF) + + Include("PchRstPcieStorage.asl") + Method(_INI) + { + Store (NIT3, NITV) + Store (NPM3, NPMV) + Store (NPC3, NPCV) + Store (NL13, NL1V) + Store (ND23, ND2V) + Store (ND13, ND1V) + Store (NLR3, NLRV) + Store (NLD3, NLDV) + Store (NEA3, NEAV) + Store (NEB3, NEBV) + Store (NEC3, NECV) + Store (NRA3, NRAV) + Store (NMB3, NMBV) + Store (NMV3, NMVV) + Store (NPB3, NPBV) + Store (NPV3, NPVV) + Store (2, NCRN) + } + } + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchS= cs.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchScs.a= sl new file mode 100644 index 0000000000..04ec0e7fe6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchScs.asl @@ -0,0 +1,8 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// Storage and Communication Subsystems definitions is not supported in Se= rver diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchS= erialIo.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/Pch= SerialIo.asl new file mode 100644 index 0000000000..72ed66a159 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchSerialIo= .asl @@ -0,0 +1,7 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchX= dci.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchXdci= .asl new file mode 100644 index 0000000000..229c861af6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchXdci.asl @@ -0,0 +1,8 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + //XDCI is not used in Server diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchX= hci.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchXhci= .asl new file mode 100644 index 0000000000..f61dc99c0f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/PchXhci.asl @@ -0,0 +1,557 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +External(\_SB.PC00.XHCI.PS0X, MethodObj) +External(\_SB.PC00.XHCI.PS3X, MethodObj) +External(\_SB.PC00.XHCI.RHUB.PS0X, MethodObj) +External(\_SB.PC00.XHCI.RHUB.PS2X, MethodObj) +External(\_SB.PC00.XHCI.RHUB.PS3X, MethodObj) +External(\_SB.PC00.XHCI.RHUB.INIR, MethodObj) + +Scope(\_SB_.PC00.XHCI) { + + OperationRegion(XPRT,PCI_Config,0x00,0x100) + Field(XPRT,AnyAcc,NoLock,Preserve) + { + DVID, 16, + Offset(0x74), + D0D3, 2, // 0x74 BIT[1:0] + , 6, + PMEE, 1, // PME Enable + , 6, + PMES, 1, // PME Status + Offset(0xA8), // SSCFG Reg for WPTLP + , 13, + MW13, 1, // 0xA8 BIT[13] + MW14, 1, // 0xA8 BIT[14] + , 17, + Offset(0xB0), // SSCFG Reg for LPTLP + , 13, + MB13, 1, // 0xB0 BIT[13] + MB14, 1, // 0xB0 BIT[14] + , 17, + Offset(0xD0), + PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register. + PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register. + PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register. + PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register + } + + // + // Variable to store the maximum D state supported in S0. + // + Name (XFLT, 0) + // + // XHCI controller won't go into D3Hot during S0 until _DSM method is = evaluated by filter driver. + // + Method(_DSM,4,serialized){ + If(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } + // + // Check GUID ac340cb7-e901-45bf-b7e6-2b34ec931e23 + // + If(LEqual(Arg0, Buffer(0x10) { 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0= xbf, 0x45, 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23 })) + { + // + // Only Supported value is "0x3" + // + If(LEqual(Arg1, 0x3)) + { + Store(Arg1,XFLT) + } + } + return(0) + } + + Method(_S3D, 0, NotSerialized) + { + Return(3) + } + Method(_S4D, 0, NotSerialized) + { + Return(3) + } + Method(_S3W, 0, NotSerialized) + { + Return(3) + } + Method(_S4W, 0, NotSerialized) + { + Return(3) + } + + // + // Once the filter driver is installed, D3 is allowed. + // + Method(_S0W, 0x0, NotSerialized) + { + If(LEqual(XFLT, Zero)) + { + Return(0x0) + } + Else + { + Return(0x3) + } + } + + Method(_PRW, 0) + { + Return(GPRW(0x6D, 4)) // can wakeup from S4 state + } + + Method(_DSW, 3) + { + Store(Arg0, PMEE) + } + + Method(_INI) { + // _INI for RTD3 run conditionally if implemented in platform specif= ic code + If(CondRefOf(\_SB.PC00.XHCI.RHUB.INIR)) { // _INI for RTD3 + \_SB.PC00.XHCI.RHUB.INIR() + } + } + + // + // GPE handler for XHCI, this is part of _Lxx handler for bus 0 PME + // + Method(GPEH) + { + If(LEqual(DVID, 0xFFFF)) { + Return() + } + Store(PMES, Local0) + Store(1, PMES) // clear PME Status + If(LAnd(PMEE, Local0)) { + Notify(XHCI, 0x02) + } + } + + OperationRegion(XHCP, SystemMemory, Add(\_SB.PC00.GPCB(), 0xA0000), 0x= 100) + Field(XHCP,AnyAcc,Lock,Preserve) + { + Offset(0x4), + PDBM, 16, + Offset(0x10), + MEMB, 64 + } + + // + // USRA (USbR port Address), method for calculating address of first U= SBR port in XHCI controller + // + Method(USRA,0,Serialized) { + If(LEqual(PCHV, SPTH)) { // SPT-H + Return (15) + } Else { // SPT-LP + Return (11) + } + } + + // + // SSPA (SuperSpeed Port Address), method for calculating address of f= irst SS port in XHCI controller + // + Method(SSPA,0,Serialized) { + If(LEqual(PCHV, SPTH)) { // SPT-H + Return (17) + } Else { // SPT-LP + Return (13) + } + } + + Name(XRST, Zero) + + Method(_PS0,0,Serialized) + { + + If(LEqual(^DVID,0xFFFF)) + { + Return() + } + + Store(^MEMB,Local2) // Save MBAR + Store(^PDBM,Local1) // Save CMD + + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME + + // + // Switch to D0 + // + Store(0,^D0D3) + + Store(\XWMB,^MEMB) // Set MBAR + Or(Local1,0x0002,^PDBM) // Set MSE + + // + // + // + + And(^PDBM,Not(0x02),^PDBM) // Clear MSE + + Store(Local2,^MEMB) // Restore MBAR + Store(Local1,^PDBM) // Restore CMD + + // + // Call platform XHC PS0 method if present + // + If(CondRefOf(\_SB.PC00.XHCI.PS0X)) + { + \_SB.PC00.XHCI.PS0X() + } + // + // + If(LAnd(UWAB,LEqual(D0D3,0))) { + + // + // If the USB WA Bit is set and any XHCI or XDCI controller is i= n D0 + // + // + // USB2 PHPY Power Gating - SW WA + // + // 1. BIOS writes a new command to the MTPMC register to cause t= he PMC to disable power gating + Store(1,MPMC) + + // 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0 + // In parallel and in response to the previous command from= BIOS, PMC FW will: + // * Make the USB2 force common lane PG match the BIOS p= olicy (common lane PG disallowed) + // * Disable SUS power gating in XHCI + // * Wait for USB2 PHY side_pok to be 1 + // * Disable core power gating in USB2 PHY + // * Disable common lane power gating in USB2 PHY (proba= bly not necessary, consider removal) + // * Wait for USB2 SUS restoration status to be set, and= do USB2 SUS power gating restoration + // * Get the PHY in the correct state before allowing tr= ansition to D0. + // * Clear MSG_FULL_STS + // BIOS sees MSG_FULL_STS clear and exits the method + // + While(PMFS) { + Sleep(10) + } + } // End If(UWAB) + + } + + Method(_PS3,0,Serialized) + { + + If(LEqual(^DVID,0xFFFF)) + { + Return() + } + + Store(^MEMB,Local2) // Save MBAR + Store(^PDBM,Local1) // Save CMD + + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME + + // + // Switch back to D0 + // + Store(0,^D0D3) + + Store(\XWMB,^MEMB) // Set MBAR + Or(Local1,0x0002,^PDBM) // Set MSE + + // + // + // + + And(^PDBM,Not(0x02),^PDBM) // Clear MSE + + // + // Switch back to D3 + // + Store(3,^D0D3) + + Store(Local2,^MEMB) // Restore MBAR + Store(Local1,^PDBM) // Restore CMD + + // + // Call platform XHC PS3 method if present + // + If(CondRefOf(\_SB.PC00.XHCI.PS3X)) + { + \_SB.PC00.XHCI.PS3X() + } + If(LAnd(UWAB,LEqual(D0D3,3))) { + // + // If the USB WA Bit is set and XHCI is in D3 + // + + // 1. BIOS writes a new command to the MTPMC register to enable = power gating + Store(3,MPMC) + + // 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0 + // In parallel and in response to the previous command from= BIOS, PMC FW will: + // * Make the USB2 force common lane PG match the BIOS po= licy (common lane PG allowed) + // * Enable SUS power gating in XHCI + // * Enable core power gating in USB2 PHY + // * Enable common lane power gating in the USB2 PHY + // * Clear MSG_FULL_STS + // BIOS sees MSG_FULL_STS clear and exits the method + // + While(PMFS) { + Sleep(10) + } + } // End If(UWAB) + } + + + // Apply S3 workaround. + // Arguments : + // None + // Changes 8090 Bit 10 before S3. + // + Method(XHCS,0, Serialized) { + Store(^MEMB,Local2) // Save MBAR + Store(^PDBM,Local1) // Save CMD + + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME + + Store(\XWMB,^MEMB) // Set MBAR + Or(Local1,0x0002,^PDBM) // Set MSE + + OperationRegion(MC11,SystemMemory,\XWMB,0x9000) + Field(MC11,DWordAcc,Lock,Preserve) + { + Offset(0x8090), // HC Transfer Manager - TRM + , 10, + UCLI, 1, // CLEAR IN EP + } + + Store(0x1,UCLI) + + And(^PDBM,Not(0x02),^PDBM) // Clear MSE + + Store(Local2,^MEMB) // Restore MBAR + Store(Local1,^PDBM) // Restore CMD + + } + + // + // + // Check for XHCI switch UUID + // + // Arguments: + // Arg0 (Buffer) : UUID + // + // Returns: + // 1: It's valid UUID + // 0: Invalid UUID + // + Method(CUID,1,Serialized) { + If(LEqual(Arg0,ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) { + Return(1) + } + Return(0) + } + + Device(RHUB) + { + Name(_ADR, Zero) + + // PS0 Method for xHCI Root Hub + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF)) + { + Return() + } + // + // Call platform XHC.RHUB PS0 method if present. + // + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS0X)) + { + \_SB.PC00.XHCI.RHUB.PS0X() + } + } + + // PS2 Method for xHCI Root Hub + Method(_PS2,0,Serialized) + { + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF)) + { + Return() + } + // + // Call platform XHC.RHUB PS2 method if present. + // + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS2X)) + { + \_SB.PC00.XHCI.RHUB.PS2X() + } + } + + // PS3 Method for xHCI Root Hub + Method(_PS3,0,Serialized) + { + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF)) + { + Return() + } + // + // Call platform XHC.RHUB PS3 method if present. + // + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS3X)) + { + \_SB.PC00.XHCI.RHUB.PS3X() + } + } + + // + // High Speed Ports (without USBR) + // + Device(HS01) + { + Name(_ADR, 0x01) + } + + Device(HS02) + { + Name(_ADR, 0x02) + } + + Device(HS03) + { + Name(_ADR, 0x03) + } + + Device(HS04) + { + Name(_ADR, 0x04) + } + + Device(HS05) + { + Name(_ADR, 0x05) + } + + Device(HS06) + { + Name(_ADR, 0x06) + } + + Device(HS07) + { + Name(_ADR, 0x07) + } + + Device(HS08) + { + Name(_ADR, 0x08) + } + + Device(HS09) + { + Name(_ADR, 0x09) + } + + Device(HS10) + { + Name(_ADR, 0x0A) + } + + // + // USBR port will be known as USBR instead of HS09 / HS15 + // + Device(USR1) + { + Method(_ADR) { Return (Add(USRA(),0)) } + } + + // + // USBR port 2 will be known as USBR instead of xxxx + // + Device(USR2) + { + Method(_ADR) { Return (Add(USRA(),1)) } + } + + // + // Super Speed Ports + // + Device(SS01) + { + Method(_ADR) { Return (Add(SSPA(),0)) } + } + + Device(SS02) + { + Method(_ADR) { Return (Add(SSPA(),1)) } + } + + Device(SS03) + { + Method(_ADR) { Return (Add(SSPA(),2)) } + } + + Device(SS04) + { + Method(_ADR) { Return (Add(SSPA(),3)) } + } + + Device(SS05) + { + Method(_ADR) { Return (Add(SSPA(),4)) } + } + + Device(SS06) + { + Method(_ADR) { Return (Add(SSPA(),5)) } + } + + } // device rhub +} //scope + +// +// SPT-H +// + + Scope(\_SB_.PC00.XHCI.RHUB) { + + + + Device(HS11) + { + Name(_ADR, 0xB) + } + + + Device(HS12) + { + Name(_ADR, 0xC) + } + + Device(HS13) + { + Name(_ADR, 0xD) + } + + Device(HS14) + { + Name(_ADR, 0xE) + } + + Device(SS07) + { + Method(_ADR) { Return (Add(SSPA(),6)) } + } + + Device(SS08) + { + Method(_ADR) { Return (Add(SSPA(),7)) } + } + + Device(SS09) + { + Method(_ADR) { Return (Add(SSPA(),8)) } + } + + Device(SS10) + { + Method(_ADR) { Return (Add(SSPA(),9)) } + } + + } //scope + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP01= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP01_A= DR.asl new file mode 100644 index 0000000000..fcadab67b2 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP01_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA1,0)) { + Return (RPA1) + } Else { + Return (0x001C0000) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP02= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP02_A= DR.asl new file mode 100644 index 0000000000..8585676ccc --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP02_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA2,0)) { + Return (RPA2) + } Else { + Return (0x001C0001) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP03= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP03_A= DR.asl new file mode 100644 index 0000000000..a9dee84da6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP03_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA3,0)) { + Return (RPA3) + } Else { + Return (0x001C0002) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP04= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP04_A= DR.asl new file mode 100644 index 0000000000..6946071d7b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP04_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA4,0)) { + Return (RPA4) + } Else { + Return (0x001C0003) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP05= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP05_A= DR.asl new file mode 100644 index 0000000000..c1bf1f508a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP05_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA5,0)) { + Return (RPA5) + } Else { + Return (0x001C0004) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP06= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP06_A= DR.asl new file mode 100644 index 0000000000..268e303314 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP06_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA6,0)) { + Return (RPA6) + } Else { + Return (0x001C0005) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP07= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP07_A= DR.asl new file mode 100644 index 0000000000..c4a3af057f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP07_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA7,0)) { + Return (RPA7) + } Else { + Return (0x001C0006) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP08= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP08_A= DR.asl new file mode 100644 index 0000000000..20c03e5d31 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP08_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA8,0)) { + Return (RPA8) + } Else { + Return (0x001C0007) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP09= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP09_A= DR.asl new file mode 100644 index 0000000000..7238eb1801 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP09_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA9,0)) { + Return (RPA9) + } Else { + Return (0x001D0000) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP10= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP10_A= DR.asl new file mode 100644 index 0000000000..d88f4bde2f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP10_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAA,0)) { + Return (RPAA) + } Else { + Return (0x001D0001) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP11= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP11_A= DR.asl new file mode 100644 index 0000000000..c81c815ee1 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP11_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAB,0)) { + Return (RPAB) + } Else { + Return (0x001D0002) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP12= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP12_A= DR.asl new file mode 100644 index 0000000000..85e0ec3046 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP12_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAC,0)) { + Return (RPAC) + } Else { + Return (0x001D0003) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP13= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP13_A= DR.asl new file mode 100644 index 0000000000..f1906e54bb --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP13_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAD,0)) { + Return (RPAD) + } Else { + Return (0x001D0004) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP14= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP14_A= DR.asl new file mode 100644 index 0000000000..1e098e4674 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP14_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAE,0)) { + Return (RPAE) + } Else { + Return (0x001D0005) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP15= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP15_A= DR.asl new file mode 100644 index 0000000000..2127a907f7 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP15_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAF,0)) { + Return (RPAF) + } Else { + Return (0x001D0006) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP16= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP16_A= DR.asl new file mode 100644 index 0000000000..af61a03383 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP16_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAG,0)) { + Return (RPAG) + } Else { + Return (0x001D0007) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP17= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP17_A= DR.asl new file mode 100644 index 0000000000..b731fc3964 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP17_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAH,0)) { + Return (RPAH) + } Else { + Return (0x001B0000) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP18= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP18_A= DR.asl new file mode 100644 index 0000000000..7b51d7d9b2 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP18_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAI,0)) { + Return (RPAI) + } Else { + Return (0x001B0001) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP19= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP19_A= DR.asl new file mode 100644 index 0000000000..4d43dd81af --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP19_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAJ,0)) { + Return (RPAJ) + } Else { + Return (0x001B0002) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP20= _ADR.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP20_A= DR.asl new file mode 100644 index 0000000000..469f32cf60 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/RP20_ADR.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAK,0)) { + Return (RPAK) + } Else { + Return (0x001B0003) + } +} \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/Trac= eHubDebug.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/T= raceHubDebug.asl new file mode 100644 index 0000000000..84e7725178 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/TraceHubDeb= ug.asl @@ -0,0 +1,142 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define TRACE_HUB_MASTER_NUM_ASL 32 +#define TRACE_HUB_CHANNEL_NUM_ASL 22 + +// +// @note Only include register definition macros in ASL. +// GCC will leak C function definitions in to ASL +// code, causing compilation errors in some cases. +// +#include +#include + +Scope(\){ + // Check if Trace Hub is enabled + Method (THEN, 0, Serialized) { + OperationRegion (THBA, SystemMemory, PCH_TRACE_HUB_SW_BASE_ADDRESS, 0x= 10) + Field (THBA, DWordAcc, NoLock, Preserve) { + Offset (0x00), + DO00, 32, + } + Return (LNotEqual(DO00, 0xFFFFFFFF)) + } + + // Trace Hub debug address + // This is internal helper runtine of THDS + // Arg0 : Master number + // Arg1 : Channel number + Method (THDA, 2, Serialized) { + // Local0 =3D PCH_TRACE_HUB_SW_BASE_ADDRESS + 0x40 * (V_PCH_TRACE_HUB_= MTB_CHLCNT * (Master - V_PCH_TRACE_HUB_MTB_STHMSTR)) + 0x40 * Channel; + Store (PCH_TRACE_HUB_SW_BASE_ADDRESS, Local0) + Add (Local0, Multiply (0x40, Multiply (V_PCH_TRACE_HUB_MTB_CHLCNT, Sub= tract (Arg0, V_PCH_TRACE_HUB_MTB_STHMSTR))), Local0) + Add (Local0, Multiply (0x40, Arg1), Local0) + Return (Local0) + } + + // String to raw data + // This is internal helper runtine of THDS + // Arg0 : string + // Arg1 : Index + // Arg2 : size + Method (STRD, 3, Serialized) { + If (LGreater (Add (Arg1, Arg2), SizeOf (Arg0))) { + Return (0) + } + // Local0 is return value + // Lccal1 is loop index + // Local2 is char of string + // Local3 is buffer of string + ToBuffer (Arg0, Local3) + Store (0, Local0) + Store (0, Local1) + While (LLess (Local1, Arg2)) { + Store (DeRefOf (Index (Local3, Add (Arg1, Local1))), Local2) + Add (Local0, ShiftLeft (Local2, Multiply (8, Local1)), Local0) + Increment (Local1) + } + Return (Local0) + } + + // Trace Hub debug string + // Arg0 : debug string + Method (THDS, 1, Serialized) { + // TH check if enabled. + If (LNot (THEN())) { + Return + } + + // Local0 is the length of string + // Local1 is the debug base address + Store (Sizeof (Arg0), Local0) + Store (THDA (TRACE_HUB_MASTER_NUM_ASL, TRACE_HUB_CHANNEL_NUM_ASL), Loc= al1) + OperationRegion (THBA, SystemMemory, local1, 0x40) + Field (THBA, QWordAcc, NoLock, Preserve) { + Offset (0x00), + QO00, 64, + } + Field (THBA, DWordAcc, NoLock, Preserve) { + Offset (0x00), + DO00, 32, + Offset (0x10), + DO10, 32, + offset (0x30), + DO30, 32, + } + Field (THBA, WordAcc, NoLock, Preserve) { + Offset (0x00), + WO00, 16, + } + Field (THBA, ByteAcc, NoLock, Preserve) { + Offset (0x00), + BO00, 8, + } + + // time stamp + Store (0x01000242, DO10) + // length of string + Store (Local0, WO00) + // string + Store (0, Local6) + Store (Local0, Local7) + while (LGreaterEqual(Local7, 8)) { + Store (STRD (Arg0, Local6, 8), QO00) + Add (Local6, 8, Local6) + Subtract (Local7, 8, Local7) + } + If (LGreaterEqual(Local7, 4)) { + Store (STRD (Arg0, Local6, 4), DO00) + Add (Local6, 4, Local6) + Subtract (Local7, 4, Local7) + } + If (LGreaterEqual(Local7, 2)) { + Store (STRD (Arg0, Local6, 2), WO00) + Add (Local6, 2, Local6) + Subtract (Local7, 2, Local7) + } + If (LGreaterEqual(Local7, 1)) { + Store (STRD (Arg0, Local6, 1), BO00) + Add (Local6, 1, Local6) + Subtract (Local7, 1, Local7) + } + // flag + Store (0, DO30) + } + + // Trace Hub debug Hex string + // Arg0 : Integer, buffer + Method (THDH, 1, Serialized) { + THDS (ToHexString (Arg0)) + } + + // Trace Hub debug decimal string + // Arg0 : Integer, buffer + Method (THDD, 1, Serialized) { + THDS (ToDecimalString (Arg0)) + } +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/usbs= bd.asl b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/usbsbd.a= sl new file mode 100644 index 0000000000..7b10048bdd --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/AcpiTables/Dsdt/usbsbd.asl @@ -0,0 +1,63 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// _DSM : Device Specific Method supporting USB Sideband Deferring function +// +// Arg0: UUID Unique function identifier +// Arg1: Integer Revision Level +// Arg2: Integer Function Index +// Arg3: Package Parameters +// +Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgO= bj}) +{ + + If (LEqual(Arg0, ToUUID ("A5FC708F-8775-4BA6-BD0C-BA90A1EC72F8"))) + { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) + { + // + // Standard query - A bitmask of functions supported + // Supports function 0-2 + // + Case (0) + { + if (LEqual(Arg1, 1)){ // test Arg1 for the revision + Return (Buffer () {0x07}) + } else { + Return (Buffer () {0}) + } + } + // + // USB Sideband Deferring Support + // 0: USB Sideband Deferring not supported on this device + // 1: USB Sideband Deferring supported + // + Case (1) + { + if (LEqual(SDGV,0xFF)){ // check for valid GPE vector + Return (0) + } else { + Return (1) + } + } + // + // GPE Vector + // Return the bit offset within the GPE block of the GPIO (HOST_ALE= RT) driven by this device + // + Case (2) + { + Return (SDGV) + } + } + } + + Return (0) +} --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726538; bh=H1CoOfdQjNsRXNsLJ2HD2mE+Yrcl545rvSRdff8AsIQ=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=sntYmw+eeloU4B+pqiJWpU1dYHi7Klrdsjx+2fCmSzs0OyGxZALnQwXe8TmzXxTY4ak SxCw32oZCSvXqqqe8ELXTryByIzu0gTQCCnOA5EEmSBFvWkRODmPlvzDe1AI16IanuGD+ DMKrmxSS20fJHpDEU8fwcKfXxtkdG12gsQU= X-ZohoMail-DKIM: pass (identity @groups.io) Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../Iio/Include/Protocol/IioSystem.h | 58 ++ .../Include/Guid/MemoryConfigData.h | 19 + .../Include/Guid/MemoryMapData.h | 74 ++ .../Include/Guid/PartialMirrorGuid.h | 59 ++ .../Include/Guid/SmramMemoryReserve.h | 43 + .../Include/Guid/SocketCommonRcVariable.h | 41 + .../Include/Guid/SocketIioVariable.h | 264 ++++++ .../Include/Guid/SocketMemoryVariable.h | 321 +++++++ .../Include/Guid/SocketMpLinkVariable.h | 173 ++++ .../Include/Guid/SocketPciResourceData.h | 42 + .../Guid/SocketPowermanagementVariable.h | 227 +++++ .../Guid/SocketProcessorCoreVariable.h | 115 +++ .../Include/Guid/SocketVariable.h | 35 + .../Include/Library/CpuPpmLib.h | 707 +++++++++++++++ .../Include/Library/CsrToPcieAddress.h | 42 + .../Include/Library/MmPciBaseLib.h | 48 ++ .../Include/Library/PcieAddress.h | 80 ++ .../Include/Library/PciePlatformHookLib.h | 27 + .../Include/Library/UsraAccessApi.h | 85 ++ .../Include/MaxSocket.h | 19 + .../Include/Ppi/SiliconRegAccess.h | 162 ++++ .../Include/Protocol/IioUds.h | 44 + .../Include/Protocol/PciCallback.h | 84 ++ .../Include/Protocol/SiliconRegAccess.h | 227 +++++ .../Include/SocketConfiguration.h | 514 +++++++++++ .../Include/UncoreCommonIncludes.h | 354 ++++++++ .../Include/UsraAccessType.h | 195 +++++ .../Chip/Skx/Include/Iio/IioConfig.h | 300 +++++++ .../Chip/Skx/Include/Iio/IioPlatformData.h | 298 +++++++ .../Chip/Skx/Include/Iio/IioRegs.h | 314 +++++++ .../Skx/Include/Iio/IioSetupDefinitions.h | 111 +++ .../Chip/Skx/Include/KtiDisc.h | 26 + .../Chip/Skx/Include/KtiHost.h | 136 +++ .../Chip/Skx/Include/KtiSi.h | 39 + .../Chip/Skx/Include/Protocol/CpuCsrAccess.h | 143 +++ .../Chip/Skx/Include/Setup/IioUniversalData.h | 187 ++++ .../BaseMemoryCoreLib/Core/Include/CpuHost.h | 255 ++++++ .../Core/Include/CsrToPcieAddress.h | 42 + .../Core/Include/DataTypes.h | 111 +++ .../BaseMemoryCoreLib/Core/Include/MemHost.h | 328 +++++++ .../Core/Include/MemHostChipCommon.h | 122 +++ .../BaseMemoryCoreLib/Core/Include/MemRegs.h | 13 + .../Core/Include/MrcCommonTypes.h | 20 + .../Core/Include/PcieAddress.h | 65 ++ .../BaseMemoryCoreLib/Core/Include/Printf.h | 74 ++ .../BaseMemoryCoreLib/Core/Include/SysHost.h | 136 +++ .../Core/Include/SysHostChipCommon.h | 86 ++ .../BaseMemoryCoreLib/Core/Include/SysRegs.h | 68 ++ .../Core/Include/UsbDebugPort.h | 318 +++++++ .../Platform/Purley/Include/MemDefaults.h | 17 + .../Platform/Purley/Include/MemPlatform.h | 81 ++ .../Platform/Purley/Include/PlatformHost.h | 176 ++++ .../Library/CsrToPcieLib/CpuCsrAccessDefine.h | 56 ++ .../Library/CsrToPcieLib/CsrToPcieDxeLib.inf | 85 ++ .../Library/CsrToPcieLib/CsrToPcieLib.c | 179 ++++ .../Library/CsrToPcieLib/CsrToPciePeiLib.inf | 81 ++ .../CsrToPcieLibNull/BaseCsrToPcieLibNull.inf | 67 ++ .../Library/CsrToPcieLibNull/CsrToPcieLib.c | 41 + .../Library/DxeMmPciBaseLib/DxeMmPciBaseLib.c | 89 ++ .../DxeMmPciBaseLib/DxeMmPciBaseLib.inf | 60 ++ .../Library/DxeMmPciBaseLib/SmmMmPciBaseLib.c | 86 ++ .../DxeMmPciBaseLib/SmmMmPciBaseLib.inf | 60 ++ .../Library/MmPciBaseLib/MmPciBaseLib.c | 69 ++ .../Library/MmPciBaseLib/MmPciBaseLib.inf | 55 ++ .../Library/PcieAddressLib/PcieAddressLib.c | 305 +++++++ .../Library/PcieAddressLib/PcieAddressLib.inf | 70 ++ .../Chip/Common/CpuPciAccessCommon.c | 812 ++++++++++++++++++ .../Chip/Include/CpuCsrAccessDefine.h | 52 ++ .../ProcMemInit/Chip/Include/CpuPciAccess.h | 117 +++ .../Chip/Include/CpuPciAccessCommon.h | 83 ++ .../ProcMemInit/Chip/Include/Rc_Revision.h | 13 + .../Library/UsraAccessLib/CsrAccess.c | 118 +++ .../Library/UsraAccessLib/PcieAccess.c | 354 ++++++++ .../Library/UsraAccessLib/UsraAccessLib.c | 235 +++++ .../Library/UsraAccessLib/UsraAccessLib.h | 257 ++++++ .../Library/UsraAccessLib/UsraAccessLib.inf | 62 ++ .../IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec | 609 +++++++++++++ .../Include/Library/CpuConfigLib.h | 667 ++++++++++++++ .../Include/Protocol/IntelCpuPcdsSetDone.h | 18 + 79 files changed, 12225 insertions(+) create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Iio/Include/Proto= col/IioSystem.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Memo= ryConfigData.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Memo= ryMapData.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Part= ialMirrorGuid.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Smra= mMemoryReserve.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Sock= etCommonRcVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Sock= etIioVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Sock= etMemoryVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Sock= etMpLinkVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Sock= etPciResourceData.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Sock= etPowermanagementVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Sock= etProcessorCoreVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Sock= etVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/C= puPpmLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/C= srToPcieAddress.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/M= mPciBaseLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/P= cieAddress.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/P= ciePlatformHookLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/U= sraAccessApi.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/MaxSocket= .h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Ppi/Silic= onRegAccess.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/= IioUds.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/= PciCallback.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/= SiliconRegAccess.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/SocketCon= figuration.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/UncoreCom= monIncludes.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/UsraAcces= sType.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Chip/Skx/Include/Iio/IioConfig.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Chip/Skx/Include/Iio/IioRegs.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Chip/Skx/Include/Iio/IioSetupDefinitions.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Chip/Skx/Include/KtiDisc.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Chip/Skx/Include/KtiHost.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Chip/Skx/Include/KtiSi.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/CpuHost.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/CsrToPcieAddress.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/DataTypes.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/MemHost.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/MemHostChipCommon.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/MemRegs.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/MrcCommonTypes.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/PcieAddress.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/Printf.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/SysHost.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/SysHostChipCommon.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/SysRegs.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Core/Include/UsbDebugPort.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Platform/Purley/Include/MemDefaults.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Platform/Purley/Include/MemPlatform.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemor= yCoreLib/Platform/Purley/Include/PlatformHost.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcie= Lib/CpuCsrAccessDefine.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcie= Lib/CsrToPcieDxeLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcie= Lib/CsrToPcieLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcie= Lib/CsrToPciePeiLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcie= LibNull/BaseCsrToPcieLibNull.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcie= LibNull/CsrToPcieLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciB= aseLib/DxeMmPciBaseLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciB= aseLib/DxeMmPciBaseLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciB= aseLib/SmmMmPciBaseLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciB= aseLib/SmmMmPciBaseLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBase= Lib/MmPciBaseLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBase= Lib/MmPciBaseLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddre= ssLib/PcieAddressLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddre= ssLib/PcieAddressLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemIn= it/Chip/Common/CpuPciAccessCommon.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemIn= it/Chip/Include/CpuCsrAccessDefine.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemIn= it/Chip/Include/CpuPciAccess.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemIn= it/Chip/Include/CpuPciAccessCommon.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemIn= it/Chip/Include/Rc_Revision.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAcces= sLib/CsrAccess.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAcces= sLib/PcieAccess.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAcces= sLib/UsraAccessLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAcces= sLib/UsraAccessLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAcces= sLib/UsraAccessLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32Fami= lyCpuPkg/IA32FamilyCpuPkg.dec create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32Fami= lyCpuPkg/Include/Library/CpuConfigLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32Fami= lyCpuPkg/Include/Protocol/IntelCpuPcdsSetDone.h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Iio/Include/Protocol/Iio= System.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Iio/Include/Protocol/IioSy= stem.h new file mode 100644 index 0000000000..0a8d3064c3 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Iio/Include/Protocol/IioSystem.h @@ -0,0 +1,58 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _IIO_SYSTEM_PROTOCOL_H_ +#define _IIO_SYSTEM_PROTOCOL_H_ + +#include +#include + +// +// IIO System driver Protocol GUID +// +// {DDC3080A-2740-4ec2-9AA5-A0ADEFD6FF9C} +#define EFI_IIO_SYSTEM_GUID \ + { \ + 0xDDC3080A, 0x2740, 0x4ec2, 0x9A, 0xA5, 0xA0, 0xAD, 0xEF, 0xD6, 0xFF, = 0x9C \ + } + +extern EFI_GUID gEfiIioSystemProtocolGuid; + +typedef struct _PORT_DESCRIPTOR{ + UINT8 Bus; + UINT8 Device; + UINT8 Function; +}PORT_DESCRIPTOR; + +typedef struct _PORT_ATTRIB{ + UINT8 PortWidth; + UINT8 PortSpeed; +}PORT_ATTRIB; + +EFI_STATUS +IioGetCpuUplinkPort ( + UINT8 IioIndex, + PORT_DESCRIPTOR *PortDescriptor, //Bus, Device, function + BOOLEAN *PortStatus, //TRUE if enabled else disabled + PORT_ATTRIB *PortAttrib //width and speed +); + +typedef +EFI_STATUS +(EFIAPI *IIO_GET_CPU_UPLINK_PORT) ( + IN UINT8 IioIndex, + OUT PORT_DESCRIPTOR *PortDescriptor, + OUT BOOLEAN *PortStatus, + OUT PORT_ATTRIB *PortAttrib +); + +typedef struct _EFI_IIO_SYSTEM_PROTOCOL{ + IIO_GLOBALS *IioGlobalData; + IIO_GET_CPU_UPLINK_PORT IioGetCpuUplinkPort; +} EFI_IIO_SYSTEM_PROTOCOL; + +#endif //_IIO_SYSTEM_PROTOCOL_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryConfi= gData.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryConfigDa= ta.h new file mode 100644 index 0000000000..f7c57af8a5 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryConfigData.h @@ -0,0 +1,19 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MEMORY_CONFIG_DATA_GUID_H_ +#define _MEMORY_CONFIG_DATA_GUID_H_ + +#define EFI_MEMORY_CONFIG_DATA_GUID \ + { \ + 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0= x31 }\ + } + +extern EFI_GUID gEfiMemoryConfigDataGuid; +extern CHAR16 EfiMemoryConfigVariable[]; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryMapDa= ta.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryMapData.h new file mode 100644 index 0000000000..c225624edc --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryMapData.h @@ -0,0 +1,74 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MEMORY_MAP_GUID_H_ +#define _MEMORY_MAP_GUID_H_ + +#include "SysHost.h" +#include "UncoreCommonIncludes.h" +#include "PartialMirrorGuid.h" + +// {F8870015-6994-4b98-95A2-BD56DA91C07F} +#define EFI_MEMORY_MAP_GUID \ + { \ + 0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \ + } + +extern EFI_GUID gEfiMemoryMapGuid; +extern CHAR16 EfiMemoryMapVariable[]; + +// +// System Memory Map HOB information +// + +#pragma pack(1) + + +typedef struct SystemMemoryMapElement { + UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1= : 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ct= rl region + UINT8 NodeId; // Node ID of the HA Owning the memory + UINT8 SocketId; // Socket Id of socket that has his memory - ON= LY IN NUMA + UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on so= cket then ImcInterBitmap and ChInterBitmap are identical in all sockets + UINT8 ImcInterBitmap; // IMC interleave bitmap for this memory + UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are i= nterleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 = & 0 are interleaved + UINT32 BaseAddress; // Base Address of the element in 64MB chunks + UINT32 ElementSize; // Size of this memory element in 64MB chunks +} SYSTEM_MEMORY_MAP_ELEMENT; + +typedef struct SystemMemoryMapHob { + UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. + UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. + UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem. + UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem. + UINT32 memSize; // Total physical memory size + UINT16 memFreq; // Mem Frequency + UINT8 memMode; // 0 - Independent, 1 - Lockstep + UINT8 volMemMode; // 0 - 1LM, 1 - 2LM + UINT8 DimmType; + UINT16 DramType; + UINT8 DdrVoltage; + UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nf= it), then this should get set + UINT8 SADNum; + UINT8 XMPProfilesSup; + UINT8 cpuType; + UINT8 cpuStepping; + UINT8 SystemRasType; + UINT8 RasModesEnabled; // RAS modes that are enabled + UINT8 ExRasModesEnabled; // Extended RAS modes that are enabled + UINT8 RasModesSupported; //RAS modes that are supported by current me= mory population. + UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 = - SNC enabled for this configuration + UINT8 NumOfCluster; + UINT8 NumChPerMC; + UINT8 numberEntries; // Number of Memory Map Elements + UINT8 maxIMC; + UINT8 maxCh; + struct SystemMemoryMapElement Element[MAX_SOCKET * SAD_RULES]; +} SYSTEM_MEMORY_MAP_HOB; + +#pragma pack() + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/PartialMirr= orGuid.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/PartialMirror= Guid.h new file mode 100644 index 0000000000..16fb0f843e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/PartialMirrorGuid.h @@ -0,0 +1,59 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PARTIAL_MIRROR_GUID_H_ +#define _PARTIAL_MIRROR_GUID_H_ + +#define ADDRESS_BASED_MIRROR_VARIABLE_GUID { 0x7b9be2e0, 0xe28a, 0x4197, 0= xad, 0x3e, 0x32, 0xf0, 0x62, 0xf9, 0x46, 0x2c } + +#define ADDRESS_RANGE_MIRROR_VARIABLE_CURRENT L"MirrorCurrent" +#define ADDRESS_RANGE_MIRROR_VARIABLE_REQUEST L"MirrorRequest" +#define ADDRESS_BASED_MIRROR_VARIABLE_SIZE sizeof(ADDRESS_RANGE_MIRROR_VAR= IABLE_DATA) +#define ADDRESS_BASED_MIRROR_VARIABLE_ATTRIBUTE (EFI_VARIABLE_NON_VOLATILE= | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS) +#define ADDRESS_RANGE_MIRROR_VARIABLE_VERSION 1 +#define MIRROR_STATUS_SUCCESS 0 +#define MIRROR_STATUS_MIRROR_INCAPABLE 1 +#define MIRROR_STATUS_VERSION_MISMATCH 2 +#define MIRROR_STATUS_INVALID_REQUEST 3 +#define MIRROR_STATUS_UNSUPPORTED_CONFIG 4 +#define MIRROR_STATUS_OEM_SPECIFIC_CONFIGURATION 5 + +extern EFI_GUID gAddressBasedMirrorGuid; + +#pragma pack(1) + +typedef struct { +// +// MirroredAmountAbove4GB is the amount of available memory above 4GB that= needs to be mirrored +// measured in basis point (hundredths of percent e.g. 12% =3D 1275). +// In a multi-socket system, platform is required to distribute the mirror= ed memory ranges such that the +// amount mirrored is approximately proportional to the amount of memory = on each NUMA node. E.g. on +// a two node machine with 64GB on node 0 and 32GB on node 1, a request fo= r 12GB of mirrored memory +// should be allocated with 8GB of mirror on node 0 and 4GB on node 1. +// +// For example, if the total memory in the system is 48GB and 12GB of memo= ry above the 4GB addresses needs to be mirrored then the amount would be: +// Total Memory =3D 48 GB +// Total Memory above 4GB =3D 44 GB +// Percentage =3D 8/44 * 100 =3D 18.18% =3D 1818 basis points +// Consider a 2S system with 32 GB of memory attached to socket 0 and 16GB= on socket 1, +// then socket 0 should mirror 8 GB of memory and socket 1 mirror 4GB to m= aintain the requested 18%. +// This ensures that OS has an adequate amount of mirrored memory on each = NUMA domain. +// + UINT8 MirrorVersion; + BOOLEAN MirrorMemoryBelow4GB; + UINT16 MirroredAmountAbove4GB; + UINT8 MirrorStatus; +} ADDRESS_RANGE_MIRROR_VARIABLE_DATA; + +typedef struct { + ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorCurrentType; + ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorRequestType; +} RASMEMORYINFO; +#pragma pack() + + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SmramMemory= Reserve.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SmramMemoryR= eserve.h new file mode 100644 index 0000000000..d7b891f40f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SmramMemoryReserve= .h @@ -0,0 +1,43 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_ +#define _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_ + +#define EFI_SMM_PEI_SMRAM_MEMORY_RESERVE \ + { \ + 0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff,= 0x3d } \ + } + +/** +* GUID specific data structure of HOB for reserving SMRAM regions. +* +* Inconsistent with specification here: +* EFI_HOB_SMRAM_DESCRIPTOR_BLOCK has been changed to EFI_SMRAM_HOB_DESCRIP= TOR_BLOCK. +* This inconsistency is kept in code in order for backward compatibility. +**/ +typedef struct { + /// + /// Designates the number of possible regions in the system + /// that can be usable for SMRAM. + /// + /// Inconsistent with specification here: + /// In Framework SMM CIS 0.91 specification, it defines the field type a= s UINTN. + /// However, HOBs are supposed to be CPU neutral, so UINT32 should be us= ed instead. + /// + UINT32 NumberOfSmmReservedRegions; + /// + /// Used throughout this protocol to describe the candidate + /// regions for SMRAM that are supported by this platform. + /// + EFI_SMRAM_DESCRIPTOR Descriptor[1]; +} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK; + +extern EFI_GUID gEfiSmmPeiSmramMemoryReserveGuid; + +#endif + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketCommo= nRcVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketCo= mmonRcVariable.h new file mode 100644 index 0000000000..b3ea677612 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketCommonRcVari= able.h @@ -0,0 +1,41 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_COMMONRC_CONFIG_DATA_H__ +#define __SOCKET_COMMONRC_CONFIG_DATA_H__ + + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketCommonRcVariableGuid; +#define SOCKET_COMMONRC_CONFIGURATION_NAME L"SocketCommonRcConfig" + +#pragma pack(1) +typedef struct { + // + // Common Section of RC + // + UINT32 MmiohBase; + UINT16 MmiohSize; + UINT8 MmcfgBase; + UINT8 MmcfgSize; + UINT8 IsocEn; + UINT8 NumaEn; + UINT8 MirrorMode; + UINT8 LockStep; + UINT8 CpuStepping; + UINT8 SystemRasType; + UINT32 FpgaPresentBitMap; + UINT8 IssCapable; + UINT8 PbfCapable; +} SOCKET_COMMONRC_CONFIGURATION; +#pragma pack() + +#endif + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketIioVa= riable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketIioVari= able.h new file mode 100644 index 0000000000..8ee87eabd1 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketIioVariable.h @@ -0,0 +1,264 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_IIO_CONFIG_DATA_H__ +#define __SOCKET_IIO_CONFIG_DATA_H__ + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketIioVariableGuid; +#define SOCKET_IIO_CONFIGURATION_NAME L"SocketIioConfig" + +#pragma pack(1) + + +typedef struct { + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D VTd Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 VTdSupport; + UINT8 InterruptRemap; + UINT8 CoherencySupport; + UINT8 ATS; + UINT8 PostedInterrupt; + UINT8 PassThroughDma; +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PCIE Setup Options =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 IioPresent[MAX_SOCKET]; + UINT8 VtdAcsWa; + + // Platform data needs to update these PCI Configuration settings + UINT8 SLOTHPCAP[MAX_TOTAL_PORTS]; // Slot Hot Plug capable -= Slot Capabilities (D0-10 / F0 / R0xA4 / B6) + UINT8 SLOTHPSUP[MAX_TOTAL_PORTS]; // Hot Plug surprise suppo= rted - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + + // General PCIE Configuration + UINT8 ConfigIOU0[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 0= 2-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P5p6p7p8) + UINT8 ConfigIOU1[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 0= 2-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P9p10p11p12) + UINT8 ConfigIOU2[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 0= 2-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4) + UINT8 ConfigMCP0[MAX_SOCKET]; // 04-x16 (p13) + UINT8 ConfigMCP1[MAX_SOCKET]; // 04-x16 (p14) + UINT8 CompletionTimeoutGlobal; // + UINT8 CompletionTimeoutGlobalValue; + UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CoherentReadPart; + UINT8 CoherentReadFull; + UINT8 PcieGlobalAspm; // + UINT8 StopAndScream; // + UINT8 SnoopResponseHoldOff; // + // + // PCIE capability + // + UINT8 PCIe_LTR; // + UINT8 PcieExtendedTagField; // + UINT8 PCIe_AtomicOpReq; // + UINT8 PcieMaxReadRequestSize; // + + + UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup + + // mixc PCIE configuration + UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieAspm[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieMaxPayload[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; // On Setup + UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup + UINT8 ExtendedSync[MAX_TOTAL_PORTS]; // On Setup + UINT8 InbandPresenceDetect[MAX_TOTAL_PORTS]; // Not implemented i= n code + UINT8 PciePortDisable[MAX_TOTAL_PORTS]; // Not implemented i= n code + UINT8 PciePmeIntEn[MAX_TOTAL_PORTS]; // Not implemented i= n code + UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for Link Control2 + // + UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; //on Setup + UINT8 ComplianceMode[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PciePortLinkMaxWidth[MAX_TOTAL_PORTS]; // On Setup + UINT8 DeEmphasis[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for MISCCTRLSTS + // + UINT8 EOI[MAX_TOTAL_PORTS]; // On Setup + UINT8 MSIFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSINFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSICOREN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; //On Setup + UINT8 DISL0STx[MAX_TOTAL_PORTS]; //On Setup + UINT8 P2PWrtDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 Peer + UINT8 P2PRdDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 peer + UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIHP[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIPM[MAX_TOTAL_PORTS]; //On Setup + UINT8 SRIS[MAX_TOTAL_PORTS]; //On Setup + UINT8 TXEQ[MAX_TOTAL_PORTS]; //On Setup + UINT8 ECRC[MAX_TOTAL_PORTS]; //On Setup + // + // PCIE RAS (Errors) + // + + UINT8 PcieUnsupportedRequests[MAX_TOTAL_PORTS]; // Unsupported Req= uest per-port option + + // + // PCIE Link Training Ctrl + // + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Crystal Beach 3 Setup Options =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 Reserved1[MAX_SOCKET]; + UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 DisableTPH; + UINT8 PrioritizeTPH; + UINT8 CbRelaxedOrdering; + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D MISC IOH Setup Options =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + + // The following are for hiding each individual device and function + UINT8 PEXPHIDE[MAX_TOTAL_PORTS]; // Hide any of the DMI o= r PCIE devices - SKT 0,1,2,3; Device 0-10 PRD + UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS]; + // Hide IOAPIC Device= 5, Function 4 + UINT8 PCUF6Hide; // Hide Device PCU Devic= e 30, Function 6 + UINT8 EN1K; // Enable/Disable 1K gra= nularity of IO for P2P bridges 0:20:0:98 bit 2 + UINT8 DualCvIoFlow; // Dual CV IO Flow + UINT8 Pci64BitResourceAllocation; + UINT8 PcieBiosTrainEnable; // Used as a work around= for A0 PCIe + UINT8 MultiCastEnable; // MultiCastEnable test = enable + UINT8 McastBaseAddrRegion; // McastBaseAddrRegion + UINT8 McastIndexPosition; // McastIndexPosition + UINT8 McastNumGroup; // McastNumGroup + + + UINT8 HidePEXPMenu[MAX_TOTAL_PORTS]; // to suppress /displa= y the PCIe port menu + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D NTB Related Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 NtbPpd[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeOverride[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSplitBar[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSBar01Prefetch[MAX_NTB_PORTS]; //on setup option + UINT8 NtbXlinkCtlOverride[MAX_NTB_PORTS]; //on setup option + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D VMD Related Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 VMDEnabled[MAX_VMD_STACKS]; + UINT8 VMDPortEnable[MAX_VMD_PORTS]; + UINT8 VMDHotPlugEnable[MAX_VMD_STACKS]; + UINT8 VMDCfgBarSz[MAX_VMD_STACKS]; + UINT8 VMDCfgBarAttr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz1[MAX_VMD_STACKS]; + UINT8 VMDMemBar1Attr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz2[MAX_VMD_STACKS]; + UINT8 VMDMemBar2Attr[MAX_VMD_STACKS]; + + + /** + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PCIe SSD Related Setup Options =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + **/ + + UINT8 PcieAICEnabled[MAX_VMD_STACKS]; + UINT8 PcieAICPortEnable[MAX_VMD_PORTS]; + UINT8 PcieAICHotPlugEnable[MAX_VMD_STACKS]; + + /** + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PCIe Global Related Setup Options =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + **/ + UINT8 NoSnoopRdCfg; //on Setup + UINT8 NoSnoopWrCfg; //on Setup + UINT8 MaxReadCompCombSize; //on Setup + UINT8 ProblematicPort; //on Setup + UINT8 DmiAllocatingFlow; //on Setup + UINT8 PcieAllocatingFlow; //on Setup + UINT8 PcieHotPlugEnable; //on Setup + UINT8 PcieAcpiHotPlugEnable; //on Setup + UINT8 HaltOnDmiDegraded; //on Setup + UINT8 RxClockWA; + UINT8 GlobalPme2AckTOCtrl; //on Setup + UINT8 MctpEn; //On Setup + UINT8 PcieSlotOprom1; //On Setup + UINT8 PcieSlotOprom2; //On Setup + UINT8 PcieSlotOprom3; //On Setup + UINT8 PcieSlotOprom4; //On Setup + UINT8 PcieSlotOprom5; //On Setup + UINT8 PcieSlotOprom6; //On Setup + UINT8 PcieSlotOprom7; //On Setup + UINT8 PcieSlotOprom8; //On Setup + UINT8 PcieSlotItemCtrl; //On Setup + UINT8 PcieRelaxedOrdering; //On Setup + UINT8 PciePhyTestMode; //On setup +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Iio Related Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + + UINT8 RtoEnable; + UINT8 RtoLtssmLogger; // On Setup + UINT8 RtoLtssmLoggerStop; // On Setup + UINT8 RtoLtssmLoggerSpeed; // On Setup + UINT8 RtoLtssmLoggerMask; // On Setup + UINT8 RtoJitterLogger; // On Setup + UINT32 RtoSocketDevFuncHide[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup + UINT8 RtoGen3NTBTestCard[MAX_TOTAL_PORTS]; // On Setup + + UINT8 RtoGen3OverrideMode[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3TestCard[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoDnTxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoRxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoUpTxPreset[MAX_TOTAL_PORTS]; //On Setup + + UINT8 InboundConfiguration[MAX_TOTAL_PORTS]; //On Setup + // Nvram variables for CLX64L CPUs. + UINT8 CLX64LCpuPresent; +} SOCKET_IIO_CONFIGURATION; +#pragma pack() + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMemor= yVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMemo= ryVariable.h new file mode 100644 index 0000000000..823e67e3f8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMemoryVariab= le.h @@ -0,0 +1,321 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_MEMORY_CONFIG_DATA_H__ +#define __SOCKET_MEMORY_CONFIG_DATA_H__ + + +#include +#include "SocketConfiguration.h" +#include + +extern EFI_GUID gEfiSocketMemoryVariableGuid; +#define SOCKET_MEMORY_CONFIGURATION_NAME L"SocketMemoryConfig" + +#pragma pack(1) +typedef struct { + UINT8 RtoMaxNodeInterleave; + UINT8 MemoryHotPlugBase; + UINT8 MemoryHotPlugLen; + UINT8 Srat; + UINT8 SratMemoryHotPlug; + UINT8 SratCpuHotPlug; + UINT8 PagePolicy; + UINT8 PatrolScrub; + UINT8 PatrolScrubDuration; + UINT8 PatrolScrubAddrMode; + UINT8 partialmirror; + UINT8 partialmirrorsad0; + UINT8 PartialMirrorUefi; + UINT16 PartialMirrorUefiPercent; + UINT16 partialmirrorsize[MAX_PARTIAL_MIRROR]; // Arra= y of sizes of different partial mirrors + UINT8 DemandScrubMode; + UINT8 SddcPlusOneEn; + UINT16 spareErrTh; + UINT8 DieSparing; + UINT8 Reserved1; + UINT8 ADDDCEn; + UINT8 AdddcErrInjEn; + UINT8 leakyBktLo; + UINT8 leakyBktHi; + UINT8 DutyCycleTraining; + UINT8 refreshMode; + UINT8 dllResetTestLoops; + UINT8 DdrMemoryType; + UINT8 HwMemTest; + UINT16 MemTestLoops; + UINT8 EccSupport; + UINT8 SocketInterleaveBelow4GB; + UINT8 Reserved2; + UINT8 Reserved3; + UINT8 Reserved4[16]; + UINT8 volMemMode; + UINT8 Reserved5; + UINT8 memInterleaveGran1LM; + UINT8 RtoMemInterleaveGranPMemUMA; + UINT8 RtoCfgMask2LM; + UINT8 ImcInterleaving; + UINT8 ChannelInterleaving; + UINT8 RankInterleaving; + UINT8 CkeProgramming; + UINT8 Reserved6; + UINT8 PkgcSrefEn; + UINT8 CkeIdleTimer; + UINT8 ApdEn; + UINT8 PpdEn; + UINT8 DdrtCkeEn; + UINT8 OppSrefEn; + UINT8 DdrtSrefEn; + UINT8 MdllOffEn; + UINT8 CkMode; + UINT8 MemTestOnFastBoot; + UINT8 AttemptFastBoot; + UINT8 AttemptFastBootCold; + UINT8 bdatEn; + UINT8 ScrambleEnDDRT; + UINT8 ScrambleEn; // for ddr4 + UINT8 allowCorrectableError; + UINT16 ScrambleSeedLow; + UINT16 ScrambleSeedHigh; + UINT8 CustomRefreshRateEn; + UINT8 CustomRefreshRate; + UINT8 mcBgfThreshold; + UINT8 readVrefCenter; + UINT8 wrVrefCenter; + UINT8 haltOnMemErr; + UINT8 thermalthrottlingsupport; + UINT8 thermalmemtrip; + UINT8 DimmTempStatValue; + UINT8 XMPProfilesSup; + UINT8 XMPMode; + UINT8 tCAS; + UINT8 tRP; + UINT8 tRCD; + UINT8 tRAS; + UINT8 tWR; + UINT16 tRFC; + UINT8 tRRD; + UINT8 tRTP; + UINT8 tWTR; + UINT8 tFAW; + UINT8 tCWL; + UINT8 tRC; + UINT8 commandTiming; + UINT16 tREFI; + UINT8 DdrFreqLimit; + UINT16 Vdd; + UINT8 lrdimmModuleDelay; + UINT32 rmtPatternLength; + UINT32 rmtPatternLengthExt; + UINT8 check_pm_sts; + UINT8 check_platform_detect; + UINT8 MemPwrSave; + UINT8 ElectricalThrottlingMode; + UINT8 MultiThreaded; + UINT8 promoteMrcWarnings; + UINT8 promoteWarnings; + UINT8 oppReadInWmm; + UINT16 normOppInterval; + UINT8 sck0ch0; + UINT8 sck0ch1; + UINT8 sck0ch2; + UINT8 sck0ch3; + UINT8 sck0ch4; + UINT8 sck0ch5; + UINT8 sck1ch0; + UINT8 sck1ch1; + UINT8 sck1ch2; + UINT8 sck1ch3; + UINT8 sck1ch4; + UINT8 sck1ch5; + UINT8 sck2ch0; + UINT8 sck2ch1; + UINT8 sck2ch2; + UINT8 sck2ch3; + UINT8 sck2ch4; + UINT8 sck2ch5; + UINT8 sck3ch0; + UINT8 sck3ch1; + UINT8 sck3ch2; + UINT8 sck3ch3; + UINT8 sck3ch4; + UINT8 sck3ch5; + UINT8 mdllSden; + UINT8 memhotSupport; + UINT8 MemhotOutputOnlyOpt; + UINT8 ADREn; + UINT8 RankMargin; + UINT8 EnableBacksideRMT; + UINT8 EnableBacksideCMDRMT; + UINT8 Reserved_0; + UINT8 rankMaskEn; + UINT8 RankSparing; + UINT8 multiSparingRanks; + UINT8 caParity; + UINT8 dimmIsolation; + UINT8 smbSpeed; + UINT8 EnforcePOR; + UINT8 pda; + UINT8 turnaroundOpt; + UINT8 dramrxeqEnable; + UINT8 rxmodctleEnable; + UINT8 oneRankTimingMode; + UINT8 eyeDiagram; + + UINT8 Reserved9; + UINT8 Reserved10; + UINT8 Reserved11; + UINT8 Reserved12; + UINT8 Reserved13; + UINT8 Reserved14; + UINT8 Reserved15; + UINT8 Reserved16; + UINT8 Reserved17; + UINT8 Reserved18; + UINT8 Reserved19; + UINT8 Reserved20; + UINT8 Reserved21; + UINT8 Reserved22; + UINT8 Reserved23; + UINT8 Reserved24; + UINT8 Reserved25; + UINT8 Reserved26; + UINT8 Reserved27; + UINT8 Reserved28; + UINT8 DramRaplInit; + UINT8 BwLimitTfOvrd; + UINT8 perbitmargin; + UINT8 DramRaplExtendedRange; + UINT8 CmsEnableDramPm; + UINT8 logParsing; + UINT8 WritePreamble; + UINT8 ReadPreamble; + UINT8 WrCRC; + + UINT8 Reserved_1; + UINT8 Reserved_2; + UINT8 Reserved_3; + UINT8 Reserved_4; + UINT8 Reserved_5; + UINT8 Reserved_6; + UINT8 Reserved_7; + UINT8 Reserved_8; + + UINT8 RmtOnColdFastBoot; + UINT8 mrcRepeatTest; + UINT8 RtoLowMemChannel; + UINT8 RtoHighAddressStartBitPosition; + UINT8 staggerref; + UINT32 memFlows; + UINT32 memFlowsExt; + UINT8 Blockgnt2cmd1cyc; + UINT8 Disddrtopprd; + UINT8 Reserved8; + UINT8 setSecureEraseAllDIMMs; + UINT8 setSecureEraseSktCh[MAX_AEP_DIMM_SETUP]; + UINT8 SetSecureEraseSktChHob[MAX_AEP_DIMM_SETUP]; + // + // PPR related + // + UINT8 pprType; + UINT8 pprErrInjTest; + // CR QoS Configuration Profiles + UINT8 FastGoConfig; + UINT8 Reserved_11; + UINT8 Reserved_12; + UINT8 Reserved_13; + UINT8 ADRDataSaveMode; + UINT8 eraseArmNVDIMMS; + UINT8 restoreNVDIMMS; + UINT8 interNVDIMMS; + UINT8 imcBclk; + UINT8 spdCrcCheck; + UINT8 TrainingResultOffsetFunctionEnable; + UINT16 OffsetTxDq; + UINT16 OffsetRxDq; + UINT16 OffsetTxVref; + UINT16 OffsetRxVref; + UINT16 OffsetCmdAll; + UINT16 OffsetCmdVref; + UINT16 OffsetCtlAll; + UINT8 PmemCaching; + UINT8 tRRD_L; + UINT8 turnaroundOptDdrt; + UINT8 NvmdimmPerfConfig; // NVMDIMM Performance rela= ted + UINT8 AepOnSystem; + UINT8 NgnEccExitCorr; + UINT8 NgnArsPublish; + UINT16 NgnAveragePower; + UINT8 NgnThrottleTemp; + UINT8 AppDirectMemoryHole; + UINT8 LatchSystemShutdownState; + UINT8 EliminateDirectoryInFarMemory; + UINT8 NvmdimmPowerCyclePolicy; + UINT8 ShortStroke2GB; + UINT8 Reserved29; + UINT8 Reserved30; + UINT8 Reserved31; + UINT8 NvmQos; + UINT8 ExtendedType17; + UINT8 Force1ChWayFM; + UINT8 DisableDirForAppDirect; + UINT8 NvmMediaStatusException; + UINT8 sck4ch0; + UINT8 sck4ch1; + UINT8 sck4ch2; + UINT8 sck4ch3; + UINT8 sck4ch4; + UINT8 sck4ch5; + UINT8 sck5ch0; + UINT8 sck5ch1; + UINT8 sck5ch2; + UINT8 sck5ch3; + UINT8 sck5ch4; + UINT8 sck5ch5; + UINT8 sck6ch0; + UINT8 sck6ch1; + UINT8 sck6ch2; + UINT8 sck6ch3; + UINT8 sck6ch4; + UINT8 sck6ch5; + UINT8 sck7ch0; + UINT8 sck7ch1; + UINT8 sck7ch2; + UINT8 sck7ch3; + UINT8 sck7ch4; + UINT8 sck7ch5; + UINT8 Reserved32; + UINT8 EadrSupport; + UINT8 Reserved33; + UINT8 FactoryResetClear; + UINT8 LsxImplementation; + UINT32 NvdimmSmbusMaxAccessTime; + UINT32 NvdimmSmbusReleaseDelay; + UINT8 Reserved34; + UINT8 Reserved35; + UINT8 TrfcPerfEnable; + UINT8 PanicWm; + UINT32 AdvMemTestOptions; + UINT8 AdvMemTestResetList; + UINT8 AdvMemTestCondition; + UINT16 AdvMemTestCondVdd; + UINT8 AdvMemTestCondTwr; + UINT16 AdvMemTestCondTrefi; + UINT32 AdvMemTestCondPause; + UINT16 OffsetRecEn; + UINT8 RcvenAve; + UINT8 allowCorrectableMemTestError; + UINT8 AdrPatrolScrubDisable; + UINT8 PatrolErrorDowngradeEn; + UINT8 BankXorEnable; + UINT8 AdvMemTestRetryAfterRepair; +} SOCKET_MEMORY_CONFIGURATION; + +#pragma pack() + +#endif + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMpLin= kVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMpLi= nkVariable.h new file mode 100644 index 0000000000..79cd5a05ab --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMpLinkVariab= le.h @@ -0,0 +1,173 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_MP_LINK_CONFIG_DATA_H__ +#define __SOCKET_MP_LINK_CONFIG_DATA_H__ + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketMpLinkVariableGuid; +#define SOCKET_MP_LINK_CONFIGURATION_NAME L"SocketMpLinkConfig" + +#pragma pack(1) +typedef struct { + // SKXTODO: rename to Kti when removing HSX code + UINT8 QpiSetupNvVariableStartTag; // This must be the very first one o= f the whole KTI Setup NV variable! + + // + // Used by the PciHostBridge DXE driver, these variables don't need to b= e exposed through setup options + // The variables are used as a communication vehicle from the PciHostBri= dge DXE driver to an OEM hook + // which updates the KTI resource map + // + // + // KTI host structure inputs + // + UINT8 BusRatio[MAX_SOCKET]; + UINT8 LegacyVgaSoc; // Socket that claims the legacy VGA range;= valid values are 0-3; 0 is default. + UINT8 LegacyVgaStack; // Stack that claims the legacy VGA range; = valid values are 0-3; 0 is default. + UINT8 MmioP2pDis; // 1 - Disable; 0 - Enable + UINT8 DebugPrintLevel; // Bit 0 - Fatal, Bit1 - Warning, Bit2 - In= fo Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable + UINT8 DegradePrecedence; // Use DEGRADE_PRECEDENCE definition; TOPOL= OGY_PRECEDENCE is default + + // + // Phy/Link Layer Options + // + UINT8 QpiLinkSpeedMode; // Link speed mode selection; 0 - Slow = Speed; 1- Full Speed + UINT8 QpiLinkSpeed; // One of SPEED_REC_96GT, SPEED_REC_104= GT, MAX_KTI_LINK_SPEED (default), FREQ_PER_LINK + UINT8 KtiLinkL0pEn; // 0 - Disable, 1 - Enable, 2- Auto (de= fault) + UINT8 KtiLinkL1En; // 0 - Disable, 1 - Enable, 2- Auto (de= fault) + UINT8 KtiFailoverEn; // 0 - Disable, 1 - Enable, 2- Auto (de= fault) + UINT8 KtiLbEn; // 0 - Disable(default), 1 - Enable + UINT8 KtiCrcMode; // 0 - 8 bit CRC 1 - 16 bit CRC Mode + UINT8 QpiCpuSktHotPlugEn; // 0 - Disable (default), 1 - Enable + UINT8 KtiCpuSktHotPlugTopology; // 0 - 4S Topology (default), 1 - 8S To= pology + UINT8 KtiSkuMismatchCheck; // 0 - No, 1 - Yes (default) + UINT8 KtiLinkVnaOverride; // 0x100 - per link, 0xff - max (defaul= t), 0x00 - min + UINT8 SncEn; // 0 - Disable (default), 1 - Enable + UINT8 IoDcMode; // 0 - Disable IODC, 1 - AUTO (default= ), 2 - IODC_EN_REM_INVITOM_PUSH, 3 - IODC_EN_REM_INVITOM_ALLOCFLOW + // 4 - IODC_EN_REM_INVITOM_ALLOC_NONALL= OC, 5 - IODC_EN_REM_INVITOM_AND_WCILF + UINT8 DirectoryModeEn; // 0 - Disable; 1 - Enable (default) + UINT8 XptPrefetchEn; // XPT Prefetch : 1 - Enable (Default)= ; 0 - Disable + UINT8 KtiPrefetchEn; // KTI Prefetch : 1 - Enable (Default)= ; 0 - Disable + UINT8 RdCurForXptPrefetchEn; // RdCur for XPT Prefetch : 0 - Disabl= e, 1 - Enable, 2- Auto (default) + UINT8 IrqThreshold; // KTI IRQ Threshold setting + UINT8 TscSyncEn; // TSC Sync Enable: 0 - Disable; 1 - En= able; 2 - AUTO (default) + UINT8 StaleAtoSOptEn; // HA A to S directory optimization + UINT8 LLCDeadLineAlloc; // Never fill dead lines in LLC: 1 - En= able, 0 - Disable + + UINT8 Reserved1; + UINT8 Reserved2; + UINT8 Reserved3; + UINT8 Reserved4; + UINT8 Reserved5; + UINT8 Reserved6; + UINT8 Reserved7; + UINT8 Reserved8; + UINT8 Reserved9; + UINT8 Reserved10; + UINT8 Reserved11; + UINT8 Reserved12; + UINT8 Reserved13; + UINT8 Reserved14; + UINT8 Reserved15; + UINT8 Reserved16; + UINT8 Reserved17; + UINT8 Reserved18; + + +#define CSICPUPRTVARIABLE(x) x##KtiPortDisable;x##KtiLinkSpeed;x##K= tiLinkVnaOverride; + + UINT8 KtiCpuPerPortStartTag; + CSICPUPRTVARIABLE(UINT8 Cpu0P0) + CSICPUPRTVARIABLE(UINT8 Cpu0P1) + CSICPUPRTVARIABLE(UINT8 Cpu0P2) +#if MAX_SOCKET > 1 + CSICPUPRTVARIABLE(UINT8 Cpu1P0) + CSICPUPRTVARIABLE(UINT8 Cpu1P1) + CSICPUPRTVARIABLE(UINT8 Cpu1P2) +#endif +#if MAX_SOCKET > 2 + CSICPUPRTVARIABLE(UINT8 Cpu2P0) + CSICPUPRTVARIABLE(UINT8 Cpu2P1) + CSICPUPRTVARIABLE(UINT8 Cpu2P2) +#endif +#if MAX_SOCKET > 3 + CSICPUPRTVARIABLE(UINT8 Cpu3P0) + CSICPUPRTVARIABLE(UINT8 Cpu3P1) + CSICPUPRTVARIABLE(UINT8 Cpu3P2) +#endif +#if (MAX_SOCKET > 4) + CSICPUPRTVARIABLE(UINT8 Cpu4P0) + CSICPUPRTVARIABLE(UINT8 Cpu4P1) + CSICPUPRTVARIABLE(UINT8 Cpu4P2) +#endif +#if (MAX_SOCKET > 5) + CSICPUPRTVARIABLE(UINT8 Cpu5P0) + CSICPUPRTVARIABLE(UINT8 Cpu5P1) + CSICPUPRTVARIABLE(UINT8 Cpu5P2) +#endif +#if (MAX_SOCKET > 6) + CSICPUPRTVARIABLE(UINT8 Cpu6P0) + CSICPUPRTVARIABLE(UINT8 Cpu6P1) + CSICPUPRTVARIABLE(UINT8 Cpu6P2) +#endif +#if (MAX_SOCKET > 7) + CSICPUPRTVARIABLE(UINT8 Cpu7P0) + CSICPUPRTVARIABLE(UINT8 Cpu7P1) + CSICPUPRTVARIABLE(UINT8 Cpu7P2) +#endif + +#define CSICPUPRTDFXVARIABLE(x) x##ReservedA;x##ReservedB;x##ReservedC;= x##ReservedD; + + UINT8 Reserved19; + CSICPUPRTDFXVARIABLE(UINT8 Cpu0P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu0P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu0P2) +#if MAX_SOCKET > 1 + CSICPUPRTDFXVARIABLE(UINT8 Cpu1P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu1P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu1P2) +#endif +#if MAX_SOCKET > 2 + CSICPUPRTDFXVARIABLE(UINT8 Cpu2P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu2P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu2P2) +#endif +#if MAX_SOCKET > 3 + CSICPUPRTDFXVARIABLE(UINT8 Cpu3P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu3P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu3P2) +#endif +#if MAX_SOCKET > 4 + CSICPUPRTDFXVARIABLE(UINT8 Cpu4P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu4P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu4P2) +#endif +#if MAX_SOCKET > 5 + CSICPUPRTDFXVARIABLE(UINT8 Cpu5P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu5P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu5P2) +#endif +#if MAX_SOCKET > 6 + CSICPUPRTDFXVARIABLE(UINT8 Cpu6P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu6P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu6P2) +#endif +#if MAX_SOCKET > 7 + CSICPUPRTDFXVARIABLE(UINT8 Cpu7P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu7P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu7P2) +#endif + + UINT8 QpiSetupNvVariableEndTag; // This must be the last one of the wh= ole KTI Setup NV variable +} SOCKET_MP_LINK_CONFIGURATION; + +#pragma pack() + +#endif // __SOCKET_MP_LINK_CONFIG_DATA_H__ + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPciRe= sourceData.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPci= ResourceData.h new file mode 100644 index 0000000000..5c8ca9fd74 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPciResourceD= ata.h @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ +#define __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ + + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketPciResourceDataGuid; +#define SOCKET_PCI_RESOURCE_CONFIGURATION_DATA_NAME L"SocketPciResourceCon= figData" + +#pragma pack(1) +typedef struct { + // + // Used by the PciHostBridge DXE driver, these variables don't need to b= e exposed through setup options + // The variables are used as a communication vehicle from the PciHostBri= dge DXE driver to an OEM hook + // which updates the KTI resource map + // + UINT16 PciSocketIoBase[MAX_SOCKET]; + UINT16 PciSocketIoLimit[MAX_SOCKET]; + UINT32 PciSocketMmiolBase[MAX_SOCKET]; + UINT32 PciSocketMmiolLimit[MAX_SOCKET]; + UINT64 PciSocketMmiohBase[MAX_SOCKET]; + UINT64 PciSocketMmiohLimit[MAX_SOCKET]; + UINT16 PciResourceIoBase[TOTAL_IIO_STACKS]; + UINT16 PciResourceIoLimit[TOTAL_IIO_STACKS]; + UINT32 PciResourceMem32Base[TOTAL_IIO_STACKS]; + UINT32 PciResourceMem32Limit[TOTAL_IIO_STACKS]; + UINT64 PciResourceMem64Base[TOTAL_IIO_STACKS]; + UINT64 PciResourceMem64Limit[TOTAL_IIO_STACKS]; +} SOCKET_PCI_RESOURCE_CONFIGURATION_DATA; +#pragma pack() + +#endif // __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPower= managementVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/S= ocketPowermanagementVariable.h new file mode 100644 index 0000000000..80491fcf89 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPowermanagem= entVariable.h @@ -0,0 +1,227 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__ +#define __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__ + + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketPowermanagementVarGuid; +#define SOCKET_POWERMANAGEMENT_CONFIGURATION_NAME L"SocketPowerManagementC= onfig" + +#define NUM_CST_LAT_MSR 3 + +#pragma pack(1) + +typedef struct { + UINT8 LOT26UnusedVrPowerDownEnable; + UINT8 WFRWAEnable; + UINT8 UFSDisable; // Allow Mailbox Command to PC= U_MISC_CONFIG Bit[28] + UINT8 ProcessorEistEnable; // EIST or GV3 setup option + + // Config TDP + UINT8 ConfigTDP; + UINT8 ConfigTDPLevel; + + // Individual controls for ACPI sleep states + // ** These can be overridden by AcpiSleepState because these knobs are = not available to CRB ** + // + UINT8 AcpiS3Enable; + UINT8 AcpiS4Enable; + + // + //HWPM starts + // + UINT8 ProcessorHWPMEnable; + UINT8 ProcessorAutonomousCstateEnable; + UINT8 ProcessorHWPMInterrupt; + UINT8 ProcessorEPPEnable; + UINT8 ProcessorEppProfile; + UINT8 ProcessorAPSrocketing; + UINT8 ProcessorScalability; + UINT8 ProcessorRaplPrioritization; + UINT8 ProcessorOutofBandAlternateEPB; + // + //HWPM ends + // + UINT8 PStateDomain; // P State Domain + UINT8 ProcessorEistPsdFunc; // EIST/PSD Function select op= tion + UINT8 ProcessorSinglePCTLEn; // PCPS - SINGLE_PCTL select o= ption + UINT8 ProcessorSPD; // PCPS - SPD select option + UINT8 BootPState; // Boot Performance Mode + + // + // Prioritized Base Frequency + // + UINT8 ProcessorActivePbf; // PBF + UINT8 ProcessorConfigurePbf; // PBF High Priority Cores + + // + // Processor Control + // + UINT8 TurboMode; + UINT8 EnableXe; + + //OverClocking + UINT8 OverclockingLock; + + UINT8 TurboRatioLimitRatio[8]; + UINT8 TurboRatioLimitCores[8]; + + UINT8 C2C3TT; + UINT8 DynamicL1; // Enabling Dynamic L1 + UINT8 ProcessorCcxEnable; // Enabling CPU C states of pr= ocessor + UINT8 PackageCState; // Package C-State Limit + UINT8 C3Enable; // Enable/Disable NHM C3(ACPI = C2) report to OS + UINT8 C6Enable; // Enable/Disable NHM C6(ACPI = C3) report to OS + UINT8 ProcessorC1eEnable; // Enabling C1E state of proce= ssor + UINT8 OSCx; // ACPI C States + + UINT8 CStateLatencyCtrlValid[NUM_CST_LAT_MSR]; // C_STATE_LATENC= Y_CONTROL_x.Valid + UINT8 CStateLatencyCtrlMultiplier[NUM_CST_LAT_MSR]; // C_STATE_LATENC= Y_CONTROL_x.Multiplier + UINT16 CStateLatencyCtrlValue[NUM_CST_LAT_MSR]; // C_STATE_LATENC= Y_CONTROL_x.Value + + UINT8 TStateEnable; // T states enable? + UINT8 OnDieThermalThrottling; // Throtte ratio + UINT8 ProchotLock; + UINT8 EnableProcHot; + UINT8 EnableThermalMonitor; + UINT8 ProchotResponse; + UINT8 EETurboDisable; + UINT8 SapmctlValCtl; + UINT8 PwrPerfTuning; + UINT8 AltEngPerfBIAS; + UINT8 PwrPerfSwitch; + UINT8 WorkLdConfig; + UINT16 EngAvgTimeWdw1; + + UINT8 ProchotResponseRatio; + UINT8 TCCActivationOffset; + + UINT8 P0TtlTimeLow1; + UINT8 P0TtlTimeHigh1; + + UINT8 PkgCLatNeg; + UINT8 LTRSwInput; + UINT8 SAPMControl; + UINT8 CurrentConfig; + UINT8 PriPlnCurCfgValCtl; + UINT8 Psi3Code; + UINT16 CurrentLimit; + + UINT8 Psi3Thshld; + UINT8 Psi2Code; + UINT8 Psi2Thshld; + UINT8 Psi1Code; + UINT8 Psi1Thshld; + + //Power Management Setup options + UINT8 PkgCstEntryValCtl; + + // PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601 + UINT8 PpcccLock; + + UINT8 SnpLatVld; + UINT8 SnpLatOvrd; + UINT8 SnpLatMult; + UINT16 SnpLatVal; + UINT16 NonSnpLatVld; + UINT8 NonSnpLatOvrd; + UINT8 NonSnpLatMult; + UINT16 NonSnpLatVal; + + // DYNAMIC_PERF_POWER_CTL (CSR 1:30:2:0x64) + UINT8 EepLOverride; + UINT8 EepLOverrideEn; + UINT8 ITurboOvrdEn; + UINT8 CstDemotOvrdEN; + UINT8 TrboDemotOvrdEn; + UINT8 UncrPerfPlmtOvrdEn; + UINT8 EetOverrideEn; + UINT8 IoBwPlmtOvrdEn; + UINT8 ImcApmOvrdEn; // unused + UINT8 IomApmOvrdEn; + UINT8 QpiApmOvrdEn; + UINT8 PerfPLmtThshld; + + // SAPMCTL_CFG (CSR 1:30:1:0xB0) + UINT8 Iio0PkgcClkGateDis[MAX_SOCKET]; //Bit[0] + UINT8 Iio1PkgcClkGateDis[MAX_SOCKET]; //Bit[1] + UINT8 Iio2PkgcClkGateDis[MAX_SOCKET]; //Bit[2] + UINT8 Kti01PkgcClkGateDis[MAX_SOCKET]; //Bit[3] + UINT8 Kti23PkgcClkGateDis[MAX_SOCKET]; //Bit[4] + UINT8 P0pllOffEna[MAX_SOCKET]; //Bit[16] + UINT8 P1pllOffEna[MAX_SOCKET]; //Bit[17] + UINT8 P2pllOffEna[MAX_SOCKET]; //Bit[18] + UINT8 Mc0pllOffEna[MAX_SOCKET]; //Bit[22] + UINT8 Mc1pllOffEna[MAX_SOCKET]; //Bit[23] + UINT8 Mc0PkgcClkGateDis[MAX_SOCKET]; //Bit[6] + UINT8 Mc1PkgcClkGateDis[MAX_SOCKET]; //Bit[7] + UINT8 Kti01pllOffEna[MAX_SOCKET]; //Bit[19] + UINT8 Kti23pllOffEna[MAX_SOCKET]; //Bit[20] + UINT8 SetvidDecayDisable[MAX_SOCKET]; //Bit[30]; + UINT8 SapmCtlLock[MAX_SOCKET]; //Bit[31]; + + // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4) + UINT8 PerfPLimitClip; + UINT8 PerfPLimitEn; + + // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4) >=3D HSX C stepping + UINT8 PerfPlimitDifferential; + UINT8 PerfPLimitClipC; + + // SKX: PKG_CST_ENTRY_CRITERIA_MASK2 (CSR 1:30:2:0x90) + UINT8 Kti0In[MAX_SOCKET]; + UINT8 Kti1In[MAX_SOCKET]; + UINT8 Kti2In[MAX_SOCKET]; + + // SKX: PKG_CST_ENTRY_CRITERIA_MASK (CSR 1:30:2:0x8c) + UINT8 PcieIio0In[MAX_SOCKET]; + UINT8 PcieIio1In[MAX_SOCKET]; + UINT8 PcieIio2In[MAX_SOCKET]; + UINT8 PcieIio3In[MAX_SOCKET]; + UINT8 PcieIio4In[MAX_SOCKET]; + UINT8 PcieIio5In[MAX_SOCKET]; + + UINT8 FastRaplDutyCycle; + UINT8 TurboPowerLimitLock; + UINT8 TurboPowerLimitCsrLock; + UINT8 PowerLimit1En; + UINT32 PowerLimit1Power; + UINT8 PowerLimit1Time; + UINT8 PkgClmpLim1; + UINT8 PowerLimit2En; + UINT32 PowerLimit2Power; + UINT8 PkgClmpLim2; + UINT8 PowerLimit2Time; + + UINT8 UsePmaxOffsetTable; + UINT8 PmaxSign; + UINT8 PmaxOffset; + + //XTU 3.0 + + UINT8 MaxEfficiencyRatio[MAX_SOCKET]; + UINT8 MaxNonTurboRatio[MAX_SOCKET]; + + // use SPT workarounds - B2P cmd MISC_WORKAROUND_ENABLE + UINT8 SPTWorkaround; + UINT8 VccSAandVccIOdisable; + + UINT8 AvxIccpLevel; + UINT8 IntelSpeedSelectSupport; // Intel Speed Select (ISS) + +} SOCKET_POWERMANAGEMENT_CONFIGURATION; +#pragma pack() + +#endif + + + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketProce= ssorCoreVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/Soc= ketProcessorCoreVariable.h new file mode 100644 index 0000000000..e164967fba --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketProcessorCor= eVariable.h @@ -0,0 +1,115 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__ +#define __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__ + + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketProcessorCoreVarGuid; +#define SOCKET_PROCESSORCORE_CONFIGURATION_NAME L"SocketProcessorCoreConfi= g" + +#pragma pack(1) + +typedef struct { + + UINT8 CpuidMaxValue; + UINT8 ExecuteDisableBit; + + UINT8 PchTraceHubEn; // PCH TRACE HUB + UINT8 C1AutoDemotion; // C1 Auto Demotion + UINT8 C3AutoDemotion; // C3 Auto Demotion + UINT8 ProcessorHyperThreadingDisable; // Hyper Threading [ALL] + UINT8 ProcessorLtsxEnable; // Enabling TXT + UINT8 ProcessorVmxEnable; // Enabling VMX + UINT8 ProcessorSmxEnable; // Enabling SMX + UINT8 ProcessorMsrLockControl; // MSR Lock Bit Control + UINT8 DebugInterface; // IA32_DEBUG_INTERFACE_MSR + UINT8 ThreeStrikeTimer; // Disable 3strike timer + UINT8 FastStringEnable; // Fast String + UINT8 MachineCheckEnable; // Machine Check + UINT8 MlcStreamerPrefetcherEnable; // Hardware Prefetch + UINT8 MlcSpatialPrefetcherEnable; // Adjacent Cache Line Prefetch + UINT8 DCUStreamerPrefetcherEnable; // DCU Streamer Prefetcher + UINT8 DCUIPPrefetcherEnable; // DCU IP Prefetcher + UINT8 DCUModeSelection; // DCU Mode Selection + UINT8 ProcessorX2apic; // Enable Processor XAPIC + UINT8 ForceX2ApicIds; // Force to use > 8bit ApicId + UINT8 BspSelection; // Select BSP + UINT8 IedSize; // IED size + UINT8 IedTraceSize; // IED trace size + UINT8 TsegSize; // TSEG size + UINT8 AllowMixedPowerOnCpuRatio; // Allow Mixed PowerOn CpuRatio + UINT8 CheckCpuBist; // check and disable BIST fail= e core or ignore + UINT8 ProcessorFlexibleRatio; // Non-Turbo Mode Processor Co= re Ratio Multiplier + UINT8 ProcessorFlexibleRatioOverrideEnable; // Non-Turbo Mode = Processor Core Ratio Multiplier Enable + UINT8 Reserved2; // Reserved 2 + UINT8 ForcePhysicalModeEnable; // Force physical destionation= mode + UINT8 LlcPrefetchEnable; // LLC Prefetch + UINT8 ProcessorVirtualWireMode; + + UINT8 AesEnable; + UINT8 PpinControl; // PPIN Control MSR + UINT8 LockChipset; // Lock Chipset + UINT8 SkipStopPbet; // Skip StopPbet + + UINT8 BiosAcmErrorReset; // Disable LT-SX and reset sys= tem when BIOS ACM error occurs + UINT8 AcmType; // 0x80 =3D debug signed ACM; = 0x40 =3D NPW production signed ACM; 0x00 =3D PW production signed ACM + + + UINT64 CoreDisableMask[MAX_SOCKET]; // one for each CPU socket + // IOT/OCLA configs +#ifndef OCLA_TOR_ENTRY_MAX + #define OCLA_TOR_ENTRY_MIN 0 + #define OCLA_TOR_ENTRY_MAX 0x11 // 15 or 17 depending on Iso= ch on/off + #define OCLA_TOR_ENTRY_DEFAULT 1 + #define OCLA_WAY_MIN 0 + #define OCLA_WAY_MAX 8 // max 8 LLC ways out of 11 = can be reserved for OCLA + #define OCLA_WAY_DEFAULT 1 +#endif + UINT8 IotEn[MAX_SOCKET]; + UINT8 OclaMaxTorEntry[MAX_SOCKET]; + UINT8 OclaMinWay[MAX_SOCKET]; + UINT32 IioLlcWaysMask; // MSR CBO_SLICE0_CR_IIO= _LLC_WAYS bitmask. - Only Bits[22:0] are used + UINT32 ExpandedIioLlcWaysMask; // MSR INGRESS_SPARE[10:= 0] bitmask. - Only Bits[10:0] are used + UINT32 RemoteWaysMask; // MSR INGRESS_SPARE[26:= 16] bitmask. - Only Bits[10:0] are used + UINT32 QlruCfgMask_Lo; // MSR VIRTUAL_MSR_CR_QL= RU_CONFIG bitmask - Lower 32-bit + UINT32 QlruCfgMask_Hi; // MSR VIRTUAL_MSR_CR_QL= RU_CONFIG bitmask - Higher 32-bit + + + UINT8 PCIeDownStreamPECIWrite; + +// +// Targeted Smi Support +// + UINT8 TargetedSmi; +// +// eSMM Save State Mode +// + UINT8 eSmmSaveState; + + UINT8 PeciInTrustControlBit; //On Setup + + UINT8 Poison; + UINT8 Viral; + UINT8 EVMode; + UINT8 SmbusErrorRecovery; + UINT8 RdtCatOpportunisticTuning; + UINT8 CpuDbpEnable; // Enable/Disable DBP-F + UINT8 L2RfoPrefetchDisable; // L2 RFO Prefetch + UINT8 MonitorMwaitEnabled; + UINT8 MonitorMwaitSwitchPresent; +} SOCKET_PROCESSORCORE_CONFIGURATION; +#pragma pack() + +#endif + + + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketVaria= ble.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketVariable.h new file mode 100644 index 0000000000..391bfb4e1e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketVariable.h @@ -0,0 +1,35 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_CONFIG_DATA_H__ +#define __SOCKET_CONFIG_DATA_H__ + +#include +#include "SocketConfiguration.h" +#include +#include +#include +#include +#include +#include + +#pragma pack(1) + +typedef struct { + SOCKET_IIO_CONFIGURATION IioConfig; + SOCKET_COMMONRC_CONFIGURATION CommonRcConfig; + SOCKET_MP_LINK_CONFIGURATION CsiConfig; + SOCKET_MEMORY_CONFIGURATION MemoryConfig; + SOCKET_POWERMANAGEMENT_CONFIGURATION PowerManagementConfig; + SOCKET_PROCESSORCORE_CONFIGURATION SocketProcessorCoreConfiguration; +} SOCKET_CONFIGURATION; + + + +#pragma pack() +#endif + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CpuPpmLi= b.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CpuPpmLib.h new file mode 100644 index 0000000000..4773837042 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CpuPpmLib.h @@ -0,0 +1,707 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_PPM_LIB_H_ +#define _CPU_PPM_LIB_H_ + + +#include +#include +#include +#include "SysHost.h" +#include "UncoreCommonIncludes.h" + +#define NUM_CST_LAT_MSR 3 + +// +// Value definition for CpuPCPSCtrl +// +#define PCD_CPU_PCPS_SINGLEPCTL 0x00000004 +#define PCD_CPU_PCPS_SPD 0x00000008 +#define PCD_CPU_PCPS_PSTATEDOMAIN 0x00000010 + +// Bits configuration for PcdAdvPwrMgtFlags +#define PCD_CPU_PKG_CST_ENTRY_VAL_CTL 0x00000001 +#define PCD_CPU_SAPM_CTL_VAL_CTL 0x00000002 +#define PCD_CPU_SKIP_PKG_CST_ENTRY 0x00000004 +#define PCD_CPU_SW_LTR_OVRD_CTL 0x00000008 +#define PCD_CPU_PRI_PLN_CURR_CFG_CTL 0x00000010 +#define PCD_CPU_CURRENT_CONFIG 0x00000020 +#define PCU_CPU_EFFICIENT_BOOT 0x00000040 +#define CPU_MSR_LOCK 0x00000080 +#define MPLL_OFF_ENA_AUTO 0x00000100 +#define DYNAMIC_L1_DISABLE 0x00000200 +#define SPT_PCH_WORKAROUND 0x00000400 +#define TURBO_LIMIT_CSR_LOCK 0x00000800 +#define VCCSA_VCCIO_DISABLE 0x00001000 + + +// PCU_CR_PMAX_CONFIG bit definition +#define PCU_CR_PMAX_CFG_OFFSET_SHIFT 0 +#define PCU_CR_PMAX_CFG_LOCK_SHIFT 31 +#define PCU_CR_PMAX_CFG_OFFSET (0x1f << PCU_CR_PMAX_CFG_OFFSET_SH= IFT) // Bits 4:0 +#define USER_PMAX_USE_OFFSET_TABLE BIT5 +#define USER_PMAX_NEGATIVE_BIT BIT4 +#define USER_PMAX_VALUE_BIT_MASK 0x0F = // Bits 3:0 +#define PCU_CR_PMAX_CFG_LOCK (0x1 << PCU_CR_PMAX_CFG_LOCK_SHIFT= ) // Bit 31 + +// DYNAMIC_PERF_POWER_CTL bit definition +#define EEP_L_OVERRIDE_SHIFT 26 // Bit 29:26 +#define EEP_L_OVERRIDE_ENABLE_SHIFT 25 // Bit 25 +#define I_TURBO_OVERRIDE_ENABLE_SHIFT 24 // Bit 24 +#define CST_DEMOTION_OVERRIDE_ENABLE_SHIFT 23 // Bit 23 +#define TURBO_DEMOTION_OVERRIDE_ENABLE_SHIFT 22 // Bit 22 +#define UNCORE_PERF_PLIMIT_OVERRIDE_ENABLE_SHIFT 20 // Bit 20 +#define EET_OVERRIDE_ENABLE_SHIFT 18 // Bit 18 +#define IO_BW_PLIMIT_OVERRIDE_ENABLE_SHIFT 15 // Bit 15 +#define IMC_APM_OVERRIDE_ENABLE_SHIFT 10 // Bit 10 +#define IOM_APM_OVERRIDE_ENABLE_SHIFT 5 // Bit 5 +#define QPI_APM_OVERRIDE_ENABLE_SHIFT 0 // Bit 0 +#define EEP_L_OVERRIDE (0xf << EEP_L_OVERRIDE_= SHIFT) // Bit 29:26 +#define EEP_L_OVERRIDE_ENABLE (1 << EEP_L_OVERRIDE_EN= ABLE_SHIFT) // Bit 25 +#define I_TURBO_OVERRIDE_ENABLE (1 << I_TURBO_OVERRIDE_= ENABLE_SHIFT) // Bit 24 +#define CST_DEMOTION_OVERRIDE_ENABLE (1 << CST_DEMOTION_OVER= RIDE_ENABLE_SHIFT) // Bit 23 +#define TURBO_DEMOTION_OVERRIDE_ENABLE (1 << TURBO_DEMOTION_OV= ERRIDE_ENABLE_SHIFT) // Bit 22 +#define UNOCRE_PERF_PLIMIT_OVERRIDE_ENABLE (1 << UNCORE_PERF_PLIMI= T_OVERRIDE_ENABLE_SHIFT) // Bit 20 +#define EET_OVERRIDE_ENABLE (1 << EET_OVERRIDE_ENAB= LE_SHIFT) // Bit 18 +#define IO_BW_PLIMIT_OVERRIDE_ENABLE (1 << IO_BW_PLIMIT_OVER= RIDE_ENABLE_SHIFT) // Bit 15 +#define IMC_APM_OVERRIDE_ENABLE (1 << IMC_APM_OVERRIDE_= ENABLE_SHIFT) // Bit 10 +#define IOM_APM_OVERRIDE_ENABLE (1 << IOM_APM_OVERRIDE_= ENABLE_SHIFT) // Bit 5 +#define QPI_APM_OVERRIDE_ENABLE (1 << QPI_APM_OVERRIDE_= ENABLE_SHIFT) // Bit 0 +#define DYNAMIC_PERF_POWER_CTL_MASK (0x3C000000 + UNOCRE_PERF_PLIMIT_OVER= RIDE_ENABLE + EET_OVERRIDE_ENABLE + IO_BW_PLIMIT_OVERRIDE_ENABLE + IMC_APM_= OVERRIDE_ENABLE + IOM_APM_OVERRIDE_ENABLE + QPI_APM_OVERRIDE_ENABLE) + +// CSR_PCIE_ILTR_OVRD (CSR 1:10:1:78) +// SW_LTR_OVRD (MSR 0xa02) -- not used +//CSR_PCIE_ILTR_OVRD bit definition +#define SNOOP_LATENCY_VLD_SHIFT 31 = // Bits 31 +#define FORCE_SNOOP_OVRD_SHIFT 30 = // Bits 30 +#define SNOOP_LATENCY_MUL_SHIFT 26 = // Bits 28:26 +#define SNOOP_LATENCY_Value_SHIFT 16 = // Bits 25:16 +#define NON_SNOOP_LATENCY_VLD_SHIFT 15 = // Bits 15 +#define FORCE_NON_SNOOP_OVRD_SHIFT 14 = // Bits 14 +#define NON_SNOOP_LATENCY_MUL_SHIFT 10 = // Bits 12:10 +#define NON_SNOOP_LATENCY_Value_SHIFT 0 = // Bits 9:0 +#define SNOOP_LATENCY_VLD_MASK (1 << SNOOP_LATENCY_VLD_S= HIFT) // Bits 31 +#define FORCE_SNOOP_OVRD_MASK (1 << FORCE_SNOOP_OVRD_SH= IFT) // Bits 30 +#define SNOOP_LATENCY_MUL_MASK (0x7 << SNOOP_LATENCY_MUL= _SHIFT) // Bits 28:26 +#define SNOOP_LATENCY_Value_MASK (0x3FF << SNOOP_LATENCY_V= alue_SHIFT) // Bits 25:16 +#define NON_SNOOP_LATENCY_VLD_MASK (1 << NON_SNOOP_LATENCY_V= LD_SHIFT) // Bits 15 +#define FORCE_NON_SNOOP_OVRD_MASK (1 << FORCE_NON_SNOOP_OVR= D_SHIFT) // Bits 14 +#define NON_SNOOP_LATENCY_MUL_MASK (0x7 << NON_SNOOP_LATENCY= _MUL_SHIFT) // Bits 12:10 +#define NON_SNOOP_LATENCY_Value_MASK (0x3FF << NON_SNOOP_LATENCY_Value_SH= IFT) // Bits 9:0 +#define SW_LTR_OVRD_CTL_MASK (SNOOP_LATENCY_VLD_MASK + FORCE_SNOOP_OVRD_= MASK + SNOOP_LATENCY_MUL_MASK + SNOOP_LATENCY_Value_MASK + \ + NON_SNOOP_LATENCY_VLD_MASK + FORCE_NON_SNOO= P_OVRD_MASK + NON_SNOOP_LATENCY_MUL_MASK + NON_SNOOP_LATENCY_Value_MASK) + +//CSR_PKG_CST_ENTRY_CRITERIA_MASK bit definition +#define DRAM_IN_SR_SHIFT 28 +#define QPI_2_IN_L1_SHIFT 27 +#define QPI_1_IN_L1_SHIFT 26 +#define QPI_0_IN_L1_SHIFT 25 +#define QPI_2_IN_L0S_SHIFT 24 +#define QPI_1_IN_L0S_SHIFT 23 +#define QPI_0_IN_L0S_SHIFT 22 +#define PCIE_IN_L1_SHIFT 11 +#define PCIE_IN_L0S_SHIFT 0 +#define DRAM_IN_SR (1 << DRAM_IN_SR_SHIFT) +#define QPI_2_IN_L1 (1 << QPI_2_IN_L1_SHIFT) +#define QPI_1_IN_L1 (1 << QPI_1_IN_L1_SHIFT) +#define QPI_0_IN_L1 (1 << QPI_0_IN_L1_SHIFT) +#define QPI_2_IN_L0S (1 << QPI_2_IN_L0S_SHIFT) +#define QPI_1_IN_L0S (1 << QPI_1_IN_L0S_SHIFT) +#define QPI_0_IN_L0S (1 << QPI_0_IN_L0S_SHIFT) +#define PCIE_IN_L1 (1 << PCIE_IN_L1_SHIFT) +#define PCIE_IN_L0S (1 << PCIE_IN_L0S_SHIFT) +#define PCIE_IN_LX_MASK 0x7FF // Bit[10:0] +#define MASK_PCIE_BITS 0xFFC00000 // clear bit= s 21:0 +// For SKX +#define KTI_2_IN_L1_SHIFT 2 +#define KTI_1_IN_L1_SHIFT 1 +#define KTI_0_IN_L1_SHIFT 0 +#define KTI_2_IN_L1 (1 << KTI_2_IN_L1_SHIFT) +#define KTI_1_IN_L1 (1 << KTI_1_IN_L1_SHIFT) +#define KTI_0_IN_L1 (1 << KTI_0_IN_L1_SHIFT) +#define MASK_PCIE_IN_L1_BITS 0xFF000000 // clear bits= 23:0 +#define SET_KTI_INPKGCENTRY (KTI_0_IN_L1 + KTI_1_IN_L1 = + KTI_2_IN_L1) +#define SET_PCIE_INPKGCENTRY 0xFFFFFF // set bits 2= 3:0 +#define SET_PCIEx_MASK 0xF +#define SET_DMI_MASK 0x1 + + +// CSR Perf PLIMIT bit definition for HSX <=3D B Stepping +#define I_TURBO_WAIT_PERIOD_SHIFT 19 = // Bits 31:19 +#define PERF_P_LIMIT_THRESHOLD_SHIFT 13 = // Bits 18:13 +#define I_TURBO_EN_SHIFT 12 = // Bit 12 +#define PERF_P_LIMIT_CLIP_SHIFT 6 = // Bits 11:6 +#define DISABLE_PERF_P_INPUT_SHIFT 5 = // Bit 5 +#define RESOLUTION_MODE_SHIFT 1 = // Bits 2:1 +#define REPERF_P_LIMIT_EN_SHIFT 0 = // Bit 0 +#define I_TURBO_WAIT_PERIOD (0x1fff << I_TURBO_WAIT_PERI= OD_SHIFT) // Bits 31:19 +#define PERF_P_LIMIT_THRESHOLD (0x3f << PERF_P_LIMIT_THRESH= OLD_SHIFT) // Bits 18:13 +#define I_TURBO_EN (1 << I_TURBO_EN_SHIFT) = // Bit 12 +#define PERF_P_LIMIT_CLIP (0x3f << PERF_P_LIMIT_CLIP_S= HIFT) // Bits 11:6 +#define DISABLE_PERF_P_INPUT (1 << DISABLE_PERF_P_INPUT_S= HIFT) // Bit 5 +#define RESOLUTION_MODE (3 << RESOLUTION_MODE_SHIFT)= // Bits 2:1 +#define REPERF_P_LIMIT_EN (1 << REPERF_P_LIMIT_EN_SHIF= T) // Bit 0 + +// CSR Perf PLIMIT bit definition for HSX >=3D C Stepping & SKX +#define PERF_PLIMIT_DIFFERENTIAL_SHIFT 15 = // Bits 17:15 +#define PERF_PLIMIT_DIFFERENTIAL (7 << PERF_PLIMIT_DIFFERENTI= AL_SHIFT) // Bits 17:15 +#define PERF_PLIMIT_CLIP_SHIFT 7 = // Bits 11:7 +#define PERF_PLIMIT_CLIP (0x1f << PERF_P_LIMIT_CLIP_S= HIFT) // Bits 11:7 +#define PERF_PLIMIT_THRESHOLD_SHIFT 1 = // Bits 5:1 +#define PERF_PLIMIT_THRESHOLD (0x1f << PERF_P_LIMIT_THRESH= OLD_SHIFT) // Bits 5:1 +#define REPERF_PLIMIT_EN_SHIFT 0 = // Bit 0 +#define REPERF_PLIMIT_EN (1 << REPERF_P_LIMIT_EN_SHIF= T) // Bit 0 +#define PERF_P_LIMIT_CTRL_MASK (PERF_PLIMIT_THRESHOLD + PERF_PLIMIT_CLIP = + PERF_PLIMIT_DIFFERENTIAL + REPERF_PLIMIT_EN) + +//CSR SAPMCTLbit definition +#define SAPMCTL_LOCK_SHIFT 31 = // Bit 31 for IVT/HSX/SKX +#define SETVID_DECAY_DISABLE_SHIFT 30 = // Bit 30 for IVT/KSX/SKX +#define QPI_L0S_PLL_SEN_ENABLE_SHIFT 29 = // Bit 29//Only for IVT +#define QPI_L0_PLL_SEN_ENABLE_SHIFT 28 = // Bit 28//Only for IVT +#define IIO_L0S_PLL_SEN_ENABLE_SHIFT 27 = // Bit 27//Only for IVT +#define IIO_L0_PLL_SEN_ENABLE_SHIFT 26 = // Bit 26//Only for IVT +#define QPI2_L0S_PLL_SEN_ENABLE_SHIFT 25 = // Bit 25//Only for IVT +#define QPI2_L0_PLL_SEN_ENABLE_SHIFT 24 = // Bit 24//Only for IVT +#define QPI2_PKGC_CLOCK_GATE_DISABLE_SHIFT 18 = // Bit 18//IVT/HSX +#define QPI01_PKGC_CLOCK_GATE_DISABLE_SHIFT 17 = // Bit 17//IVT/HSX +#define IIO_PKGC_CLOCK_GATE_DISABLE_SHIFT 16 = // Bit 16//IVT/HSX +#define MDLL_ON_DE_SHIFT 15 = // Bit 15//IVT/HSX +#define MPLL_ON_DE_SHIFT 14 = // Bit 14//IVT/HSX +#define SACG_MPLL_SHIFT 13 = // Bit 13//Only for IVT +#define NSWAKE_SREXIT_SHIFT 12 = // Bit 12//IVT/HSX +#define SACG_SREXIT_SHIFT 11 = // Bit 11//Only for IVT +#define MDLL_OFF_SEN_SHIFT 10 = // Bit 10//Only for IVT +#define MPLL_OFF_SEN_SHIFT 9 = // Bit 9//Only for IVT +#define SACG_SEN_SHIFT 8 = // Bit 8//Only for IVT +#define FORCE_PPLL_OFF_SHIFT 4 = // Bit 4 //IVT/HSX +#define QPLL_OFF_ENA_SHIFT 3 = // Bit 3//Only for IVT +#define PPLL_OFF_ENA_SHIFT 2 = // Bit 2//IVT/HSX +#define MPLL_OFF_ENA_SHIFT 1 = // Bit 1//IVT/HSX +#define SACG_ENA_SHIFT 0 = // Bit 0//Only for IVT +#define SAPMCTL_LOCK (1 << SAPMCTL_LOCK_SHIFT) = // Bit 31 +#define SETVID_DECAY_DISABLE (1 << SETVID_DECAY_DISABLE_= SHIFT) // Bit 30 +#define QPI_L0S_PLL_SEN_ENABLE (1 << QPI_L0S_PLL_SEN_ENABL= E_SHIFT) // Bit 29 +#define QPI_L0_PLL_SEN_ENABLE (1 << QPI_L0_PLL_SEN_ENABLE= _SHIFT) // Bit 28 +#define IIO_L0S_PLL_SEN_ENABLE (1 << IIO_L0S_PLL_SEN_ENABL= E_SHIFT) // Bit 27 +#define IIO_L0_PLL_SEN_ENABLE (1 << IIO_L0_PLL_SEN_ENABLE= _SHIFT) // Bit 26 +#define QPI2_L0S_PLL_SEN_ENABLE (1 << QPI2_L0S_PLL_SEN_ENAB= LE_SHIFT) // Bit 25 +#define QPI2_L0_PLL_SEN_ENABLE (1 << QPI2_L0_PLL_SEN_ENABL= E_SHIFT) // Bit 24 +#define QPI2_PKGC_CLOCK_GATE_DISABLE (1 << QPI2_PKGC_CLOCK_GATE_= DISABLE_SHIFT) // Bit 18//IVT +#define QPI01_PKGC_CLOCK_GATE_DISABLE (1 << QPI01_PKGC_CLOCK_GATE= _DISABLE_SHIFT) // Bit 17//IVT +#define IIO_PKGC_CLOCK_GATE_DISABLE (1 << IIO_PKGC_CLOCK_GATE_D= ISABLE_SHIFT) // Bit 16//IVT +#define MDLL_ON_DE (1 << MDLL_ON_DE_SHIFT) = // Bit 15 +#define MPLL_ON_DE (1 << MPLL_ON_DE_SHIFT) = // Bit 14 +#define SACG_MPLL (1 << SACG_MPLL_SHIFT) = // Bit 13 +#define NSWAKE_SREXIT (1 << NSWAKE_SREXIT_SHIFT) = // Bit 12 +#define SACG_SREXIT (1 << SACG_SREXIT_SHIFT) = // Bit 11 +#define MDLL_OFF_SEN (1 << MDLL_OFF_SEN_SHIFT) = // Bit 10 +#define MPLL_OFF_SEN (1 << MPLL_OFF_SEN_SHIFT) = // Bit 9 +#define SACG_SEN (1 << SACG_SEN_SHIFT) = // Bit 8 +#define FORCE_PPLL_OFF (1 << FORCE_PPLL_OFF_SHIFT)= // Bit 4 //IVT +#define QPLL_OFF_ENA (1 << QPLL_OFF_ENA_SHIFT) = // Bit 3 +#define PPLL_OFF_ENA (1 << PPLL_OFF_ENA_SHIFT) = // Bit 2 +#define MPLL_OFF_ENA (1 << MPLL_OFF_ENA_SHIFT) = // Bit 1 +#define SACG_ENA (1 << SACG_ENA_SHIFT) = // Bit 0 + +//CSR SAPMCTLbit definition for SKX +#define MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT 27 // Bit 27,= SKX +#define MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT 26 // Bit 26,= SKX +#define MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT 25 // Bit 25,= SKX +#define MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT 24 // Bit 24,= SKX +#define MEM_PLL_OFF_EN_SHIFT 22 // Bit 22,= 23, SKX +#define KTI_PLL_OFF_EN_SHIFT 19 // Bit 19,= 20, SKX +#define IIO_PLL_OFF_EN_SHIFT 16 // Bit 16,= 17,18, SKX +#define MC1_PKGC_CLK_GATE_DISABLE_SHIFT 7 // Bit 7, = SKX +#define MC0_PKGC_CLK_GATE_DISABLE_SHIFT 6 // Bit 6, = SKX +#define KTI23_PKGC_CLK_GATE_DISABLE_SHIFT 4 // Bit 4, = SKX +#define KTI01_PKGC_CLK_GATE_DISABLE_SHIFT 3 // Bit 3, = SKX +#define IIO012_PKGC_CLK_GATE_DISABLE_SHIFT 0 // Bit 0,1= ,2, SKX +#define MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE (1 << MC1_PKGC_DIG_VOLTAG= E_REDUCTION_DISABLE_SHIFT) // Bit 27, SKX +#define MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE (1 << MC0_PKGC_DIG_VOLTAG= E_REDUCTION_DISABLE_SHIFT) // Bit 26, SKX +#define MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE (1 << MC1_PKGC_IO_VOLTAGE= _REDUCTION_DISABLE_SHIFT) // Bit 25, SKX +#define MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE (1 << MC0_PKGC_IO_VOLTAGE= _REDUCTION_DISABLE_SHIFT) // Bit 24, SKX +#define MEM_PLL_OFF_EN (3 << MEM_PLL_OFF_EN_SHIF= T) // Bit 22,23, SKX +#define KTI_PLL_OFF_EN (3 << KTI_PLL_OFF_EN_SHIF= T) // Bit 19,20, SKX +#define IIO_PLL_OFF_EN (7 << IIO_PLL_OFF_EN_SHIF= T) // Bit 16,17,18, SKX +#define MC1_PKGC_CLK_GATE_DISABLE (1 << MC1_PKGC_CLK_GATE_D= ISABLE_SHIFT) // Bit 7, SKX +#define MC0_PKGC_CLK_GATE_DISABLE (1 << MC0_PKGC_CLK_GATE_D= ISABLE_SHIFT) // Bit 6, SKX +#define KTI23_PKGC_CLK_GATE_DISABLE (1 << KTI23_PKGC_CLK_GATE= _DISABLE_SHIFT) // Bit 4, SKX +#define KTI01_PKGC_CLK_GATE_DISABLE (1 << KTI01_PKGC_CLK_GATE= _DISABLE_SHIFT) // Bit 3, SKX +#define IIO012_PKGC_CLK_GATE_DISABLE (7 << IIO012_PKGC_CLK_GAT= E_DISABLE_SHIFT) // Bit 0,1,2, SKX +#define SAPMCTL_MASK (IIO012_PKGC_CLK_GATE_DISABLE + KTI01_PKGC_CLK_GATE_= DISABLE + KTI23_PKGC_CLK_GATE_DISABLE + MC0_PKGC_CLK_GATE_DISABLE \ + + MC1_PKGC_CLK_GATE_DISABLE + IIO_PLL_OFF_EN + KTI_PLL_OFF_EN + ME= M_PLL_OFF_EN + SETVID_DECAY_DISABLE + SAPMCTL_LOCK \ + + MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE + MC0_PKGC_IO_VOLTAGE_REDU= CTION_DISABLE + MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE + MC0_PKGC_DIG_VOLTA= GE_REDUCTION_DISABLE) + +//Config TDP +#define CONFIG_TDP_LEVEL (3 << CONFIG_TDP_LEVEL_SH= IFT) +#define CONFIG_TDP_LEVEL_SHIFT 1 // Bit [2:1] +#define CONFIG_TDP_SHIFT 0 // Bit 0 + +// MSR 0x1FC +#define MSR_POWER_CTL 0x1FC +#define PCH_NEG_DISABLE (1 << 30) +#define PCH_NEG_DISABLE_SHIFT 30 +#define LTR_SW_DISABLE (1 << 29) //LTR_IIO_DISAB= LE +#define LTR_SW_DISABLE_SHIFT 29 +#define PROCHOT_LOCK (1 << 27) +#define PROCHOT_LOCK_SHIFT 27 +#define PROCHOT_RESPONSE (1 << 26) +#define PROCHOT_RESPONSE_SHIFT 26 +#define PWR_PERF_TUNING_CFG_MODE (1 << 25) +#define PWR_PERF_TUNING_CFG_MODE_SHIFT 25 +#define PWR_PERF_TUNING_ENABLE_DYN_SWITCHING (1 << 24) +#define PWR_PERF_TUNING_ENABLE_DYN_SHIFT 24 +#define PWR_PERF_TUNING_DISABLE_EEP_CTRL (1 << 23) +#define PWR_PERF_TUNING_DISABLE_EEP_SHIFT 23 +#define PWR_PERF_TUNING_DISABLE_SAPM_CTRL (1 << 22) +#define PWR_PERF_TUNING_DISABLE_SAPM_SHIFT 22 +#define DIS_PROCHOT_OUT (1 << 21) +#define DIS_PROCHOT_OUT_SHIFT 21 +#define EE_TURBO_DISABLE (1 << 19) +#define EE_TURBO_DISABLE_SHIFT 19 +#define ENERGY_EFFICIENT_PSTATE_ENABLE (1 << 18) +#define ENERGY_EFFICIENT_PSTATE_ENABLE_SHIFT 18 +#define PHOLD_SR_DISABLE (1 << 17) +#define PHOLD_SR_DISABLE_SHIFT 17 +#define PHOLD_CST_PREVENTION_INIT (1 << 16) +#define PHOLD_CST_PREVENTION_INIT_SHIFT 16 +#define FAST_BRK_INT_EN (1 << 4) +#define FAST_BRK_INT_EN_SHIFT 4 +#define FAST_BRK_SNP_EN (1 << 3) +#define FAST_BRK_SNP_EN_SHIFT 3 +#define SAPM_IMC_C2_POLICY_EN (1 << 2) +#define SAPM_IMC_C2_POLICY_SHIFT 2 +#define C1E_ENABLE (1 << 1) +#define C1E_ENABLE_SHIFT 1 +#define ENABLE_BIDIR_PROCHOT_EN (1 << 0) +#define ENABLE_BIDIR_PROCHOT_EN_SHIFT 0 +#define POWER_CTL_MASK (PCH_NEG_DISABLE + LTR_SW_= DISABLE + PWR_PERF_TUNING_CFG_MODE + \ + PWR_PERF_TUNING_ENABLE_DYN_SWITCHING + PWR_PERF_TUNING_DISABLE_EEP= _CTRL + \ + PWR_PERF_TUNING_DISABLE_SAPM_CTRL + DIS_PROCHOT_OUT + ENABLE_BIDIR= _PROCHOT_EN + C1E_ENABLE) + +// PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601 +#define PSI3_CODE_SHIFT 27 // (Bits 61:59 actully) we opera= te on a 32 bit register +#define PSI3_THSHLD_SHIFT 20 // (Bits 58:52 actully) we opera= te on a 32 bit register +#define PSI2_CODE_SHIFT 17 // (Bits 51:49 actully) we opera= te on a 32 bit register +#define PSI2_THSHLD_SHIFT 10 // (Bits 48:42 actully) we opera= te on a 32 bit register +#define PSI1_CODE_SHIFT 7 // (Bits 41:39 actully) we opera= te on a 32 bit register +#define PSI1_THSHLD_SHIFT 0 // (Bits 38:32 actully) we opera= te on a 32 bit register +#define PPCCC_LOCK_SHIFT 31 +#define CURRENT_LIMIT_SHIFT 0 +#define PSI3_CODE (0x7 << PSI3_CODE_SHIFT) // (Bits 6= 1:59 actully) we operate on a 32 bit register +#define PSI3_THSHLD (0x7f << PSI3_THSHLD_SHIFT) // (Bit= s 58:52 actully) we operate on a 32 bit register +#define PSI2_CODE (0x7 << PSI2_CODE_SHIFT) // (Bits 5= 1:49 actully) we operate on a 32 bit register +#define PSI2_THSHLD (0x7f << PSI2_THSHLD_SHIFT) // (Bit= s 48:42 actully) we operate on a 32 bit register +#define PSI1_CODE (0x7 << PSI1_CODE_SHIFT) // (Bits 4= 1:39 actully) we operate on a 32 bit register +#define PSI1_THSHLD (0x7f << PSI1_THSHLD_SHIFT) // (Bit= s 38:32 actully) we operate on a 32 bit register +#define PPCCC_LOCK (1 << PPCCC_LOCK_SHIFT) +#define CURRENT_LIMIT (0x1fff << CURRENT_LIMIT_SHIFT) + +#define B_PCPS_DISABLE (1 << 25) // Bit 25 + +// MSR_C_STATE_LATENCY_CONTROL_0 0x60a, 60b, 60c +#define VALID_SHIFT 15 +#define MULTIPLIER_SHIFT 10 +#define VALUE_SHIFT 0 + +// MSR_TURBO_POWER_LIMIT 0x610 +// CSR_TURBO_POWER_LIMIT +#define POWER_LIMIT_ENABLE_SHIFT 15 +#define POWER_LIMIT_ENABLE (1 << POWER_LIMIT_ENABLE_SHIFT) // U= sed as Bit 15 and Bit 47 +#define PKG_CLMP_LIM_SHIFT 16 +#define PKG_CLMP_LIM (1 << PKG_CLMP_LIM_SHIFT) // u= sed as Bit 16 and Bit48 +#define POWER_LIMIT_MASK (0x7FFF) // B= its 14:0 and 46:32 +#define POWER_LIMIT_1_TIME_SHIFT 17 +#define POWER_LIMIT_1_TIME_MASK (0xFE0000) // B= its 23:17 +#define POWER_LIMIT_LOCK_SHIFT 31 +#define POWER_LIMIT_LOCK (1 << POWER_LIMIT_LOCK_SHIFT) // B= it 63 + +// MSR_ENERGY_PERF_BIAS_CONFIG 0xA01 +#define AVG_TIME_Window (0xff << AVG_TIME_Window_SHIFT= ) // Bits 31:24 +#define PO_TOTAL_TIME_THSHLD_LOW (0x3f << PO_TOTAL_TIME_THSHLD_= LOW_SHIFT) // Bits 23:18 +#define PO_TOTAL_TIME_THSHLD_HIGH (0x3f << PO_TOTAL_TIME_THSHLD_= HIGH_SHIFT) // Bis 17:12 +#define ALT_ENERGY_PERF_BIAS (0xf << ALT_ENERGY_PERF_BIAS_S= HIFT) // Bits 6:3 +#define WORKLD_CONFIG (0x7 << WORKLD_CONFIG_SHIFT) = // Bits 2:0 +#define AVG_TIME_Window_SHIFT 24 = // Bits 31:24 +#define PO_TOTAL_TIME_THSHLD_LOW_SHIFT 18 = // Bits 23:18 +#define PO_TOTAL_TIME_THSHLD_HIGH_SHIFT 12 = // Bis 17:12 +#define ALT_ENERGY_PERF_BIAS_SHIFT 3 = // Bits 6:3 +#define WORKLD_CONFIG_SHIFT 0 = // Bits 2:0 +#define ENERGY_PERF_BIAS_CTRL_MASK (AVG_TIME_Window + PO_TOTAL_TIME_THSH= LD_LOW + PO_TOTAL_TIME_THSHLD_HIGH + WORKLD_CONFIG + ALT_ENERGY_PERF_BIAS) + +// +// Cross over Mode +// +#define XOVER_MODE_2TO2 1 +#define XOVER_MODE_1TO1 2 + +// HWPM features +#define HWP_ENABLE 0x01 +#define ACC_ENABLE 0x02 + +// SPT workarounds +#define SPT_WA_ENABLE 0x03 + +// ratio in Performance Control MSR (MSR_IA32_PERF_CTL) +#define B_IA32_PERF_CTRLP_STATE_TARGET (0x7F << 8) + +#pragma pack(1) + +/************************** + Processor Power Management Data structs +***************************/ + +typedef struct _PPM_FROM_PPMINFO_HOB { + UINT8 NumberOfSockets; // # of populated sock= ets in the system + UINT8 SocketNumber; // which socket + UINT32 SocketPresentBitMap; // bitmap for present = CPU packages/nodes + UINT8 IioBusNumber[MAX_SOCKET]; // Bus# for IIO, index= ed by CPU Socket/Node ID + UINT8 UncoreBusNumber[MAX_SOCKET]; // Bus# for Uncore, in= dexed by CPU Socket/Node ID + UINT32 mmCfgBase; + UINT8 DdrXoverMode; // DDR 2.2 Mode + UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link ena= bled status for PM + UINT32 OutPciePerLinkL1En[MAX_SOCKET]; // output PCIe (IIO) l= ink enabled status for PM + UINT8 KtiPortCnt; // num KTI ports resid= ing on each Socket + UINT8 ProcessorPowerUnit[MAX_SOCKET]; // + UINT8 ProcessorTimeUnit[MAX_SOCKET]; // + UINT16 PackageTdp[MAX_SOCKET]; // Package TDP + UINT32 CapId4; //CapId CSR value + UINT32 CpuType; // CpuType + UINT8 CpuStepping; // CpuStepping + UINT32 mNumOfBitShift; // # Bits to shift rig= ht APIC ID to get next level APIC ID + UINTN NumberOfProcessors; // number of active th= reads + BOOLEAN EistCap; // EIST Capability + UINT8 Bios_Reset_Cpl_Phase; + UINT8 HwpmSupport; //HWPM support flag +}PPM_FROM_PPMINFO_HOB; + +typedef struct { + UINT8 Major; // Major Vesion + UINT8 Minor; // Minor Vesion + UINT8 Rev; // Release Version + UINT8 Build; // +} PPM_VERSION; + +typedef union _MSR_REGISTER { + UINT64 Qword; + + struct _DWORDS { + UINT32 Low; + UINT32 High; + } Dwords; + + struct _BYTES { + UINT8 FirstByte; + UINT8 SecondByte; + UINT8 ThirdByte; + UINT8 FouthByte; + UINT8 FifthByte; + UINT8 SixthByte; + UINT8 SeventhByte; + UINT8 EighthByte; + } Bytes; + +} MSR_REGISTER; + +typedef struct { + BOOLEAN C1e; + + UINT32 PkgCstEntryCriteriaMaskKti[MAX_SOCKET]; + UINT32 PkgCstEntryCriteriaMaskPcie[MAX_SOCKET]; + MSR_REGISTER LatencyCtrl[NUM_CST_LAT_MSR]; + +} CSTATE_STRUCT; + +typedef struct { + + BOOLEAN EistEnabled; // option to enable GV3 + UINT8 ConfigTdpLevel; // Config TDP Level + UINT16 CurrentPackageTdp; // Package TDP + UINT8 PcpsCtrl; + +} PSTATE_STRUCT; + +typedef struct { + BOOLEAN Enable; + UINT32 Voltage; + UINT16 RatioLimit[MAX_CORE]; +} XE_STRUCT; + +typedef struct { + UINT8 RatioLimitRatio[8]; + UINT8 RatioLimitRatioMask[8]; + UINT8 RatioLimitCores[8]; + UINT8 RatioLimitCoresMask[8]; +} TURBO_RATIO_LIMIT_RATIO_CORES; + +typedef struct { + UINT8 HWPMEnable; + UINT8 HWPMNative; + UINT8 HWPMOOB; + UINT8 HWPMInterrupt; + UINT8 AutoCState; + UINT8 EPPEnable; + UINT8 EPPProfile; + UINT8 APSrocketing; + UINT8 Scalability; + UINT8 ProcessorRaplPrioritization; + UINT8 OutofBandAlternateEPB; + UINT8 PbfEnabled; + UINT8 ConfigurePbf; + UINT64 PbfHighPriCoreMap[MAX_SOCKET]; // PBF High Priority Cores Bit= map + UINT8 PbfP1HighRatio[MAX_SOCKET]; // PBF P1_High Ratio + UINT8 PbfP1LowRatio[MAX_SOCKET]; // PBF P1_Low Ratio +} HWPM_STRUCT; + +typedef struct { + + UINT8 FastRaplDutyCycle; + UINT8 FuseTjMaxOffset; + + UINT8 OverclockingLock; + UINT8 AvxIccpLevel; + UINT32 AdvPwrMgtCtlFlags; + + MSR_REGISTER PowerCtl; + MSR_REGISTER TurboPowerLimit; + MSR_REGISTER PP0CurrentCfg; + MSR_REGISTER PerfBiasConfig; + + UINT32 ProchotRatio; + UINT32 PmaxConfig; + UINT32 SapmCtl[MAX_SOCKET]; + UINT32 PerPLimitCtl; + UINT32 C2C3TT; + UINT32 DynamicPerPowerCtl; + UINT32 PcieIltrOvrd; + + CSTATE_STRUCT Cst; + PSTATE_STRUCT Pst; + XE_STRUCT Xe; + HWPM_STRUCT Hwpm; + TURBO_RATIO_LIMIT_RATIO_CORES TurboRatioLimitRatioCores; + + UINT8 TCCActivationOffset; + UINT8 IsOppSrefEn; + +} EFI_PPM_STRUCT; + + +typedef struct { + + PPM_VERSION Version; + + EFI_CPU_CSR_ACCESS_PROTOCOL *CpuCsrAccess; + + PPM_FROM_PPMINFO_HOB *Info; + + EFI_PPM_STRUCT *Setup; + + UINTN ProcessorNumber; + +} EFI_CPU_PM_STRUCT; + + +#pragma pack() + +VOID +PStateTransition ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +InitializeCpuPPMLib ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetBiosInitDone ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetCsrLockBit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetMsrLockBit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCSRTurboPowerLimit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrDynamicPerfPowerCtl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrSapmCtl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrSwLtrOvrd ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrPkgCstEntryCriteriaMask( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrResponseRatioCfg( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +EFIAPI +SetupPCIEPkgCstEntryCriteria ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrPerfPlimitControl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrPmaxConfig ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramMsrPowerCtl ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramMsrTurboPowerLimit ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramEnergyPerfBiasConfigMsr ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgMsrPriPlaneCurtCfgCtrL ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramMsrTurboRatioLimit ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramMsrTemperatureTarget ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +GetMsrTemperatureTarget ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramMsrMiscPwrMgmt ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +Program_Bios_Reset_Cpl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PFastRaplDutyCycle ( + EFI_CPU_PM_STRUCT *ppm + ); + +UINT8 +EFIAPI +GetHwpmSupport ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +HWPMInterfaceReg ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +EnableAutonomousCStateControl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +EFIAPI +EnableHwpLvtThermalInterrupt( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +EFIAPI +EnableHwpFeatures( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramB2PPcuMiscConfig ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PHWPMMiscConfig ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramMsrCLatency ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramB2PDynamicL1 ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetMsrCstConfigCtrlLockBit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PForceUncoreAndMeshRatio ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PMiscWorkaroundEnable ( + EFI_CPU_PM_STRUCT *ppm + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CsrToPci= eAddress.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CsrToPci= eAddress.h new file mode 100644 index 0000000000..1eef535d91 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CsrToPcieAddres= s.h @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __CSR_TO_PCIE_ADDRESS_H__ +#define __CSR_TO_PCIE_ADDRESS_H__ + + +#include + +////////////////////////////////////////////////////////////////////////// +// +// CSR to Pcie Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Bo= x instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Add= ress Structure + @param[out] AlignedAddress A pointer of aligned address converted f= rom USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/MmPciBas= eLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/MmPciBaseLib= .h new file mode 100644 index 0000000000..16205126a6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/MmPciBaseLib.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_PCIE_BASE_LIB_H_ +#define _MM_PCIE_BASE_LIB_H_ + +#include + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +); + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +); + +#endif // _MM_PCIE_BASE_LIB_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PcieAddr= ess.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PcieAddress.h new file mode 100644 index 0000000000..ec5c364e0c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PcieAddress.h @@ -0,0 +1,80 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCIE_MMCFG_H__ +#define __PCIE_MMCFG_H__ + +#include + + +////////////////////////////////////////////////////////////////////////// +// +// PCIE MMCFG Table definition +// This table was based on PCI Firmware Spec Rev 3.1 +// +////////////////////////////////////////////////////////////////////////// + +typedef struct + { + UINT8 Signature[4]; // "MCFG" Signature = For this Table + UINT32 Length; // Length, in bytes,= include base address allocation structures. + UINT8 Revision; // "1" + UINT8 SegMax; // The Maximum numbe= r of Segments + UINT16 ValidSegMap; // Valid Segment Bit= Map, LSB Bit0 for Seg0, bit1 for seg1 ... + UINT8 Reserved[4]; // Reserved +} PCIE_MMCFG_HEADER_TYPE; + +typedef struct + { + UINT32 BaseAddressL; // Processor-relativ= e Base Address (Lower 32-bit) for the Enhanced Configuration Access Mechani= sm + UINT32 BaseAddressH; // Processor-relativ= e Base Address (Upper 32-bit) for the Enhanced Configuration Access Mechani= sm + UINT16 Segment; // PCI Segment Group= Number. Default is 0. + UINT8 StartBus; // Start PCI Bus num= ber decoded by the host bridge + UINT8 EndBus; // End PCI Bus numbe= r decoded by the host bridge + UINT8 Reserved[4]; // Reserved +} PCIE_MMCFG_BASE_ADDRESS_TYPE; + + +typedef struct + { + PCIE_MMCFG_HEADER_TYPE Header; // The header of MMC= FG Table + PCIE_MMCFG_BASE_ADDRESS_TYPE MmcfgBase[1]; // First Array of ba= se address allocation structures. +} PCIE_MMCFG_TABLE_TYPE; + + +/** + This Lib is used for platform to set platform specific Pcie MMCFG Table + + @param[in] MmcfgTable A pointer of the MMCFG Table structure f= or PCIE_MMCFG_TABLE_TYPE type + @param[in] NumOfSeg Number of Segments in the table + + @retval <>NULL The function completed successfully. + @retval NULL Return Error +**/ +UINTN +EFIAPI +SetPcieSegMmcfgTable ( + IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable, + IN UINT32 NumOfSeg +); + +/** + This Lib return PCIE MMCFG Base Address + + @param[in] Address A pointer of the address of the USRA Add= ress Structure for PCIE type + + @retval <>NULL The function completed successfully. + @retval NULL Return Error +**/ +UINTN +EFIAPI +GetPcieSegMmcfgBaseAddress ( + IN USRA_ADDRESS *Address + ); + + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PciePlat= formHookLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PcieP= latformHookLib.h new file mode 100644 index 0000000000..8ff5251627 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PciePlatformHoo= kLib.h @@ -0,0 +1,27 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCIE_PLATFORM_HOOK_LIB_H__ +#define __PCIE_PLATFORM_HOOK_LIB_H__ + +typedef enum { + PcieInitStart, + BeforeBifurcation, + AfterBifurcation, + BeforePortInit, + AfterPortInit, + PcieInitEnd +} PCIE_HOOK_EVENT; + +EFI_STATUS +EFIAPI +PciePlatformHookEvent ( + IN PCIE_HOOK_EVENT Event, + IN VOID *Context + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/UsraAcce= ssApi.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/UsraAccessA= pi.h new file mode 100644 index 0000000000..148ca6c5b2 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/UsraAccessApi.h @@ -0,0 +1,85 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __USRA_ACCESS_API_H__ +#define __USRA_ACCESS_API_H__ + + +#include + +////////////////////////////////////////////////////////////////////////// +// +// USRA Silicon Access Library +// +////////////////////////////////////////////////////////////////////////// + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read o= perations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterRead ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write = operations. + It transfers data from a naturally aligned data buffer into a silicon re= gister. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterWrite ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND th= en OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and w= rite the result back to the register + + @param[in] Address A pointer of the address of the silicon = register to be written + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +GetRegisterAddress ( + IN USRA_ADDRESS *Address + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/MaxSocket.h b/Si= licon/Intel/PurleyRefreshSiliconPkg/Include/MaxSocket.h new file mode 100644 index 0000000000..8552d20191 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/MaxSocket.h @@ -0,0 +1,19 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// This defines the maximum number of sockets supported by some modules. +// It is generally better to use a dynamic solution. +// This is also defined by build tools for some special build +// environments used in validation that do not support EDK II build +// and thus can't use PCD. +// + +#ifndef MAX_SOCKET +#define MAX_SOCKET (FixedPcdGet32 (PcdMaxCpuSocketCount)) +#endif + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Ppi/SiliconRegAc= cess.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Ppi/SiliconRegAccess= .h new file mode 100644 index 0000000000..9fc9b400c6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Ppi/SiliconRegAccess.h @@ -0,0 +1,162 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SILICON_REG_ACCESS_PPI_H__ +#define __SILICON_REG_ACCESS_PPI_H__ + +#include + +extern EFI_GUID gUsraPpiGuid; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read o= perations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_READ)( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write = operations. + It transfers data from a naturally aligned data buffer into a silicon re= gister. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_WRITE)( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND th= en OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and w= rite the result back to the register + + @param[in] Address A pointer of the address of the silicon = register to be written + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_MODIFY)( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + + @retval The flat address +**/ +typedef +INTN +(EFIAPI *USRA_PPI_GET_ADDR)( + IN USRA_ADDRESS *Address + ); + +/// +/// This service abstracts the ability to read/write silicon register. +/// +typedef struct { + USRA_PPI_REG_READ RegRead; + USRA_PPI_REG_WRITE RegWrite; + + USRA_PPI_REG_MODIFY RegModify; + USRA_PPI_GET_ADDR GetRegAddr; +} USRA_PPI; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read o= perations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write = operations. + It transfers data from a naturally aligned data buffer into a silicon re= gister. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegWrite ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register A= ND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and w= rite the result back to the register + + @param[in] Address A pointer of the address of the silicon = register to be written + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +PeiGetRegAddr ( + IN USRA_ADDRESS *Address + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/IioUds.= h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/IioUds.h new file mode 100644 index 0000000000..96913ebe31 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/IioUds.h @@ -0,0 +1,44 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_IIO_UDS_PROTOCOL_H_ +#define _EFI_IIO_UDS_PROTOCOL_H_ + +#include + +#define EFI_IIO_UDS_PROTOCOL_GUID \ + { 0xa7ced760, 0xc71c, 0x4e1a, 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, = 0xcb } + +typedef struct _EFI_IIO_UDS_PROTOCOL EFI_IIO_UDS_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *IIH_ENABLE_VC) ( + IN EFI_IIO_UDS_PROTOCOL *This, + IN UINT32 VcCtrlData + ); +/** + + Enables the requested VC in IIO + + @param This Pointer to the EFI_IOH_UDS_PROTOCOL insta= nce. + @param VcCtrlData Data read from VC resourse control reg. + +**/ + + +typedef struct _EFI_IIO_UDS_PROTOCOL { + IIO_UDS *IioUdsPtr; + IIH_ENABLE_VC EnableVc; +} EFI_IIO_UDS_PROTOCOL; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiIioUdsProtocolGuid; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/PciCall= back.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/PciCallback= .h new file mode 100644 index 0000000000..7da7fa3c77 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/PciCallback.h @@ -0,0 +1,84 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_PCI_CALLBACK_H +#define _EFI_PCI_CALLBACK_H + +#include +#include +#include + + +// +// Global Id for PCI callback +// +#define EFI_PCI_CALLBACK_PROTOCOL_GUID \ + { \ + 0x1ca0e202, 0xfe9e, 0x4776, 0x9f, 0xaa, 0x57, 0xc, 0x19, 0x61, 0x7a, 0= x06 \ + } + +typedef struct _EFI_PCI_CALLBACK_PROTOCOL EFI_PCI_CALLBACK_PROTOCOL; + +typedef enum { + EfiPciEnumerationDeviceScanning =3D 1, + EfiPciEnumerationBusNumberAssigned =3D 2, + EfiPciEnumerationResourceAssigned =3D 4, +} EFI_PCI_ENUMERATION_PHASE; + +typedef struct { + PCI_TYPE00 PciHeader; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; + EFI_CPU_IO2_PROTOCOL *CpuIo; +} EFI_PCI_CALLBACK_CONTEXT; + +typedef +VOID +(EFIAPI *EFI_PCI_CALLBACK_FUNC) ( + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_ENUMERATION_PHASE Phase, + IN EFI_PCI_CALLBACK_CONTEXT *Context +); + +typedef +EFI_STATUS +(EFIAPI *EFI_REGISTER_PCI_CALLBACK) ( + IN EFI_PCI_CALLBACK_PROTOCOL *This, + IN EFI_PCI_CALLBACK_FUNC Function, + IN EFI_PCI_ENUMERATION_PHASE Phase +) +/*++ + +Routine Description: + + Register a callback during PCI bus enumeration + +Arguments: + + This - Protocol instance pointer. + Function - Callback function pointer. + Phase - PCI enumeration phase. + +Returns: + + EFI_SUCCESS - Function has registed successfully + EFI_UNSUPPORTED - The function has been regisered + EFI_InVALID_PARAMETER - The parameter is incorrect + +--*/ +; + +// +// Protocol definition +// +typedef struct _EFI_PCI_CALLBACK_PROTOCOL { + EFI_REGISTER_PCI_CALLBACK RegisterPciCallback; +} EFI_PCI_CALLBACK_PROTOCOL; + +extern EFI_GUID gEfiPciCallbackProtocolGuid; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/Silicon= RegAccess.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/Silico= nRegAccess.h new file mode 100644 index 0000000000..425f44e9c7 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/SiliconRegAcce= ss.h @@ -0,0 +1,227 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SILICON_REG_ACCESS_PROTOCOL_H__ +#define __SILICON_REG_ACCESS_PROTOCOL_H__ + +#include + +extern EFI_GUID gUsraProtocolGuid; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read o= perations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_READ)( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write = operations. + It transfers data from a naturally aligned data buffer into a silicon re= gister. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_WRITE)( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write = operations. + It transfers data from a naturally aligned data buffer into a silicon re= gister. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_MODIFY)( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + + @retval The flat address +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_GET_ADDR)( + IN USRA_ADDRESS *Address + ); + +/// +/// This service abstracts the ability to read/write silicon register. +/// +typedef struct { + USRA_PROTOCOL_REG_READ RegRead; + USRA_PROTOCOL_REG_WRITE RegWrite; + USRA_PROTOCOL_REG_MODIFY RegModify; + USRA_PROTOCOL_GET_ADDR GetRegAddr; +} USRA_PROTOCOL; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read o= perations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write = operations. + It transfers data from a naturally aligned data buffer into a silicon re= gister. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND th= en OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and w= rite the result back to the register + + @param[in] Address A pointer of the address of the silicon = register to be written + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +DxeGetRegAddr ( + IN USRA_ADDRESS *Address + ); + + /** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read o= perations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write = operations. + It transfers data from a naturally aligned data buffer into a silicon re= gister. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND th= en OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and w= rite the result back to the register + + @param[in] Address A pointer of the address of the silicon = register to be written + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +SmmGetRegAddr ( + IN USRA_ADDRESS *Address + ); + + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/SocketConfigurat= ion.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/SocketConfiguration.h new file mode 100644 index 0000000000..ea1f5e3827 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/SocketConfiguration.h @@ -0,0 +1,514 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_CONFIGURATION_H__ +#define __SOCKET_CONFIGURATION_H__ + +#define SOCKET_CONFIG_CLASS_ID 44 +#define SOCKET_CONFIG_SUBCLASS_ID 0x00 + +#define VFR_BLANK_LINE subtitle text =3D STRING_TOKEN(STR_NULL_STRING); +#define VFR_END_FORM endform; +#define VFR_END_FORMSET endformset; +#define VFR_HORIZ_LINE subtitle text =3D STRING_TOKEN(STR_HORIZONTAL_LINE); + + + +#define SOCKET_IIO_CONFIG_KEY 0xFAFB +#define SOCKET_COMMONRC_CONFIG_KEY 0xFAFA +#define SOCKET_MP_LINK_CONFIG_KEY 0xFAF9 +#define SOCKET_MEMORY_CONFIG_KEY 0xFAF8 +#define SOCKET_MISC_CONFIG_KEY 0xFAF7 +#define SOCKET_CONFIG_KEY 0xF00A +#define SOCKET_POWERMANAGEMENT_CONFIGURATION_KEY 0xF00B +#define SOCKET_PROCESSORCORE_CONFIGURATION_KEY 0xF00C + + + +#define KEY_XMP_PROFILE 0x1DC0 +#define KEY_XMP_PROFILE1 0x1DC1 +#define KEY_CPU_ONLINE 0x10B8 + +// {26A69232-ABF8-4597-8876-A7DC0A7CA602} +#define SOCKET_CONFIG_SETUP_GUID {0x26a69232, 0xabf8, 0x4597, 0x88, 0x76, = 0xa7, 0xdc, 0xa, 0x7c, 0xa6, 0x2} + + + +#define VFR_FORMID_SOCKET 0x510 +#define VFR_FORMID_COMMONRC 0x511 +#define VFR_FORMID_KTI 0x512 +#define VFR_FORMID_PROCESSOR 0x513 +#define VFR_FORMID_KTI_STATUS 0x514 + +#define VFR_FORMID_SOCKET_IIO_CONFIGURATION 0x517 + +#define VFR_FORMID_IIO 0x518 +#define VFR_FORMID_IIO2 0x519 +#define VFR_FORMID_IIO3 0x51A +#define VFR_FORMID_IIO4 0x51B +#define VFR_FORMID_PWRMGT 0x51C + +// +// KTI Form for SV +// + +#define VFR_FORMID_KTI_GENERAL 0x521 +#define VFR_FORMID_KTISYSTEMWIDE 0x522 +#define VFR_FORMID_KTISYSTEM_PHY_LINK 0x523 +#define VFR_FORMID_KTISYSTEM_OSB 0x524 +#define VFR_FORMID_KTIPERSOCKET 0x525 +#define VFR_FID_KTI_CPU0 0x526 +#define VFR_FID_KTI_CPU1 0x527 +#define VFR_FID_KTI_CPU2 0x528 +#define VFR_FID_KTI_CPU3 0x529 +#define VFR_FID_KTI_CPU4 0x52A +#define VFR_FID_KTI_CPU5 0x52B +#define VFR_FID_KTI_CPU6 0x52C +#define VFR_FID_KTI_CPU7 0x52D +// +// KTI Form IDs +// +#define VFR_FORMID_CPU_KTII 0x530 +#define VFR_FID_KTI_STATUS 0x531 +#define VFR_FID_KTI_TOPOLOGY 0x532 +#define VFR_FID_KTI_TOPOLOGY_MATRIX 0x533 +#define VFR_FID_IIO_DEV_HIDE 0x534 +#define VFR_FID_KTI_SOCKET_RES 0x535 +#define VFR_FID_KTI_SOCKET_RES_REQUEST 0x536 +#define VFR_FID_KTI_SOCKET_RES_STATUS 0x537 +#define VFR_FORMID_MEMORY 0x540 +#define VFR_FORMID_MEMORY_RAS 0x541 +#define VFR_FID_KTI_CPU0_LINK0 0x542 +#define VFR_FID_KTI_CPU0_LINK1 0x543 +#define VFR_FID_KTI_CPU0_LINK2 0x544 +#define VFR_FID_KTI_CPU1_LINK0 0x545 +#define VFR_FID_KTI_CPU1_LINK1 0x546 +#define VFR_FID_KTI_CPU1_LINK2 0x547 +#define VFR_FID_KTI_CPU2_LINK0 0x548 +#define VFR_FID_KTI_CPU2_LINK1 0x549 +#define VFR_FID_KTI_CPU2_LINK2 0x54A +#define VFR_FID_KTI_CPU3_LINK0 0x54B +#define VFR_FID_KTI_CPU3_LINK1 0x54C +#define VFR_FID_KTI_CPU3_LINK2 0x54D +#define VFR_FID_KTI_CPU4_LINK0 0x54E +#define VFR_FID_KTI_CPU4_LINK1 0x54F +#define VFR_FORMID_BRANCH_RANK_CONFIG 0x571 +#define VFR_FORMID_VALHOOKS_CONFIG 0x572 +#define VFR_FORMID_THERMTHRT_CONFIG 0x573 +#define VFR_FORMID_MEMTOPOLOGY_DISPLAY 0x574 +#define VFR_FORMID_PAGE_POLICY_DISPLAY 0x57D +#define VFR_FORMID_MEMORY_TRAINING_DISPLAY 0x57E +#define VFR_FORMID_MEM_PWR_SAVE_ADV_ID 0x57F +#define VFR_FORMID_CKE_DISPLAY 0x59F +#define VFR_FORMID_SREF_DISPLAY 0x5A0 +#define VFR_FORMID_MEM_THERMAL_ID 0x580 +#define VFR_FORMID_XMP_DISPLAY 0x581 +#define VFR_FORMID_MEM_PM_CFG_ID 0x582 +#define VFR_FORMID_MEM_MAP 0x58A +#define VFR_FORMID_RAPL 0x58B +#define VFR_FORMID_SECURE_ERASE 0x58E + +#define VFR_FID_KTI_CPU4_LINK2 0x590 +#define VFR_FID_KTI_CPU5_LINK0 0x591 +#define VFR_FID_KTI_CPU5_LINK1 0x592 +#define VFR_FID_KTI_CPU5_LINK2 0x593 +#define VFR_FID_KTI_CPU6_LINK0 0x594 +#define VFR_FID_KTI_CPU6_LINK1 0x595 +#define VFR_FID_KTI_CPU6_LINK2 0x596 +#define VFR_FID_KTI_CPU7_LINK0 0x597 +#define VFR_FID_KTI_CPU7_LINK1 0x598 +#define VFR_FID_KTI_CPU7_LINK2 0x599 + +#define VFR_FID_KTI_WARNING_LOG 0x59E + + +// +// MEMORY Form IDs +// + + + + +// +// IIO Form IDs +// +#define VFR_FORMID_IIO_CONFIG 0x450 +#define VFR_FORMID_VTD 0x451 +#define VFR_FORMID_PCIE 0x452 +#define VFR_FORMID_PCIE_IIO0P0 0x453 +#define VFR_FORMID_PCIE_IIO0P1 0x454 +#define VFR_FORMID_PCIE_IIO0P2 0x455 +#define VFR_FORMID_PCIE_IIO0P3 0x456 +#define VFR_FORMID_PCIE_IIO0P4 0x457 +#define VFR_FORMID_PCIE_IIO0P5 0x458 +#define VFR_FORMID_PCIE_IIO0P6 0x459 +#define VFR_FORMID_PCIE_IIO0P7 0x45A +#define VFR_FORMID_PCIE_IIO0P8 0x45B +#define VFR_FORMID_PCIE_IIO0P9 0x45C +#define VFR_FORMID_PCIE_IIO0P10 0x45D +#define VFR_FORMID_PCIE_IIO0P11 0x45E +#define VFR_FORMID_PCIE_IIO0P12 0x45F +#define VFR_FORMID_PCIE_IIO0P13 0x460 +#define VFR_FORMID_PCIE_IIO0P14 0x461 +#define VFR_FORMID_PCIE_IIO0P15 0x488 +#define VFR_FORMID_PCIE_IIO0P16 0x489 +#define VFR_FORMID_PCIE_IIO0P17 0x48A +#define VFR_FORMID_PCIE_IIO0P18 0x48B +#define VFR_FORMID_PCIE_IIO0P19 0x48C +#define VFR_FORMID_PCIE_IIO0P20 0x48D + +#define VFR_FORMID_PCIE_IIO1P0 0x462 +#define VFR_FORMID_PCIE_IIO1P1 0x463 +#define VFR_FORMID_PCIE_IIO1P2 0x469 +#define VFR_FORMID_PCIE_IIO1P3 0x46A +#define VFR_FORMID_PCIE_IIO1P4 0x46B +#define VFR_FORMID_PCIE_IIO1P5 0x46C +#define VFR_FORMID_PCIE_IIO1P6 0x46D +#define VFR_FORMID_PCIE_IIO1P7 0x46E +#define VFR_FORMID_PCIE_IIO1P8 0x46F +#define VFR_FORMID_PCIE_IIO1P9 0x470 +#define VFR_FORMID_PCIE_IIO1P10 0x475 +#define VFR_FORMID_PCIE_IIO1P11 0x476 +#define VFR_FORMID_PCIE_IIO1P12 0x477 +#define VFR_FORMID_PCIE_IIO1P13 0x478 +#define VFR_FORMID_PCIE_IIO1P14 0x479 +#define VFR_FORMID_PCIE_IIO1P15 0x48E +#define VFR_FORMID_PCIE_IIO1P16 0x48F +#define VFR_FORMID_PCIE_IIO1P17 0x490 +#define VFR_FORMID_PCIE_IIO1P18 0x491 +#define VFR_FORMID_PCIE_IIO1P19 0x492 +#define VFR_FORMID_PCIE_IIO1P20 0x493 + +#define VFR_FORMID_IIO0 0x47A +#define VFR_FORMID_IIO1 0x47B +#define VFR_FORMID_IOAT_CONFIG 0x47C +#define VFR_FORMID_IIO0IOAT 0x47D +#define VFR_FORMID_IIO1IOAT 0x47E +#define VFR_FORMID_IIO2IOAT 0x47F +#define VFR_FORMID_IIO3IOAT 0x480 +#define VFR_FORMID_IIO_PCIE_SLOT 0x487 +// +// extended IIO form IDs for 4S +// +#define VFR_FORMID_PCIE_IIO2P0 0x0690 +#define VFR_FORMID_PCIE_IIO2P1 0x0691 +#define VFR_FORMID_PCIE_IIO2P2 0x0692 +#define VFR_FORMID_PCIE_IIO2P3 0x0693 +#define VFR_FORMID_PCIE_IIO2P4 0x0694 +#define VFR_FORMID_PCIE_IIO2P5 0x0695 +#define VFR_FORMID_PCIE_IIO2P6 0x0696 +#define VFR_FORMID_PCIE_IIO2P7 0x0697 +#define VFR_FORMID_PCIE_IIO2P8 0x0698 +#define VFR_FORMID_PCIE_IIO2P9 0x0699 +#define VFR_FORMID_PCIE_IIO2P10 0x069A +#define VFR_FORMID_PCIE_IIO2P11 0x069B +#define VFR_FORMID_PCIE_IIO2P12 0x069C +#define VFR_FORMID_PCIE_IIO2P13 0x069D +#define VFR_FORMID_PCIE_IIO2P14 0x069E +#define VFR_FORMID_PCIE_IIO2P15 0x06AA +#define VFR_FORMID_PCIE_IIO2P16 0x06AB +#define VFR_FORMID_PCIE_IIO2P17 0x06AC +#define VFR_FORMID_PCIE_IIO2P18 0x06AD +#define VFR_FORMID_PCIE_IIO2P19 0x06AE +#define VFR_FORMID_PCIE_IIO2P20 0x06AF + +#define VFR_FORMID_PCIE_IIO3P0 0x069F +#define VFR_FORMID_PCIE_IIO3P1 0x0670 +#define VFR_FORMID_PCIE_IIO3P2 0x0671 +#define VFR_FORMID_PCIE_IIO3P3 0x0672 +#define VFR_FORMID_PCIE_IIO3P4 0x0673 +#define VFR_FORMID_PCIE_IIO3P5 0x06A0 +#define VFR_FORMID_PCIE_IIO3P6 0x06A1 +#define VFR_FORMID_PCIE_IIO3P7 0x06A2 +#define VFR_FORMID_PCIE_IIO3P8 0x06A3 +#define VFR_FORMID_PCIE_IIO3P9 0x06A4 +#define VFR_FORMID_PCIE_IIO3P10 0x06A5 +#define VFR_FORMID_PCIE_IIO3P11 0x06A6 +#define VFR_FORMID_PCIE_IIO3P12 0x06A7 +#define VFR_FORMID_PCIE_IIO3P13 0x06A8 +#define VFR_FORMID_PCIE_IIO3P14 0x06A9 +#define VFR_FORMID_PCIE_IIO3P15 0x06B0 +#define VFR_FORMID_PCIE_IIO3P16 0x06B1 +#define VFR_FORMID_PCIE_IIO3P17 0x06B2 +#define VFR_FORMID_PCIE_IIO3P18 0x06B3 +#define VFR_FORMID_PCIE_IIO3P19 0x06B4 +#define VFR_FORMID_PCIE_IIO3P20 0x06B5 + +#define VFR_FORMID_VMD 0x06C0 +#define VFR_FORMID_VMD_IIO0 0x06C1 +#define VFR_FORMID_VMD_IIO1 0x06C2 +#define VFR_FORMID_VMD_IIO2 0x06C3 +#define VFR_FORMID_VMD_IIO3 0x06C4 +#define VFR_FORMID_IIO_RTO_CONFIG 0x06C5 +#define VFR_FORMID_IIO_RTO_SKT0SVDEVHIDE 0x06C6 +#define VFR_FORMID_IIO_RTO_SKT1SVDEVHIDE 0x06C7 +#define VFR_FORMID_IIO_RTO_SKT2SVDEVHIDE 0x06C8 +#define VFR_FORMID_IIO_RTO_SKT3SVDEVHIDE 0x06C9 + +#define VFR_FORMID_RTO_PCIE_IIO0P0 0x06CA +#define VFR_FORMID_RTO_PCIE_IIO0P1 0x06CB +#define VFR_FORMID_RTO_PCIE_IIO0P2 0x06CD +#define VFR_FORMID_RTO_PCIE_IIO0P3 0x06CE +#define VFR_FORMID_RTO_PCIE_IIO0P4 0x06CF +#define VFR_FORMID_RTO_PCIE_IIO0P5 0x06D0 +#define VFR_FORMID_RTO_PCIE_IIO0P6 0x06D1 +#define VFR_FORMID_RTO_PCIE_IIO0P7 0x06D2 +#define VFR_FORMID_RTO_PCIE_IIO0P8 0x06D3 +#define VFR_FORMID_RTO_PCIE_IIO0P9 0x06D4 +#define VFR_FORMID_RTO_PCIE_IIO0P10 0x06D5 +#define VFR_FORMID_RTO_PCIE_IIO0P11 0x06D6 +#define VFR_FORMID_RTO_PCIE_IIO0P12 0x06D7 +#define VFR_FORMID_RTO_PCIE_IIO0P13 0x06D8 +#define VFR_FORMID_RTO_PCIE_IIO0P14 0x06D9 +#define VFR_FORMID_RTO_PCIE_IIO0P15 0x06DA +#define VFR_FORMID_RTO_PCIE_IIO0P16 0x06DB +#define VFR_FORMID_RTO_PCIE_IIO0P17 0x06DC +#define VFR_FORMID_RTO_PCIE_IIO0P18 0x06DD +#define VFR_FORMID_RTO_PCIE_IIO0P19 0x06DE +#define VFR_FORMID_RTO_PCIE_IIO0P20 0x06DF + +#define VFR_FORMID_RTO_PCIE_IIO1P0 0x06E0 +#define VFR_FORMID_RTO_PCIE_IIO1P1 0x06E1 +#define VFR_FORMID_RTO_PCIE_IIO1P2 0x06E2 +#define VFR_FORMID_RTO_PCIE_IIO1P3 0x06E3 +#define VFR_FORMID_RTO_PCIE_IIO1P4 0x06E4 +#define VFR_FORMID_RTO_PCIE_IIO1P5 0x06E5 +#define VFR_FORMID_RTO_PCIE_IIO1P6 0x06E6 +#define VFR_FORMID_RTO_PCIE_IIO1P7 0x06E7 +#define VFR_FORMID_RTO_PCIE_IIO1P8 0x06E8 +#define VFR_FORMID_RTO_PCIE_IIO1P9 0x06E9 +#define VFR_FORMID_RTO_PCIE_IIO1P10 0x06EA +#define VFR_FORMID_RTO_PCIE_IIO1P11 0x06EB +#define VFR_FORMID_RTO_PCIE_IIO1P12 0x06EC +#define VFR_FORMID_RTO_PCIE_IIO1P13 0x06ED +#define VFR_FORMID_RTO_PCIE_IIO1P14 0x06EE +#define VFR_FORMID_RTO_PCIE_IIO1P15 0x06EF +#define VFR_FORMID_RTO_PCIE_IIO1P16 0x06F0 +#define VFR_FORMID_RTO_PCIE_IIO1P17 0x06F1 +#define VFR_FORMID_RTO_PCIE_IIO1P18 0x06F2 +#define VFR_FORMID_RTO_PCIE_IIO1P19 0x06F3 +#define VFR_FORMID_RTO_PCIE_IIO1P20 0x06F4 +#define VFR_FORMID_RTO_PCIE_IIO2P0 0x06F5 +#define VFR_FORMID_RTO_PCIE_IIO2P1 0x06F6 +#define VFR_FORMID_RTO_PCIE_IIO2P2 0x06F7 +#define VFR_FORMID_RTO_PCIE_IIO2P3 0x06F8 +#define VFR_FORMID_RTO_PCIE_IIO2P4 0x06F9 +#define VFR_FORMID_RTO_PCIE_IIO2P5 0x06FA +#define VFR_FORMID_RTO_PCIE_IIO2P6 0x06FB +#define VFR_FORMID_RTO_PCIE_IIO2P7 0x06FC +#define VFR_FORMID_RTO_PCIE_IIO2P8 0x06FD +#define VFR_FORMID_RTO_PCIE_IIO2P9 0x06FE +#define VFR_FORMID_RTO_PCIE_IIO2P10 0x06FF +#define VFR_FORMID_RTO_PCIE_IIO2P11 0x0700 +#define VFR_FORMID_RTO_PCIE_IIO2P12 0x0701 +#define VFR_FORMID_RTO_PCIE_IIO2P13 0x0702 +#define VFR_FORMID_RTO_PCIE_IIO2P14 0x0703 +#define VFR_FORMID_RTO_PCIE_IIO2P15 0x0704 +#define VFR_FORMID_RTO_PCIE_IIO2P16 0x0705 +#define VFR_FORMID_RTO_PCIE_IIO2P17 0x0706 +#define VFR_FORMID_RTO_PCIE_IIO2P18 0x0707 +#define VFR_FORMID_RTO_PCIE_IIO2P19 0x0708 +#define VFR_FORMID_RTO_PCIE_IIO2P20 0x0709 + +#define VFR_FORMID_RTO_PCIE_IIO3P0 0x070A +#define VFR_FORMID_RTO_PCIE_IIO3P1 0x070B +#define VFR_FORMID_RTO_PCIE_IIO3P2 0x070C +#define VFR_FORMID_RTO_PCIE_IIO3P3 0x070D +#define VFR_FORMID_RTO_PCIE_IIO3P4 0x070E +#define VFR_FORMID_RTO_PCIE_IIO3P5 0x070F +#define VFR_FORMID_RTO_PCIE_IIO3P6 0x0710 +#define VFR_FORMID_RTO_PCIE_IIO3P7 0x0711 +#define VFR_FORMID_RTO_PCIE_IIO3P8 0x0712 +#define VFR_FORMID_RTO_PCIE_IIO3P9 0x0713 +#define VFR_FORMID_RTO_PCIE_IIO3P10 0x0714 +#define VFR_FORMID_RTO_PCIE_IIO3P11 0x0715 +#define VFR_FORMID_RTO_PCIE_IIO3P12 0x0716 +#define VFR_FORMID_RTO_PCIE_IIO3P13 0x0717 +#define VFR_FORMID_RTO_PCIE_IIO3P14 0x0718 +#define VFR_FORMID_RTO_PCIE_IIO3P15 0x0719 +#define VFR_FORMID_RTO_PCIE_IIO3P16 0x071A +#define VFR_FORMID_RTO_PCIE_IIO3P17 0x071B +#define VFR_FORMID_RTO_PCIE_IIO3P18 0x071C +#define VFR_FORMID_RTO_PCIE_IIO3P19 0x071D +#define VFR_FORMID_RTO_PCIE_IIO3P20 0x071E + +#define VFR_FORMID_RTO_IIO0 0x071F +#define VFR_FORMID_RTO_IIO1 0x0720 +#define VFR_FORMID_RTO_IIO2 0x0721 +#define VFR_FORMID_RTO_IIO3 0x0722 + +#define VFR_FORMID_PCIEAIC 0x0723 +#define VFR_FORMID_PCIEAIC_IIO0 0x0724 +#define VFR_FORMID_PCIEAIC_IIO1 0x0725 +#define VFR_FORMID_PCIEAIC_IIO2 0x0726 +#define VFR_FORMID_PCIEAIC_IIO3 0x0727 + +#define VFR_FORMLABLE_SOCKET_TOP 0x4062 +#define VFR_FORMLABLE_SOCKET_BOTTOM 0x4063 + +// +// Defines used for variables to be range checked before consumption. +// +#define MAX_CAS_LATENCY 32 +#define MAX_TRP_LATENCY 32 +#define MAX_TRCD_LATENCY 32 +#define MAX_TRRD_LATENCY 255 +#define MAX_TWTR_LATENCY 255 +#define MAX_TRAS_LATENCY 63 +#define MAX_TRTP_LATENCY 255 +#define MAX_TWR_LATENCY 50 +#define MAX_TFAW_LATENCY 63 +#define MAX_TCWL_LATENCY 31 +#define MAX_TRC_LATENCY 255 +#define MAX_REFRESH_RATE 32767 +#define MAX_TRFC_LATENCY 1023 +#define MAX_MC_BGF_THRESHOLD 15 + + +//Per Socket forms for active core count and IOT options +#define VFR_FORMID_PER_SOCKET 0x300 +#define VFR_FORMID_CPU_SOCKET0 0x301 +#define VFR_FORMID_CPU_SOCKET1 0x302 +#define VFR_FORMID_CPU_SOCKET2 0x303 +#define VFR_FORMID_CPU_SOCKET3 0x304 +#define VFR_FORMID_CPU_SOCKET4 0x305 +#define VFR_FORMID_CPU_SOCKET5 0x306 +#define VFR_FORMID_CPU_SOCKET6 0x307 +#define VFR_FORMID_CPU_SOCKET7 0x308 +#define VFR_FORMID_IIO_ERR 0x309 + +#define SOCKET0_CPUPWRADVPMCFG_FORMID 0x310 +#define SOCKET1_CPUPWRADVPMCFG_FORMID 0x311 +#define SOCKET2_CPUPWRADVPMCFG_FORMID 0x312 +#define SOCKET3_CPUPWRADVPMCFG_FORMID 0x313 +#define SOCKET4_CPUPWRADVPMCFG_FORMID 0x314 +#define SOCKET5_CPUPWRADVPMCFG_FORMID 0x315 +#define SOCKET6_CPUPWRADVPMCFG_FORMID 0x316 +#define SOCKET7_CPUPWRADVPMCFG_FORMID 0x317 + +//P State Control Form +#define P_STATE_CONTROL_FORMID 0x380 +#define XE_RATIO_LIMIT_FORMID 0x381 +#define VID_OPTIONS_FORM_ID 0x382 + +//HWPM control Form +#define HWPM_STATE_CONTROL_FORMID 0x385 + +//C State Control Form +#define CPU0_CSTATE_CONTROL_FORM_ID 0x390 +#define HLV_SASV_FORM_ID 0x391 + +//T State Control Form +#define CPU_TSTATE_CONTROL_FORM_ID 0x392 + +//CPU Theraml Management +#define CPU_THERMMAL_MANAGE_FORM_ID 0x393 + +//Package C State Control +#define PACKAGE_CSTATE_CONTROL_FORM_ID 0x394 + +//DST 2.0 +#define CPU_THERMAL_DTS_2_0_FORM_ID 0x395 + +//Advacned PM Tuning Form +#define CPU_POWER_ADVANCED_CONFIG_FORM_ID 0x3A0 +#define ENERGY_PERF_BIAS_FORM_ID 0x3A1 +//#define PROG_POWERCTL_MSR_FORM_ID 0x3A2 +#define PROG_MSR_PP_CURT_CFG_CTRL_FORM_ID 0x3A3 +#define PROG_MSR_PP_CURT_PSI_CONFIG_FORM_ID 0x3A4 +#define PROG_ENTRY_CRITERIA_FORM_ID 0x3A5 +#define PROG_CSR_SWLTROVRD_FORM_ID 0x3A6 +#define PROG_CSR_DYNAMIC_PERF_POWER_CTL_FORM_ID 0x3A7 +#define PROG_CSR_SAPMCTL_FORM_ID 0x3A8 +#define PROG_CSR_PERF_P_LIMIT_FORM_ID 0x3A9 + +#define DRAM_RAPL_FORMID 0x3B0 +#define SOCKET_RAPL_FORMID 0x3C0 + +#define ACPI_S_STATE_FORMID 0x3D0 + +#define PROG_CSR_PMAX_CONFIG_FORM_ID 0x3E0 + +#define SOCKET0_PKGCENTRY_FORMID 0x3F0 +#define SOCKET1_PKGCENTRY_FORMID 0x3F1 +#define SOCKET2_PKGCENTRY_FORMID 0x3F2 +#define SOCKET3_PKGCENTRY_FORMID 0x3F3 +#define SOCKET4_PKGCENTRY_FORMID 0x3F4 +#define SOCKET5_PKGCENTRY_FORMID 0x3F5 +#define SOCKET6_PKGCENTRY_FORMID 0x3F6 +#define SOCKET7_PKGCENTRY_FORMID 0x3F7 + +#define SOCKET0_PKGCSAPM_FORMID 0x3F8 +#define SOCKET1_PKGCSAPM_FORMID 0x3F9 +#define SOCKET2_PKGCSAPM_FORMID 0x3FA +#define SOCKET3_PKGCSAPM_FORMID 0x3FB +#define SOCKET4_PKGCSAPM_FORMID 0x3FC +#define SOCKET5_PKGCSAPM_FORMID 0x3FD +#define SOCKET6_PKGCSAPM_FORMID 0x3FE +#define SOCKET7_PKGCSAPM_FORMID 0x3FF + +#define SOCKET0_PMAX_CONFIG_FORMID 0x400 +#define SOCKET1_PMAX_CONFIG_FORMID 0x401 +#define SOCKET2_PMAX_CONFIG_FORMID 0x402 +#define SOCKET3_PMAX_CONFIG_FORMID 0x403 +#define SOCKET4_PMAX_CONFIG_FORMID 0x404 +#define SOCKET5_PMAX_CONFIG_FORMID 0x405 +#define SOCKET6_PMAX_CONFIG_FORMID 0x406 +#define SOCKET7_PMAX_CONFIG_FORMID 0x407 + +// {516D5A04-C0D5-4657-B908-E4FB1D935EF0} +#define SOCKET_FORMSET_GUID \ + { \ + 0x516d5a04, 0xc0d5, 0x4657, 0xb9, 0x8, 0xe4, 0xfb, 0x1d, 0x93, 0x5e, 0xf= 0 \ + } + +// {DD84017E-7F52-48F9-B16E-50ED9E0DBE27} +#define SOCKET_IIO_CONFIG_GUID \ + { \ + 0xdd84017e, 0x7f52, 0x48f9, 0xb1, 0x6e, 0x50, 0xed, 0x9e, 0xd, 0xbe, 0= x27 \ + } + +// {4402CA38-808F-4279-BCEC-5BAF8D59092F} +#define SOCKET_COMMONRC_CONFIG_GUID \ + { \ + 0x4402ca38, 0x808f, 0x4279, 0xbc, 0xec, 0x5b, 0xaf, 0x8d, 0x59, 0x09, = 0x2f \ + } + +// {2B9B22DE-2AD4-4ABC-957D-5F18C504A05C} +#define SOCKET_MP_LINK_CONFIG_GUID \ + { \ + 0x2b9b22de, 0x2ad4, 0x4abc, 0x95, 0x7d, 0x5f, 0x18, 0xc5, 0x04, 0xa0, = 0x5c \ + } + +// {CA3FF937-D646-4936-90E8-1B950649B389} +#define SOCKET_PCI_RESOURCE_CONFIG_DATA_GUID \ + { \ + 0xca3ff937, 0xd646, 0x4936, 0x90, 0xe8, 0x1b, 0x95, 0x06, 0x49, 0xb3, = 0x89 \ + } + +// {98CF19ED-4109-4681-B79D-9196757C7824} +#define SOCKET_MEMORY_CONFIG_GUID \ + { \ + 0x98cf19ed, 0x4109, 0x4681, 0xb7, 0x9d, 0x91, 0x96, 0x75, 0x7c, 0x78, = 0x24 \ + } + +// {6BE64B20-C679-4ECD-ACE8-87AB4B70EC06} +#define SOCKET_MISC_CONFIG_GUID \ + { \ + 0x6be64b20, 0xc679, 0x4ecd, 0xac, 0xe8, 0x87, 0xab, 0x4b, 0x70, 0xec, = 0x6 \ + } +// {A1047342-BDBA-4DAE-A67A-40979B65C7F8} +#define SOCKET_POWERMANAGEMENT_CONFIG_GUID \ + { \ + 0xA1047342, 0xBDBA, 0x4DAE, 0xA6, 0x7A, 0x40, 0x97, 0x9B, 0x65, 0xC7, = 0xF8 \ + } +// {07013588-C789-4E12-A7C3-88FAFAE79F7C} +#define SOCKET_PROCESSORCORE_CONFIG_GUID \ + { \ + 0x07013588, 0xC789, 0x4E12, 0xA7, 0xC3, 0x88, 0xFA, 0xFA, 0xE7, 0x9F, = 0x7C \ + } +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UncoreCommonIncl= udes.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UncoreCommonIncludes= .h new file mode 100644 index 0000000000..a80d492d24 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UncoreCommonIncludes.h @@ -0,0 +1,354 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _UNCORE_COMMON_INCLUDES_H_ +#define _UNCORE_COMMON_INCLUDES_H_ + +#ifndef V_INTEL_VID +#define V_INTEL_VID 0x8086 +#endif + +#ifndef MAX_CORE +#define MAX_CORE 28 // Maximum cores per C= PU (SKX) +#define MAX_CORE_BITMASK 0xFFFFFFF // for SKX CPU +#endif + +#define MAX_PROCESSOR_CORE_RATIO 100 +#define DEFAULT_PROCESSOR_CORE_RATIO 23 +#define MAX_SCRAMBLE_SEED_LOW 65535 +#define MAX_SCRAMBLE_SEED_HIGH 65535 +#define ITURBO_MODE_TRADITIONAL 0 +#define ITURBO_MODE_POWER_OPTIMIZED 4 +#define MAX_PROCESSOR_TSEG 5 + + +// Define the different SKX package Sku's +#define SKX_PHY_CHOP_HCC 0x2 +#define SKX_PHY_CHOP_MCC 0x1 +#define SKX_PHY_CHOP_LCC 0x0 + +// +// Defines used for variables to be range checked before consumption. +// For MiniBIOS support, these are also defined in +// so any changes here need to be updated in these files as well. +// If you change this, please also update CPU_FAMILY_XXX in \Library\ProcM= emInit\Include\CpuPciAccess.h, Library\ProcessorStartup\Ia32\ProcessorStart= upPlatform.inc +#ifndef CPU_FAMILY_HSX +#define CPU_FAMILY_HSX 0x306F // Haswell CPU +#endif +#ifndef CPU_FAMILY_SKX +#define CPU_FAMILY_SKX 0x5065 // Skylake CPU +#endif + +// SKX REV_ID SiliconID SteppingID CPUID ChopType +// A0 0 0 0 0x50650 3 +// A1 0 1 0 0x50650 3 +// A2 2 2 1 0x50651 3 +// B0 3 3 2 0x50652 3 +// L0 4 4 2 0x50652 2 +// B1 5 5 3 0x50653 3 +// H0 6 6 4 0x50654 3 (xcc) +// M0 7 6 4 0x50654 2 (hcc) +// U0 8 6 4 0x50654 0 (lcc) +// +// xy_REV_SKX is the logical ID for BIOS to distinguish the Si +// A0 and A1 still keep to 0 +// +#ifndef A0_REV +#define A0_REV 0x00 +#endif +#ifndef A0_REV_SKX +#define A0_REV_SKX A0_REV +#endif +#ifndef A1_REV_SKX +#define A1_REV_SKX A0_REV +#endif +#ifndef A2_REV_SKX +#define A2_REV_SKX 0x02 +#endif +#ifndef B0_REV_SKX +#define B0_REV_SKX 0x03 +#endif +#ifndef L0_REV_SKX +#define L0_REV_SKX 0x04 +#endif +#ifndef B1_REV_SKX +#define B1_REV_SKX 0x05 +#endif +#ifndef H0_REV_SKX +#define H0_REV_SKX 0x06 +#endif +#ifndef M0_REV_SKX +#define M0_REV_SKX 0x07 +#endif +#ifndef U0_REV_SKX +#define U0_REV_SKX 0x08 +#endif + +#ifndef C0_REV_SKX +#define C0_REV_SKX 0x09 +#endif + +// +// Xy_CPU_STEP is from CPUID +// +#ifndef A0_CPU_STEP +#define A0_CPU_STEP 0x00 +#endif +#ifndef A1_CPU_STEP +#define A1_CPU_STEP A0_CPU_STEP +#endif +#ifndef A2_CPU_STEP +#define A2_CPU_STEP 0x01 +#endif +#ifndef B0_CPU_STEP +#define B0_CPU_STEP 0x02 +#endif +#ifndef L0_CPU_STEP +#define L0_CPU_STEP 0x02 +#endif +#ifndef B1_CPU_STEP +#define B1_CPU_STEP 0x03 +#endif +#ifndef H0_CPU_STEP +#define H0_CPU_STEP 0x04 +#endif +#ifndef M0_CPU_STEP +#define M0_CPU_STEP 0x04 +#endif +#ifndef U0_CPU_STEP +#define U0_CPU_STEP 0x04 +#endif + +#ifndef C0_CPU_STEP +#define C0_CPU_STEP 0x05 +#endif + +#include "MaxSocket.h" + +#define MAX_THREAD 2 +#define MAX_DIE 1 +#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE *= MAX_SOCKET) + +#ifndef MAX_HA +#define MAX_HA 2 +#endif + + +// If you change this, please also update MAX_KTI_PORTS in \Library\ProcMe= mInit\Platform\Include\PlatformHost.h +#ifndef MAX_KTI_PORTS +#define MAX_KTI_PORTS 3 // Max KTI por= ts supported +#endif + +// If you change this, please also update MAX_IMC in Library\ProcMemInit\I= nclude\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\P= latform\Include\MemDefaults.h +#ifndef MAX_IMC +#define MAX_IMC 2 // Maximum mem= ory controllers per socket +#endif + +// If you change this, please also update MAX_MC_CH in Library\ProcMemInit= \Include\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\P= latform\Include\MemDefaults.h +#ifndef MAX_MC_CH +#define MAX_MC_CH 3 // Max number = of channels per MC (3 for EP) +#endif + + +// If you change this, please also update MAX_CH in Library\ProcMemInit\In= clude\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\P= latform\Include\MemDefaults.h +#ifndef MAX_CH +#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max c= hannels per socket (worst case EP * EX combination =3D 16) +#endif + +// If you change this, please also update MAX_DIMM in Library\ProcMemInit\= Include\MemHostChip.h +#ifndef MAX_DIMM +#define MAX_DIMM 2 // Max DIMM = per channel +#endif + +// If you change this, please also update MC_MAX_NODE in Library\ProcMemIn= it\Include\MemHostChip.h +#ifndef MC_MAX_NODE +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max numbe= r of memory nodes +#endif + +// If you change this, please also update MAX_SYS_CH in Library\ProcMemIni= t\Include\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\P= latform\Include\MemDefaults.h +#ifndef MAX_SYS_CH +#define MAX_SYS_CH (MAX_CH * MAX_SOCKET) // Max chann= els in the system +#endif +#define MAX_SYS_DIMM MAX_SYS_CH * MAX_DIMM + +#define MAX_CRS_ENTRIES_PER_NODE 8 // Max numbe= r of ranges allowed on a memory node +#ifndef NUMBER_PORTS_PER_SOCKET +#define NUMBER_PORTS_PER_SOCKET 21 +#endif + +#ifndef CB3_DEVICES_PER_SOCKET +#define CB3_DEVICES_PER_SOCKET 8 +#endif + +#ifndef TOTAL_CB3_DEVICES +#if MAX_SOCKET > 4 +#define TOTAL_CB3_DEVICES 64 // Todo Check SKX CB3 devices (= IOAT_TOTAL_FUNCS * MAX_SOCKET). Note: this covers up to 8S. +#else +#define TOTAL_CB3_DEVICES 32 // Todo Check SKX CB3 devices. +#endif +#endif + +#ifndef MaxIIO +#define MaxIIO MAX_SOCKET +#endif + +#ifndef MAX_TOTAL_PORTS +#if MAX_SOCKET > 4 +#define MAX_TOTAL_PORTS 168 //NUMBER_PORTS_PER_SOCKET * Ma= xIIO. As now, treats setup S0-S3 =3D S4_S7 as optimal +#else +#define MAX_TOTAL_PORTS 84 //NUMBER_PORTS_PER_SOCKET * Max= IIO +#endif +#endif + +#ifndef TOTAL_IIO_STACKS +#if MAX_SOCKET > 4 +#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. = Not reflect architecture but only sysHost structure! +#else +#define TOTAL_IIO_STACKS 24 // MAX_SOCKET * MAX_IIO_STACK +#endif +#endif + +#ifndef NUMBER_NTB_PORTS_PER_SOCKET +#define NUMBER_NTB_PORTS_PER_SOCKET 3 +#endif + +#ifndef MAX_NTB_PORTS + +#if MAX_SOCKET > 4 +#define MAX_NTB_PORTS 24 // NUMBER_NTB_PORTS_PER_SOCKET = * MAX_SOCKET +#else +#define MAX_NTB_PORTS 12 // NUMBER_NTB_PORTS_PER_SOCKET = * MAX_SOCKET +#endif +#endif + +#ifndef VMD_STACK_PER_SOCKET +#define VMD_STACK_PER_SOCKET 3 +#endif + +#ifndef VMD_PORT_PER_STACK +#define VMD_PORT_PER_STACK 4 +#endif + +#ifndef VMD_PORTS_PER_SOCKET +#define VMD_PORTS_PER_SOCKET 12 +#endif + +#if MAX_SOCKET > 4 +#ifndef MAX_VMD_PORTS +#define MAX_VMD_PORTS 96 // VMD_PORTS_PER_SOCKET * MAX_S= OCKET +#endif + +#ifndef MAX_VMD_STACKS +#define MAX_VMD_STACKS 24 // VMD_STACK_PER_SOCKET * MAX_S= OCKET*/ +#endif +#else +#ifndef MAX_VMD_PORTS +#define MAX_VMD_PORTS 48 // VMD_PORTS_PER_SOCKET * MAX_S= OCKET +#endif + +#ifndef MAX_VMD_STACKS +#define MAX_VMD_STACKS 12 // VMD_STACK_PER_SOCKET * MAX_S= OCKET*/ +#endif +#endif + +#ifndef NUM_DEVHIDE_REGS +#define NUM_DEVHIDE_REGS 8 +#endif + +#ifndef MAX_DEVHIDE_REGS +#define MAX_DEVHIDE_REGS (MAX_IIO_STACK * NUM_DEVHIDE_REGS) +#endif + +#ifndef MAX_DEVHIDE_REGS_PER_SYSTEM + +#if MAX_SOCKET > 4 +#define MAX_DEVHIDE_REGS_PER_SYSTEM 384 //(MAX_DEVHIDE_REGS * MAX_SOCKET) +#else +#define MAX_DEVHIDE_REGS_PER_SYSTEM 192 //(MAX_DEVHIDE_REGS * MAX_SOCKET) +#endif + +#endif + + +#if MAX_SOCKET > 4 +#define MAX_TOTAL_CORE_HIDE 32 //(MAX_SOCKET * VARIABLE_FUNC3_= ELEMENTS) +#else +#define MAX_TOTAL_CORE_HIDE 16 //(MAX_SOCKET * VARIABLE_FUNC3_= ELEMENTS) +#endif + +#define MAX_IOU_PORT_DEVICES 4 + +// +// Resource Ratio units used by Uncore Init PEIM. +// +// Assumption: these values must be 2^N; Otherwise the algorithm in OemPro= cMemInit.c +// needs to be adjusted: the "if (Alignment > KTI_SOCKET_BUS_RATIO_UNIT) {= " should be +// removed when computing adjusted "Length". +// +#define KTI_SOCKET_BUS_RATIO_UNIT 0x20 +#define KTI_SOCKET_IO_RATIO_UNIT 0x2000 +#define KTI_SOCKET_MMIOL_RATIO_UNIT 0x4000000 +// +// Maximum alignment bit allowed for Socket PCI Resources. +// +#define KTI_SOCKET_MAX_BUS_ALIGNMENT 0x8 +#define KTI_SOCKET_MAX_IO_ALIGNMENT 0x10 +#define KTI_SOCKET_MAX_MMIOL_ALIGNMENT 0x20 + +#ifndef MAX_IIO_STACK +#define IIO_CSTACK 0 +#define IIO_PSTACK0 1 +#define IIO_PSTACK1 2 +#define IIO_PSTACK2 3 +#define IIO_PSTACK3 4 +#define IIO_PSTACK4 5 +#define MAX_IIO_STACK 6 +#endif + +#ifndef UNDEFINED_RAS +#define HEDT_RAS 0x0 +#define BASIC_RAS_AX 0x1 // Valid in A stepping only. +#define S1WS_RAS 0x2 // Not valid in A stepping. +#define CORE_RAS 0x3 // Not valid in A stepping . +#define STANDARD_RAS 0x4 +#define FPGA_RAS 0x5 // Not valid in A stepping. +#define ADVANCED_RAS 0x6 +#define UNDEFINED_RAS 0x7 +#endif + +// +// Defines used for variables to be range checked before consumption. +// +#define MAX_CAS_LATENCY 32 +#define MAX_TRP_LATENCY 32 +#define MAX_TRCD_LATENCY 32 +#define MAX_TRRD_LATENCY 255 +#define MAX_TWTR_LATENCY 255 +#define MAX_TRAS_LATENCY 63 +#define MAX_TRTP_LATENCY 255 +#define MAX_TWR_LATENCY 50 +#define MAX_TFAW_LATENCY 63 +#define MAX_TCWL_LATENCY 31 +#define MAX_TRC_LATENCY 255 +#define MAX_REFRESH_RATE 32767 +#define MAX_TRFC_LATENCY 1023 +#define MAX_MC_BGF_THRESHOLD 15 + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID "INTEL " +#define EFI_ACPI_OEM_TABLE_ID 0x59454C525550 // "PURLEY" +#define EFI_ACPI_OEM_REVISION 0x00000002 +#define EFI_ACPI_CREATOR_ID 0x4C544E49 // "INTL" +#define EFI_ACPI_CREATOR_REVISION 0x20091013 // Oct 13 2009 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UsraAccessType.h= b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UsraAccessType.h new file mode 100644 index 0000000000..143069b782 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UsraAccessType.h @@ -0,0 +1,195 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __USRA_ACCESS_TYPE_H__ +#define __USRA_ACCESS_TYPE_H__ + +typedef enum { + AddrTypePCIE =3D 0, + AddrTypePCIEBLK, + AddrTypeCSR, + AddrTypeMMIO, + AddrTypeIO, + AddrTypeMaximum +} USRA_ADDR_TYPE; + +typedef enum { + UsraWidth8 =3D 0, + UsraWidth16, + UsraWidth32, + UsraWidth64, + UsraWidthFifo8, + UsraWidthFifo16, + UsraWidthFifo32, + UsraWidthFifo64, + UsraWidthFill8, + UsraWidthFill16, + UsraWidthFill32, + UsraWidthFill64, + UsraWidthMaximum +} USRA_ACCESS_WIDTH; + +typedef enum { + CsrBoxInst =3D 0, + CsrChId, + CsrMcId, + CsrSubTypeMax +} CSR_INST_TYPE; + +#define USRA_ENABLE 1; +#define USRA_DISABLE 0; + +#pragma pack (1) + +typedef struct + { + UINT32 RawData32[2]; // RawData of two UINT32 type,= place holder + UINT32 AddrType:8; // Address type: CSR, PCIE, MM= IO, IO, SMBus ... + UINT32 AccessWidth:4; // The Access width for 8, 16,= 32,64 -bit access + UINT32 FastBootEn:1; // Fast Boot Flag, can be used= to log register access trace for fast boot + UINT32 S3Enable:1; // S3 Enable bit, when enabled= , it will save the write to script to support S3 + UINT32 HptrType:1; // Host Pointer type, below or= above 4GB + UINT32 ConvertedType:1; // The address type was from c= onverted type, use this field for address migration support + UINT32 RFU3:16; // Reserved for User use or Fu= ture Use + + UINT32 HostPtr:32; // The Host Pointer, to point = to Attribute buffer etc. +} ADDR_ATTRIBUTE_TYPE; + +typedef struct + { + UINT32 Offset:12; // The PCIE Register Offset + UINT32 Func:3; // The PCIE Function + UINT32 Dev:5; // The PCIE Device + UINT32 Bus:8; // The PCIE Bus + UINT32 RFU1:4; // Reserved for User use or Fu= ture Use + + UINT32 Seg:16; // The PCI Segment + UINT32 Count:16; // Access Count + +} USRA_PCIE_ADDR_TYPE; + +typedef struct + { + UINT32 Offset; // This Offset occupies 32 bi= ts. It's platform code's responsibilty to define the meaning of specific + // bits and use them according= ly. + UINT32 InstId:8; // The Box Instance, 0 based, = Index/Port within the box, Set Index as 0 if the box has only one instances + UINT32 SocketId:8; // The socket Id + UINT32 InstType:8; // The Instance Type, it can b= e Box, Memory Channel etc. + UINT32 RFU:8; // Reserved for User use or Fu= ture Ues + +} USRA_CSR_ADDR_TYPE; + +typedef struct + { + UINT32 Offset:32; // The MMIO Offset + + UINT32 OffsetH: 32; // The MMIO Offset Higher 32-b= it +} USRA_MMIO_ADDR_TYPE; + +typedef struct + { + UINT32 Offset:16; // The IO Offset + UINT32 RFU1:16; // Reserved for User use or Fu= ture Use + + UINT32 RFU2:32; // Reserved for User use or Fu= ture Use + +} USRA_IO_ADDR_TYPE; + +#pragma pack() + +typedef union { + UINT32 dwRawData[4]; + ADDR_ATTRIBUTE_TYPE Attribute; // The address attribute t= ype. + USRA_PCIE_ADDR_TYPE Pcie; + USRA_PCIE_ADDR_TYPE PcieBlk; + USRA_CSR_ADDR_TYPE Csr; + USRA_MMIO_ADDR_TYPE Mmio; + USRA_IO_ADDR_TYPE Io; +} USRA_ADDRESS; + +// +// Assemble macro for USRA_PCIE_ADDR_TYPE +// +#define USRA_PCIE_SEG_ADDRESS(Address, WIDTH, SEG, BUS, DEV, FUNC, OFFSET)= \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth =3D WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypePCIE;= \ + ((USRA_ADDRESS *)(&Address))->Pcie.Seg =3D (UINT32)(SEG); \ + ((USRA_ADDRESS *)(&Address))->Pcie.Bus =3D (UINT32)(BUS) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Dev =3D (UINT32)(DEV) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Func =3D (UINT32)(FUNC) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Offset =3D (UINT32)(OFFSET) & 0x0FFF + +// +// Assemble macro for USRA_BDFO_ADDR_TYPE +// +#define USRA_PCIE_SEG_BDFO_ADDRESS(Address, WIDTH, SEG, BDFO) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth =3D WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypePCIE;= \ + ((USRA_ADDRESS *)(&Address))->Pcie.Seg =3D (UINT32)(SEG); \ + ((USRA_ADDRESS *)(&Address))->Pcie.Bus =3D (UINT32)(BDFO >> 20) & = 0xFF; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Dev =3D (UINT32)(BDFO >> 15) & = 0x1F; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Func =3D (UINT32)(BDFO >> 12) & = 0x07; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Offset =3D (UINT32)(BDFO) & 0x0FFF + +// +// Assemble macro for USRA_PCIE_BLK_ADDR_TYPE +// +#define USRA_BLOCK_PCIE_ADDRESS(Address, WIDTH, COUNT, SEG, BUS, DEV, FUNC= , OFFSET) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth =3D WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypePCIEB= LK; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Count =3D (UINT32)COUNT; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Seg =3D (UINT32)SEG; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Bus =3D (UINT32)(BUS) & 0xFF= ; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Dev =3D (UINT32)(DEV) & 0x1F= ; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Func =3D (UINT32)(FUNC) & 0x07= ; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Offset =3D (UINT32)(OFFSET) & 0x= 0FFF +// +// Assemble macro for USRA_PCIE_SEG_ADDR_TYPE +// +#define USRA_PCIE_ADDRESS(Address, WIDTH, BUS, DEV, FUNC, OFFSET) \ + USRA_PCIE_SEG_ADDRESS(Address, WIDTH, 0, BUS, DEV, FUNC, OFFSET) + +// +// Assemble macro for USRA_CSR_ADDR_TYPE +// +#define USRA_CSR_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET, INST= TYPE) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypeCSR; \ + ((USRA_ADDRESS *)(&Address))->Csr.InstType =3D INSTTYPE; \ + ((USRA_ADDRESS *)(&Address))->Csr.SocketId =3D SOCKETID; \ + ((USRA_ADDRESS *)(&Address))->Csr.InstId =3D INSTID; \ + ((USRA_ADDRESS *)(&Address))->Csr.Offset =3D CSROFFSET + +// +// Assemble macro for ZERO_USRA ADDRESS +// +#define USRA_ZERO_ADDRESS(Address) \ + ((UINT32 *)&Address)[3] =3D (UINT32)0; \ + ((UINT32 *)&Address)[2] =3D (UINT32)0; \ + ((UINT32 *)&Address)[1] =3D (UINT32)0; \ + ((UINT32 *)&Address)[0] =3D (UINT32)0 + +// +// Assemble macro for ZERO_ADDR_TYPE +// +#define USRA_ZERO_ADDRESS_TYPE(Address, AddressType) \ + ((UINT32 *)&Address)[3] =3D (UINT32)0; \ + ((UINT32 *)&Address)[2] =3D (UINT32)((AddressType) & 0x0FF); \ + ((UINT32 *)&Address)[1] =3D (UINT32)0; \ + ((UINT32 *)&Address)[0] =3D (UINT32)0 + +#define USRA_ADDRESS_COPY(DestAddrPtr, SourceAddrPtr) \ + ((UINT32 *)DestAddrPtr)[3] =3D ((UINT32 *)SourceAddrPtr)[3]; \ + ((UINT32 *)DestAddrPtr)[2] =3D ((UINT32 *)SourceAddrPtr)[2]; \ + ((UINT32 *)DestAddrPtr)[1] =3D ((UINT32 *)SourceAddrPtr)[1]; \ + ((UINT32 *)DestAddrPtr)[0] =3D ((UINT32 *)SourceAddrPtr)[0]; + +#endif + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Chip/Skx/Include/Iio/IioConfig.h b/Silicon/Intel/PurleyRefreshSiliconPkg/= Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioConfig.h new file mode 100644 index 0000000000..1c6b16ebed --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/= Skx/Include/Iio/IioConfig.h @@ -0,0 +1,300 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _IIO_CONFIG_H +#define _IIO_CONFIG_H + +#pragma pack(1) //to align members on byte boundary +typedef struct { + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D VTd Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + + UINT8 VTdSupport; + UINT8 InterruptRemap; + UINT8 CoherencySupport; + UINT8 ATS; + UINT8 PostedInterrupt; + UINT8 PassThroughDma; + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PCIE Setup Options =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 IioPresent[MAX_SOCKET]; + UINT8 VtdAcsWa; + + // Platform data needs to update these PCI Configuration settings + UINT8 SLOTIMP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot= Implemented - PCIE Capabilities (D0-10 / F0 / R0x92 / B8) + UINT16 SLOTPSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Phys= ical slot Number - Slot Capabilities (D0-10 / F0 / R0xA4 / B31:19). Change = to use 13 bits instead of 8 + UINT8 SLOTEIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Elec= tromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B= 17) + UINT8 SLOTSPLS[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot= Power Limit Scale - Slot Capabilities (D0-10 / F0 / R0xA4 / B16:15) + UINT8 SLOTSPLV[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot= Power Limit Value - Slot Capabilities (D0-10 / F0 / R0xA4 / B14:7) + UINT8 SLOTHPCAP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot= Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6) + UINT8 SLOTHPSUP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hot = Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + UINT8 SLOTPIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Powe= r Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4) + UINT8 SLOTAIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Atte= ntion Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3) + UINT8 SLOTMRLSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // MRL = Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2) + UINT8 SLOTPCP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Powe= r Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1) + UINT8 SLOTABP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Atte= ntion Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0) + UINT8 PcieSSDCapable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; = // Indicate if Port will PcieSSD capable. + + // General PCIE Configuration + UINT8 ConfigIOU0[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 0= 2-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P5p6p7p8) + UINT8 ConfigIOU1[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 0= 2-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P9p10p11p12) + UINT8 ConfigIOU2[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 0= 2-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4) + UINT8 ConfigMCP0[MAX_SOCKET]; // 04-x16 (p13) + UINT8 ConfigMCP1[MAX_SOCKET]; // 04-x16 (p14) + UINT8 CompletionTimeoutGlobal; // + UINT8 CompletionTimeoutGlobalValue; + UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CoherentReadPart; + UINT8 CoherentReadFull; + UINT8 PcieGlobalAspm; // + UINT8 StopAndScream; // + UINT8 SnoopResponseHoldOff; // + // + // PCIE capability + // + UINT8 PCIe_LTR; // + UINT8 PcieExtendedTagField; // + UINT8 PCIe_AtomicOpReq; // + UINT8 PcieMaxReadRequestSize; // + + + UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup + + + // mixc PCIE configuration + UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieAspm[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieMaxPayload[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; //On Setup + UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; //On Setup + UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup + UINT8 ExtendedSync[MAX_TOTAL_PORTS]; // On Setup + UINT8 InbandPresenceDetect[MAX_TOTAL_PORTS]; // Not implemented in = code + UINT8 PciePortDisable[MAX_TOTAL_PORTS]; // Not implemented in = code + UINT8 PciePmeIntEn[MAX_TOTAL_PORTS]; // Not implemented in = code + UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup + // + // VPP Control + // + UINT8 VppEnable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -= - Disable, 01 -- Enable //no setup option defined- aj + UINT8 VppPort[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -= - Port 0, 01 -- Port 1 //no setup option defined- aj + UINT8 VppAddress[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 01-0= 7 for SMBUS address of Vpp //no setup option defined- aj + + // + // PCIE setup options for Link Control2 + // + UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; //on Setup + UINT8 ComplianceMode[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PciePortLinkMaxWidth[MAX_TOTAL_PORTS]; // On Setup + UINT8 DeEmphasis[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for MISCCTRLSTS + // + UINT8 EOI[MAX_TOTAL_PORTS]; // On Setup + UINT8 MSIFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSINFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSICOREN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; //On Setup + UINT8 DISL0STx[MAX_TOTAL_PORTS]; //On Setup + UINT8 P2PWrtDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 Peer + UINT8 P2PRdDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 peer + UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIHP[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIPM[MAX_TOTAL_PORTS]; //On Setup + UINT8 SRIS[MAX_TOTAL_PORTS]; //On Setup + UINT8 TXEQ[MAX_TOTAL_PORTS]; //On Setup + UINT8 ECRC[MAX_TOTAL_PORTS]; //On Setup + // + // PCIE RAS (Errors) + // + + UINT8 PcieUnsupportedRequests[MAX_TOTAL_PORTS]; // Unsupported Req= uest per-port option + UINT8 Serr; + UINT8 Perr; + UINT8 IioErrorEn; + UINT8 LerEn; + UINT8 WheaPcieErrInjEn; + + // + // PciePll + // + UINT8 PciePllSsc; //On Setup + + // + // PCIE Link Training Ctrl + // + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Crystal Beach 3 Setup Options =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 Reserved1[MAX_SOCKET]; // on setup + UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 DisableTPH; + UINT8 PrioritizeTPH; + UINT8 CbRelaxedOrdering; +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D MISC IOH Setup Options =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + + // The following are for hiding each individual device and function + UINT8 PEXPHIDE[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hide any of = the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD + UINT8 PCUF6Hide; // Hide Device PCU Devic= e 30, Function 6 + UINT8 EN1K; // Enable/Disable 1K gra= nularity of IO for P2P bridges 0:20:0:98 bit 2 + UINT8 DualCvIoFlow; // Dual CV IO Flow + UINT8 PcieBiosTrainEnable; // Used as a work around= for A0 PCIe + UINT8 MultiCastEnable; // MultiCastEnable test = enable + UINT8 McastBaseAddrRegion; // McastBaseAddrRegion + UINT8 McastIndexPosition; // McastIndexPosition + UINT8 McastNumGroup; // McastNumGroup + UINT8 MctpEn; + + UINT8 LegacyVgaSoc; + UINT8 LegacyVgaStack; + + UINT8 HidePEXPMenu[MAX_TOTAL_PORTS]; // to suppress /displa= y the PCIe port menu + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D NTB Related Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 NtbPpd[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeOverride[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSplitBar[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSBar01Prefetch[MAX_NTB_PORTS]; //on setup option + UINT8 NtbXlinkCtlOverride[MAX_NTB_PORTS]; //on setup option + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D VMD Related Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 VMDEnabled[MAX_VMD_STACKS]; + UINT8 VMDPortEnable[MAX_VMD_PORTS]; + UINT8 VMDHotPlugEnable[MAX_VMD_STACKS]; + UINT8 VMDCfgBarSz[MAX_VMD_STACKS]; + UINT8 VMDCfgBarAttr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz1[MAX_VMD_STACKS]; + UINT8 VMDMemBar1Attr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz2[MAX_VMD_STACKS]; + UINT8 VMDMemBar2Attr[MAX_VMD_STACKS]; + + /** + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PcieSSD Related Setup Options =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + **/ + UINT8 PcieAICEnabled[MAX_VMD_STACKS]; // Indic= ate if PCIE AIC Device will be connected behind an specific IOUx + UINT8 PcieAICPortEnable[MAX_VMD_PORTS]; + UINT8 PcieAICHotPlugEnable[MAX_VMD_STACKS]; + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Gen3 Related Setup Options =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + + //PCIE Global Option + UINT8 NoSnoopRdCfg; //on Setup + UINT8 NoSnoopWrCfg; //on Setup + UINT8 MaxReadCompCombSize; //on Setup + UINT8 ProblematicPort; //on Setup + UINT8 DmiAllocatingFlow; //on Setup + UINT8 PcieAllocatingFlow; //on Setup + UINT8 PcieHotPlugEnable; //on Setup + UINT8 PcieAcpiHotPlugEnable; //on Setup + UINT8 HaltOnDmiDegraded; //on Setup + UINT8 RxClockWA; + UINT8 GlobalPme2AckTOCtrl; //on Setup + + UINT8 PcieSlotOprom1; //On Setup + UINT8 PcieSlotOprom2; //On Setup + UINT8 PcieSlotOprom3; //On Setup + UINT8 PcieSlotOprom4; //On Setup + UINT8 PcieSlotOprom5; //On Setup + UINT8 PcieSlotOprom6; //On Setup + UINT8 PcieSlotOprom7; //On Setup + UINT8 PcieSlotOprom8; //On Setup + UINT8 PcieSlotItemCtrl; //On Setup + UINT8 PcieRelaxedOrdering; //On Setup + UINT8 PciePhyTestMode; //On setup +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D IOAPIC Related Setup Options =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + + UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS]; +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Security Related Setup Options =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 LockChipset; + UINT8 PeciInTrustControlBit; + UINT8 ProcessorX2apic; + UINT8 ProcessorMsrLockControl; + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Iio Related Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 RtoEnable; // On Setup + UINT8 RtoLtssmLogger; // On Setup + UINT8 RtoLtssmLoggerStop; // On Setup + UINT8 RtoLtssmLoggerSpeed; // On Setup + UINT8 RtoLtssmLoggerMask; // On Setup + UINT8 RtoJitterLogger; // On Setup + UINT32 RtoSocketDevFuncHide[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Set= up + UINT8 RtoGen3NTBTestCard[MAX_TOTAL_PORTS]; // On Setup + + UINT8 RtoGen3OverrideMode[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3TestCard[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoDnTxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoRxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoUpTxPreset[MAX_TOTAL_PORTS]; //On Setup + + UINT8 InboundConfiguration[MAX_TOTAL_PORTS]; //On Setup + +} IIO_CONFIG; +#pragma pack() + +#endif // _IIO_CONFIG_H diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Chip/Skx/Include/Iio/IioPlatformData.h b/Silicon/Intel/PurleyRefreshSilic= onPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h new file mode 100644 index 0000000000..be5ce8ddec --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/= Skx/Include/Iio/IioPlatformData.h @@ -0,0 +1,298 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _IIO_PLATFORM_DATA_H_ +#define _IIO_PLATFORM_DATA_H_ + +#include +#include +#include +#include +#ifndef MINIBIOS_BUILD +#ifndef IA32 +#include +#include +#include +#define IIO_CPU_CSR_ACCESS EFI_CPU_CSR_ACCESS_PROTOCOL +#endif +#endif + +#define IIO_HANDLE VOID * +#define IIO_STATUS UINT32 + +typedef struct { + UINT8 Register; + UINT8 Function; + UINT8 Device; + UINT8 Bus; + UINT32 ExtendedRegister; +} PCI_ROOT_BRIDGE_PCI_ADDRESS; + +typedef enum { + DmiTypeVc0, + DmiTypeVc1, + DmiTypeVcm, + MaxDmiVcType +} DMI_VC_TYPE; + +typedef enum { + IioDmiTc0, + IioDmiTc1, + IioDmiTc2, + IioDmiTc3, + IioDmiTc4, + IioDmiTc5, + IioDmiTc6, + IioDmiTc7, + IioMaxDmiTc +} IIO_DMI_TC; + +typedef enum { + IIOInitPhase1 =3D 1, + IIOInitPhase2 =3D 2, + IIOInitPhase3 =3D 4, +} IIO_INIT_PHASE; + +typedef enum { + IioBeforeBifurcation, // Point before IOU Bi-fucuation and li= nk training, no generic inbound access at this point + IioAfterBifurcation, // Point immediately after IOU bifurcat= ion and link training but before any PCIe root port initialization + IioPortEnumeration, // Point before Port initialization, no= generic inbound access at this point + IioPortEnumProgramMISCCTRL, // Inside IioPortInit.PcieSlotInit + IioEnumEnd, + IioVtDPreEn, + IioVtDInit, + IioVtDEn, // At this point it has been decided to= enable VtD through setup IioVtdInit.VtdInitialization + IioPostInitEnd, // this is the last stage of IIO PCIe p= ort init + IioBeforeResources, // At this point IIO Ports configuratio= n has been completed + IioAfterResources, // At this point PCIe Resources allocat= ion has been completed + IioReadyToBoot +} IIO_INIT_ENUMERATION; + + +extern const CHAR* IioPortLabel[]; + +#define IIO_PORT_LABEL(x) ( ((x) < NUMBER_PORTS_PER_SOCKET) ? (IioPortLa= bel[(x)]) : IioPortLabel[NUMBER_PORTS_PER_SOCKET] ) + +#pragma pack(1) + +typedef union{ + struct{ + UINT32 Value; + UINT32 ValueHigh; + }Address32bit; + UINT64 Address64bit; +}IIO_PTR_ADDRESS; + +typedef struct { + UINT32 Device; + UINT32 Function; + UINT32 RegOffset; + UINT32 AndMask; + UINT32 OrMask; +} PCI_OP_STRUCT; + +typedef struct { + UINT32 Instance; + UINT32 RegOffset; + UINT32 AndMask; + UINT32 OrMask; +} CSR_ACCESS_OP_STRUCT; + +typedef struct { + UINT8 Isoc; + UINT32 meRequestedSize; + UINT8 Vc1_pri_en; + UINT8 Isoc_Enable; +} ISOC_VC_TABLE_STRUCT; + +/* + * Following are the data structure defined to support multiple CBDMA type= s on a system + */ + +typedef struct{ + UINT32 DcaSupported : 1; + UINT32 NoSnoopSupported : 1; + UINT32 RelaxOrderSupported : 1; +}CB_CONFIG_CAPABILITY; + +typedef struct{ + UINT8 CB_VER; + UINT8 BusNo; + UINT8 DevNo; + UINT8 FunNo; + UINT8 MaxNoChannels; + CB_CONFIG_CAPABILITY CBConfigCap; +}CBDMA_CONTROLLER; + +typedef struct{ + CBDMA_CONTROLLER CbDmaDevice; +}DMA_HOST; + +// <<<< end of CBDMA data structures >>>> + +typedef union { +struct { + UINT32 Dev0 : 1; + UINT32 Dev1 : 1; + UINT32 Dev2 : 1; + UINT32 Dev3 : 1; + UINT32 Dev4 : 1; + UINT32 Dev5 : 1; + UINT32 Dev6 : 1; + UINT32 Dev7 : 1; + UINT32 Dev8 : 1; + UINT32 Dev9 : 1; + UINT32 Dev10 : 1; + UINT32 Dev11 : 1; + UINT32 Dev12 : 1; + UINT32 Dev13 : 1; + UINT32 Dev14 : 1; + UINT32 Dev15 : 1; + UINT32 Dev16 : 1; + UINT32 Dev17 : 1; + UINT32 Dev18 : 1; + UINT32 Dev19 : 1; + UINT32 Dev20 : 1; + UINT32 Dev21 : 1; + UINT32 Dev22 : 1; + UINT32 Dev23 : 1; + UINT32 Dev24 : 1; + UINT32 Dev25 : 1; + UINT32 Dev26 : 1; + UINT32 Dev27 : 1; + UINT32 Dev28 : 1; + UINT32 Dev29 : 1; + UINT32 Dev30 : 1; + UINT32 Dev31 : 1; + } Bits; + UINT32 Data; +} DEVHIDE_FIELD; + +typedef struct{ + UINT32 DevToHide[NUM_DEVHIDE_REGS]; +} IIO_DEVFUNHIDE; + +typedef struct{ + IIO_DEVFUNHIDE IioStackDevHide[MAX_IIO_STACK]; +}IIO_DEVFUNHIDE_TABLE; + +typedef struct { + UINT8 CpuType; + UINT8 CpuStepping; + UINT8 CpuSubType; + UINT8 SystemRasType; + UINT8 IsocEnable; + UINT8 EVMode; + UINT32 meRequestedSize; + UINT8 DmiVc[MaxDmiVcType]; + UINT8 DmiVcId[MaxDmiVcType]; + DMI_VC_TYPE DmiTc[IioMaxDmiTc]; + UINT8 PlatformType; + UINT8 IOxAPICCallbackBootEvent; + UINT8 RasOperation; + UINT8 SocketUnderOnline; + UINT8 CompletedReadyToBootEventServices; + UINT8 SocketPresent[MaxIIO]; + UINT8 SocketBaseBusNumber[MaxIIO]; + UINT8 SocketLimitBusNumber[MaxIIO]; + UINT8 StackPresentBitmap[MaxIIO]; + UINT64_STRUCT SegMmcfgBase[MaxIIO]; + UINT8 SegmentSocket[MaxIIO]; + UINT8 SocketStackPersonality[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackBus[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackBaseBusNumber[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackLimitBusNumber[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketPortBusNumber[MaxIIO][NUMBER_PORTS_PER_SOCKET]; + UINT8 StackPerPort[MaxIIO][NUMBER_PORTS_PER_SOCKET]; + UINT8 SocketUncoreBusNumber[MaxIIO]; + UINT32 PchIoApicBase; + UINT32 PciResourceMem32Base[MaxIIO]; + UINT32 PciResourceMem32Limit[MaxIIO]; + UINT8 Pci64BitResourceAllocation; + UINT32 StackPciResourceMem32Limit[MaxIIO][MAX_IIO_STACK]; + UINT32 VtdBarAddress[MaxIIO][MAX_IIO_STACK]; + UINT32 IoApicBase[MaxIIO][MAX_IIO_STACK]; + UINT32 RcBaseAddress; + UINT64 PciExpressBase; + UINT32 PmBase; + UINT32 PchSegRegBaseAddress; + UINT8 PcieRiser1Type; + UINT8 PcieRiser2Type; + UINT8 DmiVc1; + UINT8 DmiVcm; + UINT8 Emulation; + UINT8 SkuPersonality[MAX_SOCKET]; + UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + UINT8 IODC; + UINT8 MultiPch; + UINT8 FpgaActive[MaxIIO]; +} IIO_V_DATA; + +typedef struct { + UINT8 Device; + UINT8 Function; +} IIO_PORT_INFO; + +typedef struct { + UINT8 Valid; + UINT8 IioUplinkPortIndex; //defines platform spe= cific uplink port index (if any else FF) + IIO_PORT_INFO UplinkPortInfo; +}IIO_UPLINK_PORT_INFO; + +typedef struct _INTEL_IIO_PORT_INFO { + UINT8 Device; + UINT8 Function; + UINT8 RtoDevice; + UINT8 RtoFunction; + UINT8 RtoClusterDevice; + UINT8 RtoClusterFunction; + UINT8 RtoReutLinkSel; + UINT8 SuperClusterPort; +} INTEL_IIO_PORT_INFO; + +typedef struct _INTEL_DMI_PCIE_INFO { + INTEL_IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} INTEL_DMI_PCIE_INFO; + +typedef struct _INTEL_IIO_PRELINK_DATA { + INTEL_DMI_PCIE_INFO PcieInfo; + IIO_UPLINK_PORT_INFO UplinkInfo[MaxIIO]; +} INTEL_IIO_PRELINK_DATA; + +typedef struct { + UINT8 PciePortPresent[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortConfig[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortOwnership[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 CurrentPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 MaxPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 LinkedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 SpeedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 LaneReversedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortMaxWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortNegWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortNegSpeed[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + IIO_PTR_ADDRESS PtrAddress; + IIO_PTR_ADDRESS PtrPcieTopology; + UINT64 McastRsvdMemory; + DMA_HOST DMAhost[MaxIIO]; + UINT8 resetRequired; +} IIO_OUT_DATA; + +typedef struct { + IIO_V_DATA IioVData; + INTEL_IIO_PRELINK_DATA PreLinkData; + IIO_OUT_DATA IioOutData; +} IIO_VAR; + +typedef struct { + IIO_CONFIG SetupData; + IIO_VAR IioVar; +} IIO_GLOBALS; + +#pragma pack() + +#endif //_IIO_PLATFORM_DATA_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Chip/Skx/Include/Iio/IioRegs.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Li= brary/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioRegs.h new file mode 100644 index 0000000000..9537e7c3b0 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/= Skx/Include/Iio/IioRegs.h @@ -0,0 +1,314 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _IIO_REGS_H_ +#define _IIO_REGS_H_ + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D General Defintions =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + +#define NUMBER_PORTS_PER_SOCKET 21 +#define IIO_UPLINK_PORT_INDEX 5 //Port 2A is the uplink port in= Neon-City ///TODO Check if this is required for SKX/Purley SKX_TTEST +#define MaxIIO MAX_SOCKET + +#if MAX_SOCKET > 4 +#define TOTAL_CB3_DEVICES 64 // Todo Check SKX CB3 devices (= IOAT_TOTAL_FUNCS * MAX_SOCKET). Note: this covers up to 8S. +#define MAX_TOTAL_PORTS 168 //NUMBER_PORTS_PER_SOCKET * Ma= xIIO. As now, treats setup S0-S3 =3D S4_S7 as optimal +#else +#define TOTAL_CB3_DEVICES 32 // Todo Check SKX CB3 devices. +#define MAX_TOTAL_PORTS 84 //NUMBER_PORTS_PER_SOCKET * Max= IIO +#endif + +#if MAX_SOCKET > 4 +#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. = Not reflect architecture but only sysHost structure! +#define TOTAL_SYSTEM_IIO_STACKS 32 // In term of system architectu= re support +#else +#define TOTAL_IIO_STACKS 24 // MAX_SOCKET * MAX_IIO_STACK +#define TOTAL_SYSTEM_IIO_STACKS 24 // In term of system architectu= re support +#endif + +#define NUMBER_NTB_PORTS_PER_SOCKET 3 +#if MAX_SOCKET > 4 +#define MAX_NTB_PORTS 24 // NUMBER_NTB_PORTS_PER_SOCKET = * MAX_SOCKET +#else +#define MAX_NTB_PORTS 12 // NUMBER_NTB_PORTS_PER_SOCKET = * MAX_SOCKET +#endif +#define VMD_STACK_PER_SOCKET 3 +#define VMD_PORT_PER_STACK 4 +#define VMD_PORTS_PER_SOCKET 12 +#if MAX_SOCKET > 4 +#define MAX_VMD_PORTS 96 // VMD_PORTS_PER_SOCKET * MAX_S= OCKET +#define MAX_VMD_STACKS 24 // VMD_STACK_PER_SOCKET * MAX_S= OCKET +#else +#define MAX_VMD_PORTS 48 // VMD_PORTS_PER_SOCKET * MAX_S= OCKET +#define MAX_VMD_STACKS 12 // VMD_STACK_PER_SOCKET * MAX_S= OCKET +#endif + + +#define VARIABLE_FUNC3_ELEMENTS 4 +#if MAX_SOCKET > 4 +#define MAX_TOTAL_CORE_HIDE 32 //(MAX_SOCKET * VARIABLE_FUNC3_= ELEMENTS) +#else +#define MAX_TOTAL_CORE_HIDE 16 //(MAX_SOCKET * VARIABLE_FUNC3_= ELEMENTS) +#endif + +#define MAX_IOU_PORT_DEVICES 4 + + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D IIO Root Port Defintions =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ +typedef enum { + IioPortA =3D 0, + IioPortB =3D 1, + IioPortC =3D 2, + IioPortD =3D 3 +}IIOPORTS; + +typedef enum { + IioIou0 =3D 0, + IioIou1, + IioIou2, + IioMcp0, + IioMcp1, + IioIouMax +} IIOIOUS; + +// +// Bifurcation control register shorthand +// +#define IIO_BIFURCATE_AUTO 0xFF + +// Ports 1D-1A, 2D-2A, 3D-3A +// +#define IIO_BIFURCATE_x4x4x4x4 0 +#define IIO_BIFURCATE_x4x4xxx8 1 +#define IIO_BIFURCATE_xxx8x4x4 2 +#define IIO_BIFURCATE_xxx8xxx8 3 +#define IIO_BIFURCATE_xxxxxx16 4 +#define IIO_BIFURCATE_xxxxxxxx 0xF + +#define PORT_0_INDEX 0 +#define PCIE_PORT_2_DEV 0x02 + +// IOU2 +#define PORT_1A_INDEX 1 +#define PORT_1B_INDEX 2 +#define PORT_1C_INDEX 3 +#define PORT_1D_INDEX 4 +// IOU0 +#define PORT_2A_INDEX 5 +#define PORT_2B_INDEX 6 +#define PORT_2C_INDEX 7 +#define PORT_2D_INDEX 8 +// IOU1 +#define PORT_3A_INDEX 9 +#define PORT_3B_INDEX 10 +#define PORT_3C_INDEX 11 +#define PORT_3D_INDEX 12 +//MCP0 +#define PORT_4A_INDEX 13 +#define PORT_4B_INDEX 14 +#define PORT_4C_INDEX 15 +#define PORT_4D_INDEX 16 +//MCP1 +#define PORT_5A_INDEX 17 +#define PORT_5B_INDEX 18 +#define PORT_5C_INDEX 19 +#define PORT_5D_INDEX 20 + +// +#define SOCKET_0_INDEX 0 +#define SOCKET_1_INDEX 21 +#define SOCKET_2_INDEX 42 +#define SOCKET_3_INDEX 63 +#define SOCKET_4_INDEX 84 +#define SOCKET_5_INDEX 105 +#define SOCKET_6_INDEX 126 +#define SOCKET_7_INDEX 147 + +#define PCIE_PORT_0_DEV 0x00 +#define PCIE_PORT_0_FUNC 0x00 + +#define PCIE_PORT_1A_DEV 0x00 +#define PCIE_PORT_1B_DEV 0x01 +#define PCIE_PORT_1C_DEV 0x02 +#define PCIE_PORT_1D_DEV 0x03 +#define PCIE_PORT_1A_FUNC 0x00 +#define PCIE_PORT_1B_FUNC 0x00 +#define PCIE_PORT_1C_FUNC 0x00 +#define PCIE_PORT_1D_FUNC 0x00 + +#define PCIE_PORT_2A_DEV 0x00 +#define PCIE_PORT_2B_DEV 0x01 +#define PCIE_PORT_2C_DEV 0x02 +#define PCIE_PORT_2D_DEV 0x03 +#define PCIE_PORT_2A_FUNC 0x00 +#define PCIE_PORT_2B_FUNC 0x00 +#define PCIE_PORT_2C_FUNC 0x00 +#define PCIE_PORT_2D_FUNC 0x00 + +#define PCIE_PORT_3A_DEV 0x00 +#define PCIE_PORT_3B_DEV 0x01 +#define PCIE_PORT_3C_DEV 0x02 +#define PCIE_PORT_3D_DEV 0x03 +#define PCIE_PORT_3A_FUNC 0x00 +#define PCIE_PORT_3B_FUNC 0x00 +#define PCIE_PORT_3C_FUNC 0x00 +#define PCIE_PORT_3D_FUNC 0x00 + +#define PCIE_PORT_4A_DEV 0x00 +#define PCIE_PORT_4B_DEV 0x01 +#define PCIE_PORT_4C_DEV 0x02 +#define PCIE_PORT_4D_DEV 0x03 +#define PCIE_PORT_4A_FUNC 0x00 +#define PCIE_PORT_4B_FUNC 0x00 +#define PCIE_PORT_4C_FUNC 0x00 +#define PCIE_PORT_4D_FUNC 0x00 + +#define PCIE_PORT_5A_DEV 0x00 +#define PCIE_PORT_5B_DEV 0x01 +#define PCIE_PORT_5C_DEV 0x02 +#define PCIE_PORT_5D_DEV 0x03 +#define PCIE_PORT_5A_FUNC 0x00 +#define PCIE_PORT_5B_FUNC 0x00 +#define PCIE_PORT_5C_FUNC 0x00 +#define PCIE_PORT_5D_FUNC 0x00 + +#define PCIE_PORT_GLOBAL_RTO_DEV 0x07 +#define PCIE_PORT_GLOBAL_RTO_FUNC 0x07 + +#define PCIE_PORT_0_RTO_DEV 0x07 +#define PCIE_PORT_0_RTO_FUNC 0x00 + +#define PCIE_PORT_1A_RTO_DEV 0x07 +#define PCIE_PORT_1A_RTO_FUNC 0x00 +#define PCIE_PORT_1B_RTO_DEV 0x07 +#define PCIE_PORT_1B_RTO_FUNC 0x01 +#define PCIE_PORT_1C_RTO_DEV 0x07 +#define PCIE_PORT_1C_RTO_FUNC 0x02 +#define PCIE_PORT_1D_RTO_DEV 0x07 +#define PCIE_PORT_1D_RTO_FUNC 0x03 + + +#define PCIE_PORT_2A_RTO_DEV 0x07 +#define PCIE_PORT_2A_RTO_FUNC 0x00 +#define PCIE_PORT_2B_RTO_DEV 0x07 +#define PCIE_PORT_2B_RTO_FUNC 0x01 +#define PCIE_PORT_2C_RTO_DEV 0x07 +#define PCIE_PORT_2C_RTO_FUNC 0x02 +#define PCIE_PORT_2D_RTO_DEV 0x07 +#define PCIE_PORT_2D_RTO_FUNC 0x03 + +#define PCIE_PORT_3A_RTO_DEV 0x07 +#define PCIE_PORT_3A_RTO_FUNC 0x00 +#define PCIE_PORT_3B_RTO_DEV 0x07 +#define PCIE_PORT_3B_RTO_FUNC 0x01 +#define PCIE_PORT_3C_RTO_DEV 0x07 +#define PCIE_PORT_3C_RTO_FUNC 0x02 +#define PCIE_PORT_3D_RTO_DEV 0x07 +#define PCIE_PORT_3D_RTO_FUNC 0x03 + +#define PCIE_PORT_4A_RTO_DEV 0x07 +#define PCIE_PORT_4A_RTO_FUNC 0x00 +#define PCIE_PORT_4B_RTO_DEV 0x07 +#define PCIE_PORT_4B_RTO_FUNC 0x01 +#define PCIE_PORT_4C_RTO_DEV 0x07 +#define PCIE_PORT_4C_RTO_FUNC 0x02 +#define PCIE_PORT_4D_RTO_DEV 0x07 +#define PCIE_PORT_4D_RTO_FUNC 0x03 + +#define PCIE_PORT_5A_RTO_DEV 0x07 +#define PCIE_PORT_5A_RTO_FUNC 0x00 +#define PCIE_PORT_5B_RTO_DEV 0x07 +#define PCIE_PORT_5B_RTO_FUNC 0x01 +#define PCIE_PORT_5C_RTO_DEV 0x07 +#define PCIE_PORT_5C_RTO_FUNC 0x02 +#define PCIE_PORT_5D_RTO_DEV 0x07 +#define PCIE_PORT_5D_RTO_FUNC 0x03 + +#define PCIE_PORT_0_LINK_SEL 0x00 +#define PCIE_PORT_1A_LINK_SEL 0x00 +#define PCIE_PORT_1B_LINK_SEL 0x01 +#define PCIE_PORT_1C_LINK_SEL 0x02 +#define PCIE_PORT_1D_LINK_SEL 0x03 +#define PCIE_PORT_2A_LINK_SEL 0x00 +#define PCIE_PORT_2B_LINK_SEL 0x01 +#define PCIE_PORT_2C_LINK_SEL 0x02 +#define PCIE_PORT_2D_LINK_SEL 0x03 +#define PCIE_PORT_3A_LINK_SEL 0x00 +#define PCIE_PORT_3B_LINK_SEL 0x01 +#define PCIE_PORT_3C_LINK_SEL 0x02 +#define PCIE_PORT_3D_LINK_SEL 0x03 +#define PCIE_PORT_4A_LINK_SEL 0x00 +#define PCIE_PORT_4B_LINK_SEL 0x01 +#define PCIE_PORT_4C_LINK_SEL 0x02 +#define PCIE_PORT_4D_LINK_SEL 0x03 +#define PCIE_PORT_5A_LINK_SEL 0x00 +#define PCIE_PORT_5B_LINK_SEL 0x01 +#define PCIE_PORT_5C_LINK_SEL 0x02 +#define PCIE_PORT_5D_LINK_SEL 0x03 + +#define PCIE_PORT_0_SUPER_CLUSTER_PORT 0x00 +#define PCIE_PORT_1A_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1B_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1C_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1D_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_2A_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2B_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2C_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2D_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_3A_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3B_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3C_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3D_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_4A_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4B_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4C_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4D_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_5A_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5B_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5C_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5D_SUPER_CLUSTER_PORT 0x11 + +#define PORT_LINK_WIDTH_x16 16 +#define PORT_LINK_WIDTH_x8 8 +#define PORT_LINK_WIDTH_x4 4 +#define PORT_LINK_WIDTH_x2 2 +#define PORT_LINK_WIDTH_x1 1 + +// +// Port Config Mode +// +#define REGULAR_PCIE_OWNERSHIP 0 +#define PCIE_PORT_REGULAR_MODE 1 +#define PCIE_PORT_NTB_MODE 2 +#define VMD_OWNERSHIP 3 +#define PCIEAIC_OCL_OWNERSHIP 4 + + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Devide Hide Definitions =3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + +#define NUM_DEVHIDE_REGS 8 +// Hide all 8 Devices for every Stack +#define MAX_DEVHIDE_REGS (MAX_IIO_STACK * NUM_= DEVHIDE_REGS) +#if MaxIIO > 4 +#define MAX_DEVHIDE_REGS_PER_SYSTEM 384 //(MAX_DEVHIDE_RE= GS * MaxIIO) +#else +#define MAX_DEVHIDE_REGS_PER_SYSTEM 192 //(MAX_DEVHIDE_RE= GS * MaxIIO) +#endif + +#endif //_IIO_REGS_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Chip/Skx/Include/Iio/IioSetupDefinitions.h b/Silicon/Intel/PurleyRefreshS= iliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioSetupDefinition= s.h new file mode 100644 index 0000000000..61b7389cff --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/= Skx/Include/Iio/IioSetupDefinitions.h @@ -0,0 +1,111 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef IIOSETUPDEFINITIONS_H_ +#define IIOSETUPDEFINITIONS_H_ + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Equates common for Set= up options (.vfr/.hfr) and source files (.c/.h) =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + +#define PCIE_ASPM_AUTO 7 +#define PCIE_ASPM_DISABLE 0 +#define PCIE_ASPM_L0S_ONLY 1 +#define PCIE_ASPM_L1_ONLY 2 +#define PCIE_ASPM_L0S_L1_BOTH 3 + +#define PCIE_LINK_SPEED_AUTO 0 +#define PCIE_LINK_SPEED_GEN1 1 +#define PCIE_LINK_SPEED_GEN2 2 +#define PCIE_LINK_SPEED_GEN3 3 + +#define PCIE_L0S_4US_8US 3 +#define PCIE_L1_8US_16US 4 + +#define IIO_OPTION_AUTO 2 +#define IIO_OPTION_ENABLE 1 +#define IIO_OPTION_DISABLE 0 + +#define GEN3MANUAL_PH2_PRECURSOR_MIN 0 +#define GEN3MANUAL_PH2_CURSOR_MIN 0 +#define GEN3MANUAL_PH2_POSTCURSOR_MIN 0 + +#define GEN3MANUAL_PH2_PRECURSOR_MAX 63 +#define GEN3MANUAL_PH2_CURSOR_MAX 63 +#define GEN3MANUAL_PH2_POSTCURSOR_MAX 63 + +#define GEN3MANUAL_PH2_PRECURSOR_DEFAULT 11 +#define GEN3MANUAL_PH2_CURSOR_DEFAULT 41 +#define GEN3MANUAL_PH2_POSTCURSOR_DEFAULT 11 + +#define GEN3MANUAL_PH3_PRECURSOR_MIN 0 +#define GEN3MANUAL_PH3_CURSOR_MIN 0 +#define GEN3MANUAL_PH3_POSTCURSOR_MIN 0 + +#define GEN3MANUAL_PH3_PRECURSOR_MAX 63 +#define GEN3MANUAL_PH3_CURSOR_MAX 63 +#define GEN3MANUAL_PH3_POSTCURSOR_MAX 63 + +#define GEN3MANUAL_PH3_PRECURSOR_DEFAULT 11 +#define GEN3MANUAL_PH3_CURSOR_DEFAULT 41 +#define GEN3MANUAL_PH3_POSTCURSOR_DEFAULT 11 + +#define RTO_GEN3_OVERRIDE_MODE_UNIPHY 0 +#define RTO_GEN3_OVERRIDE_MODE_MANUAL 1 +#define RTO_GEN3_OVERRIDE_MODE_TEST_CARD 2 +#define RTO_GEN3_OVERRIDE_MODE_ALTERNATE_TXEQ 3 + +#define RTO_GEN3_TEST_CARD_LAGUNA 0 +#define RTO_GEN3_TEST_CARD_NTB 1 + +#define RTO_GEN3_EQ_MODE_TESTCARD 1 +#define RTO_GEN3_EQ_MODE_NTB_TESTCARD 2 + + +#define COMPLETION_TIMEOUT_260MS_900MS 9 + +#define SNOOP_RESP_DEF_VALUE 6 + +#define MC_INDEX_POS_12 0xC + +#define MC_NUM_GROUP_8 8 + +#define CONFIG_IOU_AUTO 0xFF + +#define NTB_BARSIZE_PBAR23_DEFAULT 0xC +#define NTB_BARSIZE_PBAR45_DEFAULT 0xC +#define NTB_BARSIZE_PBAR4_DEFAULT 0xC +#define NTB_BARSIZE_PBAR5_DEFAULT 0xC +#define NTB_BARSIZE_SBAR23_DEFAULT 0xC +#define NTB_BARSIZE_SBAR45_DEFAULT 0xC +#define NTB_BARSIZE_SBAR4_DEFAULT 0xC +#define NTB_BARSIZE_SBAR5_DEFAULT 0xC +#define NTB_IIO_XLINK_CTL_DSD_USP 2 + +#define VMD_CFG_BAR_SIZE_DEFAULT 25 +#define VMD_MEM_BAR_SIZE1_DEFAULT 25 +#define VMD_MEM_BAR_SIZE2_DEFAULT 20 + +#define VMD_32BIT_NONPREFETCH 0 +#define VMD_64BIT_NONPREFETCH 1 +#define VMD_64BIT_PREFETCH 2 + +#define IODC_DISABLE 0 +#define IODC_AUTO 1 +#define IODC_EN_REM_INVITOM_PUSH 2 +#define IODC_EN_REM_INVITOM_ALLOCFLOW 3 +#define IODC_EN_REM_INVITOM_ALLOC_NONALLOC 4 +#define IODC_EN_REM_INVITOM_AND_WCILF 5 +#define IODC_GLOBAL_KTI_OPTION 6 + +#define PCIE_PORT_DISABLE 0 +#define PCIE_PORT_ENABLE 1 +#define PCIE_PORT_AUTO 2 + +#endif /* IIOSETUPDEFINITIONS_H_ */ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Chip/Skx/Include/KtiDisc.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Librar= y/BaseMemoryCoreLib/Chip/Skx/Include/KtiDisc.h new file mode 100644 index 0000000000..44bf2ec2ff --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/= Skx/Include/KtiDisc.h @@ -0,0 +1,26 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _KTI_DISCOVERY_H_ +#define _KTI_DISCOVERY_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant c= onditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" +#include "KtiSi.h" + +#define MAX_TREE_NODES (MAX_SOCKET + 2) // 2 additional nodes since = a node will appear more than once in the tree when it is being constructed +#define MAX_RING_TREE_NODES 46 // A CPU with 3 links supported will have= 1 + 1*3 + 3*2 + 6*2 + 12*2 =3D 46 nodes maximum in ring tree +#define MAX_RINGS 6 // Maximum number of rings possible in sy= stems with upto 8 sockets (HyperCube) +#define CPUS_PER_RING 4 // # of CPUs in a CPU ring +#define VN0 0 +#define VN1 1 +#define TX 0 +#define RX 1 + +#endif // _KTI_DISCOVERY_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Chip/Skx/Include/KtiHost.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Librar= y/BaseMemoryCoreLib/Chip/Skx/Include/KtiHost.h new file mode 100644 index 0000000000..7824cfe33b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/= Skx/Include/KtiHost.h @@ -0,0 +1,136 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// Definition Flag: +// 1. KTI_HW_PLATFORM -> run with real hardware or Soft= IVT +// 2. KTI_SW_SIMULATION -> run with KTIRC Simulation +// 3. IA32 -> run with IA32 mode + + +#ifndef _KTI_HOST_H_ +#define _KTI_HOST_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant c= onditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" +#include "KtiSi.h" +#include "KtiDisc.h" + +#pragma pack(1) + +typedef INT32 KTI_STATUS; +#ifndef NULL +#define NULL 0 +#endif +#define CONST const +#define STATIC static +#define VOID void +#define VOLATILE volatile +#define KTI_SUCCESS 0 +#define KTI_REBOOT 1 +#define KTI_SNC_CHANGED 2 +#define KTI_IGNORE 3 +#define KTI_FAILURE -1 + +// +// Warning log +// +#define MAX_WARNING_LOGS 16 + +typedef enum { + NORMAL_OPERATION =3D 0, + RECOVERY_OPERATION +} SNC_COLDRESET_REGISTER_OPERATION_TYPE; + +typedef enum { + KTI_GROUP =3D 0, +} GROUP_TYPE; + +/********************************************************* + KTIRC Host Structure Related +*********************************************************/ + +typedef enum { + KTI_LINK0 =3D 0x0, + KTI_LINK1, + KTI_LINK2 +} KTI_LOGIC_LINK; + +typedef enum { + FULL_SPEED =3D 0, + HALF_SPEED +} KTI_LINK_SPEED_TYPE; + + +// +// Definitions to be used in Eparam tables: +// +typedef enum { + PER_LANES_TXEQ_ENABLED =3D 0, // each lane use different TXEQ = value + ALL_LANES_TXEQ_ENABLED // all lanes use same TXEQ value +} LANE_TXEQ_TYPE; + +// +// Number of Clusters. +// +typedef enum { + CLUSTER_MODE_1, + CLUSTER_MODE_2, +} CLUSTER_MODE; + +typedef enum { + LCC =3D 0, // 10c + MCC, // 14c + HCC, // 22c + XCC, // 28c + MAX_CHOP_TYPES +} PHYSICAL_CHOP; + + +// +// PHY settings that are system dependent. Need 1 of these for each sock= et/link/freq. +// + +typedef struct { + UINT8 SocketID; + UINT8 AllLanesUseSameTxeq; + UINT8 Freq; + UINT32 Link; + UINT32 TXEQL[20]; + UINT32 CTLEPEAK[5]; +} PER_LANE_EPARAM_LINK_INFO; + +// +// This is for full speed mode, all lanes have the same TXEQ setting +// +typedef struct { + UINT8 SocketID; + UINT8 Freq; + UINT32 Link; + UINT32 AllLanesTXEQ; + UINT8 CTLEPEAK; +} ALL_LANES_EPARAM_LINK_INFO; + +#define ADAPTIVE_CTLE 0x3f +#define PER_LANE_ADAPTIVE_CTLE 0X3f3f3f3f + +typedef enum { + TYPE_UBOX =3D 0, + TYPE_UBOX_IIO, + TYPE_MCP, + TYPE_FPGA, + TYPE_DISABLED, // This item must be prior to stack specific= disable types + TYPE_UBOX_IIO_DIS, + TYPE_MCP_DIS, + TYPE_FPGA_DIS, + TYPE_NONE +} STACK_TYPE; + +#pragma pack() + +#endif // _KTI_HOST_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Chip/Skx/Include/KtiSi.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/= BaseMemoryCoreLib/Chip/Skx/Include/KtiSi.h new file mode 100644 index 0000000000..89934b97b7 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/= Skx/Include/KtiSi.h @@ -0,0 +1,39 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _KTI_SI_H_ +#define _KTI_SI_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant c= onditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" + +/********************************************************* + KTI Topology Related +*********************************************************/ +#define SI_MAX_CPU_SOCKETS 8 // Maximum CPU sockets supported by Si +#define SI_MAX_KTI_PORTS 3 // Maximum KTI ports supported by Si + +/********************************************************* + IIO Stacks +*********************************************************/ +#define IIO_CSTACK 0 +#define IIO_PSTACK0 1 +#define IIO_PSTACK1 2 +#define IIO_PSTACK2 3 +#define IIO_PSTACK3 4 +#define IIO_PSTACK4 5 +#define MAX_IIO_STACK 6 + +/********************************************************* + M3KTI +*********************************************************/ +#define MAX_M3KTI 2 +#define MAX_PORT_IN_M3KTI 2 + +#endif // _KTI_SI_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Chip/Skx/Include/Protocol/CpuCsrAccess.h b/Silicon/Intel/PurleyRefreshSil= iconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h new file mode 100644 index 0000000000..ee2a407a40 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/= Skx/Include/Protocol/CpuCsrAccess.h @@ -0,0 +1,143 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPUCSRACCESS_PROTOCOL_H_ +#define _CPUCSRACCESS_PROTOCOL_H_ + +// +// CPU CSR Access Protocol GUID +// +// {0067835F-9A50-433a-8CBB-852078197814} +#define EFI_CPU_CSR_ACCESS_GUID \ + { \ + 0x67835f, 0x9a50, 0x433a, 0x8c, 0xbb, 0x85, 0x20, 0x78, 0x19, 0x78, 0x= 14 \ + } + +//#define REG_ADDR( bus, dev, func, reg, size ) ((size << 28) + ((bus+2) <= < 20) + (dev << 15) + (func << 12) + reg) + +typedef +UINT64 +(EFIAPI *GET_CPU_CSR_ADDRESS) ( + IN UINT8 SocId, + IN UINT8 BoxInst, + IN UINT32 Offset, + IN OUT UINT8 *Size + ); + +typedef +UINT32 +(EFIAPI *READ_CPU_CSR) ( + IN UINT8 SocId, + IN UINT8 BoxInst, + IN UINT32 Offset + ); + +typedef +VOID +(EFIAPI *WRITE_CPU_CSR) ( + IN UINT8 SocId, + IN UINT8 BoxInst, + IN UINT32 RegOffset, + IN UINT32 Data + ); + +typedef +UINT32 +(EFIAPI *READ_MC_CPU_CSR) ( + IN UINT8 SocId, + IN UINT8 McId, + IN UINT32 Offset + ); + +typedef +VOID +(EFIAPI *WRITE_MC_CPU_CSR) ( + IN UINT8 SocId, + IN UINT8 McId, + IN UINT32 RegOffset, + IN UINT32 Data + ); + +typedef +UINTN +(EFIAPI *GET_MC_CPU_ADDR) ( + IN UINT8 SocId, + IN UINT8 McId, + IN UINT32 RegOffset + ); + +typedef +UINT32 +(EFIAPI *READ_PCI_CSR) ( + IN UINT8 socket, + IN UINT32 reg + ); + +typedef +VOID +(EFIAPI *WRITE_PCI_CSR) ( + IN UINT8 socket, + IN UINT32 reg, + IN UINT32 data + ); + +typedef +UINT32 +(EFIAPI *GET_PCI_CSR_ADDR) ( + IN UINT8 socket, + IN UINT32 reg + ); + +typedef +VOID +(EFIAPI *UPDATE_CPU_CSR_ACCESS_VAR) ( + VOID + ); + +typedef +UINT32 +(EFIAPI *BIOS_2_PCODE_MAILBOX_WRITE) ( + IN UINT8 socket, + IN UINT32 command, + IN UINT32 data + ); + +typedef +UINT64 +(EFIAPI *BIOS_2_VCODE_MAILBOX_WRITE) ( + IN UINT8 socket, + IN UINT32 command, + IN UINT32 data + ); + +typedef +VOID +(EFIAPI *BREAK_AT_CHECK_POINT) ( + IN UINT8 majorCode, + IN UINT8 minorCode, + IN UINT16 data + ); + +typedef struct _EFI_CPU_CSR_ACCESS_PROTOCOL { + GET_CPU_CSR_ADDRESS GetCpuCsrAddress; + READ_CPU_CSR ReadCpuCsr; + WRITE_CPU_CSR WriteCpuCsr; + BIOS_2_PCODE_MAILBOX_WRITE Bios2PcodeMailBoxWrite; + BIOS_2_VCODE_MAILBOX_WRITE Bios2VcodeMailBoxWrite; + READ_MC_CPU_CSR ReadMcCpuCsr; + WRITE_MC_CPU_CSR WriteMcCpuCsr; + GET_MC_CPU_ADDR GetMcCpuCsrAddress; + UPDATE_CPU_CSR_ACCESS_VAR UpdateCpuCsrAccessVar; + READ_PCI_CSR ReadPciCsr; + WRITE_PCI_CSR WritePciCsr; + GET_PCI_CSR_ADDR GetPciCsrAddress; + BREAK_AT_CHECK_POINT BreakAtCheckpoint; +} EFI_CPU_CSR_ACCESS_PROTOCOL; + +extern EFI_GUID gEfiCpuCsrAccessGuid; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Chip/Skx/Include/Setup/IioUniversalData.h b/Silicon/Intel/PurleyRefreshSi= liconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h new file mode 100644 index 0000000000..c051a836c9 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/= Skx/Include/Setup/IioUniversalData.h @@ -0,0 +1,187 @@ +/** @file + +Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _IIO_UNIVERSAL_DATA_ +#define _IIO_UNIVERSAL_DATA_ + +#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, { 0xBA, 0x53= , 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } } +#include "SysHost.h" +#include "UncoreCommonIncludes.h" +#include + +//------------------------------------------------------------------------= --------------// +// Structure definitions for Universal Data Store (UDS) +//------------------------------------------------------------------------= --------------// +#define UINT64 unsigned long long + +#pragma pack(1) + + +typedef struct { + UINT8 Valid; // TRUE, if the link is valid (= i.e reached normal operation) + UINT8 PeerSocId; // Socket ID + UINT8 PeerSocType; // Socket Type (0 - CPU; 1 - II= O) + UINT8 PeerPort; // Port of the peer socket +}QPI_PEER_DATA; + +typedef struct { + UINT8 Valid; + UINT8 SocketFirstBus; + UINT8 SocketLastBus; + UINT8 segmentSocket; + UINT8 PcieSegment; + UINT64_STRUCT SegMmcfgBase; + UINT8 stackPresentBitmap; + UINT8 StackBus[MAX_IIO_STACK]; + UINT8 M2PciePresentBitmap; + UINT8 TotM3Kti; + UINT8 TotCha; + UINT32 ChaList; + UINT32 SocId; + QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info +} QPI_CPU_DATA; + +typedef struct { + UINT8 Valid; + UINT8 SocId; + QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info +} QPI_IIO_DATA; + +typedef struct { + IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} IIO_DMI_PCIE_INFO; + +typedef struct _STACK_RES { + UINT8 Personality; + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 PciResourceMem32Base; + UINT32 PciResourceMem32Limit; + UINT64 PciResourceMem64Base; + UINT64 PciResourceMem64Limit; + UINT32 VtdBarAddress; +} STACK_RES; + +typedef struct { + UINT8 Valid; + UINT8 SocketID; // Socket ID of the IIO (= 0..3) + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 PciResourceMem32Base; + UINT32 PciResourceMem32Limit; + UINT64 PciResourceMem64Base; + UINT64 PciResourceMem64Limit; + STACK_RES StackRes[MAX_IIO_STACK]; + UINT32 RcBaseAddress; + IIO_DMI_PCIE_INFO PcieInfo; + UINT8 DmaDeviceCount; +} IIO_RESOURCE_INSTANCE; + +typedef struct { + UINT16 PlatGlobalIoBase; // Global IO Base + UINT16 PlatGlobalIoLimit; // Global IO Limit + UINT32 PlatGlobalMmiolBase; // Global Mmiol base + UINT32 PlatGlobalMmiolLimit; // Global Mmiol limit + UINT64 PlatGlobalMmiohBase; // Global Mmioh Base [= 43:0] + UINT64 PlatGlobalMmiohLimit; // Global Mmioh Limit = [43:0] + QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info pe= r CPU + QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info pe= r IIO + UINT32 MemTsegSize; + UINT32 MemIedSize; + UINT64 PciExpressBase; + UINT32 PciExpressSize; + UINT32 MemTolm; + IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET]; + UINT8 numofIIO; + UINT8 MaxBusNumber; + UINT32 packageBspApicID[MAX_SOCKET]; // This data arr= ay is valid only for SBSP, not for non-SBSP CPUs. for CpuSv + UINT8 EVMode; + UINT8 Pci64BitResourceAllocation; + UINT8 SkuPersonality[MAX_SOCKET]; + UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + UINT16 IoGranularity; + UINT32 MmiolGranularity; + UINT64_STRUCT MmiohGranularity; + UINT8 RemoteRequestThreshold; + UINT64 Reserved; + BOOLEAN Simics; // TRUE - Simic= s Environtment; FALSE - H\w +} PLATFORM_DATA; + +typedef struct { + UINT8 CurrentCsiLinkSpeed;// Current programmed CSI = Link speed (Slow/Full speed mode) + UINT8 CurrentCsiLinkFrequency; // Current requested = CSI Link frequency (in GT) + UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kt= i link enabled status for PM + UINT8 IsocEnable; + UINT32 meRequestedSize; // Size of the memory range r= equested by ME FW, in MB + UINT8 DmiVc1; + UINT8 DmiVcm; + UINT32 CpuPCPSInfo; + UINT8 MinimumCpuStepping; + UINT8 LtsxEnable; + UINT8 MctpEn; + UINT8 cpuType; + UINT8 cpuSubType; + UINT8 SystemRasType; + UINT8 numCpus; // 1,..4. Total number= of CPU packages installed and detected (1..4)by QPI RC + UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask i= n the package + UINT32 ActiveCores[MAX_SOCKET];// Current actived cor= e Mask in the package + UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max = Non-turbo Ratio (per socket). + UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maxi= mum Efficiency Ratio (per socket). + UINT8 CurrentCoreToBusRatio; // Current system = Core to Bus Ratio + UINT32 IntelSpeedSelectCapable; // ISS Capable (sy= stem level) Bit[7:0] and current Config TDP Level Bit[15:8] + UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_= TDP_GET_LEVELS_INFO + UINT32 IssConfigTdpTdpInfo[MAX_SOCKET][CONFIG_TDP_MAX= _LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO + UINT32 IssConfigTdpPowerInfo[MAX_SOCKET][CONFIG_TDP_M= AX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO + UINT8 IssConfigTdpCoreCount[MAX_SOCKET][CONFIG_TDP_M= AX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT + UINT8 PbfCapable; // PBF Capab= le (Prioritized Base Frequency) + UINT64 PbfHighPriCoreMap[MAX_SOCKET]; // PBF High = Priority Cores Bitmap + UINT8 PbfP1HighRatio[MAX_SOCKET]; // PBF P1_Hi= gh Ratio + UINT8 PbfP1LowRatio[MAX_SOCKET]; // PBF P1_Lo= w Ratio + UINT32 socketPresentBitMap; // bitmap of sockets w= ith CPUs present detected by QPI RC + UINT32 FpgaPresentBitMap; // bitmap of NID w/ fp= ga present detected by QPI RC + UINT16 tolmLimit; + UINT32 tohmLimit; + UINT32 mmCfgBase; + UINT32 RcVersion; + UINT8 DdrXoverMode; // DDR 2.2 Mode + // For RAS + UINT8 bootMode; + UINT8 OutClusterOnDieEn; // Whether RC enabled COD s= upport + UINT8 OutSncEn; + UINT8 OutNumOfCluster; + UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; + UINT8 numChPerMC; + UINT8 maxCh; + UINT8 maxIMC; + UINT16 LlcSizeReg; + UINT8 chEnabled[MAX_SOCKET][MAX_CH]; + UINT8 mcId[MAX_SOCKET][MAX_CH]; + UINT8 memNode[MC_MAX_NODE]; + UINT8 IoDcMode; + UINT8 CpuAccSupport; + UINT8 SmbusErrorRecovery; + UINT8 MonitorMwaitEnabled; + UINT8 AepDimmPresent; + UINT32 VolMemMode; +} SYSTEM_STATUS; + +typedef struct { + PLATFORM_DATA PlatformData; + SYSTEM_STATUS SystemStatus; + UINT32 OemValue; +} IIO_UDS; +#pragma pack() + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/CpuHost.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/Ba= seMemoryCoreLib/Core/Include/CpuHost.h new file mode 100644 index 0000000000..c297389061 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/CpuHost.h @@ -0,0 +1,255 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef cpuhost_h +#define cpuhost_h +#include "PlatformHost.h" +#include "DataTypes.h" +#include "SysHostChipCommon.h" + +#define inline __inline + +// +// CPU ExtFamily/Family/Model bit[19:4] of cpuid(1)_eax +// +#ifndef CPU_FAMILY_HSX +#define CPU_FAMILY_HSX 0x306F // Haswell CPU +#endif +#ifndef CPU_FAMILY_SKX +#define CPU_FAMILY_SKX 0x5065 // Skylake CPU +#endif +#ifndef CPU_FAMILY_ICX +#define CPU_FAMILY_ICX 0x606a // IceLake CPU +#endif +#ifndef CPU_FAMILY_KNH +#define CPU_FAMILY_KNH 0x706F // KnightsHill CPU +#endif + + +//typedef INT32 CPU_STATUS; // this causes MiniBIOS build failure +typedef int CPU_STATUS; +#define CPU_SUCCESS 0 +#define CPU_FAILURE -1 + + +// +// Reset types needed post execution +// +#define POST_RESET_NO_RESET 0x0 +#define POST_RESET_WARM 0x2 // bit1 +#define POST_RESET_POWERGOOD 0x4 // bit2 +#define POST_RESET_AMI 0x8 // bit3 + +// +// Max reservable TOR entries defines +// +#define MAX_TOR_ENTRIES_ISOC 15 +#define MAX_TOR_ENTRIES_NORMAL 17 + +// +// Error Code used for LogError() +// +#define ERROR_CPU_BIST 0xC0 + #define ERROR_CPU_BIST_MINOR_SOME_SOCKET 0x01 + #define ERROR_CPU_BIST_MINOR_SOME_BISTRESULTMASK 0x02 + #define ERROR_CPU_BIST_MINOR_ALL 0x03 + +// +// Error Codes used for LogError() and LogWarning() +// +#define WARN_CPU_BIST 0xC0 +#define WARN_CPU_BIST_MINOR_LOWER_TILE_RANGE 0x01 +#define WARN_CPU_BIST_MINOR_MIDDLE_TILE_RANGE 0x02 +#define WARN_CPU_BIST_MINOR_UPPER_TILE_RANGE 0x03 +#define WARN_CPU_BIST_MINOR_ALL 0x04 + + +// +// MSR definitions +// +#ifndef MSR_IA32_PLATFORM_ID +#define MSR_IA32_PLATFORM_ID 0x0017 +#endif +#ifndef MSR_APIC_BASE +#define MSR_APIC_BASE 0x001B +#endif +#ifndef MSR_EBC_FREQUENCY_ID +#define MSR_EBC_FREQUENCY_ID 0x002C +#endif +#ifndef MSR_CORE_THREAD_COUNT +#define MSR_CORE_THREAD_COUNT 0x0035 +#endif +#ifndef MSR_SOCKET_ID +#define MSR_SOCKET_ID 0x0039 +#endif +#ifndef MSR_IA32_FEATURE_CONTROL +#define MSR_IA32_FEATURE_CONTROL 0x003A +#endif +#ifndef VIRTUAL_MSR_MCA_ON_NON_NEW_CACHABLE_MMIO_EN_ADDR +#define VIRTUAL_MSR_MCA_ON_NON_NEW_CACHABLE_MMIO_EN_ADDR 0x61 +#endif +#ifndef MCAONNONNEMCACHEABLEMMIO_BIT +#define MCAONNONNEMCACHEABLEMMIO_BIT 0x1 +#endif +#ifndef MSR_IA32_BIOS_UPDT_TRIG +#define MSR_IA32_BIOS_UPDT_TRIG 0x0079 +#endif +#ifndef MSR_TRACE_HUB_STH_ACPIBAR_BASE +#define MSR_TRACE_HUB_STH_ACPIBAR_BASE 0x00= 000080 +#define B_MSR_TRACE_HUB_STH_ACPIBAR_BASE_LOCK BIT0 +#define V_MSR_TRACE_HUB_STH_ACPIBAR_BASE_MASK 0x00= 03FFFF +#endif +#ifndef PCH_TRACE_HUB_FW_BASE_ADDRESS +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE= 0C0000 ///< TraceHub FW MMIO base address +#endif +#ifndef MSR_IA32_BIOS_SIGN_ID +#define MSR_IA32_BIOS_SIGN_ID 0x008B +#endif +#ifndef MSR_PLATFORM_INFO +#define MSR_PLATFORM_INFO 0x00CE +#endif +#ifndef MSR_PMG_CST_CONFIG_CONTROL +#define MSR_PMG_CST_CONFIG_CONTROL 0x00E2 +#endif +#ifndef MSR_PMG_IO_CAPTURE_BASE +#define MSR_PMG_IO_CAPTURE_BASE 0x0E4 +#endif +#ifndef MSR_MCG_CONTAIN +#define MSR_MCG_CONTAIN 0x178 +#define B_MSR_MCG_CONTAIN_PE BIT0 +#endif +#ifndef MSR_IA32_MCG_CAP +#define MSR_IA32_MCG_CAP 0x179 +#define B_MSR_MCG_CAP_GCM BIT24 +#endif +#ifndef MSR_CLOCK_FLEX_MAX +#define MSR_CLOCK_FLEX_MAX 0x0194 +#endif +#ifndef MSR_IA32_PERF_STS +#define MSR_IA32_PERF_STS 0x0198 +#endif +#ifndef MSR_IA32_PERF_CTL +#define MSR_IA32_PERF_CTL 0x0199 +#endif +#ifndef MSR_IA32_MISC_ENABLES +#define MSR_IA32_MISC_ENABLES 0x01A0 +#endif +#ifndef IA32_MISC_ENABLE +#define IA32_MISC_ENABLE 0x01A0 +#endif +#ifndef FAST_STRING_ENABLE_BIT +#define FAST_STRING_ENABLE_BIT 0x1 +#endif +#ifndef MSR_MISC_PWR_MGMT +#define MSR_MISC_PWR_MGMT 0x01AA +#endif +#ifndef MSR_TURBO_POWER_CURRENT_LIMIT +#define MSR_TURBO_POWER_CURRENT_LIMIT 0x1AC +#endif +#ifndef MSR_TURBO_RATIO_LIMIT +#define MSR_TURBO_RATIO_LIMIT 0x01AD +#endif +#ifndef MSR_POWER_CTRL +#define MSR_POWER_CTRL 0x01FC +#endif +#ifndef MSR_NO_EVICT_MODE +#define MSR_NO_EVICT_MODE 0x02E0 +#endif +#ifndef MSR_IA32_MC7_CTL +#define MSR_IA32_MC7_CTL 0x041C +#endif +#ifndef MSR_IA32_MC8_MISC2 +#define MSR_IA32_MC8_MISC2 0x0288 +#endif +#ifndef MSR_PCIEXBAR +#define MSR_PCIEXBAR 0x0300 +#endif +#ifndef MSR_PPIN_CTL +#define MSR_PPIN_CTL 0x004E +#endif +#ifndef MSR_PPIN +#define MSR_PPIN 0x004F +#endif +#ifndef MSR_MC_CTL +#define MSR_MC_CTL 0x0434 +#endif +#define MSR_UNCORE_FREQ 0x0620 + +#define MSR_UPI0_MC_STS 0x0415 +#define MSR_UPI1_MC_STS 0x0431 +#define MSR_UPI2_MC_STS 0x044d + +#ifndef MTRR_PHYS_BASE_0 +#define MTRR_PHYS_BASE_0 0x0200 +#define MTRR_PHYS_MASK_0 0x0201 +#define MTRR_PHYS_BASE_1 0x0202 +#define MTRR_PHYS_MASK_1 0x0203 +#define MTRR_PHYS_BASE_2 0x0204 +#define MTRR_PHYS_MASK_2 0x0205 +#define MTRR_PHYS_BASE_3 0x0206 +#define MTRR_PHYS_MASK_3 0x0207 +#define MTRR_PHYS_BASE_4 0x0208 +#define MTRR_PHYS_MASK_4 0x0209 +#define MTRR_PHYS_BASE_5 0x020A +#define MTRR_PHYS_MASK_5 0x020B +#define MTRR_PHYS_BASE_6 0x020C +#define MTRR_PHYS_MASK_6 0x020D +#define MTRR_PHYS_BASE_7 0x020E +#define MTRR_PHYS_MASK_7 0x020F +#define MTRR_FIX_64K_00000 0x0250 +#define MTRR_FIX_16K_80000 0x0258 +#define MTRR_FIX_16K_A0000 0x0259 +#define MTRR_FIX_4K_C0000 0x0268 +#define MTRR_FIX_4K_C8000 0x0269 +#define MTRR_FIX_4K_D0000 0x026A +#define MTRR_FIX_4K_D8000 0x026B +#define MTRR_FIX_4K_E0000 0x026C +#define MTRR_FIX_4K_E8000 0x026D +#define MTRR_FIX_4K_F0000 0x026E +#define MTRR_FIX_4K_F8000 0x026F +#define MTRR_DEF_TYPE 0x02FF + +#define MTRR_MEMORY_TYPE_UC 0x00 +#define MTRR_MEMORY_TYPE_WC 0x01 +#define MTRR_MEMORY_TYPE_WT 0x04 +#define MTRR_MEMORY_TYPE_WP 0x05 +#define MTRR_MEMORY_TYPE_WB 0x06 + +#define MTRR_DEF_TYPE_E 0x0800 +#define MTRR_DEF_TYPE_FE 0x0400 +#define MTRR_PHYS_MASK_VALID 0x0800 +#endif // MTRR_PHYS_BASE_0 + +#define CONFIG_TDP_MAX_LEVEL 5 + +// +// Memory-mapped APIC Offsets +// +#define APIC_LOCAL_APIC_ID 0x020 +#define APIC_ICR_LO 0x300 +#define APIC_ICR_HI 0x310 +#define APIC_TMR_INITIAL_CNT 0x380 +#define APIC_TMR_CURRENT_CNT 0x390 + +// +// APIC Timer runs at 133MHz and by default decrements +// the current count register at once per two clocks. +// t =3D time in milliseconds +// c =3D APIC Timer Initial Value +// c =3D (t * 10^(-6) sec) * (133 * 10^6 count/sec) * (1/2 clocks) +// Notice seconds and exponents cancel out leaving count value +// c =3D (t * 133 / 2) +// +#define APIC_TMR_1US (1 * 133 / 2) +#define APIC_TMR_10US (10 * 133 / 2) +#define APIC_TMR_20US (20 * 133 / 2) +#define APIC_TMR_100US (100 * 133 / 2) +#define APIC_TMR_200US (200 * 133 / 2) +#define APIC_TMR_10MS (10 * 1000 * 133 / 2) + + +#endif // cpuhost_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/CsrToPcieAddress.h b/Silicon/Intel/PurleyRefreshSiliconPkg/L= ibrary/BaseMemoryCoreLib/Core/Include/CsrToPcieAddress.h new file mode 100644 index 0000000000..04d0d4d790 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/CsrToPcieAddress.h @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __CSR_TO_PCIE_ADDRESS_H__ +#define __CSR_TO_PCIE_ADDRESS_H__ + + +#include + +////////////////////////////////////////////////////////////////////////// +// +// Common Silicon Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Bo= x instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Add= ress Structure + @param[out] AlignedAddress A pointer of aligned address converted f= rom USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/DataTypes.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/= BaseMemoryCoreLib/Core/Include/DataTypes.h new file mode 100644 index 0000000000..493408b256 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/DataTypes.h @@ -0,0 +1,111 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _datatypes_h +#define _datatypes_h + +typedef unsigned char BOOLEAN; +//typedef signed char INT8; // SKX TODO: All string/ASCII/ANSI character = based functions need to be ported to use CHAR type due +// to GCC difference. After that porting occurs, then INT8 should be defin= ed as signed type. MS compiler treats char as signed value. +// GNU compiler treats char as unsigned value. This creates havoc when try= ing to make code compatible with runtime libraries. So... +// henceforth all strings usage will be of type CHAR and not INT8. +typedef char CHAR; +#if defined(__GNUC__) && !defined(MINIBIOS_BUILD) +typedef signed char INT8; +#else +typedef char INT8; +#endif +typedef char CHAR8; +typedef unsigned char UINT8; +typedef short INT16; +typedef unsigned short UINT16; +typedef int INT32; +typedef unsigned int UINT32; +typedef unsigned int MMRC_STATUS; +#define MMRC_SUCCESS 0 +#define MMRC_FAILURE 0xFFFFFFFF +#ifndef CONST +#define CONST const +#endif +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif +#ifndef NULL +#define NULL ((VOID *) 0) +#endif +#ifdef MINIBIOS_BUILD +typedef unsigned long long UINT64; +#endif +typedef unsigned char UCHAR8; +typedef unsigned short CHAR16; +//typedef signed long long SINT64; +//typedef signed long SINT32; +//typedef signed short SINT16; +//typedef signed char SINT8; +#define SINT8 INT8 +#define SINT16 INT16 +#define SINT32 INT32 + +#define CONST const +#define STATIC static +#define VOID void +#define VOLATILE volatile + +#ifndef TRUE +#define TRUE ((BOOLEAN) 1 =3D=3D 1) +#endif +#ifndef FALSE +#define FALSE ((BOOLEAN) 0 =3D=3D 1) +#endif + +typedef UINT64 UINTX; + +typedef struct u64_struct { + UINT32 lo; + UINT32 hi; +} UINT64_STRUCT, *PUINT64_STRUCT; + +typedef struct u128_struct { + UINT32 one; + UINT32 two; + UINT32 three; + UINT32 four; +} UINT128; + +typedef struct { + UINT32 Data1; + UINT16 Data2; + UINT16 Data3; + UINT8 Data4[8]; +} GUID_RC; + +#ifndef NT32_BUILD +#if defined (RC_SIM) || defined (MINIBIOS_BUILD) +typedef GUID_RC EFI_GUID; +#endif // #if defined (RC_SIM) || defined (MINIBIOS_BUILD) + +#ifdef MINIBIOS_BUILD +typedef INT32 INTN; +typedef UINT32 UINTN; +typedef UINTN RETURN_STATUS; +#define MAX_BIT (1 << ((sizeof (UINTN) << 3) - 1)) +#define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCod= e))) +#define RETURN_SUCCESS 0 +#define RETURN_UNSUPPORTED ENCODE_ERROR (3) +#define EFIAPI +#define PcdUsraSupportS3 FALSE + +#endif // #ifdef MINIBIOS_BUILD +#endif // #ifndef NT32_BUILD + + +#define MAX_STRING_LENGTH 0x100 + +#endif // _datatypes_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/MemHost.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/Ba= seMemoryCoreLib/Core/Include/MemHost.h new file mode 100644 index 0000000000..a833a6dc57 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/MemHost.h @@ -0,0 +1,328 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _memhost_h +#define _memhost_h +#include "DataTypes.h" +#include "PlatformHost.h" +#include "SysRegs.h" +#include "MemRegs.h" +#include "MemDefaults.h" +#include "MrcCommonTypes.h" +#include "MemHostChipCommon.h" +#include "KtiSi.h" + +#define MAX_DIMMTABLEINDEX (MAX_CH * MAX_DIMM) + + +#define MAXFIELDVAL(bitfield) (bitfield =3D 0xffffffff) + +//EFI_GUID definition locations for different BDAT/BSSA cases + +#include + +// Debug Build code +// These should be disabled for all normal builds and only enable on deman= d for debugging +//#define DEBUG_TURNAROUNDS 1 +#define DEBUG_PERFORMANCE_STATS 1 +//#define DEBUG_RDRAND 1 +//#define DEBUG_SENSEAMP 1 + +#ifdef DEBUG_PERFORMANCE_STATS +#define MAX_NOZONE 20 +#endif // DEBUG_PERFORMANCE_STATS + +#define PGT_TIMER_ENABLE 1 +#define PGT_TIMER_DISABLE 0 + +// +// DDR3 frequencies 800 - 2666 +// DDR4 frequencies 1333 - 4200 +// +#define MAX_SUP_FREQ 28 // 26 frequencies are supp= orted (800, 1067, 1333, 1600, 1867, 2133, 2400, 2666, 2933, + // = 3200, 3400, 3467, 3600, 3733, 3800, 4000, 4200, 4266, 4400) + + + + +/// +/// External signal names +/// +typedef enum { + RAS_N, CAS_N, WE_N, + BA0, BA1, BA2, + A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A1= 6, A17, + CS0_N, CS1_N, CS2_N, CS3_N, CS4_N, CS5_N, CS6_N, CS7_N, CS8_N, CS9_N, + CKE0, CKE1, CKE2, CKE3, CKE4, CKE5, + ODT0, ODT1, ODT2, ODT3, ODT4, ODT5, + PAR, ALERT_N, + BG0, BG1, ACT_N, C0, C1, C2, + CK0, CK1, CK2, CK3, CK4, CK5, + FNV_GOOD_PARITY, DESELECT, PRECHARGE, GNT, // these are actually comma= nds as opposed to signals + gsmCsnDelim =3D INT32_MAX +} GSM_CSN; + +typedef struct { + INT16 left; + INT16 right; +} SIGNAL_EYE; + +#define MAX_PHASE 2 // MAX_PHASE + +// +// Common Core dummy defines +// + +#ifndef MAX_MC_CH +#define MAX_MC_CH 2 // Max channels per MC +#endif +#ifndef MAX_CLUSTERS +#define MAX_CLUSTERS 1 // Maximum number of clus= ters supported +#endif + +#ifndef MAX_EDC +#define MAX_EDC 1 // Maximum number of EDC = supported +#endif + +#define CATCHALL_TIMEOUT 100000 // 100 ms + +#pragma pack(push, 1) + +extern const UINT16 rankSize[MAX_TECH]; ///< Rank size in 64 MB u= nits +extern const UINT16 rankSizeDDR4[MAX_TECH]; ///< Rank size in 64 MB u= nits + + +#define ALL_DRAMS 0xFF // Indicates to write to all DRAMs when in PDA mode +#define ALL_DATABUFFERS 0xFF // Indicates to write to all Buffers in PBA M= ode + +typedef enum { +INVALID_BUS, +SMBUS, +EMRS, +CPGC, +SAD, +} BUS_TYPE; + +#ifdef SERIAL_DBG_MSG +#define MemDebugPrint(dbgInfo) debugPrintMem dbgInfo +#define MspDebugPrint(dbgInfo) debugPrintMsp dbgInfo +#define MmrcDebugPrint(dbgInfo) +#define OutputExtendedCheckpoint(dbgInfo) +#else +#define MemDebugPrint(dbgInfo) +#define MspDebugPrint(dbgInfo) +#define MmrcDebugPrint(dbgInfo) +#define OutputExtendedCheckpoint(dbgInfo) OutputCheckpoint dbgInfo +#endif + + +typedef enum +{ + MRC_PF_NULL, // All policy flags turned off. + MRC_PF_COLD =3D BIT0, // Execute MRC function on cold reset. + MRC_PF_FAST =3D BIT1, // Execute MRC function on cold reset when= S3 data is present. + MRC_PF_WARM =3D BIT2, // Execute MRC function on warm reset. + MRC_PF_S3 =3D BIT3, // Execute MRC function on S3 exit. + //MRC_PF_FULL_MRC =3D BIT4, // Execute MRC function when in Full M= RC mode. + //MRC_PF_MINI_MRC =3D BIT5, // Execute MRC function when in Mini-M= RC mode. + MRC_PF_ALL =3D 0xF // All policy flags turned off. +} PFSelectorType; + +typedef enum +{ + MRC_MP_NULL, // All policy flags turned off + MRC_MP_SERIAL =3D BIT0, // Execute function when in serial mode + MRC_MP_PARALLEL =3D BIT1, // Execute function when in parallel mode + MRC_MP_LOOP =3D BIT2, // Execute function for each socket when in = serial mode + MRC_MP_BOTH =3D MRC_MP_SERIAL | MRC_MP_PARALLEL, // Execute functi= on in both modes + MRC_MP_BOTH_LOOP =3D MRC_MP_SERIAL | MRC_MP_PARALLEL | MRC_MP_LOOP, // = Execute function in both modes and loop +} MPSelectorType; + +// +// TRR defines +// +#define PTRR_MODE BIT0 +#define TRR_MODE_A BIT1 +#define TRR_IMMUNE BIT2 +#ifdef TRR_MODE_B_SUPPORT +#define TRR_MODE_B BIT3 +#endif //TRR_MODE_B_SUPPORT + +typedef struct { + UINT8 stackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per= socket + UINT8 StackBus[MAX_SOCKET][MAX_IIO_STACK]; ///< Bus of each stack + UINT8 SocketFirstBus[MAX_SOCKET]; + UINT8 Socket10nmUboxBus0[MAX_SOCKET]; //10nm CPU use only + UINT8 SocketLastBus[MAX_SOCKET]; + UINT8 segmentSocket[MAX_SOCKET]; + UINT8 cpuType; + UINT8 stepping; + UINT32 socketPresentBitMap; + UINT32 FpgaPresentBitMap; + UINT32 mmCfgBase; + UINT8 maxCh; + UINT8 maxIMC; + UINT8 numChPerMC; + UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; + UINT8 mcId[MAX_SOCKET][MAX_CH]; + CPU_CSR_ACCESS_VAR_CHIP ///< Chip hook to enable CPU_CSR= _ACCESS_VAR fields +} CPU_CSR_ACCESS_VAR; + +#pragma pack(pop) + +/// +/// (MPT_MT - MemeoryPowerTraining_MarginType)param type for power trainin= g steps +/// +typedef enum { + GetMargin =3D 0, + TerMargin =3D 1, + BerMargin =3D 2 +} MPT_MT; + +/// +/// (MPT_PT - MemeoryPowerTraining_ParamType)param type for power training= steps +/// +typedef enum { + PerChPerByte =3D 0, + PerRank =3D 1, + PerStrobe =3D 2, + PerCh =3D 3, + PerMC =3D 4 +} MPT_PT; + +/// +/// (MPT_P - MemeoryPowerTraining_Param)param for power training steps +/// +typedef enum { + traindramron =3D 0, + trainmcodt =3D 1, + trainnontgtodt =3D 2, + trainrttwr =3D 3, + trainmcron =3D 4, + traintxeq =3D 5, + trainimode =3D 6, + trainctle =3D 7, + traintcocomp =3D 8, + traindramrxeq =3D 9, +} MPT_P; + +#define IMC0 0 +#define IMC1 1 + +// +// PPR Status +// +#define PPR_STS_SUCCESS 0x00 +#define PPR_STS_ADDR_VALID 0x01 +#define PPR_STS_FAILED 0x02 + +#define DRAM_UNKNOWN 0xFF + +#pragma pack(push, 1) +// +// -----------------------------------------------------------------------= ------ + +// +// NVRAM structures for S3 state +// + +#define MAX_CMD_CSR 16 +#define MAX_SIDE 2 + +// +// -----------------------------------------------------------------------= ------ +// +// ddrChannelSetup STRUCT 4t ; Channel setup structure declaration +// +// enabled BYTE ? ; Channel enable switch: +// ; 0 =3D channel disabled +// ; 1 =3D channel enabled +// +// options BYTE ? ; Bit-mapped options: +// +// numDimmSlots BYTE ? ; Number of Dimm slots per channel +// ; Valid options are 1, 2 or 3 +// ; MAX_DIMM is defined in mrcplatform.h. This option = can be no larger than MAX_DIMM. +// ; It overrides MAX_DIMM when it is smaller. +// +// ddrChannelSetup ENDS +// +// -----------------------------------------------------------------------= ------ +// + +// +// -----------------------------------------------------------------------= ------ +// +// Node bit-mapped options +// +// ddrSocketSetup STRUCT 4t ; Socket setup structure declaration +// +// enabled BYTE ? ; imc enable switch: +// ; 0 =3D imc disabled +// ; 1 =3D imc enabled +// +// options BYTE ? ; Bit-mapped options per socket: +// +// vrefDefaultValue BYTE ? ; Default DCP value per socket for DIMM Vref = =3D Vddq/2 +// +// vrefDcp smbDevice <> ; Defines override of DCP SMBus device and addr= ess +// ; compId =3D DCP_ISL9072X or DCP_AD5247 +// ; strapAddress +// ; busSegment +// +// ddrSocketSetup ENDS +// +// -----------------------------------------------------------------------= ------ +// + +/// +/// PPR DRAM Address +/// +typedef struct { + UINT8 dimm; + UINT8 rank; + UINT8 subRank; + UINT32 dramMask; + UINT8 bank; + UINT32 row; +} PPR_ADDR; + +// HIGH_ADDR_EN enables extention of the MMIO hole to force memory to high= address region +#define HIGH_ADDR_EN BIT0 +#define CR_MIXED_SKU BIT2 //used to enable(1)- halt on mixed sku d= iscovery and disable(0) - warn on mixed sku discovery + +//#pragma pack(pop) + +/// +/// Sub-boot state internal to MRC (8-15 are definable). The 2 main boot = types and paths through QPIRC/MRC - NormalBoot and S3Resume. +/// Within NormalBoot and S3Resume, the sub-boot type can be cold, warm, f= ast warm, fast cold, and ADR resume. These are populated +/// at the beginning of MRC so they are not applicable for QPIRC. +/// +typedef enum SubBootMode +{ + ColdBoot =3D 8, // Normal path through MRC with full mem detection= , init, training, etc. + WarmBoot =3D 9, // Warm boot path through MRC. Some functionality = can be skipped for speed. + WarmBootFast =3D 10, // Fast warm boot path uses the NVRAM structure to= skip as much MRC + // code as possible to try to get through MRC = fast. Should be as close + // as possible to the S3 flow. + ColdBootFast =3D 11, // Fast cold boot path uses the NVRAM structure to= skip as much MRC + // code as possible on a cold boot. + AdrResume =3D 12, // ADR flow can skip most of MRC (i.e. take the S3= path) for DIMMs that + // are in self-refresh. But the DIMMs that are n= ot in self-refresh + // must go through more of MRC. + Reserved13 =3D 13 +} SubBootMode; + +#define MAX_ADV_MT_LOG 16 + +#define MEM_CHIP_POLICY_DEF(x) host->var.mem.memChipPolicy.x +#define MEM_CHIP_POLICY_VALUE(host, x) host->var.mem.memChipPolicy.x +#define CHIP_FUNC_CALL(host, x) x + +#pragma pack(pop) + +#endif // _memhost_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/MemHostChipCommon.h b/Silicon/Intel/PurleyRefreshSiliconPkg/= Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h new file mode 100644 index 0000000000..87f1e2d15c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/MemHostChipCommon.h @@ -0,0 +1,122 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _memhostchipcommon_h +#define _memhostchipcommon_h + +#include "SysHostChipCommon.h" + +#define NODE_TO_SKT(node) (node / MAX_IMC) +#define SKT_TO_NODE(socket, mc) ((socket << 1) | (mc & BIT0)) +#define NODE_TO_MC(node) (node % MAX_IMC) +#define SKTMC_TO_NODE(socket, mc) ((socket * MAX_IMC) | (mc % MAX_IMC)) +#define NODECH_TO_SKTCH(node, ch) (((node % MAX_IMC)*MAX_MC_CH) + ch) + +// + +// +//MAX_CHANNELS and DYNVAR_MAX were previously defined in MmrcProjectDefini= tionsGenerated.h, but +// now are here and must be manually updated as needed depending on MMRC t= ool execution (they have been +// removed from automatic generation by the tool) +// +// Channels +// +#define MAX_CHANNELS 6 + +#define DYNVAR_MAX 51 + +#define MAX_IMC 2 + +#define MAX_MC_CH 3 // Max channel= s per MC +#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channel= s per socket +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memor= y nodes +#define MAX_DIMM 2 // Max DIMM per channel + +#define MAX_DIMM3 3 // Max DIMM per channel +#define MAX_TECH 19 // Number of entries in DR= AM technology table + +#define MAX_RIR 4 // Number of Rank Interlea= ve Register rules for DDR +#define MAX_RIR_DDRT 4 // Number of Rank Interlea= ve Register rules for NVMDIMM +#define MAX_RIR_WAYS 8 // Number of interleave wa= ys for RIR for DDR +#define TAD_RULES 8 // Number of TAD rule regi= sters +#define MAX_TAD_WAYS 3 // Number of interleave wa= ys for TAD RULES +#define SAD_RULES 24 // Number of SAD rule regi= sters +#define MAX_SAD_RULES 24 // Number of SAD rule regi= sters +#define MAX_STROBE 18 // Number of strobe groups +#define MAX_SEEDS 10 // Maximum +#if QR_DIMM_SUPPORT +#define MAX_RANK_DIMM 4 // Max ranks per DIMM +#else +#define MAX_RANK_DIMM 2 // Max ranks per DIMM +#endif +#define MAX_RANK_CH 8 // Max ranks per channel +#define MAX_SPARE_RANK 2 // Max number of spare ran= ks in a channel +#define SPD_MODULE_PART 18 // Number of bytes of modu= le part - DDR3 +#define SPD_MODULE_PART_DDR4 20 // Number of bytes of modu= le part - DDR4 +#define SAD_RULES_ADDR_RANGE 4 // Max IOT rules =3D 4, To= tal address limits (lower(4) entries each) +// Ctl FUBs +#define NUM_CTL_PLATFORM_GROUPS 4 + +// SPD Defines +//------------------------------------------------------------------------= ----- + +#pragma pack(1) + +// +// Define the WDB line. The WDB line is like the cache line. +// +#define MRC_WDB_LINES 32 +#define MRC_WDB_LINE_SIZE 64 +#define CADB_LINES 16 +// Define in the Critical Section function on what to wait. +// +typedef enum { + DoneAndRefDrained, + Done, + Immediate +} EWaitOn; + +typedef enum { + ssOne =3D 0, + ssTwo, + ssThree, + ssFour, +} TSubSequencesNumber; + +#define MAX_PHASE_IN_FINE_ADJUSTMENT 64 +#pragma pack() + +#define SKX_PCKG_TYPE 4 //CMD_CTL_DELAY_H + +#define CHIP_IOGPDLY_PSECS SKX_PCKG_TYPE + +// +// Chip specific section of the struct CPU_CSR_ACCESS_VAR +// +#define CPU_CSR_ACCESS_VAR_CHIP \ + + +typedef enum { + TYPE_SCF_BAR =3D 0, + TYPE_PCU_BAR, + TYPE_MEM_BAR0, + TYPE_MEM_BAR1, + TYPE_MEM_BAR2, + TYPE_MEM_BAR3, + TYPE_MEM_BAR4, + TYPE_MEM_BAR5, + TYPE_MEM_BAR6, + TYPE_MEM_BAR7, + TYPE_SBREG_BAR, + TYPE_MAX_MMIO_BAR +} MMIO_BARS; + + +// Output structures based on scope +#define MAX_BITS 72 + +#endif // _memhostchipcommon_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/MemRegs.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/Ba= seMemoryCoreLib/Core/Include/MemRegs.h new file mode 100644 index 0000000000..d29a5d0971 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/MemRegs.h @@ -0,0 +1,13 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _memregs_h +#define _memregs_h + +#define SPD_LR_PERS_BYTES_TOTAL 15 // LR DIMM Total number of Perso= nality Bytes + +#endif // _memregs_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/MrcCommonTypes.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Lib= rary/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h new file mode 100644 index 0000000000..0f6727924f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/MrcCommonTypes.h @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MrcCommonTypes_h_ +#define _MrcCommonTypes_h_ + +#include "DataTypes.h" + +#define INT32_MIN (0x80000000) +#ifndef INT32_MAX //INT32_MAX->Already defined +#define INT32_MAX (0x7FFFFFFF) +#endif +#define INT16_MIN (0x8000) +#define INT16_MAX (0x7FFF) + +#endif // _MrcCommonTypes_h_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/PcieAddress.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Librar= y/BaseMemoryCoreLib/Core/Include/PcieAddress.h new file mode 100644 index 0000000000..d9578056f6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/PcieAddress.h @@ -0,0 +1,65 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCIE_MMCFG_H__ +#define __PCIE_MMCFG_H__ + +#include + + +////////////////////////////////////////////////////////////////////////// +// +// PCIE MMCFG Table definition +// This table was based on PCI Firmwar Spec Rev 3.1 +// +////////////////////////////////////////////////////////////////////////// + +typedef struct + { + UINT8 Signature[4]; ///< =EF=BF=BDMCFG= =EF=BF=BD. Signature For this Table + UINT32 Length; ///< Length, in byte= s, include base address allocation structures. + UINT8 Revision; ///< "1" + UINT8 SegMax; ///< The Maximum num= ber of Segments + UINT16 ValidSegMap; ///< Valid Segment B= it Map, LSB Bit0 for Seg0, bit1 for seg1 ... + UINT8 Reserved[4]; ///< Reserved +} PCIE_MMCFG_HEADER_TYPE; + +typedef struct + { + UINT32 BaseAddressL; ///< Processor-relat= ive Base Address (Lower 32-bit) for the Enhanced Configuration Access Mecha= nism + UINT32 BaseAddressH; ///< Processor-relat= ive Base Address (Upper 32-bit) for the Enhanced Configuration Access Mecha= nism + UINT16 Segment; ///< PCI Segment Gro= up Number. Default is 0. + UINT8 StartBus; ///< Start PCI Bus n= umber decoded by the host bridge + UINT8 EndBus; ///< End PCI Bus num= ber decoded by the host bridge + UINT8 Reserved[4]; ///< Reserved +} PCIE_MMCFG_BASE_ADDRESS_TYPE; + + +typedef struct + { + PCIE_MMCFG_HEADER_TYPE Header; ///< The header of M= MCFG Table + PCIE_MMCFG_BASE_ADDRESS_TYPE MmcfgBase[1]; ///< First Arrary of= base address allocation structures. +} PCIE_MMCFG_TABLE_TYPE; + + +/** + This Lib is used for platfor to set platform specific Pcie MMCFG Table + + @param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCF= G_TABLE_TYPE type. + @param NumOfSeg: Sumber of Segments in the table. + + @retval <>NULL The function completed successfully. + @retval NULL Returen Error +**/ +UINTN +EFIAPI +SetPcieSegMmcfgTable ( + IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable, + IN UINT32 NumOfSeg +); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/Printf.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/Bas= eMemoryCoreLib/Core/Include/Printf.h new file mode 100644 index 0000000000..b531b711ed --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/Printf.h @@ -0,0 +1,74 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _printf_h +#define _printf_h + +#include "DataTypes.h" + +#define PRINTF_CONTROL_OUTOF_SYNC_ERR_MAJOR 0xCF +#define PRINTF_CONTROL_OUTOF_SYNC_ERR_MINOR 0x01 + +#define TAB_STOP 4 +#define LEFT_JUSTIFY 0x01 +#define PREFIX_SIGN 0x02 +#define PREFIX_BLANK 0x04 +#define COMMON_PREFIX_ZERO 0x08 +#define LONG_TYPE 0x10 + +#define INT_SIGNED 0x20 +#define COMA_TYPE 0x40 +#define LONG_LONG_TYPE 0x80 +#define TO_UPPER 0x100 + +#define CHAR_CR 0x0d +#define CHAR_LF 0x0a + +// +// ANSI Escape sequences for color +// +#define ANSI_FOREGROUND_BLACK 30 +#define ANSI_FOREGROUND_RED 31 +#define ANSI_FOREGROUND_GREEN 32 +#define ANSI_FOREGROUND_YELLOW 33 +#define ANSI_FOREGROUND_BLUE 34 +#define ANSI_FOREGROUND_MAGENTA 35 +#define ANSI_FOREGROUND_CYAN 36 +#define ANSI_FOREGROUND_WHITE 37 + +#define ANSI_BACKGROUND_BLACK 40 +#define ANSI_BACKGROUND_RED 41 +#define ANSI_BACKGROUND_GREEN 42 +#define ANSI_BACKGROUND_YELLOW 43 +#define ANSI_BACKGROUND_BLUE 44 +#define ANSI_BACKGROUND_MAGENTA 45 +#define ANSI_BACKGROUND_CYAN 46 +#define ANSI_BACKGROUND_WHITE 47 + +#define ANSI_ATTRIBUTE_OFF 0 +#define ANSI_ATTRIBUTE_BOLD 1 +#define ANSI_ATTRIBUTE_UNDERSCORE 4 +#define ANSI_ATTRIBUTE_BLINK 5 +#define ANSI_ATTRIBUTE_REVERSE 7 +#define ANSI_ATTRIBUTE_CONCEAL 8 + +#ifndef INT32_MAX +#define INT32_MAX 0x7fffffffU +#endif + +#ifndef va_start +typedef INT8 * va_list; +#define _INTSIZEOF(n) ((sizeof (n) + sizeof (UINT32) - 1) &~(sizeof (UIN= T32) - 1)) +#define va_start(ap, v) (ap =3D (va_list) & v + _INTSIZEOF (v)) +#define va_arg(ap, t) (*(t *) ((ap +=3D _INTSIZEOF (t)) - _INTSIZEOF (t)= )) +#define va_end(ap) (ap =3D (va_list) 0) +#endif + +#define ISDIGIT(_c) (((_c) >=3D '0') && ((_c) <=3D '9')) +#define ISHEXDIGIT(_c) (((_c) >=3D 'a') && ((_c) <=3D 'f')) + +#endif // _printf_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/SysHost.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/Ba= seMemoryCoreLib/Core/Include/SysHost.h new file mode 100644 index 0000000000..7fde63d166 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/SysHost.h @@ -0,0 +1,136 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _syshost_h +#define _syshost_h +//#define CCMRC 1 + + +#define RC_SIM_FASTCADB 0 + + + +// +// Host reset states (0-7 are definable) +// +typedef enum BootMode { + NormalBoot =3D 0, // Normal path through RC with full init, mem detect= ion, init, training, etc. + // Some of these MRC specific init routines can be = skipped based on MRC input params + // in addition to the sub-boot type (WarmBoot, Warm= BootFast, etc). + S3Resume =3D 1 // S3 flow through RC. Should do the bare minimum re= quired for S3 + // init and be optimized for speed. +} BootMode; + + +typedef struct sysHost SYSHOST, *PSYSHOST; + +#include "DataTypes.h" +#include "SysHostChipCommon.h" +#include "Printf.h" +#include "PlatformHost.h" +#include "CpuHost.h" +#include "MemHost.h" +#include "KtiHost.h" +#include "UsbDebugPort.h" + +#include "SysRegs.h" +#include "IioPlatformData.h" + +// +// ------------------------------------- +// Declarations and directives +// ------------------------------------- +// Reference Code (RC) revision in BCD format: +// [31:24] =3D Major revision number +// [23:16] =3D Minor revision number +// [15:8] =3D Release Candidate number +// +#define CCMRC_REVISION 0x00500000 + +#define SUCCESS 0 + +#define SDBG_MIN BIT0 +#define SDBG_MAX BIT1 +#define SDBG_TRACE BIT2 +#define SDBG_MEM_TRAIN BIT3 + SDBG_MAX +#define SDBG_TST BIT4 +#define SDBG_CPGC BIT5 +#define SDBG_RCWRITETAG BIT6 +#define SDBG_REG_ACCESS BIT6 // Displays = all register accesses. +#define SDBG_MINMAX SDBG_MIN + SDBG_MAX + +#define SDBG_BUF_ENABLE 1 +#define SDBG_BUF_DISABLE 0 +#define SDBG_BUF_EN_DEFAULT SDBG_BUF_DISABLE // Default d= isable + +#define SDBG_PIPE_ENABLE 1 +#define SDBG_PIPE_DISABLE 0 +#define SDBG_PIPE_DEFAULT SDBG_PIPE_DISABLE + +#define SDBG_PIPE_COMPRESS_ENABLE 1 +#define SDBG_PIPE_COMPRESS_DISABLE 0 +#define SDBG_PIPE_COMPRESS_DEFAULT SDBG_PIPE_COMPRESS_DISABLE + + +// +// -----------------------------------------------------------------------= ------ +// Variable structures +// + +// +// Warning log +// +#define MAX_LOG 64 + +#define USB_BUF_LIMIT (4096-160) +#define USB_BUF_SIZE (USB_BUF_LIMIT + 160) + +// +// System previous boot error structure +// +#define MC_BANK_STATUS_REG 1 +#define MC_BANK_ADDRESS_REG 2 +#define MC_BANK_MISC_REG 3 + +#define MSR_LOG_VALID BIT31 +#define MSR_LOG_UC BIT29 +#define MSR_LOG_EN BIT28 + +// Bit definitions for commonSetup.options +// ; PROMOTE_WARN_EN enables warnings to be treated as f= atal error +// ; PROMOTE_MRC_WARN_EN enables MRC warnings to be trea= ted as fatal error +// ; HALT_ON_ERROR_EN enables errors to loop forever +#define PROMOTE_WARN_EN BIT0 +#define PROMOTE_MRC_WARN_EN BIT1 +#define HALT_ON_ERROR_EN BIT2 + + +// -----------------------------------------------------------------------= ------ +// + +// +// Handle assertions with RC_ASSERT +// +#if defined(SIM_BUILD) || defined(IA32) || defined (HEADLESS_MRC) + +#define RC_ASSERT(assertion, majorCode, minorCode) \ + if (!(assertion)) { \ + DebugPrintRc (host, 0xFF, "\n\nRC_ASSERT! %s: %u %s ", __FILE__, __L= INE__, #assertion);\ + FatalError (host, majorCode, minorCode);\ + } + +#else + +#define RC_ASSERT(assertion, majorCode, minorCode) \ + if (!(assertion)) { \ + CpuCsrAccessError (host, "\n\nRC_ASSERT! %s: %u %s ", __FILE__, __LI= NE__, #assertion);\ + } + +#endif + + +#endif // _syshost_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/SysHostChipCommon.h b/Silicon/Intel/PurleyRefreshSiliconPkg/= Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h new file mode 100644 index 0000000000..d49767573b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/SysHostChipCommon.h @@ -0,0 +1,86 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SYSHOST_CHIP_COMMON_H_ +#define _SYSHOST_CHIP_COMMON_H_ + +#ifndef SEGMENT_ACCESS +#define SEGMENT_ACCESS +#endif + +// +// Steppings +// +#define A0_REV 0x00 + +//TODO:Need to remove the old ones. Keep for noe to allow building +#define CPU_HSX 0 +#define CPU_IVT 1 +#define CPU_BDX 2 +#define CPU_SKX 0 + +// Defines for socketType +// +#define SOCKET_2S 0 +#define SOCKET_4S 1 +#define SOCKET_HEDT 2 + +// +// CpuPciAccess +// +#define READ_ACCESS 0 +#define WRITE_ACCESS 1 + +#pragma pack(1) + +typedef union { + struct { + UINT32 Bit0:1; + UINT32 Bit1:1; + UINT32 Bit2:1; + UINT32 Bit3:1; + UINT32 Bit4:1; + UINT32 Bit5:1; + UINT32 Bit6:1; + UINT32 Bit7:1; + UINT32 Bit8:1; + UINT32 Bit9:1; + UINT32 Bit10:1; + UINT32 Bit11:1; + UINT32 Bit12:1; + UINT32 Bit13:1; + UINT32 Bit14:1; + UINT32 Bit15:1; + UINT32 Bit16:1; + UINT32 Bit17:1; + UINT32 Bit18:1; + UINT32 Bit19:1; + UINT32 Bit20:1; + UINT32 Bit21:1; + UINT32 Bit22:1; + UINT32 Bit23:1; + UINT32 Bit24:1; + UINT32 Bit25:1; + UINT32 Bit26:1; + UINT32 Bit27:1; + UINT32 Bit28:1; + UINT32 Bit29:1; + UINT32 Bit30:1; + UINT32 Bit31:1; + } Bits; + UINT32 Data; +} DUMMY_REG; + +#pragma pack() + +// +// System previous boot error structure +// +#define MAX_PREV_BOOT_ERR_ENTRIES 15 + + +#endif // _SYSHOST_CHIP_COMMON_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/SysRegs.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/Ba= seMemoryCoreLib/Core/Include/SysRegs.h new file mode 100644 index 0000000000..4ee6b7ba17 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/SysRegs.h @@ -0,0 +1,68 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _sysregs_h +#define _sysregs_h + +#include "DataTypes.h" + +#ifndef BIT0 +#define BIT0 1 +#define BIT1 (1 << 1) +#define BIT2 (1 << 2) +#define BIT3 (1 << 3) +#define BIT4 (1 << 4) +#define BIT5 (1 << 5) +#define BIT6 (1 << 6) +#define BIT7 (1 << 7) +#define BIT8 (1 << 8) +#define BIT9 (1 << 9) +#endif +#ifndef BIT10 +#define BIT10 (1 << 10) +#define BIT11 (1 << 11) +#define BIT12 (1 << 12) +#define BIT13 (1 << 13) +#define BIT14 (1 << 14) +#define BIT15 (1 << 15) +#define BIT16 (1 << 16) +#define BIT17 (1 << 17) +#define BIT18 (1 << 18) +#define BIT19 (1 << 19) +#define BIT20 (1 << 20) +#define BIT21 (1 << 21) +#define BIT22 (1 << 22) +#define BIT23 (1 << 23) +#define BIT24 (1 << 24) +#define BIT25 (1 << 25) +#define BIT26 (1 << 26) +#define BIT27 (1 << 27) +#define BIT28 (1 << 28) +#define BIT29 (1 << 29) +#define BIT30 (1 << 30) +#define BIT31 (UINT32) (1 << 31) +#endif + +#ifndef TRUE +#define TRUE ((BOOLEAN) 1 =3D=3D 1) +#endif + +#ifndef FALSE +#define FALSE ((BOOLEAN) 0 =3D=3D 1) +#endif + +#ifndef ABS +#define ABS(x) (((x) < 0) ? (-x) : (x)) +#endif +// +// disable compiler warning to use bit fields on unsigned short/long types +// +#ifdef _MSC_VER +#pragma warning(disable : 4214) +#endif + +#endif // _sysregs_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Core/Include/UsbDebugPort.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Libra= ry/BaseMemoryCoreLib/Core/Include/UsbDebugPort.h new file mode 100644 index 0000000000..172e794042 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/= Include/UsbDebugPort.h @@ -0,0 +1,318 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _USB_DEBUG_PORT_INTERNAL_H +#define _USB_DEBUG_PORT_INTERNAL_H + +#include "DataTypes.h" + +#define PCI_VENDOR_ID_OFFSET 0x00 +#define PCI_DEVICE_ID_OFFSET 0x02 +#define PCI_COMMAND_OFFSET 0x04 +#define PCI_PRIMARY_STATUS_OFFSET 0x06 +#define PCI_REVISION_ID_OFFSET 0x08 +#define PCI_CLASSCODE_OFFSET 0x09 +#define PCI_SUBCLASSCODE_OFFSET 0x0A +#define PCI_BASECLASSCODE_OFFSET 0x0B // Base Class Cod= e Register +#define PCI_CACHELINE_SIZE_OFFSET 0x0C +#define PCI_LATENCY_TIMER_OFFSET 0x0D +#define PCI_HEADER_TYPE_OFFSET 0x0E +#define PCI_BIST_OFFSET 0x0F +#define PCI_BASE_ADDRESSREG_OFFSET 0x10 +#define PCI_CARDBUS_CIS_OFFSET 0x28 +#define PCI_SVID_OFFSET 0x2C // SubSystem Vend= or id +#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C +#define PCI_SID_OFFSET 0x2E // SubSystem ID +#define PCI_SUBSYSTEM_ID_OFFSET 0x2E +#define PCI_EXPANSION_ROM_BASE 0x30 +#define PCI_CAPBILITY_POINTER_OFFSET 0x34 +#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line= Register +#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin = Register +#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Regi= ster +#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Re= gister + +#define PCI_CLASS_SERIAL 0x0C +#define PCI_CLASS_SERIAL_USB 0x03 + +#define IS_BIT_SET(Register, BitMask) (((*(volatile UINT32 *)(Register)) = & (BitMask)) !=3D 0) +#define IS_BIT_CLEAR(Register, BitMask) (((*(volatile UINT32 *)(Register)= ) & (BitMask)) =3D=3D 0) + +#define SET_R32_BIT(Register, BitMask) \ + { \ + UINT32 RegisterValue =3D *(volatile UINT32 *)(Register); \ + RegisterValue |=3D (UINT32)(BitMask); \ + *(volatile UINT32 *)(Register) =3D RegisterValue; \ + } + +#define CLR_R32_BIT(Register, BitMask) \ + { \ + UINT32 RegisterValue =3D *(volatile UINT32 *)(Register); \ + RegisterValue &=3D (UINT32)(~(BitMask)); \ + *(volatile UINT32 *)(Register) =3D RegisterValue; \ + } + +#define CLR_AND_SET_R32_BIT(Register, BitMask, Value) \ + { \ + UINT32 RegisterValue =3D *(volatile UINT32 *)(Register); \ + RegisterValue &=3D (UINT32)(~(BitMask)); \ + RegisterValue |=3D (UINT32)(Value); \ + *(volatile UINT32 *)(Register) =3D RegisterValue; \ + } + +#define SET_R16_BIT(Register, BitMask) \ + { \ + UINT16 RegisterValue =3D *(volatile UINT16 *)(Register); \ + RegisterValue |=3D (UINT16)(BitMask); \ + *(volatile UINT16 *)(Register) =3D RegisterValue; \ + } + +#define CLR_R16_BIT(Register, BitMask) \ + { \ + UINT16 RegisterValue =3D *(volatile UINT16 *)(Register); \ + RegisterValue &=3D (UINT16)(~(BitMask)); \ + *(volatile UINT16 *)(Register) =3D RegisterValue; \ + } + +#define SET_R8_BIT(Register, BitMask) \ + { \ + UINT8 RegisterValue =3D *(volatile UINT8 *)(Register); \ + RegisterValue |=3D (UINT8)(BitMask); \ + *(volatile UINT8 *)(Register) =3D RegisterValue; \ + } + +#define CLR_R8_BIT(Register, BitMask) \ + { \ + UINT8 RegisterValue =3D *(volatile UINT8 *)(Register); \ + RegisterValue &=3D (UINT8)(~(BitMask)); \ + *(volatile UINT8 *)(Register) =3D RegisterValue; \ + } + +#define PCI_CLASS_SERIAL_USB_EHCI 0x20 +#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A + +#define PCI_USB2_SBRN_OFFSET 0x60 +#define PCI_PRIMARY_BUS_NUMBER_OFFSET 0x18 +#define PCI_SECONDARY_BUS_NUMBER_OFFSET 0x19 +#define PCI_SUBORDINATE_BUS_NUMBER_OFFSET 0x1A + +#define PCI_BRIDGE_MBASE_OFFSET 0x20 +#define PCI_BRIDGE_MLIMIT_OFFSET 0x22 + +#define PCI_EHCI_DEFAULT_BUS_NUMBER 0x00 +#define PCI_EHCI_DEFAULT_DEVICE_NUMBER 0x1D +#define PCI_EHCI_DEFAULT_FUNCTION_NUMBER 0x00 +#define PCI_EHCI_DEFAULT_DEBUG_CAPID_OFFSET 0x58 +#define PCI_EHCI_DEFAULT_DEBUG_BASE_OFFSET 0x5A + +// +// USB PIDs +// +#define USB2_PID_TOKEN_OUT 0xE1 +#define USB2_PID_TOKEN_IN 0x69 +#define USB2_PID_TOKEN_SOF 0xA5 +#define USB2_PID_TOKEN_SETUP 0x2D + +#define USB2_PID_DATA0 0xC3 +#define USB2_PID_DATA1 0x4B +#define USB2_PID_DATA2 0x87 +#define USB2_PID_MDATA 0x0F + +#define USB2_PID_HANDSHAKE_ACK 0xD2 +#define USB2_PID_HANDSHAKE_NAK 0x5A +#define USB2_PID_HANDSHAKE_STALL 0x1E +#define USB2_PID_HANDSHAKE_NYET 0x96 + +#define USB2_PID_SPECIAL_PRE 0x3C +#define USB2_PID_SPECIAL_ERR 0x3C +#define USB2_PID_SPECIAL_SPLIT 0x78 +#define USB2_PID_SPECIAL_PING 0xB4 +#define USB2_PID_SPECIAL_RESERVED 0xF0 + +// +// USB2 Debug Port Register +// +#define USB2_DEBUG_PORT_STATUS_OWNER 0x40000000 +#define USB2_DEBUG_PORT_STATUS_ENABLED 0x10000000 +#define USB2_DEBUG_PORT_STATUS_DONE 0x00010000 +#define USB2_DEBUG_PORT_STATUS_INUSE 0x00000400 +#define USB2_DEBUG_PORT_STATUS_EXCEPTION 0x00000380 +#define USB2_DEBUG_PORT_STATUS_ERROR 0x00000040 +#define USB2_DEBUG_PORT_STATUS_GO 0x00000020 +#define USB2_DEBUG_PORT_STATUS_WRITE 0x00000010 +#define USB2_DEBUG_PORT_STATUS_LENGTH 0x0000000F + +#define USB2_DEBUG_PORT_DEFAULT_ADDRESS 127 + +#define USB2_DEBUG_PORT_DEVICE_BUFFER_MAX 8 + +typedef struct _USB2_DEBUG_PORT_REGISTER { + UINT32 ControlStatus; + UINT8 TokenPid; + UINT8 SendPid; + UINT8 ReceivedPid; + UINT8 Reserved1; + UINT8 DataBuffer[USB2_DEBUG_PORT_DEVICE_BUFFER_MAX]; + UINT8 UsbEndPoint; + UINT8 UsbAddress; + UINT8 Reserved2; + UINT8 Reserved3; +}USB2_DEBUG_PORT_REGISTER; + +typedef struct _USB2_EHCI_CAPABILITY_REGISTER { + UINT8 CapLength; + UINT8 Reserved; + UINT16 HciVersion; + UINT32 HcsParams; + UINT32 HccParams; + UINT32 HcspPortRoute; +}USB2_EHCI_CAPABILITY_REGISTER; + +#define USB2_EHCI_USBCMD_RUN 0x00000001 +#define USB2_EHCI_USBCMD_RESET 0x00000002 + +#define USB2_EHCI_USBSTS_HC_HALTED 0x00001000 + +#define USB2_EHCI_PORTSC_PORT_OWNER 0x00002000 +#define USB2_EHCI_PORTSC_PORT_POWER 0x00001000 +#define USB2_EHCI_PORTSC_PORT_RESET 0x00000100 +#define USB2_EHCI_PORTSC_PORT_SUSPEND 0x00000080 +#define USB2_EHCI_PORTSC_PORT_ENABLED 0x00000004 + +typedef struct _USB2_EHCI_OPERATIONAL_REGISTER { + UINT32 UsbCommand; + UINT32 UsbStatus; + UINT32 UsbInterruptEnable; + UINT32 UsbFrameIndex; + UINT32 SegmentSelector; + UINT32 FrameListBaseAddress; + UINT32 NextAsyncListAddress; + UINT32 Reserved[9]; + UINT32 ConfigFlag; + UINT32 PortSc[0x0F]; +}USB2_EHCI_OPERATIONAL_REGISTER; + +#define USB2_DEBUG_PORT_DRIVER_BUFFER_MAX USB2_DEBUG_PORT_DEVICE_BUFFE= R_MAX * 2 + +typedef struct _USB2_DEBUG_PORT_INSTANCE { + + UINT32 EhciCapRegister; + UINT32 EhciOpRegister; + UINT32 PortSc; + UINT32 DebugRegister; + + BOOLEAN Ready; + + UINT8 PciBusNumber; + UINT8 PciDeviceNumber; + UINT8 PciDeviceFunction; + + UINT8 Reserved1; + UINT8 BarIndex; + UINT16 BarOffset; + + UINT32 PortBase; + UINT8 PortNumber; + UINT8 PortAddress; + UINT8 ReadEndpoint; + UINT8 WriteEndpoint; + + UINT8 ReadEndpointDataToggle; + UINT8 WriteEndpointDataToggle; + UINT8 Reserved2[2]; + + INT32 TempDataLength; + INT32 TempDataIndex; + UINT8 TempData[USB2_DEBUG_PORT_DRIVER_BUFF= ER_MAX]; +}USB2_DEBUG_PORT_INSTANCE; + +// +// Setup Packet +// +// Data phase transfer direction +// +#define USB2_REQUEST_TYPE_HOST_TO_DEVICE 0x00 +#define USB2_REQUEST_TYPE_DEVICE_TO_HOST 0x80 + +// +// Type +// +#define USB2_REQUEST_TYPE_STANDARD 0x00 +#define USB2_REQUEST_TYPE_CLASS 0x20 +#define USB2_REQUEST_TYPE_VENDOR 0x40 + +// +// Recipient +// +#define USB2_REQUEST_TYPE_DEVICE 0x00 +#define USB2_REQUEST_TYPE_INTERFACE 0x01 +#define USB2_REQUEST_TYPE_ENDPOINT 0x02 +#define USB2_REQUEST_TYPE_OTHER 0x03 + +// +// Request +// +#define USB2_REQUEST_GET_STATUS 0x00 +#define USB2_REQUEST_CLEAR_FEATURE 0x01 +#define USB2_REQUEST_SET_FEATURE 0x03 +#define USB2_REQUEST_SET_ADDRESS 0x05 +#define USB2_REQUEST_GET_DESCRIPTOR 0x06 +#define USB2_REQUEST_SET_DESCRIPTOR 0x07 +#define USB2_REQUEST_GET_CONFIGURATION 0x08 +#define USB2_REQUEST_SET_CONFIGURATION 0x09 +#define USB2_REQUEST_GET_INTERFACE 0x0A +#define USB2_REQUEST_SET_INTERFACE 0x11 + +// +// Descriptor Types +// +#define USB2_DESCRIPTOR_TYPE_DEVICE 0x01 +#define USB2_DESCRIPTOR_TYPE_CONFIGURATION 0x02 +#define USB2_DESCRIPTOR_TYPE_STRING 0x03 +#define USB2_DESCRIPTOR_TYPE_INTERFACE 0x04 +#define USB2_DESCRIPTOR_TYPE_ENDPOINT 0x05 +#define USB2_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06 +#define USB2_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION 0x07 +#define USB2_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08 +#define USB2_DESCRIPTOR_TYPE_OTG 0x09 +#define USB2_DESCRIPTOR_TYPE_DEBUG 0x0A + +// +// Standard Feature Selectors +// +#define USB2_FEATURE_DEVICE_REMOTE_WAKEUP 0x01 +#define USB2_FEATURE_ENDPOINT_HALT 0x00 +#define USB2_FEATURE_TEST_MODE 0x02 +#define USB2_FEATURE_OTG_B_HNP_ENABLE 0x03 +#define USB2_FEATURE_OTG_A_HNP_SUPPORT 0x04 +#define USB2_FEATURE_OTG_A_ALT_HNP_SUPPORT 0x05 +#define USB2_FEATURE_DEBUG_MODE 0x06 + +typedef struct _USB2_SETUP_PACKET { + UINT8 RequestType; + UINT8 Request; + UINT8 Value[2]; + UINT16 Index; + UINT16 Length_; +}USB2_SETUP_PACKET; + +typedef struct _USB2_DEBUG_DESCRIPTOR_TYPE { + UINT8 Length_; + UINT8 DescriptorType; + UINT8 DebugInEndpoint; + UINT8 DebugOutEndpoint; +}USB2_DEBUG_DESCRIPTOR_TYPE; + +typedef struct _USB2_ENDPOINT_DESCRIPTOR_TYPE { + UINT8 Length_; + UINT8 DescriptorType; + UINT8 EndpointAddress; + UINT8 Attributes; + UINT16 MaxPacketSize; + UINT8 Interval; +}USB2_ENDPOINT_DESCRIPTOR_TYPE; + +#endif /* _USB_DEBUG_PORT_H */ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Platform/Purley/Include/MemDefaults.h b/Silicon/Intel/PurleyRefreshSilico= nPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemDefaults.h new file mode 100644 index 0000000000..df34de5a85 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platf= orm/Purley/Include/MemDefaults.h @@ -0,0 +1,17 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _mem_defaults_h +#define _mem_defaults_h + +#define MAX_PARTIAL_MIRROR 4 //Maximum number of partial mirror regi= ons that can be created + +#define PPM_AUTO 0xFF + +#define MAX_AEP_DIMM_SETUP 48 //(MAX_CH * MAX_SOCKET * MAX_AEP_CH) + +#endif // _mem_platform_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Platform/Purley/Include/MemPlatform.h b/Silicon/Intel/PurleyRefreshSilico= nPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemPlatform.h new file mode 100644 index 0000000000..2171c762c8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platf= orm/Purley/Include/MemPlatform.h @@ -0,0 +1,81 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _mem_platform_h +#define _mem_platform_h + +#include "DataTypes.h" + +#ifdef SERIAL_DBG_MSG +#define MRC_TRACE 1 +#endif + + +// +// Compatible BIOS Data Structure +// +#define BDAT_SUPPORT 0 //Memory Data Schema 4 and RMT Schema 5 of BDAT= 4.0 + +// +// QR support +// +#define QR_DIMM_SUPPORT 1 + +// +// Define to enable DIMM margin checking +// +#define MARGIN_CHECK 1 + +// +// Define to enable SODIMM module support +// +#define SODIMM_SUPPORT 1 + +// +// Define to enable ME UMA support +// +//#define ME_SUPPORT_FLAG 1 + +// +// Define to enable XMP +// +#define XMP_SUPPORT 1 + +// Define to enable DEBUG for NVMCTLR (LATE CMD CLK) +//#define DEBUG_LATECMDCLK 1 + +// Define to enable MRS Stacking +//#define MRS_STACKING 1 + +// +// Define to max ppr +// +#define MAX_PPR_ADDR_ENTRIES 20 + +// +//------------------------------------- +// DVP Platform-specific defines +//------------------------------------- +// +#ifdef DVP_PLATFORM +#endif // DVP_PLATFORM + +// +//------------------------------------- +// CRB Platform-specific defines +//------------------------------------- +// +#ifdef CRB_PLATFORM +#endif // CRB_PLATFORM + +#ifndef MAX_HA +#define MAX_HA 2 // Number of Home Agents /= IMCs +#endif + +//SKX_TODO: I have removed NonPOR elements, I will delete this line before= submit + +#endif // _mem_platform_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLi= b/Platform/Purley/Include/PlatformHost.h b/Silicon/Intel/PurleyRefreshSilic= onPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/PlatformHost.h new file mode 100644 index 0000000000..bc86d61b40 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platf= orm/Purley/Include/PlatformHost.h @@ -0,0 +1,176 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _platformhost_h +#define _platformhost_h + +// +// MAX Number of Processor supported by Intel platform +// +#include "MaxSocket.h" + +#ifndef MAX_CORE +#define MAX_CORE 28 // Maximum cores per CPU= (SKX) +#define MAX_CORE_BITMASK 0xFFFFFFF // for SKX CPU +#endif + +#ifndef MAX_KTI_PORTS +#define MAX_KTI_PORTS 3 // Max KTI ports supported +#endif + +// +// Post Package Repair +// +#define PPR_SUPPORT 1 +#define MAX_PPR_ADDR_ENTRIES 20 + +// Select one of the following platforms +//#define DVP_PLATFORM 1 // DVP +// +#define CRB_PLATFORM 1 // SRP + +#ifndef DVP_PLATFORM +#ifndef CRB_PLATFORM + +/* + MULTIPLE_PLATFORM_SUPPORT should be defined when the user KNOWS that inpu= ts + (the ones defined to zero under this flag below) are given via sysSetup = structure +*/ +#define MULTIPLE_PLATFORM_SUPPORT 1 +#endif +#endif + +#if !defined(SILENT_MODE) +#define SERIAL_DBG_MSG 1 +#endif +#define RC_BEGIN_END_DEBUG_HOOKS + +//#define HW_EMULATION 1 + +#define SOFT_SDV_FLAG BIT0 // flag to indicate running on Soft SDV +#define VP_FLAG BIT1 // flag to indicate running on VP +#define SIMICS_FLAG BIT2 // flag to indicate running on Simics +#define RTL_SIM_FLAG BIT3 // flag to indicate running on the RTL s= imulator +#define QUIET_MODE BIT16 // flag to enable minimal debug messages +#define RANDOM_TRAINING BIT17 // flag to enable random training respon= ses from Simics +#define FORCE_SETUP BIT18 // flag to force BIOS setup +#define DDR_TRAINING_EN BIT19 // flag to tell the BIOS to execute DDR = training +// +// Enumerated Platform SMBUS controllers +// + +#define PLATFORM_SMBUS_CONTROLLER_PROCESSOR 0 +#define PLATFORM_SMBUS_CONTROLLER_PCH 1 + +#ifndef TypePlatformDefault +// +// Platform types - if not defined already +// +typedef enum { + TypeNeonCityEPRP =3D 0x00, + TypeNeonCityEPECB, + TypeOpalCitySTHI, + TypePurleyLBGEPDVP, + TypeWolfPass, + TypeBuchananPass, + TypeCrescentCity, + TypeHedtEV, + TypeHedtCRB, + TypeLightningRidgeEXRP, + TypeLightningRidgeEXECB1, + TypeLightningRidgeEXECB2, + TypeLightningRidgeEXECB3, + TypeLightningRidgeEXECB4, + TypeLightningRidgeEX8S1N, + TypeLightningRidgeEX8S2N, + TypeBarkPeak, + TypeKyanite, + TypeSawtoothPass, // We need to keep the value of TypeSawtoothPass unch= anged + TypeNeonCityFPGA, + TypeOpalCityFPGA, + TypeYubaCityRP, + TypeDragonRock, + TypeBlueMountainPass, + TypeWolfPassFeatureRich, + TypeYubaCityRP48L, + TypeClx64L +} EFI_PLATFORM_TYPE; + + +#define TypePlatformUnknown 0xFF +#define TypePlatformMin TypeNeonCityEPRP +#define TypePlatformMax TypeClx64L + +#define TypePlatformDefault TypeNeonCityEPRP +#define TypePlatformOpalCityPPV 6 +#define TypePlatformOpalCityCPV 7 +#endif + + +// +// Enumerated Unique Platform Component IDs +// +#define NOT_INITIALIZED 0 +#define SPD 1 +#define DCP_ISL9072X 2 +#define DCP_AD5247 3 +#define MTS 4 //TSOD +#define RSTPLD 5 +#define NO_DEV 0xFFFF +// +// Default I/O base addresses +// +#define REG_ACPI_BASE_ADDRESS 0x40 +#define PM_ENABLE 0x44 +#define IO_REG_ACPI_TIMER 0x08 +#define REG_GPIO_BASE_ADDRESS 0x48 +#ifdef MINIBIOS_BUILD +#define ICH_PMBASE_ADDR 0x500 +#endif //MINIBIOS_BUILD + +// +//#define ICH_GPIOBASE_ADDR 0x500 +#define ICH_SMBBASE_ADDR 0x700 +#define R_PCH_SMBUS_PCICMD 0x04 +#define B_PCH_SMBUS_PCICMD_IOSE BIT0 +#define R_PCH_SMBUS_BASE 0x20 +#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 +#define R_PCH_SMBUS_HOSTC 0x40 +#define B_PCH_SMBUS_HOSTC_HST_EN BIT0 +// +#define SERIAL_DBG_COM_BASE 0x3F8 +// +// Platform SMBUS definitions +// +#define SMB_SEG0 0 +#define SMB_SEG1 1 +#define SMB_SEG2 2 +#define SMB_SEG3 3 + +// +// Major Warning codes +// +#define WARN_SETUP_INVALID 0x01 +#define WARN_MINOR_WILDCARD 0xff + +#define SMB_TIMEOUT 100000 // 100 ms +#define SMB_RETRY_LIMIT 20 // 2 sec +#define CATCHALL_TIMEOUT 100000 // 100 ms + +#define FOUR_GB_MEM 0x40 // 4GB in 64MB units +#define MAX_MEM_ADDR 0x40000 // 46-bit addressing (256M= B units) +#define HIGH_GAP 1 // High gap (256 MB units) +#define MMCFG_SIZE 256*1024*1024 // MMCFG Size (in Bytes) +#define MMIOH_SIZE 0 // MMIOH Size Granularity = per stack (1GB, (1<<(2*size))) +#define DEFAULT_COM_PORT 0x80 +// +//------------------------------------------------------------------------= ----- +// +#include "MemPlatform.h" + +#endif // _platformhost_h + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/Cpu= CsrAccessDefine.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcie= Lib/CpuCsrAccessDefine.h new file mode 100644 index 0000000000..ca98b502ed --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CpuCsrAcce= ssDefine.h @@ -0,0 +1,56 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_CSR_ACCESS_DEFINE_H_ +#define _CPU_CSR_ACCESS_DEFINE_H_ + +#include +#include +#include + +#include +#include + + +typedef enum { + BUS_CLASS =3D 0, + DEVICE_CLASS =3D 1, + FUNCTION_CLASS =3D 2 +} BDF_CLASS; + +UINT32 +GetSegmentNumber ( + IN USRA_ADDRESS *Address + ); + +UINT32 +GetBDFNumber ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + IN UINT8 BDFType + ); + +UINT32 +GetCpuCsrAddress ( + UINT8 SocId, + UINT8 BoxInst, + UINT32 Offset, + UINT8 *Size + ); + +UINT32 +GetMmcfgAddress( + PSYSHOST host + ); + +VOID +GetCpuCsrAccessVar_RC ( + PSYSHOST host, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +#endif // _CPU_CSR_ACCESS_DEFINE_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/Csr= ToPcieDxeLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieL= ib/CsrToPcieDxeLib.inf new file mode 100644 index 0000000000..c976aa60b8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPcieD= xeLib.inf @@ -0,0 +1,85 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D CsrToPcieDxeLib + FILE_GUID =3D FF3C93E7-30DE-49DE-9C02-56C2BC077561 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D CsrToPcieLib + +## {FF3C93E7-30DE-49DE-9C02-56C2BC077561} +##{ 0xff3c93e7, 0x30de, 0x49de, { 0x9c, 0x2, 0x56, 0xc2, 0xbc, 0x7, 0x75, = 0x61 } }; + + +[Sources] + CsrToPcieLib.c + ../ProcMemInit/Chip/Common/CpuPciAccessCommon.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +##########################################################################= ###### +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +##########################################################################= ###### + +[LibraryClasses] + BaseLib + UefiRuntimeServicesTableLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gEfiIioUdsProtocolGuid + +[Guids] + gEfiCpRcPkgTokenSpaceGuid + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Depex] + gEfiIioUdsProtocolGuid + +##########################################################################= ###### +# +# Protocol C Name Section - list of Protocol and Protocol Notify C Names +# that this module uses or produces. +# +##########################################################################= ###### +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr + + +[BuildOptions.Ia32] + MSFT:*_*_*_CC_FLAGS =3D /W4 /Gs999999 /GF /GL- /wd4214 /wd4334 /wd41= 42 /wd4819 /DBUILDING_FOR_IA32 /DIA32 $(DSC_GLOBAL_BUILD_OPTIONS) + GCC:*_*_*_CC_FLAGS =3D -DBUILDING_FOR_IA32 -DIA32 $(DSC_GLOBAL_BUILD= _OPTIONS) + +[BuildOptions.X64] + MSFT:*_*_X64_CC_FLAGS =3D /W2 /Gs32768 /DKTI_HW_PLATFORM /DBUILDING_FO= R_X64 /UIA32 /DRAS_FEATURES /wd4142 /wd4819 $(DSC_GLOBAL_BUILD_OPTIONS) + GCC:*_*_X64_CC_FLAGS =3D -DKTI_HW_PLATFORM -DBUILDING_FOR_X64 -UIA32 -= DRAS_FEATURES $(DSC_GLOBAL_BUILD_OPTIONS) diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/Csr= ToPcieLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/Cs= rToPcieLib.c new file mode 100644 index 0000000000..8fff1efec6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPcieL= ib.c @@ -0,0 +1,179 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CpuCsrAccessDefine.h" +#include "CpuPciAccess.h" + +CPU_CSR_ACCESS_VAR *gCpuCsrAccessVarPtr =3D NULL; +CPU_CSR_ACCESS_VAR gCpuCsrAccessVar; + + +UINT32 +GetSegmentNumber ( + IN USRA_ADDRESS *Address + ) +{ + return 0; +}; + +UINT32 +GetBDFNumber ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + IN UINT8 BDFType +// UINT8 SocId, +// UINT8 BoxType + ) +/*++ + +Routine Description: + Indetifies the bus number for given SocId & BoxType + +Arguments: + Address - A pointer of the address of the USRA Address Structure with = Csr or CsrEx type + +Returns: + PCI bus number + +--*/ +{ + UINT32 Data32 =3D0 ; + UINT8 SocId; + UINT8 BoxType; + UINT8 BoxInst; + UINT8 FuncBlk; + PSYSHOST host; + + SocId =3D (UINT8)Address->Csr.SocketId; + BoxType =3D (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.boxtype; + BoxInst =3D (UINT8)Address->Csr.InstId; + FuncBlk =3D (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.funcblk; +#ifdef IA32 + host =3D (PSYSHOST)Address->Attribute.HostPtr; +#else + host =3D (PSYSHOST)NULL; +#endif + if(BDFType =3D=3D BUS_CLASS){ + Data32 =3D GetBusNumber(host, SocId, BoxType, BoxInst, FuncBlk, CpuCsr= AccessVar); + } else if(BDFType =3D=3D DEVICE_CLASS){ + Data32 =3D GetDeviceNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAcce= ssVar); + } else { + Data32 =3D GetFunctionNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAc= cessVar); + } + return Data32; + +} + +VOID +GetBDF ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + USRA_PCIE_ADDR_TYPE *PcieAddress + ) +/*++ + +Routine Description: + Indetifies the bus number for given SocId & BoxType + +Arguments: + Address - A pointer of the address of the USRA Address Structure with = Csr or CsrEx type + +Returns: + PCI bus number + +--*/ +{ + UINT8 SocId; + UINT8 BoxType; + UINT8 BoxInst; + UINT8 FuncBlk; + PSYSHOST host; + + SocId =3D (UINT8)Address->Csr.SocketId; + BoxType =3D (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.boxtype; + BoxInst =3D (UINT8)Address->Csr.InstId; + FuncBlk =3D (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.funcblk; +#ifdef IA32 + host =3D (PSYSHOST)Address->Attribute.HostPtr; +#else + host =3D (PSYSHOST)NULL; +#endif + PcieAddress->Bus =3D GetBusNumber(host, SocId, BoxType, BoxInst, FuncB= lk, CpuCsrAccessVar); + PcieAddress->Dev =3D GetDeviceNumber(host, BoxType, BoxInst, FuncBlk, = CpuCsrAccessVar); + PcieAddress->Func =3D GetFunctionNumber(host, BoxType, BoxInst, FuncBl= k, CpuCsrAccessVar); + PcieAddress->Seg =3D SocId; // Refcode and EFI data structure differe= nce. Refcode treats this array as 1 entry per socket, and not per segment= , thus we index by SocId for now.. +} +////////////////////////////////////////////////////////////////////////// +// +// USRA Silicon Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Bo= x instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Add= ress Structure + @param[out] AlignedAddress A pointer of aligned address converted f= rom USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + CPU_CSR_ACCESS_VAR *pCpuCsrAccessVar; + USRA_ADDRESS UsraAddress; + INTN MmCfgBase; + + /***********************************************************************= ********************************** + ToDo: + For now, this implementation only covers the Bus/Dev/Fun number ge= neration for IVT and HSX CPUs. + Register offset and size information comes from the HSX style regi= ster offset passed to this function. + When the auto generation of header files using the new format is a= vailable, then we need to implement + the logic to translate the register pseudo offset into real offset. + ***********************************************************************= **********************************/ + Address->Attribute.AccessWidth =3D (UINT8) (((((CSR_OFFSET *) &Address= ->Csr.Offset)->Bits.size) & 0x06) >> 1); + +#if defined (IA32) || defined (SIM_BUILD) || defined(KTI_SW_SIMULATION) ||= defined (HEADLESS_MRC) + CpuDeadLoop(); + pCpuCsrAccessVar =3D NULL; + +#else + gCpuCsrAccessVarPtr =3D &gCpuCsrAccessVar; + GetCpuCsrAccessVar_RC ((PSYSHOST)host, &gCpuCsrAccessVar); + + pCpuCsrAccessVar =3D &gCpuCsrAccessVar; +#endif // defined + + // + // Identify the PCI Bus/Device/Function number for the access + // + USRA_ZERO_ADDRESS_TYPE(UsraAddress, AddrTypePCIE); + GetBDF(Address, pCpuCsrAccessVar, &UsraAddress.Pcie); + + UsraAddress.Pcie.Offset =3D (UINT16)((CSR_OFFSET *) &Address->Csr.Offset= )->Bits.offset; + UsraAddress.Attribute.HostPtr =3D Address->Attribute.HostPtr; + + MmCfgBase =3D GetPcieSegMmcfgBaseAddress(&UsraAddress); + *AlignedAddress =3D MmCfgBase + (UINTN)(UsraAddress.Attribute.RawData32[= 0] & 0x0fffffff); + +#if defined (IA32) || defined (SIM_BUILD) || defined(KTI_SW_SIMULATION) ||= defined (HEADLESS_MRC) + CpuDeadLoop(); +#endif + + return 0; +}; + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/Csr= ToPciePeiLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieL= ib/CsrToPciePeiLib.inf new file mode 100644 index 0000000000..ff9dfa4cbd --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPcieP= eiLib.inf @@ -0,0 +1,81 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D CsrToPciePeiLib + FILE_GUID =3D C18FB69B-D1A7-4EF0-988D-2A40FE2E96B0 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D CsrToPcieLib + +## {C18FB69B-D1A7-4EF0-988D-2A40FE2E96B0} +##{ 0xc18fb69b, 0xd1a7, 0x4ef0, { 0x98, 0x8d, 0x2a, 0x40, 0xfe, 0x2e, 0x96= , 0xb0 } }; + + +[Sources] + CsrToPcieLib.c + ../ProcMemInit/Chip/Common/CpuPciAccessCommon.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +##########################################################################= ###### +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +##########################################################################= ###### + +[LibraryClasses] + BaseLib + DebugLib + +[Protocols] + +[Guids] + gEfiCpRcPkgTokenSpaceGuid + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Depex] + + +##########################################################################= ###### +# +# Protocol C Name Section - list of Protocol and Protocol Notify C Names +# that this module uses or produces. +# +##########################################################################= ###### +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr + + +[BuildOptions.Ia32] + MSFT:*_*_*_CC_FLAGS =3D /W4 /Gs999999 /GF /GL- /wd4214 /wd4334 /wd41= 42 /wd4819 /DBUILDING_FOR_IA32 /DIA32 $(DSC_GLOBAL_BUILD_OPTIONS) + GCC:*_*_*_CC_FLAGS =3D -DBUILDING_FOR_IA32 -DIA32 $(DSC_GLOBAL_BUIL= D_OPTIONS) + +[BuildOptions.X64] + MSFT:*_*_X64_CC_FLAGS =3D /W2 /Gs32768 /DKTI_HW_PLATFORM /DBUILDING_FO= R_X64 /UIA32 /DRAS_FEATURES /wd4142 /wd4819 $(DSC_GLOBAL_BUILD_OPTIONS) + GCC:*_*_X64_CC_FLAGS =3D -DKTI_HW_PLATFORM -DBUILDING_FOR_X64 -UIA32 -= DRAS_FEATURES $(DSC_GLOBAL_BUILD_OPTIONS) diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull= /BaseCsrToPcieLibNull.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/C= srToPcieLibNull/BaseCsrToPcieLibNull.inf new file mode 100644 index 0000000000..32ea39bb1b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull/BaseCs= rToPcieLibNull.inf @@ -0,0 +1,67 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseCsrToPcieLibNull + FILE_GUID =3D 848E908E-BD11-428E-94F9-7A0EEFCD37A6 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D CsrToPcieLib + +## {848E908E-BD11-428E-94F9-7A0EEFCD37A6} +##{ 0x848e908e, 0xbd11, 0x428e, { 0x94, 0xf9, 0x7a, 0xe, 0xef, 0xcd, 0x37,= 0xa6 } }; + + +[Sources] + CsrToPcieLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + + +##########################################################################= ###### +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +##########################################################################= ###### + +[LibraryClasses] + BaseLib + PcdLib + + +[Guids] + gEfiCpRcPkgTokenSpaceGuid + +##########################################################################= ###### +# +# Protocol C Name Section - list of Protocol and Protocol Notify C Names +# that this module uses or produces. +# +##########################################################################= ###### +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull= /CsrToPcieLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLi= bNull/CsrToPcieLib.c new file mode 100644 index 0000000000..41dfb9c0c3 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull/CsrToP= cieLib.c @@ -0,0 +1,41 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +////////////////////////////////////////////////////////////////////////// +// +// USRA Csr to PCIE Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Bo= x instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Add= ress Structure + @param[out] AlignedAddress A pointer of aligned address converted f= rom USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + USRA_ADDRESS PcieAddress; + USRA_ZERO_ADDRESS_TYPE(PcieAddress, AddrTypePCIE); + return 0; +}; + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/= DxeMmPciBaseLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciB= aseLib/DxeMmPciBaseLib.c new file mode 100644 index 0000000000..faefa3661e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/DxeMmPc= iBaseLib.c @@ -0,0 +1,89 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +USRA_PROTOCOL *mPciUsra =3D NULL; + +/** + The constructor function initialize UsraProtocol. + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +DxeMmPciLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + if (mPciUsra =3D=3D NULL) + { + // + // USRA protocol need to be installed before the module access USRA. + // + Status =3D gBS->LocateProtocol (&gUsraProtocolGuid, NULL, (VOID **)&mP= ciUsra); + ASSERT_EFI_ERROR (Status); + ASSERT (mPciUsra !=3D NULL); + } + return EFI_SUCCESS; +} + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +) +{ + USRA_ADDRESS Address; + USRA_PCIE_ADDRESS(Address, UsraWidth32, Bus, Device, Function, 0); + return mPciUsra->GetRegAddr (&Address); +} + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +) +{ + USRA_ADDRESS Address; + USRA_PCIE_SEG_ADDRESS(Address, UsraWidth32, Seg, Bus, Device, Function, = Register); + return mPciUsra->GetRegAddr (&Address); +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/= DxeMmPciBaseLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPc= iBaseLib/DxeMmPciBaseLib.inf new file mode 100644 index 0000000000..2b413621c5 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/DxeMmPc= iBaseLib.inf @@ -0,0 +1,60 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D DxeSmmMmPciLib + FILE_GUID =3D 28D4B296-EFCE-46E4-8DA7-DA54D17AEDEF + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MmPciLib + CONSTRUCTOR =3D DxeMmPciLibConstructor + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# +[Sources] + DxeMmPciBaseLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +##########################################################################= ###### +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +##########################################################################= ###### + +[LibraryClasses] + BaseLib + UefiBootServicesTableLib + DxeServicesTableLib + UefiLib + IoLib + DebugLib + PcdLib + +[Protocols] + gEfiSmmCpuIo2ProtocolGuid + gUsraProtocolGuid ## CONSUMES + +[Depex] + gUsraProtocolGuid \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/= SmmMmPciBaseLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciB= aseLib/SmmMmPciBaseLib.c new file mode 100644 index 0000000000..5479d173f5 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/SmmMmPc= iBaseLib.c @@ -0,0 +1,86 @@ +/** @file + +Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +USRA_PROTOCOL *mPciUsra =3D NULL; + +/** + The constructor function initialize UsraProtocol. + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +SmmMmPciLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + if (mPciUsra =3D=3D NULL) + { + // + // USRA protocol need to be installed before the module access USRA. + // + Status =3D gSmst->SmmLocateProtocol (&gUsraProtocolGuid, NULL, (VOID *= *) &mPciUsra); + ASSERT_EFI_ERROR (Status); + ASSERT (mPciUsra !=3D NULL); + } + return EFI_SUCCESS; +} + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +) +{ + USRA_ADDRESS Address; + USRA_PCIE_ADDRESS(Address, UsraWidth32, Bus, Device, Function, 0); + return mPciUsra->GetRegAddr (&Address); +} + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +) +{ + USRA_ADDRESS Address; + USRA_PCIE_SEG_ADDRESS(Address, UsraWidth32, Seg, Bus, Device, Function, = Register); + return mPciUsra->GetRegAddr (&Address); +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/= SmmMmPciBaseLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPc= iBaseLib/SmmMmPciBaseLib.inf new file mode 100644 index 0000000000..069b5310b8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/SmmMmPc= iBaseLib.inf @@ -0,0 +1,60 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D DxeSmmMmPciLib + FILE_GUID =3D 96D31DB6-CCFC-4B80-B850-FC070806CA78 + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MmPciLib|DXE_SMM_DRIVER + CONSTRUCTOR =3D SmmMmPciLibConstructor + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# +[Sources] + SmmMmPciBaseLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +##########################################################################= ###### +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +##########################################################################= ###### + +[LibraryClasses] + BaseLib + UefiBootServicesTableLib + IoLib + DebugLib + UefiLib + SmmServicesTableLib + +[Protocols] + gEfiSmmCpuIo2ProtocolGuid + gUsraProtocolGuid ## CONSUMES + +[Depex.common.DXE_SMM_DRIVER] + gEfiSmmCpuIo2ProtocolGuid + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmP= ciBaseLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/Mm= PciBaseLib.c new file mode 100644 index 0000000000..c42c4503df --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmPciBaseL= ib.c @@ -0,0 +1,69 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +) +{ + USRA_ADDRESS Address; + USRA_PCIE_ADDRESS(Address, UsraWidth32, Bus, Device, Function, 0); + + if (!FeaturePcdGet (PcdSingleSegFixMmcfg)) + { + return GetRegisterAddress(&Address); + } + // + // If the PcdSingleSegFixMmcfg is true, do the following with static Pcd= PciExpressBaseAddress + // + return ((UINTN) (PcdGet64(PcdPciExpressBaseAddress)) + (UINTN) (Address.= Attribute.RawData32[0] & 0x00ffffff)); +} + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +) +{ + USRA_ADDRESS Address; + USRA_PCIE_SEG_ADDRESS(Address, UsraWidth32, Seg, Bus, Device, Function, = Register); + + if (!FeaturePcdGet(PcdSingleSegFixMmcfg)) + { + return GetRegisterAddress(&Address); + } + // + // If the PcdSingleSegFixMmcfg is true, do the following with static Pcd= PciExpressBaseAddress + // + return ((UINTN)(PcdGet64(PcdPciExpressBaseAddress)) + (UINTN)(Address.At= tribute.RawData32[0] & 0x00ffffff)); +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmP= ciBaseLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/= MmPciBaseLib.inf new file mode 100644 index 0000000000..ae6da88168 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmPciBaseL= ib.inf @@ -0,0 +1,55 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiDxeSmmMmPciLib + FILE_GUID =3D AA112999-A913-4F96-A9C4-28BFA0BD83EE + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MmPciLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# +[Sources] + MmPciBaseLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + + [Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +##########################################################################= ###### +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +##########################################################################= ###### + +[LibraryClasses] + BaseLib + IoLib + DebugLib + SiliconAccessLib + +[Guids] + gEfiCpRcPkgTokenSpaceGuid + +[Pcd] + gEfiCpRcPkgTokenSpaceGuid.PcdSingleSegFixMmcfg + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/P= cieAddressLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddress= Lib/PcieAddressLib.c new file mode 100644 index 0000000000..c893b9b498 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/PcieAddr= essLib.c @@ -0,0 +1,305 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "PcieAddress.h" + +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SI= M_BUILD) +#include +#endif + +#ifdef _MSC_VER +#pragma optimize ("",off) +#endif //_MSC_VER +////////////////////////////////////////////////////////////////////////// +// +// Common Silicon Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +PCIE_MMCFG_TABLE_TYPE mMmcfgTable =3D\ + { + { + {'M', 'C', 'F', 'G'}, // Signature + 0x00000090, // Length + 0x01, // Revision + 0x08, // The Maximum number of Segments + 0x00FF, // Valid Segment Bit Map, LSB Bit0 for Seg0,= bit1 for seg1 ... + {0x00,0x00,0x00,0x00} // Reserved + }, + {{ + 0, //MMCFG_BASE_ADDRESS, // Base Address Low + 0x00000000, // Base Address High + 0x0000, // Segment 0 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }} +}; +// +// Segment 1 ~ 7 +// +PCIE_MMCFG_BASE_ADDRESS_TYPE mMmcfgAddr[] =3D \ +{ + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0001, // Segment 1 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0002, // Segment 2 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0003, // Segment 3 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0004, // Segment 4 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0005, // Segment 5 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0006, // Segment 6 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0007, // Segment 7 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + } +}; + + +/** + This Lib is used for platfor to set platform specific Pcie MMCFG Table + + @param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCF= G_TABLE_TYPE type. + @param NumOfSeg: Sumber of Segments in the table. + + @retval <>NULL The function completed successfully. + @retval NULL Returen Error +**/ +UINTN +SetSocketMmcfgTable ( + IN UINT8 SocketLastBus[], + IN UINT8 SocketFirstBus[], + IN UINT8 segmentSocket[], + IN UINT32 mmCfgBaseH[], + IN UINT32 mmCfgBaseL[], + IN UINT8 NumOfSocket + ) +{ +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SI= M_BUILD) + UINT32 MmcfgTableSize; + PCIE_MMCFG_TABLE_TYPE *HobMmcfgTable; + UINT8 i, *Dest, *Source; + + union { + UINT64 D64; + UINT32 D32[2]; + } Data; + + MmcfgTableSize =3D sizeof(PCIE_MMCFG_HEADER_TYPE) + (NumOfSocket * sizeo= f(PCIE_MMCFG_BASE_ADDRESS_TYPE)); + + HobMmcfgTable =3D (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTable= Ptr); + ASSERT (MmcfgTableSize < PcdGetSize (PcdPcieMmcfgTablePtr)); + + Data.D64 =3D PcdGet64 (PcdPciExpressBaseAddress); + mMmcfgTable.MmcfgBase[0].BaseAddressL =3D Data.D32[0]; + mMmcfgTable.MmcfgBase[0].BaseAddressH =3D Data.D32[1]; + + //1. copy global variable mMcfgTable to HobMmcfgTable + // note that mMmcfgTable only has PCIE_MMCFG_BASE_ADDRESS_TYPE for seg= ment 0 (for socket 0) + // need to copy base addresses for other segments corresponding to soc= kets 1 through NumOfSocket-1 + Dest =3D (UINT8*)HobMmcfgTable; + Source =3D (UINT8*)&mMmcfgTable; + for(i=3D0; i 1){ + Dest =3D (UINT8*)&HobMmcfgTable->MmcfgBase[1]; + Source =3D (UINT8*)&mMmcfgAddr[0];//array of base addresses starting w= ith segment 1 (max segment =3D 7) + for(i =3D 0; i< (MmcfgTableSize - sizeof(PCIE_MMCFG_TABLE_TYPE)); i++){ + Dest[i] =3D Source[i]; + } + } + + HobMmcfgTable->Header.Length =3D MmcfgTableSize; + for(i=3D0; iMmcfgBase[i].StartBus =3D SocketFirstBus[i]; + HobMmcfgTable->MmcfgBase[i].EndBus =3D SocketLastBus[i]; + HobMmcfgTable->MmcfgBase[i].Segment =3D segmentSocket[i]; + HobMmcfgTable->MmcfgBase[i].BaseAddressH =3D mmCfgBaseH[i]; + HobMmcfgTable->MmcfgBase[i].BaseAddressL =3D mmCfgBaseL[i]; + } +#endif + return 0; +}; + + +/** + This Lib is used for platform to set platform specific Pcie MMCFG Table + + @param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCF= G_TABLE_TYPE type. + @param NumOfSeg: Sumber of Segments in the table. + + @retval <>NULL The function completed successfully. + @retval NULL Returen Error +**/ +UINTN +EFIAPI +SetPcieSegMmcfgTable ( + IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable, + IN UINT32 NumOfSeg + ) +{ +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SI= M_BUILD) + UINT32 MmcfgTableSize; + PCIE_MMCFG_TABLE_TYPE *HobMmcfgTable; + + union { + UINT64 D64; + UINT32 D32[2]; + } Data; + + Data.D32[0] =3D Data.D32[1] =3D 0; + MmcfgTableSize =3D sizeof(PCIE_MMCFG_HEADER_TYPE) + (NumOfSeg * sizeof(P= CIE_MMCFG_BASE_ADDRESS_TYPE)); + + HobMmcfgTable =3D (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTable= Ptr); + //ASSERT (MmcfgTableSize < PcdGetSize (PcdPcieMmcfgTablePtr)); + + //InternalMemCopyMem(HobMmcfgTable, MmcfgTable, PcdGetSize (PcdPcieMmcfg= TablePtr)); + MmcfgTable->Header.Length =3D MmcfgTableSize; + if((MmcfgTable->MmcfgBase[0].BaseAddressL =3D=3D 0) && (MmcfgTable->Mmcf= gBase[0].BaseAddressH =3D=3D 0)) + { + // + // The first time default should be the PcdPciExpressBaseAddress + // + Data.D64 =3D (UINTN) PcdGet64 (PcdPciExpressBaseAddress); + HobMmcfgTable->MmcfgBase[0].BaseAddressL =3D Data.D32[0]; + HobMmcfgTable->MmcfgBase[0].BaseAddressH =3D Data.D32[1]; + }; +#endif + return 0; +}; + + +/** + This Lib return PCIE MMCFG Base Address + + @param Address: A pointer of the address of the Common Address Structur= e for PCIE type. + @param Buffer: A pointer of buffer for the value read from platform. + + @retval <>NULL The function completed successfully. + @retval NULL Returen Error + **/ + +UINTN +EFIAPI +GetPcieSegMmcfgBaseAddress ( + IN USRA_ADDRESS *Address + ) +{ + UINT32 BaseAddressL=3D0; // Processor-relat= ive Base Address (Lower 32-bit) for the Enhanced Configuration Access Mecha= nism + UINT32 BaseAddressH=3D0; + UINTN SegMmcfgBase; + +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) + PCIE_MMCFG_TABLE_TYPE *MmcfgTable=3DNULL; + union { + UINTN D64; + UINT32 D32[2]; + } Data; +#endif +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) + if(Address->Attribute.HostPtr =3D=3D 0) { + MmcfgTable =3D (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTableP= tr); + if(MmcfgTable->Header.Length !=3D 0) + { + BaseAddressH =3D MmcfgTable->MmcfgBase[Address->Pcie.Seg].BaseAddres= sH; + BaseAddressL =3D MmcfgTable->MmcfgBase[Address->Pcie.Seg].BaseAddres= sL; + } else { + // + // if it is not valid MMCFG pointer, initialize it to use the predef= ined default MMCFG Table + // + SetPcieSegMmcfgTable(&mMmcfgTable, PcdGet32 (PcdNumOfPcieSeg)); + BaseAddressH =3D mMmcfgTable.MmcfgBase[Address->Pcie.Seg].BaseAddres= sH; + BaseAddressL =3D mMmcfgTable.MmcfgBase[Address->Pcie.Seg].BaseAddres= sL; + + if((BaseAddressL =3D=3D 0) && (BaseAddressH =3D=3D 0)){ + Data.D32[0] =3D Data.D32[1] =3D 0; + Data.D64 =3D (UINTN) PcdGet64 (PcdPciExpressBaseAddress); + BaseAddressL =3D Data.D32[0]; + BaseAddressH =3D Data.D32[1]; + } + } + } + else +#endif + { + BaseAddressH =3D 0; + BaseAddressL =3D 0; + } + + if((BaseAddressL =3D=3D 0) && (BaseAddressH =3D=3D 0)) + { + +#if defined(MINIBIOS_BUILD) || defined(KTI_SW_SIMULATION) + BaseAddressL =3D 0x80000000; + BaseAddressH =3D 0; +#else + // + // The first time default should be the PcdPciExpressBaseAddress + // + Data.D32[0] =3D Data.D32[1] =3D 0; + Data.D64 =3D (UINTN) PcdGet64 (PcdPciExpressBaseAddress); + BaseAddressL =3D Data.D32[0]; + BaseAddressH =3D Data.D32[1]; +#endif + } + return SegMmcfgBase =3D BaseAddressL; + +}; + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/P= cieAddressLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddre= ssLib/PcieAddressLib.inf new file mode 100644 index 0000000000..dad4871979 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/PcieAddr= essLib.inf @@ -0,0 +1,70 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PcieAddrLib + FILE_GUID =3D 629E0F0C-073A-475F-BF23-1F39A5D6D1C7 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PcieAddrLib + +## {629E0F0C-073A-475F-BF23-1F39A5D6D1C7} +##{ 0x629e0f0c, 0x73a, 0x475f, { 0xbf, 0x23, 0x1f, 0x39, 0xa5, 0xd6, 0xd1,= 0xc7 } }; + + +[Sources] + PcieAddressLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +##########################################################################= ###### +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +##########################################################################= ###### + +[LibraryClasses] + BaseLib + PcdLib + BaseMemoryLib + + +[Guids] + gEfiCpRcPkgTokenSpaceGuid + +##########################################################################= ###### +# +# Protocol C Name Section - list of Protocol and Protocol Notify C Names +# that this module uses or produces. +# +##########################################################################= ###### +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr + gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip= /Common/CpuPciAccessCommon.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Librar= y/ProcMemInit/Chip/Common/CpuPciAccessCommon.c new file mode 100644 index 0000000000..292dbec37b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Common= /CpuPciAccessCommon.c @@ -0,0 +1,812 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include "CpuPciAccess.h" + +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SI= M_BUILD) +#include +#endif + + + + +#ifndef IA32 + +#include "Library/IoLib.h" +#include +#include + + +static EFI_IIO_UDS_PROTOCOL *mIioUds; +IIO_UDS *mIioUdsDataPtr; +CPU_CSR_ACCESS_VAR *PCpuCsrAccessVarGlobal =3D NULL; +#endif +#ifndef IA32 +CPU_CSR_ACCESS_VAR CpuCsrAccessVarGlobal; +#endif + +// +// Disable warning for unsued input parameters +// +#ifdef _MSC_VER +#pragma warning(disable : 4100) +#pragma warning(disable : 4013) +#pragma warning(disable : 4306) +#endif + +// +// PCI function translation table; note that this table doesn't capture th= e function +// information for all instances of a box. It only captures for the first = instance. +// It has to be translated for other instances after the look up is done. +// +STATIC UINT8 FunTbl[MAX_CPU_TYPES][MAX_BOX_TYPES][8] =3D { + { + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA MISC = 0 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA PMA = 1 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA CMS = 2 + {0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // CHABC = 3 + {0, 1, 2, 3, 4, 5, 6, 7 }, // PCU = 4 + {0, 1, 2, 3, 4, 5, 6, 7 }, // VCU = 5 + {0, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // M2MEM = 6 + {0, 4, 0, 0, 4, 0, 0xFF, 0xFF}, // MC = 7 //SKX:Should be {0, 1, 4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF} + {0, 2, 4, 0, 2, 4, 0xFF, 0xFF}, // MCIO DDRIO = 8 //SKX:should be {0, 1, 6, 7, 0xFF, 0xFF, 0xFF, 0xFF} + {0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // KTI = 9 + {0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // M3KTI = 10 + {2, 6, 2, 2, 6, 2, 0xFF, 0xFF}, // MCDDC = 11 //SKX:SHould be {2, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // = MCDDC These entries all seem wrong but work + {0, 1, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // M2UPCIE = 12 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO DMI = 13 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO PCIE = 14 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO PCIENTB = 15 + {0, 1, 2, 3, 4, 5, 6, 7 }, // IIOCB = 16 + {0, 1, 2, 4, 5, 6, 0xFF, 0xFF}, // IIO VTD = 17 + {0, 0, 7, 7, 4, 4, 0xFF, 0xFF}, // IIO_RTO = 18 + {0, 1, 2, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // UBOX = 19 + }, // SKX +}; + +STATIC UINT8 m2pcieDevTable[MAX_SKX_M2PCIE] =3D { 22, 21, 22, 23, 21}; + +/** + + Populate CpuCsrAccessVar structure. + + @param host - pointer to the system host root structure + @param CpuCsrAccessVar - pointer to CpuCsrAccessVar structure to be po= pulated + + @retval None + +**/ +VOID +GetCpuCsrAccessVar_RC ( + PSYSHOST host, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ +#ifndef IA32 + EFI_STATUS Status; +#endif + + if (host !=3D NULL) { + CpuDeadLoop (); + } + +#ifndef IA32 + if (host =3D=3D NULL) { + if(PCpuCsrAccessVarGlobal =3D=3D NULL){ //check if 1st time, if ye= s, then need to update + // Locate the IIO Protocol Interface + Status =3D gBS->LocateProtocol (&gEfiIioUdsProtocolGuid, NULL, &mIio= Uds); + mIioUdsDataPtr =3D (IIO_UDS *)mIioUds->IioUdsPtr; + //ASSERT_EFI_ERROR (Status); + + PCpuCsrAccessVarGlobal =3D &CpuCsrAccessVarGlobal; + for (socket =3D 0; socket < MAX_SOCKET; socket++) { + CpuCsrAccessVarGlobal.stackPresentBitmap[socket] =3D mIioUdsDataPt= r->PlatformData.CpuQpiInfo[socket].stackPresentBitmap; + CpuCsrAccessVarGlobal.SocketFirstBus[socket] =3D mIioUdsDataPtr->P= latformData.CpuQpiInfo[socket].SocketFirstBus; + CpuCsrAccessVarGlobal.SocketLastBus[socket] =3D mIioUdsDataPtr->Pl= atformData.CpuQpiInfo[socket].SocketLastBus; + CpuCsrAccessVarGlobal.segmentSocket[socket] =3D mIioUdsDataPtr->Pl= atformData.CpuQpiInfo[socket].segmentSocket; + + for (ctr =3D 0; ctr < MAX_IIO_STACK; ctr++) { + CpuCsrAccessVarGlobal.StackBus[socket][ctr] =3D mIioUdsDataPtr->= PlatformData.CpuQpiInfo[socket].StackBus[ctr]; + } + } + + CpuCsrAccessVarGlobal.cpuType =3D mIioUdsDataPtr->SystemStatus.cpuTy= pe; + CpuCsrAccessVarGlobal.stepping =3D mIioUdsDataPtr->SystemStatus.Mini= mumCpuStepping; + CpuCsrAccessVarGlobal.socketPresentBitMap =3D mIioUdsDataPtr->System= Status.socketPresentBitMap; + CpuCsrAccessVarGlobal.FpgaPresentBitMap =3D mIioUdsDataPtr->SystemSt= atus.FpgaPresentBitMap; + CpuCsrAccessVarGlobal.mmCfgBase =3D (UINT32)mIioUdsDataPtr->Platform= Data.PciExpressBase; + CpuCsrAccessVarGlobal.numChPerMC =3D mIioUdsDataPtr->SystemStatus.nu= mChPerMC; + CpuCsrAccessVarGlobal.maxCh =3D mIioUdsDataPtr->SystemStatus.maxCh; + CpuCsrAccessVarGlobal.maxIMC =3D mIioUdsDataPtr->SystemStatus.maxIMC; + } + + if ((PCpuCsrAccessVarGlobal !=3D NULL) && (CpuCsrAccessVarGlobal.socke= tPresentBitMap !=3D mIioUdsDataPtr->SystemStatus.socketPresentBitMap)) { + for (socket =3D 0; socket < MAX_SOCKET; socket++) { + CpuCsrAccessVarGlobal.stackPresentBitmap[socket] =3D mIioUdsDataPt= r->PlatformData.CpuQpiInfo[socket].stackPresentBitmap; + CpuCsrAccessVarGlobal.SocketFirstBus[socket] =3D mIioUdsDataPtr->P= latformData.CpuQpiInfo[socket].SocketFirstBus; + CpuCsrAccessVarGlobal.SocketLastBus[socket] =3D mIioUdsDataPtr->Pl= atformData.CpuQpiInfo[socket].SocketLastBus; + CpuCsrAccessVarGlobal.segmentSocket[socket] =3D mIioUdsDataPtr->Pl= atformData.CpuQpiInfo[socket].segmentSocket; + + for (ctr =3D 0; ctr < MAX_IIO_STACK; ctr++) { + CpuCsrAccessVarGlobal.StackBus[socket][ctr] =3D mIioUdsDataPtr->= PlatformData.CpuQpiInfo[socket].StackBus[ctr]; + } + } + + CpuCsrAccessVarGlobal.cpuType =3D mIioUdsDataPtr->SystemStatus.cpuTy= pe; + CpuCsrAccessVarGlobal.stepping =3D mIioUdsDataPtr->SystemStatus.Mini= mumCpuStepping; + CpuCsrAccessVarGlobal.socketPresentBitMap =3D mIioUdsDataPtr->System= Status.socketPresentBitMap; + CpuCsrAccessVarGlobal.FpgaPresentBitMap =3D mIioUdsDataPtr->SystemSt= atus.FpgaPresentBitMap; + CpuCsrAccessVarGlobal.mmCfgBase =3D (UINT32)mIioUdsDataPtr->Platform= Data.PciExpressBase; + CpuCsrAccessVarGlobal.numChPerMC =3D mIioUdsDataPtr->SystemStatus.nu= mChPerMC; + CpuCsrAccessVarGlobal.maxCh =3D mIioUdsDataPtr->SystemStatus.maxCh; + CpuCsrAccessVarGlobal.maxIMC =3D mIioUdsDataPtr->SystemStatus.maxIMC; + } + + for (socket =3D 0; socket < MAX_SOCKET; socket++) { + CpuCsrAccessVar->stackPresentBitmap[socket] =3D CpuCsrAccessVarGloba= l.stackPresentBitmap[socket]; + + + CopyMem (&CpuCsrAccessVar->StackBus[socket], &CpuCsrAccessVarGlobal.= StackBus[socket], MAX_IIO_STACK); + } + CpuCsrAccessVar->cpuType =3D CpuCsrAccessVarGlobal.cpuType; + //CpuCsrAccessVar->stepping =3D CpuCsrAccessVarGlobal.stepping; + CpuCsrAccessVar->socketPresentBitMap =3D CpuCsrAccessVarGlobal.socketP= resentBitMap; + CpuCsrAccessVar->FpgaPresentBitMap =3D CpuCsrAccessVarGlobal.FpgaPrese= ntBitMap; + //CpuCsrAccessVar->mmCfgBase =3D CpuCsrAccessVarGlobal.mmCfgBase; + CpuCsrAccessVar->numChPerMC =3D CpuCsrAccessVarGlobal.numChPerMC; + CpuCsrAccessVar->maxCh =3D CpuCsrAccessVarGlobal.maxCh; + //CpuCsrAccessVar->maxIMC =3D CpuCsrAccessVarGlobal.maxIMC; + } +#endif +} + +/** + + Stall execution after internal assertion fails + + @param haltOnError - 1 stalls in infinite loop; 0 returns to caller + + @retval None + +**/ +VOID RcDeadLoop ( + UINT8 haltOnError + ) +{ + // + // Prevent from optimizing out + // + while (*(volatile UINT8 *) &haltOnError); +} + +/** + + CsrAccess specific print to serial output + + @param host - Pointer to the system host (root) structure + @param Format - string format + + @retval N/A + +**/ +VOID +CpuCsrAccessError ( + PSYSHOST host, + char* Format, + ... + ) +{ + UINT8 haltOnError; +#ifdef SERIAL_DBG_MSG +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SI= M_BUILD) + UINT32 *pData32; +#endif + va_list Marker; + va_start (Marker, Format); +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SI= M_BUILD) + if (host !=3D NULL) { + pData32 =3D (UINT32 *)Marker; + if( (*pData32 & 0xFFFFFF00) =3D=3D 0xFFFFFF00){ // check if input= is one byte only + *pData32 =3D *pData32 & 0x000000FF; + } if( (*pData32 & 0xFFFF0000) =3D=3D 0xFFFF0000){ // check if input= is word only + *pData32 =3D *pData32 & 0x0000FFFF; + } + DEBUG (( + DEBUG_ERROR, Format, *pData32 + )); + } +#else + if (host !=3D NULL) { + rcVprintf (host, Format, Marker); + } +#endif + va_end (Marker); +#endif + haltOnError =3D 1; + RcDeadLoop (haltOnError); + + return; +} + +/** + + Returns the CPU Index for MC func tbl lookup based on CPU type and CPU s= ub type. + This index will be used for MC box instance -> function mapping look-up + + @param host - Pointer to the system host (root) structure + + @retval Index for CPU type + +**/ +STATIC +UINT8 +GetCpuIndex ( + PSYSHOST host + ) +{ + UINT8 cpuIndex =3D 0xFF; + + cpuIndex =3D 0; + return cpuIndex; +} + +/** + + Indetifies the bus number for given SocId & BoxType + + @param host - Pointer to the system host (root) structure + @param SocId - CPU Socket Node number (Socket ID) + @param BoxType - Box Type; values come from CpuPciAccess.h + + @retval PCI bus number + +**/ +UINT32 +GetBusNumber ( + PSYSHOST host, + UINT8 SocId, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ + UINT32 Bus =3D 0; + UINT8 TempStack =3D 0; + + + + // Make sure SocId or Fpga is valid + if ((!((CpuCsrAccessVar->socketPresentBitMap & (1 << SocId)) && (BoxType= !=3D BOX_FPGA)))) { + if ((!((CpuCsrAccessVar->FpgaPresentBitMap & (1 << SocId)) && (BoxType= =3D=3D BOX_FPGA)))) { + CpuCsrAccessError (host, "\nInvalid Socket Id %d. \n", SocId); + } + } + + // + // Each socket is assigned multiple buses + // Check the box type and return the appropriate bus number. + // + if ((BoxType =3D=3D BOX_MC) || + (BoxType =3D=3D BOX_MCDDC) || + (BoxType =3D=3D BOX_MCIO) || + (BoxType =3D=3D BOX_M2MEM)) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK1]; + + } else if (BoxType =3D=3D BOX_UBOX) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else if ((BoxType =3D=3D BOX_IIO_PCIE_DMI) || + (BoxType =3D=3D BOX_IIO_CB)) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else if (BoxType =3D=3D BOX_IIO_PCIE) { + // + // IIO_PCIE is used to access all pcie ports in all stacks + // + if (BoxInst =3D=3D 0) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else { + TempStack =3D IIO_PSTACK0 + ((BoxInst-1) / 4); + if (TempStack < MAX_IIO_STACK) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid IIO_PCIE BoxInstance %d. \n", = BoxInst); + } + } + } else if (BoxType =3D=3D BOX_IIO_VTD) { + TempStack =3D IIO_CSTACK + BoxInst; + if (TempStack < MAX_IIO_STACK) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid BOX_IIO_VTD BoxInstance %d. \n",= BoxInst); + } + } else if (BoxType =3D=3D BOX_IIO_PCIE_NTB) { + if (BoxInst > 0) { + TempStack =3D IIO_PSTACK0 + ((BoxInst-1) / 4); + if (TempStack < MAX_IIO_STACK) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid BOX_IIO_PCIE_NTB BoxInstance %= d. \n", BoxInst); + } + } else { + CpuCsrAccessError (host, "\nInvalid BOX_IIO_PCIE_NTB BoxInstance %d.= \n", BoxInst); + } + } else if (BoxType =3D=3D BOX_IIO_RTO) { + if (FuncBlk =3D=3D IIO_RTO) { + // + // IIO_RTO is used to access all pcie ports in all stacks same as ii= o_pcie + // + if (BoxInst =3D=3D 0) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else { + TempStack =3D IIO_PSTACK0 + ((BoxInst-1) / 4); + if (TempStack < MAX_IIO_STACK) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid IIO_PCIE BoxInstance %d. \n"= , BoxInst); + } + } + } else if ((FuncBlk =3D=3D IIO_RTO_GLOBAL) || (FuncBlk =3D=3D IIO_RTO_= VTD)) { + // + // IIO_RTO_GLOBAL and IIO_RTO_VTD maps 1 instance per c/p/m stack + // + if ((IIO_CSTACK + BoxInst) < MAX_IIO_STACK) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK + BoxInst]; + } + } else if ((FuncBlk =3D=3D IIO_RTO_VTD_DMI) || + (FuncBlk =3D=3D IIO_RTO_DMI) || + (FuncBlk =3D=3D IIO_RTO_GLOBAL_DMI)) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else { + CpuCsrAccessError (host, "\nInvalid BoxType %d, Functional block %d.= \n", BoxType, FuncBlk); + } + } else if ((BoxType =3D=3D BOX_CHA_MISC) || + (BoxType =3D=3D BOX_CHA_PMA) || + (BoxType =3D=3D BOX_CHA_CMS) || + (BoxType =3D=3D BOX_CHABC) || + (BoxType =3D=3D BOX_PCU) || + (BoxType =3D=3D BOX_VCU)) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK0]; + } else if ((BoxType =3D=3D BOX_M2UPCIE) || + (BoxType =3D=3D BOX_KTI) || + (BoxType =3D=3D BOX_M3KTI)) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK2]; + } else if (BoxType =3D=3D BOX_FPGA) { + Bus =3D CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + + } else { + // Error + CpuCsrAccessError (host, "\nInvalid BoxType %d. \n", BoxType); + } + + return Bus; +} + +/** + + Indetifies the device number for given Box Type & Box Instance + + @param host - Pointer to the system host (root) structure + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - Box Instance, 0 based + @param FuncBlk - Functional Block; values come from CpuPciAccess.h + + @retval PCI Device number + +**/ +UINT32 +GetDeviceNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ + UINT32 Dev =3D 0; + UINT8 CpuType, NumChPerMC; + + CpuType =3D CpuCsrAccessVar->cpuType; + NumChPerMC =3D CpuCsrAccessVar->numChPerMC; + + + // + // Translate the Box Type & Instance into PCI Device number. + // + switch (BoxType) { + case BOX_MC: + case BOX_MCDDC: + if (CpuType =3D=3D CPU_SKX) { + switch (BoxInst) { + case 0: + case 1: + Dev =3D 10; + break; + case 2: + Dev =3D 11; + break; + case 3: + case 4: + Dev =3D 12; + break; + case 5: + Dev =3D 13; + break; + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_MCIO: + if (CpuType =3D=3D CPU_SKX) { + Dev =3D 22 + (BoxInst / NumChPerMC); + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_M2MEM: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst < MAX_SKX_M2MEM)) { + Dev =3D 8 + BoxInst; + } else { + CpuCsrAccessError (host, "\nInvalid M2MEM Box Instance Number %d. \n= ", BoxInst); + } + break; + + case BOX_CHA_MISC: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + if (BoxInst < 8) { + Dev =3D 8; + } else if (BoxInst < 16) { + Dev =3D 9; + } else if (BoxInst < 24) { + Dev =3D 10; + } else if (BoxInst < 28) { + Dev =3D 11; + } + } else { + CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n",= BoxInst); + } + break; + + case BOX_CHA_PMA: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + if (BoxInst < 8) { + Dev =3D 14; + } else if (BoxInst < 16) { + Dev =3D 15; + } else if (BoxInst < 24) { + Dev =3D 16; + } else if (BoxInst < 28) { + Dev =3D 17; + } + } else { + CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n",= BoxInst); + } + break; + + case BOX_CHA_CMS: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + if (BoxInst < 8) { + Dev =3D 20; + } else if (BoxInst < 16) { + Dev =3D 21; + } else if (BoxInst < 24) { + Dev =3D 22; + } else if (BoxInst < 28) { + Dev =3D 23; + } + } else { + CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n",= BoxInst); + } + break; + + case BOX_CHABC: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst =3D=3D 0)) { + Dev =3D 29; + } else { + CpuCsrAccessError (host, "\nInvalid CHABC Box Instance Number %d. \n= ", BoxInst); + } + break; + + case BOX_PCU: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst < MAX_ALL_PCU)) { + Dev =3D 30; + } else { + CpuCsrAccessError (host, "\nInvalid PCU Box Instance Number %d. \n",= BoxInst); + } + break; + + case BOX_VCU: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst < MAX_ALL_VCU)) { + Dev =3D 31; + } else { + CpuCsrAccessError (host, "\nInvalid VCU Box Instance Number %d. \n",= BoxInst); + } + break; + + case BOX_KTI: + /* + Dev # KTI(phy,logic)# + 14 0 0 + 15 1 1 + 16 2 2 + */ + if (CpuType =3D=3D CPU_SKX) { + if (BoxInst < MAX_SKX_KTIAGENT ) { + Dev =3D 14 + BoxInst; + } else { + CpuCsrAccessError (host, "\nInvalid KTI Box Instance Number %d. \n= ", BoxInst); + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_M3KTI: + /* + Logical M3KTI # Dev # Fun # + KTI01 0 18 0 + KTI23 1 18 4 + */ + + if (CpuType =3D=3D CPU_SKX) { + if (BoxInst < 2 ) { + Dev =3D 18; + } else { + CpuCsrAccessError (host, "\nInvalid Box instance.\n"); + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_M2UPCIE: + if (CpuType =3D=3D CPU_SKX) { + if (BoxInst < MAX_SKX_M2PCIE) { + Dev =3D m2pcieDevTable[BoxInst]; + } else { + CpuCsrAccessError (host, "\nInvalid KTI Box Instance Number %d. \n= ", BoxInst); + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_IIO_PCIE_DMI: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst < MAX_ALL_IIO)) { + Dev =3D 0; + } else { + CpuCsrAccessError (host, "\nInvalid IIO PCIE DMI Box Instance Number= %d. \n", BoxInst); + } + break; + + case BOX_IIO_PCIE: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst < MAX_ALL_IIO_PCIE)) { + if (BoxInst =3D=3D 0) { + // Cstack + Dev =3D 0; + } else { + // M/Pstacks + Dev =3D 0 + ((BoxInst-1) % 4); + } + } else { + CpuCsrAccessError (host, "\nInvalid IIO PCIE Box Instance Number %d.= \n", BoxInst); + } + break; + + case BOX_IIO_PCIE_NTB: + if ((CpuType =3D=3D CPU_SKX)) { + Dev =3D 0; + } else { + CpuCsrAccessError (host, "\nInvalid IIO PCIE Box Instance Number %d.= \n", BoxInst); + } + break; + + case BOX_IIO_CB: + if ((CpuType =3D=3D CPU_SKX)) { + Dev =3D 4; + } else { + CpuCsrAccessError (host, "\nInvalid IIO CB Box Instance Number %d. \= n", BoxInst); + } + break; + + case BOX_IIO_VTD: + if ((CpuType =3D=3D CPU_SKX)) { + Dev =3D 5; + } else { + CpuCsrAccessError (host, "\nInvalid IIO VTD Box Instance Number %d. = \n", BoxInst); + } + break; + + case BOX_IIO_RTO: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst < MAX_ALL_IIO_RTO)) { + Dev =3D 7; + } else { + CpuCsrAccessError (host, "\nInvalid IIO RTO Box Instance Number %d. = \n", BoxInst); + } + break; + + case BOX_UBOX: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst < MAX_ALL_UBOX)) { + Dev =3D 8; + } else { + CpuCsrAccessError (host, "\nInvalid Ubox Instance Number %d. \n", Bo= xInst); + //Note: the fatal error function writes to UBOX CSR and recurses for= ever (until stack is gone). + } + break; + case BOX_FPGA: + if ((CpuType =3D=3D CPU_SKX) && (BoxInst =3D=3D 0)) { + Dev =3D 16; + } else { + CpuCsrAccessError (host, "\nInvalid FPGA Instance number %d. \n", Bo= xInst); + } + break; + + default: + CpuCsrAccessError (host, "\nInvalid Box Type %d. \n", BoxType); + } + + if (Dev > 31) { + CpuCsrAccessError (host, "\nInvalid Device %d accessed for Box Type %d= and Box Instance %d. \n", Dev, BoxType, BoxInst); + } + return Dev; +} + +/** + + Indetifies the function number for given BoxType, BoxInst & Functional B= lock + + @param host - Pointer to the system host (root) structure + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - Box Instance, 0 based + @param FuncBlk - Functional Block; values come from CpuPciAccess.h + + @retval PCI Function number + +**/ +UINT32 +GetFunctionNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ + UINT32 Fun =3D 0; + UINT8 CpuIndex, CpuType, NumChPerMC; + + CpuType =3D CpuCsrAccessVar->cpuType; + NumChPerMC =3D CpuCsrAccessVar->numChPerMC; + + // Get the CPU type, sub type + CpuIndex =3D GetCpuIndex(host); + + // + // Translate the Box Type & Functional Block into PCI function number. N= ote that the box type & instance number + // passed to this routine are assumed to be valid; here we only need to = validate if the function number is correct + // after the look up is done. + // + + switch (BoxType) { + + case BOX_MC: + + if (FuncBlk =3D=3D 0 || FuncBlk =3D=3D 1) { + Fun =3D FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk; + } else { + Fun =3D 4; + } + break; + + case BOX_MCDDC: + + Fun =3D FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk; + break; + + case BOX_MCIO: + + if (FuncBlk =3D=3D 2) { + Fun =3D FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + 3; + + } else { + Fun =3D FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk; + } + break; + + case BOX_CHA_MISC: + case BOX_CHA_PMA: + case BOX_CHA_CMS: + // + // For Cha, no table look up is needed; the function number can be obt= ained from instance number. + // + if ((CpuType =3D=3D CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + Fun =3D (BoxInst % 8); + } + break; + + case BOX_M3KTI: + /* + Logical M3KTI # Dev # Fun # + KTI01 0 18 0 + KTI23 1 18 4 + */ + + Fun =3D FunTbl[CpuType][BoxType][FuncBlk]; + if (BoxInst =3D=3D 1) { + Fun =3D Fun + 4; + } + break; + + case BOX_M2MEM: + case BOX_CHABC: + case BOX_PCU: + case BOX_VCU: + case BOX_IIO_PCIE_DMI: + case BOX_IIO_PCIE: + case BOX_IIO_PCIE_NTB: + case BOX_IIO_CB: + case BOX_IIO_VTD: + case BOX_UBOX: + Fun =3D FunTbl[CpuType][BoxType][FuncBlk]; + break; + + case BOX_M2UPCIE: + Fun =3D FunTbl[CpuType][BoxType][FuncBlk]; + if (BoxInst =3D=3D 2 || BoxInst =3D=3D 4) { // M2PCIE2 & M2MC= P1 + Fun =3D Fun + 4; + } + break; + + case BOX_KTI: + Fun =3D FunTbl[CpuType][BoxType][FuncBlk]; + if (BoxInst >=3D9 ) { + Fun =3D Fun + 4; + } + break; + + case BOX_IIO_RTO: + if ((BoxInst < MAX_ALL_IIO_RTO) && (FunTbl[CpuType][BoxType][FuncBlk] = !=3D 0xFF)) { + if (FuncBlk =3D=3D IIO_RTO) { + if (BoxInst =3D=3D 0) { + // Cstack + Fun =3D 0; + } else { + // M/Pstacks + Fun =3D 0 + ((BoxInst-1) % 4); + } + } else { + Fun =3D FunTbl[CpuType][BoxType][FuncBlk]; + } + } else { + CpuCsrAccessError (host, "\nInvalid IIO RTO Box Instance Number %d. = \n", BoxInst); + } + break; + + case BOX_FPGA: + if (BoxInst =3D=3D 0) { + Fun =3D 0; + } else { + CpuCsrAccessError (host, "\nInvalid FPGA Box Instance Number %d. \n"= , BoxInst); + } + break; + + default: + CpuCsrAccessError (host, "\nInvalid Box Type %d. \n", BoxType); + } + + if (Fun > 7) { + CpuCsrAccessError (host, "\nInvalid Functional Block %d accessed for C= PUType %d CPUIndex %d Box Type %d and Box Instance %d. \n", + FuncBlk, CpuType, CpuIndex, BoxType, BoxInst); + } + + return Fun; +} + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip= /Include/CpuCsrAccessDefine.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Libra= ry/ProcMemInit/Chip/Include/CpuCsrAccessDefine.h new file mode 100644 index 0000000000..bee66dbed9 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Includ= e/CpuCsrAccessDefine.h @@ -0,0 +1,52 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_CSR_ACCESS_DEFINE_H_ +#define _CPU_CSR_ACCESS_DEFINE_H_ + +#include +#include + + +typedef enum { + BUS_CLASS =3D 0, + DEVICE_CLASS =3D 1, + FUNCTION_CLASS =3D 2 +} BDF_CLASS; + +UINT32 +GetSegmentNumber ( + IN USRA_ADDRESS *Address + ); + +UINT32 +GetBDFNumber ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + IN UINT8 BDFType + ); + +UINT32 +GetCpuCsrAddress ( + UINT8 SocId, + UINT8 BoxInst, + UINT32 Offset, + UINT8 *Size + ); + +UINT32 +GetMmcfgAddress( + PSYSHOST host + ); + +VOID +GetCpuCsrAccessVar_RC ( + PSYSHOST host, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +#endif // _CPU_CSR_ACCESS_DEFINE_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip= /Include/CpuPciAccess.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/Pro= cMemInit/Chip/Include/CpuPciAccess.h new file mode 100644 index 0000000000..6ace86975a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Includ= e/CpuPciAccess.h @@ -0,0 +1,117 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_PCI_ACCESS_H_ +#define _CPU_PCI_ACCESS_H_ + +#include "DataTypes.h" + + + +// +// CPU Types; this needs to be contiguous to assist in table look up +// +#define MAX_CPU_TYPES 1 + +// +// CPU Index for MC function look-up +// +#define MAX_CPU_INDEX 1 + + +// +// Box Types; this needs to be contiguous to assist in table look up +// +#define BOX_CHA_MISC 0 +#define BOX_CHA_PMA 1 +#define BOX_CHA_CMS 2 +#define BOX_CHABC 3 +#define BOX_PCU 4 +#define BOX_VCU 5 +#define BOX_M2MEM 6 +#define BOX_MC 7 +#define BOX_MCIO 8 +#define BOX_KTI 9 +#define BOX_M3KTI 10 +#define BOX_MCDDC 11 +#define BOX_M2UPCIE 12 +#define BOX_IIO_PCIE_DMI 13 +#define BOX_IIO_PCIE 14 +#define BOX_IIO_PCIE_NTB 15 +#define BOX_IIO_CB 16 +#define BOX_IIO_VTD 17 +#define BOX_IIO_RTO 18 +#define BOX_UBOX 19 +#define BOX_FPGA 20 +#define MAX_BOX_TYPES 21 + + +// +// Maximum Number of Instances supported by each box type. Note that if th= e number of instances +// are same for all supported CPUs, then we will have only one #define her= e (i.e MAX_ALL_XXXXX) +// +#define MAX_SKX_CHA 28 + +#define MAX_SKX_M2PCIE 5 + +#define MAX_ALL_CBOBC 1 + +#define MAX_SKX_M3KTI 2 + +#define MAX_SKX_KTIAGENT 3 + +#define MAX_SKX_M2MEM 2 + +#define MAX_ALL_M2PCIE 1 +#define MAX_ALL_UBOX 1 +#define MAX_ALL_IIO 4 +#define MAX_ALL_PCU 1 +#define MAX_ALL_VCU 1 + +#define MAX_ALL_IIO_CB 1 // 1 instance per CB function block +#define MAX_ALL_IIO_PCIE_DMI 1 // 0:0:0 +#define MAX_ALL_IIO_PCIE_NTB 3 // 4 instances in PCIE_NTB (0:3:0/1/2/= 3) +#define MAX_ALL_IIO_RTO 21 // 4 instances per M/PSTACK + 1 Cstack +#define MAX_ALL_IIO_RTO_DMI 4 // 4 instances in C stack +#define MAX_ALL_IIO_RTO_VTD 6 // 6 instances in IIO_RTO block across= C/P/MCP stacks +#define MAX_ALL_IIO_RTO_VTD_DMI 1 // 1 instances in IIO_RTO block across= C stack +#define MAX_ALL_IIO_PCIE 21 // 4 instances per M/PSTACK + 1 Cstack + + +#define IIO_RTO 0 +#define IIO_RTO_DMI 1 +#define IIO_RTO_GLOBAL 2 +#define IIO_RTO_GLOBAL_DMI 3 +#define IIO_RTO_VTD 4 +#define IIO_RTO_VTD_DMI 5 + +// +// Format of CSR register offset passed to helper functions. +// This must be kept in sync with the CSR XML parser tool that generates C= SR offset definitions in the CSR header files. +// +typedef union { + struct { + UINT32 offset : 12; // bits <11:0> + UINT32 size : 3; // bits <14:12> + UINT32 pseudo : 1; // bit <15> + UINT32 funcblk : 8; // bits <23:16> + UINT32 boxtype : 8; // bits <31:24> + } Bits; + UINT32 Data; +} CSR_OFFSET; + + +// +// Format of CSR register offset passed to helper functions. +// This must be kept in sync with the CSR XML parser tool that generates C= SR offset definitions in the CSR header files. +// +#define PCI_REG_ADDR(Bus,Device,Function,Offset) \ + (((Offset) & 0xff) | (((Function) & 0x07) << 8) | (((Device) & 0x1f) << = 11) | (((Bus) & 0xff) << 16)) +#define PCIE_REG_ADDR(Bus,Device,Function,Offset) \ + (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) <= < 15) | (((Bus) & 0xff) << 20)) + +#endif // _CPU_PCI_ACCESS_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip= /Include/CpuPciAccessCommon.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Libra= ry/ProcMemInit/Chip/Include/CpuPciAccessCommon.h new file mode 100644 index 0000000000..b949d7073f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Includ= e/CpuPciAccessCommon.h @@ -0,0 +1,83 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_PCI_ACCESS_COMMON_H_ +#define _CPU_PCI_ACCESS_COMMON_H_ + +#include + +/** + + Indetifies the bus number for given SocId & BoxType + + @param host - Pointer to sysHost, the system host (root) stru= cture + @param SocId - CPU Socket Node number (Socket ID) + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - IIO PCIE Box Instance + @param FuncBlk - Function Block within IIO + @param CpuCsrAccessVar - Pointer to CSR access data + + @retval (UINT32) PCI bus number + +**/ +UINT32 +GetBusNumber ( + PSYSHOST host, + UINT8 SocId, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +/** + + Indetifies the device number for given SocId & BoxType + + @param host - Pointer to sysHost, the system host (root) stru= cture + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - IIO PCIE Box Instance + @param FuncBlk - Function Block within IIO + @param CpuCsrAccessVar - Pointer to CSR access data + + @retval (UINT32) PCI device number + +**/ +UINT32 +GetDeviceNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +/** + + Indetifies the function number for given SocId & BoxType + + @param host - Pointer to sysHost, the system host (root) stru= cture + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - IIO PCIE Box Instance + @param FuncBlk - Function Block within IIO + @param CpuCsrAccessVar - Pointer to CSR access data + + @retval (UINT32) PCI function number + +**/ +UINT32 +GetFunctionNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +#endif // _CPU_PCI_ACCESS_COMMON_H_ + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip= /Include/Rc_Revision.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/Proc= MemInit/Chip/Include/Rc_Revision.h new file mode 100644 index 0000000000..8f8e123f3a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Includ= e/Rc_Revision.h @@ -0,0 +1,13 @@ +/** @file + Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// Declarations and directives +// ------------------------------------- +// Reference Code (RC) revision in BCD format: +// [31:20] =3D Major revision number +// [19:12] =3D Minor revision number +// [11:0] =3D Release Candidate number / Reserved +#define RC_REVISION 0x06104402 diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/Cs= rAccess.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/Csr= Access.c new file mode 100644 index 0000000000..ef179d9bae --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/CsrAccess= .c @@ -0,0 +1,118 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UsraAccessLib.h" + +/** + This API get the CSR address from the given USRA Address. + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Add= ress Structure + @param[out] AlignedAddress A pointer of aligned address converted f= rom USRA address + + @retval NONE +**/ +VOID +GetCsrAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + CsrGetPcieAlignAddress (Global, Virtual, Address, AlignedAddress); +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register r= ead operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + UINTN AlignedAddress =3D 0; + + GetCsrAccessAddress (NULL, 0, Address, &AlignedAddress); + + UsraRegAlignedRead((UINT32)Address->Attribute.AccessWidth, AlignedAddr= ess, Buffer); + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register w= rite operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + UINTN AlignedAddress =3D 0; + + GetCsrAccessAddress (NULL, 0, Address, &AlignedAddress); + + UsraRegAlignedWrite((UINT32)Address->Attribute.AccessWidth, AlignedAdd= ress, Buffer); + + if (FeaturePcdGet (PcdUsraSupportS3)) + { + if(Address->Attribute.S3Enable) + { + S3BootScriptSaveMemWrite ((S3_BOOT_SCRIPT_LIB_WIDTH)Address->Attribu= te.AccessWidth, (UINT64)AlignedAddress, 1, Buffer); + } + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register A= ND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and w= rite the result back to the register + + @param[in] Address A pointer of the address of the silicon = register to be written + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ) +{ + + UINT64 Data; + UINT8 WidthTable[] =3D {1,2,4,8}; + UINTN AlignedAddress =3D 0; + + GetCsrAccessAddress (NULL, 0, Address, &AlignedAddress); + + UsraRegAlignedRead((UINT32)Address->Attribute.AccessWidth, AlignedAddr= ess, &Data); + DataAndOr (&Data, AndBuffer, OrBuffer, WidthTable[(UINT8)Address->Attr= ibute.AccessWidth]); + UsraRegAlignedWrite((UINT32)Address->Attribute.AccessWidth, AlignedAdd= ress, &Data); + + return RETURN_SUCCESS; +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/Pc= ieAccess.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/Pc= ieAccess.c new file mode 100644 index 0000000000..c8df71a3f9 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/PcieAcces= s.c @@ -0,0 +1,354 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UsraAccessLib.h" + +#define MAX_IO_PORT_ADDRESS 0xFFFF + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mInStride[] =3D { + 1, // UsraWidth8 + 2, // UsraWidth16 + 4, // UsraWidth32 + 8, // UsraWidth64 + 0, // UsraWidthFifo8 + 0, // UsraWidthFifo16 + 0, // UsraWidthFifo32 + 0, // UsraWidthFifo64 + 1, // UsraWidthFill8 + 2, // UsraWidthFill16 + 4, // UsraWidthFill32 + 8 // UsraWidthFill64 +}; + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mOutStride[] =3D { + 1, // UsraWidth8 + 2, // UsraWidth16 + 4, // UsraWidth32 + 8, // UsraWidth64 + 1, // UsraWidthFifo8 + 2, // UsraWidthFifo16 + 4, // UsraWidthFifo32 + 8, // UsraWidthFifo64 + 0, // UsraWidthFill8 + 0, // UsraWidthFill16 + 0, // UsraWidthFill32 + 0 // UsraWidthFill64 +}; + + +/** + This API gets the Pcie address from the given USRA Address. + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Add= ress Structure + @param[out] AlignedAddress A pointer of aligned address converted f= rom USRA address + + @retval NONE +**/ +VOID +GetPcieAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + INTN MmCfgBase; + + MmCfgBase =3D GetPcieSegMmcfgBaseAddress(Address); + // TODO: add Error Check for NULL later + *AlignedAddress =3D MmCfgBase + (UINTN)(Address->Attribute.RawData32[0] = & 0x0fffffff); +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register = read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + UINTN AlignedAddress; + + GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress); + UsraRegAlignedRead((UINT32)Address->Attribute.AccessWidth, AlignedAddres= s, Buffer); + + return RETURN_SUCCESS; +} + +/** + Check parameters to PcieBlkRegisterRead() function request. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + UsraWidth64 do not work. Misaligned buffers, on the other hand, will + be handled by the driver. + + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port= operation. + @param[in] Width Signifies the width of the I/O or Memory opera= tion. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The n= umber of + bytes moved is Width size * Count, starting at= Address. + @param[in] Buffer For read operations, the destination buffer to= store the results. + For write operations, the source buffer from w= hich to write data. + + @retval EFI_SUCCESS The parameters for this request pass the = checks. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +RETURN_STATUS +CpuIoCheckParameter ( + IN BOOLEAN MmioOperation, + IN USRA_ACCESS_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT64 MaxCount; + UINT64 Limit; + + // + // Check to see if Buffer is NULL + // + if (Buffer =3D=3D NULL) { + return RETURN_INVALID_PARAMETER; + } + + // + // Check to see if Width is in the valid range + // + if ((UINT32)Width >=3D UsraWidthMaximum) { + return RETURN_INVALID_PARAMETER; + } + + // + // For FIFO type, the target address won't increase during the access, + // so treat Count as 1 + // + if (Width >=3D UsraWidthFifo8 && Width <=3D UsraWidthFifo64) { + Count =3D 1; + } + + // + // Check to see if Width is in the valid range for I/O Port operations + // + Width =3D (USRA_ACCESS_WIDTH) (Width & 0x03); + if (!MmioOperation && (Width =3D=3D UsraWidth64)) { + return RETURN_INVALID_PARAMETER; + } + + // + // Check to see if Address is aligned + // + if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { + return RETURN_UNSUPPORTED; + } + + // + // Check to see if any address associated with this transfer exceeds the= maximum + // allowed address. The maximum address implied by the parameters passe= d in is + // Address + Size * Count. If the following condition is met, then the = transfer + // is not supported. + // + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_POR= T_ADDRESS) + 1 + // + // Since MAX_ADDRESS can be the maximum integer value supported by the C= PU and Count + // can also be the maximum integer value supported by the CPU, this range + // check must be adjusted to avoid all oveflow conditions. + // + // The following form of the range check is equivalent but assumes that + // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1). + // + Limit =3D (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); + if (Count =3D=3D 0) { + if (Address > Limit) { + return RETURN_UNSUPPORTED; + } + } else { + MaxCount =3D RShiftU64 (Limit, Width); + if (MaxCount < (Count - 1)) { + return RETURN_UNSUPPORTED; + } + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { + return RETURN_UNSUPPORTED; + } + } + + // + // Check to see if Buffer is aligned + // (IA-32 allows UINT64 and INT64 data types to be 32-bit aligned.) + // + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != =3D 0) { + return RETURN_UNSUPPORTED; + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon reg= ister read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval RETURN_SUCCESS The function completed successfully. + @retval Others Some error occurs when executing CpuIoCh= eckParameter function. +**/ +RETURN_STATUS +PcieBlkRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + UINT8 InStride; + UINT8 OutStride; + RETURN_STATUS Status; + UINTN AlignedAddress; + UINT32 ReadCount =3D Address->PcieBlk.Count; + UINT8 *UINT8Buffer; + + GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress); + Status =3D CpuIoCheckParameter (TRUE, Address->Attribute.AccessWidth, Al= ignedAddress, ReadCount, Buffer); + if (RETURN_ERROR (Status)) { + return Status; + } + + InStride =3D mInStride[Address->Attribute.AccessWidth]; + OutStride =3D mOutStride[Address->Attribute.AccessWidth]; + for (UINT8Buffer =3D Buffer; ReadCount > 0; AlignedAddress +=3D InStride= , UINT8Buffer +=3D OutStride, ReadCount--) { + UsraRegAlignedRead((USRA_ACCESS_WIDTH) (Address->Attribute.AccessWidth= & 0x03), AlignedAddress, (VOID *)UINT8Buffer); + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register = write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + UINTN AlignedAddress; + + GetPcieAccessAddress(NULL, 0, Address, &AlignedAddress); + UsraRegAlignedWrite((UINT32)Address->Attribute.AccessWidth, AlignedAddre= ss, Buffer); + + if (FeaturePcdGet (PcdUsraSupportS3)) + { + if(Address->Attribute.S3Enable) + { + S3BootScriptSaveMemWrite ((S3_BOOT_SCRIPT_LIB_WIDTH)Address->Attribu= te.AccessWidth, (UINT64)AlignedAddress, 1, Buffer); + } + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon reg= ister write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval RETURN_SUCCESS The function completed successfully. + @retval Others Some error occurs when executing CpuIoCh= eckParameter function. +**/ +RETURN_STATUS +PcieBlkRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + UINT8 InStride; + UINT8 OutStride; + RETURN_STATUS Status; + UINTN AlignedAddress; + UINT32 WriteCount =3D Address->PcieBlk.Count; + UINT8 *UINT8Buffer; + + GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress); + Status =3D CpuIoCheckParameter (TRUE, Address->Attribute.AccessWidth, Al= ignedAddress, WriteCount, Buffer); + if (RETURN_ERROR (Status)) { + return Status; + } + + InStride =3D mInStride[Address->Attribute.AccessWidth]; + OutStride =3D mOutStride[Address->Attribute.AccessWidth]; + for (UINT8Buffer =3D Buffer; WriteCount > 0; AlignedAddress +=3D InStrid= e, UINT8Buffer +=3D OutStride, WriteCount--) { + UsraRegAlignedWrite((USRA_ACCESS_WIDTH) (Address->Attribute.AccessWidt= h & 0x03), AlignedAddress, (VOID *)UINT8Buffer); + + if (FeaturePcdGet (PcdUsraSupportS3)) { + if(Address->Attribute.S3Enable) { + S3BootScriptSaveMemWrite ((S3_BOOT_SCRIPT_LIB_WIDTH)(Address->Attr= ibute.AccessWidth & 0x03), (UINT64)AlignedAddress, 1, (VOID *)UINT8Buffer); + } + } + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register = AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and w= rite the result back to the register + + @param[in] Address A pointer of the address of the silicon = register to be modified + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ) +{ + UINT64 Data; + UINT8 WidthTable[] =3D {1,2,4,8}; + + PcieRegisterRead(Address, &Data); + DataAndOr (&Data, AndBuffer, OrBuffer, WidthTable[(UINT8)Address->Attrib= ute.AccessWidth]); + PcieRegisterWrite(Address, &Data); + + return RETURN_SUCCESS; +} + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/Us= raAccessLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib= /UsraAccessLib.c new file mode 100644 index 0000000000..d67d04a0cf --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAcces= sLib.c @@ -0,0 +1,235 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UsraAccessLib.h" + +GET_ALLIGNED_ACCESS_ADDRESS mAccessAddrPtr[] =3D +{ + &GetPcieAccessAddress, // AddrTypePCIE + &GetPcieAccessAddress, // AddrTypePCIEBLK + &GetCsrAccessAddress, // AddrTypeCSR +}; + +REGISTER_READ mRegisterReadPtr[] =3D +{ + &PcieRegisterRead, // AddrTypePCIE + &PcieBlkRegisterRead, // AddrTypePCIEBLK + &CsrRegisterRead, // AddrTypeCSR +}; + +REGISTER_WRITE mRegisterWritePtr[] =3D +{ + &PcieRegisterWrite, // AddrTypePCIE + &PcieBlkRegisterWrite, // AddrTypePCIEBLK + &CsrRegisterWrite, // AddrTypeCSR +}; + +REGISTER_MODIFY mRegisterModifyPtr[] =3D +{ + &PcieRegisterModify, // AddrTypePCIE + &PcieRegisterModify, // AddrTypePCIEBLK + &CsrRegisterModify, // AddrTypeCSR +}; + +/** + Perform MMIO read + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be read out + @param[in] Buffer A pointer of buffer contains the data to= be read out + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedRead ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ) +{ + switch (AccessWidth) + { + case UsraWidth8: + *((UINT8*)Buffer) =3D MmioRead8 (AlignedAddress); + break; + case UsraWidth16: + *((UINT16*)Buffer) =3D MmioRead16 (AlignedAddress); + break; + case UsraWidth32: + *((UINT32*)Buffer) =3D MmioRead32 (AlignedAddress); + break; + default: + *((UINT64*)Buffer) =3D MmioRead64 (AlignedAddress); + break; + } + + return RETURN_SUCCESS; +}; + +/** + Perform MMIO write + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be written + @param[in] Buffer A pointer of buffer contains the data to= be written + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedWrite ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ) +{ + switch (AccessWidth) + { + case UsraWidth8: + MmioWrite8 (AlignedAddress,*((UINT8*)Buffer)); + break; + case UsraWidth16: + MmioWrite16 (AlignedAddress,*((UINT16*)Buffer)); + break; + case UsraWidth32: + MmioWrite32 (AlignedAddress,*((UINT32*)Buffer)); + break; + default: + MmioWrite64 (AlignedAddress, *((UINT64*)Buffer)); + break; + } + return RETURN_SUCCESS; +} + +/** + Perform AND then OR operations for a input data + + @param[in out] Data A pointer of the address of the register= to be modified + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + @param[in] NumOfByte NumOfByte Count of byte data to be perfo= rmed + + @retval NONE +**/ +VOID +DataAndOr ( + IN UINT64 *Data, + IN VOID *AndBuffer, + IN VOID *OrBuffer, + IN UINT8 NumOfByte +) +{ + union{ + UINT64 QW; + UINT8 Byte[8]; + } Buffer; + UINT8 AndData[8], OrData[8], i; + + Buffer.QW =3D *Data; + for(i=3D0;iAttribute.AddrType] (NULL, 0, Address, &AlignedA= ddress); + + return AlignedAddress; +}; + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit silicon register read = operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + return mRegisterReadPtr[Address->Attribute.AddrType] (Address, Buffer); +}; + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit silicon register write= operations. + It transfers data from a naturally aligned data buffer into a silicon re= gister. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + return mRegisterWritePtr[Address->Attribute.AddrType] (Address, Buffer); +}; + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit silicon register AND t= hen OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and w= rite the result back to the register + + @param[in] Address A pointer of the address of the silicon = register to be written + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ) +{ + return mRegisterModifyPtr[Address->Attribute.AddrType] (Address, AndBuff= er, OrBuffer); +}; diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/Us= raAccessLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib= /UsraAccessLib.h new file mode 100644 index 0000000000..b699a71683 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAcces= sLib.h @@ -0,0 +1,257 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __USRA_ACCESS_LIB_H__ +#define __USRA_ACCESS_LIB_H__ + +#include +#include +#include +#include +#include +#include +#include + +// +// Get Aligned Access Address +// +typedef + VOID + (EFIAPI *GET_ALLIGNED_ACCESS_ADDRESS) (VOID*, BOOLEAN, USRA_ADDRESS*, UI= NTN*); + +// +// Register Read +// +typedef + RETURN_STATUS + (EFIAPI *REGISTER_READ) (USRA_ADDRESS *, VOID *); + +// +// Register Write +// +typedef + RETURN_STATUS + (EFIAPI *REGISTER_WRITE) (USRA_ADDRESS *, VOID *); + +// +// Register Write +// +typedef + RETURN_STATUS + (EFIAPI *REGISTER_MODIFY) (USRA_ADDRESS *, VOID *, VOID *); + +/** + This API get the Pcie address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + + @retval NONE +**/ +VOID +GetPcieAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + +/** + This API get the CSR address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval NONE +**/ +VOID +GetCsrAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register r= ead operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon regi= ster read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieBlkRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register re= ad operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be read out + @param[in] Buffer A pointer of buffer for the value read f= rom the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register w= rite operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon regi= ster write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieBlkRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register wr= ite operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Add= ress Structure to be written + @param[in] Buffer A pointer of buffer for the value write = to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register A= ND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and w= rite the result back to the register + + @param[in] Address A pointer of the address of the silicon = register to be modified + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register AN= D then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and w= rite the result back to the register + + @param[in] Address A pointer of the address of the silicon = register to be modified + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + Perform MMIO read + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be read out + @param[in] Buffer A pointer of buffer contains the data to= be read out + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedRead ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ); + +/** + Perform AND then OR operations for a input data + + @param[in out] Data A pointer of the address of the register= to be modified + @param[in] AndBuffer A pointer of buffer for the value used f= or AND operation + A NULL pointer means no AND operation. R= egisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used f= or OR operation + A NULL pointer means no OR operation. Re= gisterModify() equivalents to RegisterAnd() + @param[in] NumOfByte NumOfByte Count of byte data to be perfo= rmed + + @retval NONE +**/ +VOID +DataAndOr ( + IN UINT64 *Data, + IN VOID *AndBuffer, + IN VOID *OrBuffer, + IN UINT8 NumOfByte +); + +/** + Perform MMIO write + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be written + @param[in] Buffer A pointer of buffer contains the data to= be written + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedWrite ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ); +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/Us= raAccessLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessL= ib/UsraAccessLib.inf new file mode 100644 index 0000000000..e5f335539f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAcces= sLib.inf @@ -0,0 +1,62 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconAccessLib + FILE_GUID =3D 6CF9B31D-C5E9-4F5F-8030-78883D66CDF0 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconAccessLib + +## { 0x6cf9b31d, 0xc5e9, 0x4f5f, { 0x80, 0x30, 0x78, 0x88, 0x3d, 0x66, 0xc= d, 0xf0 } }; + +[Sources] + UsraAccessLib.c + CsrAccess.c + PcieAccess.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + + +##########################################################################= ###### +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +##########################################################################= ###### + +[LibraryClasses] + S3BootScriptLib + CsrToPcieLib + PcieAddrLib + HobLib + BaseLib + IoLib + +[Guids] + +[FeaturePcd] + gEfiCpRcPkgTokenSpaceGuid.PcdUsraSupportS3 + + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPk= g/IA32FamilyCpuPkg.dec b/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA3= 2FamilyCpuPkg/IA32FamilyCpuPkg.dec new file mode 100644 index 0000000000..47ee1dde5a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/IA32F= amilyCpuPkg.dec @@ -0,0 +1,609 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D IA32FamilyCpuPkg + PACKAGE_GUID =3D 7dbe088f-2e1a-475c-b006-55632c2a5489 + PACKAGE_VERSION =3D 0.5 + +[Includes] + Include + +[LibraryClasses] + CpuConfigLib|Include/Library/CpuConfigLib.h + CpuOnlyResetLib|Include/Library/CpuOnlyResetLib.h + Socket775LgaLib|Include/Library/SocketLga775Lib.h + SocketLga1156Lib|Include/Library/SocketLga1156Lib.h + +[Guids] + ## Include/Guid/HtBistHob.h + gEfiHtBistHobGuid =3D { 0xBE644001, 0xE7D4, 0x48B1, { 0xB0,= 0x96, 0x8B, 0xA0, 0x47, 0xBC, 0x7A, 0xE7 }} + ## Include/Guid/IA32FamilyCpuPkgTokenSpace.h + gEfiCpuTokenSpaceGuid =3D { 0x2ADA836D, 0x0A3D, 0x43D6, { 0xA2,= 0x5A, 0x38, 0x45, 0xCA, 0xD2, 0xD4, 0x00 }} + + ## IntelFrameworkModule package token space guid + # Include/Guid/IntelFrameworkModulePkgTokenSpace.h + gEfiIntelFrameworkModulePkgTokenSpaceGuid =3D { 0xD3705011, 0xBC19, 0x4a= f7, { 0xBE, 0x16, 0xF6, 0x80, 0x30, 0x37, 0x8C, 0x15 }} + +[Ppis] + ## Include/Ppi/Cache.h + gPeiCachePpiGuid =3D { 0xC153205A, 0xE898, 0x4C24, { 0x86,= 0x89, 0xA4, 0xB4, 0xBC, 0xC5, 0xC8, 0xA2 }} + +[Protocols] + gSmmCpuSyncProtocolGuid =3D { 0xd5950985, 0x8be3, 0x4b1c, { 0xb6,= 0x3f, 0x95, 0xd1, 0x5a, 0xb3, 0xb6, 0x5f }} + gSmmCpuSync2ProtocolGuid =3D { 0x9db72e22, 0x9262, 0x4a18, { 0x8f,= 0xe0, 0x85, 0xe0, 0x3d, 0xfa, 0x96, 0x73 }} + gIntelCpuPcdsSetDoneProtocolGuid =3D { 0xadb7b9e6, 0x70b7, 0x48d4, { 0xb= 6, 0xa5, 0x18, 0xfa, 0x15, 0xeb, 0xcd, 0x78 }} + +# +# [Error.gEfiCpuTokenSpaceGuid] +# 0x80000001 | Invalid value provided. +# + +[PcdsFeatureFlag] + ## Indicates if the support for Intel(R) Pentium(R) 4 (90nm) processor w= ith HT + # Technology, Intel(R) Celeron D Processor, Intel(R) Pentium(R) 4 Proce= ssor + # Extreme Edition Supporting HT Technology Processor, and Mobile Intel(= R) + # Pentium(R) 4 Processor supporting HT Technology is included in the CP= U MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Processor Family. + gEfiCpuTokenSpaceGuid.PcdCpuPrescottFamilyFlag|TRUE|BOOLEAN|0x00000001 + ## Indicates if the support for Intel(R) Pentium(R) 4 (65nm) processor s= upporting HT Technology and Intel(R) + # Celeron D Processor is included in the CPU MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Pentium(R) 4 (65nm) processor supportin= g HT Technology and Intel(R) Celeron D Processor Support. + gEfiCpuTokenSpaceGuid.PcdCpuCedarMillFamilyFlag|TRUE|BOOLEAN|0x00000002 + ## Indicates if the support for Intel(R) Core(TM)2 Processor, Intel(R) C= eleron(R) Processor, + # Intel (R) Pentium(R) Processor, and Intel(R) Xeon(R) Processor is inc= luded in + # the CPU MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Core(TM)2 Processor, Intel(R) Celeron(R= ) Processor, Intel (R) Pentium(R) Processor, and Intel(R) Xeon(R) Processor= Support. + gEfiCpuTokenSpaceGuid.PcdCpuConroeFamilyFlag|TRUE|BOOLEAN|0x00000003 + ## Indicates if the support for Intel(R) Atom(TM) E6xx processor family = is + # included in the CPU MP driver.

+ # TRUE - The support for Intel(R) Atom(TM) E6xx processor family is i= ncluded in the CPU MP driver.
+ # FALSE - The support for Intel(R) Atom(TM) E6xx processor family is n= ot included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Atom(TM) E6xx processor family Support. + gEfiCpuTokenSpaceGuid.PcdCpuTunnelCreekFamilyFlag|FALSE|BOOLEAN|0x100000= 33 + ## Indicates if the support for Intel(R) Xeon(R) (45nm QPI) processor fa= mily is included + # in the CPU MP driver.

+ # TRUE - The support for Intel(R) Xeon(R) Processor family (45nm QPI)= is included in the CPU MP driver.
+ # FALSE - The support for Intel(R) Xeon(R) Processor family (45nm QPI)= is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Xeon(R) Processor family (45nm QPI) Sup= port. + gEfiCpuTokenSpaceGuid.PcdCpuNehalemFamilyFlag|TRUE|BOOLEAN|0x10000019 + ## Indicates if the support for Intel(R) Core(TM) 2xxx processor family = is + # included in the CPU MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Xeon(R) Processor, Intel (R) Pentium(R)= Processor, Intel(R) Core(TM) Processor, Intel(R) Celeron(R) Processor Supp= ort. + gEfiCpuTokenSpaceGuid.PcdCpuSandyBridgeFamilyFlag|TRUE|BOOLEAN|0x10000030 + ## Indicates if the support for Intel(R) Atom(TM) C2xxx processor family= is + # included in the CPU MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Atom(TM) C2xxx processor family Support. + gEfiCpuTokenSpaceGuid.PcdCpuSilvermontFamilyFlag|FALSE|BOOLEAN|0x10000034 + ## Indicates if the support for Intel(R) Core(TM) 3xxx processor family = is + # included in the CPU MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Xeon(R) Processor, Intel (R) Pentium(R)= Processor, Intel(R) Core(TM) Processor Support. + gEfiCpuTokenSpaceGuid.PcdCpuIvyBridgeFamilyFlag|TRUE|BOOLEAN|0x10000031 + ## Indicates if the support for 4th Generation Intel(R) Core(TM) process= or family is included in the CPU + # MP driver.

+ # TRUE - The support for 4th Generation Intel(R) Core(TM) processor i= s included in the CPU MP driver.
+ # FALSE - The support for 4th Generation Intel(R) Core(TM) processor i= s not included in the CPU MP driver.
+ # @Prompt CPU MP driver 4th Generation Intel(R) Core(TM) processor suppo= rt. + gEfiCpuTokenSpaceGuid.PcdCpuHaswellFamilyFlag|TRUE|BOOLEAN|0x10000032 + ## Indicates if the support for 5th Generation Intel(R) Core(TM) process= or family is included in the CPU + # MP driver.

+ # TRUE - The support for 5th Generation Intel(R) Core(TM) processor i= s included in the CPU MP driver.
+ # FALSE - The support for 5th Generation Intel(R) Core(TM) processor i= s not included in the CPU MP driver.
+ # @Prompt CPU MP driver 5th Generation Intel(R) Core(TM) processor suppo= rt. + gEfiCpuTokenSpaceGuid.PcdCpuBroadwellFamilyFlag|FALSE|BOOLEAN|0x10000035 + ## Indicates if the support for 6th Generation Intel(R) Core(TM) process= or family is included in the CPU + # MP driver.

+ # TRUE - The support for 6th Generation Intel(R) Core(TM) processor i= s included in the CPU MP driver.
+ # FALSE - The support for 6th Generation Intel(R) Core(TM) processor i= s not included in the CPU MP driver.
+ # @Prompt CPU MP driver 6th Generation Intel(R) Core(TM) processor suppo= rt. + gEfiCpuTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|FALSE|BOOLEAN|0x10000036 + ## Indicates if the support for 16nm Intel(R) Atom(TM) processor family = is included in the CPU + # MP driver.

+ # TRUE - The support for 16nm Intel(R) Atom(TM) processor family is i= ncluded in the CPU MP driver.
+ # FALSE - The support for 16nm Intel(R) Atom(TM) processor family is n= ot included in the CPU MP driver.
+ # @Prompt CPU MP driver 16nm Intel(R) Atom(TM) processor family support. + gEfiCpuTokenSpaceGuid.PcdCpuGoldmontFamilyFlag|FALSE|BOOLEAN|0x10000037 + ## Indicates if the support for 14nm Intel(R) Xeon Phi(TM) Coprocessor f= amily is included in the CPU MP driver.

+ # TRUE - The support for 14nm Intel(R) Xeon Phi(TM) Coprocessor famil= y is included in the CPU MP driver.
+ # FALSE - The support for 14nm Intel(R) Xeon Phi(TM) Coprocessor famil= y is not included in the CPU MP driver.
+ # @Prompt CPU MP driver 14nm Intel(R) Xeon Phi(TM) Coprocessor family su= pport. + gEfiCpuTokenSpaceGuid.PcdCpuKnightsLandingFamilyFlag|FALSE|BOOLEAN|0x100= 00038 + ## Indicates if the support for thermal management features is included = in the CPU MP driver. + # Thermal management features include TM1, TM2 and bi-directional PROCH= OT.

+ # TRUE - The support for thermal management features is included in t= he CPU MP driver.
+ # FALSE - The support for thermal management features is not included = in the CPU MP driver.
+ # @Prompt CPU MP driver thermal management features support. + gEfiCpuTokenSpaceGuid.PcdCpuThermalManagementFlag|TRUE|BOOLEAN|0x10000001 + ## Indicates if the support for enhanced C-State feature (including C1e)= is included in the CPU MP driver.

+ # TRUE - The support for enhanced C-State feature is included in the = CPU MP driver.
+ # FALSE - The support for enhanced C-State feature is not included in = the CPU MP driver.
+ # @Prompt CPU MP driver enhanced C-State feature support. + gEfiCpuTokenSpaceGuid.PcdCpuEnhancedCStateFlag|TRUE|BOOLEAN|0x10000006 + ## Indicates if the support for Limit CPUID Maxval feature is included i= n the CPU MP driver.

+ # TRUE - The support for Limit CPUID Maxval feature is included in th= e CPU MP driver.
+ # FALSE - The support for Limit CPUID Maxval feature is not included i= n the CPU MP driver.
+ # @Prompt CPU MP driver Limit CPUID Maxval feature support. + gEfiCpuTokenSpaceGuid.PcdCpuMaxCpuIDValueLimitFlag|TRUE|BOOLEAN|0x100000= 08 + ## Indicates if the support for CPU microcode update is included in the = CPU MP driver.

+ # TRUE - The support for CPU microcode update is included in the CPU = MP driver.
+ # FALSE - The support for CPU microcode update is not included in the = CPU MP driver.
+ # @Prompt CPU MP driver CPU microcode update support. + gEfiCpuTokenSpaceGuid.PcdCpuMicrocodeUpdateFlag|TRUE|BOOLEAN|0x1000000D + ## Indicates if the support for Machine Check feature is included in the= CPU MP driver.

+ # TRUE - The support for Machine Check feature is included in the CPU= MP driver.
+ # FALSE - The support for Machine Check feature is not included in the= CPU MP driver.
+ # @Prompt CPU MP driver Machine Check feature support. + gEfiCpuTokenSpaceGuid.PcdCpuMachineCheckFlag|TRUE|BOOLEAN|0x1000000E + ## Indicates if the support for Select Least Featured Processor as BSP f= eature is included in the CPU MP driver.

+ # TRUE - The support for Select Least Featured Processor as BSP featu= re is included in the CPU MP driver.
+ # FALSE - The support for Select Least Featured Processor as BSP featu= re is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Select Least Featured Processor as BSP feature s= upport. + gEfiCpuTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|FALSE|BOOLEAN|0x1000000F + ## Indicates if BSP election in SMM will be enabled. + # If enabled, a BSP will be dynamically elected among all processors in= each SMI. + # Otherwise, processor 0 is always as BSP in each SMI.

+ # TRUE - BSP election in SMM will be enabled.
+ # FALSE - BSP election in SMM will be disabled.
+ # @Prompt Enable BSP election in SMM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106 + ## Indicates if the support for Enhanced Intel Speed Step (EIST) feature= is included in the CPU MP driver.

+ # TRUE - The support for EIST feature is included in the CPU MP drive= r.
+ # FALSE - The support for EIST feature is not included in the CPU MP d= river.
+ # @Prompt CPU MP driver EIST feature support. + gEfiCpuTokenSpaceGuid.PcdCpuEistFlag|TRUE|BOOLEAN|0x10000004 + ## Indicates if the support for VT-x and TXT initialization is included = in the CPU MP driver. + # VT-x - Intel Virtualization Technology for IA-32 Intel Architecture. + # TXT - Intel(R) Trusted Execution Technology.

+ # TRUE - The support for VT and LT initialization is included in the = CPU MP driver.
+ # FALSE - The support for VT and LT initialization is not included in = the CPU MP driver.
+ # @Prompt CPU MP driver VT-x and TXT initialization support. + gEfiCpuTokenSpaceGuid.PcdCpuVtLtFlag|TRUE|BOOLEAN|0x10000007 + ## Indicates if the support for Execute Disable Bit feature is included = in the CPU MP driver.

+ # TRUE - The support for Execute Disable Bit feature is included in t= he CPU MP driver.
+ # FALSE - The support for Execute Disable Bit feature is not included = in the CPU MP driver.
+ # @Prompt CPU MP driver Execute Disable Bit feature support. + gEfiCpuTokenSpaceGuid.PcdCpuExecuteDisableBitFlag|TRUE|BOOLEAN|0x10000009 + ## Indicates if the support for Fast Strings for REP MOVS and REP STOS f= eature is included in the CPU MP driver.

+ # TRUE - The support for Fast Strings feature is included in the CPU = MP driver.
+ # FALSE - The support for Fast Strings feature is not included in the = CPU MP driver.
+ # @Prompt CPU MP driver Fast Strings feature support. + gEfiCpuTokenSpaceGuid.PcdCpuFastStringFlag|TRUE|BOOLEAN|0x10000012 + ## Indicates if the support for Hardware Prefetcher feature is included = in the CPU MP driver.

+ # TRUE - The support for Hardware Prefetcher feature is included in t= he CPU MP driver.
+ # FALSE - The support for Hardware Prefetcher feature is not included = in the CPU MP driver.
+ # @Prompt CPU MP driver Hardware Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuHardwarePrefetcherFlag|TRUE|BOOLEAN|0x100000= 13 + ## Indicates if the support for Adjacent Cache Line Prefetcher feature i= s included in the CPU MP driver.

+ # TRUE - The support for Adjacent Cache Line Prefetcher feature is in= cluded in the CPU MP driver.
+ # FALSE - The support for Adjacent Cache Line Prefetcher feature is no= t included in the CPU MP driver.
+ # @Prompt CPU MP driver Adjacent Cache Line Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuAdjacentCacheLinePrefetchFlag|TRUE|BOOLEAN|0= x10000014 + ## Indicates if the support for DCU Streamer Prefetcher feature is inclu= ded in the CPU MP driver.

+ # TRUE - The support for DCU Streamer Prefetcher feature is included = in the CPU MP driver.
+ # FALSE - The support for DCU Streamer Prefetcher feature is not inclu= ded in the CPU MP driver.
+ # @Prompt CPU MP driver DCU Streamer Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuDcuPrefetcherFlag|TRUE|BOOLEAN|0x10000015 + ## Indicates if the support for DCU IP Prefetcher feature is included in= the CPU MP driver.

+ # TRUE - The support for DCU IP Prefetcher feature is included in the= CPU MP driver.
+ # FALSE - The support for DCU IP Prefetcher feature is not included in= the CPU MP driver.
+ # @Prompt CPU MP driver DCU IP Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuIpPrefetcherFlag|TRUE|BOOLEAN|0x10000016 + ## Indicates if the support for MLC Streamer Prefetcher feature is inclu= ded in the CPU MP driver.

+ # TRUE - The support for MLC Streamer Prefetcher feature is included = in the CPU MP driver.
+ # FALSE - The support for MLC Streamer Prefetcher feature is not inclu= ded in the CPU MP driver.
+ # @Prompt CPU MP driver MLC Streamer Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuMlcStreamerPrefetcherFlag|TRUE|BOOLEAN|0x100= 0001D + ## Indicates if the support for MLC Spatial Prefetcher feature is includ= ed in the CPU MP driver.

+ # TRUE - The support for MLC Spatial Prefetcher feature is included i= n the CPU MP driver.
+ # FALSE - The support for MLC Spatial Prefetcher feature is not includ= ed in the CPU MP driver.
+ # @Prompt CPU MP driver MLC Spatial Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuMlcSpatialPrefetcherFlag|TRUE|BOOLEAN|0x1000= 001E + ## Indicates if the support for L2 Prefetcher feature is included in the= CPU MP driver.

+ # TRUE - The support for L2 Prefetcher feature is included in the CPU= MP driver.
+ # FALSE - The support for L2 Prefetcher feature is not included in the= CPU MP driver.
+ # @Prompt CPU MP driver L2 Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuL2PrefetcherFlag|TRUE|BOOLEAN|0x1000002B + ## Indicates if the support for L1 Data Prefetcher feature is included i= n the CPU MP driver.

+ # TRUE - The support for L1 Data Prefetcher feature is included in th= e CPU MP driver.
+ # FALSE - The support for L1 Data Prefetcher feature is not included i= n the CPU MP driver.
+ # @Prompt CPU MP driver L1 Data Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuL1DataPrefetcherFlag|TRUE|BOOLEAN|0x1000002C + ## Indicates if the support for Pending Break Enable feature is included= in the CPU MP driver. + # This feature uses the FERR#/PBE# pin when the processor is in the sto= p-clock state to signal the processor + # that an interrupt is pending and that the processor should return to = normal operation to handle the interrupt.

+ # TRUE - The support for Pending Break Enable feature is included in = the CPU MP driver.
+ # FALSE - The support for Pending Break Enable feature is not included= in the CPU MP driver.
+ # @Prompt CPU MP driver Pending Break Enable feature support. + gEfiCpuTokenSpaceGuid.PcdCpuFerrSignalBreakFlag|TRUE|BOOLEAN|0x10000017 + ## Indicates if the support for Platform Enviroment Control Interface (P= ECI) feature is included in the CPU MP driver.

+ # TRUE - The support for PECI feature is included in the CPU MP drive= r.
+ # FALSE - The support for PECI feature is not included in the CPU MP d= river.
+ # @Prompt CPU MP driver Platform Environment Control Interface (PECI) fe= ature support. + gEfiCpuTokenSpaceGuid.PcdCpuPeciFlag|TRUE|BOOLEAN|0x10000018 + ## Indicates if the support for MONITOR (MONITOR and MWAIT instructions)= feature is included in the CPU MP driver.

+ # TRUE - The support for MONITOR feature is included in the CPU MP dr= iver.
+ # FALSE - The support for MONITOR feature is not included in the CPU M= P driver.
+ # @Prompt CPU MP driver MONITOR feature support. + gEfiCpuTokenSpaceGuid.PcdCpuMonitorMwaitFlag|TRUE|BOOLEAN|0x1000001F + ## Indicates if the support for Three Strike Counter feature is included= in the CPU MP driver.

+ # TRUE - The support for Three Strike Counter feature is included in = the CPU MP driver.
+ # FALSE - The support for Three Strike Counter feature is not included= in the CPU MP driver.
+ # @Prompt CPU MP driver Three Strike Counter feature support. + gEfiCpuTokenSpaceGuid.PcdCpuThreeStrikeCounterFlag|TRUE|BOOLEAN|0x100000= 20 + ## Indicates if the support for CPU Energy Efficiency Policy feature is = included in the CPU MP driver.

+ # TRUE - The support for CPU Energy Efficiency Policy feature is incl= uded in the CPU MP driver.
+ # FALSE - The support for CPU Energy Efficiency Policy feature is not = included in the CPU MP driver.
+ # @Prompt CPU MP driver CPU Energy Efficiency Policy feature support. + gEfiCpuTokenSpaceGuid.PcdCpuEnergyPerformanceBiasFlag|TRUE|BOOLEAN|0x100= 00021 + ## Indicates if the support for T-State feature is included in the CPU M= P driver.

+ # TRUE - The support for T-State feature is included in the CPU MP dr= iver.
+ # FALSE - The support for T-State feature is not included in the CPU M= P driver.
+ # @Prompt CPU MP driver T-State feature support. + gEfiCpuTokenSpaceGuid.PcdCpuTStateFlag|TRUE|BOOLEAN|0x10000022 + ## Indicates if the support for Advanced Encryption Standard (AES) featu= re is included in the CPU MP driver.

+ # TRUE - The support for AES feature is included in the CPU MP driver= .
+ # FALSE - The support for AES feature is not included in the CPU MP dr= iver.
+ # @Prompt CPU MP driver Advanced Encryption Standard (AES) feature suppo= rt. + gEfiCpuTokenSpaceGuid.PcdCpuAesFlag|TRUE|BOOLEAN|0x10000023 + ## Indicates if the support for Direct Cache Access (DCA) feature is inc= luded in the CPU MP driver.

+ # TRUE - The support for DCA feature is included in the CPU MP driver= .
+ # FALSE - The support for DCA feature is not included in the CPU MP dr= iver.
+ # @Prompt CPU MP driver Direct Cache Access (DCA) feature support. + gEfiCpuTokenSpaceGuid.PcdCpuDcaFlag|TRUE|BOOLEAN|0x10000024 + ## Indicates if the support for C-State feature is included in the CPU M= P driver.

+ # TRUE - The support for C-State feature is included in the CPU MP dr= iver.
+ # FALSE - The support for C-State feature is not included in the CPU M= P driver.
+ # @Prompt CPU MP driver C-State feature support. + gEfiCpuTokenSpaceGuid.PcdCpuCStateFlag|TRUE|BOOLEAN|0x10000025 + ## Indicates if the support for x2APIC mode is included in the CPU MP dr= iver.

+ # TRUE - The support for x2APIC mode is included in the CPU MP driver= .
+ # FALSE - The support for x2APIC mode is not included in the CPU MP dr= iver.
+ # @Prompt CPU MP driver x2APIC mode support. + gEfiCpuTokenSpaceGuid.PcdCpuX2ApicFlag|TRUE|BOOLEAN|0x10000026 + ## Indicates if the support for APIC TPR Update message feature is inclu= ded in the CPU MP driver.

+ # TRUE - The support for APIC TPR Update message feature is included = in the CPU MP driver.
+ # FALSE - The support for APIC TPR Update message feature is not inclu= ded in the CPU MP driver.
+ # @Prompt CPU MP driver APIC TPR Update message feature support. + gEfiCpuTokenSpaceGuid.PcdCpuApicTprUpdateMessageFlag|TRUE|BOOLEAN|0x1000= 0027 + ## Indicates if the support for Data Cache Unit (DCU) mode selection fea= ture is included in the CPU MP driver.

+ # TRUE - The support for Data Cache Unit (DCU) mode selection feature= is included in the CPU MP driver.
+ # FALSE - The support for Data Cache Unit (DCU) mode selection feature= is not included in the CPU MP driver.
+ # @Prompt CPU MP driver DCU mode selection feature support. + gEfiCpuTokenSpaceGuid.PcdCpuDcuModeSelectionFlag|TRUE|BOOLEAN|0x10000028 + ## Indicates if the support for A20M Disable feature is included in the = CPU MP driver. + # When the A20M #pin (Address 20 Mask) is asserted, the processor will = mask physical address bit 20 (A20#). + # The A20M Disable can disable this legacy A20M feature.

+ # TRUE - The support for A20M Disable feature is included in the CPU = MP driver.
+ # FALSE - The support for A20M Disable feature is not included in the = CPU MP driver.
+ # @Prompt CPU MP driver A20M Disable feature support. + gEfiCpuTokenSpaceGuid.PcdCpuGateA20MDisableFlag|TRUE|BOOLEAN|0x1000001A + ## Indicates if the support for CPU socket ID re-assignment feature is i= ncluded in the CPU MP driver. + # This feature allows re-assignment of CPU socket ID over hardware powe= r-on default value, which in turn + # changes the APIC ID of logical processors in the CPU socket.

+ # TRUE - The support for CPU socket ID re-assignment feature is inclu= ded in the CPU MP driver.
+ # FALSE - The support for CPU socket ID re-assignment feature is not i= ncluded in the CPU MP driver.
+ # @Prompt CPU MP driver CPU socket ID re-assignment feature support. + gEfiCpuTokenSpaceGuid.PcdCpuSocketIdReassignmentFlag|FALSE|BOOLEAN|0x100= 00029 + ## Indicates if SMM Debug will be enabled. + # If enabled, hardware breakpoints in SMRAM can be set outside of SMM m= ode and take effect in SMM.

+ # TRUE - SMM Debug will be enabled.
+ # FALSE - SMM Debug will be disabled.
+ # @Prompt Enable SMM Debug. + gEfiCpuTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B + ## Indicates if SMM Stack Guard will be enabled. + # If enabled, stack overflow in SMM can be caught which eases debugging= .

+ # TRUE - SMM Stack Guard will be enabled.
+ # FALSE - SMM Stack Guard will be disabled.
+ # @Prompt Enable SMM Stack Guard. + gEfiCpuTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE|BOOLEAN|0x1000001C + ## Indicates if SMM Startup AP in a blocking fashion. + # TRUE - SMM Startup AP in a blocking fashion.
+ # FALSE - SMM Startup AP in a non-blocking fashion.
+ # @Prompt SMM Startup AP in a blocking fashion. + gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x321321= 08 + ## Indicates if SMM Profile will be enabled. + # If enabled, instruction executions in and data accesses to memory out= side of SMRAM will be logged. + # This PCD is only for validation purpose. It should be set to false in= production.

+ # TRUE - SMM Profile will be enabled.
+ # FALSE - SMM Profile will be disabled.
+ # @Prompt Enable SMM Profile. + gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109 + ## Indicates if the SMM profile log buffer is a ring buffer. + # If disabled, no additional log can be done when the buffer is full.
+ # TRUE - the SMM profile log buffer is a ring buffer.
+ # FALSE - the SMM profile log buffer is a normal buffer.
+ # @Prompt The SMM profile log buffer is a ring buffer. + gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a + ## Indicates if SMM MP sync data resides in un-cached RAM.

+ # TRUE - SMM MP sync data will be resided in un-cached RAM.
+ # FALSE - SMM MP sync data will be resided in cached RAM.
+ # @Prompt SMM MP sync data resides in un-cached RAM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmUncacheCpuSyncData|FALSE|BOOLEAN|0x321321= 0D + ## Indidates if CPU SMM hot-plug will be enabled.

+ # TRUE - SMM CPU hot-plug will be enabled.
+ # FALSE - SMM CPU hot-plug will be disabled.
+ # @Prompt SMM CPU hot-plug. + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C + ## Indidates if lock SMM Feature Control MSR.

+ # TRUE - SMM Feature Control MSR will be locked.
+ # FALSE - SMM Feature Control MSR will not be locked.
+ # @Prompt Lock SMM Feature Control MSR. + gEfiCpuTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213= 210B + ## Whether to set the IA untrusted lock feature of SAI-capable processor= s. + # TRUE - IA untrusted lock feature is supported.
+ # FALSE - IA untrusted lock feature is not supported.
+ # @Prompt Enabled the IA untrusted lock feature. + gEfiCpuTokenSpaceGuid.PcdCpuEnableIaUntrustedModeFlag|TRUE|BOOLEAN|0x321= 3210E + ## Indicates if the support for Peci Downstream Write feature is include= d in the CPU MP driver.

+ # TRUE - The support for Peci Downstream Write feature is included in= the CPU MP driver.
+ # FALSE - The support for Peci Downstream Write feature is not include= d in the CPU MP driver.
+ # @Prompt CPU MP driver Peci Downstream Write feature support. + gEfiCpuTokenSpaceGuid.PcdCpuPeciDownstreamWriteFlag|TRUE|BOOLEAN|0x10000= 02E + + gEfiCpuTokenSpaceGuid.PcdCpuPCIeDownStreamPECIFlag|TRUE|BOOLEAN|0x100000= 2F + +[PcdsFixedAtBuild] + ## Specifies maximum number of PPIs provided by SecCore. + # @Prompt Maximum number of PPIs provided by SecCore. + gEfiCpuTokenSpaceGuid.PcdSecCoreMaxPpiSupported|0x6|UINT32|0x10001010 + +[PcdsFixedAtBuild, PcdsPatchableInModule] + ## Specifies maximum number of processors supported by the platform. + # @Prompt Maximum number of processors supported by the platform. + gEfiCpuTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x300000= 02 + ## Specifies timeout value in microseconds for the BSP in SMM to wait fo= r all APs to come into SMM. + # @Prompt AP synchronization timeout value in SMM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104 + ## Specifies stack size in bytes for each processor in SMM. + # @Prompt Processor stack size in SMM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105 + ## Specifies buffer size in bytes to save SMM profile data. The value sh= ould be a multiple of 4KB. + # @Prompt SMM profile data buffer size. + gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107 + ## Specifies the temporary RAM base address. + # @Prompt Temporary RAM base address. + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x10001001 + ## Specifies the temporary RAM size in bytes. + # @Prompt Temporary RAM size. + gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x10001002 + ## Maximum number of processors in SEC (Not used). + # @Prompt Maximum number of processors in SEC. + gEfiCpuTokenSpaceGuid.PcdSecMaximumNumberOfProcessors|1|UINT32|0x10001000 + ## Specifies stack size in the temporary RAM. 0 means half of TemporaryR= amSize. + # @Prompt Stack size in the temporary RAM. + gEfiCpuTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003 + ## Indidates if SMM Code Access Check is enabled. + # If enabled, the SMM handler cannot execut the code outside ranges def= ined by SMRR/SMRR2. + # This PCD is suggested to TRUE in production image.

+ # TRUE - SMM Code Access Check will be enabled.
+ # FALSE - SMM Code Access Check will be disabled.
+ # @Prompt SMM Code Access Check. + gEfiCpuTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x6000= 0013 + +[PcdsDynamicEx] + ## Specifies timeout value in microseconds for the BSP to detect all APs= for the first time. + # @Prompt Timeout for the BSP to detect all APs for the first time. + gEfiCpuTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x3= 0000001 + ## Specifies user's desired settings for enabling/disabling processor fe= atures, each bit corresponding to a specific feature. + # @Prompt User settings for enabling/disabling processor features. + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfiguration|0|UINT32|0= x40000001 + ## Specifies desired settings for enabling/disabling processor features,= each bit corresponding to a specific feature. + # @Prompt User extension1 settings for enabling/disabling processor feat= ures. + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfigurationEx1|0|UINT3= 2|0x40000006 + ## Specifies the Energy efficiency policy when Energy Performance Bias f= eature is enabled. + # 0 - indicates preference to highest performance. + # 15 - indicates preference to maximize energy saving. + # @Prompt The Energy efficiency policy. + # @ValidRange 0x80000001 | 0 - 15 + gEfiCpuTokenSpaceGuid.PcdCpuEnergyPolicy|0x0|UINT8|0x60008000 + ## Specifies the 16-bit IO port base address of the LVL_2 register visib= le to software. + # @Prompt LVL_2 register IO port base address. + gEfiCpuTokenSpaceGuid.PcdCpuAcpiLvl2Addr|0x0|UINT16|0x60008001 + ## Specifies the package C-State limit. + # @Prompt The package C-State limit. + # @ValidRange 0x80000001 | 0 - 7 + gEfiCpuTokenSpaceGuid.PcdCpuPackageCStateLimit|0x0|UINT8|0x60008002 + ## Specifies the On-demand clock modulation duty cycle when T-State feat= ure is enabled. + # @Prompt The encoded values for target duty cycle modulation. + # @ValidRange 0x80000001 | 0 - 15 + gEfiCpuTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x60008003 + ## Indicates if HW Coordination is enabled when EIST feature is enabled.=

+ # TRUE - HW Coordination will be enabled.
+ # FALSE - HW Coordination will be disabled.
+ # @Prompt Enable HW Coordination. + gEfiCpuTokenSpaceGuid.PcdCpuHwCoordination|FALSE|BOOLEAN|0x60008004 + ## Selects the DCU (Data Cache Unit) mode.

+ # 0 - 32-KB 8-way without ECC.
+ # 1 - 16-KB 4-way with ECC.
+ # @Prompt The DCU (Data Cache Unit) mode. + # @ValidRange 0x80000001 | 0 - 1 + gEfiCpuTokenSpaceGuid.PcdCpuDcuMode|0x0|UINT8|0x60008005 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + ## Specifies stack size in bytes for each AP. + # @Prompt AP stack size. + gEfiCpuTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x30000003 + ## Indicates if the platform supports high power load line. + # @Prompt The platform supports high power load line. + gEfiCpuTokenSpaceGuid.PcdPlatformHighPowerLoadLineSupport|TRUE|BOOLEAN|0= x60000001 + ## Platform dynamic Vid support (not used). + # @Prompt Platform dynamic Vid support. + gEfiCpuTokenSpaceGuid.PcdPlatformDynamicVidSupport|TRUE|BOOLEAN|0x600000= 02 + ## Indicates the platform type: desktop, mobile or server.

+ # 0 - desktop
+ # 1 - mobile
+ # 2 - server
+ # @Prompt Platform type. + # @ValidRange 0x80000001 | 0 - 2 + gEfiCpuTokenSpaceGuid.PcdPlatformType|0|UINT8|0x60000003 + ## Indicates the maximum CPU core frequency in the platform. + # @Prompt Maximum CPU core frequency in the platform. + gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|0x0|UINT32|0x600000= 04 + ## Platform CPU maximum FSB frequency (not used). + # @Prompt Platform CPU maximum FSB frequency. + gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxFsbFrequency|0x0|UINT32|0x60000005 + ## Specifies the base address of the first microcode Patch in the microc= ode Region. + # @Prompt Microcode Region base address. + gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x60000009 + ## Specifies the size of the microcode Region. + # @Prompt Microcode Region size. + gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x600000= 0A + ## Indicates if Intel Enhanced Debug (IED) will be enabled. + # Note that for some processors, IED is optional, but for others, IED i= s required.

+ # TRUE - IED will be enabled.
+ # FALSE - IED will be disabled.
+ # @Prompt Enable IED. + gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|FALSE|BOOLEAN|0x6000000B + ## Specifies the IEDRAM size. + # Note that there is a minimum size requirement for a processor. + # @Prompt IEDRAM size. + gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x20000|UINT32|0x6000000C + + ## Specifies the AP wait loop mode during POST. + # The value is defined as below.

+ # 1: ApInHltLoop, AP is in the Hlt-Loop state.
+ # 2: ApInMwaitLoop, AP is in the Mwait-Loop state.
+ # 3: ApInRunLoop, AP is in the Run-Loop state.
+ # @Prompt The AP wait loop mode. + # @ValidRange 0x80000001 | 1 - 3 + gEfiCpuTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006 + ## Specifies the SMRR2 base address.

+ # @Prompt SMRR2 base address. + # @Expression 0x80000001 | (gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Base & = 0xfff) =3D=3D 0 + gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Base|0|UINT32|0x60000015 + ## Specifies the SMRR2 range size.

+ # @Prompt SMRR2 range size. + # @Expression 0x80000001 | (gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Size & = 0xfff) =3D=3D 0 + gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Size|0|UINT32|0x60000016 + ## Specifies the SMRR2 range cache type. + # If SMRR2 is used to map a flash/ROM based handler, it would be config= ured as WP.

+ # 5: WP(Write Protect).
+ # 6: WB(Write Back).
+ # @Prompt SMRR2 range cache type. + # @ValidList 0x80000001 | 5, 6 + gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2CacheType|5|UINT8|0x60000017 + ## Indidates if SMM Delay feature is supported.

+ # TRUE - SMM Delay feature is supported.
+ # FALSE - SMM Delay feature is not supported.
+ # @Prompt SMM Delay feature. + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseDelayIndication|TRUE|BOOLEAN|0x60000018 + ## Indidates if SMM Block feature is supported.

+ # TRUE - SMM Block feature is supported.
+ # FALSE - SMM Block feature is not supported.
+ # @Prompt SMM Block feature. + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseBlockIndication|TRUE|BOOLEAN|0x60000019 + ## Indidates if SMM Enable/Disable feature is supported.

+ # TRUE - SMM Enable/Disable feature is supported.
+ # FALSE - SMM Enable/Disable feature is not supported.
+ # @Prompt SMM Enable/Disable feature. + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication|TRUE|BOOLEAN|0x600= 0001A + ## Specifies the TCC Activation Offset value.

+ # @Prompt TCC Activation Offset value. + gEfiCpuTokenSpaceGuid.PcdCpuTccActivationOffset|0|UINT8|0x6000001B + + +[PcdsDynamicEx] + ## Indidates if SMM Save State saved in MSRs. + # if enabled, SMM Save State will use the MSRs instead of the memory.
+ # TRUE - SMM Save State will use the MSRs.
+ # FALSE - SMM Save State will use the memory.
+ # @Prompt SMM Save State uses MSRs. + gEfiCpuTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE|BOOLEAN|0x600000= 14 + ## Indidates if SMM PROT MODE feature is supported.

+ # TRUE - SMM PROT MODE feature is supported.
+ # FALSE - SMM PROT MODE feature is not supported.
+ # @Prompt SMM PROT MODE feature. + gEfiCpuTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE|BOOLEAN|0x60000= 01C + gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue|0x0|UINT8|0x60008009 + + ## Indicates processor feature capabilities, each bit corresponding to a= specific feature. + # @Prompt Processor feature capabilities. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureCapability|0|UINT32|0x400000= 02 + ## Specifies actual settings for processor features, each bit correspond= ing to a specific feature. + # @Prompt Actual processor feature settings. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureSetting|0|UINT32|0x40000003 + ## Indicates processor feature capabilities, each bit corresponding to a= specific feature. + # @Prompt Processor feature extension1 capabilities. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureCapabilityEx1|0|UINT32|0x400= 00004 + ## Specifies actual settings for processor features, each bit correspond= ing to a specific feature. + # @Prompt Actual processor feature extension1 settings. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureSettingEx1|0|UINT32|0x400000= 05 + ## Contains the pointer to CPU Configuration Context Buffer defined in t= he CpuConfigLib. + # @Prompt The pointer to CPU Configuration Context Buffer. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0|UINT64|0x50000001 + ## Used for a callback mechanism for the CPU MP driver. + # The CPU MP driver will set this PCD at pre-defined points. If there i= s callback function registered on it, + # the callback function will be triggered, and it may change the value = of PcdCpuCallbackSignal. + # @Prompt PCD for CPU callback signal. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuCallbackSignal|0x0|UINT8|0x50000002 + ## Platform CPU frequency lists (not used). + # @Prompt Platform CPU frequency lists. + gEfiCpuTokenSpaceGuid.PcdPlatformCpuFrequencyLists|0x0|UINT64|0x60000006 + ## Specifies the number of CPU sockets in the platform. + # @Prompt The number of CPU sockets in the platform. + gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketCount|0x0|UINT32|0x60000012 + ## Contains the pointer to a pointer array of which each item points to = a unicode string of CPU socket name. + # @Prompt The name of each CPU socket. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketNames|0x0|UINT64|0x60000007 + ## Contains the pointer to a pointer array of which each item points to = a unicode string of CPU asset tag. + # @Prompt The asset tag of each CPU socket. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdPlatformCpuAssetTags|0x0|UINT64|0x60000008 + ## Indicates if the current boot is a power-on reset.

+ # TRUE - Current boot is a power-on reset.
+ # FALSE - Current boot is not a power-on reset.
+ # @Prompt Current boot is a power-on reset. + gEfiCpuTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x6000000F + ## CPU page table address (not used). + # @Prompt CPU page table address. + gEfiCpuTokenSpaceGuid.PcdCpuPageTableAddress|0x0|UINT64|0x6000000E + ## Contains the pointer to a MTRR table buffer of structure MTRR_SETTING= S. + # @Prompt The pointer to a MTRR table buffer. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuMtrrTableAddress|0x0|UINT64|0x6000000D + ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DA= TA. + # @Prompt The pointer to a CPU S3 data buffer. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010 + + ## Contains the pointer to a buffer where new socket IDs to be assigned = are stored. + # @Prompt The pointer to a new socket ID buffer. +# gEfiCpuTokenSpaceGuid.PcdCpuSocketId|{0x0}|VOID*|0x60008007 + + ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug= is supported. + # @Prompt The pointer to CPU Hot Plug Data. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011 + + ## Contains the pointer to a buffer where new socket IDs to be assigned = are stored. + # @Prompt The pointer to a new socket ID buffer. + gEfiCpuTokenSpaceGuid.PcdCpuSocketId|{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x= 1,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x3,0x0,0x0,0= x0,0x3,0x0,0x0,0x0}|VOID*|0x60008007 + gEfiCpuTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE|BOOLEAN|0x6000001D + +[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule] + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x80= 00|UINT32|0x30000005 diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPk= g/Include/Library/CpuConfigLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Ov= erride/IA32FamilyCpuPkg/Include/Library/CpuConfigLib.h new file mode 100644 index 0000000000..83daf1b06e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/Inclu= de/Library/CpuConfigLib.h @@ -0,0 +1,667 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_CONFIG_LIB_H_ +#define _CPU_CONFIG_LIB_H_ + +#include +#include + +// +// Bits definition of PcdProcessorFeatureUserConfiguration, +// PcdProcessorFeatureCapability, and PcdProcessorFeatureSetting +// +#define PCD_CPU_HT_BIT 0x00000001 +#define PCD_CPU_CMP_BIT 0x00000002 +#define PCD_CPU_L2_CACHE_BIT 0x00000004 +#define PCD_CPU_L2_ECC_BIT 0x00000008 +#define PCD_CPU_VT_BIT 0x00000010 +#define PCD_CPU_LT_BIT 0x00000020 +#define PCD_CPU_EXECUTE_DISABLE_BIT 0x00000040 +#define PCD_CPU_L3_CACHE_BIT 0x00000080 +#define PCD_CPU_MAX_CPUID_VALUE_LIMIT_BIT 0x00000100 +#define PCD_CPU_FAST_STRING_BIT 0x00000200 +#define PCD_CPU_FERR_SIGNAL_BREAK_BIT 0x00000400 +#define PCD_CPU_PECI_BIT 0x00000800 +#define PCD_CPU_HARDWARE_PREFETCHER_BIT 0x00001000 +#define PCD_CPU_ADJACENT_CACHE_LINE_PREFETCH_BIT 0x00002000 +#define PCD_CPU_DCU_PREFETCHER_BIT 0x00004000 +#define PCD_CPU_IP_PREFETCHER_BIT 0x00008000 +#define PCD_CPU_MACHINE_CHECK_BIT 0x00010000 +#define PCD_CPU_THERMAL_MANAGEMENT_BIT 0x00040000 +#define PCD_CPU_EIST_BIT 0x00080000 +#define PCD_CPU_C1E_BIT 0x00200000 +#define PCD_CPU_C2E_BIT 0x00400000 +#define PCD_CPU_C3E_BIT 0x00800000 +#define PCD_CPU_C4E_BIT 0x01000000 +#define PCD_CPU_HARD_C4E_BIT 0x02000000 +#define PCD_CPU_DEEP_C4_BIT 0x04000000 +#define PCD_CPU_A20M_DISABLE_BIT 0x08000000 +#define PCD_CPU_MONITOR_MWAIT_BIT 0x10000000 +#define PCD_CPU_TSTATE_BIT 0x20000000 +#define PCD_CPU_TURBO_MODE_BIT 0x80000000 + +// +// Bits definition of PcdProcessorFeatureUserConfigurationEx1, +// PcdProcessorFeatureCapabilityEx1, and PcdProcessorFeatureSettingEx1 +// +#define PCD_CPU_C_STATE_BIT 0x00000001 +#define PCD_CPU_C1_AUTO_DEMOTION_BIT 0x00000002 +#define PCD_CPU_C3_AUTO_DEMOTION_BIT 0x00000004 +#define PCD_CPU_MLC_STREAMER_PREFETCHER_BIT 0x00000008 +#define PCD_CPU_MLC_SPATIAL_PREFETCHER_BIT 0x00000010 +#define PCD_CPU_THREE_STRIKE_COUNTER_BIT 0x00000020 +#define PCD_CPU_ENERGY_PERFORMANCE_BIAS_BIT 0x00000040 +#define PCD_CPU_DCA_BIT 0x00000080 +#define PCD_CPU_X2APIC_BIT 0x00000100 +#define PCD_CPU_AES_BIT 0x00000200 +#define PCD_CPU_APIC_TPR_UPDATE_MESSAGE_BIT 0x00000400 +#define PCD_CPU_SOCKET_ID_REASSIGNMENT_BIT 0x00000800 +#define PCD_CPU_PECI_DOWNSTREAM_WRITE_BIT 0x00001000 +#define PCD_CPU_ENABLE_IA_UNTRUSTED_MODE_BIT 0x00002000 +#define PCD_CPU_L2_PREFETCHER_BIT 0x00004000 +#define PCD_CPU_L1_DATA_PREFETCHER_BIT 0x00008000 +#define PCD_CPU_C1_AUTO_UNDEMOTION_BIT 0x00010000 +#define PCD_CPU_C3_AUTO_UNDEMOTION_BIT 0x00020000 + +// +// Value definition for PcdCpuCallbackSignal +// +#define CPU_BYPASS_SIGNAL 0x00000000 +#define CPU_DATA_COLLECTION_SIGNAL 0x00000001 +#define CPU_PROCESSOR_FEATURE_LIST_CONFIG_SIGNAL 0x00000002 +#define CPU_REGISTER_TABLE_TRANSLATION_SIGNAL 0x00000003 +#define CPU_PROCESSOR_SETTING_SIGNAL 0x00000004 +#define CPU_PROCESSOR_SETTING_END_SIGNAL 0x00000005 + +// CPU C State Settings +#define C3_ENABLE 0x02 +#define C6_ENABLE 0x03 +#define C7_ENABLE 0x04 +#define C8_ENABLE 0x05 +#define C9_ENABLE 0x06 +#define C10_ENABLE 0x07 + +typedef struct { + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; +} EFI_CPUID_REGISTER; + +// +// Enumeration of processor features +// +typedef enum { + Ht, + Cmp, + Vt, + ExecuteDisableBit, + L3Cache, + MaxCpuidValueLimit, + FastString, + FerrSignalBreak, + Peci, + HardwarePrefetcher, + AdjacentCacheLinePrefetch, + DcuPrefetcher, + IpPrefetcher, + ThermalManagement, + Eist, + BiDirectionalProchot, + Forcepr, + C1e, + C2e, + C3e, + C4e, + HardC4e, + DeepC4, + Microcode, + Microcode2, + MachineCheck, + GateA20MDisable, + MonitorMwait, + TState, + TurboMode, + CState, + C1AutoDemotion, + C3AutoDemotion, + MlcStreamerPrefetcher, + MlcSpatialPrefetcher, + ThreeStrikeCounter, + EnergyPerformanceBias, + Dca, + X2Apic, + Aes, + ApicTprUpdateMessage, + TccActivation, + PeciDownstreamWrite, + IaUntrustedMode, + L2Prefetcher, + L1DataPrefetcher, + C1AutoUndemotion, + C3AutoUndemotion, + Dbp, + PpinCtl, + CpuFeatureMaximum +} CPU_FEATURE_ID; + +// +// Structure for collected processor feature capability, +// and feature-specific attribute. +// +typedef struct { + BOOLEAN Capability; + VOID *Attribute; +} CPU_FEATURE_DATA; + +// +// Structure for collected CPUID data. +// +typedef struct { + EFI_CPUID_REGISTER *CpuIdLeaf; + UINTN NumberOfBasicCpuidLeafs; + UINTN NumberOfExtendedCpuidLeafs; + UINTN NumberOfCacheAndTlbCpuidLeafs; + UINTN NumberOfDeterministicCacheParametersCpuidLeaf= s; + UINTN NumberOfExtendedTopologyEnumerationLeafs; +} CPU_CPUID_DATA; + +typedef struct { + UINTN Ratio; + UINTN Vid; + UINTN Power; + UINTN TransitionLatency; + UINTN BusMasterLatency; +} FVID_ENTRY; + +// +// Miscellaneous processor data +// +typedef struct { + // + // Local Apic Data + // + UINT32 InitialApicID; ///< Initial APIC ID + UINT32 ApicID; ///< Current APIC ID + EFI_PHYSICAL_ADDRESS ApicBase; + UINT32 ApicVersion; + // + // Frequency data + // + UINTN IntendedFsbFrequency; + UINTN ActualFsbFrequency; + BOOLEAN FrequencyLocked; + UINTN MaxCoreToBusRatio; + UINTN MinCoreToBusRatio; + UINTN MaxTurboRatio; + UINTN MaxVid; + UINTN MinVid; + UINTN PackageTdp; + UINTN CoreTdp; + UINTN NumberOfPStates; + FVID_ENTRY *FvidTable; + // + // Config TDP data + // + UINTN PkgMinPwrLvl1; + UINTN PkgMaxPwrLvl1; + UINTN ConfigTDPLvl1Ratio; + UINTN PkgTDPLvl1; + UINTN PkgMinPwrLvl2; + UINTN PkgMaxPwrLvl2; + UINTN ConfigTDPLvl2Ratio; + UINTN PkgTDPLvl2; + + // + // Other data + // + UINT32 PlatformRequirement; + UINT64 HealthData; + UINT32 MicrocodeRevision; + UINT64 EnabledThreadCountMsr; +} CPU_MISC_DATA; + +// +// Structure for all collected processor data +// +typedef struct { + CPU_CPUID_DATA CpuidData; + EFI_CPU_PHYSICAL_LOCATION ProcessorLocation; + CPU_MISC_DATA CpuMiscData; + CPU_FEATURE_DATA FeatureData[CpuFeatureMaximum]; + UINT8 PackageIdBitOffset; + BOOLEAN PackageBsp; +} CPU_COLLECTED_DATA; + +#define GET_CPU_MISC_DATA(ProcessorNumber, Item) \ + ((mCpuConfigLibConfigContextBuffer->CollectedDataBuffer[ProcessorNumber]= ).CpuMiscData.Item) + +// +// Signature for feature list entry +// +#define EFI_CPU_FEATURE_ENTRY_SIGNATURE SIGNATURE_32 ('C', 'f', 't', 'r') + +// +// Node of processor feature list +// +typedef struct { + UINT32 Signature; + CPU_FEATURE_ID FeatureID; + VOID *Attribute; + LIST_ENTRY Link; +} CPU_FEATURE_ENTRY; + +#define CPU_FEATURE_ENTRY_FROM_LINK(link) CR (link, CPU_FEATURE_ENTRY, Li= nk, EFI_CPU_FEATURE_ENTRY_SIGNATURE) + +// +// Definition of Processor Configuration Context Buffer +// +typedef struct { + UINTN NumberOfProcessors; + UINTN BspNumber; + CPU_COLLECTED_DATA *CollectedDataBuffer; + LIST_ENTRY *FeatureLinkListEntry; + CPU_REGISTER_TABLE *PreSmmInitRegisterTable; + CPU_REGISTER_TABLE *RegisterTable; + UINTN *SettingSequence; +} CPU_CONFIG_CONTEXT_BUFFER; + +// +// Structure conveying socket ID configuration information. +// +typedef struct { + UINT32 DefaultSocketId; + UINT32 NewSocketId; +} CPU_SOCKET_ID_INFO; + +extern CPU_CONFIG_CONTEXT_BUFFER *mCpuConfigLibConfigContextBuffer; + +/** + Set feature capability and related attribute. + + This function sets the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + @param Attribute Feature-specific data. + +**/ +VOID +EFIAPI +SetProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Clears feature capability and related attribute. + + This function clears the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + +**/ +VOID +EFIAPI +ClearProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID + ); + +/** + Get feature capability and related attribute. + + This function gets the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + @param Attribute Pointer to the output feature-specific data. + + @retval TRUE The feature is supported by the processor + @retval FALSE The feature is not supported by the processor + +**/ +BOOLEAN +EFIAPI +GetProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + OUT VOID **Attribute OPTIONAL + ); + +typedef enum { + BasicCpuidLeaf, + ExtendedCpuidLeaf, + CacheAndTlbCpuidLeafs, + DeterministicCacheParametersCpuidLeafs, + ExtendedTopologyEnumerationCpuidLeafs +} CPUID_TYPE; + +/** + Get the number of CPUID leafs of various types. + + This function get the number of CPUID leafs of various types. + + @param ProcessorNumber Handle number of specified logical processor + @param CpuidType The type of the CPU id. + + @return Maximal index of CPUID instruction for basic leafs. + +**/ +UINTN +EFIAPI +GetNumberOfCpuidLeafs ( + IN UINTN ProcessorNumber, + IN CPUID_TYPE CpuidType + ); + +/** + Get the pointer to specified CPUID leaf. + + This function gets the pointer to specified CPUID leaf. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetProcessorCpuid ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of cache and TLB parameters. + + This function gets the pointer to specified CPUID leaf of cache and TLB = parameters. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetCacheAndTlbCpuidLeaf ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of deterministic cache parameter= s. + + This function gets the pointer to specified CPUID leaf of deterministic = cache parameters. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetDeterministicCacheParametersCpuidLeaf ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of Extended Topology Enumeration. + + This function gets the pointer to specified CPUID leaf of Extended Topol= ogy Enumeration. + + @param ProcessorNumber Handle number of specified logical processor. + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetExtendedTopologyEnumerationCpuidLeafs ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the version information of specified logical processor. + + This function gets the version information of specified logical processo= r, + including family ID, model ID, stepping ID and processor type. + + @param ProcessorNumber Handle number of specified logical processor + @param DisplayedFamily Pointer to family ID for output + @param DisplayedModel Pointer to model ID for output + @param SteppingId Pointer to stepping ID for output + @param ProcessorType Pointer to processor type for output + +**/ +VOID +EFIAPI +GetProcessorVersionInfo ( + IN UINTN ProcessorNumber, + OUT UINT32 *DisplayedFamily OPTIONAL, + OUT UINT32 *DisplayedModel OPTIONAL, + OUT UINT32 *SteppingId OPTIONAL, + OUT UINT32 *ProcessorType OPTIONAL + ); + +/** + Get initial local APIC ID of specified logical processor + + This function gets initial local APIC ID of specified logical processor. + + @param ProcessorNumber Handle number of specified logical processor + + @return Initial local APIC ID of specified logical processor + +**/ +UINT32 +EFIAPI +GetInitialLocalApicId ( + UINTN ProcessorNumber + ); + +/** + Get the location of specified processor. + + This function gets the location of specified processor, including + package number, core number within package, thread number within core. + + @param ProcessorNumber Handle number of specified logical processor. + @param PackageNumber Pointer to the output package number. + @param CoreNumber Pointer to the output core number. + @param ThreadNumber Pointer to the output thread number. + +**/ +VOID +EFIAPI +GetProcessorLocation ( + IN UINTN ProcessorNumber, + OUT UINT32 *PackageNumber OPTIONAL, + OUT UINT32 *CoreNumber OPTIONAL, + OUT UINT32 *ThreadNumber OPTIONAL + ); + +/** + Get the Feature entry at specified position in a feature list. + + This function gets the Feature entry at specified position in a feature = list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureIndex The index of the node in feature list. + @param Attribute Pointer to output feature-specific attribute + + @return Feature ID of specified feature. CpuFeatureMaximum means not fou= nd + +**/ +CPU_FEATURE_ID +EFIAPI +GetProcessorFeatureEntry ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex, + OUT VOID **Attribute OPTIONAL + ); + +/** + Append a feature entry at the end of a feature list. + + This function appends a feature entry at the end of a feature list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID ID of the specified feature. + @param Attribute Feature-specific attribute. + + @retval EFI_SUCCESS This function always return EFI_SUCCESS + +**/ +EFI_STATUS +EFIAPI +AppendProcessorFeatureIntoList ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Delete a feature entry in a feature list. + + This function deletes a feature entry in a feature list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureIndex The index of the node in feature list. + + @retval EFI_SUCCESS The feature node successfully removed. + @retval EFI_INVALID_PARAMETER Index surpasses the length of list. + +**/ +EFI_STATUS +EFIAPI +DeleteProcessorFeatureFromList ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex + ); + +/** + Insert a feature entry into a feature list. + + This function insert a feature entry into a feature list before a node s= pecified by FeatureIndex. + + @param ProcessorNumber Handle number of specified logical proces= sor + @param FeatureIndex The index of the new node in feature list. + @param FeatureID ID of the specified feature. + @param Attribute Feature-specific attribute. + + @retval EFI_SUCCESS The feature node successfully inserted. + @retval EFI_INVALID_PARAMETER Index surpasses the length of list. + +**/ +EFI_STATUS +EFIAPI +InsertProcessorFeatureIntoList ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Add an entry in the post-SMM-init register table. + + This function adds an entry in the post-SMM-init register table, with gi= ven register type, + register index, bit section and value. + + @param ProcessorNumber Handle number of specified logical processor + @param RegisterType Type of the register to program + @param Index Index of the register to program + @param ValidBitStart Start of the bit section + @param ValidBitLength Length of the bit section + @param Value Value to write + +**/ +VOID +EFIAPI +WriteRegisterTable ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT32 Index, + IN UINT8 ValidBitStart, + IN UINT8 ValidBitLength, + IN UINT64 Value + ); + +/** + Add an entry in the pre-SMM-init register table. + + This function adds an entry in the pre-SMM-init register table, with giv= en register type, + register index, bit section and value. + + @param ProcessorNumber Handle number of specified logical processor + @param RegisterType Type of the register to program + @param Index Index of the register to program + @param ValidBitStart Start of the bit section + @param ValidBitLength Length of the bit section + @param Value Value to write + +**/ +VOID +EFIAPI +WritePreSmmInitRegisterTable ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT32 Index, + IN UINT8 ValidBitStart, + IN UINT8 ValidBitLength, + IN UINT64 Value + ); + +/** + Set the sequence of processor setting. + + This function sets the a processor setting at the position in + setting sequence specified by Index. + + @param Index The zero-based index in the sequence. + @param ProcessorNumber Handle number of the processor to set. + + @retval EFI_SUCCESS The sequence successfully modified. + @retval EFI_INVALID_PARAMETER Index surpasses the boundary of sequence. + @retval EFI_NOT_FOUND Processor specified by ProcessorNumber do= es not exist. + +**/ +EFI_STATUS +SetSettingSequence ( + IN UINTN Index, + IN UINTN ProcessorNumber + ); + +/** + Set PcdCpuCallbackSignal, and then read the value back. + + This function sets PCD entry PcdCpuCallbackSignal. If there is callback + function registered on it, the callback function will be triggered, and + it may change the value of PcdCpuCallbackSignal. This function then reads + the value of PcdCpuCallbackSignal back, the check whether it has been ch= anged. + + @param Value The value to set to PcdCpuCallbackSignal. + + @return The value of PcdCpuCallbackSignal read back. + +**/ +UINT8 +SetAndReadCpuCallbackSignal ( + IN UINT8 Value + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPk= g/Include/Protocol/IntelCpuPcdsSetDone.h b/Silicon/Intel/PurleyRefreshSilic= onPkg/Override/IA32FamilyCpuPkg/Include/Protocol/IntelCpuPcdsSetDone.h new file mode 100644 index 0000000000..e21cf0b679 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/Inclu= de/Protocol/IntelCpuPcdsSetDone.h @@ -0,0 +1,18 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _INTEL_CPU_PCDS_SET_DONE_PROTOCOL_H_ +#define _INTEL_CPU_PCDS_SET_DONE_PROTOCOL_H_ + +#define INTEL_CPU_PCDS_SET_DONE_PROTOCOL_GUID \ + { \ + 0xadb7b9e6, 0x70b7, 0x48d4, { 0xb6, 0xa5, 0x18, 0xfa, 0x15, 0xeb, 0xcd= , 0x78 } \ + } + +extern EFI_GUID gIntelCpuPcdsSetDoneProtocolGuid; + +#endif --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Tue, 11 May 2021 02:48:50 -0700 IronPort-SDR: Kp8436RexDekBR2raI/7KmMDi3uLAChkLh612rIb5z3O8z2+HiXj9c4gAmNavzbwRe/xm5JfZW UrzTMwfubOJQ== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="199469634" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="199469634" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:49 -0700 IronPort-SDR: A2TYxyH05y9Ja/gpSqRQCAPBfOUklddaNAOxw7r14+KW8Z6cu7okUaCzWYDwjM40hS/Lw7mJfV N2wPOp14WUUQ== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436573972" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:47 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 08/18] PurleyOpenBoardPkg: Add includes and libraries Date: Tue, 11 May 2021 02:48:16 -0700 Message-Id: <20210511094826.12495-9-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: fIlO8hFLpVOtM7GOevFIqhh2x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726540; bh=TU6IBSy4KZalgY2zumeziiGLdPVFr/ObzGUjKfnNVws=; h=Cc:Date:From:Reply-To:Subject:To; b=kW0/T4ggi69X2GXq8aZMBzgvSbPwZdvowu78Xa6Ofb9Hx6j3eORBHeGXE7Unz8VbDQ7 n6oxCe9rYLJ/lQE0/9f4veuKElhDXMYhRN/qyOy+0mGhmCVqqL6KbJ03xwMscEJ3QZA/E zTOkRDlvofS6Rg/beKCPfNtpxpYAIGTb4ME= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c | 362 ++++++++++ .../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf | 40 ++ .../Features/Ipmi/Library/IpmiLibKcs/KcsBmc.c | 485 +++++++++++++ .../Features/Ipmi/Library/IpmiLibKcs/KcsBmc.h | 208 ++++++ .../IpmiPlatformHookLib/IpmiPlatformHookLib.c | 39 ++ .../IpmiPlatformHookLib.inf | 28 + .../Include/Acpi/GlobalNvs.asi | 282 ++++++++ .../Include/Acpi/GlobalNvsAreaDef.h | 128 ++++ .../Include/Guid/PchRcVariable.h | 414 +++++++++++ .../Include/Guid/SetupVariable.h | 539 ++++++++++++++ .../Include/IioBifurcationSlotTable.h | 100 +++ .../PurleyOpenBoardPkg/Include/Platform.h | 92 +++ .../Include/Ppi/SystemBoard.h | 63 ++ .../Include/Protocol/PciIovPlatform.h | 70 ++ .../PurleyOpenBoardPkg/Include/SetupTable.h | 21 + .../PurleyOpenBoardPkg/Include/SioRegs.h | 35 + .../Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec | 141 ++++ .../SiliconPolicyInitLib.c | 130 ++++ .../SiliconPolicyInitLib.inf | 39 ++ .../PchPolicyUpdateUsb.c | 99 +++ .../SiliconPolicyUpdateLib.c | 659 ++++++++++++++++++ .../SiliconPolicyUpdateLib.inf | 54 ++ 22 files changed, 4028 insertions(+) create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library= /IpmiLibKcs/IpmiLibKcs.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library= /IpmiLibKcs/IpmiLibKcs.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library= /IpmiLibKcs/KcsBmc.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library= /IpmiLibKcs/KcsBmc.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library= /IpmiPlatformHookLib/IpmiPlatformHookLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library= /IpmiPlatformHookLib/IpmiPlatformHookLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNv= s.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNv= sAreaDef.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVar= iable.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVar= iable.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/IioBifurcatio= nSlotTable.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Platform.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Ppi/SystemBoa= rd.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Protocol/PciI= ovPlatform.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/SetupTable.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/SioRegs.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/Library/Silico= nPolicyInitLib/SiliconPolicyInitLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/Library/Silico= nPolicyInitLib/SiliconPolicyInitLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/Library/Silico= nPolicyUpdateLib/PchPolicyUpdateUsb.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/Library/Silico= nPolicyUpdateLib/SiliconPolicyUpdateLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/Library/Silico= nPolicyUpdateLib/SiliconPolicyUpdateLib.inf diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLi= bKcs/IpmiLibKcs.c b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library= /IpmiLibKcs/IpmiLibKcs.c new file mode 100644 index 0000000000..700e413aa6 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/Ip= miLibKcs.c @@ -0,0 +1,362 @@ +/** @file + IPMI library - KCS. + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "KcsBmc.h" + +#define MAX_TEMP_DATA 160 + +// +// Structure of IPMI Command buffer +// +#define EFI_IPMI_COMMAND_HEADER_SIZE 2 + +typedef struct { + UINT8 Lun : 2; + UINT8 NetFunction : 6; + UINT8 Command; + UINT8 CommandData[MAX_TEMP_DATA - EFI_IPMI_COMMAND_HEADER_SIZE]; +} EFI_IPMI_COMMAND; + +// +// Structure of IPMI Command response buffer +// +#define EFI_IPMI_RESPONSE_HEADER_SIZE 2 + +typedef struct { + UINT8 Lun : 2; + UINT8 NetFunction : 6; + UINT8 Command; + UINT8 ResponseData[MAX_TEMP_DATA - EFI_IPMI_RESPONSE_HEADER_SIZE]; +} EFI_IPMI_RESPONSE; + + +#define IPMI_INSTANCE_INFO_HOB_GUID { \ + 0x38ee71f, 0x1c78, 0x4874, { 0xba, 0xe3, 0xf8, 0xa2, 0x57, 0x75, 0x28, 0= x52 } \ + } + +EFI_GUID mIpmiInstanceGuid =3D IPMI_INSTANCE_INFO_HOB_GUID; + +#define SM_IPMI_BMC_SIGNATURE SIGNATURE_32 ('i', 'p', 'm', 'i') +typedef UINT32 EFI_BMC_STATUS; +typedef struct { + UINTN Signature; + UINT64 KcsTimeoutPeriod; + UINT16 IpmiIoBase; + UINT8 SlaveAddress; + EFI_BMC_STATUS BmcStatus; + UINT64 ErrorStatus; + UINT8 SoftErrorCount; + UINT8 TempData[MAX_TEMP_DATA]; +} IPMI_INSTANCE; + +#define EFI_BMC_OK 0 +#define EFI_BMC_SOFTFAIL 1 +#define EFI_BMC_HARDFAIL 2 +#define EFI_BMC_UPDATE_IN_PROGRESS 3 +#define EFI_BMC_NOTREADY 4 + +EFI_STATUS +UpdateErrorStatus ( + IN UINT8 BmcError, + IPMI_INSTANCE *IpmiInstance + ) +/*++ + +Routine Description: + + Check if the completion code is a Soft Error and increment the count. T= he count + is not updated if the BMC is in Force Update Mode. + +Arguments: + + BmcError - Completion code to check + IpmiInstance - BMC instance data + +Returns: + + EFI_SUCCESS - Status + +--*/ +{ + UINT8 Errors[] =3D { + IPMI_COMP_CODE_NODE_BUSY, IPMI_COMP_CODE_TIMEOUT, IPMI_COMP_CODE_OUT_O= F_SPACE, IPMI_COMP_CODE_OUT_OF_RANGE, + IPMI_COMP_CODE_CMD_RESP_NOT_PROVIDED, IPMI_COMP_CODE_FAIL_DUP_REQUEST,= IPMI_COMP_CODE_SDR_REP_IN_UPDATE_MODE, + IPMI_COMP_CODE_DEV_IN_FW_UPDATE_MODE, IPMI_COMP_CODE_BMC_INIT_IN_PROGR= ESS, IPMI_COMP_CODE_UNSPECIFIED + }; + UINT16 CodeCount; + UINT8 i; + + CodeCount =3D sizeof (Errors) / sizeof (Errors[0]); + for (i =3D 0; i < CodeCount; i++) { + if (BmcError =3D=3D Errors[i]) { + // + // Don't change Bmc Status flag if the BMC is in Force Update Mode. + // + if (IpmiInstance->BmcStatus !=3D EFI_BMC_UPDATE_IN_PROGRESS) { + IpmiInstance->BmcStatus =3D EFI_BMC_SOFTFAIL; + } + + IpmiInstance->SoftErrorCount++; + break; + } + } + + return EFI_SUCCESS; +} + +VOID +UpdateBmcStatusOnResponse ( + IN IPMI_INSTANCE *IpmiInstance, + IN EFI_IPMI_COMMAND *IpmiCommand, + IN EFI_STATUS EfiStatus, + IN EFI_IPMI_RESPONSE *IpmiResponse + ) +{ + IPMI_GET_DEVICE_ID_RESPONSE *BmcInfo; + IPMI_SELF_TEST_RESULT_RESPONSE *TestResult; + + if ((IpmiCommand->NetFunction =3D=3D IPMI_NETFN_APP) && (IpmiCommand->Co= mmand =3D=3D IPMI_APP_GET_DEVICE_ID)) { + if (EFI_ERROR(EfiStatus)) { + IpmiInstance->BmcStatus =3D EFI_BMC_HARDFAIL; + } else { + BmcInfo =3D (VOID *)IpmiResponse->ResponseData; + if (BmcInfo->FirmwareRev1.Bits.UpdateMode) { + IpmiInstance->BmcStatus =3D EFI_BMC_UPDATE_IN_PROGRESS; + } + } + } else if ((IpmiCommand->NetFunction =3D=3D IPMI_NETFN_APP) && (IpmiComm= and->Command =3D=3D IPMI_APP_GET_DEVICE_ID)) { + if (EFI_ERROR(EfiStatus)) { + IpmiInstance->BmcStatus =3D EFI_BMC_HARDFAIL; + } else { + TestResult =3D (VOID *)IpmiResponse->ResponseData; + switch (TestResult->Result) { + case IPMI_APP_SELFTEST_NO_ERROR: + case IPMI_APP_SELFTEST_NOT_IMPLEMENTED: + IpmiInstance->BmcStatus =3D EFI_BMC_OK; + break; + case IPMI_APP_SELFTEST_ERROR: + // + // Three of the possible errors result in BMC hard failure; FRU Co= rruption, + // BootBlock Firmware corruption, and Operational Firmware Corrupt= ion. All + // other errors are BMC soft failures. + // + if ((TestResult->Param & (IPMI_APP_SELFTEST_FRU_CORRUPT | IPMI_APP= _SELFTEST_FW_BOOTBLOCK_CORRUPT | IPMI_APP_SELFTEST_FW_CORRUPT)) !=3D 0) { + IpmiInstance->BmcStatus =3D EFI_BMC_HARDFAIL; + } else { + IpmiInstance->BmcStatus =3D EFI_BMC_SOFTFAIL; + } + break; + + case IPMI_APP_SELFTEST_FATAL_HW_ERROR: + IpmiInstance->BmcStatus =3D EFI_BMC_HARDFAIL; + break; + + default: + break; + } + } + } +} + +/** + This service enables submitting commands via Ipmi. + + @param[in] NetFunction Net function of the command. + @param[in] Command IPMI Command. + @param[in] RequestData Command Request Data. + @param[in] RequestDataSize Size of Command Request Data. + @param[out] ResponseData Command Response Data. The completi= on code is the first byte of response data. + @param[in, out] ResponseDataSize Size of Command Response Data. + + @retval EFI_SUCCESS The command byte stream was successfully = submit to the device and a response was successfully received. + @retval EFI_NOT_FOUND The command was not successfully sent to = the device or a response was not successfully received from the device. + @retval EFI_NOT_READY Ipmi Device is not ready for Ipmi command= access. + @retval EFI_DEVICE_ERROR Ipmi Device hardware error. + @retval EFI_TIMEOUT The command time out. + @retval EFI_UNSUPPORTED The command was not successfully sent to = the device. + @retval EFI_OUT_OF_RESOURCES The resource allcation is out of resource= or data size error. +**/ +EFI_STATUS +EFIAPI +IpmiSubmitCommand ( + IN UINT8 NetFunction, + IN UINT8 Command, + IN UINT8 *RequestData, + IN UINT32 RequestDataSize, + OUT UINT8 *ResponseData, + IN OUT UINT32 *ResponseDataSize + ) +{ + UINT8 DataSize; + EFI_STATUS Status; + EFI_IPMI_COMMAND *IpmiCommand; + EFI_IPMI_RESPONSE *IpmiResponse; + VOID *Hob; + IPMI_INSTANCE *IpmiInstance; + + DEBUG ((DEBUG_INFO, "IpmiSubmitCommand\n")); + + Hob =3D GetFirstGuidHob (&mIpmiInstanceGuid); + if (Hob !=3D NULL) { + IpmiInstance =3D GET_GUID_HOB_DATA(Hob); + } else { + IpmiInstance =3D BuildGuidHob (&mIpmiInstanceGuid, sizeof(IPMI_INSTANC= E)); + ASSERT(IpmiInstance !=3D NULL); + if (IpmiInstance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + IpmiInstance->Signature =3D SM_IPMI_BMC_SIGNATURE; + IpmiInstance->KcsTimeoutPeriod =3D PcdGet64(PcdIpmiKcsTi= meoutPeriod);=20 + IpmiInstance->SlaveAddress =3D PcdGet8(PcdIpmiBmcSla= veAddress); + IpmiInstance->IpmiIoBase =3D PcdGet16(PcdIpmiIoBas= eAddress); + DEBUG((DEBUG_INFO,"IPMI KcsTimeoutPeriod=3D0x%x\n", IpmiInstance->KcsT= imeoutPeriod)); + DEBUG((DEBUG_INFO,"IPMI SlaveAddress=3D0x%x\n", IpmiInstance->SlaveAdd= ress)); + DEBUG((DEBUG_INFO,"IPMI IpmiIoBase=3D0x%x\n", IpmiInstance->IpmiIoBase= )); + + IpmiInstance->BmcStatus =3D EFI_BMC_NOTREADY; + IpmiInstance->ErrorStatus =3D 0x00; + IpmiInstance->SoftErrorCount =3D 0x00; + + MicroSecondDelay(10*1000); + + Status =3D PlatformIpmiIoRangeSet (IpmiInstance->IpmiIoBase); + DEBUG ((DEBUG_INFO, "IPMI PlatformIpmiIoRangeSet - %r!\n", Status)); + if (EFI_ERROR(Status)) { + return Status; + } + } + + IpmiCommand =3D (VOID *)IpmiInstance->TempData; + IpmiResponse =3D (VOID *)IpmiInstance->TempData; + + // + // Send IPMI command to BMC + // + IpmiCommand->Lun =3D 0; + IpmiCommand->NetFunction =3D NetFunction; + IpmiCommand->Command =3D Command; + + // + // Ensure that the buffer is valid before attempting to copy the command= data + // buffer into the IpmiCommand structure. + // + if (RequestDataSize > 0) { + if (RequestData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + CopyMem ( + IpmiCommand->CommandData, + RequestData, + RequestDataSize + ); + } + + Status =3D SendDataToBmcPort ( + IpmiInstance->KcsTimeoutPeriod, + IpmiInstance->IpmiIoBase, + (UINT8 *)IpmiCommand, + (UINT8)(RequestDataSize + EFI_IPMI_COMMAND_HEADER_SIZE) + ); + + if (Status !=3D EFI_SUCCESS) { + IpmiInstance->BmcStatus =3D EFI_BMC_SOFTFAIL; + IpmiInstance->SoftErrorCount++; + UpdateBmcStatusOnResponse (IpmiInstance, IpmiCommand, Status, NULL); + return Status; + } + + // + // Get Response to IPMI Command from BMC. + // + DataSize =3D MAX_TEMP_DATA; + Status =3D ReceiveBmcDataFromPort ( + IpmiInstance->KcsTimeoutPeriod, + IpmiInstance->IpmiIoBase, + (UINT8 *)IpmiResponse, + &DataSize + ); + + if (Status !=3D EFI_SUCCESS) { + IpmiInstance->BmcStatus =3D EFI_BMC_SOFTFAIL; + IpmiInstance->SoftErrorCount++; + UpdateBmcStatusOnResponse (IpmiInstance, IpmiCommand, Status, NULL); + return Status; + } + + // + // If we got this far without any error codes, but the DataSize is 0 the= n the=20 + // command response failed, so do not continue. =20 + // + if (DataSize < 3) { + Status =3D EFI_DEVICE_ERROR; + IpmiInstance->BmcStatus =3D EFI_BMC_SOFTFAIL; + IpmiInstance->SoftErrorCount++; + UpdateBmcStatusOnResponse (IpmiInstance, IpmiCommand, Status, NULL); + return Status; + } + + if ((IpmiResponse->ResponseData[0] !=3D IPMI_COMP_CODE_NORMAL) && + (IpmiInstance->BmcStatus =3D=3D EFI_BMC_UPDATE_IN_PROGRESS)) { + // + // If the completion code is not normal and the BMC is in Force Update + // mode, then update the error status and return EFI_UNSUPPORTED. + // + UpdateErrorStatus ( + IpmiResponse->ResponseData[0], + IpmiInstance + ); + UpdateBmcStatusOnResponse (IpmiInstance, IpmiCommand, Status, IpmiResp= onse); + return EFI_UNSUPPORTED; + } else if (IpmiResponse->ResponseData[0] !=3D IPMI_COMP_CODE_NORMAL) { + // + // Otherwise if the BMC is in normal mode, but the completion code + // is not normal, then update the error status and return device error. + // + UpdateErrorStatus ( + IpmiResponse->ResponseData[0], + IpmiInstance + ); + UpdateBmcStatusOnResponse (IpmiInstance, IpmiCommand, Status, IpmiResp= onse); + return EFI_DEVICE_ERROR; + } + + // + // Verify the response data buffer passed in is big enough. + // + if ((UINTN)(DataSize - EFI_IPMI_RESPONSE_HEADER_SIZE) > *ResponseDataSiz= e) { + return EFI_BUFFER_TOO_SMALL; + } + + // + // Copy data over to the response data buffer. + // + if ((ResponseData !=3D NULL) && (ResponseDataSize !=3D NULL) && (*Respon= seDataSize !=3D 0)) { + *ResponseDataSize =3D DataSize - EFI_IPMI_RESPONSE_HEADER_SIZE; + CopyMem ( + ResponseData, + IpmiResponse->ResponseData, + *ResponseDataSize + ); + } + IpmiInstance->BmcStatus =3D EFI_BMC_OK; + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLi= bKcs/IpmiLibKcs.inf b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Libra= ry/IpmiLibKcs/IpmiLibKcs.inf new file mode 100644 index 0000000000..239e115ad4 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/Ip= miLibKcs.inf @@ -0,0 +1,40 @@ +## @file +# Component description file for IPMI KCS Library. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D IpmiLibKcs + FILE_GUID =3D 9879DB3A-C2CD-4615-ACDA-95C1B2EC00B3 + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D IpmiLib + +[sources] + IpmiLibKcs.c + KcsBmc.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AdvancedFeaturePkg/AdvancedFeaturePkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + HobLib + PcdLib + TimerLib + IoLib + IpmiPlatformHookLib + +[Pcd] + gEfiIpmiPkgTokenSpaceGuid.PcdIpmiKcsTimeoutPeriod + gEfiIpmiPkgTokenSpaceGuid.PcdIpmiBmcSlaveAddress + gAdvancedFeaturePkgTokenSpaceGuid.PcdIpmiIoBaseAddress \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLi= bKcs/KcsBmc.c b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/Ipm= iLibKcs/KcsBmc.c new file mode 100644 index 0000000000..483843c6da --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/Kc= sBmc.c @@ -0,0 +1,485 @@ +/** @file + KCS Transport Hook. + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "KcsBmc.h" +#include + +EFI_STATUS +KcsErrorExit ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort + ) +/*++ + +Routine Description: + + Check the KCS error status + +Arguments: + =20 + KcsPort - The base port of KCS + +Returns: + + EFI_DEVICE_ERROR - The device error happened + EFI_SUCCESS - Successfully check the KCS error status + +--*/ +{ + EFI_STATUS Status; + UINT8 KcsData; + EFI_KCS_STATUS KcsStatus; + UINT8 BmcStatus; + UINT8 RetryCount; + UINT64 TimeOut; + + TimeOut =3D 0; + RetryCount =3D 0; + while (RetryCount < KCS_ABORT_RETRY_COUNT) { + + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData =3D IoRead8 (KcsPort + 1); + if (KcsStatus.RawData =3D=3D 0xFF || (TimeOut >=3D KcsTimeoutPeriod)= ) { + RetryCount =3D KCS_ABORT_RETRY_COUNT; + break; + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + if (RetryCount >=3D KCS_ABORT_RETRY_COUNT) { + break; + } + + KcsData =3D KCS_ABORT; + IoWrite8 ((KcsPort + 1), KcsData); + + TimeOut =3D 0; + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData =3D IoRead8 (KcsPort + 1); + if (KcsStatus.RawData =3D=3D 0xFF || (TimeOut >=3D KcsTimeoutPeriod)= ) { + Status =3D EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + KcsData =3D IoRead8 (KcsPort); + + KcsData =3D 0x0; + IoWrite8 (KcsPort, KcsData); + + TimeOut =3D 0;=09 + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData =3D IoRead8 (KcsPort + 1); + if (KcsStatus.RawData =3D=3D 0xFF || (TimeOut >=3D KcsTimeoutPeriod)= ) { + Status =3D EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + if (KcsStatus.Status.State =3D=3D KcsReadState) { + TimeOut =3D 0;=09 + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData =3D IoRead8 (KcsPort + 1); + if (KcsStatus.RawData =3D=3D 0xFF || (TimeOut >=3D KcsTimeoutPerio= d)) { + Status =3D EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (!KcsStatus.Status.Obf); + + BmcStatus =3D IoRead8 (KcsPort); + + KcsData =3D KCS_READ; + IoWrite8 (KcsPort, KcsData); + + TimeOut =3D 0; + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData =3D IoRead8 (KcsPort + 1); + if (KcsStatus.RawData =3D=3D 0xFF || (TimeOut >=3D KcsTimeoutPerio= d)) { + Status =3D EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + if (KcsStatus.Status.State =3D=3D KcsIdleState) { + TimeOut =3D 0; + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData =3D IoRead8 (KcsPort + 1); + if (KcsStatus.RawData =3D=3D 0xFF || (TimeOut >=3D KcsTimeoutPer= iod)) { + Status =3D EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (!KcsStatus.Status.Obf); + + KcsData =3D IoRead8 (KcsPort); + break; + + } else { + RetryCount++; + continue; + } + + } else { + RetryCount++; + continue; + } + } + + if (RetryCount >=3D KCS_ABORT_RETRY_COUNT) { + Status =3D EFI_DEVICE_ERROR; + goto LabelError; + } + + return EFI_SUCCESS; + +LabelError: + + return Status; +} + +EFI_STATUS +KcsCheckStatus ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + KCS_STATE KcsState, + BOOLEAN *Idle + ) +/*++ + +Routine Description: + + Ckeck KCS status + +Arguments: + + KcsPort - The base port of KCS + KcsState - The state of KCS to be checked + Idle - If the KCS is idle + +Returns: + + EFI_SUCCESS - Checked the KCS status successfully + +--*/ +{ + EFI_STATUS Status =3D 0; + EFI_KCS_STATUS KcsStatus =3D { 0 }; + UINT8 KcsData =3D 0; + UINT64 TimeOut =3D 0; + =20 + if(Idle =3D=3D NULL ){=20 + return EFI_INVALID_PARAMETER; + } +=09 + *Idle =3D FALSE; + =20 + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData =3D IoRead8 (KcsPort + 1); + if (KcsStatus.RawData =3D=3D 0xFF || (TimeOut >=3D KcsTimeoutPeriod)) { + Status =3D EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + if (KcsState =3D=3D KcsWriteState) { + KcsData =3D IoRead8 (KcsPort); + } + + if (KcsStatus.Status.State !=3D KcsState) { + if ((KcsStatus.Status.State =3D=3D KcsIdleState) && (KcsState =3D=3D K= csReadState)) { + *Idle =3D TRUE; + } else { + Status =3D KcsErrorExit (KcsTimeoutPeriod, KcsPort); + goto LabelError; + } + } + + if (KcsState =3D=3D KcsReadState) { + TimeOut =3D 0; + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData =3D IoRead8 (KcsPort + 1); + if (KcsStatus.RawData =3D=3D 0xFF || (TimeOut >=3D KcsTimeoutPeriod)= ) { + Status =3D EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (!KcsStatus.Status.Obf); + } + + if (KcsState =3D=3D KcsWriteState || Idle) { + KcsData =3D IoRead8 (KcsPort); + } + + return EFI_SUCCESS; + +LabelError: + + return Status; +} + +EFI_STATUS +SendDataToBmc ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 DataSize + ) +/*++ + +Routine Description: + + Send data to BMC + +Arguments: + + Data - The data pointer to be sent + DataSize - The data size + +Returns: + + EFI_SUCCESS - Send out the data successfully + +--*/ +{ + EFI_KCS_STATUS KcsStatus; + UINT8 KcsData; + UINT16 KcsIoBase; + EFI_STATUS Status; + UINT8 i; + BOOLEAN Idle; + UINT64 TimeOut =3D 0; + + DEBUG ((DEBUG_INFO, "SendDataToBmc (%ld, 0x%x) - ", KcsTimeoutPeriod, Kc= sPort)); + for (i =3D 0; i < DataSize; i++) { + DEBUG ((DEBUG_INFO, "%02x ", Data[i])); + } + DEBUG ((DEBUG_INFO, "\n")); + + KcsIoBase =3D KcsPort; + + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData =3D IoRead8 (KcsIoBase + 1); + if ((KcsStatus.RawData =3D=3D 0xFF) || (TimeOut >=3D KcsTimeoutPeriod)) + { + if ((Status =3D KcsErrorExit (KcsTimeoutPeriod, KcsIoBase)) !=3D EFI= _SUCCESS) + { + DEBUG ((DEBUG_INFO, "KcsErrorExit - %r\n", Status)); + return Status; + } + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + KcsData =3D KCS_WRITE_START; + IoWrite8 ((KcsIoBase + 1), KcsData); + if ((Status =3D KcsCheckStatus (KcsTimeoutPeriod, KcsIoBase, KcsWriteSta= te, &Idle)) !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_INFO, "KcsCheckStatus 1 - %r\n", Status)); + return Status; + } + + for (i =3D 0; i < DataSize; i++) { + if (i =3D=3D (DataSize - 1)) { + if ((Status =3D KcsCheckStatus (KcsTimeoutPeriod, KcsIoBase, KcsWrit= eState, &Idle)) !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_INFO, "KcsCheckStatus 2 - %r\n", Status)); + return Status; + } + + KcsData =3D KCS_WRITE_END; + IoWrite8 ((KcsIoBase + 1), KcsData); + } + + Status =3D KcsCheckStatus (KcsTimeoutPeriod, KcsIoBase, KcsWriteState,= &Idle); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "KcsCheckStatus 3 - %r\n", Status)); + return Status; + } + + IoWrite8 (KcsIoBase, Data[i]); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +ReceiveBmcData ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 *DataSize + ) +/*++ + +Routine Description: + + Routine Description: + + Receive data from BMC + +Arguments: + + Data - The buffer pointer + DataSize - The buffer size + +Returns: + + EFI_SUCCESS - Received data successfully + +--*/ +{ + UINT8 KcsData; + UINT16 KcsIoBase; + EFI_STATUS Status; + BOOLEAN Idle; + UINT8 Count; + + Count =3D 0; + KcsIoBase =3D KcsPort; + + DEBUG ((DEBUG_INFO, "ReceiveBmcData (%ld, 0x%x)...\n", KcsTimeoutPeriod,= KcsPort)); + + while (TRUE) { + + if ((Status =3D KcsCheckStatus (KcsTimeoutPeriod, KcsIoBase, KcsReadSt= ate, &Idle)) !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_INFO, "KcsCheckStatus - %r\n", Status)); + return Status; + } + + if (Idle) { + DEBUG ((DEBUG_INFO, "DataSize - 0x%x\n", Count)); + *DataSize =3D Count; + break; + } + + if (Count > *DataSize) { + DEBUG ((DEBUG_INFO, "ERROR: Count(0x%x) > *DataSize(0x%x)\n", Count,= *DataSize)); + return EFI_DEVICE_ERROR; + } + + Data[Count] =3D IoRead8 (KcsIoBase); + + Count++; + + KcsData =3D KCS_READ; + IoWrite8 (KcsIoBase, KcsData); + } + + DEBUG ((DEBUG_INFO, "ReceiveBmcData (%ld, 0x%x) - ", KcsTimeoutPeriod, K= csPort)); + for (Count =3D 0; Count < *DataSize; Count++) { + DEBUG ((DEBUG_INFO, "%02x ", Data[Count])); + } + DEBUG ((DEBUG_INFO, "\n")); + + return EFI_SUCCESS; +} + +EFI_STATUS +ReceiveBmcDataFromPort ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 *DataSize + ) +/*++ + +Routine Description: + + Receive data from BMC + +Arguments: + + Data - The buffer pointer to receive data + DataSize - The buffer size + +Returns: + + EFI_SUCCESS - Received the data successfully + +--*/ +{ + EFI_STATUS Status; + UINT16 KcsIoBase; + UINT8 i; + UINT8 MyDataSize; + + MyDataSize =3D *DataSize; + + KcsIoBase =3D KcsPort; + + for (i =3D 0; i < KCS_ABORT_RETRY_COUNT; i++) { + Status =3D ReceiveBmcData (KcsTimeoutPeriod, KcsIoBase, Data, DataSize= ); + if (EFI_ERROR (Status)) { + if ((Status =3D KcsErrorExit (KcsTimeoutPeriod, KcsIoBase)) !=3D EFI= _SUCCESS) { + return Status; + } + + *DataSize =3D MyDataSize; + } else { + return Status; + } + } + + return EFI_DEVICE_ERROR; +} + +EFI_STATUS +SendDataToBmcPort ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 DataSize + ) +/*++ + +Routine Description: + + Send data to BMC + +Arguments: + + Data - The data pointer to be sent + DataSize - The data size + +Returns: + + EFI_SUCCESS - Send out the data successfully + +--*/ +{ + EFI_STATUS Status; + UINT16 KcsIoBase; + UINT8 i; + + KcsIoBase =3D KcsPort; + + for (i =3D 0; i < KCS_ABORT_RETRY_COUNT; i++) { + Status =3D SendDataToBmc (KcsTimeoutPeriod, KcsIoBase, Data, DataSize); + if (EFI_ERROR (Status)) { + if ((Status =3D KcsErrorExit (KcsTimeoutPeriod, KcsIoBase)) !=3D EFI= _SUCCESS) { + return Status; + } + } else { + return Status; + } + } + + return EFI_DEVICE_ERROR; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLi= bKcs/KcsBmc.h b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/Ipm= iLibKcs/KcsBmc.h new file mode 100644 index 0000000000..bf8ae6b63d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/Kc= sBmc.h @@ -0,0 +1,208 @@ +/** @file + KCS Transport Hook head file. + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_KCS_BMC_H +#define _EFI_KCS_BMC_H + +#include +#include +#include + +#define KCS_WRITE_START 0x61 +#define KCS_WRITE_END 0x62 +#define KCS_READ 0x68 +#define KCS_GET_STATUS 0x60 +#define KCS_ABORT 0x60 +#define KCS_DELAY_UNIT 50 // [s] Each KSC IO delay + +#define KCS_ABORT_RETRY_COUNT 1 + +typedef enum { + KcsIdleState, + KcsReadState, + KcsWriteState, + KcsErrorState +} KCS_STATE; + +typedef union { + UINT8 RawData; + struct { + UINT8 Obf : 1; + UINT8 Ibf : 1; + UINT8 SmAtn : 1; + UINT8 CD : 1; + UINT8 Oem1 : 1; + UINT8 Oem2 : 1; + UINT8 State : 2; + } Status; +} EFI_KCS_STATUS; + + +// +//External Fucntion List +// +EFI_STATUS +SendDataToBmcPort ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 DataSize + ) +/*++ + +Routine Description: + + Send data to BMC + +Arguments: + + Data - The data pointer to be sent + DataSize - The data size + +Returns: + + EFI_SUCCESS - Send out the data successfully + +--*/ +; + +EFI_STATUS +ReceiveBmcDataFromPort ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 *DataSize + ) +/*++ + +Routine Description: + + Routine Description: + + Receive data from BMC + +Arguments: + + Data - The buffer pointer + DataSize - The buffer size + +Returns: + + EFI_SUCCESS - Received data successfully + +--*/ +; + +// +//Internal Fucntion List +// +EFI_STATUS +KcsErrorExit ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort + ) +/*++ + +Routine Description: + + Check the KCS error status + +Arguments: + =20 + KcsPort - The base port of KCS + +Returns: + + EFI_DEVICE_ERROR - The device error happened + EFI_SUCCESS - Successfully check the KCS error status + +--*/ +; + +EFI_STATUS +KcsCheckStatus ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + KCS_STATE KcsState, + BOOLEAN *Idle + ) +/*++ + +Routine Description: + + Ckeck KCS status + +Arguments: + + KcsPort - The base port of KCS + KcsState - The state of KCS to be checked + Idle - If the KCS is idle + Context - The context for this operation + +Returns: + + EFI_SUCCESS - Checked the KCS status successfully + +--*/ +; + + +EFI_STATUS +SendDataToBmc ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 DataSize + ) +/*++ + +Routine Description: + + Send data to BMC + +Arguments: + + Data - The data pointer to be sent + DataSize - The data size + +Returns: + + EFI_SUCCESS - Send out the data successfully + +--*/ +; + + +EFI_STATUS +ReceiveBmcData ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 *DataSize + ) +/*++ + +Routine Description: + + Routine Description: + + Receive data from BMC + +Arguments: + + Data - The buffer pointer + DataSize - The buffer size + +Returns: + + EFI_SUCCESS - Received data successfully + +--*/ +; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPl= atformHookLib/IpmiPlatformHookLib.c b/Platform/Intel/PurleyOpenBoardPkg/Fea= tures/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c new file mode 100644 index 0000000000..1cdd39c79a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformH= ookLib/IpmiPlatformHookLib.c @@ -0,0 +1,39 @@ +/** @file + IPMI platform hook. + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +// +// Prototype definitions for IPMI Platform Update Library +// + +EFI_STATUS +EFIAPI +PlatformIpmiIoRangeSet( + UINT16 IpmiIoBase +) +/*++ + + Routine Description: + + This function sets IPMI Io range + + Arguments: + + IpmiIoBase + + Returns: + + Status + +--*/ +{ + return PchLpcGenIoRangeSet((IpmiIoBase & 0xFF0), 0x10, LPC_ESPI_FIRST_SL= AVE); +} \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPl= atformHookLib/IpmiPlatformHookLib.inf b/Platform/Intel/PurleyOpenBoardPkg/F= eatures/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf new file mode 100644 index 0000000000..94ab840a02 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformH= ookLib/IpmiPlatformHookLib.inf @@ -0,0 +1,28 @@ +## @file +# Component description file for IPMI platform hook Library. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D IpmiPlatformHookLib + FILE_GUID =3D E886B3EA-AAF3-4804-810C-C8F69897C580 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D IpmiPlatformHookLib + +[sources] + IpmiPlatformHookLib.c + +[Packages] + MdePkg/MdePkg.dec + AdvancedFeaturePkg/AdvancedFeaturePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[LibraryClasses] + DebugLib + PchCycleDecodingLib diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvs.asi b= /Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvs.asi new file mode 100644 index 0000000000..3e049cca8e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvs.asi @@ -0,0 +1,282 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // + // BIOS parameter BIOS_ACPI_PARAM + // + OperationRegion (PSYS, SystemMemory, 0x30584946, 0x400) // (FIX0 - Patch= ed by ACPI Platform Driver during POST) + Field (PSYS, ByteAcc, NoLock, Preserve) { + // IOAPIC Start + PLAT , 32, // Platform ID + Offset (0x04), //=20 +#if MAX_SOCKET > 4 + AP00 , 1, // PC00 IOAPIC Enable + AP01 , 1, // PC01 IOAPIC Enable + AP02 , 1, // PC02 IOAPIC Enable + AP03 , 1, // PC03 IOAPIC Enable + AP04 , 1, // PC04 IOAPIC Enable + AP05 , 1, // PC05 IOAPIC Enable + AP06 , 1, // PC06 IOAPIC Enable + AP07 , 1, // PC07 IOAPIC Enable + AP08 , 1, // PC08 IOAPIC Enable + AP09 , 1, // PC09 IOAPIC Enable + AP10 , 1, // PC10 IOAPIC Enable + AP11 , 1, // PC11 IOAPIC Enable + AP12 , 1, // PC12 IOAPIC Enable + AP13 , 1, // PC13 IOAPIC Enable + AP14 , 1, // PC14 IOAPIC Enable + AP15 , 1, // PC15 IOAPIC Enable + AP16 , 1, // PC16 IOAPIC Enable + AP17 , 1, // PC17 IOAPIC Enable + AP18 , 1, // PC18 IOAPIC Enable + AP19 , 1, // PC19 IOAPIC Enable + AP20 , 1, // PC20 IOAPIC Enable + AP21 , 1, // PC21 IOAPIC Enable + AP22 , 1, // PC22 IOAPIC Enable + AP23 , 1, // PC23 IOAPIC Enable + AP24 , 1, // PC24 IOAPIC Enable + AP25 , 1, // 8S PC25 IOAPIC Enable + AP26 , 1, // 8S PC26 IOAPIC Enable + AP27 , 1, // 8S PC27 IOAPIC Enable + AP28 , 1, // 8S PC28 IOAPIC Enable + AP29 , 1, // 8S PC29 IOAPIC Enable + AP30 , 1, // 8S PC30 IOAPIC Enable + AP31 , 1, // 8S PC31 IOAPIC Enable +#else + APC0 , 1, // PCH IOAPIC Enable + AP00 , 1, // PC00 IOAPIC Enable + AP01 , 1, // PC01 IOAPIC Enable + AP02 , 1, // PC02 IOAPIC Enable + AP03 , 1, // PC03 IOAPIC Enable + AP04 , 1, // PC04 IOAPIC Enable + AP05 , 1, // PC05 IOAPIC Enable + AP06 , 1, // PC06 IOAPIC Enable + AP07 , 1, // PC07 IOAPIC Enable + AP08 , 1, // PC08 IOAPIC Enable + AP09 , 1, // PC09 IOAPIC Enable + AP10 , 1, // PC10 IOAPIC Enable + AP11 , 1, // PC11 IOAPIC Enable + AP12 , 1, // PC12 IOAPIC Enable + AP13 , 1, // PC13 IOAPIC Enable + AP14 , 1, // PC14 IOAPIC Enable + AP15 , 1, // PC15 IOAPIC Enable + AP16 , 1, // PC16 IOAPIC Enable + AP17 , 1, // PC17 IOAPIC Enable + AP18 , 1, // PC18 IOAPIC Enable + AP19 , 1, // PC19 IOAPIC Enable + AP20 , 1, // PC20 IOAPIC Enable + AP21 , 1, // PC21 IOAPIC Enable + AP22 , 1, // PC22 IOAPIC Enable + AP23 , 1, // PC23 IOAPIC Enable + RESA , 7, // Unused +#endif + Offset (0x08), + SKOV , 1, // Override ApicId socket field + , 7, // Unused + // IOAPIC End + + // Power Managment Start + Offset (0x09), + , 1, //=20 + CSEN , 1, // C State Enable + C3EN , 1, // OS C3 Report Enbale + C6EN , 1, // C6 Enable + C7EN , 1, // C7 Enable + MWOS , 1, // MWAIT support Enable + PSEN , 1, // P State Enable + EMCA , 1, // EMCA Enable + Offset (0x0A), + HWAL , 2, // PSD HW_ALL Enable + KPRS , 1, // KB present Flag + MPRS , 1, // Mouse present Flag + TSEN , 1, // T State Enable Flag + FGTS , 1, // Fine grained T state Flag + OSCX , 1, // OS C States + RESX , 1, // Unused + // Power Management End + + // RAS Start + Offset (0x0B), + CPHP , 8, // Bit field for determining CPU hotplug event is happ= ening, Update every time CPU Hotpug event is registered as valid + // Bit0 CPU0 O*L Request=20 + // Bit1 CPU1 O*L Request + // Bit2 CPU2 O*L Request + // Bit3 CPU3 O*L Request + // Bit4-7 Reserved + IIOP , 8, // Bit field for determining IIO hotplug event is happ= ening, Update every time IIO Hotpug event is registered as valid + // Bit0 IIO1 O*L Request + // Bit1 IIO2 O*L Request + // Bit2 IIO3 O*L Request + // Bit3-7 Reserved + IIOH , 64, // IIO bit Mask, what IIOs are present for STA method,= Update every time IIO hotplug event happens and at boot time (Patched by A= CPI Platform Driver during POST) + PRBM , 32, // Processor Bit mask, what sockets are present for ST= A method, Update every time hotplug event happen and at boot time (Patched = by ACPI Platform Driver during POST) + P0ID , 32, // Processor 0 APIC ID base + P1ID , 32, // Processor 1 APIC ID base + P2ID , 32, // Processor 2 APIC ID base + P3ID , 32, // Processor 3 APIC ID base + P4ID , 32, // Processor 4 APIC ID base + P5ID , 32, // Processor 5 APIC ID base + P6ID , 32, // Processor 6 APIC ID base + P7ID , 32, // Processor 7 APIC ID base + P0BM , 64, // Processor 0 Bit mask, what cores are present for ST= A method=20 + P1BM , 64, // Processor 1 Bit mask, what cores are present for ST= A method=20 + P2BM , 64, // Processor 2 Bit mask, what cores are present for ST= A method=20 + P3BM , 64, // Processor 3 Bit mask, what cores are present for ST= A method=20 + P4BM , 64, // Processor 4 Bit mask, what cores are present for ST= A method=20 + P5BM , 64, // Processor 5 Bit mask, what cores are present for ST= A method=20 + P6BM , 64, // Processor 6 Bit mask, what cores are present for ST= A method=20 + P7BM , 64, // Processor 7 Bit mask, what cores are present for ST= A method=20 + MEBM , 16, // Memory controller bit mask what memory controllers = are present, for STA Method + MEBC , 16, // Memory controller change event mask what memory con= trollers have been changed, for notify + CFMM , 32, // MMCFG Base + TSSZ , 32, // TSEG Size. + M0BS , 64, // Memory Controller Base 0 + M1BS , 64, // Memory Controller Base 1 + M2BS , 64, // Memory Controller Base 2 + M3BS , 64, // Memory Controller Base 3 + M4BS , 64, // Memory Controller Base 4 + M5BS , 64, // Memory Controller Base 5 + M6BS , 64, // Memory Controller Base 6 + M7BS , 64, // Memory Controller Base 7 + M0RN , 64, // Memory Controller Range 0 + M1RN , 64, // Memory Controller Range 1 + M2RN , 64, // Memory Controller Range 2 + M3RN , 64, // Memory Controller Range 3 + M4RN , 64, // Memory Controller Range 4 + M5RN , 64, // Memory Controller Range 5 + M6RN , 64, // Memory Controller Range 6 + M7RN , 64, // Memory Controller Range 7 + SMI0 , 32, // Parameter0 used for faked SMI request + SMI1 , 32, // Parameter1 used for faked SMI request + SMI2 , 32, // Parameter2 used for faked SMI request + SMI3 , 32, // Parameter3 used for faked SMI request + SCI0 , 32, // Parameter0 used for faked SCI request + SCI1 , 32, // Parameter1 used for faked SCI request + SCI2 , 32, // Parameter2 used for faked SCI request + SCI3 , 32, // Parameter3 used for faked SCI request + MADD , 64, // Migration ActionRegion GAS address. (Migration supp= ort written for 8 CPU socket system. In a 4 socket system, CPU4-7 and MEM8-= 15 are invalid.) + CUU0 , 128, // CPU0 UUID + CUU1 , 128, // CPU1 UUID + CUU2 , 128, // CPU2 UUID + CUU3 , 128, // CPU3 UUID + CUU4 , 128, // CPU4 UUID + CUU5 , 128, // CPU5 UUID + CUU6 , 128, // CPU6 UUID + CUU7 , 128, // CPU7 UUID + CPSP , 8, // CPU spare bitmap. 1 =3D=3D IsSpare. + ME00 , 128, // MEM0 UUID + ME01 , 128, // MEM1 UUID + ME10 , 128, // MEM2 UUID + ME11 , 128, // MEM3 UUID + ME20 , 128, // MEM4 UUID + ME21 , 128, // MEM5 UUID + ME30 , 128, // MEM6 UUID + ME31 , 128, // MEM7 UUID + ME40 , 128, // MEM8 UUID + ME41 , 128, // MEM9 UUID + ME50 , 128, // MEM10 UUID + ME51 , 128, // MEM11 UUID + ME60 , 128, // MEM12 UUID + ME61 , 128, // MEM13 UUID + ME70 , 128, // MEM14 UUID + ME71 , 128, // MEM15 UUID + MESP , 16, // Memory module spare bitmap. 1 =3D=3D IsSpare. + LDIR , 64, // L1 Directory Address + PRID , 32, // Processor ID + AHPE , 8, // ACPI PCIe hot plug enable. + // RAS End + + // VTD Start + DHRD , 192, // DHRD + ATSR , 192, // ATSR + RHSA , 192, // RHSA + // VTD End + + // BIOS Guard Start + CNBS , 8, // CPU SKU number bit shift + // BIOS Guard End + + // USB3 Start + XHMD , 8, // copy of setup item PchUsb30Mode + SBV1 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#1) + SBV2 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#2) + // USB3 End =20 + + // HWPM Start + , 2, // HWPM State Enable option from setup + , 1, // Aunomous C-state Enable option from setup + HWPI , 1, // HWP Interrupt + , 4, // Reserved bits + // HWPM End + + // PCIe Multi-Seg Start + BB00 , 8, // Bus Base for PC00 + BB01 , 8, // Bus Base for PC01 + BB02 , 8, // Bus Base for PC02 + BB03 , 8, // Bus Base for PC03 + BB04 , 8, // Bus Base for PC04 + BB05 , 8, // Bus Base for PC05 + BB06 , 8, // Bus Base for PC06 + BB07 , 8, // Bus Base for PC07 + BB08 , 8, // Bus Base for PC08 + BB09 , 8, // Bus Base for PC09 + BB10 , 8, // Bus Base for PC10 + BB11 , 8, // Bus Base for PC11 + BB12 , 8, // Bus Base for PC12 + BB13 , 8, // Bus Base for PC13 + BB14 , 8, // Bus Base for PC14 + BB15 , 8, // Bus Base for PC15 + BB16 , 8, // Bus Base for PC16 + BB17 , 8, // Bus Base for PC17 + BB18 , 8, // Bus Base for PC18 + BB19 , 8, // Bus Base for PC19 + BB20 , 8, // Bus Base for PC20 + BB21 , 8, // Bus Base for PC21 + BB22 , 8, // Bus Base for PC22 + BB23 , 8, // Bus Base for PC23 + BB24 , 8, // Bus Base for PC24 + BB25 , 8, // Bus Base for PC25 + BB26 , 8, // Bus Base for PC26 + BB27 , 8, // Bus Base for PC27 + BB28 , 8, // Bus Base for PC28 + BB29 , 8, // Bus Base for PC29 + BB30 , 8, // Bus Base for PC30 + BB31 , 8, // Bus Base for PC31 + BB32 , 8, // Bus Base for PC32 + BB33 , 8, // Bus Base for PC33 + BB34 , 8, // Bus Base for PC34 + BB35 , 8, // Bus Base for PC35 + BB36 , 8, // Bus Base for PC36 + BB37 , 8, // Bus Base for PC37 + BB38 , 8, // Bus Base for PC38 + BB39 , 8, // Bus Base for PC39 + BB40 , 8, // Bus Base for PC40 + BB41 , 8, // Bus Base for PC41 + BB42 , 8, // Bus Base for PC42 + BB43 , 8, // Bus Base for PC43 + BB44 , 8, // Bus Base for PC44 + BB45 , 8, // Bus Base for PC45 + BB46 , 8, // Bus Base for PC46 + BB47 , 8, // Bus Base for PC47 + SGEN , 8, // PCIe_MultiSeg_Support enable/disable + SG00 , 8, // Segment ID for Segment Group 0 + SG01 , 8, // Segment ID for Segment Group 1 + SG02 , 8, // Segment ID for Segment Group 2 + SG03 , 8, // Segment ID for Segment Group 3 + SG04 , 8, // Segment ID for Segment Group 4 + SG05 , 8, // Segment ID for Segment Group 5 + SG06 , 8, // Segment ID for Segment Group 6 + SG07 , 8, // Segment ID for Segment Group 7 + // PCIe Multi-Seg End + + // Performance start =20 + CLOD , 8, // SncAnd2Cluster, i.e. 1=3DSNC enable and 2 Clusters,= 0 otherwise =20 + // Performance End + =20 + } + + =20 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvsAreaDe= f.h b/Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h new file mode 100644 index 0000000000..8af401de99 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h @@ -0,0 +1,128 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_GLOBAL_NVS_AREA_H_ +#define _EFI_GLOBAL_NVS_AREA_H_ + +// +// Global NVS Area definition +// +#pragma pack (1) + +typedef struct { + // IOAPIC Start + UINT32 PlatformId; + UINT32 IoApicEnable; + UINT8 ApicIdOverrided :1; + UINT8 RES0 :7; =20 + // IOAPIC End + + // Power Management Start + UINT8 Rsvd_Pms_0 :1; + UINT8 CStateEnable :1; + UINT8 C3Enable :1; + UINT8 C6Enable :1; + UINT8 C7Enable :1; + UINT8 MonitorMwaitEnable :1; + UINT8 PStateEnable :1; + UINT8 EmcaEn :1; + UINT8 HWAllEnable :2; + UINT8 KBPresent :1; + UINT8 MousePresent :1; + UINT8 TStateEnable :1; + UINT8 TStateFineGrained: 1; + UINT8 OSCX :1; + UINT8 RESX :1; =20 + // Power Management End + + // RAS Start + UINT8 CpuChangeMask; + UINT8 IioChangeMask; + UINT64 IioPresentBitMask; + UINT32 SocketBitMask; //make sure this is at 4byte boundary + UINT32 ProcessorApicIdBase[8]; + UINT64 ProcessorBitMask[8]; + UINT16 MemoryBoardBitMask; + UINT16 MemoryBoardChgEvent; + UINT32 MmCfg; + UINT32 TsegSize; + UINT64 MemoryBoardBase[8]; + UINT64 MemoryBoardRange[8]; + UINT32 SmiRequestParam[4]; + UINT32 SciRequestParam[4]; + UINT64 MigrationActionRegionAddress; + UINT8 Cpu0Uuid[16]; + UINT8 Cpu1Uuid[16];=20 + UINT8 Cpu2Uuid[16];=20 + UINT8 Cpu3Uuid[16];=20 + UINT8 Cpu4Uuid[16]; + UINT8 Cpu5Uuid[16];=20 + UINT8 Cpu6Uuid[16];=20 + UINT8 Cpu7Uuid[16];=20 + UINT8 CpuSpareMask; =20 + UINT8 Mem0Uuid[16]; =20 + UINT8 Mem1Uuid[16];=20 + UINT8 Mem2Uuid[16];=20 + UINT8 Mem3Uuid[16];=20 + UINT8 Mem4Uuid[16]; =20 + UINT8 Mem5Uuid[16];=20 + UINT8 Mem6Uuid[16];=20 + UINT8 Mem7Uuid[16];=20 + UINT8 Mem8Uuid[16]; =20 + UINT8 Mem9Uuid[16];=20 + UINT8 Mem10Uuid[16];=20 + UINT8 Mem11Uuid[16];=20 + UINT8 Mem12Uuid[16]; =20 + UINT8 Mem13Uuid[16];=20 + UINT8 Mem14Uuid[16];=20 + UINT8 Mem15Uuid[16];=20 + UINT16 MemSpareMask; + UINT64 EmcaL1DirAddr; + UINT32 ProcessorId; + UINT8 PcieAcpiHotPlugEnable; + // RAS End + + // VTD Start + UINT64 DrhdAddr[3]; =20 + UINT64 AtsrAddr[3]; =20 + UINT64 RhsaAddr[3]; + // VTD End + =20 + // BIOS Guard Start + UINT8 CpuSkuNumOfBitShift; + // BIOS Guard End + =20 + // USB3 Start + UINT8 XhciMode; + UINT8 HostAlertVector1; + UINT8 HostAlertVector2; + // USB3 End + =20 + // HWPM Start + UINT8 HWPMEnable:2; //HWPM + UINT8 AutoCstate:1; //HWPM + UINT8 HwpInterrupt:1; //HWP Interrupt + UINT8 RES1:4; //reserved bits + // HWPM End + + // PCIe Multi-Seg Start + // for 8S support needs max 32 IIO IOxAPIC being enabled! + UINT8 BusBase[48]; // MAX_SOCKET * MAX_IIO_STACK. Note: hardcode du= e to ASL constraint.=20 + UINT8 PCIe_MultiSeg_Support; // Enable /Disable switch + // for 8S support needs matching to MAX_SOCKET! + UINT8 PcieSegNum[8]; // Segment number array. Must match MAX_SOCKET.= Note: hardcode due to ASL constraint. + // PCIe Multi-seg end + + // Performance Start + UINT8 SncAnd2Cluster; //1=3DSncEn and NumCluster=3D2, otherw= ise 0 =20 + // Performance End + + } BIOS_ACPI_PARAM; + +#pragma pack () + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h= b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h new file mode 100644 index 0000000000..79b7429052 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h @@ -0,0 +1,414 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCH_RC_CONFIG_DATA_H__ +#define __PCH_RC_CONFIG_DATA_H__ + +#include +#define HDAUDIO_FEATURES 3 +#define HDAUDIO_PP_MODULES 2 + + +/// sSATA max ports for Wellsburg +#define PCH_SSATA_MAX_PORTS 6 + +#pragma pack(1) +typedef struct { + + UINT8 BiosGuard; + UINT8 Dwr_Enable; + UINT8 Dwr_Stall; + UINT8 Dwr_BmcRootPort; + + UINT8 DwrEn_PMCGBL; + UINT8 DwrEn_CPUTHRM; + UINT8 DwrEn_PCHTHRM; + UINT8 DwrEn_PBO; + UINT8 DwrEn_MEPBO; + UINT8 DwrEn_MEWDT; + UINT8 DwrEn_MEGBL; + UINT8 DwrEn_CTWDT; + UINT8 DwrEn_PMCWDT; + UINT8 DwrEn_ME_UERR; + UINT8 DwrEn_SYSPWR; + UINT8 DwrEn_OCWDT; + UINT8 DwrEn_IEPBO; + UINT8 DwrEn_IEWDT; + UINT8 DwrEn_IEGBLN; + UINT8 DwrEn_IE_UERRN; + UINT8 DwrEn_ACRU_ERR_2H_EN; + + UINT8 DwrPmcEn_HOST_RESET_TIMEOUT; + UINT8 DwrPmcEn_SX_ENTRY_TIMEOUT; + UINT8 DwrPmcEn_HOST_RST_PROM; + UINT8 DwrPmcEn_HSMB_MSG; + UINT8 DwrPmcEn_IE_MTP_TIMEOUT; + UINT8 DwrPmcEn_MTP_TIMEOUT; + UINT8 DwrPmcEn_ESPI_ERROR_DETECT; + + UINT8 Dwr_MeResetPrepDone; + UINT8 Dwr_IeResetPrepDone; + + // + // PCH_DEVICE_ENABLES + // + UINT8 BoardCapability; + UINT8 DeepSxMode; + UINT8 Gp27WakeFromDeepSx; + UINT8 GbeRegionInvalid; + UINT8 LomLanSupported; + UINT8 PchWakeOnLan; + UINT8 PchSlpLanLowDc; + UINT8 PchSmbus; + UINT8 PchPciClockRun; + UINT8 PchDisplay; + UINT8 PchCrid; + UINT8 PchRtcLock; + UINT8 PchBiosLock; + UINT8 PchAllUnLock; + UINT8 PchThermalUnlock; + UINT8 PchSerm; + UINT8 PchGbeFlashLockDown; + UINT8 PchSmmBwp; + + UINT8 Hpet; + UINT8 PchPort80Route; + UINT8 EnableClockSpreadSpec; + UINT8 IchPort80Route; + UINT8 PchSirqMode; + + // + // Usb Config + // + UINT8 PchUsbManualMode; + UINT8 PchGpioLockDown; + UINT8 RouteUsb2PinsToWhichHc; + UINT8 RouteUsb2Pin0; + UINT8 RouteUsb2Pin1; + UINT8 RouteUsb2Pin2; + UINT8 RouteUsb2Pin3; + UINT8 RouteUsb2Pin4; + UINT8 RouteUsb2Pin5; + UINT8 RouteUsb2Pin6; + UINT8 RouteUsb2Pin7; + UINT8 RouteUsb2Pin8; + UINT8 RouteUsb2Pin9; + UINT8 RouteUsb2Pin10; + UINT8 RouteUsb2Pin11; + UINT8 RouteUsb2Pin12; + UINT8 RouteUsb2Pin13; + UINT8 Usb3PinsTermination; + UINT8 EnableUsb3Pin[10]; + UINT8 PchUsbHsPort[16]; + UINT8 PchUsbSsPort[10]; + UINT8 PchUsbPortDisable; + UINT8 UsbSensorHub; + UINT8 UsbSsicSupport[2]; + UINT8 XhciDisMSICapability; + UINT8 PchUsbPerPortCtl; + UINT8 PchUsb30Port[6]; + UINT8 UsbPrecondition; + UINT8 XhciIdleL1; + UINT8 Btcg; + UINT8 PchUsbDegradeBar; + // + // XHCI OC Map + // + UINT8 XhciOcMapEnabled; + // + // xDCI Config + // + UINT8 PchXdciSupport; + // + // Sata CONFIG + // + UINT8 PchSata; + // + // Sata Interface Mode + // 0 - IDE 1 - RAID 2 - AHCI + // + UINT8 SataInterfaceMode; + UINT8 SataPort[PCH_MAX_SATA_PORTS]; + UINT8 SataHotPlug[PCH_MAX_SATA_PORTS]; + UINT8 SataMechanicalSw[PCH_MAX_SATA_PORTS]; + UINT8 SataSpinUp[PCH_MAX_SATA_PORTS]; + UINT8 SataExternal[PCH_MAX_SATA_PORTS]; + UINT8 SataType[PCH_MAX_SATA_PORTS]; + UINT8 SataRaidR0; + UINT8 SataRaidR1; + UINT8 SataRaidR10; + UINT8 SataRaidR5; + UINT8 SataRaidIrrt; + UINT8 SataRaidOub; + UINT8 SataHddlk; + UINT8 SataLedl; + UINT8 SataRaidIooe; + UINT8 SataRaidSrt; + UINT8 SataRaidLoadEfiDriver; + UINT8 SataRaidOromDelay; + UINT8 SataAlternateId; + UINT8 SataSalp; + UINT8 SataTestMode; + UINT8 PxDevSlp[PCH_MAX_SATA_PORTS]; + UINT8 EnableDitoConfig[PCH_MAX_SATA_PORTS]; + UINT16 DitoVal[PCH_MAX_SATA_PORTS]; + UINT8 DmVal[PCH_MAX_SATA_PORTS]; + UINT8 SataTopology[PCH_MAX_SATA_PORTS]; =20 + + // + // sSata CONFIG + // + UINT8 PchsSata; + // + // Sata Interface Mode + // 0 - IDE 1 - RAID 2 - AHCI + // + UINT8 sSataInterfaceMode; + UINT8 sSataPort[PCH_SSATA_MAX_PORTS]; + UINT8 sSataHotPlug[PCH_SSATA_MAX_PORTS]; + UINT8 sSataSpinUp[PCH_SSATA_MAX_PORTS]; + UINT8 sSataExternal[PCH_SSATA_MAX_PORTS]; + UINT8 sPxDevSlp[PCH_SSATA_MAX_PORTS]; + UINT8 sSataType[PCH_SSATA_MAX_PORTS]; + UINT8 sSataRaidR0; + UINT8 sSataRaidR1; + UINT8 sSataRaidR10; + UINT8 sSataRaidR5; + UINT8 sSataRaidIrrt; + UINT8 sSataRaidOub; + UINT8 sSataHddlk; + UINT8 sSataLedl; + UINT8 sSataRaidIooe; + UINT8 sSataRaidSrt; + UINT8 sSataRaidLoadEfiDriver; + UINT8 sSataRaidOromDelay; + UINT8 sSataAlternateId; + UINT8 sSataSalp; + UINT8 sSataTestMode; + UINT8 sEnableDitoConfig[PCH_SSATA_MAX_PORTS]; + UINT8 sDmVal[PCH_SSATA_MAX_PORTS]; + UINT8 sDitoVal[PCH_SSATA_MAX_PORTS]; + UINT8 sSataTopology[PCH_SSATA_MAX_PORTS]; =20 + + + + + //PCH THERMAL SENSOR + UINT8 ThermalDeviceEnable; + UINT8 PchCrossThrottling; + + UINT8 PchDmiExtSync; + UINT8 PcieDmiExtSync; + // AcpiDebug Setup Options + UINT8 PciDelayOptimizationEcr; + UINT8 PchPcieGlobalAspm; + + UINT8 PcieDmiStopAndScreamEnable; + UINT8 DmiLinkDownHangBypass; + UINT8 XTpmLen; + UINT8 PcieRootPort8xhDecode; + UINT8 Pcie8xhDecodePortIndex; + UINT8 PcieRootPortPeerMemoryWriteEnable; + UINT8 PcieComplianceTestMode; + + + UINT8 PcieRootPortSBDE; + UINT8 PcieSBDEPort; + + UINT8 RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR]; + UINT8 RstPcieStorageRemapPort[PCH_MAX_RST_PCIE_STORAGE_CR]; + UINT8 PcieRootPortFunctionSwapping; + UINT8 PcieRootPortEn[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortAspm[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortURE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortFEE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortNFE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortCEE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortMSIE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortMaxPayLoadSize[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortAER[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieTopology[PCH_MAX_PCIE_ROOT_PORTS]; =20 + =20 + UINT8 PcieLaneCm[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieLaneCp[PCH_MAX_PCIE_ROOT_PORTS]; + + UINT8 PcieSwEqOverride; + UINT8 PcieSwEqCoeffCm[PCH_PCIE_SWEQ_COEFFS_MAX]; + UINT8 PcieSwEqCoeffCp[PCH_PCIE_SWEQ_COEFFS_MAX]; + UINT8 PchPcieUX8MaxPayloadSize; + UINT8 PchPcieUX16MaxPayloadSize; + UINT8 PcieRootPortCompletionTimeout[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieClockGatingDisabled; + UINT8 PcieUsbGlitchWa; + UINT8 PcieRootPortPIE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortACS[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortEqPh3Method[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortMaxReadRequestSize; + UINT8 PcieRootPortSFE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSNE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSCE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortPMCE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortHPE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSpeed[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortTHS[PCH_MAX_PCIE_ROOT_PORTS];=20 + + // + // PCI Bridge Resources + // + UINT8 PcieRootPortL1SubStates[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 MemoryThermalManagement; + UINT8 ExttsViaTsOnBoard; + UINT8 ExttsViaTsOnDimm; + UINT8 FixupPlatformSpecificSoftstraps; + + // + // SMBUS Configuration + // + UINT8 TestSmbusSpdWriteDisable; + + + // + // HD-Audio Configuration + // + UINT8 PchHdAudio; + UINT8 PchHdAudioDsp; + UINT8 PchHdAudioPme; + UINT8 PchHdAudioIoBufferOwnership; + UINT8 PchHdAudioIoBufferVoltage; + UINT8 PchHdAudioCodecSelect; + UINT8 PchHdAudioFeature[HDAUDIO_FEATURES]; + UINT8 PchHdAudioPostProcessingMod[HDAUDIO_PP_MODULES]; + + UINT8 RtoHdaVcType; + // + // DMI Configuration + // + UINT8 TestDmiAspmCtrl; + + + // + // + // PCIe LTR Configuration + // + UINT8 PchPcieLtrEnable[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieLtrConfigLock[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieNonSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieNonSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS= ]; + UINT16 PchPcieSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS]; + UINT16 PchPcieNonSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS]; + + UINT8 PchPcieForceLtrOverride[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchSataLtrOverride; + UINT8 PchSataLtrEnable; + UINT16 PchSataSnoopLatencyOverrideValue; + UINT8 PchSataSnoopLatencyOverrideMultiplier; + UINT8 PchSataLtrConfigLock; + + UINT8 PchSSataLtrOverride; + UINT16 PchSSataSnoopLatencyOverrideValue; + UINT8 PchSSataSnoopLatencyOverrideMultiplier; + UINT8 PchSSataLtrEnable; + UINT8 PchSSataLtrConfigLock; + + UINT8 PchPcieUX16CompletionTimeout; + UINT8 PchPcieUX8CompletionTimeout; + + // + // Interrupt Configuration + // + UINT8 PchIoApic24119Entries; + + // + // DPTF SETUP items begin + // + UINT8 EnableDptf; + UINT8 EnablePchDevice; + + // + // CPU + // + UINT8 DebugDciEnable; + UINT8 DebugInterfaceEnable; + + // + // Miscellaneous options + // + UINT8 OsDebugPort; + UINT8 SlpLanLowDc; + UINT8 PchLanK1Off; + UINT8 PchWakeOnWlan; + UINT8 PchWakeOnWlanDeepSx; + UINT8 StateAfterG3; + UINT8 PciePllSsc; + UINT8 FirmwareConfiguration; + UINT8 PchDciEn; + UINT8 PchDciAutoDetect; + + // Acpi.sd + UINT8 CSNotifyEC; + UINT8 EcLowPowerMode; + + // + // TraceHub Setup Options + // + UINT8 TraceHubEnableMode; + UINT8 MemRegion0BufferSize; + UINT8 MemRegion1BufferSize; + + // + // PCH P2SB hide and lock options + // + UINT8 PchP2sbDevReveal; + UINT8 PchP2sbUnlock; + + // + // PCH SPI hide and lock options + // + UINT8 FlashLockDown; + + // + // PCH PMC option + // + UINT8 PmcReadDisable; + + + // + // ADR Configuration + // + UINT8 PchAdrEn; + UINT8 AdrTimerEn; + UINT8 AdrTimerVal; + UINT8 AdrMultiplierVal; + UINT8 AdrGpioSel; + UINT8 AdrHostPartitionReset; + + // + // Audio DSP Configuration + // + UINT8 PchAudioDsp; + UINT8 PchAudioDspD3PowerGating; + UINT8 PchAudioDspAcpiMode; + UINT8 PchAudioDspBluetooth; + UINT8 PchAudioDspAcpiInterruptMode; + + // + // Miscellaneous options + // + + UINT8 PchEvaMrom0HookEnable; + UINT8 PchEvaMrom1HookEnable; + UINT8 TestMctpBroadcastCycle; + UINT8 PchEvaLockDown; + UINT8 PchTraceHubHide; +} PCH_RC_CONFIGURATION; +#pragma pack() + +#endif + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h= b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h new file mode 100644 index 0000000000..f8ea067b50 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h @@ -0,0 +1,539 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SETUP_VARIABLE_H__ +#define __SETUP_VARIABLE_H__ + +#include "UncoreCommonIncludes.h" +// -----------------------------------------------------------------------= ---- +// +// Driver Configuration +// +// -----------------------------------------------------------------------= ---- +// + +#define MAX_PCH_PCI_EXPRESS_ROOT_PORTS 8 +#define PASSWORD_MAX_SIZE 16 +#define SHA256_DIGEST_LENGTH 32 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 + +#pragma pack(1) + +typedef struct { + + UINT8 UserPassword[SHA256_DIGEST_LENGTH]; + UINT8 AdminPassword[SHA256_DIGEST_LENGTH]; + UINT8 Access; + + // + // Keyboard + // + UINT8 Numlock; + UINT8 Ps2PortSwap; + + // + // TPM + // + UINT8 TpmEnable; + UINT8 TpmState; + UINT8 MorState; + + // + // Breakpoints + // + UINT8 ValidationBreakpointType; + UINT16 bsdBreakpoint; + + // + // Power State + // + UINT8 PowerState; + + // + // Wake On Lan + // + UINT8 WakeOnLanS5; + + // + // Boot from Network + // + UINT8 BootNetwork; + + // + // Video + // + UINT8 VideoSelect; + UINT8 EfiWindowsInt10Workaround; + UINT8 UefiOptimizedBootToggle; + + // + // Fan PWM Offset + // + UINT8 FanPwmOffset; + + // + // PCI Minimum Secondary Bus Number + // + UINT8 PCIe_MultiSeg_Support; + + // + UINT8 WakeOnLanSupport; + // + // Enable/disable for PCIe LOM by using GPO44/45 + // NOT PCH LAN + // + UINT8 LomDisableByGpio; + + UINT8 FpkPortConfig[4]; + UINT8 FpkPortConfigPrev[4]; + UINT8 FpkPortPresent[4]; + + // RTC WAKE + // + UINT8 WakeOnRTCS4S5; + UINT8 RTCWakeupTimeHour; + UINT8 RTCWakeupTimeMinute; + UINT8 RTCWakeupTimeSecond; + // PCI_EXPRESS_CONFIG, ROOT PORTS + // + // AJW: these cross the line, but depend on Platform Info + UINT8 PcieClockGating; + UINT8 PcieDmiAspm; + UINT8 PcieSBDE; + UINT8 GbePciePortNum; + UINT8 PciePortConfig1; + UINT8 PciePortConfig2; + UINT8 PciePortConfig3; + UINT8 PciePortConfig4; + UINT8 PciePortConfig5; + + // GBE + UINT8 GbeEnabled; + + // PCH Stepping + UINT8 PchStepping; + + // + // XHCI Wake On USB + // + UINT8 XhciWakeOnUsbEnabled; + + // + // EventLog + // +// +// SKX_TODO: add these for RAS, may be best to find new home for them in a= new setup variable and setup page +// + UINT8 SystemErrorEn; + //Viral, and IoMca are not supported in EP. Will need to wrap in an EX f= lag + //UINT8 ViralEn; + UINT8 PoisonEn; + UINT8 ViralEn; + UINT8 ClearViralStatus; + UINT8 CloakingEn; + UINT8 UboxToPcuMcaEn; + UINT8 FatalErrSpinLoopEn; + + UINT8 EmcaEn; + UINT8 EmcaIgnOptin; + UINT8 EmcaCsmiEn; + UINT8 EmcaMsmiEn; + UINT8 ElogCorrErrEn; + UINT8 ElogMemErrEn; + UINT8 ElogProcErrEn; + UINT8 LmceEn; + + UINT8 WheaSupportEn; + UINT8 WheaLogMemoryEn; + UINT8 WheaLogProcEn; + + UINT8 WheaLogPciEn; + + UINT8 WheaErrorInjSupportEn; + UINT8 McaBankErrInjEn; + UINT8 WheaErrInjEn; + UINT8 WheaPcieErrInjEn; + UINT8 MeSegErrorInjEn; + UINT8 PcieErrInjActionTable; + UINT8 ParityCheckEn; + + UINT8 MemErrEn; + UINT8 CorrMemErrEn; + UINT32 LeakyBktHiLeakyBktLo; + UINT8 SpareIntSelect; + UINT8 FnvErrorEn; + UINT8 FnvErrorLowPrioritySignal; // 0 - No Log, 1 - SMI, 2 - ERR0#, 3= - BOTH + UINT8 FnvErrorHighPrioritySignal; // 0 - No Log, 1 - SMI, 2 - ERR0#, 3= - BOTH + UINT8 Reserved_1; + UINT8 Reserved_2; + UINT8 Reserved_3; + + UINT8 IioErrorEn; + UINT8 IoMcaEn; + UINT8 IioErrRegistersClearEn; + UINT8 IioErrorPinEn; + UINT8 LerEn; + UINT8 DisableMAerrorLoggingDueToLER; + UINT8 IioIrpErrorEn; + UINT8 IioMiscErrorEn; + UINT8 IioVtdErrorEn; + UINT8 IioDmaErrorEn; + UINT8 IioDmiErrorEn; + UINT8 IioPcieAddCorrErrorEn; + UINT8 IioPcieAddUnCorrEn; + UINT8 IioPcieAerSpecCompEn; + + UINT8 PcieErrEn; + UINT8 PcieCorrErrEn; + UINT8 PcieUncorrErrEn; + UINT8 PcieFatalErrEn; + UINT8 PcieCorErrCntr; + UINT8 PcieCorErrMaskBitMap; + UINT16 PcieCorErrThres; + UINT8 PcieAerCorrErrEn; + UINT8 PcieAerAdNfatErrEn; + UINT8 PcieAerNfatErrEn; + UINT8 PcieAerFatErrEn; + UINT8 SerrPropEn; + UINT8 PerrPropEn; + UINT8 OsSigOnSerrEn; + UINT8 OsSigOnPerrEn; + + UINT8 CaterrGpioSmiEn; + +// Endof RAS add + //Viral, and IoMca are not supported in EP. Will need to wrap in an EX f= lag + //UINT8 IoMcaEn; + + UINT8 McBankWarmBootClearError; + UINT8 KTIFailoverSmiEn; + + UINT8 irpp0_parityError; + UINT8 irpp0_qtOverflow; + UINT8 irpp0_unexprsp; + UINT8 irpp0_csraccunaligned; + UINT8 irpp0_unceccCs1; + UINT8 irpp0_unceccCs0; + UINT8 irpp0_rcvdpoison; + UINT8 irpp0_crreccCs1; + UINT8 irpp0_crreccCs0; + + UINT8 PropagateSerr; + UINT8 PropagatePerr; + + // + // Boot Options + // + UINT8 serialDebugMsgLvl; + UINT8 serialDebugTrace; + UINT8 serialDebugMsgLvlTrainResults; + UINT8 ResetOnMemMapChange; + UINT8 ForceSetup; + UINT8 BiosGuardEnabled; + UINT8 BiosGuardPlatformSupported; + UINT8 EnableAntiFlashWearout; + UINT8 AntiFlashWearoutSupported; + UINT8 RtoPopulateBGDirectory; + + UINT8 Use1GPageTable; + // + // UINT8 QuietBoot; + // + UINT8 FastBoot; + + // + // Reserve Memory that is hidden from the OS. + // + UINT8 ReserveMem; + UINT64 ReserveStartAddr; + + // + // Reserve TAGEC Memory + // + UINT8 TagecMem; + + //Usb Configdata + UINT8 UsbMassDevNum; + UINT8 UsbLegacySupport; + UINT8 UsbEmul6064; + UINT8 UsbMassResetDelay; + UINT8 UsbNonBoot; + UINT8 UsbEmu1; + UINT8 UsbEmu2; + UINT8 UsbEmu3; + UINT8 UsbEmu4; + UINT8 UsbEmu5; + UINT8 UsbEmu6; + UINT8 UsbEmu7; + UINT8 UsbEmu8; + UINT8 UsbEmu9; + UINT8 UsbEmu10; + UINT8 UsbEmu11; + UINT8 UsbEmu12; + UINT8 UsbEmu13; + UINT8 UsbEmu14; + UINT8 UsbEmu15; + UINT8 UsbEmu16; + UINT8 UsbStackSupport; + + // Console Redirection + UINT8 ConsoleRedirection; + UINT8 FlowControl; + UINT64 BaudRate; + UINT8 TerminalType; + UINT8 LegacyOsRedirection; + UINT8 TerminalResolution; + UINT8 DataBits; + UINT8 Parity; + UINT8 StopBits; + +#ifdef EFI_PCI_IOV_SUPPORT + UINT8 SystemPageSize; + UINT8 ARIEnable; + UINT8 ARIForward; + UINT8 SRIOVEnable; + UINT8 MRIOVEnable; +#endif + // + // RAS + // + +// +// Network setup entries - start here <><><><><> +// + UINT8 LegacyPxeRom; + UINT8 EfiNetworkSupport; +// +// Network setup entries - end here <><><><><> +// + +// +// SERIALPORT BAUD RATE: Begin +// + UINT32 SerialBaudRate; +// +// SERIALPORT BAUD RATE: END +// + + UINT8 BootAllOptions; + UINT8 SetShellFirst; + + // + // Overclocking related setup variables + // + UINT8 PlatformOCSupport; + UINT8 FilterPll; + UINT8 OverclockingSupport; + + UINT8 CoreMaxOcRatio; + UINT8 CoreVoltageMode; + UINT16 CoreVoltageOverride; + UINT16 CoreVoltageOffset; + UINT8 CoreVoltageOffsetPrefix; + UINT16 CoreExtraTurboVoltage; + + // + // OC related + // + UINT8 MemoryVoltage; + UINT8 MemoryVoltageDefault; + UINT8 tCL; + + // + // CLR Related + // + UINT8 ClrMaxOcRatio; + UINT8 ClrVoltageMode; + UINT16 ClrVoltageOverride; + UINT16 ClrVoltageOffset; + UINT8 ClrVoltageOffsetPrefix; + UINT16 ClrExtraTurboVoltage; + + // + // Uncore Related + // + UINT16 UncoreVoltageOffset; + UINT8 UncoreVoltageOffsetPrefix; + UINT16 IoaVoltageOffset; + UINT8 IoaVoltageOffsetPrefix; + UINT16 IodVoltageOffset; + UINT8 IodVoltageOffsetPrefix; + + // + // SVID and FIVR Related + // + UINT8 SvidEnable; + UINT16 SvidVoltageOverride; + UINT8 FivrFaultsEnable; + UINT8 FivrEfficiencyEnable; + + UINT8 SataInterfaceRAIDMode; + UINT8 sSataInterfaceRAIDMode; + + UINT16 C01MemoryVoltage; + UINT16 C23MemoryVoltage; + + UINT16 CpuVccInVoltage; + + UINT8 VccIoVoltage; + + UINT8 CloudProfile; + UINT16 VariablePlatId; + + //XTU 3.0 + + UINT8 FlexRatioOverrideDefault; + UINT8 RatioLimit1Default; + UINT8 RatioLimit2Default; + UINT8 RatioLimit3Default; + UINT8 RatioLimit4Default; + UINT8 OverclockingLockDefault; + UINT8 DdrRefClkDefault; + UINT8 DdrRatioDefault; + UINT8 tCLDefault; + UINT8 tCWLDefault; + UINT16 tFAWDefault; + UINT16 tRASDefault; + UINT16 tRCDefault; + UINT8 tRCDDefault; + UINT16 tREFIDefault; + UINT16 tRFCDefault; + UINT8 tRPDefault; + UINT8 tRPabDefault; + UINT8 tRRDDefault; + UINT8 tRTPDefault; + UINT8 tWRDefault; + UINT8 tWTRDefault; + UINT8 NModeDefault; + UINT8 CoreMaxOcRatioDefault; + UINT8 CoreVoltageModeDefault; + UINT16 CoreVoltageOverrideDefault; + UINT16 CoreVoltageOffsetDefault; + UINT8 CoreVoltageOffsetPrefixDefault; + UINT16 CoreExtraTurboVoltageDefault; + UINT8 GtOcSupportDefault; + UINT8 GtOcFrequencyDefault; + UINT16 GtExtraTurboVoltageDefault; + UINT16 GtOcVoltageDefault; + UINT8 GtVoltageModeDefault; + UINT16 GtVoltageOverrideDefault; + UINT16 GtVoltageOffsetDefault; + UINT8 GtVoltageOffsetPrefixDefault; + UINT8 ClrMaxOcRatioDefault; + UINT8 ClrVoltageModeDefault; + UINT16 ClrVoltageOverrideDefault; + UINT16 ClrVoltageOffsetDefault; + UINT8 ClrVoltageOffsetPrefixDefault; + UINT16 ClrExtraTurboVoltageDefault; + UINT16 UncoreVoltageOffsetDefault; + UINT8 UncoreVoltageOffsetPrefixDefault; + UINT16 IoaVoltageOffsetDefault; + UINT8 IoaVoltageOffsetPrefixDefault; + UINT16 IodVoltageOffsetDefault; + UINT8 IodVoltageOffsetPrefixDefault; + UINT8 SvidEnableDefault; + UINT16 SvidVoltageOverrideDefault; + UINT8 FivrFaultsEnableDefault; + UINT8 FivrEfficiencyEnableDefault; + UINT16 VrCurrentLimitDefault; + UINT8 EnableGvDefault; + UINT8 TurboModeDefault; + UINT8 PowerLimit1TimeDefault; + UINT16 PowerLimit1Default; + UINT16 PowerLimit2Default; + + + UINT8 RatioLimit1; //ratiolimit handling has changed in SKX. knobs might= need to change too. Will have to revisit again. + UINT8 RatioLimit2; + UINT8 RatioLimit3; + UINT8 RatioLimit4; + UINT8 CpuRatio; // need to understand what is the difference between max= nonturboratio and cpuratio. if cpuratiooverride is 0, then cpuratio is same= as maxnonturboratio. add this to platform cpu policy or socketsetup. + UINT8 CpuRatioOverride; + UINT8 IsTurboRatioDefaultsInitalized; // related to initializing all the= vardefault. is this flow needed for HEDT/intended only for clients? no nee= d for set up creation. + + + UINT8 DdrRefClk; //cant find any in purley. new one? + UINT8 PcieRatioDisabled;//need to check if this is applicable to HEDT. a= lso no need to create a setup variable. + UINT8 NMode ; + UINT8 Pmtt; + + UINT16 GtVoltageOffset; //existing but no set up option + UINT16 VrCurrentLimit;//done + //UINT8 SpdProfileSelected; same as XMPMode + UINT8 NModeSupport; + UINT8 WDTSupportforNextOSBoot; // no setup option needed + UINT16 TimeforNextOSBoot; // no setup optiom needed + UINT8 PlatformUnstable; // no set up option needed. this decides if all = the vardefaults are needed. + UINT8 GtVoltageMode; //existing but no set up option + UINT8 DdrRatio; + UINT8 GtOcFrequency; + UINT16 GtExtraTurboVoltage; //existing but no set up option + UINT16 GtVoltageOverride; //existing but no set up option + UINT8 GtVoltageOffsetPrefix; + UINT8 GtOcSupport; + // + // CPU releated + // + UINT8 FlexOverrideEnable; + UINT8 FlexRatioOverride; + UINT8 PowerLimit3Override; + UINT32 PowerLimit3; + UINT8 PowerLimit3Time; + UINT8 PowerLimit3DutyCycle; + UINT8 PowerLimit3Lock; + UINT8 MemoryVoltageOverride; + + // + // ICC Related + // + UINT8 BClkOverride; + UINT8 BclkAdjustable; + UINT8 DmiPegRatio; + UINT8 SkipXmlComprs; + UINT8 DfxAdvDebugJumper; + UINT8 DfxAltPostCode; + + // + // Validation Related + // + UINT8 ValidationResetType; + UINT16 ValidationCountOuter; + UINT16 ValidationCountInner; + UINT8 ValidationStopOnError; + UINT8 ValidationBootWhenDone; + UINT8 ValidationSkxPciError; + UINT8 ValidationSkxPciLinkError; + UINT8 ValidationPchPciError; + UINT8 ValidationSkxPciLinkRecoveryCountError; + UINT16 ValidationSkxPciLinkRecoveryCountThreshold; + UINT8 ValidationKtiError; + + UINT8 TraceHubDebugInterface; + UINT8 RamDebugInterface; + UINT8 StorageOpROMSuppression; +// +// PC_SIO_END +// + UINT8 RsaSupport; + +} SYSTEM_CONFIGURATION; + +#pragma pack() + +#define EFI_HDD_PRESENT 0x01 +#define EFI_HDD_NOT_PRESENT 0x00 +#define EFI_CD_PRESENT 0x02 +#define EFI_CD_NOT_PRESENT 0x00 + +#define EFI_HDD_WARNING_ON 0x01 +#define EFI_CD_WARNING_ON 0x02 +#define EFI_SMART_WARNING_ON 0x04 +#define EFI_HDD_WARNING_OFF 0x00 +#define EFI_CD_WARNING_OFF 0x00 +#define EFI_SMART_WARNING_OFF 0x00 + +#endif // #ifndef _SETUP_VARIABLE diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/IioBifurcationSlotTa= ble.h b/Platform/Intel/PurleyOpenBoardPkg/Include/IioBifurcationSlotTable.h new file mode 100644 index 0000000000..76450ec21f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/IioBifurcationSlotTable.h @@ -0,0 +1,100 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef IIOBIFURCATIONSLOTTABLE_H +#define IIOBIFURCATIONSLOTTABLE_H + +#include "IioPlatformData.h" + +#define QAT_ENABLED 0 // QAT is active-low +#define RISER_PRESENT 0 +#define RISER_NOT_PRESENT 1 +#define RISER_HP_EN 1 +#define RISER_WINGED_IN 0 +#define RISER_SLOT9_DISABLE 1 + +typedef struct { + UINT8 Socket; + UINT8 IouNumber; + UINT8 Bifurcation; +} IIO_BIFURCATION_ENTRY; + +typedef union { + struct { + UINT8 PresentSignal:1; + UINT8 HPConf:1; + UINT8 WingConf:1; + UINT8 Slot9En:1; + } Bits; + UINT8 Data; +} PCIE_RISER_ID; + +enum { + Iio_PortA =3D 0, + Iio_PortB =3D 1, + Iio_PortC =3D 2, + Iio_PortD =3D 3 +}; +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; +/// +/// Platform Port/Socket assignments. +/// + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + +typedef struct { + UINT8 PortIndex; + UINT8 SlotNumber; // 0xff if slot not implemented , Slot number if= slot implemented + BOOLEAN InterLockPresent; + UINT8 SlotPowerLimitScale; + UINT8 SlotPowerLimitValue; + BOOLEAN HotPlugCapable; + UINT8 VppPort; // 0xff if Vpp not enabled + UINT8 VppAddress; + BOOLEAN PcieSSDCapable; + UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled + UINT8 PcieSSDVppAddress; + BOOLEAN Hidden; +} IIO_SLOT_CONFIG_ENTRY; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Platform.h b/Platfor= m/Intel/PurleyOpenBoardPkg/Include/Platform.h new file mode 100644 index 0000000000..160506039a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Platform.h @@ -0,0 +1,92 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Uefi.h" +#include "Guid/SetupVariable.h" +#include "UncoreCommonIncludes.h" +#include + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +// +// Assigning default ID and base addresses here, these definitions are use= d by ACPI tables +//=20 + +#define PCH_INTERRUPT_BASE 0 + +#if MAX_SOCKET > 4 +#define PCH_IOAPIC 0 +#else +#define PCH_IOAPIC (1 << 0) +#endif + +// +// This structure stores the base and size of the ACPI reserved memory use= d when +// resuming from S3. This region must be allocated by the platform code. +// +typedef struct { + UINT32 AcpiReservedMemoryBase; + UINT32 AcpiReservedMemorySize; + UINT32 SystemMemoryLength; +} RESERVED_ACPI_S3_RANGE; + +#define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_AC= PI_S3_RANGE)) + +// +// SMBUS Data +// +#define PCH_SMBUS_BASE_ADDRESS 0x0780 + +// +// CMOS usage +// + +#define CMOS_WARM_RESET_COUNTER_OFFSET 0xBD // 1 byte CMOS Space = for passing warm reset counter to Dxe + // due to reset in = MRC Dxe always thinks that warm reset occurs + // counter > 1 -> m= eans WarmReset + +// +// ACPI and legacy I/O register offsets from PMBASE +// +#define R_ACPI_PM1_STS 0x00 +#define R_ACPI_PM1_EN 0x02 +#define R_ACPI_PM1_CNT 0x04 +#define R_ACPI_PM1_TMR 0x08 +#define R_ACPI_PROC_CNT 0x10 +#define R_ACPI_PM2_CNT 0x50 +#define R_ACPI_GPE0_STS 0x20 +#define R_ACPI_GPE0_EN 0x28 +#define R_ACPI_SMI_EN 0x30 +#define R_ACPI_SMI_STS 0x34 +#define R_ACPI_ALT_GP_SMI_EN 0x38 +#define R_ACPI_ALT_GP_SMI_STS 0x3A + +#define R_ACPI_LV2 0x14 + +#define R_IOPORT_CMOS_STANDARD_INDEX 0x70 +#define R_IOPORT_CMOS_STANDARD_DATA 0x71 + +#define R_IOPORT_CMOS_UPPER_INDEX 0x72 +#define R_IOPORT_CMOS_UPPER_DATA 0x73 + +#define R_IOPORT_CMOS_IDX_DIAGNOSTIC_STATUS 0x0E + +// +// Misc PCI register offsets and sizes +// +#define R_EFI_PCI_SVID 0x2C +#define V_EFI_PCI_SVID_SIZE 0x2 +#define R_EFI_PCI_SID 0x2E +#define V_EFI_PCI_SID_SIZE 0x2 + +// +// Need min. of 24 MB PEI phase +// +#define PEI_MIN_MEMORY_SIZE (EFI_PHYSICAL_ADDRESS) ((320 * 0x1= 00000)) + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Ppi/SystemBoard.h b/= Platform/Intel/PurleyOpenBoardPkg/Include/Ppi/SystemBoard.h new file mode 100644 index 0000000000..ce0ebaf973 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Ppi/SystemBoard.h @@ -0,0 +1,63 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_SYSTEM_BOARD__H_ +#define _PEI_SYSTEM_BOARD__H_ + +#include +#include +#include +#include +#include +#include +#include + +/// +/// The forward declaration for SYSTEM_BOARD_INFO_PPI. +/// +typedef struct _SYSTEM_BOARD_PPI SYSTEM_BOARD_PPI; + +/** + + SystemIioPortBifurcationInit is used to updating the IIO_GLOBALS Data St= ructure with IIO + SLOT config data + Bifurcation config data + + @param *mSB - pointer to this protocol + + @retval *IioUds updated with SLOT and Bifurcation information updated. + +**/ +typedef +VOID + (EFIAPI *PEI_SYSTEM_IIO_PORT_BIF_INIT) ( + IN IIO_GLOBALS *IioGlobalData + ); +/** + + GetUplinkPortInformation is used to get board based uplink port informat= ion + + @param IioIndex - Socket ID + + @retval PortIndex for uplink. + +**/ +typedef +UINT8 + (EFIAPI *PEI_GET_UPLINK_PORT_INFORMATION) ( + IN UINT8 IioIndex + ); + + +struct _SYSTEM_BOARD_PPI { + PEI_SYSTEM_IIO_PORT_BIF_INIT SystemIioPortBifurcationInit; // Updat= e OEM IIO Port Bifurcation based on PlatformConfiguration + PEI_GET_UPLINK_PORT_INFORMATION GetUplinkPortInformation; // Get Uplin= k port information +}; + +extern EFI_GUID gEfiPeiSystemBoardPpiGuid; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Protocol/PciIovPlatf= orm.h b/Platform/Intel/PurleyOpenBoardPkg/Include/Protocol/PciIovPlatform.h new file mode 100644 index 0000000000..43762cf9ee --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Protocol/PciIovPlatform.h @@ -0,0 +1,70 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCI_IOV_PLATFORM_H_ +#define _PCI_IOV_PLATFORM_H_ + + +// +// Protocol for GUID. +// + +typedef struct _EFI_PCI_IOV_PLATFORM_PROTOCOL EFI_PCI_IOV_PLATFORM_PROTOCO= L; + +typedef UINT32 EFI_PCI_IOV_PLATFORM_POLICY; +=20 +#define EFI_PCI_IOV_POLICY_ARI 0x0001 +#define EFI_PCI_IOV_POLICY_SRIOV 0x0002 +#define EFI_PCI_IOV_POLICY_MRIOV 0x0004 + +typedef +EFI_STATUS +(EFIAPI * EFI_PCI_IOV_PLATFORM_GET_SYSTEM_LOWEST_PAGE_SIZE) ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT UINT32 *SystemLowestPageSize +) +/** + + The GetSystemLowestPageSize() function retrieves the system lowest pag= e size. + =20 + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROT= OCOL instance. + @param SystemLowestPageSize - The system lowest page size. (This syste= m supports a + page size of 2^(n+12) if bit n is set.) + =20 + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - SystemLowestPageSize is NULL. + =20 +**/ +; + +typedef +EFI_STATUS +(EFIAPI * EFI_PCI_IOV_PLATFORM_GET_PLATFORM_POLICY) ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_IOV_PLATFORM_POLICY *PciIovPolicy +) +/** + + The GetPlatformPolicy() function retrieves the platform policy regardi= ng PCI IOV. + =20 + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL ins= tance. + @param PciIovPolicy - The platform policy for PCI IOV configuration. + =20 + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - PciPolicy is NULL. + =20 +**/ +; + +typedef struct _EFI_PCI_IOV_PLATFORM_PROTOCOL { + EFI_PCI_IOV_PLATFORM_GET_SYSTEM_LOWEST_PAGE_SIZE GetSystemLowes= tPageSize; + EFI_PCI_IOV_PLATFORM_GET_PLATFORM_POLICY GetPlatformPol= icy; +} EFI_PCI_IOV_PLATFORM_PROTOCOL; + +extern EFI_GUID gEfiPciIovPlatformProtocolGuid; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/SetupTable.h b/Platf= orm/Intel/PurleyOpenBoardPkg/Include/SetupTable.h new file mode 100644 index 0000000000..7d8742ad4d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/SetupTable.h @@ -0,0 +1,21 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SETUP_TABLE_H_ +#define _SETUP_TABLE_H_ + +#include +#include +#include + +typedef struct { + SOCKET_CONFIGURATION SocketConfig; + SYSTEM_CONFIGURATION SystemConfig; + PCH_RC_CONFIGURATION PchRcConfig; +} SETUP_DATA; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/SioRegs.h b/Platform= /Intel/PurleyOpenBoardPkg/Include/SioRegs.h new file mode 100644 index 0000000000..8b25ad3162 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/SioRegs.h @@ -0,0 +1,35 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SIO_REG_H_ +#define _SIO_REG_H_ + +typedef struct { + UINT8 Index; + UINT8 Value; +} SIO_INDEX_DATA; + +#define REG_LOGICAL_DEVICE 0x07 +#define ACTIVATE 0x30 + +#define BASE_ADDRESS_HIGH0 0x60 +#define BASE_ADDRESS_LOW0 0x61 +#define INTERRUPT_TYPE 0x71 + +#define SIO_INDEX_PORT 0x2E +#define SIO_DATA_PORT 0x2F + +#define SIO_UART1 0x02 +#define SIO_SMI 0x0D +#define SIO_MAILBOX 0x0E + +#define SIO_UNLOCK 0xA5 +#define SIO_LOCK 0xAA + +#define EXIST BIT4 + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec b/Platform/= Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec new file mode 100644 index 0000000000..96dd6b5b48 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec @@ -0,0 +1,141 @@ +## @file +# Declaration file for Purley based boards. +# +# The DEC files are used by the utilities that parse DSC and +# INF files to generate AutoGen.c and AutoGen.h files +# for the build infrastructure. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D OpenBoardPkg + PACKAGE_GUID =3D 454FB726-6A01-49ce-B222-749CD093D3C5 + PACKAGE_VERSION =3D 0.91 + +[Includes] + Include + +[Guids] + gEfiMemoryConfigDataGuid =3D { 0x80dbd530, 0x= b74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 } } + gCpPlatFlashTokenSpaceGuid =3D { 0xc9c39664, 0x= 96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } + gOemSkuTokenSpaceGuid =3D { 0x9e37d253, 0x= abf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } } + gEfiIpmiPkgTokenSpaceGuid =3D { 0xe96431d, 0xc= 68e, 0x4212, { 0xa1, 0x70, 0x16, 0xa6, 0x8, 0x55, 0x12, 0xc6 } } + gPlatformTokenSpaceGuid =3D { 0x07dfa0d2, 0x= 2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } } + +[Ppis] + gEfiPeiSystemBoardPpiGuid =3D { 0xc8d85e8c, 0x= dc1c, 0x4f8c, { 0xad, 0xa7, 0x58, 0xc1, 0xd1, 0x07, 0xa3, 0x04 } } + gEfiSiliconRcHobsReadyPpi =3D { 0xecf149b5, 0x= bf4e, 0x4ac8, { 0x8a, 0x8c, 0xce, 0x87, 0xcb, 0xac, 0x93, 0xd3 } } + +[Protocols] + gEfiPciIovPlatformProtocolGuid =3D { 0xf3a4b484, 0x= 9b26, 0x4eea, { 0x90, 0xe5, 0xa2, 0x06, 0x54, 0x0c, 0xa5, 0x25 } } + gEfiDxeSystemBoardProtocolGuid =3D { 0xa57c1118, 0x= 6afc, 0x46d2, { 0xba, 0xe6, 0x92, 0x92, 0x62, 0xd3, 0xeb, 0x1e } } + +[PcdsFixedAtBuild] + + gPlatformTokenSpaceGuid.PcdCmosDebugPrintLevelReg|0x4C|UINT8|0x30000032 + + # Choose the default serial debug message level when CMOS is bad; in the= later BIOS phase, the setup default is applied + # 0 - Disable; 1 - Minimum; 2 - Normal; 3 - Max + gPlatformTokenSpaceGuid.PcdSerialDbgLvlAtBadCmos|0x1|UINT8|0x30000033 + +[PcdsFeatureFlag] + gPlatformTokenSpaceGuid.PcdFastBoot|FALSE|BOOLEAN|0x30000034 + + gPlatformTokenSpaceGuid.PcdUpdateConsoleInBds|TRUE|BOOLEAN|0x30000035 + +[PcdsDynamicEx] + gPlatformTokenSpaceGuid.PcdDfxAdvDebugJumper|FALSE|BOOLEAN|0x6000001D + + ## This value is used to save memory address of MRC data structure. + gPlatformTokenSpaceGuid.PcdSyshostMemoryAddress|0x00000000|UINT64|0x3000= 0040 + + gOemSkuTokenSpaceGuid.PcdForceTo1SConfigMode|FALSE|BOOLEAN|0x00000205 + + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x00000206 + + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0xFF|UINT8|0x00000207 + + gOemSkuTokenSpaceGuid.PcdMemTsegSize|0x0|UINT32|0x00000208 + gOemSkuTokenSpaceGuid.PcdMemIedSize|0x0|UINT32|0x00000209 + + gOemSkuTokenSpaceGuid.PcdUsb20OverCurrentMappings|0|UINT64|0x0000020A + gOemSkuTokenSpaceGuid.PcdUsb30OverCurrentMappings|0|UINT64|0x0000020B + + gOemSkuTokenSpaceGuid.PcdIioBifurcationTable|0|UINT64|0x0000020C + gOemSkuTokenSpaceGuid.PcdIioBifurcationTableEntries|0|UINT8|0x0000020D + gOemSkuTokenSpaceGuid.PcdIioSlotTable|0|UINT64|0x0000020E + gOemSkuTokenSpaceGuid.PcdIioSlotTableEntries|0|UINT8|0x0000020F + + gOemSkuTokenSpaceGuid.PcdAllLanesEparamTable|0|UINT64|0x00000210 + gOemSkuTokenSpaceGuid.PcdAllLanesEparamTableSize|0|UINT32|0x00000211 + gOemSkuTokenSpaceGuid.PcdPerLaneEparamTable|0|UINT64|0x00000212 + gOemSkuTokenSpaceGuid.PcdPerLaneEparamTableSize|0|UINT32|0x00000213 + gOemSkuTokenSpaceGuid.PcdBoardTypeBitmask|0|UINT32|0x00000214 + + gOemSkuTokenSpaceGuid.PcdSetupData|{0x0}|SYSTEM_CONFIGURATION|0x000F0001= { # SYSTEM_CONFIGURATION <=3D=3D PLA= TFORM_SETUP_VARIABLE_NAME|gEfiSetupVariableGuid + + Guid/SetupVariable.h + + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + } + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData|{0x0}|PCH_RC_CONFIGURATI= ON|0x000F0002 { # PCH_RC_CONFIGURATION <=3D=3D PCH= _RC_CONFIGURATION_NAME|gEfiPchRcVariableGuid + + Guid/PchRcVariable.h + + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData|{0x0}|SOCKET_IIO_CONFIGURAT= ION|0x000F0003 { # SOCKET_IIO_CONFIGURATION <=3D=3D= SOCKET_IIO_CONFIGURATION_NAME|gEfiSocketIioVariableGuid + + Guid/SocketIioVariable.h + + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData|{0x0}|SOCKET_COMMONRC_= CONFIGURATION|0x000F0004 { # SOCKET_COMMONRC_CONFIGURATION <= =3D=3D SOCKET_COMMONRC_CONFIGURATION_NAME|gEfiSocketCommonRcVariableGuid + + Guid/SocketCommonRcVariable.h + + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData|{0x0}|SOCKET_MP_LINK_CON= FIGURATION|0x000F0005 { # SOCKET_MP_LINK_CONFIGURATION <= =3D=3D SOCKET_MP_LINK_CONFIGURATION_NAME|gEfiSocketMpLinkVariableGuid + + Guid/SocketMpLinkVariable.h + + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData|{0x0}|SOCKET_MEMORY_CONF= IGURATION|0x000F0006 { # SOCKET_MEMORY_CONFIGURATION <=3D= =3D SOCKET_MEMORY_CONFIGURATION_NAME|gEfiSocketMemoryVariableGuid + + Guid/SocketMemoryVariable.h + + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData|{0x0}|SOCKET_PO= WERMANAGEMENT_CONFIGURATION|0x000F0007 { # SOCKET_POWERMANAGEMENT_CONFIGURA= TION <=3D=3D SOCKET_POWERMANAGEMENT_CONFIGURATION_NAME|gEfiSocketPowermanag= ementVarGuid + + Guid/SocketPowermanagementVariable.h + + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData|{0x0}|SOCKET_PROC= ESSORCORE_CONFIGURATION|0x000F0008 { # SOCKET_PROCESSORCORE_CONFIGURATION= <=3D=3D SOCKET_PROCESSORCORE_CONFIGURATION_NAME|gEfiSocketProcessorCoreV= arGuid + + Guid/SocketProcessorCoreVariable.h + + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + } + +[PcdsDynamic, PcdsDynamicEx] + gEfiIpmiPkgTokenSpaceGuid.PcdIpmiKcsTimeoutPeriod|5000|UINT64|0x90000020 + gEfiIpmiPkgTokenSpaceGuid.PcdIpmiBmcSlaveAddress|0x20|UINT8|0x90000021 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicy= InitLib/SiliconPolicyInitLib.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/L= ibrary/SiliconPolicyInitLib/SiliconPolicyInitLib.c new file mode 100644 index 0000000000..ae7720cfb1 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib= /SiliconPolicyInitLib.c @@ -0,0 +1,130 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Performs silicon pre-mem policy initialization. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The returned data must be used as input data for SiliconPolicyDonePreMem= (), + and SiliconPolicyUpdateLib.SiliconPolicyUpdatePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + Value of FspmUpd has been initialized by FSP binary default value. + Only a subset of FspmUpd needs to be updated for different silicon sku. + The return data is same FspmUpd. + + 2) In non-FSP path, the input policy could be NULL. + The return data is the initialized policy. + + @param[in, out] Policy Pointer to policy. + + @return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPreMem ( + IN OUT VOID *Policy OPTIONAL + ) +{ + EFI_STATUS Status; + PCH_POLICY_PPI *PchPolicyPpi; + + // + // Call PchCreatePolicyDefaults to initialize platform policy structure + // and get all intel default policy settings. + // + Status =3D PchCreatePolicyDefaults (&PchPolicyPpi); + ASSERT_EFI_ERROR (Status); + + return PchPolicyPpi; +} + +/* + The silicon pre-mem policy is finalized. + Silicon code can do initialization based upon the policy data. + + The input Policy must be returned by SiliconPolicyInitPreMem(). + =20 + @param[in] Policy Pointer to policy. + + @retval RETURN_SUCCESS The policy is handled consumed by silicon code. +*/ +RETURN_STATUS +EFIAPI +SiliconPolicyDonePreMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + + // + // Install PchPolicyPpi. + // While installed, RC assumes the Policy is ready and finalized. So ple= ase + // update and override any setting before calling this function. + // + Status =3D PchInstallPolicyPpi (Policy); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Performs silicon post-mem policy initialization. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The returned data must be used as input data for SiliconPolicyDonePostMe= m(), + and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + Value of FspsUpd has been initialized by FSP binary default value. + Only a subset of FspsUpd needs to be updated for different silicon sku. + The return data is same FspsUpd. + + 2) In non-FSP path, the input policy could be NULL. + The return data is the initialized policy. + + @param[in, out] Policy Pointer to policy. + + @return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPostMem ( + IN OUT VOID *Policy OPTIONAL + ) +{ + return Policy; +} + +/* + The silicon post-mem policy is finalized. + Silicon code can do initialization based upon the policy data. + + The input Policy must be returned by SiliconPolicyInitPostMem(). + =20 + @param[in] Policy Pointer to policy. + + @retval RETURN_SUCCESS The policy is handled consumed by silicon code. +*/ +RETURN_STATUS +EFIAPI +SiliconPolicyDonePostMem ( + IN VOID *Policy + ) +{ + return RETURN_SUCCESS; +} \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicy= InitLib/SiliconPolicyInitLib.inf b/Platform/Intel/PurleyOpenBoardPkg/Policy= /Library/SiliconPolicyInitLib/SiliconPolicyInitLib.inf new file mode 100644 index 0000000000..3883e9e14c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib= /SiliconPolicyInitLib.inf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyInitLib + FILE_GUID =3D B494DF39-A5F8-48A1-B2D0-EF523AD91C55 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyInitLib + +[Sources] + SiliconPolicyInitLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[LibraryClasses] + BaseMemoryLib + BaseLib + DebugLib + DebugPrintErrorLevelLib + HobLib + IoLib + MemoryAllocationLib + PeiServicesLib + PchPolicyLib diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicy= UpdateLib/PchPolicyUpdateUsb.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/L= ibrary/SiliconPolicyUpdateLib/PchPolicyUpdateUsb.c new file mode 100644 index 0000000000..73b90fd6d9 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateL= ib/PchPolicyUpdateUsb.c @@ -0,0 +1,99 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// EDK and EDKII have different GUID formats +// +#include +#include +#include "PlatformHost.h" +#include +#include +#include + + +VOID +UpdatePchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig, + IN SYSTEM_CONFIGURATION *SetupVariables, + IN PCH_RC_CONFIGURATION *PchRcVariables, + IN VOID *Usb20OverCurrentMappings, + IN VOID *Usb30OverCurrentMappings + ) +/*++ + +Routine Description: + + This function performs PCH USB Platform Policy initialzation + +Arguments: + PchUsbConfig Pointer to PCH_USB_CONFIG data buffer + SetupVariables Pointer to Setup variable + PlatformType PlatformType specified + PlatformFlavor PlatformFlavor specified + BoardType BoardType specified + +Returns: + +--*/ +{ + UINTN PortIndex; + + PchUsbConfig->UsbPrecondition =3D PchRcVariables->UsbPrecondition; + + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortInd= ex++) { + if (PchRcVariables->PchUsbHsPort[PortIndex] =3D=3D 1) { + PchUsbConfig->PortUsb20[PortIndex].Enable =3D TRUE; + } else { + PchUsbConfig->PortUsb20[PortIndex].Enable =3D FALSE; + } + } + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortInd= ex++) { + if (PchRcVariables->PchUsbSsPort[PortIndex] =3D=3D 1) { + PchUsbConfig->PortUsb30[PortIndex].Enable =3D TRUE; + } else { + PchUsbConfig->PortUsb30[PortIndex].Enable =3D FALSE; + } + } + + // + // xDCI (USB device) related settings from setup variable + // + if(PchRcVariables->PchXdciSupport =3D=3D 1) { + PchUsbConfig->XdciConfig.Enable=3D TRUE; + } else { + PchUsbConfig->XdciConfig.Enable=3D FALSE; + } + + // + // XHCI USB Over Current Pins disabled, update it based on setup option. + // + PchUsbConfig->XhciOcMapEnabled =3D PchRcVariables->XhciOcMapEnabled; + + // + // XHCI Wake On USB configured based on user input through setup option + // + PchUsbConfig->XhciWakeOnUsb =3D SetupVariables->XhciWakeOnUsbEnabled; + // + // XHCI option to disable MSIs + // + PchUsbConfig->XhciDisMSICapability =3D PchRcVariables->XhciDisMSICapabil= ity; + + // + // Platform Board programming per the layout of each port. + // + // OC Map for USB2 Ports + for (PortIndex=3D0;PortIndexPortUsb20[PortIndex].OverCurrentPin =3D (UINT8)((PCH_USB= _OVERCURRENT_PIN *)Usb20OverCurrentMappings)[PortIndex]; + } + + // OC Map for USB3 Ports + for (PortIndex=3D0;PortIndexPortUsb30[PortIndex].OverCurrentPin =3D (UINT8)((PCH_USB= _OVERCURRENT_PIN *)Usb30OverCurrentMappings)[PortIndex]; + } + +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicy= UpdateLib/SiliconPolicyUpdateLib.c b/Platform/Intel/PurleyOpenBoardPkg/Poli= cy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.c new file mode 100644 index 0000000000..cac6409719 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateL= ib/SiliconPolicyUpdateLib.c @@ -0,0 +1,659 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "Guid/SetupVariable.h" +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Haddock Creek +// +#define DIMM_SMB_SPD_P0C0D0_HC 0xA2 +#define DIMM_SMB_SPD_P0C0D1_HC 0xA0 +#define DIMM_SMB_SPD_P0C1D0_HC 0xA6 +#define DIMM_SMB_SPD_P0C1D1_HC 0xA4 +#define DIMM_SMB_SPD_P0C0D2_HC 0xAA +#define DIMM_SMB_SPD_P0C1D2_HC 0xA8 + +// +// Sawtooth Peak +// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only) +// +#define DIMM_SMB_SPD_P0C0D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C0D1_STP 0xA0 +#define DIMM_SMB_SPD_P0C1D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C1D1_STP 0xA0 + +// +// Aden Hills +// DDR4 System (1DPC) +// +#define DIMM_SMB_SPD_P0C0D0_AH 0xA0 +#define DIMM_SMB_SPD_P0C0D1_AH 0xA4 +#define DIMM_SMB_SPD_P0C1D0_AH 0xA2 +#define DIMM_SMB_SPD_P0C1D1_AH 0xA6 + + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusHCRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_HC, + DIMM_SMB_SPD_P0C0D1_HC, + DIMM_SMB_SPD_P0C1D0_HC, + DIMM_SMB_SPD_P0C1D1_HC +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_STP, + DIMM_SMB_SPD_P0C0D1_STP, + DIMM_SMB_SPD_P0C1D0_STP, + DIMM_SMB_SPD_P0C1D1_STP +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusAHRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_AH, + DIMM_SMB_SPD_P0C0D1_AH, + DIMM_SMB_SPD_P0C1D0_AH, + DIMM_SMB_SPD_P0C1D1_AH +}; + +VOID +UpdatePchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig, + IN SYSTEM_CONFIGURATION *SetupVariables, + IN PCH_RC_CONFIGURATION *PchRcVariables, + IN VOID *Usb20OverCurrentMappings, + IN VOID *Usb30OverCurrentMappings + ); + +static +VOID +InstallPlatformVerbTables ( + IN UINTN CodecType + ) +{ + +} + +EFI_STATUS +EFIAPI +UpdatePeiPchPolicy ( + IN OUT PCH_POLICY_PPI *PchPolicy + ) +/*++ + +Routine Description: + + This function performs PCH PEI Policy initialzation. + +Arguments: + + PchPolicy The PCH Policy PPI instance + +Returns: + + EFI_SUCCESS The PPI is installed and initialized. + EFI ERRORS The PPI is not successfully installed. + EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the d= river + +--*/ +{ + UINT8 Index; + UINTN LpcBaseAddress; + UINT8 MaxSataPorts; + UINT8 *SmBusReservedTable; + UINT8 SmBusReservedNum; + PCH_USB_OVERCURRENT_PIN *Usb20OverCurrentMappings=3DNULL; + PCH_USB_OVERCURRENT_PIN *Usb30OverCurrentMappings=3DNULL; + UINT8 VTdSupport; + SYSTEM_CONFIGURATION *SetupVariables; + PCH_RC_CONFIGURATION *PchRcVariables; + + DEBUG((EFI_D_ERROR, "platform common UpdatePeiPchPolicy entry\n")); + + SetupVariables =3D PcdGetPtr(PcdSetupData); + PchRcVariables =3D PcdGetPtr(PcdPchRcConfigurationData); + + LpcBaseAddress =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + PchPolicy->Port80Route =3D PchRcVariables->IchPort80Route; + + // + // DeviceEnables + // + if (PchIsGbeAvailable ()) { + PchPolicy->LanConfig.Enable =3D TRUE; + PchPolicy->LanConfig.K1OffEnable =3D PchRcVariables->PchLanK1Off; + } else { + PchPolicy->LanConfig.Enable =3D FALSE; + } + + PchPolicy->SataConfig.Enable =3D PchRcVariables->PchSata; + + PchPolicy->sSataConfig.Enable =3D PchRcVariables->PchsSata; + PchPolicy->SmbusConfig.Enable =3D TRUE; + // + // CLOCKRUN in LPC has to be disabled: + // - if a device is connected to LPC0 + // - for LBG A0 stepping + // + PchPolicy->PmConfig.PciClockRun =3D FALSE; + PchPolicy->PchConfig.Crid =3D PchRcVariables->PchCrid; + PchPolicy->PchConfig.Serm =3D PchRcVariables->PchSerm; + + + // + // SMBUS reserved addresses + // + SmBusReservedTable =3D NULL; + SmBusReservedNum =3D 0; + PchPolicy->SmbusConfig.SmbusIoBase =3D PCH_SMBUS_BASE_ADDRESS; + SmBusReservedTable =3D mSmbusSTPRsvdAddresses; + SmBusReservedNum =3D sizeof (mSmbusSTPRsvdAddresses); + + if (SmBusReservedTable !=3D NULL) { + PchPolicy->SmbusConfig.NumRsvdSmbusAddresses =3D SmBusReservedNum; + CopyMem ( + PchPolicy->SmbusConfig.RsvdSmbusAddressTable, + SmBusReservedTable, + SmBusReservedNum + ); + } + + // + // SATA Config + // + PchPolicy->SataConfig.SataMode =3D PchRcVariables->SataInterfaceMode; + MaxSataPorts =3D GetPchMaxSataPortNum (); + + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->SataTestMode =3D=3D TRUE) + { + PchPolicy->SataConfig.PortSettings[Index].Enable =3D TRUE; + } else { + PchPolicy->SataConfig.PortSettings[Index].Enable =3D PchRcVariables-= >SataPort[Index]; + } + PchPolicy->SataConfig.PortSettings[Index].HotPlug =3D PchRcVa= riables->SataHotPlug[Index]; + PchPolicy->SataConfig.PortSettings[Index].SpinUp =3D PchRcVa= riables->SataSpinUp[Index]; + PchPolicy->SataConfig.PortSettings[Index].External =3D PchRcVa= riables->SataExternal[Index]; + PchPolicy->SataConfig.PortSettings[Index].DevSlp =3D PchRcVa= riables->PxDevSlp[Index]; + PchPolicy->SataConfig.PortSettings[Index].EnableDitoConfig =3D PchRcVa= riables->EnableDitoConfig[Index]; + PchPolicy->SataConfig.PortSettings[Index].DmVal =3D PchRcVa= riables->DmVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].DitoVal =3D PchRcVa= riables->DitoVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].SolidStateDrive =3D PchRcVa= riables->SataType[Index]; + } + + if (PchPolicy->SataConfig.SataMode =3D=3D PchSataModeRaid) { + PchPolicy->SataConfig.Rst.RaidAlternateId =3D PchRcVariables->SataAlte= rnateId; + PchPolicy->SataConfig.Rst.EfiRaidDriverLoad =3D PchRcVariables->SataRa= idLoadEfiDriver; + } + PchPolicy->SataConfig.Rst.Raid0 =3D PchRcVariables->SataRaidR0; + PchPolicy->SataConfig.Rst.Raid1 =3D PchRcVariables->SataRaidR1; + PchPolicy->SataConfig.Rst.Raid10 =3D PchRcVariables->SataRaidR1= 0; + PchPolicy->SataConfig.Rst.Raid5 =3D PchRcVariables->SataRaidR5; + PchPolicy->SataConfig.Rst.Irrt =3D PchRcVariables->SataRaidIr= rt; + PchPolicy->SataConfig.Rst.OromUiBanner =3D PchRcVariables->SataRaidOu= b; + PchPolicy->SataConfig.Rst.HddUnlock =3D PchRcVariables->SataHddlk; + PchPolicy->SataConfig.Rst.LedLocate =3D PchRcVariables->SataLedl; + PchPolicy->SataConfig.Rst.IrrtOnly =3D PchRcVariables->SataRaidIo= oe; + PchPolicy->SataConfig.Rst.SmartStorage =3D PchRcVariables->SataRaidSr= t; + PchPolicy->SataConfig.Rst.OromUiDelay =3D PchRcVariables->SataRaidOr= omDelay; + + PchPolicy->SataConfig.EnclosureSupport =3D TRUE; + + PchPolicy->SataConfig.SalpSupport =3D PchRcVariables->SataSalp; + PchPolicy->SataConfig.TestMode =3D PchRcVariables->SataTestMode; + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + if ((PchRcVariables->PchSata =3D=3D TRUE) && (PchRcVariables->SataInte= rfaceMode =3D=3D PchSataModeRaid)) { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = =3D PchRcVariables->RstPcieStorageRemap[Index]; + PchPolicy->SataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = =3D PchRcVariables->RstPcieStorageRemapPort[Index]; + } else { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = =3D FALSE; + } + } + + // + // sSATA Config + // + PchPolicy->sSataConfig.SataMode =3D PchRcVariables->sSataInterfaceMode; + MaxSataPorts =3D GetPchMaxsSataPortNum (); + + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->sSataTestMode =3D=3D TRUE) + { + PchPolicy->sSataConfig.PortSettings[Index].Enable =3D TRUE; + } else { + PchPolicy->sSataConfig.PortSettings[Index].Enable =3D PchRcVariables= ->sSataPort[Index]; + } + PchPolicy->sSataConfig.PortSettings[Index].HotPlug =3D PchRcV= ariables->sSataHotPlug[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SpinUp =3D PchRcV= ariables->sSataSpinUp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].External =3D PchRcV= ariables->sSataExternal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DevSlp =3D PchRcV= ariables->sPxDevSlp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].EnableDitoConfig =3D PchRcV= ariables->sEnableDitoConfig[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DmVal =3D PchRcV= ariables->sDmVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DitoVal =3D PchRcV= ariables->sDitoVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SolidStateDrive =3D PchRcV= ariables->sSataType[Index]; + } + + if (PchPolicy->sSataConfig.SataMode =3D=3D PchSataModeRaid) { + PchPolicy->sSataConfig.Rst.RaidAlternateId =3D PchRcVariables->sSataAl= ternateId; + PchPolicy->sSataConfig.Rst.EfiRaidDriverLoad =3D PchRcVariables->sSata= RaidLoadEfiDriver; + } + PchPolicy->sSataConfig.Rst.Raid0 =3D PchRcVariables->sSataRaid= R0; + PchPolicy->sSataConfig.Rst.Raid1 =3D PchRcVariables->sSataRaid= R1; + PchPolicy->sSataConfig.Rst.Raid10 =3D PchRcVariables->sSataRaid= R10; + PchPolicy->sSataConfig.Rst.Raid5 =3D PchRcVariables->sSataRaid= R5; + PchPolicy->sSataConfig.Rst.Irrt =3D PchRcVariables->sSataRaid= Irrt; + PchPolicy->sSataConfig.Rst.OromUiBanner =3D PchRcVariables->sSataRaid= Oub; + PchPolicy->sSataConfig.Rst.HddUnlock =3D PchRcVariables->sSataHddl= k; + PchPolicy->sSataConfig.Rst.LedLocate =3D PchRcVariables->sSataLedl; + PchPolicy->sSataConfig.Rst.IrrtOnly =3D PchRcVariables->sSataRaid= Iooe; + PchPolicy->sSataConfig.Rst.SmartStorage =3D PchRcVariables->sSataRaid= Srt; + PchPolicy->sSataConfig.Rst.OromUiDelay =3D PchRcVariables->sSataRaid= OromDelay; + + PchPolicy->sSataConfig.EnclosureSupport =3D TRUE; + + PchPolicy->sSataConfig.SalpSupport =3D PchRcVariables->sSataSalp; + PchPolicy->sSataConfig.TestMode =3D PchRcVariables->sSataTestMode; + // + // Initiate DMI Configuration + // + if (SetupVariables->PcieDmiAspm !=3D PLATFORM_POR) { + if (SetupVariables->PcieDmiAspm !=3D 0xFF) { + PchPolicy->DmiConfig.DmiAspm =3D TRUE; + } else { + PchPolicy->DmiConfig.DmiAspm =3D FALSE; + } + } + DEBUG((DEBUG_ERROR, "PchPolicy->DmiConfig.DmiAspm =3D%x\n", PchPolicy->D= miConfig.DmiAspm)); + // + // PCI express config + // + PchPolicy->PcieConfig.DisableRootPortClockGating =3D SetupVariables= ->PcieClockGating; + PchPolicy->PcieConfig.EnablePort8xhDecode =3D PchRcVariables->= PcieRootPort8xhDecode; + PchPolicy->PcieConfig.PchPciePort8xhDecodePortIndex =3D PchRcVariables->= Pcie8xhDecodePortIndex; + PchPolicy->PcieConfig.EnablePeerMemoryWrite =3D PchRcVariables->= PcieRootPortPeerMemoryWriteEnable; + PchPolicy->PcieConfig.ComplianceTestMode =3D PchRcVariables->= PcieComplianceTestMode; + + for (Index =3D 0; Index < GetPchMaxPciePortNum (); Index++) { + PchPolicy->PcieConfig.RootPort[Index].Enable = =3D PchRcVariables->PcieRootPortEn[Index]; + PchPolicy->PcieConfig.RootPort[Index].PhysicalSlotNumber = =3D (UINT8) Index; + if (PchRcVariables->PchPcieGlobalAspm > PchPcieAspmDisabled) { + // Disabled a.k.a. Per individual port + PchPolicy->PcieConfig.RootPort[Index].Aspm = =3D PchRcVariables->PchPcieGlobalAspm; + } else { + PchPolicy->PcieConfig.RootPort[Index].Aspm = =3D PchRcVariables->PcieRootPortAspm[Index]; + } + PchPolicy->PcieConfig.RootPort[Index].L1Substates = =3D PchRcVariables->PcieRootPortL1SubStates[Index]; + PchPolicy->PcieConfig.RootPort[Index].AcsEnabled = =3D PchRcVariables->PcieRootPortACS[Index]; + PchPolicy->PcieConfig.RootPort[Index].PmSci = =3D PchRcVariables->PcieRootPortPMCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].HotPlug = =3D PchRcVariables->PcieRootPortHPE[Index]; + PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = =3D PchRcVariables->PcieRootPortAER[Index]; + PchPolicy->PcieConfig.RootPort[Index].UnsupportedRequestReport = =3D PchRcVariables->PcieRootPortURE[Index]; + PchPolicy->PcieConfig.RootPort[Index].FatalErrorReport = =3D PchRcVariables->PcieRootPortFEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].NoFatalErrorReport = =3D PchRcVariables->PcieRootPortNFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].CorrectableErrorReport = =3D PchRcVariables->PcieRootPortCEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnFatalError = =3D PchRcVariables->PcieRootPortSFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnNonFatalError = =3D PchRcVariables->PcieRootPortSNE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnCorrectableError = =3D PchRcVariables->PcieRootPortSCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].TransmitterHalfSwing = =3D PchRcVariables->PcieRootPortTHS[Index]; + PchPolicy->PcieConfig.RootPort[Index].CompletionTimeout = =3D PchRcVariables->PcieRootPortCompletionTimeout[Index]; + PchPolicy->PcieConfig.RootPort[Index].PcieSpeed = =3D PchRcVariables->PcieRootPortSpeed[Index]; + + PchPolicy->PcieConfig.RootPort[Index].MaxPayload = =3D PchRcVariables->PcieRootPortMaxPayLoadSize[Index]; + PchPolicy->PcieConfig.RootPort[Index].Gen3EqPh3Method = =3D PchRcVariables->PcieRootPortEqPh3Method[Index]; + } + + for (Index =3D 0; Index < GetPchMaxPciePortNum (); ++Index) { + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm =3D PchRcVariables->Pc= ieLaneCm[Index]; + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp =3D PchRcVariables->Pc= ieLaneCp[Index]; + } + if (PchRcVariables->PcieSwEqOverride) { + for (Index =3D 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) { + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cm =3D PchRcVariable= s->PcieSwEqCoeffCm[Index]; + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cp =3D PchRcVariable= s->PcieSwEqCoeffCp[Index]; + } + } + + PchPolicy->PcieConfig.MaxReadRequestSize = =3D PchRcVariables->PcieRootPortMaxReadRequestSize; + /// + /// Update Competion Timeout settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16CompletionTimeout = =3D PchRcVariables->PchPcieUX16CompletionTimeout; + PchPolicy->PcieConfig.PchPcieUX8CompletionTimeout = =3D PchRcVariables->PchPcieUX8CompletionTimeout; + /// + /// Update Max Payload Size settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16MaxPayload = =3D PchRcVariables->PchPcieUX16MaxPayloadSize; + PchPolicy->PcieConfig.PchPcieUX8MaxPayload = =3D PchRcVariables->PchPcieUX8MaxPayloadSize; + CopyMem (&VTdSupport, (UINT8 *)PcdGetPtr(PcdSocketIioConfigData) + OFFSE= T_OF(SOCKET_IIO_CONFIGURATION, VTdSupport), sizeof(VTdSupport)); + PchPolicy->PcieConfig.VTdSupport = =3D VTdSupport; + + /// + /// Assign ClkReq signal to root port. (Base 0) + /// For LP, Set 0 - 5 + /// For H, Set 0 - 15 + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be avai= lable for Root Port. (TODO for Purley) + /// + // + // HdAudioConfig + // + PchPolicy->HdAudioConfig.Enable =3D PchRcVariables->PchHdA= udio; + PchPolicy->HdAudioConfig.DspEnable =3D FALSE; + PchPolicy->HdAudioConfig.Pme =3D PchRcVariables->PchHdA= udioPme; + PchPolicy->HdAudioConfig.IoBufferOwnership =3D PchRcVariables->PchHdA= udioIoBufferOwnership; + PchPolicy->HdAudioConfig.IoBufferVoltage =3D PchRcVariables->PchHdA= udioIoBufferVoltage; + PchPolicy->HdAudioConfig.ResetWaitTimer =3D 300; + PchPolicy->HdAudioConfig.IDispCodecDisconnect =3D TRUE; //iDisp is perm= anently disabled + for(Index =3D 0; Index < HDAUDIO_FEATURES; Index++) { + PchPolicy->HdAudioConfig.DspFeatureMask |=3D (UINT32)(PchRcVariables->= PchHdAudioFeature[Index] ? (1 << Index) : 0); + } + + for(Index =3D 0; Index < HDAUDIO_PP_MODULES; Index++) { + PchPolicy->HdAudioConfig.DspPpModuleMask |=3D (UINT32)(PchRcVariables-= >PchHdAudioPostProcessingMod[Index] ? (1 << Index) : 0); + } + + if (PchPolicy->HdAudioConfig.Enable) { + InstallPlatformVerbTables (PchRcVariables->PchHdAudioCodecSelect); + } + + PchPolicy->HdAudioConfig.VcType =3D PchRcVariables->RtoHdaVcType; + // + // LockDown + // + + + PchPolicy->LockDownConfig.RtcLock =3D PchRcVariables->PchRtcL= ock; + PchPolicy->LockDownConfig.BiosLock =3D PchRcVariables->PchBios= Lock; + PchPolicy->LockDownConfig.SpiEiss =3D TRUE; + PchPolicy->LockDownConfig.GlobalSmi =3D TRUE; + PchPolicy->LockDownConfig.BiosInterface =3D TRUE; + PchPolicy->LockDownConfig.EvaLockDown =3D PchRcVariables->PchEvaL= ockDown; + PchPolicy->LockDownConfig.GpioLockDown =3D PchRcVariables->PchGpio= LockDown; + PchPolicy->LockDownConfig.TcoLock =3D TRUE; + + if(PchRcVariables->PchP2sbUnlock) { + PchPolicy->P2sbConfig.SbiUnlock =3D TRUE; + PchPolicy->P2sbConfig.PsfUnlock =3D TRUE; + } else { + PchPolicy->P2sbConfig.SbiUnlock =3D FALSE; + PchPolicy->P2sbConfig.PsfUnlock =3D FALSE; + } + PchPolicy->P2sbConfig.P2SbReveal =3D PchRcVariables->PchP2sbDevReveal; + + // + // Update SPI policies + // + PchPolicy->SpiConfig.ShowSpiController =3D TRUE; + + // + // PMC Policy + // + PchPolicy->PmConfig.PmcReadDisable =3D PchRcVariables->PmcReadDisable; + + + if (PchRcVariables->PchAdrEn !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.PchAdrEn =3D PchRcVariables->PchAdrEn; + } + PchPolicy->AdrConfig.AdrGpioSel =3D PchRcVariables->AdrGpioSel; + if (PchRcVariables->AdrHostPartitionReset !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.AdrHostPartitionReset =3D PchRcVariables->AdrHost= PartitionReset; + } + if (PchRcVariables->AdrTimerEn !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.AdrTimerEn =3D PchRcVariables->AdrTimerEn; + } + if (PchRcVariables->AdrTimerVal !=3D ADR_TMR_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrTimerVal =3D PchRcVariables->AdrTimerVal; + } + if (PchRcVariables->AdrMultiplierVal !=3D ADR_MULT_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrMultiplierVal =3D PchRcVariables->AdrMultiplie= rVal; + } + + // + // Thermal Config + // + if ((PchRcVariables->MemoryThermalManagement !=3D FALSE) && + ((PchRcVariables->ExttsViaTsOnBoard !=3D FALSE) || (PchRcVariables->= ExttsViaTsOnDimm !=3D FALSE))) + { + PchPolicy->ThermalConfig.MemoryThrottling.Enable = =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].Pm= syncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].Pm= syncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0= TransmitEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0= TransmitEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].Pi= nSelection =3D 1; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].Pi= nSelection =3D 0; + } else { + PchPolicy->ThermalConfig.MemoryThrottling.Enable =3D FALSE; + } + + // + // IOAPIC Config + // + PchPolicy->IoApicConfig.IoApicEntry24_119 =3D PchRcVariables->PchIoApic2= 4119Entries; + PchPolicy->IoApicConfig.BdfValid =3D 1; + PchPolicy->IoApicConfig.BusNumber =3D 0xF0; + PchPolicy->IoApicConfig.DeviceNumber =3D 0x1F; + PchPolicy->IoApicConfig.FunctionNumber =3D 0; + + + // + // Misc PM Config + // + PchPolicy->PmConfig.PchDeepSxPol =3D PchRcVaria= bles->DeepSxMode; + PchPolicy->PmConfig.WakeConfig.WolEnableOverride =3D PchRcVaria= bles->PchWakeOnLan; + PchPolicy->PmConfig.WakeConfig.WoWlanEnable =3D PchRcVaria= bles->PchWakeOnWlan; + PchPolicy->PmConfig.WakeConfig.WoWlanDeepSxEnable =3D PchRcVaria= bles->PchWakeOnWlanDeepSx; + PchPolicy->PmConfig.WakeConfig.Gp27WakeFromDeepSx =3D PchRcVaria= bles->Gp27WakeFromDeepSx; + PchPolicy->PmConfig.SlpLanLowDc =3D PchRcVaria= bles->PchSlpLanLowDc; + PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts =3D TRUE; + PchPolicy->PmConfig.PciePllSsc =3D PchRcVaria= bles->PciePllSsc; + + PchPolicy->PmConfig.DirtyWarmReset =3D PchRcVaria= bles->Dwr_Enable; + + PchPolicy->PmConfig.StallDirtyWarmReset =3D PchRcVaria= bles->Dwr_Stall; + PchPolicy->PmConfig.Dwr_BmcRootPort =3D PchRcVaria= bles->Dwr_BmcRootPort; + + PchPolicy->PmConfig.PchGbl2HostEn.Bits.PMCGBL =3D PchRcVaria= bles->DwrEn_PMCGBL; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.MEWDT =3D PchRcVaria= bles->DwrEn_MEWDT; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.IEWDT =3D PchRcVaria= bles->DwrEn_IEWDT; + + PchPolicy->PmConfig.Dwr_MeResetPrepDone =3D PchRcVaria= bles->Dwr_MeResetPrepDone; + PchPolicy->PmConfig.Dwr_IeResetPrepDone =3D PchRcVaria= bles->Dwr_IeResetPrepDone; + + // + // DefaultSvidSid Config + // + PchPolicy->PchConfig.SubSystemVendorId =3D V_PCH_INTEL_VENDOR_ID; + PchPolicy->PchConfig.SubSystemId =3D V_PCH_DEFAULT_SID; + PchPolicy->PchConfig.EnableClockSpreadSpec =3D PchRcVariables->EnableCl= ockSpreadSpec; + // + // Thermal Config + // + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = =3D PchRcVariables->PchCrossThrottling; + PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = =3D TRUE; + if (PchRcVariables->ThermalDeviceEnable =3D=3D PchThermalDeviceAuto) { + if (PchStepping () =3D=3D LbgA0) { + PchPolicy->ThermalConfig.ThermalDeviceEnable =3D PchThermalDeviceDis= abled; + } else { + PchPolicy->ThermalConfig.ThermalDeviceEnable =3D PchThermalDeviceEna= bledPci; + } + } else { + PchPolicy->ThermalConfig.ThermalDeviceEnable =3D PchRcVariables->Therm= alDeviceEnable; + } + + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.sSataTT.SuggestedSetting = =3D TRUE; + + // + // DCI (EXI) + // + PchPolicy->DciConfig.DciEn =3D PchRcVariables->PchDciEn; + PchPolicy->DciConfig.DciAutoDetect =3D PchRcVariables->PchDciAutoDetect; + + + // + // Initialize Serial IRQ Config + // + PchPolicy->SerialIrqConfig.SirqEnable =3D TRUE; + PchPolicy->SerialIrqConfig.StartFramePulse =3D PchSfpw4Clk; + if (PchRcVariables->PchSirqMode =3D=3D 0) { + PchPolicy->SerialIrqConfig.SirqMode =3D PchQuietMode; + } else { + PchPolicy->SerialIrqConfig.SirqMode =3D PchContinuousMode; + } + + // + // Port 61h emulation + // + PchPolicy->Port61hSmmConfig.Enable =3D TRUE; + + // + // DMI configuration + // + PchPolicy->DmiConfig.DmiLinkDownHangBypass =3D PchRcVariables->DmiLinkDo= wnHangBypass; + PchPolicy->DmiConfig.DmiStopAndScreamEnable =3D PchRcVariables->PcieDmiS= topAndScreamEnable; + + // + // Update Pch Usb Config + // + Usb20OverCurrentMappings =3D (PCH_USB_OVERCURRENT_PIN *)(UINTN)PcdGet64 = (PcdUsb20OverCurrentMappings); + Usb30OverCurrentMappings =3D (PCH_USB_OVERCURRENT_PIN *)(UINTN)PcdGet64 = (PcdUsb30OverCurrentMappings); + UpdatePchUsbConfig ( + &PchPolicy->UsbConfig, + SetupVariables, + PchRcVariables, + Usb20OverCurrentMappings, + Usb30OverCurrentMappings + ); + =20 + // + // Update TraceHub config based on setup options + // + PchPolicy->PchTraceHubConfig.EnableMode =3D PchRcVariables->Trace= HubEnableMode; + + switch (PchRcVariables->MemRegion0BufferSize) { + case 0: + PchPolicy->PchTraceHubConfig.MemReg0Size =3D 0; // No memory + break; + case 1: + PchPolicy->PchTraceHubConfig.MemReg0Size =3D 0x100000; // 1MB + break; + case 2: + PchPolicy->PchTraceHubConfig.MemReg0Size =3D 0x800000; // 8MB + break; + case 3: + PchPolicy->PchTraceHubConfig.MemReg0Size =3D 0x4000000; // 64MB + break; + } + + switch (PchRcVariables->MemRegion1BufferSize) { + case 0: + PchPolicy->PchTraceHubConfig.MemReg1Size =3D 0; // No memory + break; + case 1: + PchPolicy->PchTraceHubConfig.MemReg1Size =3D 0x100000; // 1MB + break; + case 2: + PchPolicy->PchTraceHubConfig.MemReg1Size =3D 0x800000; // 8MB + break; + case 3: + PchPolicy->PchTraceHubConfig.MemReg1Size =3D 0x4000000; // 64MB + break; + } + + PchPolicy->PchTraceHubConfig.PchTraceHubHide =3D PchRcVariables->PchTr= aceHubHide; + return EFI_SUCCESS; +} + + +/** + Performs silicon pre-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + =20 + The input Policy must be returned by SiliconPolicyDonePreMem(). + =20 + 1) In FSP path, the input Policy should be FspmUpd. + A platform may use this API to update the FSPM UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPM UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *Policy + ) +{ + UpdatePeiPchPolicy (Policy); + return Policy; +} + +/** + Performs silicon post-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + =20 + The input Policy must be returned by SiliconPolicyDonePostMem(). + =20 + 1) In FSP path, the input Policy should be FspsUpd. + A platform may use this API to update the FSPS UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPS UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *Policy + ) +{ + return Policy; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicy= UpdateLib/SiliconPolicyUpdateLib.inf b/Platform/Intel/PurleyOpenBoardPkg/Po= licy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf new file mode 100644 index 0000000000..2df0ca977f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateL= ib/SiliconPolicyUpdateLib.inf @@ -0,0 +1,54 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyUpdateLib + FILE_GUID =3D 6EA9585C-3C15-47da-9FFC-25E9E4EA4D0C + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyUpdateLib + +[Sources] + SiliconPolicyUpdateLib.c + PchPolicyUpdateUsb.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[LibraryClasses] + HobLib + MmPciLib + IoLib + PcdLib + PchGbeLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData + gOemSkuTokenSpaceGuid.PcdUsb20OverCurrentMappings + gOemSkuTokenSpaceGuid.PcdUsb30OverCurrentMappings + + gOemSkuTokenSpaceGuid.PcdSetupData + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData + +[FixedPcd] + +[Ppis] + +[Guids] + gEfiAcpiVariableGuid --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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b=jIxe9nwDFJqry+ytmp8J8qAxeerd3GSygSl7E3d0VuDkOCduMSFRGe27z+M9hlVBze32lJgVrkFDpG8WyXGnz9U0Yr536x6PDvamoAO4fLEIoMe93KH5YvT9tMh1JuAuGMO5fpxEG1UelF5SoUtX/Bg/aRacdtN4qiTVR5BJkTA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620726541; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=/RaZ0nk7182KFFc438F7iJBSZUhNVX7jQHRZ3RoW8ZU=; b=ZYCeEY1ucAACmgMZdf654KXWxFjBg8nX6zT5WV7pdbH7dOurROibg691jkLForcZaGJXGikIqS4O6hlIVRd9UtXrwDV333iKNTBZK0lexccp9DThIbfgkd6UxI2eAU63mVrkX39PrPSulIcy/i6OoBNpGveyGgT+G7lhb90z6T8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74977+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1620726541302243.8094082130292; Tue, 11 May 2021 02:49:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7EgrYY1788612x0H4LD6LDPi; Tue, 11 May 2021 02:49:00 -0700 X-Received: from mga09.intel.com (mga09.intel.com []) by mx.groups.io with SMTP id smtpd.web08.10551.1620726526771786264 for ; Tue, 11 May 2021 02:48:53 -0700 IronPort-SDR: SA5x8hvj7xQYrItKxyqrJEBRabfSbyxel/mTsixmzB1lkTuhSULq3PzecvB2IlAZvKFIvonyQn CPOYdGVlHOyA== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="199469640" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="199469640" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:50 -0700 IronPort-SDR: Q/zt1m50aHN1OLqdydI7l+XRapRrVO/FpaQLXOLU1dmhtyS3wcmIE9FxAFOpvOsVuxJCSnDgKk nzM96cexfz5Q== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436573980" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:48 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 09/18] PurleyOpenBoardPkg: Add modules Date: Tue, 11 May 2021 02:48:17 -0700 Message-Id: <20210511094826.12495-10-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: GwaUNynftlPsQEquWgUBuLnAx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726540; bh=SzF6mvZ1c2c+N4SnVu9ADHeRz50MsMfJ+wvjx/vPm9M=; h=Cc:Date:From:Reply-To:Subject:To; b=F9a6aIjk1kH6LYDzL7Y/OJ88k6xNmi+UzeH9sflpNTdkeiiSG3As5sZ9Bu5XVQPz1io mZhAVs2fe64NqhHd5bawETTw1hye4qjRXTUHEnxnvMDy34867wTJOSWWZCqMDpWJxUhco jxC4BzJsQU/cSqTR8nMBFGCodudoursMG0g= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../DxePlatformBootManagerLib/BdsPlatform.c | 1354 +++++++++++++++++ .../DxePlatformBootManagerLib/BdsPlatform.h | 184 +++ .../DxePlatformBootManagerLib.inf | 96 ++ .../DxePlatformBootManagerLib/MemoryTest.c | 85 ++ .../PlatformBootOption.c | 559 +++++++ .../Pci/PciPlatform/IoApic.h | 22 + .../Pci/PciPlatform/PciIovPlatformPolicy.c | 96 ++ .../Pci/PciPlatform/PciIovPlatformPolicy.h | 51 + .../Pci/PciPlatform/PciPlatform.c | 183 +++ .../Pci/PciPlatform/PciPlatform.h | 201 +++ .../Pci/PciPlatform/PciPlatform.inf | 70 + .../Pci/PciPlatform/PciPlatformHooks.c | 527 +++++++ .../Pci/PciPlatform/PciPlatformHooks.h | 24 + .../Pci/PciPlatform/PciSupportLib.c | 103 ++ .../Pci/PciPlatform/PciSupportLib.h | 44 + .../Policy/IioUdsDataDxe/IioUdsDataDxe.c | 86 ++ .../Policy/IioUdsDataDxe/IioUdsDataDxe.h | 81 + .../Policy/IioUdsDataDxe/IioUdsDataDxe.inf | 36 + .../PlatformCpuPolicy/PlatformCpuPolicy.c | 654 ++++++++ .../PlatformCpuPolicy/PlatformCpuPolicy.inf | 80 + .../Policy/S3NvramSave/S3NvramSave.c | 256 ++++ .../Policy/S3NvramSave/S3NvramSave.h | 31 + .../Policy/S3NvramSave/S3NvramSave.inf | 59 + .../Policy/SystemBoard/SystemBoardCommon.c | 625 ++++++++ .../Policy/SystemBoard/SystemBoardPei.c | 255 ++++ .../Policy/SystemBoard/SystemBoardPei.h | 182 +++ .../Policy/SystemBoard/SystemBoardPei.inf | 76 + 27 files changed, 6020 insertions(+) create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Int= el/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Int= el/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Int= el/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootMana= gerLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Int= el/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/MemoryTest.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Int= el/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/PlatformBootOption.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/IoApi= c.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIo= vPlatformPolicy.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIo= vPlatformPolicy.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPl= atform.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPl= atform.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPl= atform.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPl= atformHooks.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPl= atformHooks.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSu= pportLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSu= pportLib.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/= IioUdsDataDxe.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/= IioUdsDataDxe.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/= IioUdsDataDxe.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPol= icy/PlatformCpuPolicy.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPol= icy/PlatformCpuPolicy.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3= NvramSave.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3= NvramSave.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3= NvramSave.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/Sy= stemBoardCommon.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/Sy= stemBoardPei.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/Sy= stemBoardPei.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/Sy= stemBoardPei.inf diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinP= latformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.c b/Platform/I= ntel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/= DxePlatformBootManagerLib/BdsPlatform.c new file mode 100644 index 0000000000..b3b8ceba6f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatform= Pkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.c @@ -0,0 +1,1354 @@ +/** @file + This file include all platform action which can be customized by IBV/OEM. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "BdsPlatform.h" +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_BOOT_MODE gBootMode; + +BOOLEAN gPPRequireUIConfirm; + +extern UINTN mBootMenuOptionNumber; + +GLOBAL_REMOVE_IF_UNREFERENCED USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboa= rdDevicePath =3D { + { + { + MESSAGING_DEVICE_PATH, + MSG_USB_CLASS_DP, + { + (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)), + (UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8) + } + }, + 0xffff, // VendorId + 0xffff, // ProductId + CLASS_HID, // DeviceClass + SUBCLASS_BOOT, // DeviceSubClass + PROTOCOL_KEYBOARD // DeviceProtocol + }, + gEndEntire +}; + +// +// Internal shell mode +// +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellModeColumn; +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellModeRow; +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellHorizontalResolution; +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellVerticalResolution; +// +// BDS Platform Functions +// + +BOOLEAN +IsMorBitSet ( + VOID + ) +{ + UINTN MorControl; + EFI_STATUS Status; + UINTN DataSize; + + // + // Check if the MOR bit is set. + // + DataSize =3D sizeof (MorControl); + Status =3D gRT->GetVariable ( + MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME, + &gEfiMemoryOverwriteControlDataGuid, + NULL, + &DataSize, + &MorControl + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, " PlatformBootMangerLib: gEfiMemoryOverwriteContro= lDataGuid doesn't exist!!***\n")); + MorControl =3D 0; + } else { + DEBUG ((DEBUG_INFO, " PlatformBootMangerLib: Get the gEfiMemoryOverwri= teControlDataGuid =3D %x!!***\n", MorControl)); + } + + return (BOOLEAN) (MorControl & 0x01); +} + +VOID +DumpDevicePath ( + IN CHAR16 *Name, + IN EFI_DEVICE_PATH *DevicePath + ) +{ + CHAR16 *Str; + + Str =3D ConvertDevicePathToText(DevicePath, TRUE, TRUE); + DEBUG ((DEBUG_INFO, "%s: %s\n", Name, Str)); + if (Str !=3D NULL) { + FreePool (Str); + } +} + +/** + An empty function to pass error checking of CreateEventEx (). + + This empty function ensures that EVT_NOTIFY_SIGNAL_ALL is error + checked correctly since it is now mapped into CreateEventEx() in UEFI 2.= 0. + + @param Event Event whose notification function is being= invoked. + @param Context The pointer to the notification function's= context, + which is implementation-dependent. +**/ +VOID +EFIAPI +InternalBdsEmptyCallbackFuntion ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + return; +} + +VOID +ExitPmAuth ( + VOID + ) +{ + EFI_HANDLE Handle; + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + DEBUG((DEBUG_INFO,"ExitPmAuth ()- Start\n")); + // + // Prepare S3 information, this MUST be done before ExitPmAuth/EndOfDxe + // + // + // Since PI1.2.1, we need signal EndOfDxe as ExitPmAuth + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + InternalBdsEmptyCallbackFuntion, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + ASSERT_EFI_ERROR (Status); + gBS->SignalEvent (EndOfDxeEvent); + gBS->CloseEvent (EndOfDxeEvent); + DEBUG((DEBUG_INFO,"All EndOfDxe callbacks have returned successfully\n")= ); + + // + // NOTE: We need install DxeSmmReadyToLock directly here because many bo= ot script is added via ExitPmAuth/EndOfDxe callback. + // If we install them at same callback, these boot script will be reject= ed because BootScript Driver runs first to lock them done. + // So we seperate them to be 2 different events, ExitPmAuth is last chan= ce to let platform add boot script. DxeSmmReadyToLock will + // make boot script save driver lock down the interface. + // + Handle =3D NULL; + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiDxeSmmReadyToLockProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + DEBUG((DEBUG_INFO,"ExitPmAuth ()- End\n")); +} + +VOID +ConnectRootBridge ( + BOOLEAN Recursive + ) +{ + UINTN RootBridgeHandleCount; + EFI_HANDLE *RootBridgeHandleBuffer; + UINTN RootBridgeIndex; + + RootBridgeHandleCount =3D 0; + gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciRootBridgeIoProtocolGuid, + NULL, + &RootBridgeHandleCount, + &RootBridgeHandleBuffer + ); + for (RootBridgeIndex =3D 0; RootBridgeIndex < RootBridgeHandleCount; Roo= tBridgeIndex++) { + gBS->ConnectController (RootBridgeHandleBuffer[RootBridgeIndex], NULL,= NULL, Recursive); + } +} + + +/** + Return whether the device is trusted console. + + @param Device The device to be tested. + + @retval TRUE The device can be trusted. + @retval FALSE The device cannot be trusted. +**/ +BOOLEAN +IsTrustedConsole ( + IN CONSOLE_TYPE ConsoleType, + IN EFI_DEVICE_PATH_PROTOCOL *Device + ) +{ + VOID *TrustedConsoleDevicepath; + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; + EFI_DEVICE_PATH_PROTOCOL *Instance; + UINTN Size; + EFI_DEVICE_PATH_PROTOCOL *ConsoleDevice; + + if (Device =3D=3D NULL) { + return FALSE; + } + + ConsoleDevice =3D DuplicateDevicePath(Device); + + TrustedConsoleDevicepath =3D NULL; + + switch (ConsoleType) { + case ConIn: + TrustedConsoleDevicepath =3D PcdGetPtr (PcdTrustedConsoleInputDevicePa= th); + break; + case ConOut: + // + // Check GOP and remove last node + // + TempDevicePath =3D ConsoleDevice; + while (!IsDevicePathEndType (TempDevicePath)) { + if (DevicePathType (TempDevicePath) =3D=3D ACPI_DEVICE_PATH && + DevicePathSubType (TempDevicePath) =3D=3D ACPI_ADR_DP) { + SetDevicePathEndNode (TempDevicePath); + break; + } + TempDevicePath =3D NextDevicePathNode (TempDevicePath); + } + + TrustedConsoleDevicepath =3D PcdGetPtr (PcdTrustedConsoleOutputDeviceP= ath); + break; + default: + ASSERT(FALSE); + break; + } + + TempDevicePath =3D TrustedConsoleDevicepath; + do { + Instance =3D GetNextDevicePathInstance (&TempDevicePath, &Size); + if (Instance =3D=3D NULL) { + break; + } + + if (CompareMem (ConsoleDevice, Instance, Size - END_DEVICE_PATH_LENGTH= ) =3D=3D 0) { + FreePool (Instance); + FreePool (ConsoleDevice); + return TRUE; + } + + FreePool (Instance); + } while (TempDevicePath !=3D NULL); + + FreePool (ConsoleDevice); + + return FALSE; +} + +BOOLEAN +IsUsbShortForm ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + if ((DevicePathType (DevicePath) =3D=3D MESSAGING_DEVICE_PATH) && + ((DevicePathSubType (DevicePath) =3D=3D MSG_USB_CLASS_DP) || (Device= PathSubType (DevicePath) =3D=3D MSG_USB_WWID_DP)) ) { + return TRUE; + } + + return FALSE; +} + +/** + Connect the USB short form device path. + + @param DevicePath USB short form device path + + @retval EFI_SUCCESS Successfully connected the USB device + @retval EFI_NOT_FOUND Cannot connect the USB device + @retval EFI_INVALID_PARAMETER The device path is invalid. +**/ +EFI_STATUS +ConnectUsbShortFormDevicePath ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + EFI_STATUS Status; + EFI_HANDLE *Handles; + UINTN HandleCount; + UINTN Index; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT8 Class[3]; + BOOLEAN AtLeastOneConnected; + + // + // Check the passed in parameters + // + if (DevicePath =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (!IsUsbShortForm (DevicePath)) { + return EFI_INVALID_PARAMETER; + } + + // + // Find the usb host controller firstly, then connect with the remaining= device path + // + AtLeastOneConnected =3D FALSE; + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &Handles + ); + for (Index =3D 0; Index < HandleCount; Index++) { + Status =3D gBS->HandleProtocol ( + Handles[Index], + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo + ); + if (!EFI_ERROR (Status)) { + // + // Check whether the Pci device is the wanted usb host controller + // + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x09, 3, &Cla= ss); + if (!EFI_ERROR (Status) && + ((PCI_CLASS_SERIAL =3D=3D Class[2]) && (PCI_CLASS_SERIAL_USB =3D= =3D Class[1])) + ) { + Status =3D gBS->ConnectController ( + Handles[Index], + NULL, + DevicePath, + FALSE + ); + if (!EFI_ERROR(Status)) { + AtLeastOneConnected =3D TRUE; + } + } + } + } + + return AtLeastOneConnected ? EFI_SUCCESS : EFI_NOT_FOUND; +} + +/** + Update the ConIn variable with USB Keyboard device path,if its not alrea= dy exists in ConIn +**/ +VOID +EnumUsbKeyboard ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "[EnumUsbKeyboard]\n")); + EfiBootManagerUpdateConsoleVariable (ConIn, (EFI_DEVICE_PATH_PROTOCOL *)= &gUsbClassKeyboardDevicePath, NULL); + =20 + // + // Append Usb Keyboard short form DevicePath into "ConInDev" + // + EfiBootManagerUpdateConsoleVariable (ConInDev, (EFI_DEVICE_PATH_PROTOCOL= *) &gUsbClassKeyboardDevicePath, NULL); +} + +BOOLEAN +IsVgaHandle ( + IN EFI_HANDLE Handle + ) +{ + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_TYPE00 Pci; + EFI_STATUS Status; + + Status =3D gBS->HandleProtocol ( + Handle, + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (!EFI_ERROR (Status)) { + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint32, + 0, + sizeof (Pci) / sizeof (UINT32), + &Pci + ); + if (!EFI_ERROR (Status)) { + if (IS_PCI_VGA (&Pci) || IS_PCI_OLD_VGA (&Pci)) { + return TRUE; + } + } + } + return FALSE; +} + +EFI_HANDLE +IsVideoController ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + EFI_DEVICE_PATH_PROTOCOL *DupDevicePath; + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; + EFI_STATUS Status; + EFI_HANDLE DeviceHandle; + + DupDevicePath =3D DuplicateDevicePath (DevicePath); + ASSERT (DupDevicePath !=3D NULL); + if (DupDevicePath =3D=3D NULL) { + return NULL; + } + + TempDevicePath =3D DupDevicePath; + Status =3D gBS->LocateDevicePath ( + &gEfiDevicePathProtocolGuid, + &TempDevicePath, + &DeviceHandle + ); + FreePool (DupDevicePath); + if (EFI_ERROR (Status)) { + return NULL; + } + + if (IsVgaHandle (DeviceHandle)) { + return DeviceHandle; + } else { + return NULL; + } +} + +BOOLEAN +IsGopDevicePath ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + while (!IsDevicePathEndType (DevicePath)) { + if (DevicePathType (DevicePath) =3D=3D ACPI_DEVICE_PATH && + DevicePathSubType (DevicePath) =3D=3D ACPI_ADR_DP) { + return TRUE; + } + DevicePath =3D NextDevicePathNode (DevicePath); + } + return FALSE; +} + +/** + Remove all GOP device path instance from DevicePath and add the Gop to t= he DevicePath. +**/ +EFI_DEVICE_PATH_PROTOCOL * +UpdateGopDevicePath ( + EFI_DEVICE_PATH_PROTOCOL *DevicePath, + EFI_DEVICE_PATH_PROTOCOL *Gop + ) +{ + UINTN Size; + UINTN GopSize; + EFI_DEVICE_PATH_PROTOCOL *Temp; + EFI_DEVICE_PATH_PROTOCOL *Return; + EFI_DEVICE_PATH_PROTOCOL *Instance; + BOOLEAN Exist; + + Exist =3D FALSE; + Return =3D NULL; + GopSize =3D GetDevicePathSize (Gop); + do { + Instance =3D GetNextDevicePathInstance (&DevicePath, &Size); + if (Instance =3D=3D NULL) { + break; + } + if (!IsGopDevicePath (Instance) || + (Size =3D=3D GopSize && CompareMem (Instance, Gop, GopSize) =3D=3D= 0) + ) { + if (Size =3D=3D GopSize && CompareMem (Instance, Gop, GopSize) =3D= =3D 0) { + Exist =3D TRUE; + } + Temp =3D Return; + Return =3D AppendDevicePathInstance (Return, Instance); + if (Temp !=3D NULL) { + FreePool (Temp); + } + } + FreePool (Instance); + } while (DevicePath !=3D NULL); + + if (!Exist) { + Temp =3D Return; + Return =3D AppendDevicePathInstance (Return, Gop); + if (Temp !=3D NULL) { + FreePool (Temp); + } + } + return Return; +} + +/** + Get Graphics Controller Handle. + + @retval GraphicsController Successfully located + @retval NULL Failed to locate +**/ +EFI_HANDLE +EFIAPI +GetGraphicsController ( + IN BOOLEAN NeedTrustedConsole + ) +{ + EFI_STATUS Status; + UINTN Index; + EFI_HANDLE *PciHandles; + UINTN PciHandlesSize; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &PciHandlesSize, + &PciHandles + ); + if (EFI_ERROR (Status)) { + return NULL; + } + + for (Index =3D 0; Index < PciHandlesSize; Index++) { + Status =3D gBS->HandleProtocol ( + PciHandles[Index], + &gEfiDevicePathProtocolGuid, + (VOID **) &DevicePath + ); + if (EFI_ERROR(Status)) { + continue; + } + if (!IsVgaHandle (PciHandles[Index])) { + continue; + } + if ((NeedTrustedConsole && IsTrustedConsole (ConOut, DevicePath)) || + ((!NeedTrustedConsole) && (!IsTrustedConsole (ConOut, DevicePath))= )) { + return PciHandles[Index]; + } + } + + return NULL; +} + +VOID +UpdateGraphicConOut ( + IN BOOLEAN NeedTrustedConsole + ) +{ + EFI_HANDLE GraphicsControllerHandle; + EFI_DEVICE_PATH_PROTOCOL *GopDevicePath; + EFI_DEVICE_PATH_PROTOCOL *ConOutDevicePath; + EFI_DEVICE_PATH_PROTOCOL *UpdatedConOutDevicePath; + + // + // Update ConOut variable + // + GraphicsControllerHandle =3D GetGraphicsController (NeedTrustedConsole); + if (GraphicsControllerHandle !=3D NULL) { + // + // Connect the GOP driver + // + gBS->ConnectController (GraphicsControllerHandle, NULL, NULL, TRUE); + + // + // Get the GOP device path + // NOTE: We may get a device path that contains Controller node in it. + // + GopDevicePath =3D EfiBootManagerGetGopDevicePath (GraphicsControllerHa= ndle); + if (GopDevicePath !=3D NULL) { + GetEfiGlobalVariable2 (L"ConOut", (VOID **)&ConOutDevicePath, NULL); + UpdatedConOutDevicePath =3D UpdateGopDevicePath (ConOutDevicePath, G= opDevicePath); + if (ConOutDevicePath !=3D NULL) { + FreePool (ConOutDevicePath); + } + FreePool (GopDevicePath); + gRT->SetVariable ( + L"ConOut", + &gEfiGlobalVariableGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACC= ESS | EFI_VARIABLE_BOOTSERVICE_ACCESS, + GetDevicePathSize (UpdatedConOutDevicePath), + UpdatedConOutDevicePath + ); + } + } +} + +VOID +AddConsoleVariable ( + IN CONSOLE_TYPE ConsoleType, + IN EFI_DEVICE_PATH *ConsoleDevicePath + ) +{ + EFI_DEVICE_PATH *TempDevicePath; + EFI_DEVICE_PATH *Instance; + UINTN Size; + EFI_HANDLE GraphicsControllerHandle; + EFI_DEVICE_PATH *GopDevicePath; + + TempDevicePath =3D ConsoleDevicePath; + do { + Instance =3D GetNextDevicePathInstance (&TempDevicePath, &Size); + if (Instance =3D=3D NULL) { + break; + } + =20 + switch (ConsoleType) { + case ConIn: + if (IsUsbShortForm (Instance)) { + // + // Append Usb Keyboard short form DevicePath into "ConInDev" + // + EfiBootManagerUpdateConsoleVariable (ConInDev, Instance, NULL); + } + EfiBootManagerUpdateConsoleVariable (ConsoleType, Instance, NULL); + break; + case ConOut: + GraphicsControllerHandle =3D IsVideoController (Instance); + if (GraphicsControllerHandle =3D=3D NULL) { + EfiBootManagerUpdateConsoleVariable (ConsoleType, Instance, NULL); + } else { + // + // Connect the GOP driver + // + gBS->ConnectController (GraphicsControllerHandle, NULL, NULL, TRUE= ); + // + // Get the GOP device path + // NOTE: We may get a device path that contains Controller node in= it. + // + GopDevicePath =3D EfiBootManagerGetGopDevicePath (GraphicsControll= erHandle); + if (GopDevicePath !=3D NULL) { + EfiBootManagerUpdateConsoleVariable (ConsoleType, GopDevicePath,= NULL); + } + } + break; + default: + ASSERT(FALSE); + break; + } + + FreePool (Instance); + } while (TempDevicePath !=3D NULL); +} + +/** + The function connects the trusted consoles. +**/ +VOID +ConnectTrustedConsole ( + VOID + ) +{ + EFI_DEVICE_PATH_PROTOCOL *Consoles; + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; + EFI_DEVICE_PATH_PROTOCOL *Instance; + EFI_DEVICE_PATH_PROTOCOL *Next; + UINTN Size; + UINTN Index; + EFI_HANDLE Handle; + EFI_STATUS Status; + CHAR16 *ConsoleVar[] =3D {L"ConIn", L"ConOut"}; + VOID *TrustedConsoleDevicepath; + + TrustedConsoleDevicepath =3D PcdGetPtr (PcdTrustedConsoleInputDevicePath= ); + DumpDevicePath (L"TrustedConsoleIn", TrustedConsoleDevicepath); + TrustedConsoleDevicepath =3D PcdGetPtr (PcdTrustedConsoleOutputDevicePat= h); + DumpDevicePath (L"TrustedConsoleOut", TrustedConsoleDevicepath); + + for (Index =3D 0; Index < sizeof (ConsoleVar) / sizeof (ConsoleVar[0]); = Index++) { + + GetEfiGlobalVariable2 (ConsoleVar[Index], (VOID **)&Consoles, NULL); + + TempDevicePath =3D Consoles; + do { + Instance =3D GetNextDevicePathInstance (&TempDevicePath, &Size); + if (Instance =3D=3D NULL) { + break; + } + if (IsTrustedConsole (Index, Instance)) { + if (IsUsbShortForm (Instance)) { + ConnectUsbShortFormDevicePath (Instance); + } else { + for (Next =3D Instance; !IsDevicePathEnd (Next); Next =3D NextDe= vicePathNode (Next)) { + if (DevicePathType (Next) =3D=3D ACPI_DEVICE_PATH && DevicePat= hSubType (Next) =3D=3D ACPI_ADR_DP) { + break; + } else if (DevicePathType (Next) =3D=3D HARDWARE_DEVICE_PATH && + DevicePathSubType (Next) =3D=3D HW_CONTROLLER_DP && + DevicePathType (NextDevicePathNode (Next)) =3D=3D A= CPI_DEVICE_PATH && + DevicePathSubType (NextDevicePathNode (Next)) =3D= =3D ACPI_ADR_DP + ) { + break; + } + } + if (!IsDevicePathEnd (Next)) { + SetDevicePathEndNode (Next); + Status =3D EfiBootManagerConnectDevicePath (Instance, &Handle); + if (!EFI_ERROR (Status)) { + gBS->ConnectController (Handle, NULL, NULL, TRUE); + } + } else { + EfiBootManagerConnectDevicePath (Instance, NULL); + } + } + } + FreePool (Instance); + } while (TempDevicePath !=3D NULL); + + if (Consoles !=3D NULL) { + FreePool (Consoles); + } + } +} + +/** + The function connects the trusted Storages. +**/ +VOID +ConnectTrustedStorage ( + VOID + ) +{ + VOID *TrustedStorageDevicepath; + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; + EFI_DEVICE_PATH_PROTOCOL *Instance; + UINTN Size; + EFI_DEVICE_PATH_PROTOCOL *TempStorageDevicePath; + EFI_STATUS Status; + EFI_HANDLE DeviceHandle; + + TrustedStorageDevicepath =3D PcdGetPtr (PcdTrustedStorageDevicePath); + DumpDevicePath (L"TrustedStorage", TrustedStorageDevicepath); + + TempDevicePath =3D TrustedStorageDevicepath; + do { + Instance =3D GetNextDevicePathInstance (&TempDevicePath, &Size); + if (Instance =3D=3D NULL) { + break; + } + + EfiBootManagerConnectDevicePath (Instance, NULL); + + TempStorageDevicePath =3D Instance; + + Status =3D gBS->LocateDevicePath ( + &gEfiDevicePathProtocolGuid, + &TempStorageDevicePath, + &DeviceHandle + ); + if (!EFI_ERROR (Status)) { + gBS->ConnectController (DeviceHandle, NULL, NULL, FALSE); + } + + FreePool (Instance); + } while (TempDevicePath !=3D NULL); +} + +/** + The function connects the trusted consoles and then call the PP processi= ng library interface. +**/ +VOID +ProcessTcgPp ( + VOID + ) +{ + gPPRequireUIConfirm |=3D Tcg2PhysicalPresenceLibNeedUserConfirm(); + + if (gPPRequireUIConfirm) { + ConnectTrustedConsole (); + } + + Tcg2PhysicalPresenceLibProcessRequest (NULL); +} + +/** + The function connects the trusted storage to perform TPerReset. +**/ +VOID +ProcessTcgMor ( + VOID + ) +{ + if (IsMorBitSet ()) { + ConnectTrustedConsole(); + ConnectTrustedStorage(); + } +} + +/** + Check if current BootCurrent variable is internal shell boot option. + + @retval TRUE BootCurrent is internal shell. + @retval FALSE BootCurrent is not internal shell. +**/ +BOOLEAN +BootCurrentIsInternalShell ( + VOID + ) +{ + UINTN VarSize; + UINT16 BootCurrent; + CHAR16 BootOptionName[16]; + UINT8 *BootOption; + UINT8 *Ptr; + BOOLEAN Result; + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; + EFI_DEVICE_PATH_PROTOCOL *LastDeviceNode; + EFI_GUID *GuidPoint; + + BootOption =3D NULL; + Result =3D FALSE; + + // + // Get BootCurrent variable + // + VarSize =3D sizeof (UINT16); + Status =3D gRT->GetVariable ( + L"BootCurrent", + &gEfiGlobalVariableGuid, + NULL, + &VarSize, + &BootCurrent + ); + if (EFI_ERROR (Status)) { + return FALSE; + } + + // + // Create boot option Bootxxxx from BootCurrent + // + UnicodeSPrint (BootOptionName, sizeof(BootOptionName), L"Boot%04X", Boot= Current); + + GetEfiGlobalVariable2 (BootOptionName, (VOID **) &BootOption, &VarSize); + if (BootOption =3D=3D NULL || VarSize =3D=3D 0) { + return FALSE; + } + + Ptr =3D BootOption; + Ptr +=3D sizeof (UINT32); + Ptr +=3D sizeof (UINT16); + Ptr +=3D StrSize ((CHAR16 *) Ptr); + TempDevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *) Ptr; + LastDeviceNode =3D TempDevicePath; + while (!IsDevicePathEnd (TempDevicePath)) { + LastDeviceNode =3D TempDevicePath; + TempDevicePath =3D NextDevicePathNode (TempDevicePath); + } + GuidPoint =3D EfiGetNameGuidFromFwVolDevicePathNode ( + (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) LastDeviceNode + ); + if ((GuidPoint !=3D NULL) && + ((CompareGuid (GuidPoint, &gUefiShellFileGuid))) + ) { + // + // if this option is internal shell, return TRUE + // + Result =3D TRUE; + } + + if (BootOption !=3D NULL) { + FreePool (BootOption); + BootOption =3D NULL; + } + + return Result; +} + +/** + This function will change video resolution and text mode + for internl shell when internal shell is launched. + + @param None. + + @retval EFI_SUCCESS Mode is changed successfully. + @retval Others Mode failed to changed. +**/ +EFI_STATUS +EFIAPI +ChangeModeForInternalShell ( + VOID + ) +{ + EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput; + EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *SimpleTextOut; + UINTN SizeOfInfo; + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info; + UINT32 MaxGopMode; + UINT32 MaxTextMode; + UINT32 ModeNumber; + UINTN HandleCount; + EFI_HANDLE *HandleBuffer; + EFI_STATUS Status; + UINTN Index; + UINTN CurrentColumn; + UINTN CurrentRow; + + Status =3D gBS->HandleProtocol ( + gST->ConsoleOutHandle, + &gEfiGraphicsOutputProtocolGuid, + (VOID**)&GraphicsOutput + ); + if (EFI_ERROR (Status)) { + GraphicsOutput =3D NULL; + } + + Status =3D gBS->HandleProtocol ( + gST->ConsoleOutHandle, + &gEfiSimpleTextOutProtocolGuid, + (VOID**)&SimpleTextOut + ); + if (EFI_ERROR (Status)) { + SimpleTextOut =3D NULL; + } + + if ((GraphicsOutput =3D=3D NULL) || (SimpleTextOut =3D=3D NULL)) { + return EFI_UNSUPPORTED; + } + + MaxGopMode =3D GraphicsOutput->Mode->MaxMode; + MaxTextMode =3D SimpleTextOut->Mode->MaxMode; + + // + // 1. If current video resolution is same with new video resolution, + // video resolution need not be changed. + // 1.1. If current text mode is same with new text mode, text mode ne= ed not be change. + // 1.2. If current text mode is different with new text mode, text mo= de need be change to new text mode. + // 2. If current video resolution is different with new video resolution= , we need restart whole console drivers. + // + for (ModeNumber =3D 0; ModeNumber < MaxGopMode; ModeNumber++) { + Status =3D GraphicsOutput->QueryMode ( + GraphicsOutput, + ModeNumber, + &SizeOfInfo, + &Info + ); + if (!EFI_ERROR (Status)) { + if ((Info->HorizontalResolution =3D=3D mShellHorizontalResolution) && + (Info->VerticalResolution =3D=3D mShellVerticalResolution)) { + if ((GraphicsOutput->Mode->Info->HorizontalResolution =3D=3D mShel= lHorizontalResolution) && + (GraphicsOutput->Mode->Info->VerticalResolution =3D=3D mShellV= erticalResolution)) { + // + // If current video resolution is same with new resolution, + // then check if current text mode is same with new text mode. + // + Status =3D SimpleTextOut->QueryMode (SimpleTextOut, SimpleTextOu= t->Mode->Mode, &CurrentColumn, &CurrentRow); + ASSERT_EFI_ERROR (Status); + if (CurrentColumn =3D=3D mShellModeColumn && CurrentRow =3D=3D m= ShellModeRow) { + // + // Current text mode is same with new text mode, text mode nee= d not be change. + // + FreePool (Info); + return EFI_SUCCESS; + } else { + // + // Current text mode is different with new text mode, text mod= e need be change to new text mode. + // + for (Index =3D 0; Index < MaxTextMode; Index++) { + Status =3D SimpleTextOut->QueryMode (SimpleTextOut, Index, &= CurrentColumn, &CurrentRow); + if (!EFI_ERROR(Status)) { + if ((CurrentColumn =3D=3D mShellModeColumn) && (CurrentRow= =3D=3D mShellModeRow)) { + // + // New text mode is supported, set it. + // + Status =3D SimpleTextOut->SetMode (SimpleTextOut, Index); + ASSERT_EFI_ERROR (Status); + // + // Update text mode PCD. + // + Status =3D PcdSet32S (PcdConOutColumn, mShellModeColumn); + ASSERT_EFI_ERROR (Status); + + Status =3D PcdSet32S (PcdConOutRow, mShellModeRow); + ASSERT_EFI_ERROR (Status); + + FreePool (Info); + return EFI_SUCCESS; + } + } + } + if (Index =3D=3D MaxTextMode) { + // + // If new text mode is not supported, return error. + // + FreePool (Info); + return EFI_UNSUPPORTED; + } + } + } else { + FreePool (Info); + // + // If current video resolution is not same with the new one, set= new video resolution. + // In this case, the driver which produces simple text out need = be restarted. + // + Status =3D GraphicsOutput->SetMode (GraphicsOutput, ModeNumber); + if (!EFI_ERROR (Status)) { + // + // Set PCD to restart GraphicsConsole and Consplitter to chang= e video resolution + // and produce new text mode based on new resolution. + // + Status =3D PcdSet32S (PcdVideoHorizontalResolution, mShellHori= zontalResolution); + ASSERT_EFI_ERROR (Status); + + Status =3D PcdSet32S (PcdVideoVerticalResolution, mShellVertic= alResolution); + ASSERT_EFI_ERROR (Status); + + Status =3D PcdSet32S (PcdConOutColumn, mShellModeColumn); + ASSERT_EFI_ERROR (Status); + + Status =3D PcdSet32S (PcdConOutRow, mShellModeRow); + ASSERT_EFI_ERROR (Status); + + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiSimpleTextOutProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (!EFI_ERROR (Status)) { + for (Index =3D 0; Index < HandleCount; Index++) { + gBS->DisconnectController (HandleBuffer[Index], NULL, NULL= ); + } + for (Index =3D 0; Index < HandleCount; Index++) { + gBS->ConnectController (HandleBuffer[Index], NULL, NULL, T= RUE); + } + if (HandleBuffer !=3D NULL) { + FreePool (HandleBuffer); + } + break; + } + } + } + } + FreePool (Info); + } + } + + if (ModeNumber =3D=3D MaxGopMode) { + // + // If the new resolution is not supported, return error. + // + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** + ReadyToBoot callback to set video and text mode for internal shell boot. + That will not connect USB controller while CSM and FastBoot are disabled= , we need to connect them + before booting to Shell for showing USB devices in Shell. + + When FastBoot is enabled and Windows Console is the chosen Console behav= ior, input devices will not be connected + by default. Hence, when booting to EFI shell, connecting input consoles = are required. + + @param Event Pointer to this event + @param Context Event hanlder private data + + @retval None. +**/ +VOID +EFIAPI +OnReadyToBootCallBack ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + DEBUG ((EFI_D_INFO, "OnReadyToBootCallBack\n")); + + if (BootCurrentIsInternalShell ()) { + + ChangeModeForInternalShell (); + EfiBootManagerConnectAllDefaultConsoles(); + gDS->Dispatch (); + } +} + +/** + Platform Bds init. Incude the platform firmware vendor, revision + and so crc check. +**/ +VOID +EFIAPI +PlatformBootManagerBeforeConsole ( + VOID + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *VarConOut; + EFI_DEVICE_PATH_PROTOCOL *VarConIn; + EFI_EVENT Event; + + DEBUG ((EFI_D_INFO, "PlatformBootManagerBeforeConsole\n")); + + Status =3D EFI_SUCCESS; + + // + // Get user defined text mode for internal shell only once. + // + mShellHorizontalResolution =3D PcdGet32 (PcdSetupVideoHorizontalResoluti= on); + mShellVerticalResolution =3D PcdGet32 (PcdSetupVideoVerticalResolution= ); + mShellModeColumn =3D PcdGet32 (PcdSetupConOutColumn); + mShellModeRow =3D PcdGet32 (PcdSetupConOutRow); + + if (PcdGetBool (PcdUpdateConsoleInBds) =3D=3D TRUE) { + // + // Create event to set proper video resolution and text mode for inter= nal shell. + // + Status =3D EfiCreateEventReadyToBootEx ( + TPL_CALLBACK, + OnReadyToBootCallBack, + NULL, + &Event + ); + ASSERT_EFI_ERROR (Status); + + // + // Connect Root Bridge to make PCI BAR resource allocated and all PciI= o created + // + ConnectRootBridge (FALSE); + + // + // Fill ConIn/ConOut in Full Configuration boot mode + // + DEBUG ((DEBUG_INFO, "PlatformBootManagerInit - %x\n", gBootMode)); + + if (gBootMode =3D=3D BOOT_WITH_FULL_CONFIGURATION || + gBootMode =3D=3D BOOT_WITH_DEFAULT_SETTINGS || + gBootMode =3D=3D BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS || + gBootMode =3D=3D BOOT_IN_RECOVERY_MODE) { + + GetEfiGlobalVariable2 (L"ConOut", (VOID **)&VarConOut, NULL); if (= VarConOut !=3D NULL) { FreePool (VarConOut); } + GetEfiGlobalVariable2 (L"ConIn", (VOID **)&VarConIn, NULL); if (V= arConIn !=3D NULL) { FreePool (VarConIn); } + + // + // Only fill ConIn/ConOut when ConIn/ConOut is empty because we may = drop to Full Configuration boot mode in non-first boot + // + if (VarConOut =3D=3D NULL || VarConIn =3D=3D NULL) { + if (PcdGetSize (PcdTrustedConsoleOutputDevicePath) >=3D sizeof(EFI= _DEVICE_PATH_PROTOCOL)) { + AddConsoleVariable (ConOut, PcdGetPtr (PcdTrustedConsoleOutputDe= vicePath)); + } + if (PcdGetSize (PcdTrustedConsoleInputDevicePath) >=3D sizeof(EFI_= DEVICE_PATH_PROTOCOL)) { + AddConsoleVariable (ConIn, PcdGetPtr (PcdTrustedConsoleInputDevi= cePath)); + } + } + } + + EnumUsbKeyboard (); + // + // For trusted console it must be handled here. + // + UpdateGraphicConOut (TRUE); + + // + // Dynamically register hot key: F2/F7/Enter + // + RegisterDefaultBootOption (); + RegisterStaticHotkey (); + } + =20 + PERF_START_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7010); + if (PcdGetBool (PcdTpm2Enable)) { + ProcessTcgPp (); + ProcessTcgMor (); + } + PERF_END_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7011); + + // + // We should make all UEFI memory and GCD information populated before E= xitPmAuth. + // SMM may consume these information. + // + MemoryTest((EXTENDMEM_COVERAGE_LEVEL) PcdGet32 (PcdPlatformMemoryCheckLe= vel)); + + PERF_START_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7020); + ExitPmAuth (); + PERF_END_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7021); + + // + // Dispatch the deferred 3rd party images. + // + EfiBootManagerDispatchDeferredImages (); + + // + // For non-trusted console it must be handled here. + // + if (PcdGetBool (PcdUpdateConsoleInBds) =3D=3D TRUE) { + UpdateGraphicConOut (FALSE); + } +} + + +/** + Connect with predeined platform connect sequence, + the OEM/IBV can customize with their own connect sequence. + + @param[in] BootMode Boot mode of this boot. +**/ +VOID +ConnectSequence ( + IN EFI_BOOT_MODE BootMode + ) +{ + EfiBootManagerConnectAll (); +} + +/** + The function is to consider the boot order which is not in our expectati= on. + In the case that we need to re-sort the boot option. + + @retval TRUE Need to sort Boot Option. + @retval FALSE Don't need to sort Boot Option. +**/ +BOOLEAN +IsNeedSortBootOption ( + VOID + ) +{ + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + + BootOptions =3D EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOpti= onTypeBoot); + + // + // If setup is the first priority in boot option, we need to sort boot o= ption. + // + if ((BootOptionCount > 1) && + (((StrnCmp (BootOptions->Description, L"Enter Setup", StrLen (L"Ente= r Setup"))) =3D=3D 0) || + ((StrnCmp (BootOptions->Description, L"BootManagerMenuApp", StrLen = (L"BootManagerMenuApp"))) =3D=3D 0))) { + return TRUE; + } + + return FALSE; +} + +/** + The function will excute with as the platform policy, current policy + is driven by boot mode. IBV/OEM can customize this code for their specif= ic + policy action. + + @param DriverOptionList - The header of the driver option link list + @param BootOptionList - The header of the boot option link list + @param ProcessCapsules - A pointer to ProcessCapsules() + @param BaseMemoryTest - A pointer to BaseMemoryTest() +**/ +VOID +EFIAPI +PlatformBootManagerAfterConsole ( + VOID + ) +{ + EFI_BOOT_MODE LocalBootMode; + + DEBUG ((EFI_D_INFO, "PlatformBootManagerAfterConsole\n")); + + // + // Get current Boot Mode + // + LocalBootMode =3D gBootMode; + DEBUG ((DEBUG_INFO, "Current local bootmode - %x\n", LocalBootMode)); + + // + // Go the different platform policy with different boot mode + // Notes: this part code can be change with the table policy + // + switch (LocalBootMode) { + + case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES: + case BOOT_WITH_MINIMAL_CONFIGURATION: + case BOOT_ON_S4_RESUME: + // + // Perform some platform specific connect sequence + // + if (PcdGetBool (PcdFastBoot) =3D=3D FALSE) { + PERF_START_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7050); + ConnectSequence (LocalBootMode); + PERF_END_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7051); + } + + break; + + case BOOT_WITH_FULL_CONFIGURATION: + case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS: + case BOOT_WITH_DEFAULT_SETTINGS: + default: + // + // Perform some platform specific connect sequence + // + ConnectSequence (LocalBootMode); + + // + // Only in Full Configuration boot mode we do the enumeration of boot = device + // + // + // Dispatch all but Storage Oprom explicitly, because we assume Int13T= hunk driver is there. + // + EfiBootManagerRefreshAllBootOption (); + + if (IsNeedSortBootOption()) { + EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBoo= tOption); + } + // + // PXE boot option may appear after boot option enumeration + // + + break; + } + + if (PcdGetBool (PcdFastBoot) =3D=3D FALSE) { + Print (L"Press F7 for BootMenu!\n"); + + EfiBootManagerRefreshAllBootOption (); + EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBootO= ption); + } +} + +/** + The function is called when no boot option could be launched, + including platform recovery options and options pointing to applications + built into firmware volumes. + + If this function returns, BDS attempts to enter an infinite loop. +**/ +VOID +EFIAPI +PlatformBootManagerUnableToBoot ( + VOID + ) +{ + EFI_STATUS Status; + EFI_BOOT_MANAGER_LOAD_OPTION BootDeviceList; + CHAR16 OptionName[sizeof ("Boot####")]; + + if (mBootMenuOptionNumber =3D=3D LoadOptionNumberUnassigned) { + return; + } + UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", mBootMenuOp= tionNumber); + Status =3D EfiBootManagerVariableToLoadOption (OptionName, &BootDeviceLi= st); + if (EFI_ERROR (Status)) { + return; + } + for (;;) { + EfiBootManagerBoot (&BootDeviceList); + } +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinP= latformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.h b/Platform/I= ntel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/= DxePlatformBootManagerLib/BdsPlatform.h new file mode 100644 index 0000000000..360a00d7d7 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatform= Pkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.h @@ -0,0 +1,184 @@ +/** @file + Header file for BDS Platform specific code + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _BDS_PLATFORM_H +#define _BDS_PLATFORM_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/// +/// ConnectType +/// +#define CONSOLE_OUT 0x00000001 +#define STD_ERROR 0x00000002 +#define CONSOLE_IN 0x00000004 +#define CONSOLE_ALL (CONSOLE_OUT | CONSOLE_IN | STD_ERROR) + +extern EFI_GUID gUefiShellFileGuid; +extern EFI_BOOT_MODE gBootMode; + +#define gPciRootBridge \ + { \ + { \ + ACPI_DEVICE_PATH, \ + ACPI_DP, \ + { \ + (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \ + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \ + }, \ + }, \ + EISA_PNP_ID (0x0A03), \ + 0 \ + } + +#define gEndEntire \ + { \ + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PAT= H_LENGTH, 0 } \ + } + +typedef struct { + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + UINTN ConnectType; +} BDS_CONSOLE_CONNECT_ENTRY; + +// +// Platform Root Bridge +// +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_ROOT_BRIDGE_DEVICE_PATH; + +// +// Below is the platform console device path +// +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + PCI_DEVICE_PATH IsaBridge; + ACPI_HID_DEVICE_PATH Keyboard; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_KEYBOARD_DEVICE_PATH; + +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + PCI_DEVICE_PATH PciDevice; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_ONBOARD_CONTROLLER_DEVICE_PATH; + +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + PCI_DEVICE_PATH Pci0Device; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_PEG_ROOT_CONTROLLER_DEVICE_PATH; + +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + PCI_DEVICE_PATH PciBridge; + PCI_DEVICE_PATH PciDevice; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_PCI_CONTROLLER_DEVICE_PATH; + +// +// Below is the boot option device path +// + +#define CLASS_HID 3 +#define SUBCLASS_BOOT 1 +#define PROTOCOL_KEYBOARD 1 + +typedef struct { + USB_CLASS_DEVICE_PATH UsbClass; + EFI_DEVICE_PATH_PROTOCOL End; +} USB_CLASS_FORMAT_DEVICE_PATH; + +extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePa= th; + +// +// Platform BDS Functions +// + + +/** + Perform the memory test base on the memory test intensive level, + and update the memory resource. + + @param Level The memory test intensive level. + + @retval EFI_STATUS Success test all the system memory and update + the memory resource + +**/ +EFI_STATUS +MemoryTest ( + IN EXTENDMEM_COVERAGE_LEVEL Level + ); + +VOID +ConnectSequence ( + IN EFI_BOOT_MODE BootMode + ); + + +INTN +EFIAPI +CompareBootOption ( + CONST VOID *Left, + CONST VOID *Right + ); + + +VOID +RegisterStaticHotkey ( + VOID + ); +VOID +RegisterDefaultBootOption ( + VOID + ); + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinP= latformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.= inf b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatform= Pkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf new file mode 100644 index 0000000000..5790743565 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatform= Pkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf @@ -0,0 +1,96 @@ +## @file +# Component name for module DxePlatformBootManagerLib +# +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D DxePlatformBootManagerLib + FILE_GUID =3D A6BC385D-59E5-4B77-87D7-200ABAA83C15 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_DRIVER + UEFI_SPECIFICATION_VERSION =3D 2.10 + LIBRARY_CLASS =3D PlatformBootManagerLib|DXE_DRIVER +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# + +[LibraryClasses] + BaseLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseMemoryLib + DebugLib + PcdLib + PrintLib + DevicePathLib + UefiLib + HobLib + DxeServicesLib + DxeServicesTableLib + HiiLib + UefiBootManagerLib + PerformanceLib + TimerLib + Tcg2PhysicalPresenceLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SecurityPkg/SecurityPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUM= ES + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut ## PRO= DUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution ## PRO= DUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution ## PRO= DUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow ## PRO= DUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn ## PRO= DUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn ## CON= SUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow ## CON= SUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution ## CON= SUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution ## CON= SUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand ## PRO= DUCES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformMemoryCheckLevel ## CONSUM= ES + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly ## CONSUM= ES + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdTrustedStorageDevicePath ## CONSU= MES + gPlatformTokenSpaceGuid.PcdUpdateConsoleInBds ## CONSU= MES + gPlatformTokenSpaceGuid.PcdFastBoot ## CONSU= MES + +[Sources] + BdsPlatform.c + BdsPlatform.h + PlatformBootOption.c + MemoryTest.c + +[Protocols] + gEfiPciRootBridgeIoProtocolGuid ## CONSUMES + gEfiPciIoProtocolGuid ## CONSUMES + gEfiCpuIo2ProtocolGuid ## CONSUMES + gEfiDxeSmmReadyToLockProtocolGuid ## PRODUCES + gEfiGenericMemTestProtocolGuid ## CONSUMES + gEfiDiskInfoProtocolGuid ## CONSUMES + gEfiDevicePathToTextProtocolGuid ## CONSUMES + gEfiSimpleTextInputExProtocolGuid ## CONSUMES + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + gEfiFormBrowser2ProtocolGuid ## CONSUMES + gEfiGenericMemTestProtocolGuid ## CONSUMES + +[Guids] + gEfiGlobalVariableGuid ## PRODUCES + gEfiMemoryOverwriteControlDataGuid ## PRODUCES + gEfiEndOfDxeEventGroupGuid ## CONSUMES + +[Depex.common.DXE_DRIVER] + gEfiVariableArchProtocolGuid diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinP= latformPkg/Bds/Library/DxePlatformBootManagerLib/MemoryTest.c b/Platform/In= tel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/D= xePlatformBootManagerLib/MemoryTest.c new file mode 100644 index 0000000000..e6445fecf8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatform= Pkg/Bds/Library/DxePlatformBootManagerLib/MemoryTest.c @@ -0,0 +1,85 @@ +/** @file + Perform the platform memory test + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "BdsPlatform.h" +#include + +/** + Perform the memory test base on the memory test intensive level, + and update the memory resource. + + @param Level The memory test intensive level. + + @retval EFI_STATUS Success test all the system memory and update + the memory resource + +**/ +EFI_STATUS +MemoryTest ( + IN EXTENDMEM_COVERAGE_LEVEL Level + ) +{ + EFI_STATUS Status; + BOOLEAN RequireSoftECCInit; + EFI_GENERIC_MEMORY_TEST_PROTOCOL *GenMemoryTest; + UINT64 TestedMemorySize; + UINT64 TotalMemorySize; + BOOLEAN ErrorOut; + BOOLEAN TestAbort; + + TestedMemorySize =3D 0; + TotalMemorySize =3D 0; + ErrorOut =3D FALSE; + TestAbort =3D FALSE; + + RequireSoftECCInit =3D FALSE; + + Status =3D gBS->LocateProtocol ( + &gEfiGenericMemTestProtocolGuid, + NULL, + (VOID **) &GenMemoryTest + ); + if (EFI_ERROR (Status)) { + return EFI_SUCCESS; + } + + Status =3D GenMemoryTest->MemoryTestInit ( + GenMemoryTest, + Level, + &RequireSoftECCInit + ); + if (Status =3D=3D EFI_NO_MEDIA) { + // + // The PEI codes also have the relevant memory test code to check the = memory, + // it can select to test some range of the memory or all of them. If P= EI code + // checks all the memory, this BDS memory test will has no not-test me= mory to + // do the test, and then the status of EFI_NO_MEDIA will be returned by + // "MemoryTestInit". So it does not need to test memory again, just re= turn. + // + return EFI_SUCCESS; + } + + if (PcdGetBool (PcdFastBoot) =3D=3D FALSE) { + do { + Status =3D GenMemoryTest->PerformMemoryTest ( + GenMemoryTest, + &TestedMemorySize, + &TotalMemorySize, + &ErrorOut, + TestAbort + ); + if (ErrorOut && (Status =3D=3D EFI_DEVICE_ERROR)) { + ASSERT (0); + } + } while (Status !=3D EFI_NOT_FOUND); + } + + Status =3D GenMemoryTest->Finished (GenMemoryTest); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinP= latformPkg/Bds/Library/DxePlatformBootManagerLib/PlatformBootOption.c b/Pla= tform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/L= ibrary/DxePlatformBootManagerLib/PlatformBootOption.c new file mode 100644 index 0000000000..84aa097d58 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatform= Pkg/Bds/Library/DxePlatformBootManagerLib/PlatformBootOption.c @@ -0,0 +1,559 @@ +/** @file + Driver for Platform Boot Options support. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "BdsPlatform.h" + +#include + +BOOLEAN mContinueBoot =3D FALSE; +BOOLEAN mBootMenuBoot =3D FALSE; +BOOLEAN mPxeBoot =3D FALSE; +BOOLEAN mHotKeypressed =3D FALSE; +EFI_EVENT HotKeyEvent =3D NULL; + +UINTN mBootMenuOptionNumber; + +EFI_DEVICE_PATH_PROTOCOL * +BdsCreateShellDevicePath ( + VOID + ) +/*++ + +Routine Description: + + This function will create a SHELL BootOption to boot. + +Arguments: + + None. + +Returns: + + Shell Device path for booting. + +--*/ +{ + UINTN FvHandleCount; + EFI_HANDLE *FvHandleBuffer; + UINTN Index; + EFI_STATUS Status; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + UINTN Size; + UINT32 AuthenticationStatus; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + VOID *Buffer; + + DevicePath =3D NULL; + Status =3D EFI_SUCCESS; + + DEBUG ((DEBUG_INFO, "BdsCreateShellDevicePath\n")); + gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &FvHandleCount, + &FvHandleBuffer + ); + + for (Index =3D 0; Index < FvHandleCount; Index++) { + gBS->HandleProtocol ( + FvHandleBuffer[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **) &Fv + ); + + Buffer =3D NULL; + Size =3D 0; + Status =3D Fv->ReadSection ( + Fv, + &gUefiShellFileGuid, + EFI_SECTION_PE32, + 0, + &Buffer, + &Size, + &AuthenticationStatus + ); + if (EFI_ERROR (Status)) { + // + // Skip if no shell file in the FV + // + continue; + } else { + // + // Found the shell + // + break; + } + } + + if (EFI_ERROR (Status)) { + // + // No shell present + // + if (FvHandleCount) { + FreePool (FvHandleBuffer); + } + return NULL; + } + // + // Build the shell boot option + // + DevicePath =3D DevicePathFromHandle (FvHandleBuffer[Index]); + + if (FvHandleCount) { + FreePool (FvHandleBuffer); + } + + return DevicePath; +} + + +EFI_STATUS +CreateFvBootOption ( + EFI_GUID *FileGuid, + CHAR16 *Description, + EFI_BOOT_MANAGER_LOAD_OPTION *BootOption, + UINT32 Attributes, + UINT8 *OptionalData, OPTIONAL + UINT32 OptionalDataSize + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + UINT32 AuthenticationStatus; + VOID *Buffer; + UINTN Size; + + if ((BootOption =3D=3D NULL) || (FileGuid =3D=3D NULL) || (Description = =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid); + + if (!CompareGuid (&gUefiShellFileGuid, FileGuid)) { + Status =3D gBS->HandleProtocol ( + gImageHandle, + &gEfiLoadedImageProtocolGuid, + (VOID **) &LoadedImage + ); + if (!EFI_ERROR (Status)) { + Status =3D gBS->HandleProtocol ( + LoadedImage->DeviceHandle, + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **) &Fv + ); + if (!EFI_ERROR (Status)) { + Buffer =3D NULL; + Size =3D 0; + Status =3D Fv->ReadSection ( + Fv, + FileGuid, + EFI_SECTION_PE32, + 0, + &Buffer, + &Size, + &AuthenticationStatus + ); + if (Buffer !=3D NULL) { + FreePool (Buffer); + } + } + } + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + DevicePath =3D AppendDevicePathNode ( + DevicePathFromHandle (LoadedImage->DeviceHandle), + (EFI_DEVICE_PATH_PROTOCOL *) &FileNode + ); + } else { + DevicePath =3D AppendDevicePathNode ( + BdsCreateShellDevicePath (), + (EFI_DEVICE_PATH_PROTOCOL *) &FileNode + ); + } + + Status =3D EfiBootManagerInitializeLoadOption ( + BootOption, + LoadOptionNumberUnassigned, + LoadOptionTypeBoot, + Attributes, + Description, + DevicePath, + OptionalData, + OptionalDataSize + ); + FreePool (DevicePath); + return Status; +} + +EFI_GUID mUiFile =3D { + 0x462CAA21, 0x7614, 0x4503, { 0x83, 0x6E, 0x8A, 0xB6, 0xF4, 0x66, 0x23, = 0x31 } +}; +EFI_GUID mBootMenuFile =3D { + 0xEEC25BDC, 0x67F2, 0x4D95, { 0xB1, 0xD5, 0xF8, 0x1B, 0x20, 0x39, 0xD1, = 0x1D } +}; + + +/** + Return the index of the load option in the load option array. + + The function consider two load options are equal when the + OptionType, Attributes, Description, FilePath and OptionalData are equal. + + @param Key Pointer to the load option to be found. + @param Array Pointer to the array of load options to be found. + @param Count Number of entries in the Array. + + @retval -1 Key wasn't found in the Array. + @retval 0 ~ Count-1 The index of the Key in the Array. +**/ +INTN +PlatformFindLoadOption ( + IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key, + IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array, + IN UINTN Count + ) +{ + UINTN Index; + + for (Index =3D 0; Index < Count; Index++) { + if ((Key->OptionType =3D=3D Array[Index].OptionType) && + (Key->Attributes =3D=3D Array[Index].Attributes) && + (StrCmp (Key->Description, Array[Index].Description) =3D=3D 0) && + (CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSi= ze (Key->FilePath)) =3D=3D 0) && + (Key->OptionalDataSize =3D=3D Array[Index].OptionalDataSize) && + (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->Op= tionalDataSize) =3D=3D 0)) { + return (INTN) Index; + } + } + + return -1; +} + +UINTN +RegisterFvBootOption ( + EFI_GUID *FileGuid, + CHAR16 *Description, + UINTN Position, + UINT32 Attributes, + UINT8 *OptionalData, OPTIONAL + UINT32 OptionalDataSize + ) +{ + EFI_STATUS Status; + UINTN OptionIndex; + EFI_BOOT_MANAGER_LOAD_OPTION NewOption; + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + + NewOption.OptionNumber =3D LoadOptionNumberUnassigned; + Status =3D CreateFvBootOption (FileGuid, Description, &NewOption, Attrib= utes, OptionalData, OptionalDataSize); + if (!EFI_ERROR (Status)) { + BootOptions =3D EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOp= tionTypeBoot); + + OptionIndex =3D PlatformFindLoadOption (&NewOption, BootOptions, BootO= ptionCount); + + if (OptionIndex =3D=3D -1) { + Status =3D EfiBootManagerAddLoadOptionVariable (&NewOption, Position= ); + ASSERT_EFI_ERROR (Status); + } else { + NewOption.OptionNumber =3D BootOptions[OptionIndex].OptionNumber; + } + EfiBootManagerFreeLoadOption (&NewOption); + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); + } + + return NewOption.OptionNumber; +} + + + +VOID +EFIAPI +PlatformBootManagerWaitCallback ( + UINT16 TimeoutRemain + ) +{ + EFI_STATUS Status; + EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *TxtInEx; + EFI_KEY_DATA KeyData; + BOOLEAN PausePressed; + + // + // Pause on PAUSE key + // + Status =3D gBS->HandleProtocol (gST->ConsoleInHandle, &gEfiSimpleTextInp= utExProtocolGuid, (VOID **) &TxtInEx); + ASSERT_EFI_ERROR (Status); + + PausePressed =3D FALSE; + + while (TRUE) { + Status =3D TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyData); + if (EFI_ERROR (Status)) { + break; + } + + if (KeyData.Key.ScanCode =3D=3D SCAN_PAUSE) { + PausePressed =3D TRUE; + break; + } + } + + // + // Loop until non-PAUSE key pressed + // + while (PausePressed) { + Status =3D TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyData); + if (!EFI_ERROR (Status)) { + DEBUG (( + DEBUG_INFO, "[PauseCallback] %x/%x %x/%x\n", + KeyData.Key.ScanCode, KeyData.Key.UnicodeChar, + KeyData.KeyState.KeyShiftState, KeyData.KeyState.KeyToggleState + )); + PausePressed =3D (BOOLEAN) (KeyData.Key.ScanCode =3D=3D SCAN_PAUSE); + } + } +} + + +EFI_GUID gUefiShellFileGuid =3D { 0x7C04A583, 0x9E3E, 0x4f1c, { 0xAD, 0x65= , 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } }; + +#define INTERNAL_UEFI_SHELL_NAME L"Internal UEFI Shell 2.0" +#define UEFI_HARD_DRIVE_NAME L"UEFI Hard Drive" + +VOID +RegisterDefaultBootOption ( + VOID + ) +{ +#if 0 + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; +#endif + UINT16 *ShellData; + UINT32 ShellDataSize; + + ShellData =3D NULL; + ShellDataSize =3D 0; + RegisterFvBootOption (&gUefiShellFileGuid, INTERNAL_UEFI_SHELL_NA= ME, (UINTN) -1, LOAD_OPTION_ACTIVE, (UINT8 *)ShellData, ShellDataSize); + + // + // Boot Menu + // + mBootMenuOptionNumber =3D RegisterFvBootOption (&mBootMenuFile, L"Boot D= evice List", (UINTN) -1, LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | = LOAD_OPTION_HIDDEN, NULL, 0); + + if (mBootMenuOptionNumber =3D=3D LoadOptionNumberUnassigned) { + DEBUG ((DEBUG_INFO, "BootMenuOptionNumber (%d) should not be same to L= oadOptionNumberUnassigned(%d).\n", mBootMenuOptionNumber, LoadOptionNumberU= nassigned)); + } +#if 0 + // + // Boot Manager Menu + // + EfiInitializeFwVolDevicepathNode (&FileNode, &mUiFile); + + gBS->HandleProtocol ( + gImageHandle, + &gEfiLoadedImageProtocolGuid, + (VOID **) &LoadedImage + ); + DevicePath =3D AppendDevicePathNode (DevicePathFromHandle (LoadedImage->= DeviceHandle), (EFI_DEVICE_PATH_PROTOCOL *) &FileNode); +#endif + +} + +VOID +RegisterBootOptionHotkey ( + UINT16 OptionNumber, + EFI_INPUT_KEY *Key, + BOOLEAN Add + ) +{ + EFI_STATUS Status; + + if (!Add) { + // + // No enter hotkey when force to setup or there is no boot option + // + Status =3D EfiBootManagerDeleteKeyOptionVariable (NULL, 0, Key, NULL); + ASSERT (Status =3D=3D EFI_SUCCESS || Status =3D=3D EFI_NOT_FOUND); + } else { + // + // Register enter hotkey for the first boot option + // + Status =3D EfiBootManagerAddKeyOptionVariable (NULL, OptionNumber, 0, = Key,NULL); + ASSERT (Status =3D=3D EFI_SUCCESS || Status =3D=3D EFI_ALREADY_STARTED= ); + } +} + +EFI_STATUS +EFIAPI +DetectKeypressCallback ( + IN EFI_KEY_DATA *KeyData +) +{ + mHotKeypressed =3D TRUE; + + if (HotKeyEvent !=3D NULL) { + gBS->SignalEvent(HotKeyEvent); + } + + return EFI_SUCCESS; +} + +/** + This function is called after all the boot options are enumerated and or= dered properly. +**/ +VOID +RegisterStaticHotkey ( + VOID + ) +{ + + EFI_INPUT_KEY Enter; + EFI_KEY_DATA F2; + EFI_KEY_DATA F7; + BOOLEAN EnterSetup; + EFI_STATUS Status; + EFI_BOOT_MANAGER_LOAD_OPTION BootOption; + + EnterSetup =3D FALSE; + + // + // [Enter] + // + mContinueBoot =3D !EnterSetup; + if (mContinueBoot) { + Enter.ScanCode =3D SCAN_NULL; + Enter.UnicodeChar =3D CHAR_CARRIAGE_RETURN; + EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL); + } + + + // + // [F2]/[F7] + // + F2.Key.ScanCode =3D SCAN_F2; + F2.Key.UnicodeChar =3D CHAR_NULL; + F2.KeyState.KeyShiftState =3D EFI_SHIFT_STATE_VALID; + F2.KeyState.KeyToggleState =3D 0; + Status =3D EfiBootManagerGetBootManagerMenu (&BootOption); + ASSERT_EFI_ERROR (Status); + RegisterBootOptionHotkey ((UINT16) BootOption.OptionNumber, &F2.Key, TRU= E); + EfiBootManagerFreeLoadOption (&BootOption); + + F7.Key.ScanCode =3D SCAN_F7; + F7.Key.UnicodeChar =3D CHAR_NULL; + F7.KeyState.KeyShiftState =3D EFI_SHIFT_STATE_VALID; + F7.KeyState.KeyToggleState =3D 0; + mBootMenuBoot =3D !EnterSetup; + RegisterBootOptionHotkey ((UINT16) mBootMenuOptionNumber, &F7.Key, mBoot= MenuBoot); + +} + +UINT8 +BootOptionType ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + EFI_DEVICE_PATH_PROTOCOL *Node; + EFI_DEVICE_PATH_PROTOCOL *NextNode; + + for (Node =3D DevicePath; !IsDevicePathEndType (Node); Node =3D NextDevi= cePathNode (Node)) { + if (DevicePathType (Node) =3D=3D MESSAGING_DEVICE_PATH) { + // + // Make sure the device path points to the driver device. + // + NextNode =3D NextDevicePathNode (Node); + if (DevicePathSubType(NextNode) =3D=3D MSG_DEVICE_LOGICAL_UNIT_DP) { + // + // if the next node type is Device Logical Unit, which specify the= Logical Unit Number (LUN), + // skip it + // + NextNode =3D NextDevicePathNode (NextNode); + } + if (IsDevicePathEndType (NextNode)) { + if ((DevicePathType (Node) =3D=3D MESSAGING_DEVICE_PATH)) { + return DevicePathSubType (Node); + } else { + return MSG_SATA_DP; + } + } + } + } + + return (UINT8) -1; +} + +/** + Returns the priority number. + OptionType EFI + ------------------------------------ + PXE 2 + DVD 4 + USB 6 + NVME 7 + HDD 8 + EFI Shell 9 + Others 100 + + @param BootOption +**/ +UINTN +BootOptionPriority ( + CONST EFI_BOOT_MANAGER_LOAD_OPTION *BootOption + ) +{ + // + // EFI boot options + // + switch (BootOptionType (BootOption->FilePath)) { + case MSG_MAC_ADDR_DP: + case MSG_VLAN_DP: + case MSG_IPv4_DP: + case MSG_IPv6_DP: + return 2; + + case MSG_SATA_DP: + case MSG_ATAPI_DP: + case MSG_UFS_DP: + case MSG_NVME_NAMESPACE_DP: + return 4; + + case MSG_USB_DP: + return 6; + + } + if (StrCmp (BootOption->Description, INTERNAL_UEFI_SHELL_NAME) =3D=3D = 0) { + if (PcdGetBool (PcdBootToShellOnly)) { + return 0; + } + return 9; + } + if (StrCmp (BootOption->Description, UEFI_HARD_DRIVE_NAME) =3D=3D 0) { + return 8; + } + return 100; +} + +INTN +EFIAPI +CompareBootOption ( + CONST VOID *Left, + CONST VOID *Right + ) +{ + return BootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Left) - + BootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Right); +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/IoApic.h b/P= latform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/IoApic.h new file mode 100644 index 0000000000..3ec3baa207 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/IoApic.h @@ -0,0 +1,22 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _IOAPIC_H_ +#define _IOAPIC_H_ + +#define EFI_IO_APIC_INDEX_OFFSET 0x00 +#define EFI_IO_APIC_DATA_OFFSET 0x10 +#define EFI_IO_APIC_IRQ_ASSERTION_OFFSET 0x20 +#define EFI_IO_APIC_EOI_OFFSET 0x40 + +#define EFI_IO_APIC_ID_REGISTER 0x0 +#define EFI_IO_APIC_ID_BITSHIFT 24 +#define EFI_IO_APIC_VER_REGISTER 0x1 +#define EFI_IO_APIC_BOOT_CONFIG_REGISTER 0x3 +#define EFI_IO_APIC_FSB_INT_DELIVERY 0x1 + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatfo= rmPolicy.c b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatfo= rmPolicy.c new file mode 100644 index 0000000000..0b941ccb07 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatformPolic= y.c @@ -0,0 +1,96 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include "PciPlatform.h" +#include + +#ifdef EFI_PCI_IOV_SUPPORT + +/** + + The GetSystemLowestPageSize() function retrieves the system lowest pag= e size. + =20 + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROT= OCOL instance. + @param SystemLowestPageSize - The system lowest page size. (This syste= m supports a + page size of 2^(n+12) if bit n is set.) + =20 + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - SystemLowestPageSize is NULL. + =20 +**/ +EFI_STATUS +EFIAPI +GetSystemLowestPageSize ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT UINT32 *SystemLowestPageSize +) +{ + UINT8 SystemPageSize; =20 + + CopyMem (&SystemPageSize, (UINT8 *)PcdGetPtr(PcdSetupData) + OFFSET_OF(S= YSTEM_CONFIGURATION, SystemPageSize), sizeof(UINT8)); + =20 + if (SystemLowestPageSize !=3D NULL) { + // + // Page size is 4K + // + //*SystemLowestPageSize =3D 1; + *SystemLowestPageSize =3D SystemPageSize; + } + return EFI_SUCCESS; +} + +/** + + The GetIovPlatformPolicy() function retrieves the platform policy rega= rding PCI IOV. + =20 + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL ins= tance. + @param PciIovPolicy - The platform policy for PCI IOV configuration. + =20 + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - PciPolicy is NULL. + =20 +**/ +EFI_STATUS +EFIAPI=20 +GetIovPlatformPolicy ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_IOV_PLATFORM_POLICY *PciIovPolicy +) +{ + UINT8 PolicyEnable; + UINT8 ARIEnable; + UINT8 SRIOVEnable; + UINT8 MRIOVEnable; + + PolicyEnable =3D 0; + =20 + CopyMem (&ARIEnable, (UINT8 *)PcdGetPtr(PcdSetupData) + OFFSET_OF(SYSTEM= _CONFIGURATION, ARIEnable), sizeof(UINT8)); + CopyMem (&SRIOVEnable, (UINT8 *)PcdGetPtr(PcdSetupData) + OFFSET_OF(SYST= EM_CONFIGURATION, SRIOVEnable), sizeof(UINT8)); + CopyMem (&MRIOVEnable, (UINT8 *)PcdGetPtr(PcdSetupData) + OFFSET_OF(SYST= EM_CONFIGURATION, MRIOVEnable), sizeof(UINT8)); + + if (ARIEnable =3D=3D TRUE) { + PolicyEnable =3D PolicyEnable | EFI_PCI_IOV_POLICY_ARI; + } + + if (SRIOVEnable =3D=3D TRUE) { + PolicyEnable =3D PolicyEnable | EFI_PCI_IOV_POLICY_SRIOV; + } + + if (MRIOVEnable =3D=3D TRUE) { + PolicyEnable =3D PolicyEnable | EFI_PCI_IOV_POLICY_MRIOV; + } + =20 + if (PciIovPolicy !=3D NULL) { + //*PciIovPolicy =3D EFI_PCI_IOV_POLICY_ARI | EFI_PCI_IOV_POLICY_SRIOV; + *PciIovPolicy =3D PolicyEnable; + } + return EFI_SUCCESS; +} + +#endif + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatfo= rmPolicy.h b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatfo= rmPolicy.h new file mode 100644 index 0000000000..f7a8cb06a0 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatformPolic= y.h @@ -0,0 +1,51 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PCI_IOV_PLATFORM_POLICY_H_ +#define PCI_IOV_PLATFORM_POLICY_H_ + +/** + + The GetSystemLowestPageSize() function retrieves the system lowest pag= e size. + =20 + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROT= OCOL instance. + @param SystemLowestPageSize - The system lowest page size. (This syste= m supports a + page size of 2^(n+12) if bit n is set.) + =20 + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - SystemLowestPageSize is NULL. + =20 +**/ +EFI_STATUS +EFIAPI +GetSystemLowestPageSize ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT UINT32 *SystemLowestPageSize +) +; + + +/** + + The GetPlatformPolicy() function retrieves the platform policy regardi= ng PCI IOV. + =20 + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL ins= tance. + @param PciIovPolicy - The platform policy for PCI IOV configuration. + =20 + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - PciPolicy is NULL. + =20 +**/ +EFI_STATUS +EFIAPI=20 +GetIovPlatformPolicy ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_IOV_PLATFORM_POLICY *PciIovPolicy +) +; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.= c b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.c new file mode 100644 index 0000000000..b479ec5992 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.c @@ -0,0 +1,183 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include "PciPlatform.h" +#include +#ifdef EFI_PCI_IOV_SUPPORT +#include "PciIovPlatformPolicy.h" +#endif + +PCI_PLATFORM_PRIVATE_DATA mPciPrivateData; + +BOOLEAN FirstCall =3D TRUE; +UINT8 sSataRaidLoadEfiDriverOption; +UINT8 SataRaidLoadEfiDriverOption; +UINT8 BootNetworkOption; + +/** + + Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO= _ALIAS. + + @param This - The pointer to the Protocol itself. + PciPolicy - the returned Policy. + + @retval EFI_UNSUPPORTED - Function not supported. + @retval EFI_INVALID_PARAMETER - Invalid PciPolicy value. + +**/ +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +{ + if (PciPolicy =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_UNSUPPORTED; +} + +/** + + Return a PCI ROM image for the onboard device represented by PciHandle. + + @param This - Protocol instance pointer. + PciHandle - PCI device to return the ROM image for. + RomImage - PCI Rom Image for onboard device. + RomSize - Size of RomImage in bytes. + + @retval EFI_SUCCESS - RomImage is valid. + @retval EFI_NOT_FOUND - No RomImage. + +**/ +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +{ + return EFI_NOT_FOUND; +} + +/** + + GC_TODO: Add function description + + @param This - GC_TODO: add argument description + @param Function - GC_TODO: add argument description + @param Phase - GC_TODO: add argument description + + @retval EFI_INVALID_PARAMETER - GC_TODO: Add description for return value + @retval EFI_INVALID_PARAMETER - GC_TODO: Add description for return value + @retval EFI_UNSUPPORTED - GC_TODO: Add description for return value + @retval EFI_SUCCESS - GC_TODO: Add description for return value + +**/ +EFI_STATUS +EFIAPI +RegisterPciCallback ( + IN EFI_PCI_CALLBACK_PROTOCOL *This, + IN EFI_PCI_CALLBACK_FUNC Function, + IN EFI_PCI_ENUMERATION_PHASE Phase + ) +{ + LIST_ENTRY *NodeEntry; + PCI_CALLBACK_DATA *PciCallbackData; + + if (Function =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if ( (Phase & (EfiPciEnumerationDeviceScanning | EfiPciEnumerationBusNu= mberAssigned \ + | EfiPciEnumerationResourceAssigned)) =3D=3D 0) { + return EFI_INVALID_PARAMETER;=20 + } + // + // Check if the node has been added + // + NodeEntry =3D GetFirstNode (&mPciPrivateData.PciCallbackList); + while (!IsNull (&mPciPrivateData.PciCallbackList, NodeEntry)) { + PciCallbackData =3D PCI_CALLBACK_DATA_FROM_LINK (NodeEntry); + if (PciCallbackData->Function =3D=3D Function) { + return EFI_UNSUPPORTED; + } + + NodeEntry =3D GetNextNode (&mPciPrivateData.PciCallbackList, NodeEntry= ); + } + + PciCallbackData =3D NULL; + PciCallbackData =3D AllocateZeroPool (sizeof (PCI_CALLBACK_DATA)); + ASSERT (PciCallbackData !=3D NULL); + + if(PciCallbackData !=3D NULL){ + PciCallbackData->Signature =3D PCI_CALLBACK_DATA_SIGNATURE; + PciCallbackData->Function =3D Function; + PciCallbackData->Phase =3D Phase; + InsertTailList (&mPciPrivateData.PciCallbackList, &PciCallbackData->Li= nk); + return EFI_SUCCESS; + } else { + return EFI_UNSUPPORTED; + } +} + + +/** + + Main Entry point of the Pci Platform Driver. + =20 + @param ImageHandle - Handle to the image. + @param SystemTable - Handle to System Table. + =20 + @retval EFI_STATUS - Status of the function calling. + +**/ +EFI_STATUS +EFIAPI +PciPlatformDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + ZeroMem (&mPciPrivateData, sizeof (mPciPrivateData)); + InitializeListHead (&mPciPrivateData.PciCallbackList); + + mPciPrivateData.PciPlatform.PlatformNotify =3D PhaseNotify;=20 + mPciPrivateData.PciPlatform.PlatformPrepController =3D PlatformPrepCont= roller; + mPciPrivateData.PciPlatform.GetPlatformPolicy =3D GetPlatformPolic= y; + mPciPrivateData.PciPlatform.GetPciRom =3D GetPciRom; + mPciPrivateData.PciCallback.RegisterPciCallback =3D RegisterPciCallb= ack; +#ifdef EFI_PCI_IOV_SUPPORT + mPciPrivateData.PciIovPlatform.GetSystemLowestPageSize =3D GetSystemLowe= stPageSize; + mPciPrivateData.PciIovPlatform.GetPlatformPolicy =3D GetIovPlatfor= mPolicy; +#endif + + // + // Install on a new handle =09 + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mPciPrivateData.PciPlatformHandle, + &gEfiPciPlatformProtocolGuid, + &mPciPrivateData.PciPlatform, + &gEfiPciCallbackProtocolGuid, + &mPciPrivateData.PciCallback, +#ifdef EFI_PCI_IOV_SUPPORT + &gEfiPciIovPlatformProtocolGuid, + &mPciPrivateData.PciIovPlatform, +#endif + NULL + ); + + return Status; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.= h b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.h new file mode 100644 index 0000000000..353715688a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.h @@ -0,0 +1,201 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PCI_PLATFORM_H_ +#define PCI_PLATFORM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Global variables for Option ROMs +// + +#define INVALID 0xBD + +#define PCI_CALLBACK_DATA_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'c') + +typedef struct { + UINT32 Signature; + LIST_ENTRY Link; + EFI_PCI_CALLBACK_FUNC Function; + EFI_PCI_ENUMERATION_PHASE Phase; +} PCI_CALLBACK_DATA; + +typedef struct { + EFI_HANDLE PciPlatformHandle; + EFI_HANDLE RootBridgeHandle; + EFI_PCI_PLATFORM_PROTOCOL PciPlatform; + EFI_PCI_CALLBACK_PROTOCOL PciCallback; +#ifdef EFI_PCI_IOV_SUPPORT + EFI_PCI_IOV_PLATFORM_PROTOCOL PciIovPlatform; +#endif + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; + EFI_CPU_IO2_PROTOCOL *CpuIo; + EFI_LIST_ENTRY PciCallbackList; + EFI_PCI_CALLBACK_CONTEXT Context; + EFI_PCI_ENUMERATION_PHASE PciEnumerationPhase; + UINT8 BusAssignedTime; +} PCI_PLATFORM_PRIVATE_DATA; + +#define PCI_CALLBACK_DATA_FROM_LINK(_node) \ + CR ( \ + _node, \ + PCI_CALLBACK_DATA, \ + Link, \ + PCI_CALLBACK_DATA_SIGNATURE \ + ) + +extern PCI_PLATFORM_PRIVATE_DATA mPciPrivateData; +extern EFI_GUID gPchSataEfiLoadProtocolGuid; + +/** + + Perform initialization by the phase indicated. + + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instanc= e. + @param HostBridge - The associated PCI host bridge handle. + @param Phase - The phase of the PCI controller enumeration. + @param ChipsetPhase - Defines the execution phase of the PCI chipset d= river. + + @retval EFI_SUCCESS - Must return with success. + +**/ +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +; + +/** + + The PlatformPrepController() function can be used to notify the platform= driver so that + it can perform platform-specific actions. No specific actions are requir= ed. + Several notification points are defined at this time. More synchronizati= on points may be + added as required in the future. The PCI bus driver calls the platform d= river twice for + every PCI controller-once before the PCI Host Bridge Resource Allocation= Protocol driver + is notified, and once after the PCI Host Bridge Resource Allocation Prot= ocol driver has + been notified. + This member function may not perform any error checking on the input par= ameters. It also + does not return any error codes. If this member function detects any err= or condition, it + needs to handle those errors on its own because there is no way to surfa= ce any errors to + the caller. + + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instanc= e. + @param HostBridge - The associated PCI host bridge handle. + @param RootBridge - The associated PCI root bridge handle. + @param PciAddress - The address of the PCI device on the PCI bus. + @param Phase - The phase of the PCI controller enumeration. + @param ChipsetPhase - Defines the execution phase of the PCI chipset d= river. + + @retval EFI_SUCCESS - The function completed successfully. + +**/ +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +; + +/** + + Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO= _ALIAS. + + @param This - The pointer to the Protocol itself. + PciPolicy - the returned Policy. + + @retval EFI_UNSUPPORTED - Function not supported. + @retval EFI_INVALID_PARAMETER - Invalid PciPolicy value. + +**/ +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +; + +/** + + Return a PCI ROM image for the onboard device represented by PciHandle. + + @param This - Protocol instance pointer. + PciHandle - PCI device to return the ROM image for. + RomImage - PCI Rom Image for onboard device. + RomSize - Size of RomImage in bytes. + + @retval EFI_SUCCESS - RomImage is valid. + @retval EFI_NOT_FOUND - No RomImage. + +**/ +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +; + +/** + + Register a callback during PCI bus enumeration + + @param This - Protocol instance pointer. + @param Function - Callback function pointer. + @param Phase - PCI enumeration phase. + + @retval EFI_SUCCESS - Function has registed successfully + @retval EFI_UNSUPPORTED - The function has been regisered + @retval EFI_InVALID_PARAMETER - The parameter is incorrect + +**/ +EFI_STATUS +EFIAPI +RegisterPciCallback ( + IN EFI_PCI_CALLBACK_PROTOCOL *This, + IN EFI_PCI_CALLBACK_FUNC Function, + IN EFI_PCI_ENUMERATION_PHASE Phase + ) +; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.= inf b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.inf new file mode 100644 index 0000000000..884d151b49 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.inf @@ -0,0 +1,70 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PciPlatform + FILE_GUID =3D E2441B64-7EF4-41fe-B3A3-8CAA7F8D3017 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PciPlatformDriverEntry + +[Sources] + PciPlatform.c + PciPlatform.h + PciPlatformHooks.c + PciPlatformHooks.h + PciIovPlatformPolicy.c + PciIovPlatformPolicy.h + PciSupportLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + IoLib + BaseMemoryLib + DebugLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + HobLib + S3PciLib + PcdLib + +[Protocols] + gEfiPciCallbackProtocolGuid + gEfiCpuIo2ProtocolGuid + gEfiFirmwareVolume2ProtocolGuid + gEfiPciIoProtocolGuid + gEfiPciPlatformProtocolGuid + gEfiIioUdsProtocolGuid + gEfiPciRootBridgeIoProtocolGuid + gEfiPciIovPlatformProtocolGuid + gEfiIioSystemProtocolGuid + gEfiPciHostBridgeResourceAllocationProtocolGuid + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport + gOemSkuTokenSpaceGuid.PcdSetupData + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel + +[Depex] + TRUE + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformH= ooks.c b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks= .c new file mode 100644 index 0000000000..2556d46407 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks.c @@ -0,0 +1,527 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include =20 +#include +#include +#include +#include +#include +#include + +EFI_IIO_UDS_PROTOCOL *mIioUds =3D NULL; +EFI_IIO_SYSTEM_PROTOCOL *IioSystemProtocol =3D NULL; +IIO_GLOBALS *IioGlobalData =3D NULL; + +VOID +ChipsetCallback ( + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_ENUMERATION_PHASE Phase, + EFI_PCI_CALLBACK_CONTEXT *Context + ) +{ + EFI_LIST_ENTRY *NodeEntry; + PCI_CALLBACK_DATA *PciCallbackData; + + // + // Check if the node has been added + // + // DEBUG ((DEBUG_ERROR, "PCI Callback (%d,%d,%d)\n",PciAddress.Bus, PciA= ddress.Device, PciAddress.Function )); + // + Context->PciRootBridgeIo =3D mPciPrivateData.PciRootBridgeIo; + NodeEntry =3D GetFirstNode (&mPciPrivateData.PciCallback= List); + while (!IsNull (&mPciPrivateData.PciCallbackList, NodeEntry)) { + PciCallbackData =3D PCI_CALLBACK_DATA_FROM_LINK (NodeEntry); + if (PciCallbackData->Phase & Phase) { + (PciCallbackData->Function) (RootBridgeHandle, PciAddress, Phase, Co= ntext); + } + + NodeEntry =3D GetNextNode (&mPciPrivateData.PciCallbackList, NodeEntry= ); + } +} + +/** + + GC_TODO: add routine description + + @param StartBus - GC_TODO: add arg description + + @retval EFI_SUCCESS - GC_TODO: add retval description + +**/ +EFI_STATUS +PciTreeTraverse ( + IN UINT8 StartBus + ) +{ + UINT64 PciAddress; + UINT8 Device; + UINT8 Func; + UINT8 SecondaryBus; + BOOLEAN MultiFunc; + + for (Device =3D 0; Device <=3D PCI_MAX_DEVICE; Device++) { + MultiFunc =3D FALSE; + for (Func =3D 0; Func <=3D PCI_MAX_FUNC; Func++) { + if (IsPciDevicePresent ( + mPciPrivateData.PciRootBridgeIo, + &mPciPrivateData.Context.PciHeader, + StartBus, + Device, + Func + )) { + if ((Func =3D=3D 0) && IS_PCI_MULTI_FUNC(&(mPciPrivateData.Context= .PciHeader))) { + MultiFunc =3D TRUE; + } + PciAddress =3D EFI_PCI_ADDRESS (StartBus, Device, Func, 0); + ChipsetCallback ( + mPciPrivateData.RootBridgeHandle, + *(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &PciAddress, + mPciPrivateData.PciEnumerationPhase, + &(mPciPrivateData.Context) + ); + if (IS_PCI_BRIDGE (&(mPciPrivateData.Context.PciHeader))) { + PciAddress =3D EFI_PCI_ADDRESS (StartBus, Device, Func, PCI_BRID= GE_SECONDARY_BUS_REGISTER_OFFSET); + mPciPrivateData.PciRootBridgeIo->Pci.Read ( + mPciPrivateData.PciRootBri= dgeIo, + EfiPciWidthUint8, + *(UINT64 *) &PciAddress, + 1, + &SecondaryBus + ); + if ((SecondaryBus > 0) && (SecondaryBus < 0xFF)) { + PciTreeTraverse (SecondaryBus); + } + } + } + + if (MultiFunc =3D=3D FALSE) { + // + // Skip sub functions, this is not a multi function device + // + Func =3D PCI_MAX_FUNC; + } + } + } + + return EFI_SUCCESS; +} + +/** + + Program Io Apic Id + + @param IoApicAddress and IoApicId + + @retval None + +**/ +VOID +ProgramIoApicId ( + IN UINT32 IoApicAddress, + IN UINT8 IoApicId + ) +{ + + UINT32 Data; + + mPciPrivateData.CpuIo->Mem.Read ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_INDEX_OFFSET, + 1, + &Data + ); + + // + // IOAPIC is not there + // + if (Data =3D=3D (UINT32) -1) { + return ; + } + // + // Set up IO APIC ID and enable FSB delivery + // Use CPU IO protocol since the IO APIC ranges + // are not included in PCI apertures + // + Data =3D EFI_IO_APIC_ID_REGISTER; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_INDEX_OFFSET, + 1, + &Data + ); + + Data =3D IoApicId << EFI_IO_APIC_ID_BITSHIFT; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_DATA_OFFSET, + 1, + &Data + ); + + Data =3D EFI_IO_APIC_BOOT_CONFIG_REGISTER; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_INDEX_OFFSET, + 1, + &Data + ); + + Data =3D EFI_IO_APIC_FSB_INT_DELIVERY; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_DATA_OFFSET, + 1, + &Data + ); +} + +#ifdef EFI_PCI_IOV_SUPPORT +/** + + Initialize the Pci Iov Platform Data. + + @param ImageHandle - Handle to the image. + @param SystemTable - Handle to System Table. + + @retval EFI_STATUS - Status of the function calling. + +**/ +EFI_STATUS +EFIAPI +PciPlatformInitPciIovData ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PCI_IOV_PLATFORM_POLICY PciIovPolicy; + UINT32 SystemPageSize; + EFI_PCI_IOV_PLATFORM_PROTOCOL *gPciIovPlatformProtocol; + + Status =3D gBS->LocateProtocol ( + &gEfiPciIovPlatformProtocolGuid, + NULL, + &gPciIovPlatformProtocol + ); + if (!EFI_ERROR (Status)) { + Status =3D gPciIovPlatformProtocol->GetSystemLowestPageSize ( + gPciIovPlatformProtocol, + &SystemPageSize + ); + if (!EFI_ERROR (Status)) { + Status =3D PcdSet32S (PcdSrIovSystemPageSize, (1 << SystemPageSize)); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + return Status; + } + Status =3D gPciIovPlatformProtocol->GetPlatformPolicy ( + gPciIovPlatformProtocol, + &PciIovPolicy + ); + if (!EFI_ERROR (Status)) { + if (PciIovPolicy & EFI_PCI_IOV_POLICY_ARI) { + Status =3D PcdSetBoolS (PcdAriSupport, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status =3D PcdSetBoolS (PcdAriSupport, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + if (PciIovPolicy & EFI_PCI_IOV_POLICY_SRIOV) { + Status =3D PcdSetBoolS (PcdSrIovSupport, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status =3D PcdSetBoolS (PcdSrIovSupport, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + if (PciIovPolicy & EFI_PCI_IOV_POLICY_MRIOV) { + Status =3D PcdSetBoolS (PcdMrIovSupport, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status =3D PcdSetBoolS (PcdMrIovSupport, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + } else { + return Status; + } + DEBUG (( + EFI_D_INFO, + " Initialized SR-IOV Platform Data: PCIIovPolicy =3D 0x%x; Syste= mPageSize =3D 0x%x;\n", + PciIovPolicy, SystemPageSize + )); + } else { + DEBUG (( + EFI_D_INFO, + " Using default values for SystemPageSize;\n" + )); + } + return Status; +} +#endif + +/** + + Platform Pci Express init. + + @param HostBridgeInstance - Pointer to Host Bridge private data + does not support 64 bit memory addresses. + + @retval EFI_SUCCESS - Success. + =20 +**/ +EFI_STATUS +PciPlatformEarlyInit ( + VOID + ) +{ + EFI_STATUS Status; + // + // Locate the IIO Protocol Interface + // + Status =3D gBS->LocateProtocol (&gEfiIioUdsProtocolGuid,NULL,&mIioUds); + ASSERT_EFI_ERROR (Status); + Status =3D gBS->LocateProtocol (&gEfiIioSystemProtocolGuid, NULL, &IioSy= stemProtocol); + ASSERT_EFI_ERROR (Status);=20 + + IioGlobalData =3D IioSystemProtocol->IioGlobalData; + +#ifdef EFI_PCI_IOV_SUPPORT + Status =3D PciPlatformInitPciIovData(); // Update IOV PCD values +#endif + return EFI_SUCCESS; +} + + +/** + =20 + Init pci device registers after the device resources have been allocated= , so + that devices behind a bus could be accessed. + =20 + @param HostBridgeInstance - PCI_HOST_BRIDGE_INSTANCE. + + @retval EFI_SUCCESS - Function has completed successfully. + +**/ +EFI_STATUS +PciPlatformPostInit ( + VOID + ) +{ + // + // Program all the IOAPIC in system + // + UINT8 Socket, Stack, IoApicId; + UINT8 Step; + UINT8 MaxSocket; + +#if MAX_SOCKET <=3D 4 + Step =3D 6; + MaxSocket =3D 4; +#else + Step =3D 4; + MaxSocket =3D 8; +#endif + + Stack =3D 0; + IoApicId =3D 0; + ProgramIoApicId (mIioUds->IioUdsPtr->PlatformData.IIO_resource[0].StackR= es[0].IoApicBase, PcdGet8(PcdIoApicId)); + for (Socket =3D 0; Socket < MAX_SOCKET; Socket++) { + if (!(mIioUds->IioUdsPtr->SystemStatus.socketPresentBitMap & (1 << Soc= ket))) + continue; + + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPrese= ntBitmap & (1 << Stack))) + continue; + + if ((Socket < MaxSocket) && (Stack < Step)) { + IoApicId =3D PcdGet8(PcdPcIoApicIdBase) + Step * Socket + Stack; + } + + if ((Socket =3D=3D 0) && (Stack =3D=3D 0)) { + ProgramIoApicId ((mIioUds->IioUdsPtr->PlatformData.IIO_resource[So= cket].StackRes[Stack].IoApicBase + 0x1000), IoApicId); + } else { + ProgramIoApicId (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Soc= ket].StackRes[Stack].IoApicBase, IoApicId); + } + } + } + return EFI_SUCCESS; +} + +/** + + The PlatformPrepController() function can be used to notify the platform= driver so that=20 + it can perform platform-specific actions. No specific actions are requir= ed.=20 + Several notification points are defined at this time. More synchronizati= on points may be=20 + added as required in the future. The PCI bus driver calls the platform d= river twice for=20 + every PCI controller-once before the PCI Host Bridge Resource Allocation= Protocol driver=20 + is notified, and once after the PCI Host Bridge Resource Allocation Prot= ocol driver has=20 + been notified.=20 + This member function may not perform any error checking on the input par= ameters. It also=20 + does not return any error codes. If this member function detects any err= or condition, it=20 + needs to handle those errors on its own because there is no way to surfa= ce any errors to=20 + the caller. =20 + =20 + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instanc= e. =20 + @param HostBridge - The associated PCI host bridge handle.=20 + @param RootBridge - The associated PCI root bridge handle. + @param PciAddress - The address of the PCI device on the PCI bus.=20 + @param Phase - The phase of the PCI controller enumeration.=20 + @param ChipsetPhase - Defines the execution phase of the PCI chipset d= river.=20 + =20 + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_UNSUPPORTED - Not supported. + =20 +**/ +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + if (mPciPrivateData.RootBridgeHandle =3D=3D NULL) { + mPciPrivateData.RootBridgeHandle =3D RootBridge; + } + + return EFI_SUCCESS; +} + +/** + + Perform initialization by the phase indicated. + + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instanc= e. + @param HostBridge - The associated PCI host bridge handle. + @param Phase - The phase of the PCI controller enumeration. + @param ChipsetPhase - Defines the execution phase of the PCI chipset d= river. + + @retval EFI_SUCCESS - Must return with success. + +**/ +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + EFI_STATUS Status; + UINT8 i; + UINT8 Stack; + + if (ChipsetPhase =3D=3D ChipsetEntry) { + return EFI_SUCCESS; + } + // + // If for multiple host bridges, need special consideration + // + switch (Phase) { + + case EfiPciHostBridgeBeginEnumeration: + // + // Pre-initialization before PCI bus enumeration + // No bus number and no PCI resource + // + Status =3D gBS->LocateProtocol ( + &gEfiPciRootBridgeIoProtocolGuid, + NULL, + &(mPciPrivateData.PciRootBridgeIo) + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gBS->LocateProtocol ( + &gEfiCpuIo2ProtocolGuid, + NULL, + &(mPciPrivateData.CpuIo) + ); + ASSERT_EFI_ERROR (Status); + mPciPrivateData.Context.CpuIo =3D mPciPrivateData.CpuIo; + + DEBUG ((DEBUG_ERROR, "PCI Platform Pre-Initialization (Before bus scan= ning)\n")); + PciPlatformEarlyInit (); + break; + + case EfiPciHostBridgeEndBusAllocation: + // + // There are two rounds PCI bus scanning + // First round will initilize the PCI hotplug device + // Second round will be the final one + // + if (mPciPrivateData.BusAssignedTime =3D=3D 0) { + mPciPrivateData.PciEnumerationPhase =3D EfiPciEnumerationDeviceScann= ing; + for (i =3D 0 ; i < MaxIIO ; i++) { + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[i].Valid) { + for(Stack =3D 0; Stack < MAX_IIO_STACK; Stack ++) { + PciTreeTraverse (mIioUds->IioUdsPtr->PlatformData.CpuQpi= Info[i].StackBus[Stack]); + } + } + } + mPciPrivateData.BusAssignedTime++; + DEBUG ((DEBUG_ERROR, "PCI Platform bus assigned\n")); + } + break; + + case EfiPciHostBridgeBeginResourceAllocation: + // + // PCI bus number has been assigned, but resource is still empty + // + DEBUG ((DEBUG_ERROR, "PCI Platform Mid-Initialization (After bus numbe= r assignment)\n")); + mPciPrivateData.PciEnumerationPhase =3D EfiPciEnumerationBusNumberAssi= gned; + for (i =3D 0 ; i < MaxIIO ; i++) { + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[i].Valid) { + for(Stack =3D 0; Stack < MAX_IIO_STACK; Stack ++) { + PciTreeTraverse (mIioUds->IioUdsPtr->PlatformData.CpuQpiIn= fo[i].StackBus[Stack]); + } + } + } + //PciPlatformMidInit (); + break; + + case EfiPciHostBridgeEndResourceAllocation: + // + // Resource enumeration is done. + // Both bus number and resource have been assigned + // Do any post initialization. + // + DEBUG ((DEBUG_ERROR, "PCI Platform Post-Initialization (After resource= alloction)\n")); + mPciPrivateData.PciEnumerationPhase =3D EfiPciEnumerationResourceAssig= ned; + for (i =3D 0 ; i < MaxIIO ; i++) { + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[i].Valid) { + for(Stack =3D 0; Stack < MAX_IIO_STACK; Stack ++) { + PciTreeTraverse (mIioUds->IioUdsPtr->PlatformData.CpuQpiIn= fo[i].StackBus[Stack]); + } + } + } + PciPlatformPostInit (); + break; + + default: + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformH= ooks.h b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks= .h new file mode 100644 index 0000000000..a5cee1b3a5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks.h @@ -0,0 +1,24 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PCI_PLATFORM_HOOKS_H_ +#define PCI_PLATFORM_HOOKS_H_ + +VOID +ChipsetCallback ( + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_ENUMERATION_PHASE Phase, + EFI_PCI_CALLBACK_CONTEXT *Context + ); + +EFI_STATUS +PciTreeTraverse ( + IN UINT8 StartBus + ); + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLi= b.c b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.c new file mode 100644 index 0000000000..d8bf65439f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.c @@ -0,0 +1,103 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PiDxe.h" +#include +#include +#include +#include +#include +#include "IndustryStandard/Pci.h" +#include "PciSupportLib.h" + +PCIE_STACK mPcieStack; + + +/** + + This routine is used to check whether the pci device is present + + @retval None + +**/ +BOOLEAN +IsPciDevicePresent ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, + PCI_TYPE00 *Pci, + UINT8 Bus, + UINT8 Device, + UINT8 Func + ) +// TODO: PciRootBridgeIo - add argument and description to function com= ment +// TODO: Pci - add argument and description to function comment +// TODO: Bus - add argument and description to function comment +// TODO: Device - add argument and description to function comment +// TODO: Func - add argument and description to function comment +// TODO: EFI_SUCCESS - add return value to function comment +// TODO: EFI_NOT_FOUND - add return value to function comment +{ + UINT64 Address; + UINT32 Dummy; + EFI_STATUS Status; + =20 + Dummy=3D0xFFFFFFFF; + // + // Create PCI address map in terms of Bus, Device and Func + // + Address =3D EFI_PCI_ADDRESS (Bus, Device, Func, 0); + + // + // Read the Vendor Id register + // + Status =3D PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + Pci + ); + if ((Pci->Hdr).VendorId =3D=3D 0xffff) { + /// PCIe card could have been assigned a temporary bus number.=20 + /// An write cycle can be used to try to rewrite the Bus number in the= card + /// Try to write the Vendor Id register, and recheck if the card is pr= esent.=20 + Status =3D PciRootBridgeIo->Pci.Write( + PciRootBridgeIo,=20 + EfiPciWidthUint32,=20 + Address,=20 + 1, =20 + &Dummy + );=20 + =09 + // Retry the previous read after the PCI cycle has been tried.=20 + Status =3D PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + Pci + ); + } + + if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId !=3D 0xffff) { + + // + // Read the entire config header for the device + // + + Status =3D PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + sizeof (PCI_TYPE00) / sizeof (UINT32), + Pci + ); + + return TRUE; + } + + return FALSE; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLi= b.h b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.h new file mode 100644 index 0000000000..dc123b0d42 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.h @@ -0,0 +1,44 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_PCI_SUPPORT_H_ +#define _EFI_PCI_SUPPORT_H_ + +#include + +#include + +typedef struct { + UINT8 PcieCapPtr; + UINT8 Function; + UINT8 Device; =20 + UINT8 Bus; + UINT16 PcieLnkCap; + UINT16 PcieDevCap; + //Added to Support AtomicOp Request-->Start + UINT16 PcieDevCap2; + //Added to Support AtomicOp Request-->End +} PCIE_CAP_INFO; + +typedef struct { + INTN Top; + PCIE_CAP_INFO PcieCapInfo[FixedPcdGet32(PcdMaxNestedLevel)]; +} PCIE_STACK; + +extern PCIE_STACK mPcieStack; + +BOOLEAN +IsPciDevicePresent ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, + PCI_TYPE00 *Pci, + UINT8 Bus, + UINT8 Device, + UINT8 Func + ); + =20 + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsD= ataDxe.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDat= aDxe.c new file mode 100644 index 0000000000..6c626cf05d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.c @@ -0,0 +1,86 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Statements that include other files +// +#include "IioUdsDataDxe.h" + +#define STRING_WIDTH_40 40 + +// +// Instantiation of Driver's private data. +// +EFI_IIO_UDS_DRIVER_PRIVATE mIioUdsPrivateData; +IIO_UDS *IioUdsData; // Pointer to UD= S in Allocated Memory Pool + +/** + + Entry point for the driver. + + @param ImageHandle - Image Handle. + @param SystemTable - EFI System Table. + =20 + @retval EFI_SUCCESS - Function has completed successfully. + =20 +**/ +EFI_STATUS +EFIAPI +IioUdsDataInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + IIO_UDS *UdsHobPtr; + EFI_GUID UniversalDataGuid =3D IIO_UNIVERSAL_DATA= _GUID; + + // + // Time to get the IIO_UDS HOB data stored in the PEI driver + // + GuidHob =3D GetFirstGuidHob (&UniversalDataGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + UdsHobPtr =3D GET_GUID_HOB_DATA(GuidHob);=20 + + // + // Allocate Memory Pool for Universal Data Storage so that protocol can = expose it + // + Status =3D gBS->AllocatePool ( EfiReservedMemoryType, sizeof (IIO_UDS), = (VOID **) &IioUdsData ); + ASSERT_EFI_ERROR (Status); + =20 + // + // Initialize the Pool Memory with the data from the Hand-Off-Block + // + CopyMem(IioUdsData, UdsHobPtr, sizeof(IIO_UDS)); + + // + // Build the IIO_UDS driver instance for protocol publishing =20 + // + ZeroMem (&mIioUdsPrivateData, sizeof (mIioUdsPrivateData)); + =20 + mIioUdsPrivateData.Signature =3D EFI_IIO_UDS_DRIVER_PRIVATE_S= IGNATURE; + mIioUdsPrivateData.IioUds.IioUdsPtr =3D IioUdsData; + mIioUdsPrivateData.IioUds.EnableVc =3D NULL; + + // + // Install the IioUds Protocol. + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mIioUdsPrivateData.Handle, + &gEfiIioUdsProtocolGuid, + &mIioUdsPrivateData.IioUds, + NULL + ); + ASSERT_EFI_ERROR (Status); =20 + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsD= ataDxe.h b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDat= aDxe.h new file mode 100644 index 0000000000..62da06d605 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.h @@ -0,0 +1,81 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_TYPES_H_ +#define _PLATFORM_TYPES_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + + + +#define EFI_PLATFORM_TYPE_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('T', 'Y'= , 'P', 'P') +#define EFI_IIO_UDS_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('S', 'D', 'U',= 'I') + + +typedef unsigned char BYTE; //!< 8-bit quantities +typedef unsigned short WORD; //!< 16-bit quantities +typedef unsigned long DWORD; //!< 32-bit quantities + +typedef enum +{ +#ifndef SUCCESS + SUCCESS =3D 0x00, //!< Packet it good! .data[] is valid +#endif + DEFER =3D 0x01, //!< Packet is defered. .data[1] =3D Buf= ID + W_EARLY_NACK =3D 0x02, //!< Packet mastered on the SMBus by the= MCU was NACKed earlier than expected + NOT_RESP =3D 0x03, //!< Packet mastered on the SMBus by the= MCU was NACKed during the address byte + BUFFER_OVERRUN =3D 0x04, //!< Too many BYTE s were stuffed into t= he buffer. + NO_BUFFER =3D 0x05, //!< All the buffers are used + INVALID_BUF =3D 0x06, //!< Command passed a buffer id that was= not in range + BUF_NOT_IN_QUEUE =3D 0x07, //!< Command passed a buffer id is not b= eing used. + ARBITRATION_LOST =3D 0x08, //!< While the MCU was mastering a packe= t on the SMBus it lost arbitration. + TIMEOUT =3D 0x0B, //!< SMBus timed out. + CHECKSUM_ERR =3D 0x0C, //!< Operation encountered a checksum mi= smatch + DATA_NACK =3D 0x0D, //!< Still don't know what these mean? + BUS_ERR =3D 0x0E, //!< ? + FAIL =3D 0x0F, //!< Generic error + BUSY =3D 0x10, //!< ? + R_EARLY_NACK =3D 0x11, //!< ? + INVALID_LCD_COL_OFF =3D 0x12, //!< The cursor on the LCD was set to a = column that was out of range. + INVALID_LCD_ROW_OFF =3D 0x13, //!< The cursor on the LCD was set to a = row that was out of range. + INVALID_CK410_SEL =3D 0x14, //!< ? + CMD_NOT_SUPPORTED =3D 0x15, //!< This command is not supported + MORE_DATA_AVAILABLE =3D 0x16, //!< Do the command again to get more da= ta +} STATUS; + +typedef struct { + BYTE byte_count;=20 + STATUS status; + BYTE data[31]; +} BUFFER_RSLT; + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; // Handle for protoc= ol this driver installs on + EFI_IIO_UDS_PROTOCOL IioUds; // Policy protocol t= his driver installs +} EFI_IIO_UDS_DRIVER_PRIVATE; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsD= ataDxe.inf b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsD= ataDxe.inf new file mode 100644 index 0000000000..db425e3836 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.= inf @@ -0,0 +1,36 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D IioUdsDataDxe + FILE_GUID =3D 036125ED-DD4C-4BF7-AC8D-83FE11CDD5DB + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D IioUdsDataInit + +[Sources] + IioUdsDataDxe.c + IioUdsDataDxe.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[LibraryClasses] + HobLib + BaseMemoryLib + UefiDriverEntryPoint + +[Protocols] + gEfiIioUdsProtocolGuid + +[Depex] + TRUE diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/Pla= tformCpuPolicy.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPoli= cy/PlatformCpuPolicy.c new file mode 100644 index 0000000000..1cd8d657c1 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/PlatformCp= uPolicy.c @@ -0,0 +1,654 @@ +/** @file + +Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PlatformHost.h" +#include + +CHAR16 mCpuSocketStr[8][5] =3D {L"CPU0", L"CPU1", L"CPU2", L"CPU3", L"CPU4= ", L"CPU5", L"CPU6", L"CPU7"}; +CHAR16 mCpuAssetTagStr[] =3D L"UNKNOWN"; +IIO_UDS *mIioUds; + +/** + + GC_TODO: add routine description + + @param None + + @retval None + +**/ +VOID +CheckAndReAssignSocketId( + VOID + ) +{ +#define APICID_MASK_BIT14_8 0x7F //current Si support programmable APIC= ID up to 15bits + CPU_SOCKET_ID_INFO *pcdSktIdPtr; + UINT32 i, IntraPackageIdBits; + UINTN PcdSize; + EFI_STATUS Status; + UINT32 MaxSocketCount; + + MaxSocketCount =3D FixedPcdGet32(PcdMaxCpuSocketCount); + DEBUG ((EFI_D_ERROR, "::SocketCount %08x\n", MaxSocketCount)); + pcdSktIdPtr =3D (CPU_SOCKET_ID_INFO *)PcdGetPtr(PcdCpuSocketId); + PcdSize =3D PcdGetSize (PcdCpuSocketId); //MAX_SOCKET * sizeof(CPU_SOCKE= T_ID_INFO); + ASSERT(PcdSize =3D=3D (MAX_SOCKET * sizeof(CPU_SOCKET_ID_INFO))); + Status =3D PcdSetPtrS (PcdCpuSocketId, &PcdSize, (VOID *)pcdSktIdPtr); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return; + DEBUG ((EFI_D_INFO, "::SockeId Pcd at %08x, size %x\n", PcdGetPtr(PcdCpu= SocketId), PcdSize)); + + for(i =3D 0; i < MAX_SOCKET; i++) { + if(mIioUds->PlatformData.CpuQpiInfo[i].Valid) { + pcdSktIdPtr[i].DefaultSocketId =3D mIioUds->PlatformData.CpuQpiInfo[= i].SocId; + pcdSktIdPtr[i].NewSocketId =3D mIioUds->PlatformData.CpuQpiInfo[= i].SocId; + } else { + pcdSktIdPtr[i].DefaultSocketId =3D (UINT32)-1; //make sure Default= and New are same + pcdSktIdPtr[i].NewSocketId =3D (UINT32)-1; + } + } + + AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, &IntraPackageIdBits, NULL, NULL,= NULL); + //assign new socketId + for(i =3D 0; i < MAX_SOCKET; i++) { + + if(pcdSktIdPtr[i].DefaultSocketId =3D=3D (UINT32)-1) continue; + + switch(IntraPackageIdBits) { + case 4: //socket bit starts from bit4 of ApicId + case 5: //socket bit starts from bit5 of ApicId + if(MAX_SOCKET =3D=3D 4) { + pcdSktIdPtr[i].NewSocketId |=3D (APICID_MASK_BIT14_8 << (8 - Int= raPackageIdBits)); + } else { + //3bit in lower 8bit as skt field, to avoid ApicID=3D FFs, leave= bit8 untouched for 8S + pcdSktIdPtr[i].NewSocketId |=3D (0x7E << (8 - IntraPackageIdBits= )); //leave bit8 to 0 so we don't have FFs in ApicId + } + break; + + case 6: //socket bit starts from bit6 of ApicId + if(MAX_SOCKET =3D=3D 4) { + //only 2bit in lower 8bit as skt field, to avoid ApicID=3D FFs, = leave bit8 untouched for 4S + pcdSktIdPtr[i].NewSocketId |=3D (0x7E << (8 - IntraPackageIdBits= )); + } else { + //only 2bit in lower 8bit as skt field, to avoid ApicID=3D FFs, = leave bit9 untouched for 8S + pcdSktIdPtr[i].NewSocketId |=3D (0x7C << (8 - IntraPackageIdBits= )); + } + break; + + default: + DEBUG ((EFI_D_INFO, "::Need more info to make sure we can support!= !!\n")); + break; + + } //end switch + } +} + + +/** + + This is the EFI driver entry point for the CpuPolicy Driver. This + driver is responsible for getting microcode patches from FV. + + @param ImageHandle - Handle for the image of this driver. + @param SystemTable - Pointer to the EFI System Table. + + @retval EFI_SUCCESS - Protocol installed sucessfully. + +**/ +EFI_STATUS +EFIAPI +PlatformCpuPolicyEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + SETUP_DATA SetupData; + UINT32 CpuPolicy; + UINT32 CpuPolicyEx1; + EFI_HANDLE Handle; + UINT32 CsrSapmCtl =3D 0; + UINT32 CsrPerfPlimitCtl =3D 0; + UINT8 PCPSOptions =3D 0; + UINT32 AdvPwrMgtCtl; + UINT8 socket; + UINT32 *UpiInPkgCEntry =3D NULL; + UINT32 *PcieInPkgCEntry =3D NULL; + UINT32 MsrPowerCtlLow =3D 0; + UINT32 MsrTurboPowerLimitHigh =3D 0; + UINT32 MsrTurboPowerLimitLow =3D 0; + UINT32 MsrPriPlaneCurrentCfgCtlHigh =3D 0; + UINT32 MsrPriPlaneCurrentCfgCtlLow =3D 0; + UINT32 CsrDynamicPerfPowerCtl =3D 0; + UINT32 CsrPcieIltrOvrd =3D 0; + UINT32 MsrPerfBiasConfig =3D 0; + MSR_REGISTER *CStateLatencyCtrl =3D NULL; + UINT32 CpuFamilyModelStepping; + UINT64 i; + UINT64 *Addr; + EFI_PPM_STRUCT *ppm =3D NULL; + XE_STRUCT *XePtr =3D NULL; + TURBO_RATIO_LIMIT_RATIO_CORES *TurboRatioLimitRatioCores =3D NULL; + UINT8 PackageCStateSetting =3D 0; + UINT8 CpuCStateValue =3D 0; + + EFI_GUID UniversalDataGuid =3D IIO_UNIVERSAL_DAT= A_GUID; + EFI_HOB_GUID_TYPE *GuidHob; + + GuidHob =3D GetFirstGuidHob (&UniversalDataGuid); + ASSERT (GuidHob !=3D NULL); + if(GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + mIioUds =3D GET_GUID_HOB_DATA(GuidHob); + + AsmCpuid (1, &CpuFamilyModelStepping, NULL, NULL, NULL); + + Status =3D gBS->AllocatePool ( + EfiBootServicesData, + sizeof(EFI_PPM_STRUCT), + (VOID **) &Addr + ); + if(Status !=3D EFI_SUCCESS) { + DEBUG ((EFI_D_INFO, "::Failed to allocate mem for PPM Struct\n")); + ASSERT_EFI_ERROR (Status); //may need to create a default + } else { + ZeroMem(Addr, sizeof(EFI_PPM_STRUCT)); + i =3D (UINT32)(*(UINT64 *)(&Addr)); + ppm =3D (EFI_PPM_STRUCT *)(Addr); + Status =3D PcdSet64S (PcdCpuPmStructAddr, i); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + DEBUG ((EFI_D_INFO, "::PPM mem allocate @ %x %X %X\n", i, PcdGet64(Pcd= CpuPmStructAddr), ppm)); + UpiInPkgCEntry =3D (UINT32 *)(((EFI_PPM_STRUCT *)Addr)->Cst.PkgCstEntr= yCriteriaMaskKti); + PcieInPkgCEntry =3D (UINT32 *)(((EFI_PPM_STRUCT *)Addr)->Cst.PkgCstEnt= ryCriteriaMaskPcie); + XePtr =3D (XE_STRUCT *)(&((EFI_PPM_STRUCT *)Addr)->Xe); + TurboRatioLimitRatioCores =3D (TURBO_RATIO_LIMIT_RATIO_CORES *)(&((EFI= _PPM_STRUCT *)Addr)->TurboRatioLimitRatioCores); + DEBUG ((EFI_D_INFO, ":: XE @ %X\n", (UINTN) XePtr)); + + CStateLatencyCtrl =3D (MSR_REGISTER *)(ppm->Cst.LatencyCtrl); + DEBUG ((EFI_D_INFO, "CStateLatencyCtrl[%X]\n", (UINTN) CStateLatencyCt= rl)); + } + + // + // Read the current system configuration variable store. + // + ZeroMem (&SetupData, sizeof(SETUP_DATA)); + CopyMem (&SetupData.SocketConfig.IioConfig, PcdGetPtr(PcdSocketIioConfig= Data), sizeof(SOCKET_IIO_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.CommonRcConfig, PcdGetPtr(PcdSocketComm= onRcConfigData), sizeof(SOCKET_COMMONRC_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.CsiConfig, PcdGetPtr(PcdSocketMpLinkCon= figData), sizeof(SOCKET_MP_LINK_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.MemoryConfig, PcdGetPtr(PcdSocketMemory= ConfigData), sizeof(SOCKET_MEMORY_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.PowerManagementConfig, PcdGetPtr(PcdSoc= ketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION)= ); + CopyMem (&SetupData.SocketConfig.SocketProcessorCoreConfiguration, PcdGe= tPtr(PcdSocketProcessorCoreConfigData), sizeof(SOCKET_PROCESSORCORE_CONFIGU= RATION)); + CopyMem (&SetupData.SystemConfig, PcdGetPtr(PcdSetupData), sizeof(SYSTEM= _CONFIGURATION)); + CopyMem (&SetupData.PchRcConfig, PcdGetPtr(PcdPchRcConfigurationData), s= izeof(PCH_RC_CONFIGURATION)); + + { + + if (SetupData.SocketConfig.PowerManagementConfig.PackageCState =3D=3D PPM= _AUTO) { + PackageCStateSetting =3D 3; //POR Default =3D C6 + } else { + PackageCStateSetting =3D SetupData.SocketConfig.PowerManagementCon= fig.PackageCState; + } + + // Temporary override to prevent accidental enabling until CR dungeon = approves + if (SetupData.SocketConfig.PowerManagementConfig.PackageCState !=3D 0)= { + DEBUG((EFI_D_ERROR, "Crystal Ridge Configuration Warning: Package c-= states are not disabled\n")); + } + + if ((SetupData.SocketConfig.PowerManagementConfig.C6Enable =3D=3D PPM_= AUTO) || + SetupData.SocketConfig.PowerManagementConfig.ProcessorAutonomous= CstateEnable) { + CpuCStateValue |=3D C6_ENABLE; //POR Default =3D Enabled + } else { + CpuCStateValue |=3D (SetupData.SocketConfig.PowerManagementConfig.= C6Enable * C6_ENABLE); + } + + Status =3D PcdSet8S (PcdCpuCoreCStateValue, CpuCStateValue); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + + // + // If ACC enabled, then override C1E to be enabled + // + if (SetupData.SocketConfig.PowerManagementConfig.ProcessorAutonomousCs= tateEnable) { + SetupData.SocketConfig.PowerManagementConfig.ProcessorC1eEnable =3D = TRUE; + } + + // + // Verify that the value being set is within the valid range 0 to MAX_= SOCKET - 1 + // + if (SetupData.SocketConfig.SocketProcessorCoreConfiguration.BspSelecti= on > MAX_SOCKET) + SetupData.SocketConfig.SocketProcessorCoreConfiguration.BspSelection= =3D 0xFF; + Status =3D PcdSet8S (PcdSbspSelection, SetupData.SocketConfig.SocketPr= ocessorCoreConfiguration.BspSelection); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + // + // Map CPU setup options to PcdCpuProcessorFeatureUserConfiguration + // + CpuPolicy =3D (SetupData.SocketConfig.SocketProcessorCoreConfiguration= .ProcessorHyperThreadingDisable ? 0 : PCD_CPU_HT_BIT) | + (SetupData.SocketConfig.PowerManagementConfig.ProcessorEis= tEnable ? PCD_CPU_EIST_BIT : 0) | + (SetupData.SocketConfig.PowerManagementConfig.ProcessorC1e= Enable ? PCD_CPU_C1E_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.P= rocessorVmxEnable ? PCD_CPU_VT_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.P= rocessorSmxEnable ? PCD_CPU_LT_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.F= astStringEnable ? PCD_CPU_FAST_STRING_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.C= puidMaxValue ? PCD_CPU_MAX_CPUID_VALUE_LIMIT_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.E= xecuteDisableBit ? PCD_CPU_EXECUTE_DISABLE_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.M= achineCheckEnable ? PCD_CPU_MACHINE_CHECK_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.D= CUStreamerPrefetcherEnable ? PCD_CPU_DCU_PREFETCHER_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.D= CUIPPrefetcherEnable ? PCD_CPU_IP_PREFETCHER_BIT : 0) | + PCD_CPU_MONITOR_MWAIT_BIT | //never disable Mwait + (SetupData.SocketConfig.PowerManagementConfig.TurboMode ? = PCD_CPU_TURBO_MODE_BIT : 0) | + (SetupData.SocketConfig.PowerManagementConfig.EnableTherma= lMonitor ? PCD_CPU_THERMAL_MANAGEMENT_BIT : 0); + + if (SetupData.SocketConfig.PowerManagementConfig.TStateEnable && (Setu= pData.SocketConfig.PowerManagementConfig.OnDieThermalThrottling > 0)) { + CpuPolicy |=3D (SetupData.SocketConfig.PowerManagementConfig.TState= Enable ? PCD_CPU_TSTATE_BIT : 0); + } + + CpuPolicyEx1 =3D (SetupData.SocketConfig.SocketProcessorCoreConfigurat= ion.MlcStreamerPrefetcherEnable ? PCD_CPU_MLC_STREAMER_PREFETCHER_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguratio= n.MlcSpatialPrefetcherEnable ? PCD_CPU_MLC_SPATIAL_PREFETCHER_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguratio= n.ThreeStrikeTimer ? PCD_CPU_THREE_STRIKE_COUNTER_BIT : 0) | + PCD_CPU_ENERGY_PERFORMANCE_BIAS_BIT | + (SetupData.SocketConfig.SocketProcessorCoreConfiguratio= n.ProcessorX2apic ? PCD_CPU_X2APIC_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguratio= n.AesEnable ? PCD_CPU_AES_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguratio= n.PCIeDownStreamPECIWrite ? PCD_CPU_PECI_DOWNSTREAM_WRITE_BIT : 0) | + PCD_CPU_C_STATE_BIT; + + + PCPSOptions =3D (SetupData.SocketConfig.PowerManagementConfig.Process= orSinglePCTLEn ? PCD_CPU_PCPS_SINGLEPCTL : 0) | + (SetupData.SocketConfig.PowerManagementConfig.Processor= SPD ? PCD_CPU_PCPS_SPD : 0) | + (SetupData.SocketConfig.PowerManagementConfig.PStateDom= ain ? PCD_CPU_PCPS_PSTATEDOMAIN : 0) | + (UINT8) SetupData.SocketConfig.PowerManagementConfig.Pr= ocessorEistPsdFunc; + + ppm->Pst.PcpsCtrl =3D PCPSOptions; + ppm->OverclockingLock =3D SetupData.SocketConfig.PowerManagementConfig= .OverclockingLock; + + ppm->FastRaplDutyCycle =3D SetupData.SocketConfig.PowerManagementConfi= g.FastRaplDutyCycle; + + if(mIioUds->PlatformData.EVMode) + CpuPolicy &=3D ~PCD_CPU_LT_BIT; + + if (SetupData.SocketConfig.PowerManagementConfig.ProcessorEistEnable) { + Status =3D PcdSetBoolS (PcdCpuHwCoordination, SetupData.SocketConfig= .PowerManagementConfig.ProcessorEistPsdFunc ? FALSE : TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + + Status =3D PcdSet16S (PcdCpuAcpiLvl2Addr, PcdGet16 (PcdPchAcpiIoPortBa= seAddress) + R_ACPI_LV2); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status =3D PcdSet8S (PcdCpuPackageCStateLimit, PackageCStateSetting); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + + if ((SetupData.SocketConfig.PowerManagementConfig.TStateEnable) && (Se= tupData.SocketConfig.PowerManagementConfig.OnDieThermalThrottling > 0)) { + Status =3D PcdSet8S (PcdCpuClockModulationDutyCycle, SetupData.Socke= tConfig.PowerManagementConfig.OnDieThermalThrottling); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + ppm->TCCActivationOffset =3D SetupData.SocketConfig.PowerManagementC= onfig.TCCActivationOffset; + } + Status =3D PcdSet8S (PcdCpuDcuMode, SetupData.SocketConfig.SocketProce= ssorCoreConfiguration.DCUModeSelection); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + + if((CpuFamilyModelStepping >> 4) =3D=3D CPU_FAMILY_SKX) { + Status =3D PcdSetBoolS (PcdCpuSmmRuntimeCtlHooks, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status =3D PcdSetBoolS (PcdCpuSmmRuntimeCtlHooks, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + DEBUG ((EFI_D_INFO, ":: PcdCpuSmmRuntimeCtlHooks=3D %x\n", PcdGetBool(= PcdCpuSmmRuntimeCtlHooks))); + + if(mIioUds->PlatformData.EVMode || SetupData.SystemConfig.LmceEn) { + Status =3D PcdSet8S (PcdCpuProcessorMsrLockCtrl, 0); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status =3D PcdSet8S (PcdCpuProcessorMsrLockCtrl, SetupData.SocketCon= fig.SocketProcessorCoreConfiguration.ProcessorMsrLockControl); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + + Status =3D PcdSet64S(PcdCpuIioLlcWaysBitMask, SetupData.SocketConfig.S= ocketProcessorCoreConfiguration.IioLlcWaysMask); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status =3D PcdSet64S(PcdCpuExpandedIioLlcWaysBitMask, SetupData.Socket= Config.SocketProcessorCoreConfiguration.ExpandedIioLlcWaysMask); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status =3D PcdSet64S(PcdCpuRemoteWaysBitMask, SetupData.SocketConfig.S= ocketProcessorCoreConfiguration.RemoteWaysMask); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status =3D PcdSet8S(PcdPchTraceHubEn, SetupData.SocketConfig.SocketPro= cessorCoreConfiguration.PchTraceHubEn); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status =3D PcdSet64S(PcdCpuQlruCfgBitMask, ((UINT64) SetupData.SocketC= onfig.SocketProcessorCoreConfiguration.QlruCfgMask_Hi << 32) | (UINT64)Setu= pData.SocketConfig.SocketProcessorCoreConfiguration.QlruCfgMask_Lo ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status =3D PcdSet64S(PcdCpuRRQCountThreshold, mIioUds->PlatformData.Re= moteRequestThreshold); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + + //CSR SAPM CTL + CsrSapmCtl =3D 0; + + for( socket =3D 0; socket < MAX_SOCKET; socket++) { + CsrSapmCtl =3D (( SetupData.SocketConfig.PowerManagementConfig.Iio0P= kgcClkGateDis[socket] << IIO012_PKGC_CLK_GATE_DISABLE_SHIFT) | + ( SetupData.SocketConfig.PowerManagementConfig.Iio1Pkgc= ClkGateDis[socket] << (IIO012_PKGC_CLK_GATE_DISABLE_SHIFT + 1)) | + ( SetupData.SocketConfig.PowerManagementConfig.Iio2Pkgc= ClkGateDis[socket] << (IIO012_PKGC_CLK_GATE_DISABLE_SHIFT + 2)) ); + + CsrSapmCtl |=3D (( SetupData.SocketConfig.PowerManagementConfig.Kti2= 3PkgcClkGateDis[socket] << KTI23_PKGC_CLK_GATE_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Kti01PkgcC= lkGateDis[socket] << KTI01_PKGC_CLK_GATE_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Kti01pllOf= fEna[socket] << KTI_PLL_OFF_EN_SHIFT) | + ( SetupData.SocketConfig.PowerManagementConfig.Kti23pllOf= fEna[socket] << (KTI_PLL_OFF_EN_SHIFT + 1) ) ); + + CsrSapmCtl |=3D (( SetupData.SocketConfig.PowerManagementConfig.Mc= 1PkgcClkGateDis[socket] << MC1_PKGC_CLK_GATE_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Mc0PkgcC= lkGateDis[socket] << MC0_PKGC_CLK_GATE_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Mc0pllOf= fEna[socket] << MEM_PLL_OFF_EN_SHIFT) | + ( SetupData.SocketConfig.PowerManagementConfig.Mc1pllOf= fEna[socket] << (MEM_PLL_OFF_EN_SHIFT + 1) )); + + if (SetupData.SocketConfig.MemoryConfig.OppSrefEn =3D=3D 1) { + CsrSapmCtl |=3D ((1 << MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT= ) | (1 << MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT) | + (1 << MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT) = | (1 << MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT)) ; + } + + CsrSapmCtl |=3D (( SetupData.SocketConfig.PowerManagementConfig.P0pl= lOffEna[socket] << IIO_PLL_OFF_EN_SHIFT) | + ( SetupData.SocketConfig.PowerManagementConfig.P1pllOffEn= a[socket] << (IIO_PLL_OFF_EN_SHIFT + 1) ) | + ( SetupData.SocketConfig.PowerManagementConfig.P2pllOffEn= a[socket] << (IIO_PLL_OFF_EN_SHIFT + 2) ) | + ( SetupData.SocketConfig.PowerManagementConfig.SetvidDeca= yDisable[socket] << SETVID_DECAY_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.SapmCtlLoc= k[socket] << SAPMCTL_LOCK_SHIFT) ); + + ppm->SapmCtl[socket] =3D CsrSapmCtl; + } + + ppm->PmaxConfig =3D (SetupData.SocketConfig.PowerManagementConfig.Use= PmaxOffsetTable ? USER_PMAX_USE_OFFSET_TABLE : 0 ) | + SetupData.SocketConfig.PowerManagementConfig.PmaxOf= fset | + (SetupData.SocketConfig.PowerManagementConfig.PmaxSi= gn ? USER_PMAX_NEGATIVE_BIT : 0); + + CsrPerfPlimitCtl =3D ( SetupData.SocketConfig.PowerManagementConfig.Pe= rfPLmtThshld << PERF_PLIMIT_THRESHOLD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PerfP= LimitClipC << PERF_PLIMIT_CLIP_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PerfP= limitDifferential << PERF_PLIMIT_DIFFERENTIAL_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PerfP= LimitEn << REPERF_PLIMIT_EN_SHIFT ); + ppm->PerPLimitCtl =3D CsrPerfPlimitCtl; + + // + // IssConfigTdpLevelInfo Bit[23:16]: the currently active Config TDP L= evel + // + ppm->Pst.ConfigTdpLevel =3D (UINT8) ((mIioUds->SystemStatus.IssConfigT= dpLevelInfo >> 16) & 0xFF); + ppm->Pst.CurrentPackageTdp =3D (mIioUds->SystemStatus.IssConfigTdpTdpI= nfo[0][ppm->Pst.ConfigTdpLevel] & 0x7FFF); + + for( socket =3D 0; socket < MAX_SOCKET; socket++) { + UpiInPkgCEntry[socket] =3D (SetupData.SocketConfig.PowerManagement= Config.Kti0In[socket] | + (SetupData.SocketConfig.Powe= rManagementConfig.Kti1In[socket] << 1) | + (SetupData.SocketConfig.Powe= rManagementConfig.Kti2In[socket] << 2) ); + + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio0In[socket= ]) { + PcieInPkgCEntry[socket] |=3D SET_PCIEx_MASK; + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio1In[socket= ]) { + PcieInPkgCEntry[socket] |=3D (SET_PCIEx_MASK << 4); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio2In[socket= ]) { + PcieInPkgCEntry[socket] |=3D (SET_PCIEx_MASK << 8); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio3In[socket= ]) { + PcieInPkgCEntry[socket] |=3D (SET_PCIEx_MASK << 12); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio4In[socket= ]) { + PcieInPkgCEntry[socket] |=3D (SET_PCIEx_MASK << 16); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio5In[socket= ]) { + PcieInPkgCEntry[socket] |=3D (SET_PCIEx_MASK << 20); + } + + } + + AdvPwrMgtCtl =3D (SetupData.SocketConfig.PowerManagementConfig.Sapmctl= ValCtl? PCD_CPU_SAPM_CTL_VAL_CTL : 0) | + (SetupData.SocketConfig.PowerManagementConfig.CurrentCon= fig? PCD_CPU_CURRENT_CONFIG : 0) | + (SetupData.SocketConfig.PowerManagementConfig.BootPState= ? PCU_CPU_EFFICIENT_BOOT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration= .ProcessorMsrLockControl? CPU_MSR_LOCK : 0) | + (SetupData.SocketConfig.PowerManagementConfig.TurboPower= LimitCsrLock? TURBO_LIMIT_CSR_LOCK : 0); + + AdvPwrMgtCtl |=3D SetupData.SocketConfig.PowerManagementConfig.PkgCstE= ntryValCtl; //PCD_CPU_PKG_CST_ENTRY_VAL_CTL + + if (SetupData.SocketConfig.PowerManagementConfig.ProcessorEistEnable = =3D=3D 0) { + AdvPwrMgtCtl |=3D PCU_CPU_EFFICIENT_BOOT; + } + + if (((CpuFamilyModelStepping >> 4) =3D=3D CPU_FAMILY_HSX) && SetupData= .SocketConfig.PowerManagementConfig.PriPlnCurCfgValCtl) { + AdvPwrMgtCtl |=3D PCD_CPU_PRI_PLN_CURR_CFG_CTL; + } + + if ((PackageCStateSetting > 0) && SetupData.SocketConfig.PowerManageme= ntConfig.DynamicL1) { + AdvPwrMgtCtl |=3D DYNAMIC_L1_DISABLE; + } + + if (SetupData.SocketConfig.PowerManagementConfig.SPTWorkaround) { + AdvPwrMgtCtl |=3D SPT_PCH_WORKAROUND; + } + + if (SetupData.SocketConfig.PowerManagementConfig.VccSAandVccIOdisable)= { + AdvPwrMgtCtl |=3D VCCSA_VCCIO_DISABLE; + } + ppm->AdvPwrMgtCtlFlags =3D AdvPwrMgtCtl; + + // MSR_POWER_CTL 0x1FC + MsrPowerCtlLow =3D ( SetupData.SocketConfig.PowerManagementConfig.PkgC= LatNeg << PCH_NEG_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.LTRSwI= nput << LTR_SW_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PwrPer= fTuning << PWR_PERF_TUNING_CFG_MODE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PwrPer= fSwitch << PWR_PERF_TUNING_ENABLE_DYN_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.SAPMCo= ntrol << PWR_PERF_TUNING_DISABLE_SAPM_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.EETurb= oDisable << EE_TURBO_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Procho= tLock << PROCHOT_LOCK_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Proces= sorC1eEnable << C1E_ENABLE_SHIFT ) | + ( (SetupData.SocketConfig.PowerManagementConfig.Enabl= eProcHot & 0x1) << DIS_PROCHOT_OUT_SHIFT ) | + ( (SetupData.SocketConfig.PowerManagementConfig.Enabl= eProcHot & 0x2) >> 1 ); + + // 5332865 BIOS needs to set bit 25 in MSR 0x1FC when enabling HWP aut= onomous out of band mode + if (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable = =3D=3D 2) { //if HWPM =3D OOB Mode + MsrPowerCtlLow |=3D ( 1 << PWR_PERF_TUNING_CFG_MODE_SHIFT ); + } + + ppm->PowerCtl.Dwords.Low =3D MsrPowerCtlLow; + + ppm->ProchotRatio =3D SetupData.SocketConfig.PowerManagementConfig.Pro= chotResponseRatio; + + if ((CpuFamilyModelStepping >> 4) =3D=3D CPU_FAMILY_HSX) { + // PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601 + MsrPriPlaneCurrentCfgCtlHigh =3D ( SetupData.SocketConfig.PowerManag= ementConfig.Psi3Code << PSI3_CODE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Psi3Thshld << PSI3_= THSHLD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Psi2Code << PSI2_CO= DE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Psi2Thshld << PSI2_= THSHLD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Psi1Code << PSI1_CO= DE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Psi1Thshld << PSI1_= THSHLD_SHIFT ); + } + + MsrPriPlaneCurrentCfgCtlLow =3D ( SetupData.SocketConfig.PowerManageme= ntConfig.PpcccLock << PPCCC_LOCK_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.CurrentLimit << CURRE= NT_LIMIT_SHIFT ); + + ppm->PP0CurrentCfg.Dwords.High =3D MsrPriPlaneCurrentCfgCtlHigh; + ppm->PP0CurrentCfg.Dwords.Low =3D MsrPriPlaneCurrentCfgCtlLow; + + // MSR_TURBO_POWER_LIMIT 0x610 + // CSR_TURBO_POWER_LIMIT 1:30:0:0xe8 + MsrTurboPowerLimitHigh =3D ( SetupData.SocketConfig.PowerManagementCon= fig.TurboPowerLimitLock << POWER_LIMIT_LOCK_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit2En << POWE= R_LIMIT_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PkgClmpLim2 << PKG_CL= MP_LIM_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit2Power ); + + MsrTurboPowerLimitLow =3D ( SetupData.SocketConfig.PowerManagementConf= ig.PowerLimit1Time << POWER_LIMIT_1_TIME_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit1En << POWE= R_LIMIT_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit1Power ); + + if ((CpuFamilyModelStepping >> 4) =3D=3D CPU_FAMILY_HSX) { + MsrTurboPowerLimitLow |=3D ( SetupData.SocketConfig.PowerManagement= Config.PkgClmpLim1 << PKG_CLMP_LIM_SHIFT ); + MsrTurboPowerLimitHigh |=3D ( SetupData.SocketConfig.PowerManagement= Config.PkgClmpLim2 << PKG_CLMP_LIM_SHIFT ); + } + + if ((CpuFamilyModelStepping >> 4) =3D=3D CPU_FAMILY_SKX) { + MsrTurboPowerLimitHigh |=3D ( SetupData.SocketConfig.PowerManagement= Config.PowerLimit2Time << POWER_LIMIT_1_TIME_SHIFT ); + } + + ppm->TurboPowerLimit.Dwords.Low =3D MsrTurboPowerLimitLow; + ppm->TurboPowerLimit.Dwords.High =3D MsrTurboPowerLimitHigh; + + // DYNAMIC_PERF_POWER_CTL (CSR 1:30:2:0x64) + CsrDynamicPerfPowerCtl =3D ( SetupData.SocketConfig.PowerManagementCon= fig.UncrPerfPlmtOvrdEn << UNCORE_PERF_PLIMIT_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.EetOverrideEn << EET_= OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.IoBwPlmtOvrdEn << IO_= BW_PLIMIT_OVERRIDE_ENABLE_SHIFT ) | + //( SetupData.SocketConfig.PowerManagementConfig.ImcApmOvrdEn << IMC= _APM_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.IomApmOvrdEn << IOM_A= PM_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.QpiApmOvrdEn << QPI_A= PM_OVERRIDE_ENABLE_SHIFT ); //4986218: Remove both changes from 4168487 + + if((CpuFamilyModelStepping >> 4) =3D=3D CPU_FAMILY_HSX) { + CsrDynamicPerfPowerCtl |=3D (( SetupData.SocketConfig.PowerManagemen= tConfig.EepLOverride << EEP_L_OVERRIDE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.EepLOverrideEn << E= EP_L_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.ITurboOvrdEn << I_T= URBO_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.CstDemotOvrdEN << C= ST_DEMOTION_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.TrboDemotOvrdEn << = TURBO_DEMOTION_OVERRIDE_ENABLE_SHIFT )); + } + + ppm->DynamicPerPowerCtl =3D CsrDynamicPerfPowerCtl; + + // CSR_PCIE_ILTR_OVRD (CSR 1:30:1:78) + // SW_LTR_OVRD (MSR 0xa02) -- not used + CsrPcieIltrOvrd =3D ( SetupData.SocketConfig.PowerManagementConfig.Snp= LatVld << SNOOP_LATENCY_VLD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.SnpLatOvrd << FORCE_S= NOOP_OVRD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.SnpLatMult << SNOOP_L= ATENCY_MUL_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.SnpLatVal << SNOOP_LA= TENCY_Value_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatVld << NON_S= NOOP_LATENCY_VLD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatOvrd << FORC= E_NON_SNOOP_OVRD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatMult << NON_= SNOOP_LATENCY_MUL_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatVal << NON_S= NOOP_LATENCY_Value_SHIFT ); + + ppm-> PcieIltrOvrd =3D CsrPcieIltrOvrd; + + if((CpuFamilyModelStepping >> 4) =3D=3D CPU_FAMILY_SKX) { //Need to ch= eck if programming needs to be limited only if Turbo mode is enabled. + for(i =3D 0; i < 8; i++) { + TurboRatioLimitRatioCores->RatioLimitRatio[i] =3D SetupData.Socket= Config.PowerManagementConfig.TurboRatioLimitRatio[i]; + + TurboRatioLimitRatioCores->RatioLimitRatioMask[i] =3D 0xFF; + if (SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitRa= tio[i] > 0) { + TurboRatioLimitRatioCores->RatioLimitRatioMask[i] =3D 0; + } + + TurboRatioLimitRatioCores->RatioLimitCoresMask[i] =3D 0xFF; + TurboRatioLimitRatioCores->RatioLimitCores[i] =3D 0; + if (SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitCo= res[i] !=3D 0xFF) { + TurboRatioLimitRatioCores->RatioLimitCoresMask[i] =3D 0; + TurboRatioLimitRatioCores->RatioLimitCores[i] =3D SetupData.Sock= etConfig.PowerManagementConfig.TurboRatioLimitCores[i]; + } + } + } + + MsrPerfBiasConfig =3D ( SetupData.SocketConfig.PowerManagementConfig.E= ngAvgTimeWdw1 << AVG_TIME_Window_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.P0TtlTimeLow1 << PO_T= OTAL_TIME_THSHLD_LOW_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.P0TtlTimeHigh1 << PO_= TOTAL_TIME_THSHLD_HIGH_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.AltEngPerfBIAS << ALT= _ENERGY_PERF_BIAS_SHIFT) | + ( SetupData.SocketConfig.PowerManagementConfig.WorkLdConfig << WORKL= D_CONFIG_SHIFT ); + + ppm->PerfBiasConfig.Dwords.Low =3D MsrPerfBiasConfig; + + // + //ProcessorHWPM-init as disabled. + // + ppm->Hwpm.HWPMNative =3D 0; + ppm->Hwpm.HWPMOOB =3D 0; + ppm->Hwpm.HWPMEnable =3D SetupData.SocketConfig.PowerManagementConfig.= ProcessorHWPMEnable; + ppm->Hwpm.AutoCState =3D SetupData.SocketConfig.PowerManagementConfig.= ProcessorAutonomousCstateEnable; + ppm->Hwpm.HWPMInterrupt =3D SetupData.SocketConfig.PowerManagementConf= ig.ProcessorHWPMInterrupt; + ppm->Hwpm.EPPEnable =3D SetupData.SocketConfig.PowerManagementConfig.P= rocessorEPPEnable; + ppm->Hwpm.EPPProfile =3D SetupData.SocketConfig.PowerManagementConfig.= ProcessorEppProfile; + + if ((SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable = =3D=3D 1) || + (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable = =3D=3D 3)) { + ppm->Hwpm.HWPMNative =3D SetupData.SocketConfig.PowerManagementConfi= g.ProcessorHWPMEnable; + }else if (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEn= able =3D=3D 2){ + ppm->Hwpm.HWPMOOB =3D SetupData.SocketConfig.PowerManagementConfig.P= rocessorHWPMEnable; + ppm->Hwpm.HWPMInterrupt =3D 0; + }else if (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEn= able =3D=3D 0){ + ppm->Hwpm.HWPMNative =3D 0; + ppm->Hwpm.HWPMOOB =3D 0; + ppm->Hwpm.HWPMInterrupt =3D 0; + ppm->Hwpm.EPPEnable =3D 0; + } + + ppm->Hwpm.APSrocketing =3D SetupData.SocketConfig.PowerManagementConfi= g.ProcessorAPSrocketing; + ppm->Hwpm.Scalability =3D SetupData.SocketConfig.PowerManagementConfig= .ProcessorScalability; + ppm->Hwpm.OutofBandAlternateEPB =3D SetupData.SocketConfig.PowerManage= mentConfig.ProcessorOutofBandAlternateEPB; + + if(SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorX2= apic && SetupData.SocketConfig.SocketProcessorCoreConfiguration.ForceX2Apic= Ids && + (CpuPolicyEx1 & PCD_CPU_X2APIC_BIT)) { //if user want to reprogram = > 8bit ApicId (must be X2Apic too) + CheckAndReAssignSocketId(); + } + + for(i =3D 0; i < NUM_CST_LAT_MSR; i++) { //3 CStateLatencyCtrl CSRs + ppm->Cst.LatencyCtrl[i].Dwords.Low =3D ( SetupData.SocketConfig.Powe= rManagementConfig.CStateLatencyCtrlValid[i] << VALID_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfi= g.CStateLatencyCtrlMultiplier[i] << MULTIPLIER_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfi= g.CStateLatencyCtrlValue[i] << VALUE_SHIFT ); + } + + if(SetupData.SocketConfig.PowerManagementConfig.C2C3TT) { //if option = is not AUTO + ppm->C2C3TT =3D (UINT32)SetupData.SocketConfig.PowerManagementConfig= .C2C3TT; + } else { + ppm->C2C3TT =3D 0x10; + } + + } //end - else + + CpuPolicy |=3D PCD_CPU_L3_CACHE_BIT; + + Status =3D PcdSet32S (PcdCpuProcessorFeatureUserConfiguration, CpuPolicy= ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status =3D PcdSet32S (PcdCpuProcessorFeatureUserConfigurationEx1, CpuPol= icyEx1); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + if (SetupData.SystemConfig.McBankWarmBootClearError =3D=3D 1) { + Status =3D PcdSetBoolS (PcdIsPowerOnReset, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status =3D PcdSetBoolS (PcdIsPowerOnReset, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + + // + // Cpu Driver could be dispatched after this protocol installed. + // + Handle =3D NULL; + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gIntelCpuPcdsSetDoneProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/Pla= tformCpuPolicy.inf b/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPo= licy/PlatformCpuPolicy.inf new file mode 100644 index 0000000000..dce03194e2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/PlatformCp= uPolicy.inf @@ -0,0 +1,80 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformCpuPolicy + FILE_GUID =3D 76A7B4FC-C8D5-462d-A4D2-6E88338A772A + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformCpuPolicyEntryPoint + +[Sources] + PlatformCpuPolicy.c + +[Packages] + UefiCpuPkg/UefiCpuPkg.dec + MdePkg/MdePkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + PcdLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseLib + MemoryAllocationLib + BaseMemoryLib + HobLib + IoLib + +[Protocols] + gIntelCpuPcdsSetDoneProtocolGuid + +[Pcd] + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfiguration + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfigurationEx1 + gEfiCpuTokenSpaceGuid.PcdCpuEnergyPolicy + gEfiCpuTokenSpaceGuid.PcdCpuAcpiLvl2Addr + gEfiCpuTokenSpaceGuid.PcdCpuPackageCStateLimit + gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue + gEfiCpuTokenSpaceGuid.PcdCpuClockModulationDutyCycle + gEfiCpuTokenSpaceGuid.PcdCpuHwCoordination + gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketCount + gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketNames + gEfiCpuTokenSpaceGuid.PcdPlatformCpuAssetTags + gEfiCpuTokenSpaceGuid.PcdIsPowerOnReset + gEfiCpuTokenSpaceGuid.PcdCpuDcuMode + gEfiCpuTokenSpaceGuid.PcdCpuTurboOverride + gEfiCpuTokenSpaceGuid.PcdCpuProcessorMsrLockCtrl + gEfiCpuTokenSpaceGuid.PcdCpuIioLlcWaysBitMask + gEfiCpuTokenSpaceGuid.PcdCpuExpandedIioLlcWaysBitMask + gEfiCpuTokenSpaceGuid.PcdPchTraceHubEn + gEfiCpuTokenSpaceGuid.PcdCpuQlruCfgBitMask + gEfiCpuTokenSpaceGuid.PcdSbspSelection + gEfiCpuTokenSpaceGuid.PcdCpuPmStructAddr + gEfiCpuTokenSpaceGuid.PcdCpuSocketId + gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress + gEfiCpuTokenSpaceGuid.PcdCpuRemoteWaysBitMask + gEfiCpuTokenSpaceGuid.PcdCpuRRQCountThreshold + gEfiCpuTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gOemSkuTokenSpaceGuid.PcdSetupData + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData + +[Depex] + gEfiVariableArchProtocolGuid + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSa= ve.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.c new file mode 100644 index 0000000000..158b19c169 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.c @@ -0,0 +1,256 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "S3NvramSave.h" +#include +#include +#include + +/** + + This function will retrieve the S3 data from HOBs produced by MRC + and will save it to NVRAM if the data is absent or different from + the previously saved data. + + @param VOID + + @retval VOID + +**/ +VOID +SaveS3StructToNvram ( + VOID + ) +{ + EFI_STATUS Status; + UINTN BufferSize; + UINTN CurrentHobSize; + UINTN S3ChunkSize; + CHAR16 EfiMemoryConfigVariable[] =3D L"MemoryCo= nfig0"; + EFI_HOB_GUID_TYPE *GuidHob =3D NULL; + VOID *HobData =3D NULL; + VOID *VariableData =3D NULL; + =20 + UINTN CompressedDataSize; + UINT32 ScratchSize; + VOID *CompressedData =3D NULL; + VOID *Scratch =3D NULL; + EFI_DECOMPRESS_PROTOCOL *Decompress =3D NULL; + VOID *CompressedVariableData =3D NULL; + UINTN CompressedBufferSize; + EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock =3D NULL; + =20 + // + // Get first S3 data HOB + // + GuidHob =3D GetFirstGuidHob (&gEfiMemoryConfigDataHobGuid); + + Status =3D gBS->LocateProtocol (&gEfiDecompressProtocolGuid, NULL, (VOID= **) &Decompress); + DEBUG((DEBUG_INFO, "[SaveMemoryConfigEntryPoint] Locate Decompress proto= col - %r\n", Status)); + if(EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + =20 + Status =3D gBS->LocateProtocol(&gEdkiiVariableLockProtocolGuid, NULL, (V= OID **)&VariableLock); + DEBUG((DEBUG_INFO, "[SaveMemoryConfigEntryPoint] Locate Variable Lock pr= otocol - %r\n", Status)); + ASSERT_EFI_ERROR(Status);=20 + + while (TRUE) { + if (GuidHob =3D=3D NULL) { + break; + } + HobData =3D GET_GUID_HOB_DATA(GuidHob);=20 + CurrentHobSize =3D GET_GUID_HOB_DATA_SIZE (GuidHob); + + DEBUG((EFI_D_INFO, " Current Hob Size(bytes) is: %d\n", CurrentHobSi= ze)); + // + // Use the HOB data to save Memory Configuration Data + // + BufferSize =3D CurrentHobSize; + Status =3D gBS->AllocatePool ( + EfiBootServicesData, + BufferSize, + (VOID**)&VariableData + ); + + ASSERT (VariableData !=3D NULL);=20 + S3ChunkSize =3D MAX_HOB_ENTRY_SIZE / 8; + DEBUG((EFI_D_INFO, " S3ChunkSize Hob Size(bytes): %d\n", S3ChunkSize= )); + + while (CurrentHobSize) { + if (S3ChunkSize > CurrentHobSize) { + S3ChunkSize =3D CurrentHobSize; + } + BufferSize =3D S3ChunkSize; + CompressedDataSize =3D 0; + ScratchSize =3D 0; + Status =3D gRT->GetVariable ( + EfiMemoryConfigVariable, + &gEfiMemoryConfigDataGuid, + NULL, + &CompressedDataSize, + NULL + ); + =20 + if(Status =3D=3D EFI_BUFFER_TOO_SMALL) { + Status =3D gBS->AllocatePool ( + EfiBootServicesData, + CompressedDataSize, + (VOID**)&CompressedData + ); + ASSERT (Status =3D=3D EFI_SUCCESS);=20 + } + + if(!EFI_ERROR (Status)) + { + Status =3D gRT->GetVariable ( + EfiMemoryConfigVariable, + &gEfiMemoryConfigDataGuid, + NULL, + &CompressedDataSize, + CompressedData + ); + + if (!EFI_ERROR (Status)) { + Status =3D Decompress->GetInfo ( + Decompress, + CompressedData, + (UINT32)CompressedDataSize, + (UINT32*)&BufferSize, + &ScratchSize + ); + } + + if (!EFI_ERROR (Status)) { + Status =3D gBS->AllocatePool ( + EfiBootServicesData, + ScratchSize, + (VOID**)&Scratch + ); + } + + if (!EFI_ERROR (Status)) { + Status =3D Decompress->Decompress ( + Decompress, + CompressedData, + (UINT32)CompressedDataSize, + VariableData, + (UINT32)BufferSize, + Scratch, + ScratchSize + ); + } + + if (EFI_ERROR (Status)) { + DEBUG((EFI_D_ERROR, "Getting variables error: 0x%x\n", Status)); + ASSERT (Status =3D=3D EFI_SUCCESS);=20 + } + + if(Scratch !=3D NULL) { + gBS->FreePool (Scratch); + Scratch =3D NULL; + } + } + + if(CompressedData !=3D NULL) { + gBS->FreePool (CompressedData); + CompressedData =3D NULL; + } + + if ( (EFI_ERROR(Status)) || (CompareMem (HobData, VariableData, S3Ch= unkSize) !=3D 0) ) { + Status =3D gBS->AllocatePool ( + EfiBootServicesData, + BufferSize, + (VOID**)&CompressedVariableData + ); + ASSERT (CompressedVariableData !=3D NULL);=20 + if (Status =3D=3D EFI_SUCCESS) { + CompressedBufferSize =3D BufferSize; + Status =3D Compress(HobData, S3ChunkSize, CompressedVariableData= , &CompressedBufferSize); + if (Status =3D=3D EFI_BUFFER_TOO_SMALL){ + gBS->FreePool(CompressedVariableData); + Status =3D gBS->AllocatePool( + EfiBootServicesData, + CompressedBufferSize, + (VOID**)&CompressedVariableData + ); + ASSERT (CompressedVariableData !=3D NULL); + Status =3D Compress(HobData, S3ChunkSize, CompressedVariableDa= ta, &CompressedBufferSize); + } + if(Status =3D=3D EFI_SUCCESS) { + Status =3D gRT->SetVariable ( + EfiMemoryConfigVariable, + &gEfiMemoryConfigDataGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTS= ERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + CompressedBufferSize, + CompressedVariableData + ); + } + if(CompressedVariableData !=3D NULL) { + gBS->FreePool(CompressedVariableData); + CompressedVariableData =3D NULL; + } + } + =20 + if (EFI_ERROR (Status)) { + DEBUG((EFI_D_ERROR, "Set variable error. Status: 0x%x\n", Status= )); + ASSERT_EFI_ERROR (Status); + } + } + // + // Lock the Memory Config Variable + // + Status =3D VariableLock->RequestToLock(VariableLock, EfiMemoryConfig= Variable, &gEfiMemoryConfigDataGuid); + ASSERT_EFI_ERROR(Status); + HobData =3D (UINT8 *) (HobData) + S3ChunkSize; + =20 + CurrentHobSize -=3D S3ChunkSize; + EfiMemoryConfigVariable[12]++; // Increment number in the string + } + // + // Get next S3 Config data hob, if none left, results NULL + // + GuidHob =3D GET_NEXT_HOB (GuidHob); // Increment to next HOB + GuidHob =3D GetNextGuidHob (&gEfiMemoryConfigDataHobGuid, GuidHob); /= / Now search for next MemConfig HOB + + if(VariableData !=3D NULL) { + gBS->FreePool(VariableData); + VariableData =3D NULL; + } + } + + return; +} + +EFI_STATUS +EFIAPI +S3NvramSaveEntry (=20 + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + )=20 +/** + + This is the main entry point of the S3 NVRAM Save module. + + @param ImageHandle - Handle for the image of this driver. + @param SystemTable - Pointer to the EFI System Table. + + @retval EFI_SUCCESS - Module launched successfully. + +**/ +{ + EFI_STATUS Status =3D EFI_SUCCESS; + =20 + // + // Save the s3 strututre from MRC into NVRAM if needed + // + SaveS3StructToNvram(); + =20 + return Status; + =20 +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSa= ve.h b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.h new file mode 100644 index 0000000000..ad8efe572a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.h @@ -0,0 +1,31 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include "SysHost.h" + +extern EFI_GUID gEfiMemoryConfigDataHobGuid; +extern EFI_GUID gEfiMemoryConfigDataGuid; + +#define MAX_HOB_ENTRY_SIZE 60*1024 + +EFI_STATUS +EFIAPI +S3NvramSaveEntry (=20 + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +); + +VOID +SaveS3StructToNvram ( + VOID +); diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSa= ve.inf b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.i= nf new file mode 100644 index 0000000000..0376b38bb1 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf @@ -0,0 +1,59 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D S3NvramSave + FILE_GUID =3D 62DC08AC-A651-4EE9-AF81-EAA9261E9780 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D S3NvramSaveEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Sources] + S3NvramSave.h + S3NvramSave.c + +[LibraryClasses] + UefiDriverEntryPoint + MemoryAllocationLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + HobLib + BaseMemoryLib + CompressLib + +[Protocols] + gEfiDecompressProtocolGuid + gEdkiiVariableLockProtocolGuid + +[Guids] + gEfiMemoryConfigDataGuid + gEfiMemoryConfigDataHobGuid + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Depex] + gEfiVariableArchProtocolGuid AND + gEfiVariableWriteArchProtocolGuid AND + gEfiDecompressProtocolGuid AND + gEdkiiVariableLockProtocolGuid + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoa= rdCommon.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoa= rdCommon.c new file mode 100644 index 0000000000..6b9efae0f6 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardCommo= n.c @@ -0,0 +1,625 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +VOID +SetBifurcations( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_BIFURCATION_ENTRY *BifurcationTable, + IN UINT8 BifurcationEntries +) +{ + UINT8 Socket; + UINT8 Iou; + UINT8 Index; + + for (Index =3D 0; Index < BifurcationEntries ; Index++) { + Socket =3D BifurcationTable[Index].Socket; + Iou =3D BifurcationTable[Index].IouNumber; + switch (Iou) { + case Iio_Iou0: + if (IioGlobalData->SetupData.ConfigIOU0[Socket]=3D=3DIIO_BIFURCATE_= AUTO) { + IioGlobalData->SetupData.ConfigIOU0[Socket] =3D BifurcationTable[= Index].Bifurcation; + } + break; + case Iio_Iou1: + if (IioGlobalData->SetupData.ConfigIOU1[Socket] =3D=3D IIO_BIFURCAT= E_AUTO) { + IioGlobalData->SetupData.ConfigIOU1[Socket] =3D BifurcationTable[= Index].Bifurcation; + } + break; + case Iio_Iou2: + if (IioGlobalData->SetupData.ConfigIOU2[Socket]=3D=3DIIO_BIFURCATE_= AUTO) { + IioGlobalData->SetupData.ConfigIOU2[Socket] =3D BifurcationTable[= Index].Bifurcation; + } + break; + case Iio_Mcp0: + if (IioGlobalData->SetupData.ConfigMCP0[Socket] =3D=3D IIO_BIFURCAT= E_AUTO) { + IioGlobalData->SetupData.ConfigMCP0[Socket] =3D BifurcationTabl= e[Index].Bifurcation; + } + break; + case Iio_Mcp1: + if (IioGlobalData->SetupData.ConfigMCP1[Socket] =3D=3D IIO_BIFURCAT= E_AUTO) { + IioGlobalData->SetupData.ConfigMCP1[Socket] =3D BifurcationTabl= e[Index].Bifurcation; + } + break; + default: + DEBUG((EFI_D_ERROR, "Invalid bifurcation table: Bad Iou (%d)", Iou)= ); + ASSERT(Iou); + break; + } + } +} + +VOID +EnableHotPlug ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN UINT8 Port, + IN UINT8 VppPort, + IN UINT8 VppAddress, + IN UINT8 PortOwnership + ) +{ + IioGlobalData->SetupData.SLOTHPCAP[Port]=3D ENABLE; + IioGlobalData->SetupData.SLOTAIP[Port] =3D ENABLE; // Attention Indica= tor Present + IioGlobalData->SetupData.SLOTPIP[Port] =3D ENABLE; // Power Indicator = Present + IioGlobalData->SetupData.SLOTMRLSP[Port]=3D ENABLE; // MRL Sensor Present + IioGlobalData->SetupData.SLOTABP[Port] =3D ENABLE; // Attention Button = Present + IioGlobalData->SetupData.SLOTPCP[Port] =3D ENABLE; // Power Controlled = Present + + if (PortOwnership =3D=3D PCIEAIC_OCL_OWNERSHIP){ + IioGlobalData->SetupData.SLOTAIP[Port] =3D DISABLE; // Attention Ind= icator Present + IioGlobalData->SetupData.SLOTPIP[Port] =3D DISABLE; // Power Indicat= or Present + } + if (PortOwnership =3D=3D VMD_OWNERSHIP){ + IioGlobalData->SetupData.SLOTABP[Port] =3D DISABLE; + IioGlobalData->SetupData.SLOTPCP[Port] =3D DISABLE; + IioGlobalData->SetupData.SLOTMRLSP[Port]=3D DISABLE; + } + // + // Set SLTCAP settings based on VMD/PCIe SSD Ownership + // + if ((PortOwnership =3D=3D PCIEAIC_OCL_OWNERSHIP) || + (PortOwnership =3D=3D VMD_OWNERSHIP)){ + IioGlobalData->SetupData.SLOTHPSUP[Port]=3D ENABLE; // HotPlug Surpr= ise + }=20 + + if (VppPort!=3D VPP_PORT_MAX) { + IioGlobalData->SetupData.VppEnable[Port]=3D ENABLE; + IioGlobalData->SetupData.VppPort[Port]=3D VppPort; + IioGlobalData->SetupData.VppAddress[Port] =3D VppAddress; + } else { + DEBUG((EFI_D_ERROR, "PCIE HOT Plug. Missing VPP values on slot table= \n")); + } +} + +VOID +ConfigSlots ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_SLOT_CONFIG_ENTRY *Slot, + IN UINT8 SlotEntries + ) +{ + UINT8 Index; + UINT8 Port; + + for (Index =3D0; Index < SlotEntries; Index ++) { + Port=3DSlot[Index].PortIndex; + if (Slot[Index].Hidden !=3D NOT_HIDE) { + IioGlobalData->SetupData.HidePEXPMenu[Port] =3D HIDE; + IioGlobalData->SetupData.PEXPHIDE[Port]=3D HIDE; + } + /// Check if slot is assigned. + if (Slot[Index].SlotNumber!=3D NO_SLT_IMP){ + IioGlobalData->SetupData.SLOTIMP[Port]=3D SLT_IMP; + IioGlobalData->SetupData.SLOTPSP[Port]=3DSlot[Index].SlotNumber; + IioGlobalData->SetupData.SLOTEIP[Port]=3DSlot[Index].InterLockPrese= nt; + if (Slot[Index].SlotPowerLimitScale!=3D PWR_SCL_MAX) { + IioGlobalData->SetupData.SLOTSPLS[Port] =3D Slot[Index].SlotPower= LimitScale; + IioGlobalData->SetupData.SLOTSPLV[Port] =3D Slot[Index].SlotPower= LimitValue; + } + if (Slot[Index].HotPlugCapable !=3D DISABLE) { + EnableHotPlug(IioGlobalData, Port, Slot[Index].VppPort, Slot[Inde= x].VppAddress, REGULAR_PCIE_OWNERSHIP); + } + } + } +} + +/** + Verify if and Slot should be implemented based on IOUX bifurcation set= tings. + + @param IioGlobalData Pointer to Iio Globals. + @param Port - Port Index + + @retval TRUE/FALSE to determine if an slot shoudl be implement= ed or not=20 + based on the IOUX bifurcation settings in c= ase user want to do an=20 + override and VMD is enabled. + +**/ +BOOLEAN +SlotImplemented( + IN OUT IIO_GLOBALS *IioGlobalData, + IN UINT8 Port + ){ + UINT8 IioIndex; + UINT8 PortIndex; + UINT8 Stack; + BOOLEAN SlotImp =3D FALSE; + + IioIndex =3D Port/NUMBER_PORTS_PER_SOCKET; + PortIndex =3D (Port - (NUMBER_PORTS_PER_SOCKET * IioIndex)); + // Stack =3D (((PortIndex + 3)/4) - 1) + (IioIndex*VMD_STACK_PER_SOCKET); + Stack =3D IioGlobalData->IioVar.IioVData.StackPerPort[IioIndex][PortInde= x]; + DEBUG((DEBUG_INFO, "SlotImplemented:IioIndex =3D %x, Stack =3D %x, Port = =3D %x, PortIndex =3D%x\n", IioIndex, Stack, Port, PortIndex)); + + switch(Stack){ + case IIO_PSTACK0: + if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] =3D=3D IIO_BIFURCA= TE_x4x4x4x4){ + SlotImp =3D TRUE; + } else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] =3D=3D IIO_= BIFURCATE_x4x4xxx8){ + if ((PortIndex =3D=3D PORT_1D_INDEX) || (PortIndex =3D=3D PORT_1C_= INDEX) || (PortIndex =3D=3D PORT_1A_INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] =3D=3D IIO_= BIFURCATE_xxx8x4x4){ + if ((PortIndex =3D=3D PORT_1C_INDEX) || (PortIndex =3D=3D PORT_1B_= INDEX) || (PortIndex =3D=3D PORT_1A_INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] =3D=3D IIO_= BIFURCATE_xxx8xxx8){ + if ((PortIndex =3D=3D PORT_1C_INDEX) || (PortIndex =3D=3D PORT_1A_= INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] =3D=3D IIO_= BIFURCATE_xxxxxx16){ + if (PortIndex =3D=3D PORT_1A_INDEX){ + SlotImp =3D TRUE; + } + } + break; + case IIO_PSTACK1: + if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] =3D=3D IIO_BIFURCA= TE_x4x4x4x4){ + SlotImp =3D TRUE; + } else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] =3D=3D IIO_= BIFURCATE_x4x4xxx8){ + if ((PortIndex =3D=3D PORT_2D_INDEX) || (PortIndex =3D=3D PORT_2C_= INDEX) || (PortIndex =3D=3D PORT_2A_INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] =3D=3D IIO_= BIFURCATE_xxx8x4x4){ + if ((PortIndex =3D=3D PORT_2C_INDEX) || (PortIndex =3D=3D PORT_2B_= INDEX) || (PortIndex =3D=3D PORT_2A_INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] =3D=3D IIO_= BIFURCATE_xxx8xxx8){ + if ((PortIndex =3D=3D PORT_2C_INDEX) || (PortIndex =3D=3D PORT_2A_= INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] =3D=3D IIO_= BIFURCATE_xxxxxx16){ + if (PortIndex =3D=3D PORT_2A_INDEX){ + SlotImp =3D TRUE; + } + } + break; + case IIO_PSTACK2: + if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] =3D=3D IIO_BIFURCA= TE_x4x4x4x4){ + SlotImp =3D TRUE; + } else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] =3D=3D IIO_= BIFURCATE_x4x4xxx8){ + if ((PortIndex =3D=3D PORT_3D_INDEX) || (PortIndex =3D=3D PORT_3C_= INDEX) || (PortIndex =3D=3D PORT_3A_INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] =3D=3D IIO_= BIFURCATE_xxx8x4x4){ + if ((PortIndex =3D=3D PORT_3C_INDEX) || (PortIndex =3D=3D PORT_3B_= INDEX) || (PortIndex =3D=3D PORT_3A_INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] =3D=3D IIO_= BIFURCATE_xxx8xxx8){ + if ((PortIndex =3D=3D PORT_3C_INDEX) || (PortIndex =3D=3D PORT_3A_= INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] =3D=3D IIO_= BIFURCATE_xxxxxx16){ + if (PortIndex =3D=3D PORT_3A_INDEX){ + SlotImp =3D TRUE; + } + } + break; + } + DEBUG((DEBUG_INFO, "SlotImplemented: =3D %x\n", SlotImp)); + return SlotImp; +} + +/** + Verify if VMD is enabled and override Slot conofgiration + based on the VMD settings + + @param IioGlobalData Pointer to Iio Globals. + @param Slot - Slot configuarion settings=20 + @param SlotEntries - Number of slot entries + + @retval None + +**/ +VOID +OverrideConfigSlots ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_SLOT_CONFIG_ENTRY *Slot, + IN UINT8 SlotEntries + ) +{ + UINT8 Index; + UINT8 Port; + UINT8 IioIndex; + UINT8 VmdPort; + UINT8 Stack; + + for (Index =3D0; Index < SlotEntries; Index ++) { + Port =3D Slot[Index].PortIndex; + // + // Check if Slot is capable of PcieSSD Solution and override the SLOT = Config values + // + if (Slot[Index].PcieSSDCapable){ + IioIndex =3D Port/NUMBER_PORTS_PER_SOCKET; + Stack =3D ((((Port - (NUMBER_PORTS_PER_SOCKET * IioIndex))+ 3)/4) - = 1) + (IioIndex*VMD_STACK_PER_SOCKET); + DEBUG((DEBUG_INFO, "Stack =3D %x, Port =3D %x\n", Stack, Port)); + + // + // check if VMD will own Pcie Root Port + // + if(IioGlobalData->SetupData.VMDEnabled[Stack]){ + VmdPort =3D ((IioIndex * VMD_PORTS_PER_SOCKET) + (Port - (NUMBER_P= ORTS_PER_SOCKET * IioIndex))) - 1; + if (IioGlobalData->SetupData.VMDPortEnable[VmdPort]){ + IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] =3D VMD= _OWNERSHIP; + } + } else { + + DEBUG((DEBUG_INFO, "IioGlobalData->SetupData.PcieAICEnabled[%x] = =3D %x\n",Stack, IioGlobalData->SetupData.PcieAICEnabled[Stack])); + // + // Check if Pcie AIC Card will be present on Pcie Root Port + // + if(IioGlobalData->SetupData.PcieAICEnabled[Stack]){ + // + // Force to have this port enabled by default for hot-plug. + // + IioGlobalData->SetupData.PciePortDisable[(IioIndex * NUMBER_PORT= S_PER_SOCKET) + Port] =3D ENABLE; + IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] =3D PCI= EAIC_OCL_OWNERSHIP; + DEBUG((DEBUG_ERROR, "Port =3D %x, PciePortDisable =3D %x\n",Port= ,IioGlobalData->SetupData.PciePortDisable[(IioIndex * NUMBER_PORTS_PER_SOCK= ET) + Port])); + } + } // No _VMD Ownership + + DEBUG((DEBUG_INFO, "PciePortOwnerShip[%x] =3D %x\n",Port, IioGlobalD= ata->IioVar.IioOutData.PciePortOwnership[Port])); + + // if PcieSSDSupport required do slot override settings accordingly + if((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] !=3D RE= GULAR_PCIE_OWNERSHIP) &&=20 + (SlotImplemented(IioGlobalData, Port) =3D=3D TRUE)){ + IioGlobalData->SetupData.SLOTIMP[Port]=3D SLT_IMP; + IioGlobalData->SetupData.SLOTPSP[Port]=3D 0x50 + Port; // Just = program a value for PCIEACI_OCL/VMD + IioGlobalData->SetupData.SLOTEIP[Port]=3D DISABLE; + + if (Slot[Index].SlotPowerLimitScale!=3D PWR_SCL_MAX) { + IioGlobalData->SetupData.SLOTSPLS[Port] =3D Slot[Index].SlotPo= werLimitScale; + IioGlobalData->SetupData.SLOTSPLV[Port] =3D Slot[Index].SlotPo= werLimitValue; + } + DEBUG((DEBUG_INFO,"Slot[Index].PcieSSDVppPort =3D %x\n", Slot[In= dex].PcieSSDVppPort)); + // Enable hot-plug if slot/port supports it + if (Slot[Index].PcieSSDVppPort !=3D VPP_PORT_MAX) { + DEBUG((DEBUG_INFO, "IioGlobalData->SetupData.VMDHotPlugEnable[%x= ] =3D %x\n",Stack,IioGlobalData->SetupData.VMDHotPlugEnable[Stack])); + DEBUG((DEBUG_INFO, "IioGlobalData->SetupData.PcieAICHotPlugEnabl= e[%x] =3D %x\n",Stack,IioGlobalData->SetupData.PcieAICHotPlugEnable[Stack])= ); + // Check if hot-plug is enabled for VMD or PCIeAIC case. + if (((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port]= =3D=3D VMD_OWNERSHIP) && (IioGlobalData->SetupData.VMDHotPlugEnable[Stack]= )) || + ((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] = =3D=3D PCIEAIC_OCL_OWNERSHIP) && (IioGlobalData->SetupData.PcieAICHotPlugEn= able[Stack]))) { + EnableHotPlug(IioGlobalData, Port, Slot[Index].PcieSSDVppPor= t, Slot[Index].PcieSSDVppAddress, IioGlobalData->IioVar.IioOutData.PciePort= Ownership[Port]); + DEBUG((DEBUG_INFO,"Enable HotPlug Done\n")); + } + } + // + // Unhide the port in order to get configured and it will be hid= e later for VMDLateSetup if VMD own the Pcie Root Port + // + IioGlobalData->SetupData.PEXPHIDE[Port]=3D NOT_HIDE; + }// PcieSSDSupport + }// PcieSSDCapable + }// Per Slot +} + + +/** + Auto determine which PCIe Root port to be hidden if its + lanes are assigned to its preceding root port...use the + Setup option variable of ConfigIOU to determine which ports + are to be hidden on each IOU for corresponding IIO + + @param IOUx - IOUx Index + @param IioIndex - Index to Iio + @param IioGlobalData Pointer to Iio Globals. + + @retval None + +**/ +VOID +CalculatePEXPHideFromIouBif ( + IN UINT8 Iou, + IN UINT8 IioIndex, + IN OUT IIO_GLOBALS *IioGlobalData +) +{ + + UINT8 *PXPHide, *HidePEXPMenu; + UINT8 CurrentIOUConfigValue; + UINT8 PXPOffset; + PXPHide =3D IioGlobalData->SetupData.PEXPHIDE; + HidePEXPMenu =3D IioGlobalData->SetupData.HidePEXPMenu; + CurrentIOUConfigValue =3D0; + + PXPOffset=3DIioIndex * NUMBER_PORTS_PER_SOCKET; + + switch (Iou) { + case Iio_Iou0: + CurrentIOUConfigValue =3D IioGlobalData->SetupData.ConfigIOU0[IioIndex= ]; + PXPOffset+=3D PORT_1A_INDEX; + break; + case Iio_Iou1: + CurrentIOUConfigValue =3D IioGlobalData->SetupData.ConfigIOU1[IioIndex= ]; + PXPOffset+=3D PORT_2A_INDEX; + break; + case Iio_Iou2: + CurrentIOUConfigValue =3D IioGlobalData->SetupData.ConfigIOU2[IioIndex= ]; + PXPOffset+=3D PORT_3A_INDEX; + break; + case Iio_Mcp0: + CurrentIOUConfigValue =3D IioGlobalData->SetupData.ConfigMCP0[IioIndex= ]; + PXPOffset+=3D PORT_4A_INDEX; + break; + case Iio_Mcp1: + CurrentIOUConfigValue =3D IioGlobalData->SetupData.ConfigMCP1[IioIndex= ]; + PXPOffset +=3D PORT_5A_INDEX; + break; + } + + switch(CurrentIOUConfigValue){ + case IIO_BIFURCATE_xxxxxxxx: + PXPHide[PXPOffset + Iio_PortA] =3D HIDE; // hide A + PXPHide[PXPOffset + Iio_PortB] =3D HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] =3D HIDE; // hide C + PXPHide[PXPOffset + Iio_PortD] =3D HIDE; // hide D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D HIDE; // hide the Setu= p menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] =3D HIDE; // hide the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D HIDE; // hide the Setu= p menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] =3D HIDE; // hide the Setu= p menu for D + break; + case IIO_BIFURCATE_x4x4xxx8: + PXPHide[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] =3D HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] =3D NOT_HIDE; // show D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortB] =3D HIDE; // hide the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show the Setu= p menu for D + HidePEXPMenu[PXPOffset + Iio_PortD] =3D NOT_HIDE; // show the Setu= p menu for B + break; + case IIO_BIFURCATE_xxx8x4x4: + PXPHide[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] =3D NOT_HIDE; // show B + PXPHide[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] =3D HIDE; // hide port D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show the Setu= p menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] =3D NOT_HIDE; // show the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show the Setu= p menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] =3D HIDE; // hide the Setu= p menu for D + break; + case IIO_BIFURCATE_xxx8xxx8: + PXPHide[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] =3D HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] =3D HIDE; // hide D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show the Setu= p menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] =3D HIDE; // hide the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show the Setu= p menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] =3D HIDE; // hide the Setu= p menu for D + break; + case IIO_BIFURCATE_xxxxxx16: + PXPHide[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] =3D HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] =3D HIDE; // hide C + PXPHide[PXPOffset + Iio_PortD] =3D HIDE; // hide D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show the Setu= p menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] =3D HIDE; // hide the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D HIDE; // hide the Setu= p menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] =3D HIDE; // hide the Setu= p menu for D + break; + default: + PXPHide[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] =3D NOT_HIDE; // show B + PXPHide[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] =3D NOT_HIDE; // show port D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show the Setu= p menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] =3D NOT_HIDE; // show the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show the Setu= p menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] =3D NOT_HIDE; // show the Setu= p menu for D + break; + } + + // + // Change PEXPHIDE setting to hide all PCIe port of a IOU if IIO_BIFURCA= TE_xxxxxxxx is set. + // And set ConfigIOUx/ConfigMCPx to default bifucation control value + // Bifurcation_Control[2:0] in IOU Bifurcation Control (PCIE_IOU_BIF_CTR= L) register should be 000b ~ 100b. + // + if (CurrentIOUConfigValue =3D=3D IIO_BIFURCATE_xxxxxxxx) { + switch (Iou) { + case Iio_Iou0: =20 + IioGlobalData->SetupData.ConfigIOU0[IioIndex] =3D IIO_BIFURCATE_x4x4= x4x4; + break; + case Iio_Iou1: + IioGlobalData->SetupData.ConfigIOU1[IioIndex] =3D IIO_BIFURCATE_x4x4= x4x4; + break; + case Iio_Iou2: + IioGlobalData->SetupData.ConfigIOU2[IioIndex] =3D IIO_BIFURCATE_x4x4= x4x4; + break; + case Iio_Mcp0: + IioGlobalData->SetupData.ConfigMCP0[IioIndex] =3D IIO_BIFURCATE_x4x4= x4x4; + break; + case Iio_Mcp1: + IioGlobalData->SetupData.ConfigMCP1[IioIndex] =3D IIO_BIFURCATE_x4x4= x4x4; + break; + default: + break; + } + } +} + + +VOID +DumpPort( + IIO_GLOBALS *IioGlobalData, + UINT8 Port, + UINT8 NumberOfPorts +) +{ + UINT8 Index; + DEBUG((EFI_D_INFO, "IDX, Port Hide, Slot Impl, Slot Number, HotPlug, Pci= eSSD, VppPort, VppAddress, Interlock\n")); + for (Index =3D Port; Index < (Port + NumberOfPorts); Index++ ) { + DEBUG((EFI_D_INFO, "%3d| %2d | %2d | %3d | %3d | %= 3d | 0x%02x | 0x%02x | %2d \n", \ + Index, \ + IioGlobalData->SetupData.PEXPHIDE[Index], \ + IioGlobalData->SetupData.SLOTIMP[Index], \ + IioGlobalData->SetupData.SLOTPSP[Index], \ + IioGlobalData->SetupData.SLOTHPCAP[Index], \ + IioGlobalData->IioVar.IioOutData.PciePortOwnership[= Index], \ + IioGlobalData->SetupData.VppPort[Index], \ + IioGlobalData->SetupData.VppAddress[Index],\ + IioGlobalData->SetupData.SLOTEIP[Index])); + } + } +/// Dump iio configuration. Dump the current IIO configuration to the seri= al +/// log. +VOID +DumpIioConfiguration( + IN UINT8 iio, + IN IIO_GLOBALS *IioGlobalData +) +{ + UINT8 Iou; + UINT8 PortIndex; + UINT8 Bifurcation; + UINT8 IouPorts; + PortIndex =3D iio * NUMBER_PORTS_PER_SOCKET; + /// First dump the socket number; + DEBUG((EFI_D_INFO, "Socket number: %d \n", iio)); + + /// Dump DMI configuration: + if ((iio =3D=3D 0) && (PortIndex =3D=3D 0)){ + DEBUG((EFI_D_INFO, "PORT 0: DMI Port\n")); + } else { + DEBUG((EFI_D_INFO, "PORT 0: DMI Port working as PCIE\n")); + DumpPort(IioGlobalData, PortIndex, 1); + } + IouPorts=3D4; + /// Dump IOU bifurcations: + for (Iou =3D Iio_Iou0; Iou< Iio_IouMax; Iou ++) { + /// Reset port index. + PortIndex =3D iio * NUMBER_PORTS_PER_SOCKET; + // Get the bifurcation + switch (Iou) { + case Iio_Iou0: + Bifurcation =3D IioGlobalData->SetupData.ConfigIOU0[iio]; + PortIndex +=3D PORT_1A_INDEX; + DEBUG((EFI_D_INFO, "IUO0: Root Port 1, Bifurcation: %d\n", Bifur= cation)); + break; + case Iio_Iou1: + Bifurcation =3D IioGlobalData->SetupData.ConfigIOU1[iio]; + PortIndex +=3D PORT_2A_INDEX; + DEBUG((EFI_D_INFO, "IUO1: Root Port 2, Bifurcation: %d\n", Bifur= cation)); + break; + case Iio_Iou2: + Bifurcation =3D IioGlobalData->SetupData.ConfigIOU2[iio]; + PortIndex +=3D PORT_3A_INDEX; + DEBUG((EFI_D_INFO, "IUO2: Root Port 3, Bifurcation: %d\n", Bifur= cation)); + break; + case Iio_Mcp0: + Bifurcation =3D IioGlobalData->SetupData.ConfigMCP0[iio]; + PortIndex +=3D PORT_4A_INDEX; + DEBUG((EFI_D_INFO, "MCP0, Bifurcation: %d\n", Bifurcation)); + break; + case Iio_Mcp1: + Bifurcation =3D IioGlobalData->SetupData.ConfigMCP1[iio]; + PortIndex +=3D PORT_5A_INDEX; + DEBUG((EFI_D_INFO, "MCP1, Bifurcation: %d\n", Bifurcation)); + break; + default: + DEBUG((EFI_D_INFO, "Iou no detected =3D %d",Iou)); + break; + } + DumpPort(IioGlobalData, PortIndex, IouPorts); + } + +} + +UINT8 +GetUplinkPortInformationCommon ( + IN UINT8 IioIndex +) +{ + UINT8 UplinkPortIndex =3D 0xFF; + + if (IioIndex =3D=3D 0) { + UplinkPortIndex =3D PcdGet8(PcdOemSkuUplinkPortIndex); + } + + return UplinkPortIndex; +} +/** + + SystemIioPortBifurcationInit - Program the UDS data structure with OEM I= IO init values + for SLOTs and Bifurcation. + + @param mSB - pointer to this protocol + @param IioUds - Pointer to the IIO UDS datastructure. + + @retval EFI_SUCCESS + +**/ +VOID +SystemIioPortBifurcationInitCommon ( + IIO_GLOBALS *IioGlobalData, + IIO_BIFURCATION_ENTRY **BifurcationTable, + UINT8 *BifurcationEntries, + IIO_SLOT_CONFIG_ENTRY **SlotTable, + UINT8 *SlotEntries +) +{ + + UINT8 PortIndex;//, iio; + + /// This function outline: + //// 1 Based on platform apply the default bifurcation and slot configur= ation. + //// 2 Apply dynamic overrides based on GPIO and other configurations. + //// 3 Hide unused ports due bifurcation. + + for (PortIndex =3D 0; PortIndex < MAX_SOCKET*NUMBER_PORTS_PER_SOCKET; Po= rtIndex++) { + IioGlobalData->SetupData.PEXPHIDE[PortIndex] =3D 0; + IioGlobalData->SetupData.HidePEXPMenu[PortIndex] =3D 0; + } + + *BifurcationEntries =3D 0; + *SlotEntries =3D 0; + + *BifurcationTable =3D (IIO_BIFURCATION_ENTRY *)(UINTN)PcdGet64 (PcdIio= BifurcationTable); + *BifurcationEntries =3D PcdGet8 (PcdIioBifurcationTableEntries); + *SlotTable =3D (IIO_SLOT_CONFIG_ENTRY *)(UINTN)PcdGet64 (PcdIio= SlotTable); + *SlotEntries =3D PcdGet8 (PcdIioSlotTableEntries); +} + +VOID +SystemHideIioPortsCommon( + IIO_GLOBALS *IioGlobalData, + UINT8 IioIndex +) +{ + CalculatePEXPHideFromIouBif(Iio_Iou0, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif(Iio_Iou1, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif(Iio_Iou2, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif(Iio_Mcp0, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif(Iio_Mcp1, IioIndex, IioGlobalData); + DumpIioConfiguration(IioIndex, IioGlobalData); +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoa= rdPei.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardP= ei.c new file mode 100644 index 0000000000..9d05a39c68 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.c @@ -0,0 +1,255 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SystemBoardPei.h" + +#include +#include + +#include + +extern IIO_BIFURCATION_ENTRY mIioBifurcationTable[]; +extern UINT8 mIioBifurcationTableEntries; +extern IIO_SLOT_CONFIG_ENTRY mIioSlotTable[]; +extern UINT8 mIioSlotTableEntries; + +// +// System board PPI structure +// +static SYSTEM_BOARD_PPI mSystemBoardPpi =3D { + SystemIioPortBifurcationInit, // Set IIO Bifurcation ports config= uration + GetUplinkPortInformation, +}; + +static EFI_PEI_PPI_DESCRIPTOR mSystemBoardPpiDesc =3D { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiSystemBoardPpiGuid, + &mSystemBoardPpi +}; + +/** + + GetUplinkPortInformation - Get uplink port information + + @param IioIndex - socket ID. + + @retval PortIndex for uplink port + +**/ +UINT8 +EFIAPI +GetUplinkPortInformation ( + IN UINT8 IioIndex +) +{ + UINT8 UplinkPortIndex; + + UplinkPortIndex =3D GetUplinkPortInformationCommon(IioIndex); + return UplinkPortIndex; +} + +/** + + SystemIioPortBifurcationInit - Program the UDS data structure with OEM I= IO init values + for SLOTs and Bifurcation. + + @param mSB - pointer to this protocol + @param IioUds - Pointer to the IIO UDS datastructure. + + @retval EFI_SUCCESS + +**/ +VOID +InternalSystemIioPortBifurcationInitCommon ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN OUT IIO_BIFURCATION_ENTRY **BifurcationTable, + IN OUT UINT8 *BifurcationEntries, + IN OUT IIO_SLOT_CONFIG_ENTRY **SlotTable, + IN OUT UINT8 *SlotEntries +) +{ + + UINT8 PortIndex;//, iio; + =20 + /// This function outline: + //// 1 Based on platform apply the default bifurcation and slot configur= ation. + //// 2 Apply dynamic overrides based on GPIO and other configurations. + //// 3 Hide unused ports due bifurcation. + + for (PortIndex =3D 0; PortIndex < MAX_SOCKET*NUMBER_PORTS_PER_SOCKET; Po= rtIndex++) { + IioGlobalData->SetupData.PEXPHIDE[PortIndex] =3D 0; + IioGlobalData->SetupData.HidePEXPMenu[PortIndex] =3D 0; + } + + *BifurcationEntries =3D 0; + *SlotEntries =3D 0; + + // Purley Intel boards are not Multi-PCH + IioGlobalData->IioVar.IioVData.MultiPch =3D 0; + + *BifurcationTable =3D (IIO_BIFURCATION_ENTRY *)(UINTN)PcdGet64 (PcdIio= BifurcationTable); + *BifurcationEntries =3D PcdGet8 (PcdIioBifurcationTableEntries); + *SlotTable =3D (IIO_SLOT_CONFIG_ENTRY *)(UINTN)PcdGet64 (PcdIio= SlotTable); + *SlotEntries =3D PcdGet8 (PcdIioSlotTableEntries); +} + +/** + + SystemIioPortBifurcationInit - Program the IIO_GLOBALS data structure wi= th OEM IIO init values + for SLOTs and Bifurcation. + + @param mSB - pointer to this protocol + @param IioUds - Pointer to the IIO UDS datastructure. + + @retval EFI_SUCCESS + +**/ +VOID +SystemIioPortBifurcationInit ( + IN IIO_GLOBALS *IioGlobalData +) +{ + + UINT8 IioIndex; + IIO_BIFURCATION_ENTRY *BifurcationTable =3D NULL; + UINT8 BifurcationEntries; + IIO_SLOT_CONFIG_ENTRY *SlotTable =3D NULL; + UINT8 SlotEntries; + + // This function outline: + // 1. Based on platform apply the default bifurcation and slot configura= tion. + // 2. Apply dynamic overrides based on GPIO and other configurations. + // 3. Hide unused ports due bifurcation. + + SystemIioPortBifurcationInitCommon(IioGlobalData, &BifurcationTable, &Bi= furcationEntries, &SlotTable, &SlotEntries); + /// Set the default bifurcations for this platform. + SetBifurcations(IioGlobalData, BifurcationTable, BifurcationEntries); + ConfigSlots(IioGlobalData, SlotTable, SlotEntries); + OverrideConfigSlots(IioGlobalData, SlotTable, SlotEntries); + + // All overrides have been applied now. + // Hide root ports whose lanes are assigned preceding ports. + for (IioIndex =3D Iio_Socket0; IioIndex < MaxIIO; IioIndex++) { + if (IioGlobalData->IioVar.IioVData.SocketPresent[IioIndex]) { + SystemHideIioPortsCommon(IioGlobalData, IioIndex); + } + } +} + + +/** + + This function dump raw data. + + @param Data raw data + @param Size raw data size + +**/ +VOID +InternalDumpData ( + IN UINT8 *Data, + IN UINTN Size + ) +{ + UINTN Index; + for (Index =3D 0; Index < Size; Index++) { + DEBUG ((EFI_D_INFO, "%02x", (UINTN)Data[Index])); + } +} + +/** + + This function dump raw data with colume format. + + @param Data raw data + @param Size raw data size + +**/ +VOID +InternalDumpHex ( + IN UINT8 *Data, + IN UINTN Size + ) +{ + UINTN Index; + UINTN Count; + UINTN Left; + +#define COLUME_SIZE (16 * 2) + + Count =3D Size / COLUME_SIZE; + Left =3D Size % COLUME_SIZE; + for (Index =3D 0; Index < Count; Index++) { + DEBUG ((EFI_D_INFO, "%04x: ", Index * COLUME_SIZE)); + InternalDumpData (Data + Index * COLUME_SIZE, COLUME_SIZE); + DEBUG ((EFI_D_INFO, "\n")); + } + + if (Left !=3D 0) { + DEBUG ((EFI_D_INFO, "%04x: ", Index * COLUME_SIZE)); + InternalDumpData (Data + Index * COLUME_SIZE, Left); + DEBUG ((EFI_D_INFO, "\n")); + } +} + +VOID +DumpConfig ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "PcdSetupData - 0x%x\n", PcdGetSize (PcdSetupData))); + InternalDumpHex (PcdGetPtr (PcdSetupData), PcdGetSize (PcdSetupData)); + DEBUG ((DEBUG_INFO, "PcdPchRcConfigurationData - 0x%x\n", PcdGetSize (Pc= dPchRcConfigurationData))); + InternalDumpHex (PcdGetPtr (PcdPchRcConfigurationData), PcdGetSize (PcdP= chRcConfigurationData)); + DEBUG ((DEBUG_INFO, "PcdSocketIioConfigData - 0x%x\n", PcdGetSize (PcdSo= cketIioConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketIioConfigData), PcdGetSize (PcdSock= etIioConfigData)); + DEBUG ((DEBUG_INFO, "PcdSocketCommonRcConfigData - 0x%x\n", PcdGetSize (= PcdSocketCommonRcConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketCommonRcConfigData), PcdGetSize (Pc= dSocketCommonRcConfigData)); + DEBUG ((DEBUG_INFO, "PcdSocketMpLinkConfigData - 0x%x\n", PcdGetSize (Pc= dSocketMpLinkConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketMpLinkConfigData), PcdGetSize (PcdS= ocketMpLinkConfigData)); + DEBUG ((DEBUG_INFO, "PcdSocketMemoryConfigData - 0x%x\n", PcdGetSize (Pc= dSocketMemoryConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketMemoryConfigData), PcdGetSize (PcdS= ocketMemoryConfigData)); + DEBUG ((DEBUG_INFO, "PcdSocketPowerManagementConfigData - 0x%x\n", PcdGe= tSize (PcdSocketPowerManagementConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketPowerManagementConfigData), PcdGetS= ize (PcdSocketPowerManagementConfigData)); + DEBUG ((DEBUG_INFO, "PcdSocketProcessorCoreConfigData - 0x%x\n", PcdGetS= ize (PcdSocketProcessorCoreConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketProcessorCoreConfigData), PcdGetSiz= e (PcdSocketProcessorCoreConfigData)); +} + +// +// PEI entry point - SystemBoardPpi entry point +// +/** + + PEI system board PPI intialization main entry point. This will setup up = a PPI that will handle providing system board level + configuration for the platform. + + @param FileHandle Pointer to the PEIM FFS file header. + @param PeiServices General purpose services available to every PEI= M. + + @retval EFI_SUCCESS Operation completed successfully. + @retval Otherwise System board initialization failed. +**/ +EFI_STATUS +EFIAPI +SystemBoardPeiEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + DEBUG ((EFI_D_ERROR, "--> SystemBoard PEI BoardDetection\n")); + + //DumpConfig (); + + // + // Initialize system board information PPI + // + Status =3D PeiServicesInstallPpi(&mSystemBoardPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoa= rdPei.h b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardP= ei.h new file mode 100644 index 0000000000..1adc59cb3d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.h @@ -0,0 +1,182 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_SYSTEM_BOARD_PPI_H_ +#define _EFI_SYSTEM_BOARD_PPI_H_ + +#include +#include +#include + + +// GUID +#include +#include + +// PPI +#include +#include +#include +#include + + +// Library +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +// CMOS access Port address +#define LAST_CMOS_BYTE 0x7F +#define NMI_OFF 0x80 +#define B_PCH_RTC_REGB_SRBRST 0x02 // Value to be reset to during POST +#define R_PCH_RTC_REGD 0x0D // CMOS Register D Status +#define R_PCH_RTC_REGE 0x0E // CMOS Register E Status +#define B_PCH_RTC_REGE_INVTIM 0x04 // CMOS invalid time found + +#define TIMER1_CONTROL_PORT 0x43 +#define TIMER1_COUNT_PORT 0x41 +#define LOAD_COUNTER1_LSB 0x54 +#define COUNTER1_COUNT 0x12 +// +// Reset Generator I/O Port +// +#define RESET_GENERATOR_PORT 0xCF9 + +//-----------------------------------------------------------------------; +// PCH: Chipset Configuration Register Equates +//-----------------------------------------------------------------------; +#define ICH_RCRB_IRQ0 0 +#define ICH_RCRB_IRQA 1 +#define ICH_RCRB_IRQB 2 +#define ICH_RCRB_IRQC 3 +#define ICH_RCRB_IRQD 4 +#define ICH_RCRB_PIRQA 0 +#define ICH_RCRB_PIRQB 1 +#define ICH_RCRB_PIRQC 2 +#define ICH_RCRB_PIRQD 3 +#define ICH_RCRB_PIRQE 4 +#define ICH_RCRB_PIRQF 5 +#define ICH_RCRB_PIRQG 6 +#define ICH_RCRB_PIRQH 7 + +// +// From WBG Soft Straps WIP.xlsx +// +#define WBG_DOWNSKU_STRAP_DSKU 0x80046000 +#define WBG_DOWNSKU_STRAP_BSKU 0x8004E003 +#define WBG_DOWNSKU_STRAP_TSKU 0x00044000 + +#define PCHSTRAP_9 9 +#define PCHSTRAP_10 10 +#define PCHSTRAP_16 16 +#define PCHSTRAP_17 17 + +#define RESET_PORT 0x0CF9 +#define CLEAR_RESET_BITS 0x0F1 +#define COLD_RESET 0x02 // Set bit 1 for cold reset +#define RST_CPU 0x04 // Setting this bit triggers a res= et of the CPU +#define FULL_RESET 0x08 // Set bit 4 with bit 1 for full r= eset + +// +// PPI functions +// + +VOID +SetBifurcations( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_BIFURCATION_ENTRY *BifurcationTable, + IN UINT8 BifurcationEntries +); + +VOID +EnableHotPlug ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN UINT8 Port, + IN UINT8 VppPort, + IN UINT8 VppAddress, + IN UINT8 PortOwnership + ); + + +VOID +ConfigSlots ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_SLOT_CONFIG_ENTRY *Slot, + IN UINT8 SlotEntries + ); + +VOID +OverrideConfigSlots ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_SLOT_CONFIG_ENTRY *Slot, + IN UINT8 SlotEntries + ); + =20 +VOID +CalculatePEXPHideFromIouBif ( + IN UINT8 Iou, + IN UINT8 IioIndex, + IN OUT IIO_GLOBALS *IioGlobalData +); + +VOID +DumpIioConfiguration( + IN UINT8 iio, + IN IIO_GLOBALS *IioGlobalData +); + +VOID +OverrideDefaultBifSlots( + IN IIO_GLOBALS *IioGlobalData +); + +UINT8 +GetUplinkPortInformationCommon ( + IN UINT8 IioIndex +); + +VOID +SystemIioPortBifurcationInitCommon ( + IIO_GLOBALS *IioGlobalData, + IIO_BIFURCATION_ENTRY **BifurcationTable, + UINT8 *BifurcationEntries, + IIO_SLOT_CONFIG_ENTRY **SlotTable, + UINT8 *SlotEntries +); + +VOID +SystemHideIioPortsCommon( + IIO_GLOBALS *IioGlobalData, + UINT8 IioIndex +); + +UINT8 +GetUplinkPortInformation ( + IN UINT8 IioIndex +); + +VOID +SystemIioPortBifurcationInit ( + IN IIO_GLOBALS *IioGlobalData + ); + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoa= rdPei.inf b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoar= dPei.inf new file mode 100644 index 0000000000..9bd2dfbb59 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.i= nf @@ -0,0 +1,76 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SystemBoardPei + FILE_GUID =3D C0989520-2F0D-470a-9BE4-2969E0EC5641 + MODULE_TYPE =3D PEIM + ENTRY_POINT =3D SystemBoardPeiEntry + +[Sources] + SystemBoardPei.c + SystemBoardCommon.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + PeiServicesLib + PeimEntryPoint + DebugLib + HobLib + IoLib + PciLib + PcdLib + PeiServicesTablePointerLib + PciExpressLib + PchInfoLib + GpioLib + TimerLib + PchCycleDecodingLib + PchSbiAccessLib + PchInfoLib + PchP2sbLib + PchPcrLib + MmPciLib + PcdLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gOemSkuTokenSpaceGuid.PcdIioBifurcationTable + gOemSkuTokenSpaceGuid.PcdIioBifurcationTableEntries + gOemSkuTokenSpaceGuid.PcdIioSlotTable + gOemSkuTokenSpaceGuid.PcdIioSlotTableEntries + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex + + gOemSkuTokenSpaceGuid.PcdSetupData + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData + + +[Ppis] + gEfiPeiSystemBoardPpiGuid ## PRODUCES + gEfiPeiSmbus2PpiGuid + gPchPlatformPolicyPpiGuid + +[Depex] + gEfiPeiPcdPpiGuid AND + gEfiPeiReadOnlyVariable2PpiGuid + --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Tue, 11 May 2021 02:48:57 -0700 IronPort-SDR: BirPgH+xiYGHk2USW+I8US+3way+qh4P63Js5FW8h6G3oSuNukZD19Kip5c3fIZ+6bvCY2xN6q mZbO5vU3VdEA== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="199469658" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="199469658" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:51 -0700 IronPort-SDR: Vbk2IHHHzSfBVbAZS7yTMRQmT1tUCp9imY0BDZ858VkaH5jngK6Pkp/J271nzgt98tihvYabzl ttkyKeevvZzQ== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436573989" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:49 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 10/18] PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add PlatformPciTree_WFP.asi Date: Tue, 11 May 2021 02:48:18 -0700 Message-Id: <20210511094826.12495-11-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: OfT6CPpvz1eD4uEOieT0opjdx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726539; bh=6itr+u0chtbe0088T4X35rwUAb18tkhQONcROfSKbmQ=; h=Cc:Date:From:Reply-To:Subject:To; b=XUX1jRQN0I8L9jJQI3Bwu72KVJNsasMnXBs7HT5X2EXRqO7DdTWUu430tCf29LwbWbz gV57iR4D/5X/JYtvWF3WuSxLm9Vrg+UDhxxPmpGxRWZIjZSMiwjSQWkZ7zztlPA2B0bkY +7wW9zRn2HIK+8XThtH2sLlDGNXif2zNu+c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../BoardAcpiDxe/Dsdt/PlatformPciTree_WFP.asi | 8070 +++++++++++++++++ 1 file changed, 8070 insertions(+) create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PlatformPciTree_WFP.asi diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platf= ormPciTree_WFP.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/PlatformPciTree_WFP.asi new file mode 100644 index 0000000000..457b8bba4a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformPciT= ree_WFP.asi @@ -0,0 +1,8070 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +Scope (\_SB) { + + Name (PR00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PC00 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CB0A]: CB3DMA on PC00 + // [CB0E]: CB3DMA on PC00 + Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CB0B]: CB3DMA on PC00 + // [CB0F]: CB3DMA on PC00 + Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [CB0C]: CB3DMA on PC00 + // [CB0G]: CB3DMA on PC00 + Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [CB0D]: CB3DMA on PC00 + // [CB0H]: CB3DMA on PC00 + Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [IIM0]: IIOMISC on PC00 + Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UBX0]: Uncore 0 UBOX Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [DISP]: Display Controller + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [IHC2]: HECI #2 + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [TERM]: Thermal Subsystem on PCH + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [CAMR]: Camera IO Host Controller on PCH + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [HEC2]: HECI #2 on PCH + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [SAT1]: SATA controller 1 on PCH + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [NAN1]: NAND Cycle Router on PCH + Package() { 0x0018FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RP17]: PCIE PCH Root Port #17 + Package() { 0x001BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RP18]: PCIE PCH Root Port #18 + Package() { 0x001BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [RP19]: PCIE PCH Root Port #19 + Package() { 0x001BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [RP20]: PCIE PCH Root Port #20 + Package() { 0x001BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package() { 0x001CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package() { 0x001CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package() { 0x001CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package() { 0x001CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UAR0]: UART #0 on PCH + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [UAR1]: UART #1 on PCH + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [SPI0]: SPI #0 on PCH + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [SPI1]: SPI #1 on PCH + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PC00 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [CB0A]: CB3DMA on PC00 + // [CB0E]: CB3DMA on PC00 + Package() { 0x0004FFFF, 0, 0, 16 }, + // [CB0B]: CB3DMA on PC00 + // [CB0F]: CB3DMA on PC00 + Package() { 0x0004FFFF, 1, 0, 17 }, + // [CB0C]: CB3DMA on PC00 + // [CB0G]: CB3DMA on PC00 + Package() { 0x0004FFFF, 2, 0, 18 }, + // [CB0D]: CB3DMA on PC00 + // [CB0H]: CB3DMA on PC00 + Package() { 0x0004FFFF, 3, 0, 19 }, + // [IIM0]: IIOMISC on PC00 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX0]: Uncore 0 UBOX Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [DISP]: Display Controller + Package() { 0x000FFFFF, 0, 0, 16 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package() { 0x0010FFFF, 0, 0, 16 }, + // [IHC2]: HECI #2 + Package() { 0x0010FFFF, 1, 0, 17 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package() { 0x0010FFFF, 2, 0, 18 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package() { 0x0010FFFF, 3, 0, 19 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package() { 0x0011FFFF, 0, 0, 16 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 0, 0, 16 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package() { 0x0014FFFF, 1, 0, 17 }, + // [TERM]: Thermal Subsystem on PCH + Package() { 0x0014FFFF, 2, 0, 18 }, + // [CAMR]: Camera IO Host Controller on PCH + Package() { 0x0014FFFF, 3, 0, 19 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package() { 0x0016FFFF, 0, 0, 16 }, + // [HEC2]: HECI #2 on PCH + Package() { 0x0016FFFF, 1, 0, 17 }, + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 2, 0, 18 }, + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 3, 0, 19 }, + // [SAT1]: SATA controller 1 on PCH + Package() { 0x0017FFFF, 0, 0, 16 }, + // [NAN1]: NAND Cycle Router on PCH + Package() { 0x0018FFFF, 0, 0, 16 }, + // [RP17]: PCIE PCH Root Port #17 + Package() { 0x001BFFFF, 0, 0, 16 }, + // [RP18]: PCIE PCH Root Port #18 + Package() { 0x001BFFFF, 1, 0, 17 }, + // [RP19]: PCIE PCH Root Port #19 + Package() { 0x001BFFFF, 2, 0, 18 }, + // [RP20]: PCIE PCH Root Port #20 + Package() { 0x001BFFFF, 3, 0, 19 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package() { 0x001CFFFF, 0, 0, 16 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package() { 0x001CFFFF, 1, 0, 17 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package() { 0x001CFFFF, 2, 0, 18 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package() { 0x001CFFFF, 3, 0, 19 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package() { 0x001DFFFF, 0, 0, 16 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package() { 0x001DFFFF, 1, 0, 17 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package() { 0x001DFFFF, 2, 0, 18 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package() { 0x001DFFFF, 3, 0, 19 }, + // [UAR0]: UART #0 on PCH + Package() { 0x001EFFFF, 0, 0, 20 }, + // [UAR1]: UART #1 on PCH + Package() { 0x001EFFFF, 1, 0, 21 }, + // [SPI0]: SPI #0 on PCH + Package() { 0x001EFFFF, 2, 0, 22 }, + // [SPI1]: SPI #1 on PCH + Package() { 0x001EFFFF, 3, 0, 23 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package() { 0x001FFFFF, 0, 0, 16 }, + }) + + Name (AH00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PC00 + Package() { 0x0000FFFF, 0, 0, 31 }, + // [CB0A]: CB3DMA on PC00 + // [CB0E]: CB3DMA on PC00 + Package() { 0x0004FFFF, 0, 0, 26 }, + // [CB0B]: CB3DMA on PC00 + // [CB0F]: CB3DMA on PC00 + Package() { 0x0004FFFF, 1, 0, 27 }, + // [CB0C]: CB3DMA on PC00 + // [CB0G]: CB3DMA on PC00 + Package() { 0x0004FFFF, 2, 0, 26 }, + // [CB0D]: CB3DMA on PC00 + // [CB0H]: CB3DMA on PC00 + Package() { 0x0004FFFF, 3, 0, 27 }, + // [IIM0]: IIOMISC on PC00 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX0]: Uncore 0 UBOX Device + Package() { 0x0008FFFF, 0, 0, 24 }, + Package() { 0x0008FFFF, 1, 0, 28 }, + Package() { 0x0008FFFF, 2, 0, 29 }, + Package() { 0x0008FFFF, 3, 0, 30 }, + // [DISP]: Display Controller + Package() { 0x000FFFFF, 0, 0, 16 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package() { 0x0010FFFF, 0, 0, 16 }, + // [IHC2]: HECI #2 + Package() { 0x0010FFFF, 1, 0, 17 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package() { 0x0010FFFF, 2, 0, 18 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package() { 0x0010FFFF, 3, 0, 19 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package() { 0x0011FFFF, 0, 0, 16 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 0, 0, 16 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package() { 0x0014FFFF, 1, 0, 17 }, + // [TERM]: Thermal Subsystem on PCH + Package() { 0x0014FFFF, 2, 0, 18 }, + // [CAMR]: Camera IO Host Controller on PCH + Package() { 0x0014FFFF, 3, 0, 19 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package() { 0x0016FFFF, 0, 0, 16 }, + // [HEC2]: HECI #2 on PCH + Package() { 0x0016FFFF, 1, 0, 17 }, + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 2, 0, 18 }, + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 3, 0, 19 }, + // [SAT1]: SATA controller 1 on PCH + Package() { 0x0017FFFF, 0, 0, 16 }, + // [NAN1]: NAND Cycle Router on PCH + Package() { 0x0018FFFF, 0, 0, 16 }, + // [RP17]: PCIE PCH Root Port #17 + Package() { 0x001BFFFF, 0, 0, 16 }, + // [RP18]: PCIE PCH Root Port #18 + Package() { 0x001BFFFF, 1, 0, 17 }, + // [RP19]: PCIE PCH Root Port #19 + Package() { 0x001BFFFF, 2, 0, 18 }, + // [RP20]: PCIE PCH Root Port #20 + Package() { 0x001BFFFF, 3, 0, 19 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package() { 0x001CFFFF, 0, 0, 16 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package() { 0x001CFFFF, 1, 0, 17 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package() { 0x001CFFFF, 2, 0, 18 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package() { 0x001CFFFF, 3, 0, 19 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package() { 0x001DFFFF, 0, 0, 16 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package() { 0x001DFFFF, 1, 0, 17 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package() { 0x001DFFFF, 2, 0, 18 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package() { 0x001DFFFF, 3, 0, 19 }, + // [UAR0]: UART #0 on PCH + Package() { 0x001EFFFF, 0, 0, 20 }, + // [UAR1]: UART #1 on PCH + Package() { 0x001EFFFF, 1, 0, 21 }, + // [SPI0]: SPI #0 on PCH + Package() { 0x001EFFFF, 2, 0, 22 }, + // [SPI1]: SPI #1 on PCH + Package() { 0x001EFFFF, 3, 0, 23 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package() { 0x001FFFFF, 0, 0, 16 }, + }) + + Name (PR01, Package() { + // [SLTH]: PCIE PCH Slot #17 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR01, Package() { + // [SLTH]: PCIE PCH Slot #17 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR02, Package() { + // [SLTI]: PCIE PCH Slot #18 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR02, Package() { + // [SLTI]: PCIE PCH Slot #18 + Package() { 0x0000FFFF, 0, 0, 17 }, + Package() { 0x0000FFFF, 1, 0, 18 }, + Package() { 0x0000FFFF, 2, 0, 19 }, + Package() { 0x0000FFFF, 3, 0, 16 }, + }) + + Name (PR03, Package() { + // [SLTJ]: PCIE PCH Slot #19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR03, Package() { + // [SLTJ]: PCIE PCH Slot #19 + Package() { 0x0000FFFF, 0, 0, 18 }, + Package() { 0x0000FFFF, 1, 0, 19 }, + Package() { 0x0000FFFF, 2, 0, 16 }, + Package() { 0x0000FFFF, 3, 0, 17 }, + }) + + Name (PR04, Package() { + // [SLTK]: PCIE PCH Slot #20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR04, Package() { + // [SLTK]: PCIE PCH Slot #20 + Package() { 0x0000FFFF, 0, 0, 19 }, + Package() { 0x0000FFFF, 1, 0, 16 }, + Package() { 0x0000FFFF, 2, 0, 17 }, + Package() { 0x0000FFFF, 3, 0, 18 }, + }) + + Name (PR05, Package() { + // [SLT1]: PCIE PCH Slot #1 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR05, Package() { + // [SLT1]: PCIE PCH Slot #1 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR06, Package() { + // [SLT2]: PCIE PCH Slot #2 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR06, Package() { + // [SLT2]: PCIE PCH Slot #2 + Package() { 0x0000FFFF, 0, 0, 17 }, + Package() { 0x0000FFFF, 1, 0, 18 }, + Package() { 0x0000FFFF, 2, 0, 19 }, + Package() { 0x0000FFFF, 3, 0, 16 }, + }) + + Name (PR07, Package() { + // [SLT3]: PCIE PCH Slot #3 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR07, Package() { + // [SLT3]: PCIE PCH Slot #3 + Package() { 0x0000FFFF, 0, 0, 18 }, + Package() { 0x0000FFFF, 1, 0, 19 }, + Package() { 0x0000FFFF, 2, 0, 16 }, + Package() { 0x0000FFFF, 3, 0, 17 }, + }) + + Name (PR08, Package() { + // [SLT4]: PCIE PCH Slot #4 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR08, Package() { + // [SLT4]: PCIE PCH Slot #4 + Package() { 0x0000FFFF, 0, 0, 19 }, + Package() { 0x0000FFFF, 1, 0, 16 }, + Package() { 0x0000FFFF, 2, 0, 17 }, + Package() { 0x0000FFFF, 3, 0, 18 }, + }) + + Name (PR09, Package() { + // [SLT5]: PCIE PCH Slot #5 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR09, Package() { + // [SLT5]: PCIE PCH Slot #5 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR0A, Package() { + // [SLT6]: PCIE PCH Slot #6 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR0A, Package() { + // [SLT6]: PCIE PCH Slot #6 + Package() { 0x0000FFFF, 0, 0, 17 }, + Package() { 0x0000FFFF, 1, 0, 18 }, + Package() { 0x0000FFFF, 2, 0, 19 }, + Package() { 0x0000FFFF, 3, 0, 16 }, + }) + + Name (PR0B, Package() { + // [SLT7]: PCIE PCH Slot #7 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR0B, Package() { + // [SLT7]: PCIE PCH Slot #7 + Package() { 0x0000FFFF, 0, 0, 18 }, + Package() { 0x0000FFFF, 1, 0, 19 }, + Package() { 0x0000FFFF, 2, 0, 16 }, + Package() { 0x0000FFFF, 3, 0, 17 }, + }) + + Name (PR0C, Package() { + // [SLT8]: PCIE PCH Slot #8 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR0C, Package() { + // [SLT8]: PCIE PCH Slot #8 + Package() { 0x0000FFFF, 0, 0, 19 }, + Package() { 0x0000FFFF, 1, 0, 16 }, + Package() { 0x0000FFFF, 2, 0, 17 }, + Package() { 0x0000FFFF, 3, 0, 18 }, + }) + + Name (PR0D, Package() { + // [SLT9]: PCIE PCH Slot #9 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR0D, Package() { + // [SLT9]: PCIE PCH Slot #9 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR0E, Package() { + // [SLTA]: PCIE PCH Slot #10 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR0E, Package() { + // [SLTA]: PCIE PCH Slot #10 + Package() { 0x0000FFFF, 0, 0, 17 }, + Package() { 0x0000FFFF, 1, 0, 18 }, + Package() { 0x0000FFFF, 2, 0, 19 }, + Package() { 0x0000FFFF, 3, 0, 16 }, + }) + + Name (PR0F, Package() { + // [SLTB]: PCIE PCH Slot #11 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR0F, Package() { + // [SLTB]: PCIE PCH Slot #11 + Package() { 0x0000FFFF, 0, 0, 18 }, + Package() { 0x0000FFFF, 1, 0, 19 }, + Package() { 0x0000FFFF, 2, 0, 16 }, + Package() { 0x0000FFFF, 3, 0, 17 }, + }) + + Name (PR10, Package() { + // [SLTC]: PCIE PCH Slot #12 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR10, Package() { + // [SLTC]: PCIE PCH Slot #12 + Package() { 0x0000FFFF, 0, 0, 19 }, + Package() { 0x0000FFFF, 1, 0, 16 }, + Package() { 0x0000FFFF, 2, 0, 17 }, + Package() { 0x0000FFFF, 3, 0, 18 }, + }) + + Name (PR11, Package() { + // [SLTD]: PCIE PCH Slot #13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR11, Package() { + // [SLTD]: PCIE PCH Slot #13 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR12, Package() { + // [SLTE]: PCIE PCH Slot #14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR12, Package() { + // [SLTE]: PCIE PCH Slot #14 + Package() { 0x0000FFFF, 0, 0, 17 }, + Package() { 0x0000FFFF, 1, 0, 18 }, + Package() { 0x0000FFFF, 2, 0, 19 }, + Package() { 0x0000FFFF, 3, 0, 16 }, + }) + + Name (PR13, Package() { + // [SLTF]: PCIE PCH Slot #15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR13, Package() { + // [SLTF]: PCIE PCH Slot #15 + Package() { 0x0000FFFF, 0, 0, 18 }, + Package() { 0x0000FFFF, 1, 0, 19 }, + Package() { 0x0000FFFF, 2, 0, 16 }, + Package() { 0x0000FFFF, 3, 0, 17 }, + }) + + Name (PR14, Package() { + // [SLTG]: PCIE PCH Slot #16 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR14, Package() { + // [SLTG]: PCIE PCH Slot #16 + Package() { 0x0000FFFF, 0, 0, 19 }, + Package() { 0x0000FFFF, 1, 0, 16 }, + Package() { 0x0000FFFF, 2, 0, 17 }, + Package() { 0x0000FFFF, 3, 0, 18 }, + }) + + Name (PR15, Package() { + // [BR1A]: PCI Express Port 1A on PC01 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR1B]: PCI Express Port 1B on PC01 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR1C]: PCI Express Port 1C on PC01 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR1D]: PCI Express Port 1D on PC01 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CHA0]: Uncore 1 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA1]: Uncore 1 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA2]: Uncore 1 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA3]: Uncore 1 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA4]: Uncore 1 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA5]: Uncore 1 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA6]: Uncore 1 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA7]: Uncore 1 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS0]: Uncore 1 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS1]: Uncore 1 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS2]: Uncore 1 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS3]: Uncore 1 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CDL0]: Uncore 1 CHASADALL Device + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [PCU0]: Uncore 1 PCUCR Devices + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [VCU0]: Uncore 1 VCUCR Device + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR15, Package() { + // [BR1A]: PCI Express Port 1A on PC01 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [BR1B]: PCI Express Port 1B on PC01 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [BR1C]: PCI Express Port 1C on PC01 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [BR1D]: PCI Express Port 1D on PC01 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [CHA0]: Uncore 1 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [CHA1]: Uncore 1 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [CHA2]: Uncore 1 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [CHA3]: Uncore 1 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [CHA4]: Uncore 1 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [CHA5]: Uncore 1 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [CHA6]: Uncore 1 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [CHA7]: Uncore 1 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + // [CMS0]: Uncore 1 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + // [CMS1]: Uncore 1 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [CMS2]: Uncore 1 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [CMS3]: Uncore 1 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + // [CDL0]: Uncore 1 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + // [PCU0]: Uncore 1 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + // [VCU0]: Uncore 1 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + Name (AH15, Package() { + // [BR1A]: PCI Express Port 1A on PC01 + Package() { 0x0000FFFF, 0, 0, 39 }, + // [BR1B]: PCI Express Port 1B on PC01 + Package() { 0x0001FFFF, 0, 0, 39 }, + // [BR1C]: PCI Express Port 1C on PC01 + Package() { 0x0002FFFF, 0, 0, 39 }, + // [BR1D]: PCI Express Port 1D on PC01 + Package() { 0x0003FFFF, 0, 0, 39 }, + // [CHA0]: Uncore 1 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 32 }, + Package() { 0x0008FFFF, 1, 0, 36 }, + Package() { 0x0008FFFF, 2, 0, 37 }, + Package() { 0x0008FFFF, 3, 0, 38 }, + // [CHA1]: Uncore 1 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 32 }, + Package() { 0x0009FFFF, 1, 0, 36 }, + Package() { 0x0009FFFF, 2, 0, 37 }, + Package() { 0x0009FFFF, 3, 0, 38 }, + // [CHA2]: Uncore 1 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 32 }, + Package() { 0x000AFFFF, 1, 0, 36 }, + Package() { 0x000AFFFF, 2, 0, 37 }, + Package() { 0x000AFFFF, 3, 0, 38 }, + // [CHA3]: Uncore 1 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 32 }, + Package() { 0x000BFFFF, 1, 0, 36 }, + Package() { 0x000BFFFF, 2, 0, 37 }, + Package() { 0x000BFFFF, 3, 0, 38 }, + // [CHA4]: Uncore 1 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 32 }, + Package() { 0x000EFFFF, 1, 0, 36 }, + Package() { 0x000EFFFF, 2, 0, 37 }, + Package() { 0x000EFFFF, 3, 0, 38 }, + // [CHA5]: Uncore 1 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 32 }, + Package() { 0x000FFFFF, 1, 0, 36 }, + Package() { 0x000FFFFF, 2, 0, 37 }, + Package() { 0x000FFFFF, 3, 0, 38 }, + // [CHA6]: Uncore 1 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 32 }, + Package() { 0x0010FFFF, 1, 0, 36 }, + Package() { 0x0010FFFF, 2, 0, 37 }, + Package() { 0x0010FFFF, 3, 0, 38 }, + // [CHA7]: Uncore 1 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 32 }, + Package() { 0x0011FFFF, 1, 0, 36 }, + Package() { 0x0011FFFF, 2, 0, 37 }, + Package() { 0x0011FFFF, 3, 0, 38 }, + // [CMS0]: Uncore 1 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 32 }, + Package() { 0x0014FFFF, 1, 0, 36 }, + Package() { 0x0014FFFF, 2, 0, 37 }, + Package() { 0x0014FFFF, 3, 0, 38 }, + // [CMS1]: Uncore 1 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 32 }, + Package() { 0x0015FFFF, 1, 0, 36 }, + Package() { 0x0015FFFF, 2, 0, 37 }, + Package() { 0x0015FFFF, 3, 0, 38 }, + // [CMS2]: Uncore 1 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 32 }, + Package() { 0x0016FFFF, 1, 0, 36 }, + Package() { 0x0016FFFF, 2, 0, 37 }, + Package() { 0x0016FFFF, 3, 0, 38 }, + // [CMS3]: Uncore 1 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 32 }, + Package() { 0x0017FFFF, 1, 0, 36 }, + Package() { 0x0017FFFF, 2, 0, 37 }, + Package() { 0x0017FFFF, 3, 0, 38 }, + // [CDL0]: Uncore 1 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 32 }, + Package() { 0x001DFFFF, 1, 0, 36 }, + Package() { 0x001DFFFF, 2, 0, 37 }, + Package() { 0x001DFFFF, 3, 0, 38 }, + // [PCU0]: Uncore 1 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 32 }, + Package() { 0x001EFFFF, 1, 0, 36 }, + Package() { 0x001EFFFF, 2, 0, 37 }, + Package() { 0x001EFFFF, 3, 0, 38 }, + // [VCU0]: Uncore 1 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 32 }, + Package() { 0x001FFFFF, 1, 0, 36 }, + Package() { 0x001FFFFF, 2, 0, 37 }, + Package() { 0x001FFFFF, 3, 0, 38 }, + }) + + Name (PR16, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PC01 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR16, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PC01 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH16, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PC01 + Package() { 0x0000FFFF, 0, 0, 32 }, + Package() { 0x0000FFFF, 1, 0, 36 }, + Package() { 0x0000FFFF, 2, 0, 37 }, + Package() { 0x0000FFFF, 3, 0, 38 }, + }) + + Name (PR17, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PC01 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR17, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PC01 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH17, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PC01 + Package() { 0x0000FFFF, 0, 0, 33 }, + Package() { 0x0000FFFF, 1, 0, 38 }, + Package() { 0x0000FFFF, 2, 0, 36 }, + Package() { 0x0000FFFF, 3, 0, 37 }, + }) + + Name (PR18, Package() { + // [SL03]: PCI Express Slot 3 on 1C on PC01 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR18, Package() { + // [SL03]: PCI Express Slot 3 on 1C on PC01 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH18, Package() { + // [SL03]: PCI Express Slot 3 on 1C on PC01 + Package() { 0x0000FFFF, 0, 0, 34 }, + Package() { 0x0000FFFF, 1, 0, 37 }, + Package() { 0x0000FFFF, 2, 0, 38 }, + Package() { 0x0000FFFF, 3, 0, 36 }, + }) + + Name (PR19, Package() { + // [SL04]: PCI Express Slot 4 on 1D on PC01 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR19, Package() { + // [SL04]: PCI Express Slot 4 on 1D on PC01 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH19, Package() { + // [SL04]: PCI Express Slot 4 on 1D on PC01 + Package() { 0x0000FFFF, 0, 0, 35 }, + Package() { 0x0000FFFF, 1, 0, 38 }, + Package() { 0x0000FFFF, 2, 0, 36 }, + Package() { 0x0000FFFF, 3, 0, 37 }, + }) + + Name (PR1A, Package() { + // [BR2A]: PCI Express Port 2A on PC02 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR2B]: PCI Express Port 2B on PC02 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR2C]: PCI Express Port 2C on PC02 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR2D]: PCI Express Port 2D on PC02 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [M2M0]: Uncore 2 M2MEM0 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2M1]: Uncore 2 M2MEM10 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM0]: Uncore 2 MCMAIN Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD0]: Uncore 2 MCDECS2 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM1]: Uncore 2 MCMAIN Device + Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD1]: Uncore 2 MCDECS12 Device + Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR1A, Package() { + // [BR2A]: PCI Express Port 2A on PC02 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [BR2B]: PCI Express Port 2B on PC02 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [BR2C]: PCI Express Port 2C on PC02 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [BR2D]: PCI Express Port 2D on PC02 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [M2M0]: Uncore 2 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [M2M1]: Uncore 2 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [MCM0]: Uncore 2 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [MCD0]: Uncore 2 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [MCM1]: Uncore 2 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + // [MCD1]: Uncore 2 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + // [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH1A, Package() { + // [BR2A]: PCI Express Port 2A on PC02 + Package() { 0x0000FFFF, 0, 0, 47 }, + // [BR2B]: PCI Express Port 2B on PC02 + Package() { 0x0001FFFF, 0, 0, 47 }, + // [BR2C]: PCI Express Port 2C on PC02 + Package() { 0x0002FFFF, 0, 0, 47 }, + // [BR2D]: PCI Express Port 2D on PC02 + Package() { 0x0003FFFF, 0, 0, 47 }, + // [M2M0]: Uncore 2 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 40 }, + Package() { 0x0008FFFF, 1, 0, 44 }, + Package() { 0x0008FFFF, 2, 0, 45 }, + Package() { 0x0008FFFF, 3, 0, 46 }, + // [M2M1]: Uncore 2 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 40 }, + Package() { 0x0009FFFF, 1, 0, 44 }, + Package() { 0x0009FFFF, 2, 0, 45 }, + Package() { 0x0009FFFF, 3, 0, 46 }, + // [MCM0]: Uncore 2 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 40 }, + Package() { 0x000AFFFF, 1, 0, 44 }, + Package() { 0x000AFFFF, 2, 0, 45 }, + Package() { 0x000AFFFF, 3, 0, 46 }, + // [MCD0]: Uncore 2 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 40 }, + Package() { 0x000BFFFF, 1, 0, 44 }, + Package() { 0x000BFFFF, 2, 0, 45 }, + Package() { 0x000BFFFF, 3, 0, 46 }, + // [MCM1]: Uncore 2 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 40 }, + Package() { 0x000CFFFF, 1, 0, 44 }, + Package() { 0x000CFFFF, 2, 0, 45 }, + Package() { 0x000CFFFF, 3, 0, 46 }, + // [MCD1]: Uncore 2 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 40 }, + Package() { 0x000DFFFF, 1, 0, 44 }, + Package() { 0x000DFFFF, 2, 0, 45 }, + Package() { 0x000DFFFF, 3, 0, 46 }, + // [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 40 }, + Package() { 0x0016FFFF, 1, 0, 44 }, + Package() { 0x0016FFFF, 2, 0, 45 }, + Package() { 0x0016FFFF, 3, 0, 46 }, + // [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 40 }, + Package() { 0x0017FFFF, 1, 0, 44 }, + Package() { 0x0017FFFF, 2, 0, 45 }, + Package() { 0x0017FFFF, 3, 0, 46 }, + }) + + Name (PR1B, Package() { + // [SL05]: PCI Express Slot 5 on 2A on PC02 + // [EPCU]: EVA PCIe Uplink + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR1B, Package() { + // [SL05]: PCI Express Slot 5 on 2A on PC02 + // [EPCU]: EVA PCIe Uplink + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH1B, Package() { + // [SL05]: PCI Express Slot 5 on 2A on PC02 + // [EPCU]: EVA PCIe Uplink + Package() { 0x0000FFFF, 0, 0, 40 }, + Package() { 0x0000FFFF, 1, 0, 44 }, + Package() { 0x0000FFFF, 2, 0, 45 }, + Package() { 0x0000FFFF, 3, 0, 46 }, + }) + + Name (PR1C, Package() { + // [VSP0]: EVA Virtual Switch Port 0 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [VSP1]: EVA Virtual Switch Port 1 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [VSP2]: EVA Virtual Switch Port 2 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [VSP3]: EVA Virtual Switch Port 3 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR1C, Package() { + // [VSP0]: EVA Virtual Switch Port 0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + // [VSP1]: EVA Virtual Switch Port 1 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [VSP2]: EVA Virtual Switch Port 2 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [VSP3]: EVA Virtual Switch Port 3 + Package() { 0x0003FFFF, 0, 0, 16 }, + }) + + Name (AH1C, Package() { + // [VSP0]: EVA Virtual Switch Port 0 + Package() { 0x0000FFFF, 0, 0, 40 }, + Package() { 0x0000FFFF, 1, 0, 44 }, + Package() { 0x0000FFFF, 2, 0, 45 }, + Package() { 0x0000FFFF, 3, 0, 46 }, + // [VSP1]: EVA Virtual Switch Port 1 + Package() { 0x0001FFFF, 0, 0, 40 }, + // [VSP2]: EVA Virtual Switch Port 2 + Package() { 0x0002FFFF, 0, 0, 40 }, + // [VSP3]: EVA Virtual Switch Port 3 + Package() { 0x0003FFFF, 0, 0, 40 }, + }) + + Name (PR1D, Package() { + // [CPM0]: EVA CPM0 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR1D, Package() { + // [CPM0]: EVA CPM0 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH1D, Package() { + // [CPM0]: EVA CPM0 + Package() { 0x0000FFFF, 0, 0, 40 }, + }) + + Name (PR1E, Package() { + // [CPM1]: EVA CPM1 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR1E, Package() { + // [CPM1]: EVA CPM1 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH1E, Package() { + // [CPM1]: EVA CPM1 + Package() { 0x0000FFFF, 0, 0, 41 }, + }) + + Name (PR1F, Package() { + // [CPM2]: EVA CPM2 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR1F, Package() { + // [CPM2]: EVA CPM2 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH1F, Package() { + // [CPM2]: EVA CPM2 + Package() { 0x0000FFFF, 0, 0, 45 }, + }) + + Name (PR20, Package() { + // [FPK0]: EVA Fort Park 0 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [FPK1]: EVA Fort Park 1 + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [FPK2]: EVA Fort Park 2 + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [FPK3]: EVA Fort Park 3 + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR20, Package() { + // [FPK0]: EVA Fort Park 0 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [FPK1]: EVA Fort Park 1 + Package() { 0x0000FFFF, 1, 0, 17 }, + // [FPK2]: EVA Fort Park 2 + Package() { 0x0000FFFF, 2, 0, 18 }, + // [FPK3]: EVA Fort Park 3 + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH20, Package() { + // [FPK0]: EVA Fort Park 0 + Package() { 0x0000FFFF, 0, 0, 46 }, + // [FPK1]: EVA Fort Park 1 + Package() { 0x0000FFFF, 1, 0, 46 }, + // [FPK2]: EVA Fort Park 2 + Package() { 0x0000FFFF, 2, 0, 46 }, + // [FPK3]: EVA Fort Park 3 + Package() { 0x0000FFFF, 3, 0, 46 }, + }) + + Name (PR21, Package() { + // [SL06]: PCI Express Slot 6 on 2B on PC02 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR21, Package() { + // [SL06]: PCI Express Slot 6 on 2B on PC02 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH21, Package() { + // [SL06]: PCI Express Slot 6 on 2B on PC02 + Package() { 0x0000FFFF, 0, 0, 41 }, + Package() { 0x0000FFFF, 1, 0, 46 }, + Package() { 0x0000FFFF, 2, 0, 44 }, + Package() { 0x0000FFFF, 3, 0, 45 }, + }) + + Name (PR22, Package() { + // [SL07]: PCI Express Slot 7 on 2C on PC02 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR22, Package() { + // [SL07]: PCI Express Slot 7 on 2C on PC02 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH22, Package() { + // [SL07]: PCI Express Slot 7 on 2C on PC02 + Package() { 0x0000FFFF, 0, 0, 42 }, + Package() { 0x0000FFFF, 1, 0, 45 }, + Package() { 0x0000FFFF, 2, 0, 46 }, + Package() { 0x0000FFFF, 3, 0, 44 }, + }) + + Name (PR23, Package() { + // [SL08]: PCI Express Slot 8 on 2D on PC02 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR23, Package() { + // [SL08]: PCI Express Slot 8 on 2D on PC02 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH23, Package() { + // [SL08]: PCI Express Slot 8 on 2D on PC02 + Package() { 0x0000FFFF, 0, 0, 43 }, + Package() { 0x0000FFFF, 1, 0, 46 }, + Package() { 0x0000FFFF, 2, 0, 44 }, + Package() { 0x0000FFFF, 3, 0, 45 }, + }) + + Name (PR24, Package() { + // [BR3A]: PCI Express Port 3A on PC03 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR3B]: PCI Express Port 3B on PC03 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR3C]: PCI Express Port 3C on PC03 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR3D]: PCI Express Port 3D on PC03 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [KTI0]: KTI0 + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI1]: KTI1 + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI2]: KTI2 + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M3K0]: M3K0 + Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2U0]: M2U0 + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2D0]: M2D0 + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M20]: M20 + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR24, Package() { + // [BR3A]: PCI Express Port 3A on PC03 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [BR3B]: PCI Express Port 3B on PC03 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [BR3C]: PCI Express Port 3C on PC03 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [BR3D]: PCI Express Port 3D on PC03 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [KTI0]: KTI0 + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [KTI1]: KTI1 + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [KTI2]: KTI2 + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [M3K0]: M3K0 + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + // [M2U0]: M2U0 + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [M2D0]: M2D0 + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [M20]: M20 + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH24, Package() { + // [BR3A]: PCI Express Port 3A on PC03 + Package() { 0x0000FFFF, 0, 0, 55 }, + // [BR3B]: PCI Express Port 3B on PC03 + Package() { 0x0001FFFF, 0, 0, 55 }, + // [BR3C]: PCI Express Port 3C on PC03 + Package() { 0x0002FFFF, 0, 0, 55 }, + // [BR3D]: PCI Express Port 3D on PC03 + Package() { 0x0003FFFF, 0, 0, 55 }, + // [KTI0]: KTI0 + Package() { 0x000EFFFF, 0, 0, 48 }, + Package() { 0x000EFFFF, 1, 0, 52 }, + Package() { 0x000EFFFF, 2, 0, 53 }, + Package() { 0x000EFFFF, 3, 0, 54 }, + // [KTI1]: KTI1 + Package() { 0x000FFFFF, 0, 0, 48 }, + Package() { 0x000FFFFF, 1, 0, 52 }, + Package() { 0x000FFFFF, 2, 0, 53 }, + Package() { 0x000FFFFF, 3, 0, 54 }, + // [KTI2]: KTI2 + Package() { 0x0010FFFF, 0, 0, 48 }, + Package() { 0x0010FFFF, 1, 0, 52 }, + Package() { 0x0010FFFF, 2, 0, 53 }, + Package() { 0x0010FFFF, 3, 0, 54 }, + // [M3K0]: M3K0 + Package() { 0x0012FFFF, 0, 0, 48 }, + Package() { 0x0012FFFF, 1, 0, 52 }, + Package() { 0x0012FFFF, 2, 0, 53 }, + Package() { 0x0012FFFF, 3, 0, 54 }, + // [M2U0]: M2U0 + Package() { 0x0015FFFF, 0, 0, 48 }, + Package() { 0x0015FFFF, 1, 0, 52 }, + Package() { 0x0015FFFF, 2, 0, 53 }, + Package() { 0x0015FFFF, 3, 0, 54 }, + // [M2D0]: M2D0 + Package() { 0x0016FFFF, 0, 0, 48 }, + Package() { 0x0016FFFF, 1, 0, 52 }, + Package() { 0x0016FFFF, 2, 0, 53 }, + Package() { 0x0016FFFF, 3, 0, 54 }, + // [M20]: M20 + Package() { 0x0017FFFF, 0, 0, 48 }, + Package() { 0x0017FFFF, 1, 0, 52 }, + Package() { 0x0017FFFF, 2, 0, 53 }, + Package() { 0x0017FFFF, 3, 0, 54 }, + }) + + Name (PR25, Package() { + // [SL09]: PCI Express Slot 9 on 3A on PC03 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR25, Package() { + // [SL09]: PCI Express Slot 9 on 3A on PC03 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH25, Package() { + // [SL09]: PCI Express Slot 9 on 3A on PC03 + Package() { 0x0000FFFF, 0, 0, 48 }, + Package() { 0x0000FFFF, 1, 0, 52 }, + Package() { 0x0000FFFF, 2, 0, 53 }, + Package() { 0x0000FFFF, 3, 0, 54 }, + }) + + Name (PR26, Package() { + // [SL0A]: PCI Express Slot 10 on 3B on PC03 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR26, Package() { + // [SL0A]: PCI Express Slot 10 on 3B on PC03 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH26, Package() { + // [SL0A]: PCI Express Slot 10 on 3B on PC03 + Package() { 0x0000FFFF, 0, 0, 49 }, + Package() { 0x0000FFFF, 1, 0, 54 }, + Package() { 0x0000FFFF, 2, 0, 52 }, + Package() { 0x0000FFFF, 3, 0, 53 }, + }) + + Name (PR27, Package() { + // [SL0B]: PCI Express Slot 11 on 3C on PC03 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR27, Package() { + // [SL0B]: PCI Express Slot 11 on 3C on PC03 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH27, Package() { + // [SL0B]: PCI Express Slot 11 on 3C on PC03 + Package() { 0x0000FFFF, 0, 0, 50 }, + Package() { 0x0000FFFF, 1, 0, 53 }, + Package() { 0x0000FFFF, 2, 0, 54 }, + Package() { 0x0000FFFF, 3, 0, 52 }, + }) + + Name (PR28, Package() { + // [SL0C]: PCI Express Slot 12 on 3D on PC03 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR28, Package() { + // [SL0C]: PCI Express Slot 12 on 3D on PC03 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH28, Package() { + // [SL0C]: PCI Express Slot 12 on 3D on PC03 + Package() { 0x0000FFFF, 0, 0, 51 }, + Package() { 0x0000FFFF, 1, 0, 54 }, + Package() { 0x0000FFFF, 2, 0, 52 }, + Package() { 0x0000FFFF, 3, 0, 53 }, + }) + + Name (PR29, Package() { + // [MCP0]: PCI Express Port 4 on PC04 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR29, Package() { + // [MCP0]: PCI Express Port 4 on PC04 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH29, Package() { + // [MCP0]: PCI Express Port 4 on PC04 + Package() { 0x0000FFFF, 0, 0, 63 }, + }) + + Name (PR2A, Package() { + // [SL0D]: PCI Express Slot 13 on 4 on PC04 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR2A, Package() { + // [SL0D]: PCI Express Slot 13 on 4 on PC04 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH2A, Package() { + // [SL0D]: PCI Express Slot 13 on 4 on PC04 + Package() { 0x0000FFFF, 0, 0, 56 }, + Package() { 0x0000FFFF, 1, 0, 60 }, + Package() { 0x0000FFFF, 2, 0, 61 }, + Package() { 0x0000FFFF, 3, 0, 62 }, + }) + + Name (PR2B, Package() { + // [MCP1]: PCI Express Port 5 on PC05 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR2B, Package() { + // [MCP1]: PCI Express Port 5 on PC05 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH2B, Package() { + // [MCP1]: PCI Express Port 5 on PC05 + Package() { 0x0000FFFF, 0, 0, 71 }, + }) + + Name (PR2C, Package() { + // [SL0E]: PCI Express Slot 14 on 5 on PC05 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR2C, Package() { + // [SL0E]: PCI Express Slot 14 on 5 on PC05 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH2C, Package() { + // [SL0E]: PCI Express Slot 14 on 5 on PC05 + Package() { 0x0000FFFF, 0, 0, 64 }, + Package() { 0x0000FFFF, 1, 0, 68 }, + Package() { 0x0000FFFF, 2, 0, 69 }, + Package() { 0x0000FFFF, 3, 0, 70 }, + }) + + Name (PR2D, Package() { + // [QRP0]: PCI Express Port 0 on PC06 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CB1B]: CB3DMA on PC06 + // [CB1F]: CB3DMA on PC06 + Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [CB1C]: CB3DMA on PC06 + // [CB1G]: CB3DMA on PC06 + Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [CB1D]: CB3DMA on PC06 + // [CB1H]: CB3DMA on PC06 + Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CB1E]: CB3DMA on PC06 + // [CB1A]: CB3DMA on PC06 + Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [IIM1]: IIOMISC on PC01 + Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UBX1]: Uncore 4 UBOX Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR2D, Package() { + // [QRP0]: PCI Express Port 0 on PC06 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [CB1B]: CB3DMA on PC06 + // [CB1F]: CB3DMA on PC06 + Package() { 0x0004FFFF, 1, 0, 17 }, + // [CB1C]: CB3DMA on PC06 + // [CB1G]: CB3DMA on PC06 + Package() { 0x0004FFFF, 2, 0, 18 }, + // [CB1D]: CB3DMA on PC06 + // [CB1H]: CB3DMA on PC06 + Package() { 0x0004FFFF, 3, 0, 19 }, + // [CB1E]: CB3DMA on PC06 + // [CB1A]: CB3DMA on PC06 + Package() { 0x0004FFFF, 0, 0, 16 }, + // [IIM1]: IIOMISC on PC01 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX1]: Uncore 4 UBOX Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + }) + + Name (AH2D, Package() { + // [QRP0]: PCI Express Port 0 on PC06 + Package() { 0x0000FFFF, 0, 0, 79 }, + // [CB1B]: CB3DMA on PC06 + // [CB1F]: CB3DMA on PC06 + Package() { 0x0004FFFF, 1, 0, 75 }, + // [CB1C]: CB3DMA on PC06 + // [CB1G]: CB3DMA on PC06 + Package() { 0x0004FFFF, 2, 0, 74 }, + // [CB1D]: CB3DMA on PC06 + // [CB1H]: CB3DMA on PC06 + Package() { 0x0004FFFF, 3, 0, 75 }, + // [CB1E]: CB3DMA on PC06 + // [CB1A]: CB3DMA on PC06 + Package() { 0x0004FFFF, 0, 0, 74 }, + // [IIM1]: IIOMISC on PC01 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX1]: Uncore 4 UBOX Device + Package() { 0x0008FFFF, 0, 0, 72 }, + Package() { 0x0008FFFF, 1, 0, 76 }, + Package() { 0x0008FFFF, 2, 0, 77 }, + Package() { 0x0008FFFF, 3, 0, 78 }, + }) + + Name (PR2E, Package() { + // [SL0F]: PCI Express Slot 15 on P0 on PC06 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR2E, Package() { + // [SL0F]: PCI Express Slot 15 on P0 on PC06 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH2E, Package() { + // [SL0F]: PCI Express Slot 15 on P0 on PC06 + Package() { 0x0000FFFF, 0, 0, 72 }, + Package() { 0x0000FFFF, 1, 0, 76 }, + Package() { 0x0000FFFF, 2, 0, 77 }, + Package() { 0x0000FFFF, 3, 0, 78 }, + }) + + Name (PR2F, Package() { + // [QR1A]: PCI Express Port 1A on PC07 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR1B]: PCI Express Port 1B on PC07 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR1C]: PCI Express Port 1C on PC07 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR1D]: PCI Express Port 1D on PC07 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CHB0]: Uncore 5 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB1]: Uncore 5 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB2]: Uncore 5 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB3]: Uncore 5 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB4]: Uncore 5 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB5]: Uncore 5 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB6]: Uncore 5 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB7]: Uncore 5 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS4]: Uncore 5 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS5]: Uncore 5 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS6]: Uncore 5 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS7]: Uncore 5 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CDL1]: Uncore 5 CHASADALL Device + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [PCU1]: Uncore 5 PCUCR Devices + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [VCU1]: Uncore 5 VCUCR Device + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR2F, Package() { + // [QR1A]: PCI Express Port 1A on PC07 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [QR1B]: PCI Express Port 1B on PC07 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [QR1C]: PCI Express Port 1C on PC07 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [QR1D]: PCI Express Port 1D on PC07 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [CHB0]: Uncore 5 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [CHB1]: Uncore 5 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [CHB2]: Uncore 5 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [CHB3]: Uncore 5 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [CHB4]: Uncore 5 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [CHB5]: Uncore 5 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [CHB6]: Uncore 5 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [CHB7]: Uncore 5 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + // [CMS4]: Uncore 5 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + // [CMS5]: Uncore 5 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [CMS6]: Uncore 5 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [CMS7]: Uncore 5 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + // [CDL1]: Uncore 5 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + // [PCU1]: Uncore 5 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + // [VCU1]: Uncore 5 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + Name (AH2F, Package() { + // [QR1A]: PCI Express Port 1A on PC07 + Package() { 0x0000FFFF, 0, 0, 87 }, + // [QR1B]: PCI Express Port 1B on PC07 + Package() { 0x0001FFFF, 0, 0, 87 }, + // [QR1C]: PCI Express Port 1C on PC07 + Package() { 0x0002FFFF, 0, 0, 87 }, + // [QR1D]: PCI Express Port 1D on PC07 + Package() { 0x0003FFFF, 0, 0, 87 }, + // [CHB0]: Uncore 5 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 80 }, + Package() { 0x0008FFFF, 1, 0, 84 }, + Package() { 0x0008FFFF, 2, 0, 85 }, + Package() { 0x0008FFFF, 3, 0, 86 }, + // [CHB1]: Uncore 5 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 80 }, + Package() { 0x0009FFFF, 1, 0, 84 }, + Package() { 0x0009FFFF, 2, 0, 85 }, + Package() { 0x0009FFFF, 3, 0, 86 }, + // [CHB2]: Uncore 5 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 80 }, + Package() { 0x000AFFFF, 1, 0, 84 }, + Package() { 0x000AFFFF, 2, 0, 85 }, + Package() { 0x000AFFFF, 3, 0, 86 }, + // [CHB3]: Uncore 5 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 80 }, + Package() { 0x000BFFFF, 1, 0, 84 }, + Package() { 0x000BFFFF, 2, 0, 85 }, + Package() { 0x000BFFFF, 3, 0, 86 }, + // [CHB4]: Uncore 5 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 80 }, + Package() { 0x000EFFFF, 1, 0, 84 }, + Package() { 0x000EFFFF, 2, 0, 85 }, + Package() { 0x000EFFFF, 3, 0, 86 }, + // [CHB5]: Uncore 5 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 80 }, + Package() { 0x000FFFFF, 1, 0, 84 }, + Package() { 0x000FFFFF, 2, 0, 85 }, + Package() { 0x000FFFFF, 3, 0, 86 }, + // [CHB6]: Uncore 5 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 80 }, + Package() { 0x0010FFFF, 1, 0, 84 }, + Package() { 0x0010FFFF, 2, 0, 85 }, + Package() { 0x0010FFFF, 3, 0, 86 }, + // [CHB7]: Uncore 5 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 80 }, + Package() { 0x0011FFFF, 1, 0, 84 }, + Package() { 0x0011FFFF, 2, 0, 85 }, + Package() { 0x0011FFFF, 3, 0, 86 }, + // [CMS4]: Uncore 5 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 80 }, + Package() { 0x0014FFFF, 1, 0, 84 }, + Package() { 0x0014FFFF, 2, 0, 85 }, + Package() { 0x0014FFFF, 3, 0, 86 }, + // [CMS5]: Uncore 5 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 80 }, + Package() { 0x0015FFFF, 1, 0, 84 }, + Package() { 0x0015FFFF, 2, 0, 85 }, + Package() { 0x0015FFFF, 3, 0, 86 }, + // [CMS6]: Uncore 5 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 80 }, + Package() { 0x0016FFFF, 1, 0, 84 }, + Package() { 0x0016FFFF, 2, 0, 85 }, + Package() { 0x0016FFFF, 3, 0, 86 }, + // [CMS7]: Uncore 5 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 80 }, + Package() { 0x0017FFFF, 1, 0, 84 }, + Package() { 0x0017FFFF, 2, 0, 85 }, + Package() { 0x0017FFFF, 3, 0, 86 }, + // [CDL1]: Uncore 5 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 80 }, + Package() { 0x001DFFFF, 1, 0, 84 }, + Package() { 0x001DFFFF, 2, 0, 85 }, + Package() { 0x001DFFFF, 3, 0, 86 }, + // [PCU1]: Uncore 5 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 80 }, + Package() { 0x001EFFFF, 1, 0, 84 }, + Package() { 0x001EFFFF, 2, 0, 85 }, + Package() { 0x001EFFFF, 3, 0, 86 }, + // [VCU1]: Uncore 5 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 80 }, + Package() { 0x001FFFFF, 1, 0, 84 }, + Package() { 0x001FFFFF, 2, 0, 85 }, + Package() { 0x001FFFFF, 3, 0, 86 }, + }) + + Name (PR30, Package() { + // [SL10]: PCI Express Slot 16 on 1A on PC07 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR30, Package() { + // [SL10]: PCI Express Slot 16 on 1A on PC07 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH30, Package() { + // [SL10]: PCI Express Slot 16 on 1A on PC07 + Package() { 0x0000FFFF, 0, 0, 80 }, + Package() { 0x0000FFFF, 1, 0, 84 }, + Package() { 0x0000FFFF, 2, 0, 85 }, + Package() { 0x0000FFFF, 3, 0, 86 }, + }) + + Name (PR31, Package() { + // [SL11]: PCI Express Slot 17 on 1B on PC07 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR31, Package() { + // [SL11]: PCI Express Slot 17 on 1B on PC07 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH31, Package() { + // [SL11]: PCI Express Slot 17 on 1B on PC07 + Package() { 0x0000FFFF, 0, 0, 81 }, + Package() { 0x0000FFFF, 1, 0, 86 }, + Package() { 0x0000FFFF, 2, 0, 84 }, + Package() { 0x0000FFFF, 3, 0, 85 }, + }) + + Name (PR32, Package() { + // [SL12]: PCI Express Slot 18 on 1C on PC07 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR32, Package() { + // [SL12]: PCI Express Slot 18 on 1C on PC07 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH32, Package() { + // [SL12]: PCI Express Slot 18 on 1C on PC07 + Package() { 0x0000FFFF, 0, 0, 82 }, + Package() { 0x0000FFFF, 1, 0, 85 }, + Package() { 0x0000FFFF, 2, 0, 86 }, + Package() { 0x0000FFFF, 3, 0, 84 }, + }) + + Name (PR33, Package() { + // [SL13]: PCI Express Slot 19 on 1D on PC07 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR33, Package() { + // [SL13]: PCI Express Slot 19 on 1D on PC07 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH33, Package() { + // [SL13]: PCI Express Slot 19 on 1D on PC07 + Package() { 0x0000FFFF, 0, 0, 83 }, + Package() { 0x0000FFFF, 1, 0, 86 }, + Package() { 0x0000FFFF, 2, 0, 84 }, + Package() { 0x0000FFFF, 3, 0, 85 }, + }) + + Name (PR34, Package() { + // [QR2A]: PCI Express Port 2A on PC08 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR2B]: PCI Express Port 2B on PC08 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR2C]: PCI Express Port 2C on PC08 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR2D]: PCI Express Port 2D on PC08 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [M2M2]: Uncore 6 M2MEM0 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2M3]: Uncore 6 M2MEM10 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM2]: Uncore 6 MCMAIN Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD2]: Uncore 6 MCDECS2 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM3]: Uncore 6 MCMAIN Device + Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD3]: Uncore 6 MCDECS12 Device + Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR34, Package() { + // [QR2A]: PCI Express Port 2A on PC08 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [QR2B]: PCI Express Port 2B on PC08 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [QR2C]: PCI Express Port 2C on PC08 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [QR2D]: PCI Express Port 2D on PC08 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [M2M2]: Uncore 6 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [M2M3]: Uncore 6 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [MCM2]: Uncore 6 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [MCD2]: Uncore 6 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [MCM3]: Uncore 6 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + // [MCD3]: Uncore 6 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + // [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH34, Package() { + // [QR2A]: PCI Express Port 2A on PC08 + Package() { 0x0000FFFF, 0, 0, 95 }, + // [QR2B]: PCI Express Port 2B on PC08 + Package() { 0x0001FFFF, 0, 0, 95 }, + // [QR2C]: PCI Express Port 2C on PC08 + Package() { 0x0002FFFF, 0, 0, 95 }, + // [QR2D]: PCI Express Port 2D on PC08 + Package() { 0x0003FFFF, 0, 0, 95 }, + // [M2M2]: Uncore 6 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 88 }, + Package() { 0x0008FFFF, 1, 0, 92 }, + Package() { 0x0008FFFF, 2, 0, 93 }, + Package() { 0x0008FFFF, 3, 0, 94 }, + // [M2M3]: Uncore 6 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 88 }, + Package() { 0x0009FFFF, 1, 0, 92 }, + Package() { 0x0009FFFF, 2, 0, 93 }, + Package() { 0x0009FFFF, 3, 0, 94 }, + // [MCM2]: Uncore 6 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 88 }, + Package() { 0x000AFFFF, 1, 0, 92 }, + Package() { 0x000AFFFF, 2, 0, 93 }, + Package() { 0x000AFFFF, 3, 0, 94 }, + // [MCD2]: Uncore 6 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 88 }, + Package() { 0x000BFFFF, 1, 0, 92 }, + Package() { 0x000BFFFF, 2, 0, 93 }, + Package() { 0x000BFFFF, 3, 0, 94 }, + // [MCM3]: Uncore 6 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 88 }, + Package() { 0x000CFFFF, 1, 0, 92 }, + Package() { 0x000CFFFF, 2, 0, 93 }, + Package() { 0x000CFFFF, 3, 0, 94 }, + // [MCD3]: Uncore 6 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 88 }, + Package() { 0x000DFFFF, 1, 0, 92 }, + Package() { 0x000DFFFF, 2, 0, 93 }, + Package() { 0x000DFFFF, 3, 0, 94 }, + // [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 88 }, + Package() { 0x0016FFFF, 1, 0, 92 }, + Package() { 0x0016FFFF, 2, 0, 93 }, + Package() { 0x0016FFFF, 3, 0, 94 }, + // [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 88 }, + Package() { 0x0017FFFF, 1, 0, 92 }, + Package() { 0x0017FFFF, 2, 0, 93 }, + Package() { 0x0017FFFF, 3, 0, 94 }, + }) + + Name (PR35, Package() { + // [SL14]: PCI Express Slot 20 on 2A on PC08 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR35, Package() { + // [SL14]: PCI Express Slot 20 on 2A on PC08 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH35, Package() { + // [SL14]: PCI Express Slot 20 on 2A on PC08 + Package() { 0x0000FFFF, 0, 0, 88 }, + Package() { 0x0000FFFF, 1, 0, 92 }, + Package() { 0x0000FFFF, 2, 0, 93 }, + Package() { 0x0000FFFF, 3, 0, 94 }, + }) + + Name (PR36, Package() { + // [SL15]: PCI Express Slot 21 on 2B on PC08 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR36, Package() { + // [SL15]: PCI Express Slot 21 on 2B on PC08 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH36, Package() { + // [SL15]: PCI Express Slot 21 on 2B on PC08 + Package() { 0x0000FFFF, 0, 0, 89 }, + Package() { 0x0000FFFF, 1, 0, 94 }, + Package() { 0x0000FFFF, 2, 0, 92 }, + Package() { 0x0000FFFF, 3, 0, 93 }, + }) + + Name (PR37, Package() { + // [SL16]: PCI Express Slot 22 on 2C on PC08 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR37, Package() { + // [SL16]: PCI Express Slot 22 on 2C on PC08 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH37, Package() { + // [SL16]: PCI Express Slot 22 on 2C on PC08 + Package() { 0x0000FFFF, 0, 0, 90 }, + Package() { 0x0000FFFF, 1, 0, 93 }, + Package() { 0x0000FFFF, 2, 0, 94 }, + Package() { 0x0000FFFF, 3, 0, 92 }, + }) + + Name (PR38, Package() { + // [SL17]: PCI Express Slot 23 on 2D on PC08 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR38, Package() { + // [SL17]: PCI Express Slot 23 on 2D on PC08 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH38, Package() { + // [SL17]: PCI Express Slot 23 on 2D on PC08 + Package() { 0x0000FFFF, 0, 0, 91 }, + Package() { 0x0000FFFF, 1, 0, 94 }, + Package() { 0x0000FFFF, 2, 0, 92 }, + Package() { 0x0000FFFF, 3, 0, 93 }, + }) + + Name (PR39, Package() { + // [QR3A]: PCI Express Port 3A on PC09 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR3B]: PCI Express Port 3B on PC09 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR3C]: PCI Express Port 3C on PC09 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR3D]: PCI Express Port 3D on PC09 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [KTI3]: Uncore 7 KTI3 + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI4]: Uncore 7 KTI4 + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI5]: Uncore 7 KTI5 + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M3K1]: Uncore 7 M3K1 + Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2U1]: Uncore 7 M2U1 + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2D1]: Uncore 7 M2D1 + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M21]: Uncore 7 M21 + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR39, Package() { + // [QR3A]: PCI Express Port 3A on PC09 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [QR3B]: PCI Express Port 3B on PC09 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [QR3C]: PCI Express Port 3C on PC09 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [QR3D]: PCI Express Port 3D on PC09 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [KTI3]: Uncore 7 KTI3 + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [KTI4]: Uncore 7 KTI4 + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [KTI5]: Uncore 7 KTI5 + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [M3K1]: Uncore 7 M3K1 + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + // [M2U1]: Uncore 7 M2U1 + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [M2D1]: Uncore 7 M2D1 + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [M21]: Uncore 7 M21 + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH39, Package() { + // [QR3A]: PCI Express Port 3A on PC09 + Package() { 0x0000FFFF, 0, 0, 103 }, + // [QR3B]: PCI Express Port 3B on PC09 + Package() { 0x0001FFFF, 0, 0, 103 }, + // [QR3C]: PCI Express Port 3C on PC09 + Package() { 0x0002FFFF, 0, 0, 103 }, + // [QR3D]: PCI Express Port 3D on PC09 + Package() { 0x0003FFFF, 0, 0, 103 }, + // [KTI3]: Uncore 7 KTI3 + Package() { 0x000EFFFF, 0, 0, 96 }, + Package() { 0x000EFFFF, 1, 0, 100 }, + Package() { 0x000EFFFF, 2, 0, 101 }, + Package() { 0x000EFFFF, 3, 0, 102 }, + // [KTI4]: Uncore 7 KTI4 + Package() { 0x000FFFFF, 0, 0, 96 }, + Package() { 0x000FFFFF, 1, 0, 100 }, + Package() { 0x000FFFFF, 2, 0, 101 }, + Package() { 0x000FFFFF, 3, 0, 102 }, + // [KTI5]: Uncore 7 KTI5 + Package() { 0x0010FFFF, 0, 0, 96 }, + Package() { 0x0010FFFF, 1, 0, 100 }, + Package() { 0x0010FFFF, 2, 0, 101 }, + Package() { 0x0010FFFF, 3, 0, 102 }, + // [M3K1]: Uncore 7 M3K1 + Package() { 0x0012FFFF, 0, 0, 96 }, + Package() { 0x0012FFFF, 1, 0, 100 }, + Package() { 0x0012FFFF, 2, 0, 101 }, + Package() { 0x0012FFFF, 3, 0, 102 }, + // [M2U1]: Uncore 7 M2U1 + Package() { 0x0015FFFF, 0, 0, 96 }, + Package() { 0x0015FFFF, 1, 0, 100 }, + Package() { 0x0015FFFF, 2, 0, 101 }, + Package() { 0x0015FFFF, 3, 0, 102 }, + // [M2D1]: Uncore 7 M2D1 + Package() { 0x0016FFFF, 0, 0, 96 }, + Package() { 0x0016FFFF, 1, 0, 100 }, + Package() { 0x0016FFFF, 2, 0, 101 }, + Package() { 0x0016FFFF, 3, 0, 102 }, + // [M21]: Uncore 7 M21 + Package() { 0x0017FFFF, 0, 0, 96 }, + Package() { 0x0017FFFF, 1, 0, 100 }, + Package() { 0x0017FFFF, 2, 0, 101 }, + Package() { 0x0017FFFF, 3, 0, 102 }, + }) + + Name (PR3A, Package() { + // [SL18]: PCI Express Slot 24 on 3A on PC09 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR3A, Package() { + // [SL18]: PCI Express Slot 24 on 3A on PC09 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH3A, Package() { + // [SL18]: PCI Express Slot 24 on 3A on PC09 + Package() { 0x0000FFFF, 0, 0, 96 }, + Package() { 0x0000FFFF, 1, 0, 100 }, + Package() { 0x0000FFFF, 2, 0, 101 }, + Package() { 0x0000FFFF, 3, 0, 102 }, + }) + + Name (PR3B, Package() { + // [SL19]: PCI Express Slot 25 on 3B on PC09 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR3B, Package() { + // [SL19]: PCI Express Slot 25 on 3B on PC09 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH3B, Package() { + // [SL19]: PCI Express Slot 25 on 3B on PC09 + Package() { 0x0000FFFF, 0, 0, 97 }, + Package() { 0x0000FFFF, 1, 0, 102 }, + Package() { 0x0000FFFF, 2, 0, 100 }, + Package() { 0x0000FFFF, 3, 0, 101 }, + }) + + Name (PR3C, Package() { + // [SL1A]: PCI Express Slot 26 on 3C on PC09 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR3C, Package() { + // [SL1A]: PCI Express Slot 26 on 3C on PC09 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH3C, Package() { + // [SL1A]: PCI Express Slot 26 on 3C on PC09 + Package() { 0x0000FFFF, 0, 0, 98 }, + Package() { 0x0000FFFF, 1, 0, 101 }, + Package() { 0x0000FFFF, 2, 0, 102 }, + Package() { 0x0000FFFF, 3, 0, 100 }, + }) + + Name (PR3D, Package() { + // [SL1B]: PCI Express Slot 27 on 3D on PC09 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR3D, Package() { + // [SL1B]: PCI Express Slot 27 on 3D on PC09 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH3D, Package() { + // [SL1B]: PCI Express Slot 27 on 3D on PC09 + Package() { 0x0000FFFF, 0, 0, 99 }, + Package() { 0x0000FFFF, 1, 0, 102 }, + Package() { 0x0000FFFF, 2, 0, 100 }, + Package() { 0x0000FFFF, 3, 0, 101 }, + }) + + Name (PR3E, Package() { + // [MCP2]: PCI Express Port 13 on PC10 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR3E, Package() { + // [MCP2]: PCI Express Port 13 on PC10 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH3E, Package() { + // [MCP2]: PCI Express Port 13 on PC10 + Package() { 0x0000FFFF, 0, 0, 111 }, + }) + + Name (PR3F, Package() { + // [SL1C]: PCI Express Slot 28 on 4 on PC10 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR3F, Package() { + // [SL1C]: PCI Express Slot 28 on 4 on PC10 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH3F, Package() { + // [SL1C]: PCI Express Slot 28 on 4 on PC10 + Package() { 0x0000FFFF, 0, 0, 104 }, + Package() { 0x0000FFFF, 1, 0, 108 }, + Package() { 0x0000FFFF, 2, 0, 109 }, + Package() { 0x0000FFFF, 3, 0, 110 }, + }) + + Name (PR40, Package() { + // [MCP3]: PCI Express Port 14 on PC11 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR40, Package() { + // [MCP3]: PCI Express Port 14 on PC11 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH40, Package() { + // [MCP3]: PCI Express Port 14 on PC11 + Package() { 0x0000FFFF, 0, 0, 119 }, + }) + + Name (PR41, Package() { + // [SL1D]: PCI Express Slot 29 on 5 on PC11 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR41, Package() { + // [SL1D]: PCI Express Slot 29 on 5 on PC11 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH41, Package() { + // [SL1D]: PCI Express Slot 29 on 5 on PC11 + Package() { 0x0000FFFF, 0, 0, 112 }, + Package() { 0x0000FFFF, 1, 0, 116 }, + Package() { 0x0000FFFF, 2, 0, 117 }, + Package() { 0x0000FFFF, 3, 0, 118 }, + }) + + Name (PR42, Package() { + // [RRP0]: PCI Express Port 0 on PC12 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CB2B]: CB3DMA on PC12 + // [CB2F]: CB3DMA on PC12 + Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [CB2C]: CB3DMA on PC12 + // [CB2G]: CB3DMA on PC12 + Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [CB2D]: CB3DMA on PC12 + // [CB2H]: CB3DMA on PC12 + Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CB2E]: CB3DMA on PC12 + // [CB2A]: CB3DMA on PC12 + Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [IIM2]: IIOMISC on PC02 + Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UBX2]: Uncore 8 UBOX Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR42, Package() { + // [RRP0]: PCI Express Port 0 on PC12 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [CB2B]: CB3DMA on PC12 + // [CB2F]: CB3DMA on PC12 + Package() { 0x0004FFFF, 1, 0, 17 }, + // [CB2C]: CB3DMA on PC12 + // [CB2G]: CB3DMA on PC12 + Package() { 0x0004FFFF, 2, 0, 18 }, + // [CB2D]: CB3DMA on PC12 + // [CB2H]: CB3DMA on PC12 + Package() { 0x0004FFFF, 3, 0, 19 }, + // [CB2E]: CB3DMA on PC12 + // [CB2A]: CB3DMA on PC12 + Package() { 0x0004FFFF, 0, 0, 16 }, + // [IIM2]: IIOMISC on PC02 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX2]: Uncore 8 UBOX Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + }) + + Name (AH42, Package() { + // [RRP0]: PCI Express Port 0 on PC12 + Package() { 0x0000FFFF, 0, 0, 127 }, + // [CB2B]: CB3DMA on PC12 + // [CB2F]: CB3DMA on PC12 + Package() { 0x0004FFFF, 1, 0, 123 }, + // [CB2C]: CB3DMA on PC12 + // [CB2G]: CB3DMA on PC12 + Package() { 0x0004FFFF, 2, 0, 122 }, + // [CB2D]: CB3DMA on PC12 + // [CB2H]: CB3DMA on PC12 + Package() { 0x0004FFFF, 3, 0, 123 }, + // [CB2E]: CB3DMA on PC12 + // [CB2A]: CB3DMA on PC12 + Package() { 0x0004FFFF, 0, 0, 122 }, + // [IIM2]: IIOMISC on PC02 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX2]: Uncore 8 UBOX Device + Package() { 0x0008FFFF, 0, 0, 120 }, + Package() { 0x0008FFFF, 1, 0, 124 }, + Package() { 0x0008FFFF, 2, 0, 125 }, + Package() { 0x0008FFFF, 3, 0, 126 }, + }) + + Name (PR43, Package() { + // [SL1E]: PCI Express Slot 30 on P0 on PC12 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR43, Package() { + // [SL1E]: PCI Express Slot 30 on P0 on PC12 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH43, Package() { + // [SL1E]: PCI Express Slot 30 on P0 on PC12 + Package() { 0x0000FFFF, 0, 0, 120 }, + Package() { 0x0000FFFF, 1, 0, 124 }, + Package() { 0x0000FFFF, 2, 0, 125 }, + Package() { 0x0000FFFF, 3, 0, 126 }, + }) + + Name (PR44, Package() { + // [RR1A]: PCI Express Port 1A on PC13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR1B]: PCI Express Port 1B on PC13 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR1C]: PCI Express Port 1C on PC13 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR1D]: PCI Express Port 1D on PC13 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CHC0]: Uncore 9 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC1]: Uncore 9 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC2]: Uncore 9 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC3]: Uncore 9 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC4]: Uncore 9 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC5]: Uncore 9 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC6]: Uncore 9 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC7]: Uncore 9 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS8]: Uncore 9 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS9]: Uncore 9 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CDL2]: Uncore 9 CHASADALL Device + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [PCU2]: Uncore 9 PCUCR Devices + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [VCU2]: Uncore 9 VCUCR Device + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR44, Package() { + // [RR1A]: PCI Express Port 1A on PC13 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [RR1B]: PCI Express Port 1B on PC13 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [RR1C]: PCI Express Port 1C on PC13 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [RR1D]: PCI Express Port 1D on PC13 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [CHC0]: Uncore 9 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [CHC1]: Uncore 9 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [CHC2]: Uncore 9 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [CHC3]: Uncore 9 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [CHC4]: Uncore 9 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [CHC5]: Uncore 9 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [CHC6]: Uncore 9 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [CHC7]: Uncore 9 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + // [CMS8]: Uncore 9 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + // [CMS9]: Uncore 9 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [CDL2]: Uncore 9 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + // [PCU2]: Uncore 9 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + // [VCU2]: Uncore 9 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + Name (AH44, Package() { + // [RR1A]: PCI Express Port 1A on PC13 + Package() { 0x0000FFFF, 0, 0, 135 }, + // [RR1B]: PCI Express Port 1B on PC13 + Package() { 0x0001FFFF, 0, 0, 135 }, + // [RR1C]: PCI Express Port 1C on PC13 + Package() { 0x0002FFFF, 0, 0, 135 }, + // [RR1D]: PCI Express Port 1D on PC13 + Package() { 0x0003FFFF, 0, 0, 135 }, + // [CHC0]: Uncore 9 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 128 }, + Package() { 0x0008FFFF, 1, 0, 132 }, + Package() { 0x0008FFFF, 2, 0, 133 }, + Package() { 0x0008FFFF, 3, 0, 134 }, + // [CHC1]: Uncore 9 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 128 }, + Package() { 0x0009FFFF, 1, 0, 132 }, + Package() { 0x0009FFFF, 2, 0, 133 }, + Package() { 0x0009FFFF, 3, 0, 134 }, + // [CHC2]: Uncore 9 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 128 }, + Package() { 0x000AFFFF, 1, 0, 132 }, + Package() { 0x000AFFFF, 2, 0, 133 }, + Package() { 0x000AFFFF, 3, 0, 134 }, + // [CHC3]: Uncore 9 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 128 }, + Package() { 0x000BFFFF, 1, 0, 132 }, + Package() { 0x000BFFFF, 2, 0, 133 }, + Package() { 0x000BFFFF, 3, 0, 134 }, + // [CHC4]: Uncore 9 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 128 }, + Package() { 0x000EFFFF, 1, 0, 132 }, + Package() { 0x000EFFFF, 2, 0, 133 }, + Package() { 0x000EFFFF, 3, 0, 134 }, + // [CHC5]: Uncore 9 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 128 }, + Package() { 0x000FFFFF, 1, 0, 132 }, + Package() { 0x000FFFFF, 2, 0, 133 }, + Package() { 0x000FFFFF, 3, 0, 134 }, + // [CHC6]: Uncore 9 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 128 }, + Package() { 0x0010FFFF, 1, 0, 132 }, + Package() { 0x0010FFFF, 2, 0, 133 }, + Package() { 0x0010FFFF, 3, 0, 134 }, + // [CHC7]: Uncore 9 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 128 }, + Package() { 0x0011FFFF, 1, 0, 132 }, + Package() { 0x0011FFFF, 2, 0, 133 }, + Package() { 0x0011FFFF, 3, 0, 134 }, + // [CMS8]: Uncore 9 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 128 }, + Package() { 0x0014FFFF, 1, 0, 132 }, + Package() { 0x0014FFFF, 2, 0, 133 }, + Package() { 0x0014FFFF, 3, 0, 134 }, + // [CMS9]: Uncore 9 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 128 }, + Package() { 0x0015FFFF, 1, 0, 132 }, + Package() { 0x0015FFFF, 2, 0, 133 }, + Package() { 0x0015FFFF, 3, 0, 134 }, + // [CDL2]: Uncore 9 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 128 }, + Package() { 0x001DFFFF, 1, 0, 132 }, + Package() { 0x001DFFFF, 2, 0, 133 }, + Package() { 0x001DFFFF, 3, 0, 134 }, + // [PCU2]: Uncore 9 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 128 }, + Package() { 0x001EFFFF, 1, 0, 132 }, + Package() { 0x001EFFFF, 2, 0, 133 }, + Package() { 0x001EFFFF, 3, 0, 134 }, + // [VCU2]: Uncore 9 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 128 }, + Package() { 0x001FFFFF, 1, 0, 132 }, + Package() { 0x001FFFFF, 2, 0, 133 }, + Package() { 0x001FFFFF, 3, 0, 134 }, + }) + + Name (PR45, Package() { + // [SL1F]: PCI Express Slot 31 on 1A on PC13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR45, Package() { + // [SL1F]: PCI Express Slot 31 on 1A on PC13 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH45, Package() { + // [SL1F]: PCI Express Slot 31 on 1A on PC13 + Package() { 0x0000FFFF, 0, 0, 128 }, + Package() { 0x0000FFFF, 1, 0, 132 }, + Package() { 0x0000FFFF, 2, 0, 133 }, + Package() { 0x0000FFFF, 3, 0, 134 }, + }) + + Name (PR46, Package() { + // [SL20]: PCI Express Slot 32 on 1B on PC13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR46, Package() { + // [SL20]: PCI Express Slot 32 on 1B on PC13 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH46, Package() { + // [SL20]: PCI Express Slot 32 on 1B on PC13 + Package() { 0x0000FFFF, 0, 0, 129 }, + Package() { 0x0000FFFF, 1, 0, 134 }, + Package() { 0x0000FFFF, 2, 0, 132 }, + Package() { 0x0000FFFF, 3, 0, 133 }, + }) + + Name (PR47, Package() { + // [SL21]: PCI Express Slot 33 on 1C on PC13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR47, Package() { + // [SL21]: PCI Express Slot 33 on 1C on PC13 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH47, Package() { + // [SL21]: PCI Express Slot 33 on 1C on PC13 + Package() { 0x0000FFFF, 0, 0, 130 }, + Package() { 0x0000FFFF, 1, 0, 133 }, + Package() { 0x0000FFFF, 2, 0, 134 }, + Package() { 0x0000FFFF, 3, 0, 132 }, + }) + + Name (PR48, Package() { + // [SL22]: PCI Express Slot 34 on 1D on PC13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR48, Package() { + // [SL22]: PCI Express Slot 34 on 1D on PC13 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH48, Package() { + // [SL22]: PCI Express Slot 34 on 1D on PC13 + Package() { 0x0000FFFF, 0, 0, 131 }, + Package() { 0x0000FFFF, 1, 0, 134 }, + Package() { 0x0000FFFF, 2, 0, 132 }, + Package() { 0x0000FFFF, 3, 0, 133 }, + }) + + Name (PR49, Package() { + // [RR2A]: PCI Express Port 2A on PC14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR2B]: PCI Express Port 2B on PC14 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR2C]: PCI Express Port 2C on PC14 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR2D]: PCI Express Port 2D on PC14 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [M2M4]: Uncore 10 M2MEM0 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2M5]: Uncore 10 M2MEM10 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM4]: Uncore 10 MCMAIN Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD4]: Uncore 10 MCDECS2 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM5]: Uncore 10 MCMAIN Device + Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD5]: Uncore 10 MCDECS12 Device + Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR49, Package() { + // [RR2A]: PCI Express Port 2A on PC14 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [RR2B]: PCI Express Port 2B on PC14 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [RR2C]: PCI Express Port 2C on PC14 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [RR2D]: PCI Express Port 2D on PC14 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [M2M4]: Uncore 10 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [M2M5]: Uncore 10 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [MCM4]: Uncore 10 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [MCD4]: Uncore 10 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [MCM5]: Uncore 10 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + // [MCD5]: Uncore 10 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + // [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH49, Package() { + // [RR2A]: PCI Express Port 2A on PC14 + Package() { 0x0000FFFF, 0, 0, 143 }, + // [RR2B]: PCI Express Port 2B on PC14 + Package() { 0x0001FFFF, 0, 0, 143 }, + // [RR2C]: PCI Express Port 2C on PC14 + Package() { 0x0002FFFF, 0, 0, 143 }, + // [RR2D]: PCI Express Port 2D on PC14 + Package() { 0x0003FFFF, 0, 0, 143 }, + // [M2M4]: Uncore 10 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 136 }, + Package() { 0x0008FFFF, 1, 0, 140 }, + Package() { 0x0008FFFF, 2, 0, 141 }, + Package() { 0x0008FFFF, 3, 0, 142 }, + // [M2M5]: Uncore 10 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 136 }, + Package() { 0x0009FFFF, 1, 0, 140 }, + Package() { 0x0009FFFF, 2, 0, 141 }, + Package() { 0x0009FFFF, 3, 0, 142 }, + // [MCM4]: Uncore 10 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 136 }, + Package() { 0x000AFFFF, 1, 0, 140 }, + Package() { 0x000AFFFF, 2, 0, 141 }, + Package() { 0x000AFFFF, 3, 0, 142 }, + // [MCD4]: Uncore 10 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 136 }, + Package() { 0x000BFFFF, 1, 0, 140 }, + Package() { 0x000BFFFF, 2, 0, 141 }, + Package() { 0x000BFFFF, 3, 0, 142 }, + // [MCM5]: Uncore 10 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 136 }, + Package() { 0x000CFFFF, 1, 0, 140 }, + Package() { 0x000CFFFF, 2, 0, 141 }, + Package() { 0x000CFFFF, 3, 0, 142 }, + // [MCD5]: Uncore 10 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 136 }, + Package() { 0x000DFFFF, 1, 0, 140 }, + Package() { 0x000DFFFF, 2, 0, 141 }, + Package() { 0x000DFFFF, 3, 0, 142 }, + // [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 136 }, + Package() { 0x0016FFFF, 1, 0, 140 }, + Package() { 0x0016FFFF, 2, 0, 141 }, + Package() { 0x0016FFFF, 3, 0, 142 }, + // [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 136 }, + Package() { 0x0017FFFF, 1, 0, 140 }, + Package() { 0x0017FFFF, 2, 0, 141 }, + Package() { 0x0017FFFF, 3, 0, 142 }, + }) + + Name (PR4A, Package() { + // [SL23]: PCI Express Slot 35 on 2A on PC14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4A, Package() { + // [SL23]: PCI Express Slot 35 on 2A on PC14 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH4A, Package() { + // [SL23]: PCI Express Slot 35 on 2A on PC14 + Package() { 0x0000FFFF, 0, 0, 136 }, + Package() { 0x0000FFFF, 1, 0, 140 }, + Package() { 0x0000FFFF, 2, 0, 141 }, + Package() { 0x0000FFFF, 3, 0, 142 }, + }) + + Name (PR4B, Package() { + // [SL24]: PCI Express Slot 36 on 2B on PC14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4B, Package() { + // [SL24]: PCI Express Slot 36 on 2B on PC14 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH4B, Package() { + // [SL24]: PCI Express Slot 36 on 2B on PC14 + Package() { 0x0000FFFF, 0, 0, 137 }, + Package() { 0x0000FFFF, 1, 0, 142 }, + Package() { 0x0000FFFF, 2, 0, 140 }, + Package() { 0x0000FFFF, 3, 0, 141 }, + }) + + Name (PR4C, Package() { + // [SL25]: PCI Express Slot 37 on 2C on PC14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4C, Package() { + // [SL25]: PCI Express Slot 37 on 2C on PC14 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH4C, Package() { + // [SL25]: PCI Express Slot 37 on 2C on PC14 + Package() { 0x0000FFFF, 0, 0, 138 }, + Package() { 0x0000FFFF, 1, 0, 141 }, + Package() { 0x0000FFFF, 2, 0, 142 }, + Package() { 0x0000FFFF, 3, 0, 140 }, + }) + + Name (PR4D, Package() { + // [SL26]: PCI Express Slot 38 on 2D on PC14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4D, Package() { + // [SL26]: PCI Express Slot 38 on 2D on PC14 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH4D, Package() { + // [SL26]: PCI Express Slot 38 on 2D on PC14 + Package() { 0x0000FFFF, 0, 0, 139 }, + Package() { 0x0000FFFF, 1, 0, 142 }, + Package() { 0x0000FFFF, 2, 0, 140 }, + Package() { 0x0000FFFF, 3, 0, 141 }, + }) + + Name (PR4E, Package() { + // [RR3A]: PCI Express Port 3A on PC15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR3B]: PCI Express Port 3B on PC15 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR3C]: PCI Express Port 3C on PC15 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR3D]: PCI Express Port 3D on PC15 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [KTI6]: Uncore 11 KTI6 + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI7]: Uncore 11 KTI7 + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI8]: Uncore 11 KTI8 + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M3K2]: Uncore 11 M3K2 + Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2U2]: Uncore 11 M2U2 + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2D2]: Uncore 11 M2D2 + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M22]: Uncore 11 M22 + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4E, Package() { + // [RR3A]: PCI Express Port 3A on PC15 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [RR3B]: PCI Express Port 3B on PC15 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [RR3C]: PCI Express Port 3C on PC15 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [RR3D]: PCI Express Port 3D on PC15 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [KTI6]: Uncore 11 KTI6 + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [KTI7]: Uncore 11 KTI7 + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [KTI8]: Uncore 11 KTI8 + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [M3K2]: Uncore 11 M3K2 + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + // [M2U2]: Uncore 11 M2U2 + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [M2D2]: Uncore 11 M2D2 + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [M22]: Uncore 11 M22 + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH4E, Package() { + // [RR3A]: PCI Express Port 3A on PC15 + Package() { 0x0000FFFF, 0, 0, 151 }, + // [RR3B]: PCI Express Port 3B on PC15 + Package() { 0x0001FFFF, 0, 0, 151 }, + // [RR3C]: PCI Express Port 3C on PC15 + Package() { 0x0002FFFF, 0, 0, 151 }, + // [RR3D]: PCI Express Port 3D on PC15 + Package() { 0x0003FFFF, 0, 0, 151 }, + // [KTI6]: Uncore 11 KTI6 + Package() { 0x000EFFFF, 0, 0, 144 }, + Package() { 0x000EFFFF, 1, 0, 148 }, + Package() { 0x000EFFFF, 2, 0, 149 }, + Package() { 0x000EFFFF, 3, 0, 150 }, + // [KTI7]: Uncore 11 KTI7 + Package() { 0x000FFFFF, 0, 0, 144 }, + Package() { 0x000FFFFF, 1, 0, 148 }, + Package() { 0x000FFFFF, 2, 0, 149 }, + Package() { 0x000FFFFF, 3, 0, 150 }, + // [KTI8]: Uncore 11 KTI8 + Package() { 0x0010FFFF, 0, 0, 144 }, + Package() { 0x0010FFFF, 1, 0, 148 }, + Package() { 0x0010FFFF, 2, 0, 149 }, + Package() { 0x0010FFFF, 3, 0, 150 }, + // [M3K2]: Uncore 11 M3K2 + Package() { 0x0012FFFF, 0, 0, 144 }, + Package() { 0x0012FFFF, 1, 0, 148 }, + Package() { 0x0012FFFF, 2, 0, 149 }, + Package() { 0x0012FFFF, 3, 0, 150 }, + // [M2U2]: Uncore 11 M2U2 + Package() { 0x0015FFFF, 0, 0, 144 }, + Package() { 0x0015FFFF, 1, 0, 148 }, + Package() { 0x0015FFFF, 2, 0, 149 }, + Package() { 0x0015FFFF, 3, 0, 150 }, + // [M2D2]: Uncore 11 M2D2 + Package() { 0x0016FFFF, 0, 0, 144 }, + Package() { 0x0016FFFF, 1, 0, 148 }, + Package() { 0x0016FFFF, 2, 0, 149 }, + Package() { 0x0016FFFF, 3, 0, 150 }, + // [M22]: Uncore 11 M22 + Package() { 0x0017FFFF, 0, 0, 144 }, + Package() { 0x0017FFFF, 1, 0, 148 }, + Package() { 0x0017FFFF, 2, 0, 149 }, + Package() { 0x0017FFFF, 3, 0, 150 }, + }) + + Name (PR4F, Package() { + // [SL27]: PCI Express Slot 39 on 3A on PC15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4F, Package() { + // [SL27]: PCI Express Slot 39 on 3A on PC15 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH4F, Package() { + // [SL27]: PCI Express Slot 39 on 3A on PC15 + Package() { 0x0000FFFF, 0, 0, 144 }, + Package() { 0x0000FFFF, 1, 0, 148 }, + Package() { 0x0000FFFF, 2, 0, 149 }, + Package() { 0x0000FFFF, 3, 0, 150 }, + }) + + Name (PR50, Package() { + // [SL28]: PCI Express Slot 40 on 3B on PC15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR50, Package() { + // [SL28]: PCI Express Slot 40 on 3B on PC15 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH50, Package() { + // [SL28]: PCI Express Slot 40 on 3B on PC15 + Package() { 0x0000FFFF, 0, 0, 145 }, + Package() { 0x0000FFFF, 1, 0, 150 }, + Package() { 0x0000FFFF, 2, 0, 148 }, + Package() { 0x0000FFFF, 3, 0, 149 }, + }) + + Name (PR51, Package() { + // [SL29]: PCI Express Slot 41 on 3C on PC15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR51, Package() { + // [SL29]: PCI Express Slot 41 on 3C on PC15 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH51, Package() { + // [SL29]: PCI Express Slot 41 on 3C on PC15 + Package() { 0x0000FFFF, 0, 0, 146 }, + Package() { 0x0000FFFF, 1, 0, 149 }, + Package() { 0x0000FFFF, 2, 0, 150 }, + Package() { 0x0000FFFF, 3, 0, 148 }, + }) + + Name (PR52, Package() { + // [SL2A]: PCI Express Slot 42 on 3D on PC15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR52, Package() { + // [SL2A]: PCI Express Slot 42 on 3D on PC15 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH52, Package() { + // [SL2A]: PCI Express Slot 42 on 3D on PC15 + Package() { 0x0000FFFF, 0, 0, 147 }, + Package() { 0x0000FFFF, 1, 0, 150 }, + Package() { 0x0000FFFF, 2, 0, 148 }, + Package() { 0x0000FFFF, 3, 0, 149 }, + }) + + Name (PR53, Package() { + // [MCP4]: PCI Express Port 4 on PC16 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR53, Package() { + // [MCP4]: PCI Express Port 4 on PC16 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH53, Package() { + // [MCP4]: PCI Express Port 4 on PC16 + Package() { 0x0000FFFF, 0, 0, 159 }, + }) + + Name (PR54, Package() { + // [SL2B]: PCI Express Slot 43 on 4 on PC16 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR54, Package() { + // [SL2B]: PCI Express Slot 43 on 4 on PC16 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH54, Package() { + // [SL2B]: PCI Express Slot 43 on 4 on PC16 + Package() { 0x0000FFFF, 0, 0, 152 }, + Package() { 0x0000FFFF, 1, 0, 156 }, + Package() { 0x0000FFFF, 2, 0, 157 }, + Package() { 0x0000FFFF, 3, 0, 158 }, + }) + + Name (PR55, Package() { + // [MCP5]: PCI Express Port 5 on PC17 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR55, Package() { + // [MCP5]: PCI Express Port 5 on PC17 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH55, Package() { + // [MCP5]: PCI Express Port 5 on PC17 + Package() { 0x0000FFFF, 0, 0, 167 }, + }) + + Name (PR56, Package() { + // [SL2C]: PCI Express Slot 44 on 4 on PC17 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR56, Package() { + // [SL2C]: PCI Express Slot 44 on 4 on PC17 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH56, Package() { + // [SL2C]: PCI Express Slot 44 on 4 on PC17 + Package() { 0x0000FFFF, 0, 0, 160 }, + Package() { 0x0000FFFF, 1, 0, 164 }, + Package() { 0x0000FFFF, 2, 0, 165 }, + Package() { 0x0000FFFF, 3, 0, 166 }, + }) + + Name (PR57, Package() { + // [SRP0]: PCI Express Port 0 on PC18 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CB3B]: CB3DMA on PC18 + // [CB3F]: CB3DMA on PC18 + Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [CB3C]: CB3DMA on PC18 + // [CB3G]: CB3DMA on PC18 + Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [CB3D]: CB3DMA on PC18 + // [CB3H]: CB3DMA on PC18 + Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CB3E]: CB3DMA on PC18 + // [CB3A]: CB3DMA on PC18 + Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [IIM3]: IIOMISC on PC03 + Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UBX3]: Uncore 12 UBOX Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR57, Package() { + // [SRP0]: PCI Express Port 0 on PC18 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [CB3B]: CB3DMA on PC18 + // [CB3F]: CB3DMA on PC18 + Package() { 0x0004FFFF, 1, 0, 17 }, + // [CB3C]: CB3DMA on PC18 + // [CB3G]: CB3DMA on PC18 + Package() { 0x0004FFFF, 2, 0, 18 }, + // [CB3D]: CB3DMA on PC18 + // [CB3H]: CB3DMA on PC18 + Package() { 0x0004FFFF, 3, 0, 19 }, + // [CB3E]: CB3DMA on PC18 + // [CB3A]: CB3DMA on PC18 + Package() { 0x0004FFFF, 0, 0, 16 }, + // [IIM3]: IIOMISC on PC03 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX3]: Uncore 12 UBOX Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + }) + + Name (AH57, Package() { + // [SRP0]: PCI Express Port 0 on PC18 + Package() { 0x0000FFFF, 0, 0, 175 }, + // [CB3B]: CB3DMA on PC18 + // [CB3F]: CB3DMA on PC18 + Package() { 0x0004FFFF, 1, 0, 171 }, + // [CB3C]: CB3DMA on PC18 + // [CB3G]: CB3DMA on PC18 + Package() { 0x0004FFFF, 2, 0, 170 }, + // [CB3D]: CB3DMA on PC18 + // [CB3H]: CB3DMA on PC18 + Package() { 0x0004FFFF, 3, 0, 171 }, + // [CB3E]: CB3DMA on PC18 + // [CB3A]: CB3DMA on PC18 + Package() { 0x0004FFFF, 0, 0, 170 }, + // [IIM3]: IIOMISC on PC03 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX3]: Uncore 12 UBOX Device + Package() { 0x0008FFFF, 0, 0, 168 }, + Package() { 0x0008FFFF, 1, 0, 172 }, + Package() { 0x0008FFFF, 2, 0, 173 }, + Package() { 0x0008FFFF, 3, 0, 174 }, + }) + + Name (PR58, Package() { + // [SL2D]: PCI Express Slot 45 on P0 on PC18 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR58, Package() { + // [SL2D]: PCI Express Slot 45 on P0 on PC18 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH58, Package() { + // [SL2D]: PCI Express Slot 45 on P0 on PC18 + Package() { 0x0000FFFF, 0, 0, 168 }, + Package() { 0x0000FFFF, 1, 0, 172 }, + Package() { 0x0000FFFF, 2, 0, 173 }, + Package() { 0x0000FFFF, 3, 0, 174 }, + }) + + Name (PR59, Package() { + // [SR1A]: PCI Express Port 1A on PC19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR1B]: PCI Express Port 1B on PC19 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR1C]: PCI Express Port 1C on PC19 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR1D]: PCI Express Port 1D on PC19 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CHD0]: Uncore 13 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD1]: Uncore 13 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD2]: Uncore 13 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD3]: Uncore 13 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD4]: Uncore 13 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD5]: Uncore 13 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD6]: Uncore 13 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD7]: Uncore 13 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CM12]: Uncore 13 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CM13]: Uncore 13 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CM14]: Uncore 13 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CM15]: Uncore 13 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CDL3]: Uncore 13 CHASADALL Device + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [PCU3]: Uncore 13 PCUCR Devices + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [VCU3]: Uncore 13 VCUCR Device + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR59, Package() { + // [SR1A]: PCI Express Port 1A on PC19 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [SR1B]: PCI Express Port 1B on PC19 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [SR1C]: PCI Express Port 1C on PC19 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [SR1D]: PCI Express Port 1D on PC19 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [CHD0]: Uncore 13 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [CHD1]: Uncore 13 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [CHD2]: Uncore 13 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [CHD3]: Uncore 13 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [CHD4]: Uncore 13 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [CHD5]: Uncore 13 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [CHD6]: Uncore 13 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [CHD7]: Uncore 13 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + // [CM12]: Uncore 13 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + // [CM13]: Uncore 13 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [CM14]: Uncore 13 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [CM15]: Uncore 13 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + // [CDL3]: Uncore 13 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + // [PCU3]: Uncore 13 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + // [VCU3]: Uncore 13 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + Name (AH59, Package() { + // [SR1A]: PCI Express Port 1A on PC19 + Package() { 0x0000FFFF, 0, 0, 183 }, + // [SR1B]: PCI Express Port 1B on PC19 + Package() { 0x0001FFFF, 0, 0, 183 }, + // [SR1C]: PCI Express Port 1C on PC19 + Package() { 0x0002FFFF, 0, 0, 183 }, + // [SR1D]: PCI Express Port 1D on PC19 + Package() { 0x0003FFFF, 0, 0, 183 }, + // [CHD0]: Uncore 13 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 176 }, + Package() { 0x0008FFFF, 1, 0, 180 }, + Package() { 0x0008FFFF, 2, 0, 181 }, + Package() { 0x0008FFFF, 3, 0, 182 }, + // [CHD1]: Uncore 13 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 176 }, + Package() { 0x0009FFFF, 1, 0, 180 }, + Package() { 0x0009FFFF, 2, 0, 181 }, + Package() { 0x0009FFFF, 3, 0, 182 }, + // [CHD2]: Uncore 13 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 176 }, + Package() { 0x000AFFFF, 1, 0, 180 }, + Package() { 0x000AFFFF, 2, 0, 181 }, + Package() { 0x000AFFFF, 3, 0, 182 }, + // [CHD3]: Uncore 13 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 176 }, + Package() { 0x000BFFFF, 1, 0, 180 }, + Package() { 0x000BFFFF, 2, 0, 181 }, + Package() { 0x000BFFFF, 3, 0, 182 }, + // [CHD4]: Uncore 13 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 176 }, + Package() { 0x000EFFFF, 1, 0, 180 }, + Package() { 0x000EFFFF, 2, 0, 181 }, + Package() { 0x000EFFFF, 3, 0, 182 }, + // [CHD5]: Uncore 13 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 176 }, + Package() { 0x000FFFFF, 1, 0, 180 }, + Package() { 0x000FFFFF, 2, 0, 181 }, + Package() { 0x000FFFFF, 3, 0, 182 }, + // [CHD6]: Uncore 13 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 176 }, + Package() { 0x0010FFFF, 1, 0, 180 }, + Package() { 0x0010FFFF, 2, 0, 181 }, + Package() { 0x0010FFFF, 3, 0, 182 }, + // [CHD7]: Uncore 13 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 176 }, + Package() { 0x0011FFFF, 1, 0, 180 }, + Package() { 0x0011FFFF, 2, 0, 181 }, + Package() { 0x0011FFFF, 3, 0, 182 }, + // [CM12]: Uncore 13 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 176 }, + Package() { 0x0014FFFF, 1, 0, 180 }, + Package() { 0x0014FFFF, 2, 0, 181 }, + Package() { 0x0014FFFF, 3, 0, 182 }, + // [CM13]: Uncore 13 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 176 }, + Package() { 0x0015FFFF, 1, 0, 180 }, + Package() { 0x0015FFFF, 2, 0, 181 }, + Package() { 0x0015FFFF, 3, 0, 182 }, + // [CM14]: Uncore 13 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 176 }, + Package() { 0x0016FFFF, 1, 0, 180 }, + Package() { 0x0016FFFF, 2, 0, 181 }, + Package() { 0x0016FFFF, 3, 0, 182 }, + // [CM15]: Uncore 13 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 176 }, + Package() { 0x0017FFFF, 1, 0, 180 }, + Package() { 0x0017FFFF, 2, 0, 181 }, + Package() { 0x0017FFFF, 3, 0, 182 }, + // [CDL3]: Uncore 13 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 176 }, + Package() { 0x001DFFFF, 1, 0, 180 }, + Package() { 0x001DFFFF, 2, 0, 181 }, + Package() { 0x001DFFFF, 3, 0, 182 }, + // [PCU3]: Uncore 13 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 176 }, + Package() { 0x001EFFFF, 1, 0, 180 }, + Package() { 0x001EFFFF, 2, 0, 181 }, + Package() { 0x001EFFFF, 3, 0, 182 }, + // [VCU3]: Uncore 13 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 176 }, + Package() { 0x001FFFFF, 1, 0, 180 }, + Package() { 0x001FFFFF, 2, 0, 181 }, + Package() { 0x001FFFFF, 3, 0, 182 }, + }) + + Name (PR5A, Package() { + // [SL2E]: PCI Express Slot 46 on 1A on PC19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5A, Package() { + // [SL2E]: PCI Express Slot 46 on 1A on PC19 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH5A, Package() { + // [SL2E]: PCI Express Slot 46 on 1A on PC19 + Package() { 0x0000FFFF, 0, 0, 176 }, + Package() { 0x0000FFFF, 1, 0, 180 }, + Package() { 0x0000FFFF, 2, 0, 181 }, + Package() { 0x0000FFFF, 3, 0, 182 }, + }) + + Name (PR5B, Package() { + // [SL2F]: PCI Express Slot 47 on 1B on PC19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5B, Package() { + // [SL2F]: PCI Express Slot 47 on 1B on PC19 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH5B, Package() { + // [SL2F]: PCI Express Slot 47 on 1B on PC19 + Package() { 0x0000FFFF, 0, 0, 177 }, + Package() { 0x0000FFFF, 1, 0, 182 }, + Package() { 0x0000FFFF, 2, 0, 180 }, + Package() { 0x0000FFFF, 3, 0, 181 }, + }) + + Name (PR5C, Package() { + // [SL30]: PCI Express Slot 48 on 1C on PC19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5C, Package() { + // [SL30]: PCI Express Slot 48 on 1C on PC19 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH5C, Package() { + // [SL30]: PCI Express Slot 48 on 1C on PC19 + Package() { 0x0000FFFF, 0, 0, 178 }, + Package() { 0x0000FFFF, 1, 0, 181 }, + Package() { 0x0000FFFF, 2, 0, 182 }, + Package() { 0x0000FFFF, 3, 0, 180 }, + }) + + Name (PR5D, Package() { + // [SL31]: PCI Express Slot 49 on 1D on PC19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5D, Package() { + // [SL31]: PCI Express Slot 49 on 1D on PC19 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH5D, Package() { + // [SL31]: PCI Express Slot 49 on 1D on PC19 + Package() { 0x0000FFFF, 0, 0, 179 }, + Package() { 0x0000FFFF, 1, 0, 182 }, + Package() { 0x0000FFFF, 2, 0, 180 }, + Package() { 0x0000FFFF, 3, 0, 181 }, + }) + + Name (PR5E, Package() { + // [SR2A]: PCI Express Port 2A on PC20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR2B]: PCI Express Port 2B on PC20 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR2C]: PCI Express Port 2C on PC20 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR2D]: PCI Express Port 2D on PC20 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [M2M6]: Uncore 14 M2MEM0 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2M7]: Uncore 14 M2MEM10 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM6]: Uncore 14 MCMAIN Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD6]: Uncore 14 MCDECS2 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM7]: Uncore 14 MCMAIN Device + Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD7]: Uncore 14 MCDECS12 Device + Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5E, Package() { + // [SR2A]: PCI Express Port 2A on PC20 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [SR2B]: PCI Express Port 2B on PC20 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [SR2C]: PCI Express Port 2C on PC20 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [SR2D]: PCI Express Port 2D on PC20 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [M2M6]: Uncore 14 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [M2M7]: Uncore 14 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [MCM6]: Uncore 14 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [MCD6]: Uncore 14 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [MCM7]: Uncore 14 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + // [MCD7]: Uncore 14 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + // [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH5E, Package() { + // [SR2A]: PCI Express Port 2A on PC20 + Package() { 0x0000FFFF, 0, 0, 191 }, + // [SR2B]: PCI Express Port 2B on PC20 + Package() { 0x0001FFFF, 0, 0, 191 }, + // [SR2C]: PCI Express Port 2C on PC20 + Package() { 0x0002FFFF, 0, 0, 191 }, + // [SR2D]: PCI Express Port 2D on PC20 + Package() { 0x0003FFFF, 0, 0, 191 }, + // [M2M6]: Uncore 14 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 184 }, + Package() { 0x0008FFFF, 1, 0, 188 }, + Package() { 0x0008FFFF, 2, 0, 189 }, + Package() { 0x0008FFFF, 3, 0, 190 }, + // [M2M7]: Uncore 14 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 184 }, + Package() { 0x0009FFFF, 1, 0, 188 }, + Package() { 0x0009FFFF, 2, 0, 189 }, + Package() { 0x0009FFFF, 3, 0, 190 }, + // [MCM6]: Uncore 14 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 184 }, + Package() { 0x000AFFFF, 1, 0, 188 }, + Package() { 0x000AFFFF, 2, 0, 189 }, + Package() { 0x000AFFFF, 3, 0, 190 }, + // [MCD6]: Uncore 14 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 184 }, + Package() { 0x000BFFFF, 1, 0, 188 }, + Package() { 0x000BFFFF, 2, 0, 189 }, + Package() { 0x000BFFFF, 3, 0, 190 }, + // [MCM7]: Uncore 14 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 184 }, + Package() { 0x000CFFFF, 1, 0, 188 }, + Package() { 0x000CFFFF, 2, 0, 189 }, + Package() { 0x000CFFFF, 3, 0, 190 }, + // [MCD7]: Uncore 14 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 184 }, + Package() { 0x000DFFFF, 1, 0, 188 }, + Package() { 0x000DFFFF, 2, 0, 189 }, + Package() { 0x000DFFFF, 3, 0, 190 }, + // [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 184 }, + Package() { 0x0016FFFF, 1, 0, 188 }, + Package() { 0x0016FFFF, 2, 0, 189 }, + Package() { 0x0016FFFF, 3, 0, 190 }, + // [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 184 }, + Package() { 0x0017FFFF, 1, 0, 188 }, + Package() { 0x0017FFFF, 2, 0, 189 }, + Package() { 0x0017FFFF, 3, 0, 190 }, + }) + + Name (PR5F, Package() { + // [SL32]: PCI Express Slot 50 on 2A on PC20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5F, Package() { + // [SL32]: PCI Express Slot 50 on 2A on PC20 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH5F, Package() { + // [SL32]: PCI Express Slot 50 on 2A on PC20 + Package() { 0x0000FFFF, 0, 0, 184 }, + Package() { 0x0000FFFF, 1, 0, 188 }, + Package() { 0x0000FFFF, 2, 0, 189 }, + Package() { 0x0000FFFF, 3, 0, 190 }, + }) + + Name (PR60, Package() { + // [SL33]: PCI Express Slot 51 on 2B on PC20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR60, Package() { + // [SL33]: PCI Express Slot 51 on 2B on PC20 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH60, Package() { + // [SL33]: PCI Express Slot 51 on 2B on PC20 + Package() { 0x0000FFFF, 0, 0, 185 }, + Package() { 0x0000FFFF, 1, 0, 190 }, + Package() { 0x0000FFFF, 2, 0, 188 }, + Package() { 0x0000FFFF, 3, 0, 189 }, + }) + + Name (PR61, Package() { + // [SL34]: PCI Express Slot 52 on 2C on PC20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR61, Package() { + // [SL34]: PCI Express Slot 52 on 2C on PC20 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH61, Package() { + // [SL34]: PCI Express Slot 52 on 2C on PC20 + Package() { 0x0000FFFF, 0, 0, 186 }, + Package() { 0x0000FFFF, 1, 0, 189 }, + Package() { 0x0000FFFF, 2, 0, 190 }, + Package() { 0x0000FFFF, 3, 0, 188 }, + }) + + Name (PR62, Package() { + // [SL35]: PCI Express Slot 53 on 2D on PC20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR62, Package() { + // [SL35]: PCI Express Slot 53 on 2D on PC20 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH62, Package() { + // [SL35]: PCI Express Slot 53 on 2D on PC20 + Package() { 0x0000FFFF, 0, 0, 187 }, + Package() { 0x0000FFFF, 1, 0, 190 }, + Package() { 0x0000FFFF, 2, 0, 188 }, + Package() { 0x0000FFFF, 3, 0, 189 }, + }) + + Name (PR63, Package() { + // [SR3A]: PCI Express Port 3A on PC21 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR3B]: PCI Express Port 3B on PC21 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR3C]: PCI Express Port 3C on PC21 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR3D]: PCI Express Port 3D on PC21 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [KTI9]: Uncore 15 KTI9 + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KT10]: Uncore 15 KT10 + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KT11]: Uncore 15 KT11 + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M3K3]: Uncore 15 M3K3 + Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2U3]: Uncore 15 M2U3 + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2D3]: Uncore 15 M2D3 + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M23]: Uncore 15 M23 + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR63, Package() { + // [SR3A]: PCI Express Port 3A on PC21 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [SR3B]: PCI Express Port 3B on PC21 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [SR3C]: PCI Express Port 3C on PC21 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [SR3D]: PCI Express Port 3D on PC21 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [KTI9]: Uncore 15 KTI9 + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [KT10]: Uncore 15 KT10 + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [KT11]: Uncore 15 KT11 + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [M3K3]: Uncore 15 M3K3 + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + // [M2U3]: Uncore 15 M2U3 + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [M2D3]: Uncore 15 M2D3 + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [M23]: Uncore 15 M23 + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH63, Package() { + // [SR3A]: PCI Express Port 3A on PC21 + Package() { 0x0000FFFF, 0, 0, 199 }, + // [SR3B]: PCI Express Port 3B on PC21 + Package() { 0x0001FFFF, 0, 0, 199 }, + // [SR3C]: PCI Express Port 3C on PC21 + Package() { 0x0002FFFF, 0, 0, 199 }, + // [SR3D]: PCI Express Port 3D on PC21 + Package() { 0x0003FFFF, 0, 0, 199 }, + // [KTI9]: Uncore 15 KTI9 + Package() { 0x000EFFFF, 0, 0, 192 }, + Package() { 0x000EFFFF, 1, 0, 196 }, + Package() { 0x000EFFFF, 2, 0, 197 }, + Package() { 0x000EFFFF, 3, 0, 198 }, + // [KT10]: Uncore 15 KT10 + Package() { 0x000FFFFF, 0, 0, 192 }, + Package() { 0x000FFFFF, 1, 0, 196 }, + Package() { 0x000FFFFF, 2, 0, 197 }, + Package() { 0x000FFFFF, 3, 0, 198 }, + // [KT11]: Uncore 15 KT11 + Package() { 0x0010FFFF, 0, 0, 192 }, + Package() { 0x0010FFFF, 1, 0, 196 }, + Package() { 0x0010FFFF, 2, 0, 197 }, + Package() { 0x0010FFFF, 3, 0, 198 }, + // [M3K3]: Uncore 15 M3K3 + Package() { 0x0012FFFF, 0, 0, 192 }, + Package() { 0x0012FFFF, 1, 0, 196 }, + Package() { 0x0012FFFF, 2, 0, 197 }, + Package() { 0x0012FFFF, 3, 0, 198 }, + // [M2U3]: Uncore 15 M2U3 + Package() { 0x0015FFFF, 0, 0, 192 }, + Package() { 0x0015FFFF, 1, 0, 196 }, + Package() { 0x0015FFFF, 2, 0, 197 }, + Package() { 0x0015FFFF, 3, 0, 198 }, + // [M2D3]: Uncore 15 M2D3 + Package() { 0x0016FFFF, 0, 0, 192 }, + Package() { 0x0016FFFF, 1, 0, 196 }, + Package() { 0x0016FFFF, 2, 0, 197 }, + Package() { 0x0016FFFF, 3, 0, 198 }, + // [M23]: Uncore 15 M23 + Package() { 0x0017FFFF, 0, 0, 192 }, + Package() { 0x0017FFFF, 1, 0, 196 }, + Package() { 0x0017FFFF, 2, 0, 197 }, + Package() { 0x0017FFFF, 3, 0, 198 }, + }) + + Name (PR64, Package() { + // [SL36]: PCI Express Slot 54 on 3A on PC21 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR64, Package() { + // [SL36]: PCI Express Slot 54 on 3A on PC21 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH64, Package() { + // [SL36]: PCI Express Slot 54 on 3A on PC21 + Package() { 0x0000FFFF, 0, 0, 192 }, + Package() { 0x0000FFFF, 1, 0, 196 }, + Package() { 0x0000FFFF, 2, 0, 197 }, + Package() { 0x0000FFFF, 3, 0, 198 }, + }) + + Name (PR65, Package() { + // [SL37]: PCI Express Slot 55 on 3B on PC21 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR65, Package() { + // [SL37]: PCI Express Slot 55 on 3B on PC21 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH65, Package() { + // [SL37]: PCI Express Slot 55 on 3B on PC21 + Package() { 0x0000FFFF, 0, 0, 193 }, + Package() { 0x0000FFFF, 1, 0, 198 }, + Package() { 0x0000FFFF, 2, 0, 196 }, + Package() { 0x0000FFFF, 3, 0, 197 }, + }) + + Name (PR66, Package() { + // [SL38]: PCI Express Slot 56 on 3C on PC21 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR66, Package() { + // [SL38]: PCI Express Slot 56 on 3C on PC21 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH66, Package() { + // [SL38]: PCI Express Slot 56 on 3C on PC21 + Package() { 0x0000FFFF, 0, 0, 194 }, + Package() { 0x0000FFFF, 1, 0, 197 }, + Package() { 0x0000FFFF, 2, 0, 198 }, + Package() { 0x0000FFFF, 3, 0, 196 }, + }) + + Name (PR67, Package() { + // [SL39]: PCI Express Slot 57 on 3D on PC21 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR67, Package() { + // [SL39]: PCI Express Slot 57 on 3D on PC21 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH67, Package() { + // [SL39]: PCI Express Slot 57 on 3D on PC21 + Package() { 0x0000FFFF, 0, 0, 195 }, + Package() { 0x0000FFFF, 1, 0, 198 }, + Package() { 0x0000FFFF, 2, 0, 196 }, + Package() { 0x0000FFFF, 3, 0, 197 }, + }) + + Name (PR68, Package() { + // [MCP6]: PCI Express Port 4 on PC22 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR68, Package() { + // [MCP6]: PCI Express Port 4 on PC22 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH68, Package() { + // [MCP6]: PCI Express Port 4 on PC22 + Package() { 0x0000FFFF, 0, 0, 207 }, + }) + + Name (PR69, Package() { + // [SL3A]: PCI Express Slot 58 on 4 on PC22 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR69, Package() { + // [SL3A]: PCI Express Slot 58 on 4 on PC22 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH69, Package() { + // [SL3A]: PCI Express Slot 58 on 4 on PC22 + Package() { 0x0000FFFF, 0, 0, 200 }, + Package() { 0x0000FFFF, 1, 0, 204 }, + Package() { 0x0000FFFF, 2, 0, 205 }, + Package() { 0x0000FFFF, 3, 0, 206 }, + }) + + Name (PR6A, Package() { + // [MCP7]: PCI Express Port 5 on PC23 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR6A, Package() { + // [MCP7]: PCI Express Port 5 on PC23 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH6A, Package() { + // [MCP7]: PCI Express Port 5 on PC23 + Package() { 0x0000FFFF, 0, 0, 215 }, + }) + + Name (PR6B, Package() { + // [SL3B]: PCI Express Slot 59 on 4 on PC23 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR6B, Package() { + // [SL3B]: PCI Express Slot 59 on 4 on PC23 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH6B, Package() { + // [SL3B]: PCI Express Slot 59 on 4 on PC23 + Package() { 0x0000FFFF, 0, 0, 208 }, + Package() { 0x0000FFFF, 1, 0, 212 }, + Package() { 0x0000FFFF, 2, 0, 213 }, + Package() { 0x0000FFFF, 3, 0, 214 }, + }) + + Name (PR6C, Package() { + // [FPG0]: FPGA Device + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR6C, Package() { + // [FPG0]: FPGA Device + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (PR6D, Package() { + // [FPG1]: FPGA Device + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR6D, Package() { + // [FPG1]: FPGA Device + Package() { 0x0000FFFF, 1, 0, 17 }, + }) + + Name (PR6E, Package() { + // [FPG2]: FPGA Device + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR6E, Package() { + // [FPG2]: FPGA Device + Package() { 0x0000FFFF, 2, 0, 18 }, + }) + + Name (PR6F, Package() { + // [FPG3]: FPGA Device + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR6F, Package() { + // [FPG3]: FPGA Device + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR70, Package() { + // [FKT0]: FPGA Device + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR70, Package() { + // [FKT0]: FPGA Device + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (PR71, Package() { + // [FKT1]: FPGA Device + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR71, Package() { + // [FKT1]: FPGA Device + Package() { 0x0000FFFF, 1, 0, 17 }, + }) + + Name (PR72, Package() { + // [FKT2]: FPGA Device + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR72, Package() { + // [FKT2]: FPGA Device + Package() { 0x0000FFFF, 2, 0, 18 }, + }) + + Name (PR73, Package() { + // [FKT3]: FPGA Device + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR73, Package() { + // [FKT3]: FPGA Device + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + // Socket 0 Root bridge (Stack 0) + Device (PC00) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x00) + Method (_BBN, 0, NotSerialized) { + return (BB00) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR00) + } + If (LEqual(AP00, One)) { + Return (AH00) + } + Return (AR00) + } + + #include "PC00.asi" + #include "HostBus.asl" + + // Legacy PCI Express Port 0 on PC00 + Device (DMI0) { + Name (_ADR, 0x00000000) + } + + // CB3DMA on PC00 + Device (CB0A) { + Name (_ADR, 0x00040000) + } + + // CB3DMA on PC00 + Device (CB0B) { + Name (_ADR, 0x00040001) + } + + // CB3DMA on PC00 + Device (CB0C) { + Name (_ADR, 0x00040002) + } + + // CB3DMA on PC00 + Device (CB0D) { + Name (_ADR, 0x00040003) + } + + // CB3DMA on PC00 + Device (CB0E) { + Name (_ADR, 0x00040004) + } + + // CB3DMA on PC00 + Device (CB0F) { + Name (_ADR, 0x00040005) + } + + // CB3DMA on PC00 + Device (CB0G) { + Name (_ADR, 0x00040006) + } + + // CB3DMA on PC00 + Device (CB0H) { + Name (_ADR, 0x00040007) + } + + // IIOMISC on PC00 + Device (IIM0) { + Name (_ADR, 0x00050000) + } + + // Uncore 0 UBOX Device + Device (UBX0) { + Name (_ADR, 0x00080000) + } + + // High definition Audio Controller + Device (ALZA) { + Name (_ADR, 0x000E0000) + } + + // Display Controller + Device (DISP) { + Name (_ADR, 0x000F0000) + } + + // HECI #1 + Device (IHC1) { + Name (_ADR, 0x00100000) + } + + // HECI #2 + Device (IHC2) { + Name (_ADR, 0x00100001) + } + + // IDE-Redirection (IDE-R) + Device (IIDR) { + Name (_ADR, 0x00100002) + } + + // Keyboard and Text (KT) Redirection + Device (IMKT) { + Name (_ADR, 0x00100003) + } + + // HECI #3 + Device (IHC3) { + Name (_ADR, 0x00100004) + } + + // MROM 0 function function + Device (MRO0) { + Name (_ADR, 0x00110000) + } + + // MROM 1 function function + Device (MRO1) { + Name (_ADR, 0x00110001) + } + + // sSATA Host controller 2 on PCH + Device (SAT2) { + Name (_ADR, 0x00110005) + } + + // xHCI controller 1 on PCH + Device (XHCI) { + Name (_ADR, 0x00140000) + } + + // USB Device Controller (OTG) on PCH + Device (OTG0) { + Name (_ADR, 0x00140001) + } + + // Thermal Subsystem on PCH + Device (TERM) { + Name (_ADR, 0x00140002) + } + + // Camera IO Host Controller on PCH + Device (CAMR) { + Name (_ADR, 0x00140003) + } + + // Northpeak Phantom (ACPI) Function on PCH + Device (NTHP) { + Name (_ADR, 0x00140004) + } + + // HECI #1 on PCH + Device (HEC1) { + Name (_ADR, 0x00160000) + } + + // HECI #2 on PCH + Device (HEC2) { + Name (_ADR, 0x00160001) + } + + // ME IDE redirect on PCH + Device (IDER) { + Name (_ADR, 0x00160002) + } + + // MEKT on PCH + Device (MEKT) { + Name (_ADR, 0x00160003) + } + + // HECI #3 on PCH + Device (HEC3) { + Name (_ADR, 0x00160004) + } + + // SATA controller 1 on PCH + Device (SAT1) { + Name (_ADR, 0x00170000) + } + + // NAND Cycle Router on PCH + Device (NAN1) { + Name (_ADR, 0x00180000) + } + + // PCIE PCH Root Port #17 + Device (RP17) { + #include "RP17_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR01) + } + Return (AR01) + } + + // PCIE PCH Slot #17 + Device (SLTH) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #18 + Device (RP18) { + #include "RP18_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR02) + } + Return (AR02) + } + + // PCIE PCH Slot #18 + Device (SLTI) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #19 + Device (RP19) { + #include "RP19_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR03) + } + Return (AR03) + } + + // PCIE PCH Slot #19 + Device (SLTJ) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #20 + Device (RP20) { + #include "RP20_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR04) + } + Return (AR04) + } + + // PCIE PCH Slot #20 + Device (SLTK) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #1 + Device (RP01) { + #include "RP01_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR05) + } + Return (AR05) + } + } + + // PCIE PCH Root Port #2 + Device (RP02) { + #include "RP02_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR06) + } + Return (AR06) + } + } + + // PCIE PCH Root Port #3 + Device (RP03) { + #include "RP03_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR07) + } + Return (AR07) + } + } + + // PCIE PCH Root Port #4 + Device (RP04) { + #include "RP04_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR08) + } + Return (AR08) + } + } + + // PCIE PCH Root Port #5 + Device (RP05) { + #include "RP05_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR09) + } + Return (AR09) + } + } + + // PCIE PCH Root Port #6 + Device (RP06) { + #include "RP06_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0A) + } + Return (AR0A) + } + } + + // PCIE PCH Root Port #7 + Device (RP07) { + #include "RP07_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0B) + } + Return (AR0B) + } + } + + // PCIE PCH Root Port #8 + Device (RP08) { + #include "RP08_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0C) + } + Return (AR0C) + } + } + + // PCIE PCH Root Port #9 + Device (RP09) { + #include "RP09_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0D) + } + Return (AR0D) + } + + // PCIE PCH Slot #9 + Device (SLT9) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #10 + Device (RP10) { + #include "RP10_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0E) + } + Return (AR0E) + } + + // PCIE PCH Slot #10 + Device (SLTA) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #11 + Device (RP11) { + #include "RP11_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0F) + } + Return (AR0F) + } + + // PCIE PCH Slot #11 + Device (SLTB) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #12 + Device (RP12) { + #include "RP12_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR10) + } + Return (AR10) + } + + // PCIE PCH Slot #12 + Device (SLTC) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #13 + Device (RP13) { + #include "RP13_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR11) + } + Return (AR11) + } + + // PCIE PCH Slot #13 + Device (SLTD) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #14 + Device (RP14) { + #include "RP14_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR12) + } + Return (AR12) + } + + // PCIE PCH Slot #14 + Device (SLTE) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #15 + Device (RP15) { + #include "RP15_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR13) + } + Return (AR13) + } + + // PCIE PCH Slot #15 + Device (SLTF) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #16 + Device (RP16) { + #include "RP16_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR14) + } + Return (AR14) + } + + // PCIE PCH Slot #16 + Device (SLTG) { + Name (_ADR, 0x00000000) + } + } + + // UART #0 on PCH + Device (UAR0) { + Name (_ADR, 0x001E0000) + } + + // UART #1 on PCH + Device (UAR1) { + Name (_ADR, 0x001E0001) + } + + // SPI #0 on PCH + Device (SPI0) { + Name (_ADR, 0x001E0002) + } + + // SPI #1 on PCH + Device (SPI1) { + Name (_ADR, 0x001E0003) + } + + // ISA Bridge on PCH + Device (LPC0) { + Name (_ADR, 0x001F0000) + + #include "PchLpc.asi" + } + + // Power Management Controller on PCH + Device (PMC1) { + Name (_ADR, 0x001F0002) + } + + // HD Audio Subsystem Controller on PCH + Device (CAVS) { + Name (_ADR, 0x001F0003) + } + + // SMBus controller on PCH + Device (SMBS) { + Name (_ADR, 0x001F0004) + } + + // SPI controller on PCH + Device (SPIC) { + Name (_ADR, 0x001F0005) + } + + // GbE Controller on PCH + Device (GBE1) { + Name (_ADR, 0x001F0006) + } + + // Northpeak Controller on PCH + Device (NTPK) { + Name (_ADR, 0x001F0007) + } + } + + // Socket 0 Root bridge (Stack 1) + Device (PC01) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x01) + Method (_BBN, 0, NotSerialized) { + return (BB01) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR15) + } + If (LEqual(AP01, One)) { + Return (AH15) + } + Return (AR15) + } + + #include "PC01.asi" + + // PCI Express Port 1A on PC01 + Device (BR1A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR16) + } + If (LEqual(AP01, One)) { + Return (AH16) + } + Return (AR16) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 1B on PC01 + Device (BR1B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR17) + } + If (LEqual(AP01, One)) { + Return (AH17) + } + Return (AR17) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 1C on PC01 + Device (BR1C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR18) + } + If (LEqual(AP01, One)) { + Return (AH18) + } + Return (AR18) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 1D on PC01 + Device (BR1D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR19) + } + If (LEqual(AP01, One)) { + Return (AH19) + } + Return (AR19) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // Uncore 1 CHAUTIL0-7 Device + Device (CHA0) { + Name (_ADR, 0x00080000) + } + + // Uncore 1 CHAUTIL8-15 Device + Device (CHA1) { + Name (_ADR, 0x00090000) + } + + // Uncore 1 CHAUTIL16-23 Device + Device (CHA2) { + Name (_ADR, 0x000A0000) + } + + // Uncore 1 CHAUTIL24-27 Device + Device (CHA3) { + Name (_ADR, 0x000B0000) + } + + // Uncore 1 CHASAD0-7 Device + Device (CHA4) { + Name (_ADR, 0x000E0000) + } + + // Uncore 1 CHASAD8-15 Device + Device (CHA5) { + Name (_ADR, 0x000F0000) + } + + // Uncore 1 CHASAD16-23 Device + Device (CHA6) { + Name (_ADR, 0x00100000) + } + + // Uncore 1 CHASAD24-27 Device + Device (CHA7) { + Name (_ADR, 0x00110000) + } + + // Uncore 1 CMSCHA0-7 Device + Device (CMS0) { + Name (_ADR, 0x00140000) + } + + // Uncore 1 CMS0CHA8-15 Device + Device (CMS1) { + Name (_ADR, 0x00150000) + } + + // Uncore 1 CMS0CHA16-23 Device + Device (CMS2) { + Name (_ADR, 0x00160000) + } + + // Uncore 1 CMS0CHA24-27 Device + Device (CMS3) { + Name (_ADR, 0x00170000) + } + + // Uncore 1 CHASADALL Device + Device (CDL0) { + Name (_ADR, 0x001D0000) + } + + // Uncore 1 PCUCR Devices + Device (PCU0) { + Name (_ADR, 0x001E0000) + } + + // Uncore 1 VCUCR Device + Device (VCU0) { + Name (_ADR, 0x001F0000) + } + } + + // Socket 0 Root bridge (Stack 2) + Device (PC02) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x02) + Method (_BBN, 0, NotSerialized) { + return (BB02) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1A) + } + If (LEqual(AP02, One)) { + Return (AH1A) + } + Return (AR1A) + } + + #include "PC02.asi" + + // PCI Express Port 2A on PC02 + Device (BR2A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1B) + } + If (LEqual(AP02, One)) { + Return (AH1B) + } + Return (AR1B) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + + // EVA PCIe Uplink + Device (EPCU) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x0B, 0x00}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1C) + } + If (LEqual(AP02, One)) { + Return (AH1C) + } + Return (AR1C) + } + + // EVA Virtual Switch Port 0 + Device (VSP0) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x0B, 0x00}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1D) + } + If (LEqual(AP02, One)) { + Return (AH1D) + } + Return (AR1D) + } + + // EVA CPM0 + Device (CPM0) { + Name (_ADR, 0x00000000) + } + } + + // EVA Virtual Switch Port 1 + Device (VSP1) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x0B, 0x00}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1E) + } + If (LEqual(AP02, One)) { + Return (AH1E) + } + Return (AR1E) + } + + // EVA CPM1 + Device (CPM1) { + Name (_ADR, 0x00000000) + } + } + + // EVA Virtual Switch Port 2 + Device (VSP2) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x0B, 0x00}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1F) + } + If (LEqual(AP02, One)) { + Return (AH1F) + } + Return (AR1F) + } + + // EVA CPM2 + Device (CPM2) { + Name (_ADR, 0x00000000) + } + } + + // EVA Virtual Switch Port 3 + Device (VSP3) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x0B, 0x00}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR20) + } + If (LEqual(AP02, One)) { + Return (AH20) + } + Return (AR20) + } + + // EVA Fort Park 0 + Device (FPK0) { + Name (_ADR, 0x00000000) + } + + // EVA Fort Park 1 + Device (FPK1) { + Name (_ADR, 0x00000001) + } + + // EVA Fort Park 2 + Device (FPK2) { + Name (_ADR, 0x00000002) + } + + // EVA Fort Park 3 + Device (FPK3) { + Name (_ADR, 0x00000003) + } + } + } + } + + // PCI Express Port 2B on PC02 + Device (BR2B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR21) + } + If (LEqual(AP02, One)) { + Return (AH21) + } + Return (AR21) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 2C on PC02 + Device (BR2C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR22) + } + If (LEqual(AP02, One)) { + Return (AH22) + } + Return (AR22) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 2D on PC02 + Device (BR2D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR23) + } + If (LEqual(AP02, One)) { + Return (AH23) + } + Return (AR23) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // Uncore 2 M2MEM0 Device + Device (M2M0) { + Name (_ADR, 0x00080000) + } + + // Uncore 2 M2MEM10 Device + Device (M2M1) { + Name (_ADR, 0x00090000) + } + + // Uncore 2 MCMAIN Device + Device (MCM0) { + Name (_ADR, 0x000A0000) + } + + // Uncore 2 MCDECS2 Device + Device (MCD0) { + Name (_ADR, 0x000B0000) + } + + // Uncore 2 MCMAIN Device + Device (MCM1) { + Name (_ADR, 0x000C0000) + } + + // Uncore 2 MCDECS12 Device + Device (MCD1) { + Name (_ADR, 0x000D0000) + } + + // Uncore 2 Unicast MC0 DDRIO0 Device + Device (UMC0) { + Name (_ADR, 0x00160000) + } + + // Uncore 2 Unicast MC1 DDRIO0 Device + Device (UMC1) { + Name (_ADR, 0x00170000) + } + } + + // Socket 0 Root bridge (Stack 3) + Device (PC03) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x03) + Method (_BBN, 0, NotSerialized) { + return (BB03) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR24) + } + If (LEqual(AP03, One)) { + Return (AH24) + } + Return (AR24) + } + + #include "PC03.asi" + + // PCI Express Port 3A on PC03 + Device (BR3A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR25) + } + If (LEqual(AP03, One)) { + Return (AH25) + } + Return (AR25) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 3B on PC03 + Device (BR3B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR26) + } + If (LEqual(AP03, One)) { + Return (AH26) + } + Return (AR26) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 3C on PC03 + Device (BR3C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR27) + } + If (LEqual(AP03, One)) { + Return (AH27) + } + Return (AR27) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 3D on PC03 + Device (BR3D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR28) + } + If (LEqual(AP03, One)) { + Return (AH28) + } + Return (AR28) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // KTI0 + Device (KTI0) { + Name (_ADR, 0x000E0000) + } + + // KTI1 + Device (KTI1) { + Name (_ADR, 0x000F0000) + } + + // KTI2 + Device (KTI2) { + Name (_ADR, 0x00100000) + } + + // M3K0 + Device (M3K0) { + Name (_ADR, 0x00120000) + } + + // M2U0 + Device (M2U0) { + Name (_ADR, 0x00150000) + } + + // M2D0 + Device (M2D0) { + Name (_ADR, 0x00160000) + } + + // M20 + Device (M20) { + Name (_ADR, 0x00170000) + } + } + + // Socket 0 Root bridge (Stack 4) + Device (PC04) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x04) + Method (_BBN, 0, NotSerialized) { + return (BB04) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR29) + } + If (LEqual(AP04, One)) { + Return (AH29) + } + Return (AR29) + } + + #include "PC04.asi" + + // PCI Express Port 4 on PC04 + Device (MCP0) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2A) + } + If (LEqual(AP04, One)) { + Return (AH2A) + } + Return (AR2A) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + } + } + + // Socket 0 Root bridge (Stack 5) + Device (PC05) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x05) + Method (_BBN, 0, NotSerialized) { + return (BB05) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2B) + } + If (LEqual(AP05, One)) { + Return (AH2B) + } + Return (AR2B) + } + + #include "PC05.asi" + + // PCI Express Port 5 on PC05 + Device (MCP1) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2C) + } + If (LEqual(AP05, One)) { + Return (AH2C) + } + Return (AR2C) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + } + } + + // Socket 1 Root bridge (Stack 0) + Device (PC06) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x06) + Method (_BBN, 0, NotSerialized) { + return (BB06) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2D) + } + If (LEqual(AP06, One)) { + Return (AH2D) + } + Return (AR2D) + } + + #include "PC06.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 0 on PC06 + Device (QRP0) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2E) + } + If (LEqual(AP06, One)) { + Return (AH2E) + } + Return (AR2E) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // CB3DMA on PC06 + Device (CB1B) { + Name (_ADR, 0x00040001) + } + + // CB3DMA on PC06 + Device (CB1C) { + Name (_ADR, 0x00040002) + } + + // CB3DMA on PC06 + Device (CB1D) { + Name (_ADR, 0x00040003) + } + + // CB3DMA on PC06 + Device (CB1E) { + Name (_ADR, 0x00040004) + } + + // CB3DMA on PC06 + Device (CB1F) { + Name (_ADR, 0x00040005) + } + + // CB3DMA on PC06 + Device (CB1G) { + Name (_ADR, 0x00040006) + } + + // CB3DMA on PC06 + Device (CB1H) { + Name (_ADR, 0x00040007) + } + + // IIOMISC on PC01 + Device (IIM1) { + Name (_ADR, 0x00050000) + } + + // Uncore 4 UBOX Device + Device (UBX1) { + Name (_ADR, 0x00080000) + } + + // CB3DMA on PC06 + Device (CB1A) { + Name (_ADR, 0x00040000) + } + } + + // Socket 1 Root bridge (Stack 1) + Device (PC07) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x07) + Method (_BBN, 0, NotSerialized) { + return (BB07) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2F) + } + If (LEqual(AP07, One)) { + Return (AH2F) + } + Return (AR2F) + } + + #include "PC07.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 1A on PC07 + Device (QR1A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR30) + } + If (LEqual(AP07, One)) { + Return (AH30) + } + Return (AR30) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 1B on PC07 + Device (QR1B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR31) + } + If (LEqual(AP07, One)) { + Return (AH31) + } + Return (AR31) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 1C on PC07 + Device (QR1C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR32) + } + If (LEqual(AP07, One)) { + Return (AH32) + } + Return (AR32) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 1D on PC07 + Device (QR1D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR33) + } + If (LEqual(AP07, One)) { + Return (AH33) + } + Return (AR33) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // Uncore 5 CHAUTIL0-7 Device + Device (CHB0) { + Name (_ADR, 0x00080000) + } + + // Uncore 5 CHAUTIL8-15 Device + Device (CHB1) { + Name (_ADR, 0x00090000) + } + + // Uncore 5 CHAUTIL16-23 Device + Device (CHB2) { + Name (_ADR, 0x000A0000) + } + + // Uncore 5 CHAUTIL24-27 Device + Device (CHB3) { + Name (_ADR, 0x000B0000) + } + + // Uncore 5 CHASAD0-7 Device + Device (CHB4) { + Name (_ADR, 0x000E0000) + } + + // Uncore 5 CHASAD8-15 Device + Device (CHB5) { + Name (_ADR, 0x000F0000) + } + + // Uncore 5 CHASAD16-23 Device + Device (CHB6) { + Name (_ADR, 0x00100000) + } + + // Uncore 5 CHASAD24-27 Device + Device (CHB7) { + Name (_ADR, 0x00110000) + } + + // Uncore 5 CMSCHA0-7 Device + Device (CMS4) { + Name (_ADR, 0x00140000) + } + + // Uncore 5 CMS0CHA8-15 Device + Device (CMS5) { + Name (_ADR, 0x00150000) + } + + // Uncore 5 CMS0CHA16-23 Device + Device (CMS6) { + Name (_ADR, 0x00160000) + } + + // Uncore 5 CMS0CHA24-27 Device + Device (CMS7) { + Name (_ADR, 0x00170000) + } + + // Uncore 5 CHASADALL Device + Device (CDL1) { + Name (_ADR, 0x001D0000) + } + + // Uncore 5 PCUCR Devices + Device (PCU1) { + Name (_ADR, 0x001E0000) + } + + // Uncore 5 VCUCR Device + Device (VCU1) { + Name (_ADR, 0x001F0000) + } + } + + // Socket 1 Root bridge (Stack 2) + Device (PC08) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x08) + Method (_BBN, 0, NotSerialized) { + return (BB08) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR34) + } + If (LEqual(AP08, One)) { + Return (AH34) + } + Return (AR34) + } + + #include "PC08.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 2A on PC08 + Device (QR2A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR35) + } + If (LEqual(AP08, One)) { + Return (AH35) + } + Return (AR35) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 2B on PC08 + Device (QR2B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR36) + } + If (LEqual(AP08, One)) { + Return (AH36) + } + Return (AR36) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 2C on PC08 + Device (QR2C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR37) + } + If (LEqual(AP08, One)) { + Return (AH37) + } + Return (AR37) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 2D on PC08 + Device (QR2D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR38) + } + If (LEqual(AP08, One)) { + Return (AH38) + } + Return (AR38) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // Uncore 6 M2MEM0 Device + Device (M2M2) { + Name (_ADR, 0x00080000) + } + + // Uncore 6 M2MEM10 Device + Device (M2M3) { + Name (_ADR, 0x00090000) + } + + // Uncore 6 MCMAIN Device + Device (MCM2) { + Name (_ADR, 0x000A0000) + } + + // Uncore 6 MCDECS2 Device + Device (MCD2) { + Name (_ADR, 0x000B0000) + } + + // Uncore 6 MCMAIN Device + Device (MCM3) { + Name (_ADR, 0x000C0000) + } + + // Uncore 6 MCDECS12 Device + Device (MCD3) { + Name (_ADR, 0x000D0000) + } + + // Uncore 6 Unicast MC0 DDRIO0 Device + Device (UMC2) { + Name (_ADR, 0x00160000) + } + + // Uncore 6 Unicast MC1 DDRIO0 Device + Device (UMC3) { + Name (_ADR, 0x00170000) + } + } + + // Socket 1 Root bridge (Stack 3) + Device (PC09) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x09) + Method (_BBN, 0, NotSerialized) { + return (BB09) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR39) + } + If (LEqual(AP09, One)) { + Return (AH39) + } + Return (AR39) + } + + #include "PC09.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 3A on PC09 + Device (QR3A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3A) + } + If (LEqual(AP09, One)) { + Return (AH3A) + } + Return (AR3A) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 3B on PC09 + Device (QR3B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3B) + } + If (LEqual(AP09, One)) { + Return (AH3B) + } + Return (AR3B) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 3C on PC09 + Device (QR3C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3C) + } + If (LEqual(AP09, One)) { + Return (AH3C) + } + Return (AR3C) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 3D on PC09 + Device (QR3D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3D) + } + If (LEqual(AP09, One)) { + Return (AH3D) + } + Return (AR3D) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // Uncore 7 KTI3 + Device (KTI3) { + Name (_ADR, 0x000E0000) + } + + // Uncore 7 KTI4 + Device (KTI4) { + Name (_ADR, 0x000F0000) + } + + // Uncore 7 KTI5 + Device (KTI5) { + Name (_ADR, 0x00100000) + } + + // Uncore 7 M3K1 + Device (M3K1) { + Name (_ADR, 0x00120000) + } + + // Uncore 7 M2U1 + Device (M2U1) { + Name (_ADR, 0x00150000) + } + + // Uncore 7 M2D1 + Device (M2D1) { + Name (_ADR, 0x00160000) + } + + // Uncore 7 M21 + Device (M21) { + Name (_ADR, 0x00170000) + } + } + + // Socket 1 Root bridge (Stack 4) + Device (PC10) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0A) + Method (_BBN, 0, NotSerialized) { + return (BB10) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3E) + } + If (LEqual(AP10, One)) { + Return (AH3E) + } + Return (AR3E) + } + + #include "PC10.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 13 on PC10 + Device (MCP2) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3F) + } + If (LEqual(AP10, One)) { + Return (AH3F) + } + Return (AR3F) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + } + + // Socket 1 Root bridge (Stack 5) + Device (PC11) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0B) + Method (_BBN, 0, NotSerialized) { + return (BB11) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR40) + } + If (LEqual(AP11, One)) { + Return (AH40) + } + Return (AR40) + } + + #include "PC11.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 14 on PC11 + Device (MCP3) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR41) + } + If (LEqual(AP11, One)) { + Return (AH41) + } + Return (AR41) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + } + + // Socket 2 Root bridge (Stack 0) + Device (PC12) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0C) + Method (_BBN, 0, NotSerialized) { + return (BB12) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR42) + } + If (LEqual(AP12, One)) { + Return (AH42) + } + Return (AR42) + } + + #include "PC12.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 0 on PC12 + Device (RRP0) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR43) + } + If (LEqual(AP12, One)) { + Return (AH43) + } + Return (AR43) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // CB3DMA on PC12 + Device (CB2B) { + Name (_ADR, 0x00040001) + } + + // CB3DMA on PC12 + Device (CB2C) { + Name (_ADR, 0x00040002) + } + + // CB3DMA on PC12 + Device (CB2D) { + Name (_ADR, 0x00040003) + } + + // CB3DMA on PC12 + Device (CB2E) { + Name (_ADR, 0x00040004) + } + + // CB3DMA on PC12 + Device (CB2F) { + Name (_ADR, 0x00040005) + } + + // CB3DMA on PC12 + Device (CB2G) { + Name (_ADR, 0x00040006) + } + + // CB3DMA on PC12 + Device (CB2H) { + Name (_ADR, 0x00040007) + } + + // IIOMISC on PC02 + Device (IIM2) { + Name (_ADR, 0x00050000) + } + + // Uncore 8 UBOX Device + Device (UBX2) { + Name (_ADR, 0x00080000) + } + + // CB3DMA on PC12 + Device (CB2A) { + Name (_ADR, 0x00040000) + } + } + + // Socket 2 Root bridge (Stack 1) + Device (PC13) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0D) + Method (_BBN, 0, NotSerialized) { + return (BB13) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR44) + } + If (LEqual(AP13, One)) { + Return (AH44) + } + Return (AR44) + } + + #include "PC13.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 1A on PC13 + Device (RR1A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR45) + } + If (LEqual(AP13, One)) { + Return (AH45) + } + Return (AR45) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 1B on PC13 + Device (RR1B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR46) + } + If (LEqual(AP13, One)) { + Return (AH46) + } + Return (AR46) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 1C on PC13 + Device (RR1C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR47) + } + If (LEqual(AP13, One)) { + Return (AH47) + } + Return (AR47) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 1D on PC13 + Device (RR1D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR48) + } + If (LEqual(AP13, One)) { + Return (AH48) + } + Return (AR48) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // Uncore 9 CHAUTIL0-7 Device + Device (CHC0) { + Name (_ADR, 0x00080000) + } + + // Uncore 9 CHAUTIL8-15 Device + Device (CHC1) { + Name (_ADR, 0x00090000) + } + + // Uncore 9 CHAUTIL16-23 Device + Device (CHC2) { + Name (_ADR, 0x000A0000) + } + + // Uncore 9 CHAUTIL24-27 Device + Device (CHC3) { + Name (_ADR, 0x000B0000) + } + + // Uncore 9 CHASAD0-7 Device + Device (CHC4) { + Name (_ADR, 0x000E0000) + } + + // Uncore 9 CHASAD8-15 Device + Device (CHC5) { + Name (_ADR, 0x000F0000) + } + + // Uncore 9 CHASAD16-23 Device + Device (CHC6) { + Name (_ADR, 0x00100000) + } + + // Uncore 9 CHASAD24-27 Device + Device (CHC7) { + Name (_ADR, 0x00110000) + } + + // Uncore 9 CMSCHA0-7 Device + Device (CMS8) { + Name (_ADR, 0x00140000) + } + + // Uncore 9 CMS0CHA8-15 Device + Device (CMS9) { + Name (_ADR, 0x00150000) + } + + // Uncore 9 CHASADALL Device + Device (CDL2) { + Name (_ADR, 0x001D0000) + } + + // Uncore 9 PCUCR Devices + Device (PCU2) { + Name (_ADR, 0x001E0000) + } + + // Uncore 9 VCUCR Device + Device (VCU2) { + Name (_ADR, 0x001F0000) + } + } + + // Socket 2 Root bridge (Stack 2) + Device (PC14) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0E) + Method (_BBN, 0, NotSerialized) { + return (BB14) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR49) + } + If (LEqual(AP14, One)) { + Return (AH49) + } + Return (AR49) + } + + #include "PC14.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 2A on PC14 + Device (RR2A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4A) + } + If (LEqual(AP14, One)) { + Return (AH4A) + } + Return (AR4A) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 2B on PC14 + Device (RR2B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4B) + } + If (LEqual(AP14, One)) { + Return (AH4B) + } + Return (AR4B) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 2C on PC14 + Device (RR2C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4C) + } + If (LEqual(AP14, One)) { + Return (AH4C) + } + Return (AR4C) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 2D on PC14 + Device (RR2D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4D) + } + If (LEqual(AP14, One)) { + Return (AH4D) + } + Return (AR4D) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // Uncore 10 M2MEM0 Device + Device (M2M4) { + Name (_ADR, 0x00080000) + } + + // Uncore 10 M2MEM10 Device + Device (M2M5) { + Name (_ADR, 0x00090000) + } + + // Uncore 10 MCMAIN Device + Device (MCM4) { + Name (_ADR, 0x000A0000) + } + + // Uncore 10 MCDECS2 Device + Device (MCD4) { + Name (_ADR, 0x000B0000) + } + + // Uncore 10 MCMAIN Device + Device (MCM5) { + Name (_ADR, 0x000C0000) + } + + // Uncore 10 MCDECS12 Device + Device (MCD5) { + Name (_ADR, 0x000D0000) + } + + // Uncore 10 Unicast MC0 DDRIO0 Device + Device (UMC4) { + Name (_ADR, 0x00160000) + } + + // Uncore 10 Unicast MC1 DDRIO0 Device + Device (UMC5) { + Name (_ADR, 0x00170000) + } + } + + // Socket 2 Root bridge (Stack 3) + Device (PC15) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0F) + Method (_BBN, 0, NotSerialized) { + return (BB15) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4E) + } + If (LEqual(AP15, One)) { + Return (AH4E) + } + Return (AR4E) + } + + #include "PC15.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 3A on PC15 + Device (RR3A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4F) + } + If (LEqual(AP15, One)) { + Return (AH4F) + } + Return (AR4F) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 3B on PC15 + Device (RR3B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR50) + } + If (LEqual(AP15, One)) { + Return (AH50) + } + Return (AR50) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 3C on PC15 + Device (RR3C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR51) + } + If (LEqual(AP15, One)) { + Return (AH51) + } + Return (AR51) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 3D on PC15 + Device (RR3D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR52) + } + If (LEqual(AP15, One)) { + Return (AH52) + } + Return (AR52) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // Uncore 11 KTI6 + Device (KTI6) { + Name (_ADR, 0x000E0000) + } + + // Uncore 11 KTI7 + Device (KTI7) { + Name (_ADR, 0x000F0000) + } + + // Uncore 11 KTI8 + Device (KTI8) { + Name (_ADR, 0x00100000) + } + + // Uncore 11 M3K2 + Device (M3K2) { + Name (_ADR, 0x00120000) + } + + // Uncore 11 M2U2 + Device (M2U2) { + Name (_ADR, 0x00150000) + } + + // Uncore 11 M2D2 + Device (M2D2) { + Name (_ADR, 0x00160000) + } + + // Uncore 11 M22 + Device (M22) { + Name (_ADR, 0x00170000) + } + } + + // Socket 2 Root bridge (Stack 4) + Device (PC16) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x10) + Method (_BBN, 0, NotSerialized) { + return (BB16) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR53) + } + If (LEqual(AP16, One)) { + Return (AH53) + } + Return (AR53) + } + + #include "PC16.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 4 on PC16 + Device (MCP4) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR54) + } + If (LEqual(AP16, One)) { + Return (AH54) + } + Return (AR54) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + } + + // Socket 2 Root bridge (Stack 5) + Device (PC17) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x11) + Method (_BBN, 0, NotSerialized) { + return (BB17) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR55) + } + If (LEqual(AP17, One)) { + Return (AH55) + } + Return (AR55) + } + + #include "PC17.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 5 on PC17 + Device (MCP5) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR56) + } + If (LEqual(AP17, One)) { + Return (AH56) + } + Return (AR56) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + } + + // Socket 3 Root bridge (Stack 0) + Device (PC18) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x12) + Method (_BBN, 0, NotSerialized) { + return (BB18) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR57) + } + If (LEqual(AP18, One)) { + Return (AH57) + } + Return (AR57) + } + + #include "PC18.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 0 on PC18 + Device (SRP0) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR58) + } + If (LEqual(AP18, One)) { + Return (AH58) + } + Return (AR58) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // CB3DMA on PC18 + Device (CB3B) { + Name (_ADR, 0x00040001) + } + + // CB3DMA on PC18 + Device (CB3C) { + Name (_ADR, 0x00040002) + } + + // CB3DMA on PC18 + Device (CB3D) { + Name (_ADR, 0x00040003) + } + + // CB3DMA on PC18 + Device (CB3E) { + Name (_ADR, 0x00040004) + } + + // CB3DMA on PC18 + Device (CB3F) { + Name (_ADR, 0x00040005) + } + + // CB3DMA on PC18 + Device (CB3G) { + Name (_ADR, 0x00040006) + } + + // CB3DMA on PC18 + Device (CB3H) { + Name (_ADR, 0x00040007) + } + + // IIOMISC on PC03 + Device (IIM3) { + Name (_ADR, 0x00050000) + } + + // Uncore 12 UBOX Device + Device (UBX3) { + Name (_ADR, 0x00080000) + } + + // CB3DMA on PC18 + Device (CB3A) { + Name (_ADR, 0x00040000) + } + } + + // Socket 3 Root bridge (Stack 1) + Device (PC19) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x13) + Method (_BBN, 0, NotSerialized) { + return (BB19) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR59) + } + If (LEqual(AP19, One)) { + Return (AH59) + } + Return (AR59) + } + + #include "PC19.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 1A on PC19 + Device (SR1A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5A) + } + If (LEqual(AP19, One)) { + Return (AH5A) + } + Return (AR5A) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 1B on PC19 + Device (SR1B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5B) + } + If (LEqual(AP19, One)) { + Return (AH5B) + } + Return (AR5B) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 1C on PC19 + Device (SR1C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5C) + } + If (LEqual(AP19, One)) { + Return (AH5C) + } + Return (AR5C) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 1D on PC19 + Device (SR1D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5D) + } + If (LEqual(AP19, One)) { + Return (AH5D) + } + Return (AR5D) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // Uncore 13 CHAUTIL0-7 Device + Device (CHD0) { + Name (_ADR, 0x00080000) + } + + // Uncore 13 CHAUTIL8-15 Device + Device (CHD1) { + Name (_ADR, 0x00090000) + } + + // Uncore 13 CHAUTIL16-23 Device + Device (CHD2) { + Name (_ADR, 0x000A0000) + } + + // Uncore 13 CHAUTIL24-27 Device + Device (CHD3) { + Name (_ADR, 0x000B0000) + } + + // Uncore 13 CHASAD0-7 Device + Device (CHD4) { + Name (_ADR, 0x000E0000) + } + + // Uncore 13 CHASAD8-15 Device + Device (CHD5) { + Name (_ADR, 0x000F0000) + } + + // Uncore 13 CHASAD16-23 Device + Device (CHD6) { + Name (_ADR, 0x00100000) + } + + // Uncore 13 CHASAD24-27 Device + Device (CHD7) { + Name (_ADR, 0x00110000) + } + + // Uncore 13 CMSCHA0-7 Device + Device (CM12) { + Name (_ADR, 0x00140000) + } + + // Uncore 13 CMS0CHA8-15 Device + Device (CM13) { + Name (_ADR, 0x00150000) + } + + // Uncore 13 CMS0CHA16-23 Device + Device (CM14) { + Name (_ADR, 0x00160000) + } + + // Uncore 13 CMS0CHA24-27 Device + Device (CM15) { + Name (_ADR, 0x00170000) + } + + // Uncore 13 CHASADALL Device + Device (CDL3) { + Name (_ADR, 0x001D0000) + } + + // Uncore 13 PCUCR Devices + Device (PCU3) { + Name (_ADR, 0x001E0000) + } + + // Uncore 13 VCUCR Device + Device (VCU3) { + Name (_ADR, 0x001F0000) + } + } + + // Socket 3 Root bridge (Stack 2) + Device (PC20) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x14) + Method (_BBN, 0, NotSerialized) { + return (BB20) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5E) + } + If (LEqual(AP20, One)) { + Return (AH5E) + } + Return (AR5E) + } + + #include "PC20.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 2A on PC20 + Device (SR2A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5F) + } + If (LEqual(AP20, One)) { + Return (AH5F) + } + Return (AR5F) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 2B on PC20 + Device (SR2B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR60) + } + If (LEqual(AP20, One)) { + Return (AH60) + } + Return (AR60) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 2C on PC20 + Device (SR2C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR61) + } + If (LEqual(AP20, One)) { + Return (AH61) + } + Return (AR61) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 2D on PC20 + Device (SR2D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR62) + } + If (LEqual(AP20, One)) { + Return (AH62) + } + Return (AR62) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // Uncore 14 M2MEM0 Device + Device (M2M6) { + Name (_ADR, 0x00080000) + } + + // Uncore 14 M2MEM10 Device + Device (M2M7) { + Name (_ADR, 0x00090000) + } + + // Uncore 14 MCMAIN Device + Device (MCM6) { + Name (_ADR, 0x000A0000) + } + + // Uncore 14 MCDECS2 Device + Device (MCD6) { + Name (_ADR, 0x000B0000) + } + + // Uncore 14 MCMAIN Device + Device (MCM7) { + Name (_ADR, 0x000C0000) + } + + // Uncore 14 MCDECS12 Device + Device (MCD7) { + Name (_ADR, 0x000D0000) + } + + // Uncore 14 Unicast MC0 DDRIO0 Device + Device (UMC6) { + Name (_ADR, 0x00160000) + } + + // Uncore 14 Unicast MC1 DDRIO0 Device + Device (UMC7) { + Name (_ADR, 0x00170000) + } + } + + // Socket 3 Root bridge (Stack 3) + Device (PC21) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x15) + Method (_BBN, 0, NotSerialized) { + return (BB21) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR63) + } + If (LEqual(AP21, One)) { + Return (AH63) + } + Return (AR63) + } + + #include "PC21.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 3A on PC21 + Device (SR3A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR64) + } + If (LEqual(AP21, One)) { + Return (AH64) + } + Return (AR64) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 3B on PC21 + Device (SR3B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR65) + } + If (LEqual(AP21, One)) { + Return (AH65) + } + Return (AR65) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 3C on PC21 + Device (SR3C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR66) + } + If (LEqual(AP21, One)) { + Return (AH66) + } + Return (AR66) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 3D on PC21 + Device (SR3D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR67) + } + If (LEqual(AP21, One)) { + Return (AH67) + } + Return (AR67) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // Uncore 15 KTI9 + Device (KTI9) { + Name (_ADR, 0x000E0000) + } + + // Uncore 15 KT10 + Device (KT10) { + Name (_ADR, 0x000F0000) + } + + // Uncore 15 KT11 + Device (KT11) { + Name (_ADR, 0x00100000) + } + + // Uncore 15 M3K3 + Device (M3K3) { + Name (_ADR, 0x00120000) + } + + // Uncore 15 M2U3 + Device (M2U3) { + Name (_ADR, 0x00150000) + } + + // Uncore 15 M2D3 + Device (M2D3) { + Name (_ADR, 0x00160000) + } + + // Uncore 15 M23 + Device (M23) { + Name (_ADR, 0x00170000) + } + } + + // Socket 3 Root bridge (Stack 4) + Device (PC22) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x16) + Method (_BBN, 0, NotSerialized) { + return (BB22) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR68) + } + If (LEqual(AP22, One)) { + Return (AH68) + } + Return (AR68) + } + + #include "PC22.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 4 on PC22 + Device (MCP6) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR69) + } + If (LEqual(AP22, One)) { + Return (AH69) + } + Return (AR69) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + } + + // Socket 3 Root bridge (Stack 5) + Device (PC23) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x17) + Method (_BBN, 0, NotSerialized) { + return (BB23) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR6A) + } + If (LEqual(AP23, One)) { + Return (AH6A) + } + Return (AR6A) + } + + #include "PC23.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 5 on PC23 + Device (MCP7) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR6B) + } + If (LEqual(AP23, One)) { + Return (AH6B) + } + Return (AR6B) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + + } + } +} + +Scope (\_GPE) { + // [BR1A]: PCI Express Port 1A on PC01 + // [BR1B]: PCI Express Port 1B on PC01 + // [BR1C]: PCI Express Port 1C on PC01 + // [BR1D]: PCI Express Port 1D on PC01 + // [BR2A]: PCI Express Port 2A on PC02 + // [BR2B]: PCI Express Port 2B on PC02 + // [BR2C]: PCI Express Port 2C on PC02 + // [BR2D]: PCI Express Port 2D on PC02 + // [BR3A]: PCI Express Port 3A on PC03 + // [BR3B]: PCI Express Port 3B on PC03 + // [BR3C]: PCI Express Port 3C on PC03 + // [BR3D]: PCI Express Port 3D on PC03 + // [MCP0]: PCI Express Port 4 on PC04 + // [MCP1]: PCI Express Port 5 on PC05 + // [QRP0]: PCI Express Port 0 on PC06 + // [QR1A]: PCI Express Port 1A on PC07 + // [QR1B]: PCI Express Port 1B on PC07 + // [QR1C]: PCI Express Port 1C on PC07 + // [QR1D]: PCI Express Port 1D on PC07 + // [QR2A]: PCI Express Port 2A on PC08 + // [QR2B]: PCI Express Port 2B on PC08 + // [QR2C]: PCI Express Port 2C on PC08 + // [QR2D]: PCI Express Port 2D on PC08 + // [QR3A]: PCI Express Port 3A on PC09 + // [QR3B]: PCI Express Port 3B on PC09 + // [QR3C]: PCI Express Port 3C on PC09 + // [QR3D]: PCI Express Port 3D on PC09 + // [MCP2]: PCI Express Port 13 on PC10 + // [MCP3]: PCI Express Port 14 on PC11 + // [RRP0]: PCI Express Port 0 on PC12 + // [RR1A]: PCI Express Port 1A on PC13 + // [RR1B]: PCI Express Port 1B on PC13 + // [RR1C]: PCI Express Port 1C on PC13 + // [RR1D]: PCI Express Port 1D on PC13 + // [RR2A]: PCI Express Port 2A on PC14 + // [RR2B]: PCI Express Port 2B on PC14 + // [RR2C]: PCI Express Port 2C on PC14 + // [RR2D]: PCI Express Port 2D on PC14 + // [RR3A]: PCI Express Port 3A on PC15 + // [RR3B]: PCI Express Port 3B on PC15 + // [RR3C]: PCI Express Port 3C on PC15 + // [RR3D]: PCI Express Port 3D on PC15 + // [MCP4]: PCI Express Port 4 on PC16 + // [MCP5]: PCI Express Port 5 on PC17 + // [SRP0]: PCI Express Port 0 on PC18 + // [SR1A]: PCI Express Port 1A on PC19 + // [SR1B]: PCI Express Port 1B on PC19 + // [SR1C]: PCI Express Port 1C on PC19 + // [SR1D]: PCI Express Port 1D on PC19 + // [SR2A]: PCI Express Port 2A on PC20 + // [SR2B]: PCI Express Port 2B on PC20 + // [SR2C]: PCI Express Port 2C on PC20 + // [SR2D]: PCI Express Port 2D on PC20 + // [SR3A]: PCI Express Port 3A on PC21 + // [SR3B]: PCI Express Port 3B on PC21 + // [SR3C]: PCI Express Port 3C on PC21 + // [SR3D]: PCI Express Port 3D on PC21 + // [MCP6]: PCI Express Port 4 on PC22 + // [MCP7]: PCI Express Port 5 on PC23 + Method (_L09, 0x0, NotSerialized) { + #include "Gpe.asl" + Notify (\_SB.PC01.BR1A, 0x02) + Notify (\_SB.PC01.BR1B, 0x02) + Notify (\_SB.PC01.BR1C, 0x02) + Notify (\_SB.PC01.BR1D, 0x02) + Notify (\_SB.PC02.BR2A, 0x02) + Notify (\_SB.PC02.BR2B, 0x02) + Notify (\_SB.PC02.BR2C, 0x02) + Notify (\_SB.PC02.BR2D, 0x02) + Notify (\_SB.PC03.BR3A, 0x02) + Notify (\_SB.PC03.BR3B, 0x02) + Notify (\_SB.PC03.BR3C, 0x02) + Notify (\_SB.PC03.BR3D, 0x02) + Notify (\_SB.PC04.MCP0, 0x02) + Notify (\_SB.PC05.MCP1, 0x02) + Notify (\_SB.PC06.QRP0, 0x02) + Notify (\_SB.PC07.QR1A, 0x02) + Notify (\_SB.PC07.QR1B, 0x02) + Notify (\_SB.PC07.QR1C, 0x02) + Notify (\_SB.PC07.QR1D, 0x02) + Notify (\_SB.PC08.QR2A, 0x02) + Notify (\_SB.PC08.QR2B, 0x02) + Notify (\_SB.PC08.QR2C, 0x02) + Notify (\_SB.PC08.QR2D, 0x02) + Notify (\_SB.PC09.QR3A, 0x02) + Notify (\_SB.PC09.QR3B, 0x02) + Notify (\_SB.PC09.QR3C, 0x02) + Notify (\_SB.PC09.QR3D, 0x02) + Notify (\_SB.PC10.MCP2, 0x02) + Notify (\_SB.PC11.MCP3, 0x02) + Notify (\_SB.PC12.RRP0, 0x02) + Notify (\_SB.PC13.RR1A, 0x02) + Notify (\_SB.PC13.RR1B, 0x02) + Notify (\_SB.PC13.RR1C, 0x02) + Notify (\_SB.PC13.RR1D, 0x02) + Notify (\_SB.PC14.RR2A, 0x02) + Notify (\_SB.PC14.RR2B, 0x02) + Notify (\_SB.PC14.RR2C, 0x02) + Notify (\_SB.PC14.RR2D, 0x02) + Notify (\_SB.PC15.RR3A, 0x02) + Notify (\_SB.PC15.RR3B, 0x02) + Notify (\_SB.PC15.RR3C, 0x02) + Notify (\_SB.PC15.RR3D, 0x02) + Notify (\_SB.PC16.MCP4, 0x02) + Notify (\_SB.PC17.MCP5, 0x02) + Notify (\_SB.PC18.SRP0, 0x02) + Notify (\_SB.PC19.SR1A, 0x02) + Notify (\_SB.PC19.SR1B, 0x02) + Notify (\_SB.PC19.SR1C, 0x02) + Notify (\_SB.PC19.SR1D, 0x02) + Notify (\_SB.PC20.SR2A, 0x02) + Notify (\_SB.PC20.SR2B, 0x02) + Notify (\_SB.PC20.SR2C, 0x02) + Notify (\_SB.PC20.SR2D, 0x02) + Notify (\_SB.PC21.SR3A, 0x02) + Notify (\_SB.PC21.SR3B, 0x02) + Notify (\_SB.PC21.SR3C, 0x02) + Notify (\_SB.PC21.SR3D, 0x02) + Notify (\_SB.PC22.MCP6, 0x02) + Notify (\_SB.PC23.MCP7, 0x02) + } + + // [EPCU]: EVA PCIe Uplink + // [VSP0]: EVA Virtual Switch Port 0 + // [VSP1]: EVA Virtual Switch Port 1 + // [VSP2]: EVA Virtual Switch Port 2 + // [VSP3]: EVA Virtual Switch Port 3 + Method (_L0B, 0x0, NotSerialized) { + Notify (\_SB.PC02.BR2A.EPCU, 0x02) + Notify (\_SB.PC02.BR2A.EPCU.VSP0, 0x02) + Notify (\_SB.PC02.BR2A.EPCU.VSP1, 0x02) + Notify (\_SB.PC02.BR2A.EPCU.VSP2, 0x02) + Notify (\_SB.PC02.BR2A.EPCU.VSP3, 0x02) + } + +} + --=20 2.27.0.windows.1 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Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726546; bh=9FbDqByiCGX7zgFqmPEidFn8eq+epsPt/T9xLLcsHXo=; h=Cc:Date:From:Reply-To:Subject:To; b=A9Fd4l+p8LhzDD+cZMBMCvdjrLtxYeipt0FPuq4rBewy3HVoiz1Q6C96MBSZ3NnObY/ DSyAlM1PXNsiETPACumTQFXCl0KyMXe/NWOou/ax9L4nZBGIhi/Q2cjYRjGkPdO1jxO4Q GXKNWHl16JLcQOgOL9KaXwn4eq2rZzhn/MY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../Acpi/BoardAcpiDxe/Dsdt/PC00.asi | 385 ++++++++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC01.asi | 255 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC02.asi | 255 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC03.asi | 260 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC04.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC05.asi | 233 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC06.asi | 328 +++++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi | 9 + .../Acpi/BoardAcpiDxe/Dsdt/PC07.asi | 259 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC08.asi | 262 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC09.asi | 260 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC10.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC11.asi | 231 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC12.asi | 324 +++++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi | 9 + .../Acpi/BoardAcpiDxe/Dsdt/PC13.asi | 256 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC14.asi | 259 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC15.asi | 259 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC16.asi | 231 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC17.asi | 231 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC18.asi | 342 ++++++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi | 9 + .../Acpi/BoardAcpiDxe/Dsdt/PC19.asi | 259 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC20.asi | 260 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC21.asi | 260 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC22.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC23.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC24.asi | 231 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC25.asi | 259 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC26.asi | 259 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC27.asi | 259 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC28.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC29.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC30.asi | 256 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC31.asi | 259 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC32.asi | 260 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC33.asi | 260 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC34.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC35.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC36.asi | 257 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC37.asi | 259 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC38.asi | 260 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC39.asi | 260 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC40.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC41.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC42.asi | 290 +++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC43.asi | 259 ++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC44.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC45.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC46.asi | 232 +++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PC47.asi | 232 +++++++++++ 51 files changed, 12312 insertions(+) create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC00.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC01.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC02.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC03.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC04.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC05.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC06.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC06Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC07.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC08.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC09.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC10.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC11.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC12.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC12Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC13.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC14.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC15.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC16.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC17.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC18.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC18Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC19.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC20.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC21.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC22.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC23.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC24.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC25.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC26.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC27.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC28.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC29.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC30.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC31.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC32.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC33.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC34.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC35.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC36.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC37.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC38.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC39.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC40.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC41.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC42.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC43.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC44.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC45.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC46.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PC47.asi diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC00.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC00.asi new file mode 100644 index 0000000000..aaf1237835 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC00.asi @@ -0,0 +1,385 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + // + // Set this root port to use the correct Proximity Domain + // + Name(_PXM, 0) + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + +#include "Pch.asi" +#include "PchApic.asi" + + +#define RESOURCE_CHUNK1_OFF 0 +#define RESOURCE_CHUNK2_OFF 16 //(RESOURCE_CHUNK1_OFF + 16) +#define RESOURCE_CHUNK3_OFF 24 //(RESOURCE_CHUNK2_OFF + 8) +#define RESOURCE_CHUNK4_OFF 40 //(RESOURCE_CHUNK3_OFF + 16) +#define RESOURCE_CHUNK5_OFF 56 //(RESOURCE_CHUNK4_OFF + 16) +#define RESOURCE_CHUNK6_OFF 82 //(RESOURCE_CHUNK5_OFF + 26) +#define RESOURCE_CHUNK7_OFF 108 //(RESOURCE_CHUNK6_OFF + 26) + +#define PciResourceStart Local0 +#define PciResourceLen Local1 + + Name(P0RS, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( // Bus number resource (0); the bridge produ= ces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + IO( // Consumed resource (CF8-CFF) + Decode16, + 0x0cf8, + 0xcf8, + 1, + 8 + ) + + //RESOURCE_CHUNK3_OFF + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0000, // Min + 0x0cf7, // Max + 0x0000, // Translation + 0x0cf8 // Range Length + ) + + //RESOURCE_CHUNK4_OFF + WORDIO( // Consumed-and-produced resource (all I/O a= bove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Plat= form Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Plat= form Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Plat= form Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length (FIX2 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // Descriptor Name + ) + + //RESOURCE_CHUNK6_OFF + DWORDMEMORY( // descriptor for Shadow RAM + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Min (calculated dynamically) + 0x00000000, // Max (calculated dynamically) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) + , + , + SRAM // DescriptorName populated so iASL doesn't = flag 0 value fields and no tag as error + ) +/* + //RESOURCE_TPM + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity + 0xFED40000, // Min (calculated dynamically) + 0xFEDFFFFF, // Max =3D 4GB - 1MB (fwh + fwh alias...) + 0x00000000, // Translation + 0x000C0000 // Range Length (calculated dynamically) + ) +*/ + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, + ReadWrite,0x00,0xFE010000,0xFE010FFF,0x00,0x1000) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of P0RS Buffer + + OperationRegion(TMEM, PCI_Config, 0x00, 0x100) + Field(TMEM, ByteAcc, NoLock, Preserve) { + Offset(0x40), + , 4, + BSEG, 4, + PAMS, 48, + Offset(0x52), + DIM0, 4, + DIM1, 4, + , 8, + DIM2, 4, + } + + Name(MTBL, Package(0x10) { + 0x0, + 0x20, + 0x20, + 0x30, + 0x40, + 0x40, + 0x60, + 0x80, + 0x80, + 0x80, + 0x80, + 0xc0, + 0x100, + 0x100, + 0x100, + 0x200 + }) + + Name(ERNG, Package(0xd) { + 0xc0000, + 0xc4000, + 0xc8000, + 0xcc000, + 0xd0000, + 0xd4000, + 0xd8000, + 0xdc000, + 0xe0000, + 0xe4000, + 0xe8000, + 0xec000, + 0xf0000 + }) + + Name(PAMB, Buffer(0x7) { + }) + + Method(EROM, 0x0, NotSerialized) { + CreateDWordField(P0RS, ^SRAM._MIN, RMIN) // Do not reference hard-code= d address + CreateDWordField(P0RS, ^SRAM._MAX, RMAX) // Do not reference hard-code= d address + CreateDWordField(P0RS, ^SRAM._LEN, RLEN) // Do not reference hard-code= d address + CreateByteField(PAMB, 0x6, BREG) + Store(PAMS, PAMB) + Store(BSEG, BREG) + Store(0x0, RMIN) + Store(0x0, RMAX) + Store(0x0, RLEN) + Store(0x0, Local0) + While(LLess(Local0, 0xd)) + { + ShiftRight(Local0, 0x1, Local1) + Store(DerefOf(Index(PAMB, Local1, )), Local2) + If(And(Local0, 0x1, )) + { + ShiftRight(Local2, 0x4, Local2) + } + And(Local2, 0x3, Local2) + If(RMIN) + { + If(Local2) + { + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX) + If(LEqual(RMAX, 0xf3fff)) + { + Store(0xfffff, RMAX) + } + Subtract(RMAX, RMIN, RLEN) + Increment(RLEN) + } + Else + { + Store(0xc, Local0) + } + } + Else + { + If(Local2) + { + Store(DerefOf(Index(ERNG, Local0, )), RMIN) + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX) + If(LEqual(RMAX, 0xf3fff)) + { + Store(0xfffff, RMAX) + } + Subtract(RMAX, RMIN, RLEN) + Increment(RLEN) + } + Else + { + } + } + Increment(Local0) + } + } + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + EROM() + Return(P0RS) + } + + // + // Memory Riser UID will be in Interger form to support CPU Migration. + // First two digits will indicate Memory Device(01) and last two + // digits will represent the Memory Riser number. + // + Device (MHP0) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "00-00") + + // MHP0 - Config register for Slot status + OperationRegion(MHP0, PCI_Config, 0x00, 0x100) + Field(MHP0,ByteAcc,NoLock,Preserve) { + Offset(0x0E), + STM0,7, + } + } + + Device (MHP1) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "00-01") + + // MHP1 - Config register for Slot status + OperationRegion(MHP1, PCI_Config, 0x00, 0x100) + Field(MHP1,ByteAcc,NoLock,Preserve) { + Offset(0x1E), + STM1,7, + } + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC01.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC01.asi new file mode 100644 index 0000000000..1e61aac3f6 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC01.asi @@ -0,0 +1,255 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + // + // Set this root port to use the correct Proximity Domain + // + Name(_PXM, 0) + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + Store (0xE3, IO80) + \_SB.PC01.BR1A.OSHP () + \_SB.PC01.BR1B.OSHP () + \_SB.PC01.BR1C.OSHP () + \_SB.PC01.BR1D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 0, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Shift for IIO Stack 1 + ShiftRight(IIOH, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR01, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR01 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR01) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC02.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC02.asi new file mode 100644 index 0000000000..65035cf70e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC02.asi @@ -0,0 +1,255 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + // + // Set this root port to use the correct Proximity Domain + // + Name(_PXM, 0) + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC02.BR2A.OSHP () + \_SB.PC02.BR2B.OSHP () + \_SB.PC02.BR2C.OSHP () + \_SB.PC02.BR2D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 0, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Shift for IIO Stack 2 + ShiftRight(IIOH, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR02, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR02 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR02) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC03.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC03.asi new file mode 100644 index 0000000000..c1af96c1b7 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC03.asi @@ -0,0 +1,260 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + // + // Set this root port to use the correct Proximity Domain + // + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(0) + } else { + Return(1) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC03.BR3A.OSHP () + \_SB.PC03.BR3B.OSHP () + \_SB.PC03.BR3C.OSHP () + \_SB.PC03.BR3D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 0, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Shift for IIO Stack 3 + ShiftRight(IIOH, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR03, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR03 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR03) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC04.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC04.asi new file mode 100644 index 0000000000..f73f55d60f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC04.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + // + // Set this root port to use the correct Proximity Domain + // + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(0) + } else { + Return(1) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 0, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Shift for IIO Stack 4 + ShiftRight(IIOH, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR04, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR04 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR04) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC05.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC05.asi new file mode 100644 index 0000000000..7334dc56f1 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC05.asi @@ -0,0 +1,233 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + // + // Set this root port to use the correct Proximity Domain + // + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(0) + } else { + Return(1) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 0, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Shift for IIO Stack 5 + ShiftRight(IIOH, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR05, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR05 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR05) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06.asi new file mode 100644 index 0000000000..c4ddd10612 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06.asi @@ -0,0 +1,328 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(2) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC06.QRP0.OSHP () + + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + // owning control method can't be reentrant, so _DSM must be Serialized + Method (_DSM, 4, Serialized) { // Device specific method + if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){ + Switch(ToInteger(Arg2)) { + case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 sup= ported + case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x31, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/= O Hub n + + case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x31, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O= Hub n + case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x31, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O= Hub n=20 + Default { } + } + } + Return (Buffer() {0}) + } + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA +/* TODO: ifdef does not work here, need to enable this code after PPO + // All PCI-Ex ports are dependent on IIOx stack + Name(_EDL, Package() { + \_SB.PC06.QRP0, \_SB.PC07.QR1A, \_SB.PC07.QR1B, \_SB.PC07.QR1C, \_SB.P= C07.QR1D,=20 + \_SB.PC08.QR2A, \_SB.PC08.QR2B, \_SB.PC08.QR2C, \_SB.PC08.QR2D,=20 + \_SB.PC09.QR3A, \_SB.PC09.QR3B, \_SB.PC09.QR3C, \_SB.PC09.QR3D + }) +*/ + Name(PR06, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR06 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR06) + } + + // + // Memory Riser UID will be in Interger form to support CPU Migration. + // First two digits will indicate Memory Device(01) and last two + // digits will represent the Memory Riser number. + // + Device (MHP0) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "01-00") + + // MHP0 - Config register for Slot status + OperationRegion(MHP0, PCI_Config, 0xE, 2) + Field(MHP0,ByteAcc,NoLock,Preserve) { + STM2,7, + } + } + + Device (MHP1) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "01-01") + + // MHP1 - Config register for Slot status + OperationRegion(MHP1, PCI_Config, 0x1E, 2) + Field(MHP1,ByteAcc,NoLock,Preserve) { + STM3,7, + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06E= jd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.a= si new file mode 100644 index 0000000000..bd53705140 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi @@ -0,0 +1,9 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // Eject device if PC06 is removed. + Name(_EJD,"\\_SB.PC06") // Dependent on PC06 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC07.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC07.asi new file mode 100644 index 0000000000..c2011b6ed2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC07.asi @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(2) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC07.QR1A.OSHP () + \_SB.PC07.QR1B.OSHP () + \_SB.PC07.QR1C.OSHP () + \_SB.PC07.QR1D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR07, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR07 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR07) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC08.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC08.asi new file mode 100644 index 0000000000..373575105a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC08.asi @@ -0,0 +1,262 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(2) + } + } + +// +// Moving _OSC method to respective stack PCXX.asi. +// + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC08.QR2A.OSHP () + \_SB.PC08.QR2B.OSHP () + \_SB.PC08.QR2C.OSHP () + \_SB.PC08.QR2D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR08, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR08 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR08) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC09.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC09.asi new file mode 100644 index 0000000000..4908507c19 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC09.asi @@ -0,0 +1,260 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(3) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC09.QR3A.OSHP () + \_SB.PC09.QR3B.OSHP () + \_SB.PC09.QR3C.OSHP () + \_SB.PC09.QR3D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR09, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR09 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR09) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC10.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC10.asi new file mode 100644 index 0000000000..274280715c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC10.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(3) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR10, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR10 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR10) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC11.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC11.asi new file mode 100644 index 0000000000..a3fcda98e0 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC11.asi @@ -0,0 +1,231 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(3) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR11, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR11 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR11) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12.asi new file mode 100644 index 0000000000..8d0ea8c4b2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12.asi @@ -0,0 +1,324 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(4) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC12.RRP0.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + // owning control method can't be reentrant, so _DSM must be Serialized + Method (_DSM, 4, Serialized) { // Device specific method + if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){ + Switch(ToInteger(Arg2)) { + case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 sup= ported + case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x32, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/= O Hub n + + case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x32, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O= Hub n + case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x32, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O= Hub n=20 + Default { } + } + } + Return (Buffer() {0}) + } + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA +/* TODO: ifdef does not work here, need to enable this code after PPO + // All PCI-Ex ports are dependent on IIO2 + Name(_EDL, Package() { + \_SB.PC12.RRP0, \_SB.PC13.RR1A, \_SB.PC13.RR1B, \_SB.PC13.RR1C, \_SB.P= C13.RR1D, + \_SB.PC14.RR2A, \_SB.PC14.RR2B, \_SB.PC14.RR2C, \_SB.PC14.RR2D,=20 + \_SB.PC15.RR3A, \_SB.PC15.RR3B, \_SB.PC15.RR3C, \_SB.PC15.RR3D + }) +*/ + Name(PR12, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR12 Buffer + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR12) + } + + // + // Memory Riser UID will be in Interger form to support CPU Migration. + // First two digits will indicate Memory Device(01) and last two + // digits will represent the Memory Riser number. + // + Device (MHP0) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "02-00") + + // MHP0 - Config register for Slot status + OperationRegion(MHP0, PCI_Config, 0xE, 2) + Field(MHP0,ByteAcc,NoLock,Preserve) { + STM4,7, + } + } + + Device (MHP1) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "02-01") + + // MHP1 - Config register for Slot status + OperationRegion(MHP1, PCI_Config, 0x1E, 2) + Field(MHP1,ByteAcc,NoLock,Preserve) { + STM5,7, + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12E= jd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.a= si new file mode 100644 index 0000000000..6969f3f503 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi @@ -0,0 +1,9 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // Eject device if PC12 is removed. + Name(_EJD,"\\_SB.PC12") // Dependent on PC12 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC13.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC13.asi new file mode 100644 index 0000000000..f53903cad1 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC13.asi @@ -0,0 +1,256 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(4) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC13.RR1A.OSHP () + \_SB.PC13.RR1B.OSHP () + \_SB.PC13.RR1C.OSHP () + \_SB.PC13.RR1D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR13, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR13 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR13) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC14.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC14.asi new file mode 100644 index 0000000000..6eee61de72 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC14.asi @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(4) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + //Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC14.RR2A.OSHP () + \_SB.PC14.RR2B.OSHP () + \_SB.PC14.RR2C.OSHP () + \_SB.PC14.RR2D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR14, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR14 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR14) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC15.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC15.asi new file mode 100644 index 0000000000..b9b0349d34 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC15.asi @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(5) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC15.RR3A.OSHP () + \_SB.PC15.RR3B.OSHP () + \_SB.PC15.RR3C.OSHP () + \_SB.PC15.RR3D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR15, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR15 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR15) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC16.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC16.asi new file mode 100644 index 0000000000..6d288be750 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC16.asi @@ -0,0 +1,231 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(5) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR16, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR16 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR16) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC17.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC17.asi new file mode 100644 index 0000000000..ecee6b9937 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC17.asi @@ -0,0 +1,231 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(5) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR17, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR17 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR17) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18.asi new file mode 100644 index 0000000000..bf8ad0ca3a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18.asi @@ -0,0 +1,342 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(6) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC18.SRP0.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + // owning control method can't be reentrant, so _DSM must be Serialized + Method (_DSM, 4, Serialized) { // Device specific method + if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){ + Switch(ToInteger(Arg2)) { + case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 sup= ported + case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/= O Hub n + + case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O= Hub n + case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O= Hub n=20 + Default { } + } + } + Return (Buffer() {0}) + } + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA +/* TODO: ifdef does not work here, need to enable this code after PPO + // All PCI-Ex ports are dependent on IIO3 + Name(_EDL, Package() { + \_SB.PC18.SRP0, \_SB.PC19.SR1A, \_SB.PC19.SR1B, \_SB.PC19.SR1C, \_SB.P= C19.SR1D,=20 + \_SB.PC20.SR2A, \_SB.PC20.SR2B, \_SB.PC20.SR2C, \_SB.PC20.SR2D,=20 + \_SB.PC21.SR3A, \_SB.PC21.SR3B, \_SB.PC21.SR3C, \_SB.PC21.SR3D + }) + + Method(_EJ0, 1) { + Notify(\_SB.PC18.SRP0, Arg0) + Notify(\_SB.PC19.SR1A, Arg0) + Notify(\_SB.PC19.SR1B, Arg0) + Notify(\_SB.PC19.SR1C, Arg0) + Notify(\_SB.PC19.SR1D, Arg0) + Notify(\_SB.PC20.SR2A, Arg0) + Notify(\_SB.PC20.SR2B, Arg0) + Notify(\_SB.PC20.SR2C, Arg0) + Notify(\_SB.PC20.SR2D, Arg0) + Notify(\_SB.PC21.SR3A, Arg0) + Notify(\_SB.PC21.SR3B, Arg0) + Notify(\_SB.PC21.SR3C, Arg0) + Notify(\_SB.PC21.SR3D, Arg0) + \_SB.GSMI(3, 3) //EVENT_IIO_HP, IIO ID + } +*/ + Name(PR18, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIXH - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR18 Buffer + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR18) + } + + // + // Memory Riser UID will be in Interger form to support CPU Migration. + // First two digits will indicate Memory Device(01) and last two + // digits will represent the Memory Riser number. + // + Device (MHP0) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "03-00") + + // MHP0 - Config register for Slot status + OperationRegion(MHP0, PCI_Config, 0xE, 2) + Field(MHP0,ByteAcc,NoLock,Preserve) { + STM6,7, + } + } + + Device (MHP1) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "03-01") + + // MHP1 - Config register for Slot status + OperationRegion(MHP1, PCI_Config, 0x1E, 2) + Field(MHP1,ByteAcc,NoLock,Preserve) { + STM7,7, + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18E= jd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.a= si new file mode 100644 index 0000000000..466163cacc --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi @@ -0,0 +1,9 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // Eject device if PC18 is removed. + Name(_EJD,"\\_SB.PC18") // Dependent on PC18 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC19.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC19.asi new file mode 100644 index 0000000000..d54e11fc64 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC19.asi @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(6) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC19.SR1A.OSHP () + \_SB.PC19.SR1B.OSHP () + \_SB.PC19.SR1C.OSHP () + \_SB.PC19.SR1D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR19, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR19 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR19) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC20.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC20.asi new file mode 100644 index 0000000000..6a3c340378 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC20.asi @@ -0,0 +1,260 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(6) + } + } + + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC20.SR2A.OSHP () + \_SB.PC20.SR2B.OSHP () + \_SB.PC20.SR2C.OSHP () + \_SB.PC20.SR2D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR20, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR20 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR20) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC21.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC21.asi new file mode 100644 index 0000000000..b4600b9476 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC21.asi @@ -0,0 +1,260 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(7) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC21.SR3A.OSHP () + \_SB.PC21.SR3B.OSHP () + \_SB.PC21.SR3C.OSHP () + \_SB.PC21.SR3D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR21, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR21 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR21) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC22.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC22.asi new file mode 100644 index 0000000000..aaf798453e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC22.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(7) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR22, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR22 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR22) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC23.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC23.asi new file mode 100644 index 0000000000..8d4ff618cb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC23.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(7) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR23, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR23 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR23) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC24.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC24.asi new file mode 100644 index 0000000000..e62913a7cf --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC24.asi @@ -0,0 +1,231 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(8) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR24, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR24 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR24) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC25.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC25.asi new file mode 100644 index 0000000000..43779e6b56 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC25.asi @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(8) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC25.CR1A.OSHP () + \_SB.PC25.CR1B.OSHP () + \_SB.PC25.CR1C.OSHP () + \_SB.PC25.CR1D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR25, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR25 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR25) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC26.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC26.asi new file mode 100644 index 0000000000..28a6784e0e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC26.asi @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(8) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC26.CR2A.OSHP () + \_SB.PC26.CR2B.OSHP () + \_SB.PC26.CR2C.OSHP () + \_SB.PC26.CR2D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR26, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR26 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR26) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC27.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC27.asi new file mode 100644 index 0000000000..c6657242a4 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC27.asi @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(9) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC27.CR3A.OSHP () + \_SB.PC27.CR3B.OSHP () + \_SB.PC27.CR3C.OSHP () + \_SB.PC27.CR3D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR27, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR27 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR27) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC28.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC28.asi new file mode 100644 index 0000000000..1d5a489cd2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC28.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(9) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR28, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR28 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR28) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC29.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC29.asi new file mode 100644 index 0000000000..3678f10cc0 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC29.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(9) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR29, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR29 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR29) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC30.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC30.asi new file mode 100644 index 0000000000..d0bec9972d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC30.asi @@ -0,0 +1,256 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(10) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC30.TRP0.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR30, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR30 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR30) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC31.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC31.asi new file mode 100644 index 0000000000..e141868896 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC31.asi @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(10) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC31.TR1A.OSHP () + \_SB.PC31.TR1B.OSHP () + \_SB.PC31.TR1C.OSHP () + \_SB.PC31.TR1D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR31, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR31 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR31) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC32.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC32.asi new file mode 100644 index 0000000000..6b16fb096e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC32.asi @@ -0,0 +1,260 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(10) + } + } + + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC32.TR2A.OSHP () + \_SB.PC32.TR2B.OSHP () + \_SB.PC32.TR2C.OSHP () + \_SB.PC32.TR2D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR32, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR32 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR32) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC33.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC33.asi new file mode 100644 index 0000000000..1b4566d4f5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC33.asi @@ -0,0 +1,260 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(11) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC33.TR3A.OSHP () + \_SB.PC33.TR3B.OSHP () + \_SB.PC33.TR3C.OSHP () + \_SB.PC33.TR3D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR33, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR33 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR33) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC34.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC34.asi new file mode 100644 index 0000000000..fa58f4e60c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC34.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(11) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR34, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR34 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR34) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC35.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC35.asi new file mode 100644 index 0000000000..e0bbe6adf2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC35.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(11) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR35, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR35 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR35) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC36.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC36.asi new file mode 100644 index 0000000000..a3d906aafd --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC36.asi @@ -0,0 +1,257 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(12) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC36.URP0.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR36, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR36 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR36) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC37.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC37.asi new file mode 100644 index 0000000000..8cd169311c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC37.asi @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(12) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC37.UR1A.OSHP () + \_SB.PC37.UR1B.OSHP () + \_SB.PC37.UR1C.OSHP () + \_SB.PC37.UR1D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR37, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR37 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR37) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC38.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC38.asi new file mode 100644 index 0000000000..d0d766954d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC38.asi @@ -0,0 +1,260 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(12) + } + } + + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC38.UR2A.OSHP () + \_SB.PC38.UR2B.OSHP () + \_SB.PC38.UR2C.OSHP () + \_SB.PC38.UR2D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR38, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR38 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR38) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC39.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC39.asi new file mode 100644 index 0000000000..5c37da53ec --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC39.asi @@ -0,0 +1,260 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(13) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC39.UR3A.OSHP () + \_SB.PC39.UR3B.OSHP () + \_SB.PC39.UR3C.OSHP () + \_SB.PC39.UR3D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR39, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR39 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR39) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC40.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC40.asi new file mode 100644 index 0000000000..d16d46b466 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC40.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(13) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR40, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR40 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR40) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC41.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC41.asi new file mode 100644 index 0000000000..73dd6567fc --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC41.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(13) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR41, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR41 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR41) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC42.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC42.asi new file mode 100644 index 0000000000..7efc2854dc --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC42.asi @@ -0,0 +1,290 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(14) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC42.VRP0.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + // owning control method can't be reentrant, so _DSM must be Serialized + Method (_DSM, 4, Serialized) { // Device specific method + if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){ + Switch(ToInteger(Arg2)) { + case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 sup= ported + case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/= O Hub n + + case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O= Hub n + case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,=20 + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00= ,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O= Hub n=20 + Default { } + } + } + Return (Buffer() {0}) + } + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR42, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR42 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR42) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC43.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC43.asi new file mode 100644 index 0000000000..c3a9e250a6 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC43.asi @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(14) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions n= ot met? =20 + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC43.VR1A.OSHP () + \_SB.PC43.VR1B.OSHP () + \_SB.PC43.VR1C.OSHP () + \_SB.PC43.VR1D.OSHP () + =20 + Store (0x01, GPSH) // Clear Hotplug SCI Enable = in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR43, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR43 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR43) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC44.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC44.asi new file mode 100644 index 0000000000..aecee85a33 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC44.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(14) + } + } + + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR44, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR44 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR44) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC45.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC45.asi new file mode 100644 index 0000000000..dc7d050938 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC45.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(15) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR45, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR45 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR45) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC46.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC46.asi new file mode 100644 index 0000000000..4ad40d819a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC46.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(15) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR46, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR46 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR46) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC47.= asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC47.asi new file mode 100644 index 0000000000..b2daca6242 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC47.asi @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + =20 + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(15) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + =20 + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmwa= re First model in WHEA + // + And (CTRL, 0x17, CTRL) + =20 + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is s= till in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00)=20 + + } // End Method STA + + Name(PR47, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produc= es bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is con= nected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Plat= form Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Plat= form Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O ab= ove CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patche= d by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + //Off board video card not detected in device manager when it is conne= cted to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O b= elow CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platf= orm Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platf= orm Driver during POST)=20 + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs = offset for it in a .h file + )=20 + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FI= X3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of mem= ory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platf= orm Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patc= hed by ACPI Platform Driver during POST) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (FIX= 4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FI= X4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs = offset for it in a .h file + ) + }) // end of PR47 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR47) + } + --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74982): https://edk2.groups.io/g/devel/message/74982 Mute This Topic: https://groups.io/mt/82742443/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 12:00:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74981+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74981+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1620726550; cv=none; d=zohomail.com; s=zohoarc; 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[66.175.222.108]) by mx.zohomail.com with SMTPS id 1620726550498457.93934657266766; Tue, 11 May 2021 02:49:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4FlkYY1788612xVScgPzDBP7; Tue, 11 May 2021 02:49:09 -0700 X-Received: from mga12.intel.com (mga12.intel.com []) by mx.groups.io with SMTP id smtpd.web11.10477.1620726537998796077 for ; Tue, 11 May 2021 02:49:03 -0700 IronPort-SDR: sYche5Sa3JsQicnNhVCDMXHOj5jklz8b0ymBTTXQsZAfd+MpeqDoW25LASZVidiscqGP5P4dVx 2dB9WsRGCCxg== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="178994719" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="178994719" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:54 -0700 IronPort-SDR: RxVAGUlcnfXYG/vx4j3NpfvTHjVU3uvFFa5ZkYub53zlgBDIlp+vJNztDLkGBYVfIYpGpccbER u7kp1AyMxXrw== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436574015" X-Received: from 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Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726549; bh=B93yFF10aTF3YhUAq0anFSPSmllULWGI1ZirgEi8RFw=; h=Cc:Date:From:Reply-To:Subject:To; b=HYS9FY7Ynr6QPNwhFQr+MHgstVri2mKyuUzZ3CRzQTsbd+r0tt65xRyNq6ltbYMtJrv Xk6V9UkgnEkljD5bMjeX1lqco0oigPGx3Reg0J8Hg5oICcSHjBPCd2BXFQcdwxe2olILU +af4YfEhLPwEgY6HAtsUl0A46qvwWPdEjvo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl | 19 + .../Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi | 227 +++++ .../Acpi/BoardAcpiDxe/Dsdt/DSDT.asl | 77 ++ .../Acpi/BoardAcpiDxe/Dsdt/Gpe.asl | 134 +++ .../Acpi/BoardAcpiDxe/Dsdt/HostBus.asl | 256 ++++++ .../Dsdt/IioPcieHotPlugGpeHandler.asl | 842 ++++++++++++++++++ .../Dsdt/IioPcieRootPortHotPlug.asl | 686 ++++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/Itss.asl | 32 + .../Acpi/BoardAcpiDxe/Dsdt/Mother.asi | 202 +++++ .../Acpi/BoardAcpiDxe/Dsdt/Os.asi | 145 +++ .../Acpi/BoardAcpiDxe/Dsdt/Pch.asi | 10 + .../Acpi/BoardAcpiDxe/Dsdt/PchApic.asi | 17 + .../Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi | 91 ++ .../Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi | 92 ++ .../Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl | 17 + .../Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi | 22 + .../Acpi/BoardAcpiDxe/Dsdt/PchSata.asi | 807 +++++++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi | 329 +++++++ .../Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi | 312 +++++++ .../Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi | 455 ++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi | 644 ++++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi | 14 + .../Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi | 16 + .../Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi | 355 ++++++++ .../Acpi/BoardAcpiDxe/Dsdt/Platform.asl | 79 ++ .../Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi | 78 ++ .../Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi | 9 + .../Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi | 9 + .../Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi | 9 + .../Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi | 33 + .../Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi | 175 ++++ .../Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi | 125 +++ .../Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi | 98 ++ .../Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl | 189 ++++ 34 files changed, 6605 insertions(+) create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/AMLUPD.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/CommonPlatform.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/DSDT.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Gpe.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/HostBus.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/IioPcieHotPlugGpeHandler.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/IioPcieRootPortHotPlug.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Itss.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Mother.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Os.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Pch.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PchApic.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PchEhci1.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PchEhci2.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PchGbe.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PchLpc.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PchSata.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PchXhci.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PciCrs.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PciIrq.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PcieHp.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PcieHpDev.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PcieNonHpDev.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PcieSeg.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Platform.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/PlatformGpe.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Sck1Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Sck2Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Sck3Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Uncore0.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Uncore1.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Uncore2.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Uncore3.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/WFPPlatform.asl diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUP= D.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl new file mode 100644 index 0000000000..b76b062a94 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl @@ -0,0 +1,19 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +//////////////////////////////////////////////////////////////////////////= ///////// +//Values are set like this to have ASL compiler reserve enough space for o= bjects=20 +//////////////////////////////////////////////////////////////////////////= ///////// +// +// Available Sleep states +// +Name(SS1,0) +Name(SS2,0) +Name(SS3,1) +Name(SS4,1) + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Commo= nPlatform.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Co= mmonPlatform.asi new file mode 100644 index 0000000000..f5317cff86 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatfo= rm.asi @@ -0,0 +1,227 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MaxSocket.h" + + // + // External declarations + // HECI-1/HECI-2 are in PurleyPlatPkg\Me\Sps\Acpi\SpsNm.asl + // + External(\_SB.PC00.HEC2.HPTS, MethodObj) + External(\_SB.PC00.HEC2.HWAK, MethodObj) + =20 + // + // System Sleep States + // + Name (\_S0,Package (){0,0,0,0}) + Name (\_S3,Package (){5,0,0,0}) // Name changed to \DS3 if disabled in= Setup + Name (\_S4,Package (){6,0,0,0}) // Name changed to \DS4 if disabled in= Setup + Name (\_S5,Package (){7,0,0,0}) + =20 + // + // Native OS hot plug support, 0->ACPI, 1->OS=20 + // + Name (\OSHF, 0) + + // + // OS flag + // + #include "Os.asi" + + // + // for determing PIC mode + // + Name (\PICM,Zero) + Method (\_PIC, 1, NotSerialized) { + Store(Arg0,\PICM) + } + + OperationRegion (DBG0, SystemIO, 0x80, 2) + Field (DBG0, ByteAcc,NoLock,Preserve) { + IO80, 8, + IO81, 8 + } + + // + // Access CMOS range + // + OperationRegion (ACMS, SystemIO, 0x72, 2) + Field ( ACMS, ByteAcc, NoLock, Preserve) { + INDX, 8, + DATA, 8 + } + + //=20 + // SWGPE_CTRL + // + OperationRegion (GPCT, SystemIO, 0x442, 1) + Field ( GPCT, ByteAcc, NoLock, Preserve) { + , 1, + SGPC , 1, + } + + //=20 + // GPI_INV + // + OperationRegion (GPIV, SystemIO, 0x52c, 2) + Field ( GPIV, ByteAcc, NoLock, Preserve) { + GP0I , 1, + } + +#include "Acpi/GlobalNvs.asi" + + // + // Operation region for GPI status bits + // + OperationRegion (GSTS, SystemIO, 0x422, 2) + Field ( GSTS, ByteAcc, NoLock, Preserve) { + GP00 , 1, + , 12, + GP13 , 1, + } + + // + // GPE0 HOT_PLUG_EN + // + OperationRegion (GPE0, SystemIO, 0x428, 8) + Field (GPE0, ByteAcc,NoLock,Preserve) { + ,1, + GPEH,1, + ,1, + USB1,1, + USB2,1, + USB5,1, + ,3,=20 + PCIE,1, + ,1, + PMEE,1, + USB3,1, + PMB0,1, + USB4,1, + ,9, + ,1, + ,7, + USB6,1, + ,15, + } + + // + // GPES Status + // + OperationRegion (GPES, SystemIO, 0x420, 8) + Field (GPES, ByteAcc,NoLock,Preserve) { + ,1, + GPSH,1, + SGPS,1, + US1S,1, + US2S,1, + US5S,1, + ,1,=20 + SMWS,1, + ,1,=20 + PEES,1, + ,1, + PMES,1, + =20 + US3S ,1, + PMBS,1, + US4S ,1, + ,9, + ,1, + ,7, + US6S,1, + ,15, + } + =20 + // + // System sleep down + // + Method (_PTS, 1, NotSerialized) + { + Store (0x72, IO80) // Sync with EfiPostCode.h + + // + // Clear wake event status. + // + Store(1,US1S) + Store(1,US2S) + Store(1,US5S) + Store(1,SMWS) + Store(1,PMES) + Store(1,US3S) + Store(1,PMBS) + Store(1,US4S) + Store(1,US6S) + + // + // Enable SCI and wake event sources. + // + Store(1,GPEH) + Store(1,USB1) + Store(1,USB2) + Store(1,USB5) + Store(1,PCIE) + Store(1,PMEE) + Store(1,USB3) + Store(1,PMB0) + Store(1,USB4) + Store(1,USB6) + + // + // If HECI-2 exist call its prepare-to-sleep handler. + // The handler checks whether HECI-2 is enabled. + // + If (CondRefOf(\_SB.PC00.HEC2.HPTS)) + { + \_SB.PC00.HEC2.HPTS() + } + + /// WA for S3 on XHCI + \_SB.PC00.XHCI.XHCS() + } + + //#include "Uncore.asi" + + // + // System Wake up + // + Method (_WAK, 1, Serialized) + { + Store (0x73, IO80) // Sync with EfiPostCode.h + + // + // If HECI-2 exist call its wake-up handler. + // The handler checks whether HECI-2 is enabled. + // + If (CondRefOf(\_SB.PC00.HEC2.HWAK)) + { + \_SB.PC00.HEC2.HWAK() + } + + // + // If waking from S3 + // + If (LEqual(Arg0, 3)) { + } + + Return(Package(){0, 0}) + } + + Scope(\_SB) { + =20 + // Information on CPU and Memory for hotplug SKUs + // #include "CpuMemHp.asi" + =20 + OperationRegion (IOB2, SystemIO, 0xB2, 2) //MKF_SMIPORT + Field (IOB2, ByteAcc, NoLock, Preserve) { + SMIC, 8, // SW-SMI ctrl port + SMIS, 8, // SW-SMI status port + } + + } // end _SB scope + + =20 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.= asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl new file mode 100644 index 0000000000..55b4c11741 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl @@ -0,0 +1,77 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +// Comment out includes as ifdefs don't work at trim stage + +// +// + +Scope(\_SB) { + // + //----------------------------------------------------------------------= ----- + // List of IRQ resource buffers compatible with _PRS return format. + //----------------------------------------------------------------------= ----- + // Naming legend: + // RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, = "xy" - last two characters of IRQ Link name. + // Note. PRSy name is generated if IRQ Link name starts from "LNK". + // HLxy , LLxy - reference names, can be used to access bit mask of avai= lable IRQs. HL and LL stand for active High(Low) Level triggered Irq model. + //----------------------------------------------------------------------= ----- + Name(PRSA, ResourceTemplate(){ // Link name: LNKA + IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15} + }) + Alias(PRSA,PRSB) // Link name: LNKB + Alias(PRSA,PRSC) // Link name: LNKC + Alias(PRSA,PRSD) // Link name: LNKD + Alias(PRSA,PRSE) // Link name: LNKE + Alias(PRSA,PRSF) // Link name: LNKF + Alias(PRSA,PRSG) // Link name: LNKG + Alias(PRSA,PRSH) // Link name: LNKH +} + +// +// + + Scope(\_SB.PC00) { + // + // PCI-specific method's GUID + // + Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) + // + // PCI's _DSM - an attempt at modular _DSM implementation + // When writing your own _DSM function that needs to include PCI-speci= fic methods, do this: + // + // Method(_YOUR_DSM,4){=20 + // if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } + // ...continue your _DSM by checking different GUIDs... + // else { return(0) } + // }=20 + // + Method(PCID, 4, Serialized) { + If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID + If(LGreaterEqual(Arg1,3)) { = // revision at least 3 + If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } = // function 0: list of supported functions + If(LEqual(Arg2,8)) { Return (1) } = // function 8: Avoiding Power-On Reset Delay Duplication on Sx Resume + If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,On= es}) } // function 9: Specifying Device Readiness Durations + } + } + return (Buffer(1){0}) + } + }//scope +Scope(\_SB.PC00) { + //PciCheck, Arg0=3DUUID, returns true if support for 'PCI delays optimiz= ation ECR' is enabled and the UUID is correct + Method(PCIC,1,Serialized) { + If(LEqual(ECR1,1)) { + If(LEqual(Arg0, PCIG)) { + return (1) + } + } + return (0) + } +} + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.a= sl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl new file mode 100644 index 0000000000..97a3ba0eb3 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl @@ -0,0 +1,134 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // General Purpose Events. This Scope handles the Run-time and + // Wake-time SCIs. The specific method called will be determined by + // the _Lxx value, where xx equals the bit location in the General + // Purpose Event register(s). + + // + // If the Root Port is enabled, run PCI_EXP_STS handler + // + If(LNotEqual(\_SB.PC00.RP01.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP01.HPME() + Notify(\_SB.PC00.RP01, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP02.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP02.HPME() + Notify(\_SB.PC00.RP02, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP03.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP03.HPME() + Notify(\_SB.PC00.RP03, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP04.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP04.HPME() + Notify(\_SB.PC00.RP04, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP05.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP05.HPME() + Notify(\_SB.PC00.RP05, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP06.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP06.HPME() + Notify(\_SB.PC00.RP06, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP07.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP07.HPME() + Notify(\_SB.PC00.RP07, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP08.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP08.HPME() + Notify(\_SB.PC00.RP08, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP09.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP09.HPME() + Notify(\_SB.PC00.RP09, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP10.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP10.HPME() + Notify(\_SB.PC00.RP10, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP11.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP11.HPME() + Notify(\_SB.PC00.RP11, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP12.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP12.HPME() + Notify(\_SB.PC00.RP12, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP13.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP13.HPME() + Notify(\_SB.PC00.RP13, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP14.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP14.HPME() + Notify(\_SB.PC00.RP14, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP15.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP15.HPME() + Notify(\_SB.PC00.RP15, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP16.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP16.HPME() + Notify(\_SB.PC00.RP16, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP17.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP17.HPME() + Notify(\_SB.PC00.RP17, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP18.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP18.HPME() + Notify(\_SB.PC00.RP18, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP19.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP19.HPME() + Notify(\_SB.PC00.RP19, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP20.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP20.HPME() + Notify(\_SB.PC00.RP20, 0x02) + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostB= us.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.a= sl new file mode 100644 index 0000000000..daf80171a1 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl @@ -0,0 +1,256 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Define various System Agent (SA) PCI Configuration Space +// registers which will be used to dynamically produce all +// resources in the Host Bus _CRS. +// +OperationRegion (HBUS, PCI_Config, 0x00, 0x100) +Field (HBUS, DWordAcc, NoLock, Preserve) +{ + Offset(0x40), // EPBAR (0:0:0:40) + EPEN, 1, // Enable + , 11, + EPBR, 20, // EPBAR [31:12] + + Offset(0x48), // MCHBAR (0:0:0:48) + MHEN, 1, // Enable + , 14, + MHBR, 17, // MCHBAR [31:15] + + Offset(0x50), // GGC (0:0:0:50) + GCLK, 1, // GGCLCK + + Offset(0x54), // DEVEN (0:0:0:54) + D0EN, 1, // DEV0 Enable + D1F2, 1, // DEV1 FUN2 Enable + D1F1, 1, // DEV1 FUN1 Enable + D1F0, 1, // DEV1 FUN0 Enable + + Offset(0x60), // PCIEXBAR (0:0:0:60) + PXEN, 1, // Enable + PXSZ, 2, // PCI Express Size + , 23, + PXBR, 6, // PCI Express BAR [31:26] + + Offset(0x68), // DMIBAR (0:0:0:68) + DIEN, 1, // Enable + , 11, + DIBR, 20, // DMIBAR [31:12] + + Offset(0x70), // MESEG_BASE (0:0:0:70) + , 20, + MEBR, 12, // MESEG_BASE [31:20] + + Offset(0x80), // PAM0 Register (0:0:0:80) + , 4, + PM0H, 2, // PAM 0, High Nibble + , 2, + + Offset(0x81), // PAM1 Register (0:0:0:81) + PM1L, 2, // PAM1, Low Nibble + , 2, + PM1H, 2, // PAM1, High Nibble + , 2, + + Offset(0x82), // PAM2 Register (0:0:0:82) + PM2L, 2, // PAM2, Low Nibble + , 2, + PM2H, 2, // PAM2, High Nibble + , 2, + + Offset(0x83), // PAM3 Register (0:0:0:83) + PM3L, 2, // PAM3, Low Nibble + , 2, + PM3H, 2, // PAM3, High Nibble + , 2, + + Offset(0x84), // PAM4 Register (0:0:0:84) + PM4L, 2, // PAM4, Low Nibble + , 2, + PM4H, 2, // PAM4, High Nibble + , 2, + + Offset(0x85), // PAM5 Register (0:0:0:85) + PM5L, 2, // PAM5, Low Nibble + , 2, + PM5H, 2, // PAM5, High Nibble + , 2, + + Offset(0x86), // PAM6 Register (0:0:0:86) + PM6L, 2, // PAM6, Low Nibble + , 2, + PM6H, 2, // PAM6, High Nibble + , 2, + + Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8) + , 20, + TUUD, 19, // TOUUD [38:20] + + Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC) + , 20, + TLUD, 12, // TOLUD [31:20] + + Offset(0xC8), // ERRSTS register (0:0:0:C8) + , 7, + HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR +} +// +// Define a buffer that will store all the bus, memory, and IO information +// relating to the Host Bus. This buffer will be dynamically altered in +// the _CRS and passed back to the OS. +// +Name(BUF0,ResourceTemplate() +{ + // + // Bus Number Allocation: Bus 0 to 0xFF + // + WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00, + 0x0000,0x00FF,0x00,0x0100,,,PB00) + + // + // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 ) + // + DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, + 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00) + + // + // PCI Configuration Registers ( 0x0CF8 - 0x0CFF ) + // + Io(Decode16,0x0CF8,0x0CF8,1,0x08) + + // + // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF ) + // + DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, + 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01) + + // + // Video Buffer Area ( 0xA0000 - 0xBFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000) + + // + // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000) + + // + // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400) + + // + // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800) + + // + // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00) + + // + // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000) + + // + // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400) + + // + // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800) + + // + // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00) + + // + // BIOS Extension Area ( 0xE0000 - 0xE3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000) + + // + // BIOS Extension Area ( 0xE4000 - 0xE7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400) + + // + // BIOS Extension Area ( 0xE8000 - 0xEBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800) + + // + // BIOS Extension Area ( 0xEC000 - 0xEFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00) + + // + // BIOS Area ( 0xF0000 - 0xFFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000) + +// // +// // Memory Hole Region ( 0xF00000 - 0xFFFFFF ) +// // +// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, +// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE) + + // + // PCI Memory Region ( TOLUD - 0xFEAFFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0x00000000,0xFEAFFFFF,0x00,0xFEB00000,,,PM01) + + // + // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) ) + // (This is dummy range for OS compatibility, will patch it in _CRS) + // + QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02) +}) + +Name(EP_B, 0) // to store EP BAR +Name(MH_B, 0) // to store MCH BAR +Name(PC_B, 0) // to store PCIe BAR +Name(PC_L, 0) // to store PCIe BAR Length +Name(DM_B, 0) // to store DMI BAR + + +// +// Get PCIe BAR +// +Method(GPCB,0,Serialized) +{ + if(LEqual(PC_B,0)) + { + //ShiftLeft(\_SB.PC00.PXBR,26,PC_B) + Store(MCFG,PC_B) + } + Return(PC_B) +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPc= ieHotPlugGpeHandler.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiD= xe/Dsdt/IioPcieHotPlugGpeHandler.asl new file mode 100644 index 0000000000..9631d8cee3 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPl= ugGpeHandler.asl @@ -0,0 +1,842 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // + // Delay introduced as initial delay after entering ACPI hotplug method=20 + // + Sleep (200) + Store (0x01, IO80) + Sleep (10) + Store (0,Local1) + + // PC01 Port 1A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC01.BR1A.PMEP,1) ) { + Store(\_SB.PC01.BR1A.PMEH(1), Local0) + } else { + Store (\_SB.PC01.BR1A.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC01.BR1A, Local0) + } + + // PC01 Port 1B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC01.BR1B.PMEP,1) ) { + Store(\_SB.PC01.BR1B.PMEH(2), Local0) + } else { + Store (\_SB.PC01.BR1B.HPEH(2), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(2, Local1) + Notify(\_SB.PC01.BR1B, Local0) + } + + // PC01 Port 1C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC01.BR1C.PMEP,1) ) { + Store(\_SB.PC01.BR1C.PMEH(3), Local0) + } else { + Store (\_SB.PC01.BR1C.HPEH(3), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(3, Local1) + Notify(\_SB.PC01.BR1C, Local0) + } + + // PC01 Port 1D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC01.BR1D.PMEP,1) ) { + Store(\_SB.PC01.BR1D.PMEH(4), Local0) + } else { + Store (\_SB.PC01.BR1D.HPEH(4), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(4, Local1) + Notify(\_SB.PC01.BR1D, Local0) + } + + // PC02 Port 2A PCI-Ex Hot Plug + If( LEqual(\_SB.PC02.BR2A.PMEP,1) ) { + Store(\_SB.PC02.BR2A.PMEH(5), Local0) + } else { + Store (\_SB.PC02.BR2A.HPEH(5), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(5, Local1) + Notify(\_SB.PC02.BR2A, Local0) + } + + // PC02 Port 2B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC02.BR2B.PMEP,1) ) { + Store(\_SB.PC02.BR2B.PMEH(6), Local0) + } else { + Store (\_SB.PC02.BR2B.HPEH(6), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(6, Local1) + Notify(\_SB.PC02.BR2B, Local0) + } + + // PC02 Port 2C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC02.BR2C.PMEP,1) ) { + Store(\_SB.PC02.BR2C.PMEH(7), Local0) + } else { + Store (\_SB.PC02.BR2C.HPEH(7), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(7, Local1) + Notify(\_SB.PC02.BR2C, Local0) + } + + // PC02 Port 2D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC02.BR2D.PMEP,1) ) { + Store(\_SB.PC02.BR2D.PMEH(8), Local0) + } else { + Store (\_SB.PC02.BR2D.HPEH(8), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(8, Local1) + Notify(\_SB.PC02.BR2D, Local0) + } + + // PC03 Port 3A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC03.BR3A.PMEP,1) ) { + Store(\_SB.PC03.BR3A.PMEH(9), Local0) + } else { + Store (\_SB.PC03.BR3A.HPEH(9), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(9, Local1) + Notify(\_SB.PC03.BR3A, Local0) + } + + // PC03 Port 3B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC03.BR3B.PMEP,10) ) { + Store(\_SB.PC03.BR3B.PMEH(10), Local0) + } else { + Store (\_SB.PC03.BR3B.HPEH(10), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(10, Local1) + Notify(\_SB.PC03.BR3B, Local0) + } + + // PC03 Port 3C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC03.BR3C.PMEP,1) ) { + Store(\_SB.PC03.BR3C.PMEH(11), Local0) + } else { + Store (\_SB.PC03.BR3C.HPEH(11), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(11, Local1) + Notify(\_SB.PC03.BR3C, Local0) + } + + // PC03 Port 3D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC03.BR3D.PMEP,1) ) { + Store(\_SB.PC03.BR3D.PMEH(12), Local0) + } else { + Store (\_SB.PC03.BR3D.HPEH(12), Local0)=20 + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(12, Local1) + Notify(\_SB.PC03.BR3D, Local0) + } + + // PC06 Port 0 PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC06.QRP0.PMEP,1) ) { + Store(\_SB.PC06.QRP0.PMEH(1), Local0) + } else { + Store (\_SB.PC06.QRP0.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC06.QRP0, Local0) + } + + // PC07 Port 1A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC07.QR1A.PMEP,1) ) { + Store(\_SB.PC07.QR1A.PMEH(1), Local0) + } else { + Store (\_SB.PC07.QR1A.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC07.QR1A, Local0) + } + + // PC07 Port 1B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC07.QR1B.PMEP,1) ) { + Store(\_SB.PC07.QR1B.PMEH(2), Local0) + } else { + Store (\_SB.PC07.QR1B.HPEH(2), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(2, Local1) + Notify(\_SB.PC07.QR1B, Local0) + } + + // PC07 Port 1C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC07.QR1C.PMEP,1) ) { + Store(\_SB.PC07.QR1C.PMEH(3), Local0) + } else { + Store (\_SB.PC07.QR1C.HPEH(3), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(3, Local1) + Notify(\_SB.PC07.QR1C, Local0) + } + + // PC07 Port 1D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC07.QR1D.PMEP,1) ) { + Store(\_SB.PC07.QR1D.PMEH(4), Local0) + } else { + Store (\_SB.PC07.QR1D.HPEH(4), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(4, Local1) + Notify(\_SB.PC07.QR1D, Local0) + } + + // PC08 Port 2A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC08.QR2A.PMEP,1) ) { + Store(\_SB.PC08.QR2A.PMEH(5), Local0) + } else { + Store (\_SB.PC08.QR2A.HPEH(5), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(5, Local1) + Notify(\_SB.PC08.QR2A, Local0) + } + + // PC08 Port 2B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC08.QR2B.PMEP,1) ) { + Store(\_SB.PC08.QR2B.PMEH(6), Local0) + } else { + Store (\_SB.PC08.QR2B.HPEH(6), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(6, Local1) + Notify(\_SB.PC08.QR2B, Local0) + } + + // PC08 Port 2C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC08.QR2C.PMEP,1) ) { + Store(\_SB.PC08.QR2C.PMEH(7), Local0) + } else { + Store (\_SB.PC08.QR2C.HPEH(7), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(7, Local1) + Notify(\_SB.PC08.QR2C, Local0) + } + + // PC08 Port 2D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC08.QR2D.PMEP,1) ) { + Store(\_SB.PC08.QR2D.PMEH(8), Local0) + } else { + Store (\_SB.PC08.QR2D.HPEH(8), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(8, Local1) + Notify(\_SB.PC08.QR2D, Local0) + } + + // PC09 Port 3A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC09.QR3A.PMEP,1) ) { + Store(\_SB.PC09.QR3A.PMEH(9), Local0) + } else { + Store (\_SB.PC09.QR3A.HPEH(9), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(9, Local1) + Notify(\_SB.PC09.QR3A, Local0) + } + + // PC09 Port 3B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC09.QR3B.PMEP,1) ) { + Store(\_SB.PC09.QR3B.PMEH(10), Local0) + } else { + Store (\_SB.PC09.QR3B.HPEH(10), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(10, Local1) + Notify(\_SB.PC09.QR3B, Local0) + } + + // PC09 Port 3C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC09.QR3C.PMEP,1) ) { + Store(\_SB.PC09.QR3C.PMEH(11), Local0) + } else { + Store (\_SB.PC09.QR3C.HPEH(11), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(11, Local1) + Notify(\_SB.PC09.QR3C, Local0) + } + + // PC09 Port 3D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC09.QR3D.PMEP,1) ) { + Store(\_SB.PC09.QR3D.PMEH(12), Local0) + } else { + Store (\_SB.PC09.QR3D.HPEH(12), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(12, Local1) + Notify(\_SB.PC09.QR3D, Local0) + } + + // PC12 Port 0 PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC12.RRP0.PMEP,1) ) { + Store(\_SB.PC12.RRP0.PMEH(1), Local0) + } else { + Store (\_SB.PC12.RRP0.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC12.RRP0, Local0) + } + + // PC13 Port 1A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC13.RR1A.PMEP,1) ) { + Store(\_SB.PC13.RR1A.PMEH(1), Local0) + } else { + Store (\_SB.PC13.RR1A.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC13.RR1A, Local0) + } + + // PC13 Port 1B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC13.RR1B.PMEP,1) ) { + Store(\_SB.PC13.RR1B.PMEH(2), Local0) + } else { + Store (\_SB.PC13.RR1B.HPEH(2), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(2, Local1) + Notify(\_SB.PC13.RR1B, Local0) + } + + // PC13 Port 1C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC13.RR1C.PMEP,1) ) { + Store(\_SB.PC13.RR1C.PMEH(3), Local0) + } else { + Store (\_SB.PC13.RR1C.HPEH(3), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(3, Local1) + Notify(\_SB.PC13.RR1C, Local0) + } + + // PC13 Port 1D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC13.RR1D.PMEP,1) ) { + Store(\_SB.PC13.RR1D.PMEH(4), Local0) + } else { + Store (\_SB.PC13.RR1D.HPEH(4), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(4, Local1) + Notify(\_SB.PC13.RR1D, Local0) + } + + // PC14 Port 2A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC14.RR2A.PMEP,1) ) { + Store(\_SB.PC14.RR2A.PMEH(5), Local0) + } else { + Store (\_SB.PC14.RR2A.HPEH(5), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(5, Local1) + Notify(\_SB.PC14.RR2A, Local0) + } + + // PC14 Port 2B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC14.RR2B.PMEP,1) ) { + Store(\_SB.PC14.RR2B.PMEH(6), Local0) + } else { + Store (\_SB.PC14.RR2B.HPEH(6), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(6, Local1) + Notify(\_SB.PC14.RR2B, Local0) + } + + // PC14 Port 2C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC14.RR2C.PMEP,1) ) { + Store(\_SB.PC14.RR2C.PMEH(7), Local0) + } else { + Store (\_SB.PC14.RR2C.HPEH(7), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(7, Local1) + Notify(\_SB.PC14.RR2C, Local0) + } + + // PC15 Port 2D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC14.RR2D.PMEP,1) ) { + Store(\_SB.PC14.RR2D.PMEH(8), Local0) + } else { + Store (\_SB.PC14.RR2D.HPEH(8), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(8, Local1) + Notify(\_SB.PC14.RR2D, Local0) + } + + // PC15 Port 3A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC15.RR3A.PMEP,1) ) { + Store(\_SB.PC15.RR3A.PMEH(9), Local0) + } else { + Store (\_SB.PC15.RR3A.HPEH(9), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(9, Local1) + Notify(\_SB.PC15.RR3A, Local0) + } + + // PC15 Port 3B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC15.RR3B.PMEP,1) ) { + Store(\_SB.PC15.RR3B.PMEH(10), Local0) + } else { + Store (\_SB.PC15.RR3B.HPEH(10), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(10, Local1) + Notify(\_SB.PC15.RR3B, Local0) + } + + // PC15 Port 3C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC15.RR3C.PMEP,1) ) { + Store(\_SB.PC15.RR3C.PMEH(11), Local0) + } else { + Store (\_SB.PC15.RR3C.HPEH(11), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(11, Local1) + Notify(\_SB.PC15.RR3C, Local0) + } + + // PC15 Port 3D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC15.RR3D.PMEP,1) ) { + Store(\_SB.PC15.RR3D.PMEH(12), Local0) + } else { + Store (\_SB.PC15.RR3D.HPEH(12), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(12, Local1) + Notify(\_SB.PC15.RR3D, Local0) + } + + // PC18 Port 0 PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC18.SRP0.PMEP,1) ) { + Store(\_SB.PC18.SRP0.PMEH(1), Local0) + } else { + Store (\_SB.PC18.SRP0.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC18.SRP0, Local0) + } + + // PC19 Port 1A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC19.SR1A.PMEP,1) ) { + Store(\_SB.PC19.SR1A.PMEH(1), Local0) + } else { + Store (\_SB.PC19.SR1A.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC19.SR1A, Local0) + } + + // PC19 Port 1B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC19.SR1B.PMEP,1) ) { + Store(\_SB.PC19.SR1B.PMEH(2), Local0) + } else { + Store (\_SB.PC19.SR1B.HPEH(2), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(2, Local1) + Notify(\_SB.PC19.SR1B, Local0) + } + + // PC19 Port 1C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC19.SR1C.PMEP,1) ) { + Store(\_SB.PC19.SR1C.PMEH(3), Local0) + } else { + Store (\_SB.PC19.SR1C.HPEH(3), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(3, Local1) + Notify(\_SB.PC19.SR1C, Local0) + } + + // PC19 Port 1D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC19.SR1D.PMEP,1) ) { + Store(\_SB.PC19.SR1D.PMEH(4), Local0) + } else { + Store (\_SB.PC19.SR1D.HPEH(4), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(4, Local1) + Notify(\_SB.PC19.SR1D, Local0) + } + + // PC20 Port 2A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC20.SR2A.PMEP,1) ) { + Store(\_SB.PC20.SR2A.PMEH(5), Local0) + } else { + Store (\_SB.PC20.SR2A.HPEH(5), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(5, Local1) + Notify(\_SB.PC20.SR2A, Local0) + } + + // PC20 Port 2B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC20.SR2B.PMEP,1) ) { + Store(\_SB.PC20.SR2B.PMEH(6), Local0) + } else { + Store (\_SB.PC20.SR2B.HPEH(6), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(6, Local1) + Notify(\_SB.PC20.SR2B, Local0) + } + + // PC20 Port 2C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC20.SR2C.PMEP,1) ) { + Store(\_SB.PC20.SR2C.PMEH(7), Local0) + } else { + Store (\_SB.PC20.SR2C.HPEH(7), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(7, Local1) + Notify(\_SB.PC20.SR2C, Local0) + } + + // PC20 Port 2D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC20.SR2D.PMEP,1) ) { + Store(\_SB.PC20.SR2D.PMEH(8), Local0) + } else { + Store (\_SB.PC20.SR2D.HPEH(8), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(8, Local1) + Notify(\_SB.PC20.SR2D, Local0) + } + + // PC21 Port 3A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC21.SR3A.PMEP,1) ) { + Store(\_SB.PC21.SR3A.PMEH(9), Local0) + } else { + Store (\_SB.PC21.SR3A.HPEH(9), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(9, Local1) + Notify(\_SB.PC21.SR3A, Local0) + } + + // PC21 Port 3B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC21.SR3B.PMEP,1) ) { + Store(\_SB.PC21.SR3B.PMEH(10), Local0) + } else { + Store (\_SB.PC21.SR3B.HPEH(10), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(10, Local1) + Notify(\_SB.PC21.SR3B, Local0) + } + + // PC21 Port 3C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC21.SR3C.PMEP,1) ) { + Store(\_SB.PC21.SR3C.PMEH(11), Local0) + } else { + Store (\_SB.PC21.SR3C.HPEH(11), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(11, Local1) + Notify(\_SB.PC21.SR3C, Local0) + } + + // PC21 Port 3D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC21.SR3D.PMEP,1) ) { + Store(\_SB.PC21.SR3D.PMEH(12), Local0) + } else { + Store (\_SB.PC21.SR3D.HPEH(12), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(12, Local1) + Notify(\_SB.PC21.SR3D, Local0) + } + + //If a hotplug event was serviced check if this was generated by PM_PME + If (Lnot (LEqual(Local0, 0))) { + //Clear the status bit 16 of PMEStatus + //Clear the PME Pending bit 17 of PMEStatus + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC01.BR1A.PMES) + Store(1, \_SB.PC01.BR1A.PMEP) + } + If( LEqual(Local1, 2)) { + Store(1, \_SB.PC01.BR1B.PMES) + Store(1, \_SB.PC01.BR1B.PMEP) + } + If( LEqual(Local1, 3)) { + Store(1, \_SB.PC01.BR1C.PMES) + Store(1, \_SB.PC01.BR1C.PMEP) + } + If( LEqual(Local1, 4)) { + Store(1, \_SB.PC01.BR1D.PMES) + Store(1, \_SB.PC01.BR1D.PMEP) + } + + If( LEqual(Local1, 5)) { + Store(1, \_SB.PC02.BR2A.PMES) + Store(1, \_SB.PC02.BR2A.PMEP) + } + If( LEqual(Local1, 6)) { + Store(1, \_SB.PC02.BR2B.PMES) + Store(1, \_SB.PC02.BR2B.PMEP) + } + If( LEqual(Local1, 7)) { + Store(1, \_SB.PC02.BR2C.PMES) + Store(1, \_SB.PC02.BR2C.PMEP) + } + If( LEqual(Local1, 8)) { + Store(1, \_SB.PC02.BR2D.PMES) + Store(1, \_SB.PC02.BR2D.PMEP) + } + If( LEqual(Local1, 9)) { + Store(1, \_SB.PC03.BR3A.PMES) + Store(1, \_SB.PC03.BR3A.PMEP) + } + If( LEqual(Local1, 10)) { + Store(1, \_SB.PC03.BR3B.PMES) + Store(1, \_SB.PC03.BR3B.PMEP) + } + If( LEqual(Local1, 11)) { + Store(1, \_SB.PC03.BR3C.PMES) + Store(1, \_SB.PC03.BR3C.PMEP) + } + If( LEqual(Local1, 12)) { + Store(1, \_SB.PC03.BR3D.PMES) + Store(1, \_SB.PC03.BR3D.PMEP) + } + + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC06.QRP0.PMES) + Store(1, \_SB.PC06.QRP0.PMEP) + } + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC07.QR1A.PMES) + Store(1, \_SB.PC07.QR1A.PMEP) + } + If( LEqual(Local1, 2)) { + Store(1, \_SB.PC07.QR1B.PMES) + Store(1, \_SB.PC07.QR1B.PMEP) + } + If( LEqual(Local1, 3)) { + Store(1, \_SB.PC07.QR1C.PMES) + Store(1, \_SB.PC07.QR1C.PMEP) + } + If( LEqual(Local1, 4)) { + Store(1, \_SB.PC07.QR1D.PMES) + Store(1, \_SB.PC07.QR1D.PMEP) + } + If( LEqual(Local1, 5)) { + Store(1, \_SB.PC08.QR2A.PMES) + Store(1, \_SB.PC08.QR2A.PMEP) + } + If( LEqual(Local1, 6)) { + Store(1, \_SB.PC08.QR2B.PMES) + Store(1, \_SB.PC08.QR2B.PMEP) + } + If( LEqual(Local1, 7)) { + Store(1, \_SB.PC08.QR2C.PMES) + Store(1, \_SB.PC08.QR2C.PMEP) + } + If( LEqual(Local1, 8)) { + Store(1, \_SB.PC08.QR2D.PMES) + Store(1, \_SB.PC08.QR2D.PMEP) + } + If( LEqual(Local1, 9)) { + Store(1, \_SB.PC09.QR3A.PMES) + Store(1, \_SB.PC09.QR3A.PMEP) + } + If( LEqual(Local1, 10)) { + Store(1, \_SB.PC09.QR3B.PMES) + Store(1, \_SB.PC09.QR3B.PMEP) + } + If( LEqual(Local1, 11)) { + Store(1, \_SB.PC09.QR3C.PMES) + Store(1, \_SB.PC09.QR3C.PMEP) + } + If( LEqual(Local1, 12)) { + Store(1, \_SB.PC09.QR3D.PMES) + Store(1, \_SB.PC09.QR3D.PMEP) + } + + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC12.RRP0.PMES) + Store(1, \_SB.PC12.RRP0.PMEP) + } + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC13.RR1A.PMES) + Store(1, \_SB.PC13.RR1A.PMEP) + } + If( LEqual(Local1, 2)) { + Store(1, \_SB.PC13.RR1B.PMES) + Store(1, \_SB.PC13.RR1B.PMEP) + } + If( LEqual(Local1, 3)) { + Store(1, \_SB.PC13.RR1C.PMES) + Store(1, \_SB.PC13.RR1C.PMEP) + } + If( LEqual(Local1, 4)) { + Store(1, \_SB.PC13.RR1D.PMES) + Store(1, \_SB.PC13.RR1D.PMEP) + } + If( LEqual(Local1, 5)) { + Store(1, \_SB.PC14.RR2A.PMES) + Store(1, \_SB.PC14.RR2A.PMEP) + } + If( LEqual(Local1, 6)) { + Store(1, \_SB.PC14.RR2B.PMES) + Store(1, \_SB.PC14.RR2B.PMEP) + } + If( LEqual(Local1, 7)) { + Store(1, \_SB.PC14.RR2C.PMES) + Store(1, \_SB.PC14.RR2C.PMEP) + } + If( LEqual(Local1, 8)) { + Store(1, \_SB.PC14.RR2D.PMES) + Store(1, \_SB.PC14.RR2D.PMEP) + } + If( LEqual(Local1, 9)) { + Store(1, \_SB.PC15.RR3A.PMES) + Store(1, \_SB.PC15.RR3A.PMEP) + } + If( LEqual(Local1, 10)) { + Store(1, \_SB.PC15.RR3B.PMES) + Store(1, \_SB.PC15.RR3B.PMEP) + } + If( LEqual(Local1, 11)) { + Store(1, \_SB.PC15.RR3C.PMES) + Store(1, \_SB.PC15.RR3C.PMEP) + } + If( LEqual(Local1, 12)) { + Store(1, \_SB.PC15.RR3D.PMES) + Store(1, \_SB.PC15.RR3D.PMEP) + } + + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC18.SRP0.PMES) + Store(1, \_SB.PC18.SRP0.PMEP) + } + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC19.SR1A.PMES) + Store(1, \_SB.PC19.SR1A.PMEP) + } + If( LEqual(Local1, 2)) { + Store(1, \_SB.PC19.SR1B.PMES) + Store(1, \_SB.PC19.SR1B.PMEP) + } + If( LEqual(Local1, 3)) { + Store(1, \_SB.PC19.SR1C.PMES) + Store(1, \_SB.PC19.SR1C.PMEP) + } + If( LEqual(Local1, 4)) { + Store(1, \_SB.PC19.SR1D.PMES) + Store(1, \_SB.PC19.SR1D.PMEP) + } + If( LEqual(Local1, 5)) { + Store(1, \_SB.PC20.SR2A.PMES) + Store(1, \_SB.PC20.SR2A.PMEP) + } + If( LEqual(Local1, 6)) { + Store(1, \_SB.PC20.SR2B.PMES) + Store(1, \_SB.PC20.SR2B.PMEP) + } + If( LEqual(Local1, 7)) { + Store(1, \_SB.PC20.SR2C.PMES) + Store(1, \_SB.PC20.SR2C.PMEP) + } + If( LEqual(Local1, 8)) { + Store(1, \_SB.PC20.SR2D.PMES) + Store(1, \_SB.PC20.SR2D.PMEP) + } + If( LEqual(Local1, 9)) { + Store(1, \_SB.PC21.SR3A.PMES) + Store(1, \_SB.PC21.SR3A.PMEP) + } + If( LEqual(Local1, 10)) { + Store(1, \_SB.PC21.SR3B.PMES) + Store(1, \_SB.PC21.SR3B.PMEP) + } + If( LEqual(Local1, 11)) { + Store(1, \_SB.PC21.SR3C.PMES) + Store(1, \_SB.PC21.SR3C.PMEP) + } + If( LEqual(Local1, 12)) { + Store(1, \_SB.PC21.SR3D.PMES) + Store(1, \_SB.PC21.SR3D.PMEP) + } + + Store(0x01,PEES) //Clear bit 9 of Status + Store(0x00,PMEE) //Clear bit 9 of GPE0_EN + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPc= ieRootPortHotPlug.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe= /Dsdt/IioPcieRootPortHotPlug.asl new file mode 100644 index 0000000000..2dd9357359 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootP= ortHotPlug.asl @@ -0,0 +1,686 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +//;***********************************************************************= *; +//; IMPORTANT NOTE: +//; Code in this file should be generic/common for any IIO PCIe root = port. +//; DO NOT use hard-coded Bus/Dev/Function # in this file. +//; +//;***********************************************************************= *; + + + + Name(DBFL, 0) // Debug flag 0/1 =3D disable/enable debug checkpoin= ts in this file + + + + //;*********************************************************************= ***; + //; This DVPS() method detects if the root port is present and hot-plug = capable. + //; Input : None + //; Output: Non-zero - Root port is present and hot-plug capable + //; Zero - otherwise + //;*********************************************************************= ***; + Method(DVPS,0) { + // Check if VID/DID =3D 3C0x_8086 to see if the root port exists + If (LNotEqual(VID, 0x8086)) { Return(Zero) } + //If( LNotEqual(And(DID, 0xFFF0), 0x3C00)) { Return(Zero) } + If( LNotEqual(And(DID, 0xFFF0), 0x2F00)) { Return(Zero) } //HSX + // Check the root port to see if slot is implemented and Hot-Plug = Capable + If(LNot(And(SLIP, HPCP))) { Return(Zero) } + Return (One) + } + + + //;*********************************************************************= ***; + //; This HPEN() method programs "Enable ACPI mode for Hot-plug" bit base= d on input Arg0 + //; See IIO PCIe rootport MISCCTRLSTS register 188h[3] definition + //; Input : 0/1 bit value to set "Enable ACPI mode for Hot-plug" (= IIO PCIe rootport register 188h[3]) =20 + //; Output: None + //;*********************************************************************= ***; + Method (HPEN, 1, Serialized) { + + DB55(0x71, 0) // debug point + + // get Bus/Dev/Func information of this root port + Store(^^_BBN, Local0) // Local0 =3D Bus# of paren= t Host bus + //Store(_BBN, Local0) // implicit reference to P= C00._BBN + ShiftRight(_ADR, 16, Local1) // Local1 =3D self Device # + And(_ADR, 0x0000ffff, Local2) // Local2 =3D self Function= # +=20 + // Calculate MMCFG config address of MISCCTRLSTS register at B:D:F:o= ffset 188h + //Name (MISR, 0xC0000188) + Name (MISR, 0) // create a pointer to M= MCFG region space + Add(MMBS, 0x188, MISR) // MISR =3D MMCFG_BASE_A= DDR + Offset of MISCCTRLSTS CSR + Add(ShiftLeft(Local0, 20), MISR, MISR) // Build bus/dev/func nu= mber fields of MISR + Add(ShiftLeft(Local1, 15), MISR, MISR) + Add(ShiftLeft(Local2, 12), MISR, MISR) + + DB55(0x77, MISR) // debug point + + + // Create OpRegion for MISCCTRLSTS register at B:D:F:offset 188h + OperationRegion (OP37, SystemMemory, MISR, 0x04) + Field (OP37, DWordAcc, NoLock, Preserve) { + , 3, + HGPE, 1, // "Enable ACPI mode = for Hot-plug" (register 188h[3])=20 + } + + // Program "Enable ACPI mode for Hot-plug" bit to input Arg0 + Store(Arg0, HGPE) + } + + //;*********************************************************************= ***; + //; This DB55() method is a debug method + //; Input : Arg0 Postcode to be sent to IO Port 80h + //; Arg1 DWord data to be copied to debug memory location + //; in BIOS Data Area (DBA) 40:42 + //; Output: None + //;*********************************************************************= ***; + Method (DB55, 2, NotSerialized) { + + If (DBFL) { // if debug is enabled + Store(Arg0, IO80) // send postcode to port 80h + Store(Arg1, MDWD) // store Arg1 to debug memory location=20 + Sleep(4000) // stall for 4 seconds + } + } + + OperationRegion (OP38, SystemMemory, 0x442, 0x04) + Field (OP38, AnyAcc, NoLock, Preserve) { + MDWD, 32, // dword at BIOS Data Area (BDA) 40= :42 (floppy task-file), used as debug memory location + } + + + Method (_INI, 0, NotSerialized) { + + If (LEqual(Zero,DVPS)) { + Return // Do nothing if this root port = is not "Present and Hot-plugable" + } + HPEN(1) // No. Enable ACPI Hot-plug events + } + + +/* Greencity code + OperationRegion (MCTL, SystemMemory, 0xA0048188, 0x04) + Field (MCTL, ByteAcc, NoLock, Preserve) { + , 3, + HGPE, 1, + , 7, + , 8, + , 8 + } + + Method (_INI, 0, NotSerialized) { + Store (0x01, HGPE) //enable GPE message generation for ACPI h= otplug support + } +*/ + +//MCWU Changed ^HP02 to HP02 to avoid re-definition when this file is inc= luded under multiple BRxx devices + //Name(^HP02, Package(4){0x08, 0x40, 1, 0} ) + Name(HP02, Package(4){0x08, 0x40, 1, 0} ) + Method(_HPP, 0) { return(HP02) } + + // + // begin hotplug code + // + Name(SHPC, 0x40) // Slot Hot-plug Capable + + Name(SPDS, 0x040) // Slot Presence Detect State + + Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on + Name(CCOM, 0x010) // Command Complete + Name(SPDC, 0x08) // Slot Presence Detect Changes + Name(MRLC, 0x04) // Slot MRL Changed + Name(SPFD, 0x02) // Slot Power Fault Detected + Name(SABP, 0x01) // Slot Attention Button Pressed + + Name(SPOF, 0x10) // Slot Power Off + Name(SPON, 0x0F) // Slot Power On Mask + + Name(ALMK, 0x1C) // Slot Atten. LED Mask + Name(ALON, 0x01) // Slot Atten. LED On + Name(ALBL, 0x02) // Slot Atten LED Blink + Name(ALOF, 0x03) // Slot Atten LED Off + + Name(PLMK, 0x13) // Slot Pwr. LED Mask + Name(PLON, 0x04) // Slot Pwr. LED On + Name(PLBL, 0x08) // Slot Pwr. LED Blink + Name(PLOF, 0x0C) // Slot Pwr. LED Off + + //;************************************* + //; Bit 3 =3D Presence Detect Event + //; Bit 2 =3D MRL Sensor Event + //; Bit 1 =3D PWR Fault Event + //; Bit 0 =3D Attention Button Event + //;************************************* + Name(HPEV, 0xF) // Possible interrupt events (all) + + //;*********************************************************************= ***; + //; + //; PCIe Slot Capabilities Register A4-A7h + //; Bit - 31-7 - Not used + //; Bit - 6 - Hot-Plug Capable + //; Bit - 5 - Hot-Plug Surprise + //; Bit - 4 - Power Indicator Present. + //; Bit - 3 - Attention Indicator Present. + //; Bit - 2 - MRL Sensor Present. + //; Bit - 1 - Power Controller Present. + //; Bit - 0 - Attention Button Present. + //; + //; PCIe Slot control Register A8-A9h + //; + //; Bit - 10 - PWR Control Disable + //; Bit - 9:8 - Attn Indicator + //; Bit - 7:6 - PWR Indicator + //; Bit - 5 - Hot-Plug Interrupt Event Enable + //; Bit - 4 - Command Complete Interrupt enable + //; Bit - 3 - Presence Detect Changed Interrupt enable + //; Bit - 2 - MRL Sensor Changed Interrupt enable + //; Bit - 1 - PwrFault Detect Interrupt enable + //; Bit - 0 - Attention Button Pressed Interrupt Enable + //; + //; PCIe Slot Status Registers AA-ADh + //; + //; Bit - 6 - Presence Detect State. + //; Bit - 5 - MRL Sensor State. + //; Bit - 4 - Command Completed. + //; + //; RWC Status Bits + //; + //; Bit - 3 - Presence Detect Changed. + //; Bit - 2 - MRL Sensor Changed. + //; Bit - 1 - Power Fault Detected. + //; Bit - 0 - Attention Button Pressed. + //;*********************************************************************= ***; + + OperationRegion(PPA4, PCI_Config, 0x00, 0x0ff) + Field(PPA4,ByteAcc,NoLock,Preserve) { + + Offset(0x00), // VenderID/DeviceID register + VID, 16, // VID =3D 0x8086 + DID, 16, // Device IDs for IIO PCI Express root port= s are as follows: + // 0x3C00: DMI mode 0x3C01: the DMI port= running in PCIe mode + // 0x3C02: Port 1a + // 0x3C03: Port 1b + // 0x3C04: Port 2a + // 0x3C05: Port 2b + // 0x3C06: Port 2c + // 0x3C07: Port 2d + // 0x3C08: Port 3a in PCIe mode + // 0x3C09: Port 3b + // 0x3C0A: Port 3c + // 0x3C0B: Port 3d + // (0x3C0F: IIO NTB Secondary Endpoint) + + Offset(0x92), // PXPCAP - PCIe CAP Register + , 8, + SLIP, 1, // bit8 Slot Implemented + + offset(0xA4), // SLTCAP - Slot Capabilities Register + ATBP,1, // bit0 Attention Button Present + PWCP,1, // bit1 Power Controller Present + MRSP,1, // bit2 MRL Sensor Present + ATIP,1, // bit3 Attention Indicator Present + PWIP,1, // bit4 Power Indicator Present + HPSR,1, // bit5 Hot-Plug Surprise + HPCP,1, // bit6 Hot-Plug Capable + + offset(0xA8), // SLTCON - PCIE Slot Control Register + ABIE,1, // bit0 Attention Button Pressed Interr= upt Enable + PFIE,1, // bit1 Power Fault Detected Interrupt = Enable + MSIE,1, // bit2 MRL Sensor Changed Interrupt En= able + PDIE,1, // bit3 Presence Detect Changed Interru= pt Enable. + CCIE,1, // bit4 Command Complete Interrupt Enab= le. + HPIE,1, // bit5 Hot-plug Interrupt Enable. + SCTL,5, // bit[10:6] Attn/Power indicator and Po= wer controller. + + offset(0xAA), // SLTSTS - PCIE Slot Status Register + SSTS,7, // The status bits in Slot Status Reg + ,1, +} + + OperationRegion(PPA8, PCI_Config, 0x00, 0x0ff) + Field(PPA8,ByteAcc,NoLock,Preserve) { + Offset(0xA8), // SLTCON - PCIE Slot Control Register + ,6, + ATID,2, // bit[7:6] Attention Indicator Control. + PWID,2, // bit[9:8] Power Indicator Control. + PWCC,1, // bit[10] Power Controller Control. + ,5, + Offset(0xAA), // SLTSTS - PCIE Slot status Register (WRC) + ABPS,1, // bit0 Attention Button Pressed Status= (RWC) + PFDS,1, // bit1 Power Fault Detect Status (RWC) + MSCS,1, // bit2 MRL Sensor Changed Status + PDCS,1, // bit3 Presence Detect Changed Status + CMCS,1, // bit4 Command Complete Status + MSSC,1, // bit5 MRL Sensor State + PRDS,1, // bit6 Presence Detect State + ,1, + } + + //;*********************************************************************= ***; + //; This OSHP (Operating System Hot Plug) method is provided for each HPC + //; which is controlled by ACPI. This method disables ACPI access to the + //; HPC and restores the normal System Interrupt and Wakeup Signal + //; connection. + //;*********************************************************************= ***; + Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express = HP code. + Store(0, SSTS) // Clear any status +// Store(0x0, HGPE) // Disable GPE generation + HPEN(0) // Disable GPE generation + } + + //;*********************************************************************= ***; + //; Hot Plug Controller Command Method + //; + //; Input: Arg0 - Command to issue + //; + //;*********************************************************************= ***; + Method(HPCC,1) { + Store(SCTL, Local0) // get current command state + Store(0, Local1) // reset the timeout value + If(LNotEqual(Arg0, Local0)) { // see if state is different + Store(Arg0, SCTL) // Update the Slot Control + While(LAnd (LNot(CMCS), LNotEqual(100, Local1))) { // spin while = CMD complete bit is not set, + // check for t= imeout to avoid dead loop + Store(0x2C, IO80) + Sleep(2) // allow processor time slice + Add(Local1, 2, Local1) + } + Store(0x1, CMCS) // Clear the command complete status + } + } + + //;*********************************************************************= ***; + //; Attention Indicator Command + //; + //; Input: Arg0 - Command to issue + //; 1 =3D ON + //; 2 =3D Blink + //; 3 =3D OFF + //;*********************************************************************= ***; + Method(ATCM,1) { + Store(SCTL, Local0) // Get Slot Control + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits + If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?" + Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON" + } + If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?" + Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK" + } + If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?" + Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF" + } + HPCC(Local0) + } + + //;*********************************************************************= ***; + //; Power Indicator Command + //; + //; Input: Arg0 - Command to issue + //; 1 =3D ON + //; 2 =3D Blink + //; 3 =3D OFF + //;*********************************************************************= ***; + Method(PWCM,1){ + Store(SCTL, Local0) // Get Slot Control + And(Local0, PLMK, Local0) // Mask the Power Indicator Bits + If(LEqual(Arg0, 0x1)){ // Power indicator "ON?" + Or(Local0, PLON, Local0) // Set the Power Indicator to "ON" + } + If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?" + Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK" + } + If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?" + Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF" + } + HPCC(Local0) + } + + //;*********************************************************************= ***; + //; Power Slot Command + //; + //; Input: Arg0 - Command to issue + //; 1 =3D Slot Power ON + //; 2 =3D Slot Power Off + //;*********************************************************************= ***; + Method(PWSL,1){ + Store(SCTL, Local0) // Get Slot Control + If(Arg0){ // Power Slot "ON" Arg0 =3D 1 + And(Local0, SPON, Local0) // Turns the Power "ON" + } Else { // Power Slot "OFF" + Or(Local0, SPOF, Local0) // Turns the Power "OFF" + } + HPCC(Local0) + } + + //;*********************************************************************= ***; + //; _OST Methods to indicate that the device Eject/insert request is + //; pending, OS could not complete it + //; + //; Input: Arg0 - Value used in Notify to OS + //; 0x00 - card insert + //; 0x03 - card eject =20 + //; Arg1 - status of Notify + //; 0 - success + //; 0x80 - Ejection not supported by OSPM + //; 0x81 - Device in use + //; 0x82 - Device Busy + //; 0x84 - Ejection in progress-pending + //;*********************************************************************= ***; + Method(_OST,3,Serialized) { + Switch(And(Arg0,0xFF)) { // Mask to retain low byte + Case(0x03) { // Ejection Request + Switch(ToInteger(Arg1)) { + Case(Package() {0x80, 0x81, 0x82, 0x83}) { + // + // Ejection Failure for some reason + // + If (Lnot(PWCC)) { // if slot is powered + PWCM(0x1) // Set PowerIndicator to ON + Store(0x1,ABIE) // Set AttnBtn Interrupt ON + } + } + } + } + } + } // End _OST + + //;*********************************************************************= ***; + //; Eject Control Methods to indicate that the device is hot-ejectable a= nd + //; should "eject" the device. + //; + //; Input: Arg0 - Not use. + //; + //;*********************************************************************= ***; + Method(EJ02, 1){ + Store(0xFF, IO80) + Store(SCTL, Local0) // Get IOH Port 9/SLot3 Control state + if( LNot( LEqual( ATID, 1))) { // Check if Attention LED is not solid= "ON" + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits + Or(Local0, ALBL, Local0) // Set the Attention Indicator to bli= nk + } + HPCC(Local0) // issue command + + Store(SCTL, Local0) // Get IOH Port 9/SLot3 Control state + Or(Local0, SPOF, Local0) // Set the Power Controller Control to= Power Off + HPCC(Local0) + + Store(SCTL, Local0) // Get PEXH Port 9/SLot3 Control state + Or(Local0, PLOF, Local0) // Set the Power Indicator to Off. + HPCC(Local0) + } // End of EJ02 + + //;*********************************************************************= ***; + //; PM_PME Wake Handler for Slot 3 only + //; + //; Input: Arg0 - Slot Number + //; + //;*********************************************************************= ***; + Method(PMEH,1){ // Handler for PCI-E PM_PME Wake Event= /Interrupt (GPI xxh) + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events + If(ABPS) { + Store (Arg0, IO80) // Send slot number to Port 80 + Store(0x1, ABPS) // Clear the interrupt status + Sleep(200) // delay 200ms + } + } + Return (0xff) // Indicate that this controller did n= ot interrupt + } // End of Method PMEH + + //;*********************************************************************= ***; + //; Hot-Plug Handler for an IIO PCIe root port slot + //; + //; Input: Arg0 - Slot Numnber (not used) + //; Output:=20 + //; 0xFF - No hotplug event detected + //; 0x03 - Eject Request detected + //; 0x00 - Device Presence Changed + //; + //;*********************************************************************= ***; + Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/In= terupt Called from \_SB.GPE._L01() + + If (LEqual(Zero,DVPS)) { + Return (0xff) // Do nothing if root port is not "Pre= sent and Hot-plugable" + } + + Store(0x22, IO80) + Sleep(100) + Store(0,CCIE) // Disable command interrupt + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events + Store(0x3A, IO80) + Sleep(10) + Store(PP3H(0x0), Local0) // Call the Slot 3 Hot plug Interrupt = Handler + Return(Local0) // Return PP2H information + } + Else{ + Return (0xff) // Indicate that this controller did n= ot interrupt + } + Store(0x2F, IO80) + Sleep(10) + } // End of Method HPEH + + //;*********************************************************************= ***; + //; Interrut Event Handler + //; + //; Input: Arg0 - Slot Numnber + //; + //;*********************************************************************= ***; + Method(PP3H,1){ // Slot 3 Hot plug Interrupt Handler + // + // Check for the Atention Button Press, Slot Empty/Presence, Power Con= troller Control. + // + Sleep(200) // HW Workaround for AttentionButton= Status to stabilise + If(ABPS) { // Check if Attention Button Pressed= for Device 4 + If(LNot(PRDS)) { // See if nothing installed (no card= in slot) + PWSL(0x0) // make sure Power is Off + PWCM(0x3) // Set Power Indicator to "OFF" + // + // Check for MRL here and set attn indicator accordingly + // + If(LEqual(MSSC,MRLS)) { // Standby power is on - MRL closed + ATCM(0x2) // Set Attention Indicator to "BLINK" + } else { // Standby power is off - MRL open + ATCM(0x3) // set attention indicator "OFF" + } + Store(0x0, ABIE) // set Attention Button Interrupt to= disable + Store(0x1, ABPS) // Clear the interrupt status + Sleep(200) // delay 200ms + Return(0xff) // Attn Button pressed without card = in slot. Do nothing + } + // + // Card is present in slot so.... + // + Store(0x0, ABIE) // set Attention Button Interrupt to= disable + // Attn Btn Interrupt has to be enab= led only after an insert oprn + Store(0x1, ABPS) // Clear the interrupt status + Sleep(200) // delay 200ms + // + // Check for MRL here - only if SPWR is OFF blink AttnInd and retun = 0xff + // + If(LNot(LEqual(MSSC,MRLS))) { // Standby power is off + PWSL(0x0) // make sure Power is Off + PWCM(0x3) // Set Power Indicator to "OFF" + ATCM(0x2) // Set Attention Indicator to "BLINK" + Return(0xff) // Attn Button pressed with card in = slot, but MRL open. Do nothing + } + //Card Present, if StandbyPwr is ON proceed as below with Eject Sequ= ence + If(PWCC) { // Slot not Powered + PWCM(0x3) // Set Power Indicator to "OFF" + ATCM(0x2) // Set Attention Indicator to "BLINK" + Return(0xff) // Attn Button pressed with card in = slot, MRL closed, Slot not powered. Do nothing + } else { // See if Slot is already Powered + PWCM(0x2) // Set power Indicator to BLINK + Sleep(600) // Wait 100ms + Store(600, Local0) // set 5 second accumulator to 0 + Store(0x1, ABPS) // Clear the interrupt status + Sleep(200) // delay 200ms + While(LNot(ABPS)) { // check for someone pressing Attent= ion + Sleep(200) // Wait 200ms + Add(Local0, 200, Local0) + If(LEqual(5000, Local0)) { // heck if 5sec has passed without p= ressing attnetion btn + Store(0x1, ABPS) // Clear the interrupt status + Sleep(200) // delay 200ms=20 + Return (0x3) // continue with Eject request + } + } + PWCM(0x1) // Set power Indicator baCK "ON" + Store(0x1, ABPS) // Clear the Attention status + Sleep(200) // delay 200ms + Store(0x1, ABIE) // set Attention Button Interrupt to= enable + Return (0xff) // do nothing and abort + } + } // End if for the Attention Button Hot Plug Interrupt. + + If(PFDS) { // Check if Power Fault Detected + Store(0x1, PFDS) // Clear the Power Fault Status + PWSL(0x0) // set Power Off + PWCM(0x3) // set power indicator to OFF + ATCM(0x1) // set attention indicator "ON" + Return(0x03) // Eject request. + } // End if for the Power Fault Interrupt. + + If(MSCS) { // Check interrupt caused by the MRL= Sensor + Store(0x1, MSCS) // Clear the MRL Status + If(LEqual(MSSC,MRLS)) { // Standby power is on - MRL closed + If(PRDS) { // Card is Present + // Slot Power is Off, so power up th= e slot + ATCM(0x3) // Set Attention Indicator to off + PWCM(0x2) // Set Power Indicator to Blink + Sleep(600) // Wait 100ms + Store(600, Local0) // set 5 second accumulator to 0 + Store(0x1, ABPS) // Clear the interrupt status + While(LNot(ABPS)) { // check for someone pressing Attent= ion + Sleep(200) // Wait 200ms + Add(Local0, 200, Local0) + If(LEqual(5000, Local0)) { // Check if 5 sec elapsed + Store(0x1, ABIE) // Enable Attention button interrupt + ATCM(0x3) // set attention indicator "OFF" + PWSL(0x1) // Power the Slot + Sleep(500) // Wait for .5 Sec for the Power to = Stabilize. + // Check for the Power Fault Detection + If(LNot(PFDS)) { // No Power Fault + PWCM(0x1) // Set Power Indicator to = "ON" + // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slo= t Clock (GPIO16) + // Notify the OS to load the Driver for the card + Store(0x00, Local1) + Store(0x1, ABIE) // Enable Attention button= interrupt + } Else { // Power Fault present + PWSL(0x0) // set Slot Power Off + PWCM(0x3) // set power indicator to = OFF + ATCM(0x1) // set attention indicator= "ON" + // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Sl= ot Clock (GPIO16) + Store(0x03, Local1) // Eject request. + } // End if for the Slot Pow= er Fault + Store(0x1, ABPS) // Clear the Attention sta= tus + Sleep(200) // delay 200ms + Return(Local1) + } + } + // + // someone pressed Attention Button + // + Store(0x1, ABPS) // Clear the Attention status + Sleep(200) // delay 200ms + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + ATCM(02) // Set Attention Indicator to "BLINK" + Return(0xff) // leave it off + // End of Insert sequence + } + //MRL is closed, Card is not present + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + ATCM(02) // Set Attention Indicator to "BLINK" + Return(0xff) // leave it off + } else { // MRL is open i.e Stdby power is turn= ed off + If(PRDS) { + //card present MRL switched off + ATCM(0x2) // Set Attention Indicator to "BLINK" + If(Lnot(PWCC)) { // If slot is powered + // This event is not supported and someone has opened the MRL = and dumped the power + // on the slot with possible pending transactions. This could= hose the OS. + // Try to Notify the OS to unload the drivers. + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + Return(0x03) // Eject request. + } else { // Slot not powered, MRL is opened, ca= rd still in slot - Eject not fully complete + Return(0xFF) + } + } + //no card present and Stdby power switched off, turn AI off + ATCM(0x3) // Set Attention Indicator to "OFF" + Return(0xff) // leave it off + } // End of MRL switch open/close state + } // End of MRL Sensor State Change + + If(PDCS) { // Check if Presence Detect Changed St= atus + Store(0x1, PDCS) // Clear the Presence Detect Changed S= tatus + If(LNot(PRDS)) { // Slot is Empty + PWSL(0x0) // Set Slot Power "OFF" + PWCM(0x3) // set power indicator to "OFF" + If(LEqual(MSSC,MRLS)) { // If Standby power is on + ATCM(0x2) // Set Attention Indicator to "Blink" + } else { + ATCM(0x3) // Set Attention Indicator to "OFF" + } + Return(0xFF) // Do nothing + } Else { // Slot Card is inserted + // Irrespective of MRL state blink indicator + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + ATCM(0x2) // Set Attention Indicator to "Blink" + Return(0xFF) // Do nothing + } + } // End if for the Presence Detect Changed Hot Plug Interrupt. + Return(0xff) // should not get here, but do device check if it does. + } // End of method PP5H + // + // End of hotplug code + // + + Device(H000) { + Name(_ADR, 0x00000000) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H001) { + Name(_ADR, 0x00000001) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H002) { + Name(_ADR, 0x00000002) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H003) { + Name(_ADR, 0x00000003) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H004) { + Name(_ADR, 0x00000004) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H005) { + Name(_ADR, 0x00000005) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H006) { + Name(_ADR, 0x00000006) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H007) { + Name(_ADR, 0x00000007) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.= asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl new file mode 100644 index 0000000000..af3f6581db --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl @@ -0,0 +1,32 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// ITSS +// Define the needed ITSS registers used by ASL on Interrupt +// mapping. + +scope(\_SB){ + OperationRegion(ITSS, SystemMemory, 0xfdc43100, 0x208) + Field(ITSS, ByteAcc, NoLock, Preserve) + { + PARC, 8, + PBRC, 8, + PCRC, 8, + PDRC, 8, + PERC, 8, + PFRC, 8, + PGRC, 8, + PHRC, 8, + Offset(0x200), // Offset 3300h ITSSPRC - ITSS Power Reduction Con= trol + , 1, + , 1, + SCGE, 1, // ITSSPRC[2]: 8254 Static Clock Gating Enable (82= 54CGE) + + } +} + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mothe= r.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi new file mode 100644 index 0000000000..863518b3a5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi @@ -0,0 +1,202 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Device (DMAC) { + Name (_HID, EISAID("PNP0200")) + Name (_CRS,ResourceTemplate() { + IO(Decode16, 0x0, 0x0, 0, 0x10) + IO(Decode16, 0x81, 0x81, 0, 0x3) + IO(Decode16, 0x87, 0x87, 0, 0x1) + IO(Decode16, 0x89, 0x89, 0, 0x3) + IO(Decode16, 0x8f, 0x8f, 0, 0x1) + IO(Decode16, 0xc0, 0xc0, 0, 0x20) + DMA(Compatibility,NotBusMaster,Transfer8) {4} + }) +} + +Device (RTC) { + Name (_HID,EISAID("PNP0B00")) + Name (_CRS,ResourceTemplate() { + IO(Decode16,0x70,0x70,0x01,0x02) + IO(Decode16,0x74,0x74,0x01,0x04) + IRQNoFlags(){8} + }) +} + +Device (PIC) { + Name (_HID,EISAID("PNP0000")) + Name (_CRS,ResourceTemplate() { + IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes all = aliases + IO(Decode16,0xA0,0xA0,0x01,0x1E) + IO(Decode16,0x4D0,0x4D0,0x01,0x02) + }) +} + +Device (FPU) { + Name (_HID,EISAID("PNP0C04")) + Name (_CRS,ResourceTemplate() { + IO(Decode16,0xF0,0xF0,0x01,0x1) + IRQNoFlags(){13} + }) +} + +Device(TMR) +{ + Name(_HID,EISAID("PNP0100")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16,0x40,0x40,0x01,0x04) + IO(Decode16,0x50,0x50,0x01,0x04) // alias + IRQNoFlags(){0} + }) +} + +Device (SPKR) { + Name (_HID,EISAID("PNP0800")) + Name (_CRS,ResourceTemplate() { + IO(Decode16,0x61,0x61,0x01,0x01) + }) +} + +// +// all "PNP0C02" devices- pieces that don't fit anywhere else +// +Device(XTRA) { + Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices + Name(_CRS, + ResourceTemplate() { + IO(Decode16,0x500,0x500,0x01,0x40) // GPIO space, I= CH5 + IO(Decode16,0x400,0x400,0x01,0x80) // PM IO, ICH5 + IO(Decode16,0x92,0x92,0x01,0x01) // INIT & Fast A= 20 port, ICH5 + // + // Resource conflict with COM Port + // + //IO(Decode16,0x680,0x680,0x01,0x80) // Runtime reg= isters, National SIO + IO(Decode16,0x10,0x10,0x01,0x10) + IO(Decode16,0x72,0x72,0x01,0x02) + IO(Decode16,0x80,0x80,0x01,0x01) + IO(Decode16,0x84,0x84,0x01,0x03) + IO(Decode16,0x88,0x88,0x01,0x01) + IO(Decode16,0x8c,0x8c,0x01,0x03) + IO(Decode16,0x90,0x90,0x01,0x10) + // + // SMBus decode range=20 + // + IO(Decode16,0x540,0x540,0x01,0x40) + // + // Pilot Mail Box decode range + // + IO(Decode16,0x600,0x600,0x01,0x20) + // + // BMC KCS decode range + // + IO(Decode16,0xCA0,0xCA0,0x01,0x6) + // + // Performance Status and control ports decode range + // + IO(Decode16,0x880,0x880,0x01,0x4) + + //IO Descriptor added for range 800-81f for S501302 + IO(Decode16,0x800,0x800,0x01,0x20) + //IO Descriptor added for range 2F8-2FF for S501706 + //IO(Decode16,0x2F8,0x2F8,0x01,0x08) + //IO(Decode16,0x60,0x60,0x01,0x01) + //IO(Decode16,0x64,0x64,0x01,0x01) + + //PCH_ACPI_FLAG: RCBA is not supported in SPT + // + // RCBA memory range + // + //Memory32Fixed (ReadOnly, 0xFED1C000, 0x6FFFF) // ICH9 bios spec se= ction 5.10 - reserved memory address space. + Memory32Fixed (ReadOnly, 0xFED1C000, 0x24000) // ICH9 bios spec sect= ion 5.10 - reserved memory address space. + // Leave FED40000-FED45000 for TPM + Memory32Fixed (ReadOnly, 0xFED45000, 0x47000) // ICH9 bios spec sect= ion 5.10 - reserved memory address space. + + // + // FLASH range + // + Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000) //16MB as per IIO sp= ec + + // + // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) + // + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) + + // + // HECI range, 32 bytes from HECI1_BASE_ADDRESS (0xFE90_0000 to 0xFE= 90_001F) + // + //Memory32Fixed (ReadWrite, 0xFE900000, 0x20) + Memory32Fixed (ReadWrite, 0xFED12000, 0x10) + + // + // HECI range, 32 bytes from HECI2_BASE_ADDRESS (0xFEA0_0000 to 0xFE= A0_001F) + // + //Memory32Fixed (ReadWrite, 0xFEA00000, 0x20) + Memory32Fixed (ReadWrite, 0xFED12010, 0x10) + + // + // IIO RCBA memory range + // + Memory32Fixed (ReadOnly, 0xFED1B000, 0x1000) + } + ) +} + +// +// High Performance Event Timer (HPET) +// +Device (HPET) { + Name (_HID, EisaId ("PNP0103")) + + Method (_STA, 0, NotSerialized) { + If (\HPTE) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Name (CRS0, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) + }) + + Name (CRS1, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFED01000, 0x00000400) + }) + + Name (CRS2, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFED02000, 0x00000400) + }) + + Name (CRS3, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFED03000, 0x00000400) + }) + + // + // Owning control method can't be re-entrant, so _CRS must be Serialized + // + Method (_CRS, 0, Serialized) { + Switch (ToInteger(\HPTB)) { + Case (0xFED00000) { + Return (CRS0) + } + + Case (0xFED01000) { + Return (CRS1) + } + + Case (0xFED02000) { + Return (CRS2) + } + + Case (0xFED03000) { + Return (CRS3) + } + } + Return (CRS0) + } +} \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.as= i b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi new file mode 100644 index 0000000000..532e5ba448 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi @@ -0,0 +1,145 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope (\_SB) { + + Name (XCNT, 0) + Name (OSYS, 0) // Global variable for type of OS. + + // + // Device specific method + // + Method (_DSM, 4, Serialized) { + If (LEqual(Arg0,ToUUID("663E35AF-CC10-41A4-88EA-5470AF055295"))){ + + // L1 DIR POINTER + Switch (ToInteger(Arg2)) { + // + //Function 0: Return supported functions, based on revision + // + Case(0) + { + Switch (ToInteger(Arg1)) { + Case(0) {=20 + If (Lequal(EMCA,1)) + { + Return ( Buffer() {0x3} ) + } + Else + { + Return (Buffer() {0}) + } + } + } + =20 + }=20 + // + // Function 1:=20 + // + Case(1) {Return (LDIR) } + Default { } + }=20 + } + + Return (Buffer() {0}) + } + + Method (_INI) { + + If (CondRefOf (_OSI)) { + + If (\_OSI ("Windows 2001.1 SP1")) { + Store (5, OSYS) // Windows Server 2003 SP1 + } + + If (\_OSI ("Windows 2001.1")) { + Store (6, OSYS) // Windows Server 2003 + } + + If (\_OSI ("Windows 2001 SP2")) { + Store (7, OSYS) // Windows XP SP2 + } + + If (\_OSI ("Windows 2001")) { + Store (8, OSYS) // Windows XP + } + + If (\_OSI ("Windows 2006.1")) { + Store (9, OSYS) // Windows Server 2008 + } + + If (\_OSI ("Windows 2006 SP1")) { + Store (10, OSYS) // Windows Vista SP1 + }=20 + + If (\_OSI ("Windows 2006")) { + Store (11, OSYS) // Windows Vista + } + + If (\_OSI ("Windows 2009")) { + Store (12, OSYS) // Windows Server 2008 R2 & Windows 7 + } + + If (\_OSI ("Windows 2012")) { + Store (13, OSYS) // Windows Server 2012 & Windows 8 + } + + If (\_OSI ("Windows 2013")) { + Store (14, OSYS) // Windows Server 2012 R2 & Windows 8.1 + } + + If (\_OSI ("Windows 2015")) { + Store (15, OSYS) // Windows 10 & Windows Server Technical Pre= view + } + + If (\_OSI ("Windows 2016")) { + Store (16, OSYS) // Windows 10, version 1607 + } + + If (\_OSI ("Windows 2017")) { + Store (17, OSYS) // Windows 10, version 1703 + } + + // + // Check Linux also + // + If (\_OSI ("Linux")) { + Store (1, OSYS) + } + + If (\_OSI ("FreeBSD")) { + Store (2, OSYS) + } + + If (\_OSI ("HP-UX")) { + Store (3, OSYS) + } + + If (\_OSI ("OpenVMS")) { + Store (4, OSYS) + } + + // + // Running WinSvr2012, Win8, or later? + // + If (LGreaterEqual (\_SB.OSYS, 13)) { + // + // It is Svr2012 or Win8 + // Call xHCI device to switch USB ports over + // unless it has been done already + // + If (LEqual (XCNT, 0)) { + Store (0x84, IO80) + Increment (XCNT) + } + } Else { + Store (\_SB.OSYS, IO80) + } + } =20 + } // End Method (_INI) + =20 +} // End Scope (_SB) diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.a= si b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi new file mode 100644 index 0000000000..6b9ae9b3e7 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi @@ -0,0 +1,10 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// I/O controller miscellaneous=20 +// diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchAp= ic.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.a= si new file mode 100644 index 0000000000..57bc9f2ba1 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi @@ -0,0 +1,17 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Device(APIC) { + Name (_HID,EISAID("PNP0003")) // APIC resources + Name (_CRS, ResourceTemplate() { + // + // APIC range(0xFEC0_0000 to 0xFECF_FFFF) + // + Memory32Fixed (ReadOnly, 0xFEC00000, 0x100000) // IO APIC =20 + } + ) +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEh= ci1.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1= .asi new file mode 100644 index 0000000000..c25af50ed8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi @@ -0,0 +1,91 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Name (OPAC, 0) + +OperationRegion(PWKE,PCI_Config,0x54,0x18) +Field(PWKE,DWordAcc,NoLock,Preserve) +{ + , 8, + PMEE, 1, // PWR_CNTL_STS.PME_En + , 6, + PMES, 1, // PWR_CNTL_STS.PME_Sts + Offset (0x0E), + , 1, + PWUC, 10 // Port Wake Up Capability Mask +} + +// +// Indicate access to OperationRegions is enabled/disabled +// +Method (_REG, 2) +{ + // If OperationRegion ID =3D PCI_Config + // + If (LEqual (Arg0, 2)) + { + // If access is enabled + // + If (LEqual(Arg1, 1)) + { + // Set local flag + // + Store (One, OPAC) + } + Else + { + // Clear local flag + // + Store (One, OPAC) + } + } +} + +// +// Enable/disable ports on this controller to wake the system +// +Method (_PSW,1) +{ + If (Arg0) + { + Store (Ones,PWUC) + } + Else + { + Store (0,PWUC) + } +} + +// +// Initialization for this controller +// +Method (_INI, 0) +{ + // If access to OperationRegion is enabled + // + If (LEqual (OPAC, One)) + { + Store (1, PMES) // clear PME status + Store (0, PMEE) // clear PME enable + } +} + +// The CRB leaves the USB ports on in S3/S4 to allow +// the ability to Wake from USB. Therefore, define +// the below control methods to state D2 entry during +// the given S-State. + +Method(_S3D,0) +{ + Return(2) +} + +Method(_S4D,0) +{ + Return(2) +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEh= ci2.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2= .asi new file mode 100644 index 0000000000..8caae9bbac --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi @@ -0,0 +1,92 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Name (OPAC, 0) + +OperationRegion(PWKE,PCI_Config,0x54,0x18) +Field(PWKE,DWordAcc,NoLock,Preserve) +{ + , 8, + PMEE, 1, // PWR_CNTL_STS.PME_En + , 6, + PMES, 1, // PWR_CNTL_STS.PME_Sts + Offset (0x0E), + , 1, + PWUC, 10 // Port Wake Up Capability Mask +} + +// +// Indicate access to OperationRegions is enabled/disabled +// +Method (_REG, 2) +{ + // If OperationRegion ID =3D PCI_Config + // + If (LEqual (Arg0, 2)) + { + // If access is enabled + // + If (LEqual(Arg1, 1)) + { + // Set local flag + // + Store (One, OPAC) + } + Else + { + // Clear local flag + // + Store (One, OPAC) + } + } +} + +// +// Enable/disable ports on this controller to wake the system +// +Method (_PSW,1) +{ + If (Arg0) + { + Store (Ones,PWUC) + } + Else + { + Store (0,PWUC) + } +} + +// +// Initialization for this controller +// +Method (_INI, 0) +{ + // If access to OperationRegion is enabled + // + If (LEqual (OPAC, One)) + { + Store (1, PMES) // clear PME status + Store (0, PMEE) // clear PME enable + } +} + +// The CRB leaves the USB ports on in S3/S4 to allow +// the ability to Wake from USB. Therefore, define +// the below control methods to state D2 entry during +// the given S-State. + +Method(_S3D,0) +{ + Return(2) +} + +Method(_S4D,0) +{ + Return(2) +} + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGb= e.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl new file mode 100644 index 0000000000..8ae7c7b8be --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl @@ -0,0 +1,17 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/// +/// Gbe Ethernet ASL methods and structures=20 +/// + + // + // GPE bit 13 indicates wake from this device, can wakeup from S4 state + // + Method(_PRW, 0) { + Return(Package() {13, 4}) + } \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLp= c.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi new file mode 100644 index 0000000000..d62d5044b4 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi @@ -0,0 +1,22 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Define bits in LPC bridge config space +// (\_SB.PCI0.LPC0) +// +OperationRegion (LPCB, PCI_Config, 0x00, 0x100) +Field (LPCB, DWordAcc, NoLock, Preserve) +{ + Offset (0xAC), + , 16, + XSMB, 1 // set when OS routes USB ports to xHCI in SmartAuto mode so = next POST will know +} + +#include "IrqLink.asl" // PCI routing control methods +#include "Mother.asi" // Static motherboard device resource declara= tion + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSa= ta.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.a= si new file mode 100644 index 0000000000..a74c9b9aae --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi @@ -0,0 +1,807 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + OperationRegion (IDER,PCI_Config,0x40,0x20) + Field (IDER, AnyAcc, NoLock, Preserve)=20 + { + PFT0 , 1 , // Drive 0 Fast Timing Bank (TIME0) + PIE0 , 1 , // Drive 0 IORDY Sample Point Enable (IE0) + PPE0 , 1 , // Drive 0 Prefetch/Posting Enable (PPE0) + PDE0 , 1 , // Drive 0 DMA Timing Enable (DTE0) + PFT1 , 1 , // Drive 1 Fast Timing Bank (TIME1) + PIE1 , 1 , // Drive 1 IORDY Sample Point Enable (IE1) + PPE1 , 1 , // Drive 1 Prefetch/Posting Enable (PPE1) + PDE1 , 1 , // Drive 1 DMA Timing Enable (DTE1) + PRT0 , 2 , // Drive 0 Recovery Time (RCT) + , 2 , // Reserved + PIP0 , 2 , // Drive 0 IORDY Sample Point (ISP) + PSIT , 1 , // Drive 1 Timing Register Enable (SITRE)=20 + PIDE , 1 , // IDE Decode Enable (IDE) + offset (0x2) , + SFT0 , 1 , // Drive 0 Fast Timing Bank (TIME0) + SIE0 , 1 , // Drive 0 IORDY Sample Point Enable (IE0) + SPE0 , 1 , // Drive 0 Prefetch/Posting Enable (PPE0) + SDE0 , 1 , // Drive 0 DMA Timing Enable (DTE0) + SFT1 , 1 , // Drive 1 Fast Timing Bank (TIME1)=20 + SIE1 , 1 , // Drive 1 IORDY Sample Point Enable (IE1) + SPE1 , 1 , // Drive 1 Prefetch/Posting Enable (PPE1) + SDE1 , 1 , // Drive 1 DMA Timing Enable (DTE1)=20 + SRT0 , 2 , // Drive 0 Recovery Time (RCT) + , 2 , // Reserved + SIP0 , 2 , // Drive 0 IORDY Sample Point (ISP)=20 + SSIT , 1 , // Drive 1 Timing Register Enable (SITRE) + SIDE , 1 , // IDE Decode Enable (IDE)=20 + =20 + PRT1 , 2 , // Drive 1 Recovery Time (RCT)=20 + PIP1 , 2 , // Drive 1 IORDY Sample Point (ISP) + SRT1 , 2 , // Drive 1 Recovery Time (RCT)=20 + SIP1 , 2 , // Drive 1 IORDY Sample Point (ISP)=20 + =20 + offset (0x08) , =20 + =20 + UDM0 , 1 , // Primary Drive 0 Synchronous DMA Mode Enable=20 + UDM1 , 1 , // Primary Drive 1 Synchronous DMA Mode Enable=20 + UDM2 , 1 , // Secondary Drive 0 Synchronous DMA Mode Enable=20 + UDM3 , 1 , // Secondary Drive 1 Synchronous DMA Mode Enable=20 + =20 + offset (0x0A) , + =20 + PCT0 , 2 , // Primary Drive 0 Cycle Time (PCT0) + , 2 , // Reserved + PCT1 , 2 , // Primary Drive 1 Cycle Time (PCT1) + , 2 , // Reserved + SCT0 , 2 , // Secondary Drive 0 Cycle Time (SCT0) + , 2 , // Reserved + SCT1 , 2 , // Secondary Drive 1 Cycle Time (SCT1) + =20 + offset (0x14) , + PCB0 , 1 , // Primary Drive 0 Base Clock (PCB0)=20 + PCB1 , 1 , // Primary Drive 0 Base Clock (PCB0) + SCB0 , 1 , // Secondary Drive 1 Base Clock (SCB0) + SCB1 , 1 , // Secondary Drive 1 Base Clock (SCB1) + PCCR , 2 , // Primary Channel Cable Reporting + SCCR , 2 , // Secondary Channel Cable Reporting + , 4 , // Reserved + PUM0 , 1 , // Primary Drive 0 UDMA 5 Supported + PUM1 , 1 , // Primary Drive 1 UDMA 5 Supported + SUM0 , 1 , // Secondary Drive 0 UDMA 5 Supported + SUM1 , 1 , // Secondary Drive 1 UDMA 5 Supported + PSIG , 2 , // PRIM_SIG_MODE + SSIG , 2 , // SEC_SIG_MODE =20 + } + =20 + // + // Get PIO Timing=20 + // Arg0 Fast PIO Timing=20 + // Arg1 DMA Fast Timing + // Arg2 RCT Timing + // Arg3 ISP Timing + // + + Method(GPIO,4) + { + =20 + If (LEqual (Or (Arg0, Arg1) , 0) ) { + // + // No PIO Timing and DMA Timing support + //=20 + Return (0xFFFFFFFF) + =20 + } Else { + If (And ( LEqual (Arg0, 0) , LEqual (Arg1, 1) ) ) { + // + // Compatible PIO timing support=20 + // + Return (900) =20 + } + } + =20 + //=20 + // Using ISP and RCT timing , PCI Clock =3D 33 Mhz , 30ns per clo= ck + // =20 + Return (Multiply(30,Subtract(9,Add(Arg2,Arg3)))) =20 + } + // + // Get DMA Timing + // Arg0 UDMA Supported + // Arg1 Ata100 + // Arg2 Ata66/33 + // Arg3 Cable report / SATA No mater this input + // Arg4 Cycle Timing + // + Method(GDMA,5) + { + // + // Ultra DMA 66 & 100 need 80 pin conductor + // + If (LEqual (Arg0, 1)) { + // + // Ultra DMA Support + // + If (LEqual (Arg1, 1)) { + //=20 + // ATA100 80 pin conducter support , Ultra DMA 5 Support + // + If (LEqual (Arg4, 2)) { + Return (15) + } =20 + Return (20) + =20 + }=20 + If (LEqual (Arg2, 1)) { + //=20 + // ATA66 80 pin conducter support , Base Clock 66Mhz , 15= ns per clock + // + Return (Multiply(15,Subtract(4,Arg4))) =20 + } + // + // Else Ultra DMA33Mhz Supported only,Base Clock 33Mhz , 30ns= per clock + //=20 + Return (Multiply(30,Subtract(4,Arg4))) =20 + } =20 + // Doesnt support DMA mode + =20 + Return (0xFFFFFFFE) + } + // + // Set Flag + // Arg0 IORDY for drive 0 + // Arg1 Ultra DMA for drive 0 + // Arg2 IORDY for drive 1 + // Arg3 Ultra DMA for drive 1 + // Arg4 indicates chipset can set timing independently for each drive + // =20 + Method(SFLG, 5) + { + // + // The Chipset always support separate timing setting and always s= upport IORDY + // + Store (0, Local0) + Or (Arg1 ,Local0,Local0) + Or (ShiftLeft (Arg0,1) ,Local0, Local0) + Or (ShiftLeft (Arg2,3) ,Local0, Local0) + Or (ShiftLeft (Arg3,2) ,Local0, Local0) =20 + Or (ShiftLeft (Arg4,4) ,Local0, Local0) + Return (Local0) + } + // + // Set PIO Timing + // Arg0 Timing + // Arg1 ATA Device PIO Mode Supported Flag + // Arg2 ATA Device PIO Mode Supported Timing + // + // PIO/Mode Timing + // PIO0/Compatible 900 ns + // PIO2/SW2 240 ns + // PIO3/MW1 180 ns + // PIO4/MW2 120 ns + // + =20 + Method(SPIO , 3) + { + Name(PBUF, Buffer(5) { 0x00,0x00,0x00,0x00,0x00}) + CreateByteField(PBUF, 0, RCT) + CreateByteField(PBUF, 1, ISP) + CreateByteField(PBUF, 2, FAST)=20 + CreateByteField(PBUF, 3, DMAE) =20 + CreateByteField(PBUF, 4, PIOT)=20 + If (LOr (LEqual (Arg0, 0x0), LEqual (Arg0, 0x0FFFFFFFF)) ) { + =20 + Return (PBUF) + } + If (LGreater (Arg0, 240)) { + // + // Compatible timing + // + Store (1, DMAE) // PIO Mode 0 + Store (0, PIOT) // Set to PIO Mode 0 =20 + =20 + } Else { + // + // Fast Timing Enable + // =20 + Store (1, FAST) =20 + =20 + If (And (Arg1, 0x002)) { + // + // ATA Device Supported PIO Mode Report + // + If (And (LEqual (Arg0, 120), And( Arg2 , 0x002) ) ) { + // + // Device support PIO Mode 4 + // =20 + Store (3, RCT) // RCT =3D 1 CLK + Store (2, ISP) // ISP =3D 3 CLK + Store (4, PIOT) // Set to PIO Mode 4=20 + } Else { + If (And (LLessEqual (Arg0, 180), And( Arg2 , 0x001) ) ) { + // + // Device support PIO Mode 3 + // + Store (1, RCT) // RCT =3D 3 CLK + Store (2, ISP) // ISP =3D 3 CLK =20 + Store (3, PIOT) // Set to PIO Mode 3 =20 + } Else { + //=20 + // PIO Mode 2 + //=20 + Store (0, RCT) // RCT =3D 4 CLK + Store (1, ISP) // ISP =3D 4 CLK=20 + Store (2, PIOT) // Set to PIO Mode 2=20 + } + } + } + } + Return (PBUF) =20 + } + // + // Set DMA Timing + // Arg0 Timing + // Arg1 ATA Device PIO Mode Supported Flag + // Arg2 ATA Device PIO Mode Supported Timing + // + // UDMA/Mode Timing=20 + // UDMA5 20 ns + // UDMA4 30 ns + // UDMA3 45 ns + // UDMA2 60 ns + // UDMA1 90 ns + // UDMA0 120 ns + // + =20 + Method(SDMA , 3) + { + Name(PBUF, Buffer(5) { 0x00,0x00,0x00,0x00}) + CreateByteField(PBUF, 0, PCT) + CreateByteField(PBUF, 1, PCB) + CreateByteField(PBUF, 2, UDMT) // ATA 100 Support + CreateByteField(PBUF, 3, UDME) // Ultra DMA Enable + CreateByteField(PBUF, 4, DMAT)=20 + If (LOr (LEqual (Arg0, 0x0), LEqual (Arg0, 0x0FFFFFFFF)) ) { + =20 + Return (PBUF) + } + If (LLessEqual (Arg0, 120)) { + // + // Ultra DMA Supported + // + If (And (Arg1, 0x004)) { + // + // ATA Device Supported UDMA Mode Report + // + Store (1, UDME) =20 + If (And (LEqual (Arg0, 15), And( Arg2 , 0x0040) ) ) { + // + // Ultra DMA 6 + // =20 + Store (1, UDMT) + Store (1, PCB) + Store (2, PCT) + Store (6, DMAT) // Set to UDMA Mode 6 + } Else { =20 + If (And (LEqual (Arg0, 20), And( Arg2 , 0x0020) ) ) { + // + // Ultra DMA 5 + // =20 + Store (1, UDMT) + Store (1, PCB) + Store (1, PCT) + Store (5, DMAT) // Set to UDMA Mode 5 + } Else { + =20 + If (And (LLessEqual (Arg0, 30), And( Arg2 , 0x00010) ) ) { + // + // Ultra DMA 4 + // + Store (1, PCB)=20 + Store (2, PCT) + Store (4, DMAT) // Set to UDMA Mode 4 + =20 + } Else { + =20 + If (And (LLessEqual (Arg0, 45), And( Arg2 , 0x0008) ) ) { + // + // Ultra DMA 3 + // =20 + Store (1, PCB) + Store (1, PCT) + Store (3, DMAT) // Set to UDMA Mode 3 + =20 + } Else { + =20 + If (And (LLessEqual (Arg0, 60), And( Arg2 , 0x0004) ) ) { + // + // Ultra DMA 2 + // + Store (2, PCT) + Store (2, DMAT) // Set to UDMA Mode 2 + } Else { + =20 + If (And (LLessEqual (Arg0, 90), And( Arg2 , 0x0002) ) ) { + // + // Ultra DMA 1 + // =20 + Store (1, PCT) =20 + Store (1, DMAT) // Set to UDMA Mode 1 =20 + } Else { + =20 + If (And (LLessEqual (Arg0, 120), And( Arg2 , 0x0001) ) ) { + // + // Ultra DMA 0 + // =20 + Store (0, DMAT) // Set to UDMA Mode 0 =20 + } =20 + }}}}}} + } + } + Return (PBUF) =20 + } + =20 + + // + // Primary ide channel + // + Device(PRID) + { + Name(_ADR,0) + Name(TDM0, 0) // Drive 0 Ultra DMA Type + Name(TPI0, 0) // Drive 0 PIO Type + Name(TDM1, 0) // Drive 1 Ultra DMA Type + Name(TPI1, 0) // Drive 1 PIO Type + =20 + Method(_GTM) + { + Name(PBUF, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0= 0, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00 }) + + CreateDwordField(PBUF, 0, PIO0) + CreateDwordField(PBUF, 4, DMA0) + CreateDwordField(PBUF, 8, PIO1) + CreateDwordField(PBUF, 12, DMA1) + CreateDwordField(PBUF, 16, FLAG) =20 + =20 + Store ( GPIO (PFT0, PDE0, PRT0, PIP0 ), PIO0) =20 + // + // Setting the Drive1 PIO Timing, check if we use the same tim= ging for + // both Drive0 and Drive1, and if the Drive0 is attached, else= use=20 + // separate timing + // + =20 + If ( And (PSIT, 1) ) { + Store ( GPIO (PFT1, PDE1, PRT1, PIP1 ), PIO1) + } Else { =20 + Store ( GPIO (PFT1, PDE1, PRT0, PIP0 ), PIO1) + } + =20 + If (LEqual (PIO0, 0xFFFFFFFF)) { + Store(PIO0, DMA0) + } Else { + Store ( GDMA(UDM0, PUM0, PCB0,And (PCCR ,0x1), PCT0) , DMA= 0) + If ( LGreater ( DMA0, PIO0)) { + Store(PIO0, DMA0) =20 + } =20 + } + If (LEqual (PIO1, 0xFFFFFFFF)) { + Store(PIO1, DMA1) =20 + } Else { + Store ( GDMA(UDM1, PUM1, PCB1,And (PCCR ,0x2), PCT1) , DMA= 1) + If ( LGreater ( DMA1, PIO1)) { + Store(PIO1, DMA1) + } + } + Store (SFLG (PIE0, UDM0, PIE1, UDM1, 1), FLAG) =20 + =20 + Return (PBUF) + } + =20 + Method(_STM,3) + { + CreateDwordField(Arg0, 0, PIO0) + CreateDwordField(Arg0, 4, DMA0) + CreateDwordField(Arg0, 8, PIO1) + CreateDwordField(Arg0, 12, DMA1) + CreateDwordField(Arg0, 16, FLAG) =20 + =20 + // + // Device 0 Raw data + // + CreateWordField(Arg1, 106, RPS0) // word 53 + CreateWordField(Arg1, 128, IOM0) // word 64 + CreateWordField(Arg1, 176, DMM0) // Word 88 + =20 + // + // Device 1 Raw data + // + CreateWordField(Arg2, 106, RPS1) // word 53 + CreateWordField(Arg2, 128, IOM1) // word 64 + CreateWordField(Arg2, 176, DMM1) // Word 88 + =20 + Name(IOTM, Buffer(5) { 0x00,0x00,0x00,0x00}) + =20 + CreateByteField(IOTM, 0, RCT) + CreateByteField(IOTM, 1, ISP) + CreateByteField(IOTM, 2, FAST)=20 + CreateByteField(IOTM, 3, DMAE) + CreateByteField(IOTM, 4, TPIO) // PIO Type + =20 + Name(DMAT, Buffer(5) { 0x00,0x00,0x00,0x00}) + + CreateByteField(DMAT, 0, PCT) + CreateByteField(DMAT, 1, PCB) + CreateByteField(DMAT, 2, UDMT) // ATA 100 Support + CreateByteField(DMAT, 3, UDME) // Ultra DMA Enable=20 + CreateByteField(DMAT, 4, TDMA) // UDMA Type + =20 + If (And (FLAG , 0x10)) { + Store (1, PSIT) + } + =20 + Store (SPIO (PIO0,RPS0,IOM0), IOTM) + =20 + If (Or (DMAE, FAST)) { + Store (RCT, PRT0) + Store (ISP, PIP0) + Store (FAST, PFT0) + Store (DMAE, PDE0) + Store (TPIO, TPI0) + } + Store (SPIO (PIO1,RPS1,IOM1), IOTM) + =20 + If (Or (DMAE, FAST)) { + Store (FAST, PFT1) + Store (DMAE, PDE1) + Store (TPIO, TPI1) + If (And (PSIT,1)) { + // + // Need set Drive 1 PIO Timing seperate + // =20 + Store (RCT, PRT1) + Store (ISP, PIP1) =20 + } Else { + Store (RCT, PRT0) + Store (ISP, PIP0) + } + } + If (And (FLAG , 0x01)) { + Store (SDMA (DMA0,RPS0,DMM0), DMAT) + Store (PCT , PCT0) + Store (PCB , PCB0) + Store (UDME, UDM0) + Store (UDMT, PUM0) + Store (TDMA, TDM0) + } Else { + Store (0, UDM0) + } + =20 + If (And (FLAG , 0x04)) { + Store (SDMA (DMA1,RPS1,DMM1), DMAT) + Store (PCT , PCT1) + Store (PCB , PCB1) + Store (UDME, UDM1) + Store (UDMT, PUM1) + Store (TDMA, TDM1) + } Else { + Store (0, UDM1) + } =20 + // + // Check IORDY Support=20 + // + If (And (FLAG , 0x2)) {=20 + Store (1 , PIE0) + } + If (And (FLAG , 0x8)) {=20 + Store (1 , PIE1) + } + =20 + } + Device(MAST) + { + Name(_ADR,0) + Method(_GTF) + { + // + // Set ATA Device to corresponding Mode + // + Name(ATA0, Buffer(14) + { 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF }) + =20 + CreateByteField(ATA0,1,PIO0) // PIO0 =3D PIO Mode, Drive 0 + CreateByteField(ATA0,8,DMA0) // DMA0 =3D DMA Mode, Drive 0 + =20 + =20 + Store (TPI0, PIO0) // Type we Already get + =20 + Or (PIO0, 0x08 ,PIO0) + =20 + If ( And (UDM0, 1)) { + Store (TDM0, DMA0) // Ultra DMA + Or (DMA0, 0x40, DMA0) + } Else { + Store (TPI0, DMA0) // Use PIO Timing + If ( LNotEqual (DMA0, 0)) { + Subtract(DMA0, 2, DMA0) + } + Or (DMA0, 0x20, DMA0) + } + Return (ATA0) + } =20 + } + Device(SLAV) + { + Name(_ADR,1) + Method(_GTF) + { + // + // Set ATA Device to corresponding Mode + // + Name(ATA1, Buffer(14) + { 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF }) + =20 + CreateByteField(ATA1,1,PIO1) // PIO0 =3D PIO Mode, Drive 0 + CreateByteField(ATA1,8,DMA1) // DMA0 =3D DMA Mode, Drive 0 + =20 + Store (TPI1, PIO1) // Type we Already get + =20 + Or (PIO1, 0x08 ,PIO1) + =20 + If ( And (UDM1, 1)) { + Store (TDM1, DMA1) // Ultra DMA + Or (DMA1, 0x40, DMA1) + } Else { + Store (TPI1, DMA1) // Use PIO Timing + If ( LNotEqual (DMA1, 0)) { + Subtract(DMA1, 2, DMA1) + } + Or (DMA1, 0x20, DMA1) + } + Return(ATA1) + } =20 + } + } + // + // Secondary SATA channel + // + Device(SECD) + { + Name(_ADR,1) + Name(TDM0, 0) + Name(TPI0, 0) + Name(TDM1, 0) + Name(TPI1, 0) + =20 + Name(DMT1, Buffer(5) { 0x00,0x00,0x00,0x00}) + Name(DMT2, Buffer(5) { 0x00,0x00,0x00,0x00}) + Name(POT1, Buffer(5) { 0x00,0x00,0x00,0x00}) =20 + Name(POT2, Buffer(5) { 0x00,0x00,0x00,0x00}) + =20 + Name(STMI, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00 }) + =20 + Method(_GTM) + { + Name(PBUF, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0= 0, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00 }) + + CreateDwordField(PBUF, 0, PIO0) + CreateDwordField(PBUF, 4, DMA0) + CreateDwordField(PBUF, 8, PIO1) + CreateDwordField(PBUF, 12, DMA1) + CreateDwordField(PBUF, 16, FLAG) + =20 + Store ( GPIO (SFT0, SDE0, SRT0, SIP0 ), PIO0) =20 + // + // Setting the Drive1 PIO Timing, check if we use the same tim= ging for + // both Drive0 and Drive1, and if the Drive0 is attached, else= use=20 + // separate timing + // + If ( And (SSIT, 1) ) { + Store ( GPIO (SFT1, SDE1, SRT1, SIP1 ), PIO1) + } Else { =20 + Store ( GPIO (SFT1, SDE1, SRT0, SIP0 ), PIO1) + } + =20 + If (LEqual (PIO0, 0xFFFFFFFF)) { + Store(PIO0, DMA0) + } Else { + Store ( GDMA(UDM2, SUM0, SCB0,And (SCCR ,0x1), SCT0) , DMA= 0) + If ( LGreater ( DMA0, PIO0)) { + Store(PIO0, DMA0) + } + } + =20 + If (LEqual (PIO1, 0xFFFFFFFF)) { + Store(PIO1, DMA1) =20 + } Else { + Store ( GDMA(UDM3, SUM1, SCB1,And (SCCR ,0x2), SCT1) , DMA= 1) + If ( LGreater ( DMA1, PIO1)) { + Store(PIO1, DMA1) + } + } + =20 + Store (SFLG (SIE0, UDM2, SIE1, UDM3, 1), FLAG) + =20 + Return (PBUF) + } + Method(_STM,3) + { + CreateDwordField(Arg0, 0, PIO0) + CreateDwordField(Arg0, 4, DMA0) + CreateDwordField(Arg0, 8, PIO1) + CreateDwordField(Arg0, 12, DMA1) + CreateDwordField(Arg0, 16, FLAG) + =20 + Store (Arg0, STMI) + // + // Device 0 Raw data + // + CreateWordField(Arg1, 106, RPS0) // word 53 + CreateWordField(Arg1, 128, IOM0) // word 64 + CreateWordField(Arg1, 176, DMM0) // Word 88 + =20 + // + // Device 1 Raw data + // + CreateWordField(Arg2, 106, RPS1) // word 53 + CreateWordField(Arg2, 128, IOM1) // word 64 + CreateWordField(Arg2, 176, DMM1) // Word 88 + =20 + Name(IOTM, Buffer(5) { 0x00,0x00,0x00,0x00}) + + CreateByteField(IOTM, 0, RCT) + CreateByteField(IOTM, 1, ISP) + CreateByteField(IOTM, 2, FAST)=20 + CreateByteField(IOTM, 3, DMAE) + CreateByteField(IOTM, 4, TPIO) // PIO Type + + Name(DMAT, Buffer(5) { 0x00,0x00,0x00,0x00}) + + CreateByteField(DMAT, 0, PCT) + CreateByteField(DMAT, 1, PCB) + CreateByteField(DMAT, 2, UDMT) // ATA 100 Support + CreateByteField(DMAT, 3, UDME) // Ultra DMA Enable=20 + CreateByteField(DMAT, 4, TDMA) // UDMA Type + + If (And (FLAG , 0x10)) { + Store (1, SSIT) + } + =20 + // + // Get Timing and Flag Setting + // =20 + Store (SPIO (PIO0,RPS0,IOM0), IOTM) + // + // If no drive0 connect, do nothing to program Drive0 timing + // + If (Or (DMAE, FAST)) { + Store (RCT, SRT0) + Store (ISP, SIP0) + Store (FAST, SFT0) + Store (DMAE, SDE0) + Store (TPIO, TPI0) + } =20 + =20 + Store (SPIO (PIO1,RPS1,IOM1), IOTM) + =20 + Store (IOTM,POT2) + =20 + If (Or (DMAE, FAST)) { + Store (FAST, SFT1) + Store (DMAE, SDE1) + Store (TPIO, TPI1) + If (And (SSIT,1)) { + // + // Need set Drive 1 PIO Timing separately + // =20 + Store (RCT, SRT1) + Store (ISP, SIP1) + } Else { + Store (RCT, SRT0) + Store (ISP, SIP0) + }=20 + } + =20 + If (And (FLAG , 0x01)) { + Store (SDMA (DMA0,RPS0,DMM0), DMAT) + Store (PCT , SCT0) + Store (PCB , SCB0) + Store (UDME , UDM2) + Store (UDMT , SUM0) + Store (TDMA, TDM0) + } Else { + Store (0, UDM2) + } + If (And (FLAG , 0x04)) { + Store (SDMA (DMA1,RPS1,DMM1), DMAT) + Store (PCT , SCT1) + Store (PCB , SCB1) + Store (UDME , UDM3) + Store (UDMT , SUM1) + Store (TDMA , TDM1) + } Else { + Store (0, UDM3) + } + // + // Check IORDY Support=20 + // + If (And (FLAG , 0x2)) {=20 + Store (1 , SIE0) + } + If (And (FLAG , 0x8)) {=20 + Store (1 , SIE1) + } + =20 + } + Device(MAST) + { + Name(_ADR,0) + Method(_GTF) + { + // + // Set ATA Device to corresponding Mode + // + Name(ATA0, Buffer(14) + { 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF }) + =20 + CreateByteField(ATA0,1,PIO0) // PIO0 =3D PIO Mode, Drive 0 + CreateByteField(ATA0,8,DMA0) // DMA0 =3D DMA Mode, Drive 0 + =20 + Store (TPI0, PIO0) // Type we Already get + =20 + Or (PIO0, 0x08 ,PIO0) + =20 + If ( And (UDM2, 1)) { + Store (TDM0, DMA0) // Ultra DMA + Or (DMA0, 0x40, DMA0) + } Else { + Store (TPI0, DMA0) // Use PIO Timing + If ( LNotEqual (DMA0, 0)) { + Subtract(DMA0, 2, DMA0) + } + Or (DMA0, 0x20, DMA0) + } + Return (ATA0) + } =20 + } + Device(SLAV) + { + Name(_ADR,1) + Method(_GTF) + { + // + // Set ATA Device to corresponding Mode + // + Name(ATA1, Buffer(14) + { 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF }) + =20 + CreateByteField(ATA1,1,PIO1) // PIO0 =3D PIO Mode, Drive 0 + CreateByteField(ATA1,8,DMA1) // DMA0 =3D DMA Mode, Drive 0 + =20 + Store (TPI1, PIO1) // Type we Already get + =20 + Or (PIO1, 0x08 ,PIO1) + =20 + If ( And (UDM3, 1)) { + Store (TDM1, DMA1) // Ultra DMA + Or (DMA1, 0x40, DMA1) + } Else { + Store (TPI1, DMA1) // Use PIO Timing + If ( LNotEqual (DMA1, 0)) { + Subtract(DMA1, 2, DMA1) + } + Or (DMA1, 0x20, DMA1) + } + Return(ATA1) + } + } + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXh= ci.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.a= si new file mode 100644 index 0000000000..d2563e0487 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi @@ -0,0 +1,329 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Name (OPAC, Zero) +Name (XRST, Zero) +Name (XUSB, Zero) + +OperationRegion (XPRT, PCI_Config, 0x74, 0x6C) +Field (XPRT, DWordAcc, NoLock, Preserve) +{ + , 8, + PMEE, 1, // PWR_CNTL_STS.PME_En + , 6, + PMES, 1, // PWR_CNTL_STS.PME_Sts + Offset (0x5C), + PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register. + PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register. + PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register. + PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register +} + +Method (_PSW,1) +{ + If (Arg0) + { + Store (Ones,PMEE) + } + Else + { + Store (0,PMEE) + } +} + + +// +// Indicate access to OperationRegions is enabled/disabled +// +Method (_REG, 2) { + // + // If OperationRegion ID =3D PCI_Config + // + If (LEqual (Arg0, 2)) { + // + // If access is enabled + // + If (LEqual(Arg1, 1)) { + // + // Set local flag + // + Store (One, OPAC) + + } Else { + // + // Clear local flag + // + Store (One, OPAC) + } + } +} + +// +// Initialization for this controller +// +Method (_INI, 0) { + // + // If access to OperationRegion is enabled + // + If (LEqual (OPAC, One)) { + Store (1, PMES) // clear PME status + Store (0, PMEE) // clear PME enable + } +} + +// +// _OSC for xHCI +// This method enables XHCI controller if available. +// +// Arguments: +// Arg0 (Integer): Revision ID - should be set to 1 +// +// Arg1 (Integer): Count of DWords in Arg3 +// +// Arg2 (Buffer) : Capabilities Buffer +// DWORD #0 (Status/Error): +// Bit 0 - Query Support Flag +// Bit 1 - Always clear(0) +// Bit 2 - Always clear(0) +// Bit 3 - Always clear(0) +// +// All others - reserved +// +// DWORD #1 (Supported): +// Bit 0 - 1: Switch to xHCI +// +// All others - reserved +// +// DWORD #2 (Controlled): +// Bit 0 - 1: Clear Smart Auto state (disable xHCI) +// +// All others - reserved +// +// Returns: +// Capabilities Buffer: +// DWORD #0 (Status): +// Bit 0 - Reserved (not used) +// +// Bit 1 - _OSC failure. Platform Firmware was unable to = process the request or query. +// Capabilities bits may have been masked. +// +// Bit 2 - Unrecognized UUID. This bit is set to indicate= that the platform firmware +// does not recognize the UUID passed in _OSC Arg= 0. +// Capabilities bits are preserved. +// +// Bit 3 - Unrecognized Revision. This bit is set to indi= cate that the platform firmware +// does not recognize the Revision ID passed in v= ia Arg1. +// Capabilities bits beyond those comprehended by= the firmware will be masked. +// +// Bit 4 - Capabilities Masked. This bit is set to indica= te +// that capabilities bits set by driver software +// have been cleared by platform firmware. +// +// Bit 5 - 0: EHCI controller exposed to OS +// 1: xHCI controller exposed to OS +// +// All others - reserved (return 0) +// +// DWORD #1 (Supported): +// Bit 0 - 0: EHCI supported +// 1: xHCI supported +// +// All others - reserved +// +// DWORD #2 (Controlled): +// +// All bits - reserved +// + +Method (POSC, 3) { + + Store (0x81, IO80) + + // + // Create DWord fields from the Capabilities Buffer + // + CreateDWordField (Arg2, 0, CDW1) // CDW1 =3D DWORD that starts at off= set 0 of Arg2 + CreateDWordField (Arg2, 4, CDW2) // CDW2 =3D DWORD that starts at off= set 4 of Arg2 + CreateDWordField (Arg2, 8, CDW3) // CDW3 =3D DWORD that starts at off= set 8 of Arg2 + + // + // Are we running a version of Windows that runs the Intel xHCI driver? + // i.e. Windows Server 2008 through Windows Server 2008 R2 & Windows 7 + // + If (LAnd (LGreaterEqual (\_SB.OSYS, 9), LLessEqual (\_SB.OSYS, 12))) { + // + // Running Windows + // Check revision is >=3D 2 + // + If (LLess (Arg0, 2)) { + // + // Set unknown revision bit + // + Or (CDW1, 8, CDW1) + Store (0x82, IO80) + } + } Else { + // + // If the Intel xHCI driver not calling, + // then it must be SVOS + If (LNotEqual (Arg0, 1)) { + // + // Set unknown revision bit + // + Or (CDW1, 8, CDW1) + Store (0x82, IO80) + } + } + + // + // Set failure if xHCI is disabled by BIOS + // + If (LEqual (XHMD, 0)) { + Or (CDW1, 2, CDW1) + Store (0x83, IO80) + } + + // + // If no error bits set + // + If (LEqual (And (CDW1, 0xE), 0)) { + // + // If not just querying support + // + If (LNot (And (CDW1, 1))) { + // + // If uninstaller calling + // to switch back to EHCI + // + If (And (CDW3, 1)) { + // + // Switch to EHCI + // + ESEL() + Store (0x85, IO80) + + // + // And clear ACPINVS variable + // that is a copy of USB3.0 setup option + // so that we will not re-enable xHCI until + // the next reboot + // + Store (0, XHMD) + } + + // + // Uninstaller not calling, + // OS wants to enable xHCI? + // + If (And (CDW2, 1)) { + // + // Switch to xHCI + // + XSEL(0) + Store (0x84, IO80) + } Else { + // + // Switch to EHCI + // + ESEL() + Store (0x85, IO80) + } + } + } + + Return(Arg2) +} + +// +// Put all ports in XHCI mode +// +Method (XSEL, 1, Serialized) { + // + // If xHCI in auto or smart auto mode + // or Arg0 =3D=3D 1 + // + If ( LOr (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3)), Arg0) ) { + // + // If xHCI in smart auto mode + // + If (LEqual (XHMD, 3)) { + // + // Set B0:D31:F0 ACh[16] to indicate OS has routed ports to xHCI con= troller + // + Store (1, \_SB.PC00.LPC0.XSMB) + } + + // + // Set flags so on Sx resume, we'll know OS has previously + // routed ports to xHCI + // + Store (1, XUSB) + Store (1, XRST) // Backup XUSB, cause it might lost in iRST G3 or Deep= Sx + + // + // Enable selected SS ports, route corresponding HS ports to xHCI + // + Store (0, Local0) + And (PR3, 0xFFFFFFC0, Local0) + Or (Local0, PR3M, PR3) + Store (0, Local0) + And (PR2, 0xFFFF8000, Local0) + Or (Local0, PR2M, PR2) + } +} + +// +// Put all ports in EHCI mode +// +Method (ESEL, 0, Serialized) { + // + // xHCI in auto or smart auto mode + // + If (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3))) { + // + // Disable all SS ports, route all HS ports to EHCI + // + And (PR3, 0xFFFFFFC0, PR3) + And (PR2, 0xFFFF8000, PR2) + + // + // Mark as not routed. + // + Store (0, XUSB) + Store (0, XRST) + } +} + +Method (XWAK, 0, Serialized) { + // + // If ports were routed to xHCI before sleep + // + If (LOr (LEqual (XUSB, 1), LEqual (XRST, 1))) { + // + // Restore back to xHCI, ignore XHMD + // + XSEL(1) + + // + // And tell OS to re-enumerate xHCI + // + Notify (\_SB.PC00.XHCI, 0x00) + } +} + +// +// Report what D state the controller is in +// when the system changes to S3 and S4 +// +Method(_S3D, 0, NotSerialized) { + Return(2) +} + +Method(_S4D, 0, NotSerialized) { + Return(2) +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCr= s.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi new file mode 100644 index 0000000000..6fb2cb589d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi @@ -0,0 +1,312 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// Return the proximity domain/node # that this bus is on +// With this info OSPM will know what memory and I/O resources +// are under the same IOH +// +Name(_PXM, 0) + +#define RESOURCE_CHUNK1_OFF 0 +#define RESOURCE_CHUNK2_OFF 16 //(RESOURCE_CHUNK1_OFF + 16) +#define RESOURCE_CHUNK3_OFF 24 //(RESOURCE_CHUNK2_OFF + 8) +#define RESOURCE_CHUNK4_OFF 40 //(RESOURCE_CHUNK3_OFF + 16) +#define RESOURCE_CHUNK5_OFF 56 //(RESOURCE_CHUNK4_OFF + 16) +#define RESOURCE_CHUNK6_OFF 82 //(RESOURCE_CHUNK5_OFF + 26) +#define RESOURCE_CHUNK7_OFF 108 //(RESOURCE_CHUNK6_OFF + 26) + +#define PciResourceStart Local0 +#define PciResourceLen Local1 + +Name(PBRS, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces= bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity + 0x0000, // Min + 0x0000, // Max + 0x0000, // Translation + 0x0000,,, // Range Length =3D Max-Min+1 + PB00 + ) + + //RESOURCE_CHUNK2_OFF + IO( //Consumed resource (CF8-CFF) + Decode16,=20 + 0x0cf8,=20 + 0xcf8,=20 + 1, + 8 + ) + + //RESOURCE_CHUNK3_OFF + WORDIO( //Consumed-and-produced resource (all I/O belo= w CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0000, // Min + 0x0cf7, // Max + 0x0000, // Translation + 0x0cf8 // Range Length + ) + + //RESOURCE_CHUNK4_OFF + WORDIO( //Consumed-and-produced resource (all I/O abov= e CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x00, // Granularity + 0x0000, // Min + 0x0000, // Max + 0x00, // Translation + 0x0000,,, // Range Length + PI01 + ) + + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000a0000, // Min + 0x000bffff, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + //RESOURCE_CHUNK6_OFF + DWORDMEMORY( // descriptor for Shadow RAM + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Min (calculated dynamically) + 0x00000000, // Max (calculated dynamically) + 0x00000000, // Translation + 0x00000000,,, // Range Length (calculated dynamically) + SDRM + ) + + //RESOURCE_TPM + DWORDMemory( // Consumed-and-produced resource(all of memor= y space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity + 0xFED40000, // Min (calculated dynamically) + 0xFEDFFFFF, // Max =3D 4GB - 1MB (fwh + fwh alias...) + 0x00000000, // Translation + 0x000C0000 // Range Length (calculated dynamically) + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memor= y space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00, // Granularity + 0x00000000, // Min (calculated dynamically) + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias...) + 0x00, // Translation + 0x00000000,,, // Range Length (calculated dynamically) + PM01 + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memor= y space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00, // Granularity + 0x00000000000, // Min (calculated dynamically) + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias...) + 0x00, // Translation + 0x00000000000,,, // Range Length (calculated dynamically) + PM02 + ) +}) // end of PBRS Buffer + + +Method(_CRS, 0x0, NotSerialized) +{ + //calculate Shadow RAM + EROM() + + // Fix up Bus Number Resources + CreateWordField(PBRS, ^PB00._MIN, PBMN) + Store(BBI0, PBMN) + CreateWordField(PBRS, ^PB00._MAX, PBMX) // (MAX bus decoded - 1, a= ssuming Uncore Bus is MAX decoded BUS Number) + Store(BBL0, PBMX) + CreateWordField(PBRS, ^PB00._LEN, PBLN) + Subtract(PBMX, PBMN, PBLN) + Add(1, PBLN, PBLN) + + // Fix up 16-bit IO resources + CreateWordField(PBRS, ^PI01._MIN, PIMN) + Store(IOBA, PIMN) + CreateWordField(PBRS, ^PI01._MAX, PIMX) + Store(IOLA, PIMX) + CreateWordField(PBRS, ^PI01._LEN, PILN) + Subtract(PIMX, PIMN, PILN) + Add(1, PILN, PILN) + + // Fix up 32-bit Memory resources + CreateDWordField(PBRS, ^PM01._MIN, PMMN) + Store(MMB0, PMMN) + CreateDWordField(PBRS, ^PM01._MAX, PMMX) + Store(MML0, PMMX) + CreateDWordField(PBRS, ^PM01._LEN, PMLN) + Subtract(PMMX, PMMN, PMLN) + Add(1, PMLN, PMLN) + + // Fix up 64-bit Memory resources +// If(LAnd(MMH0, LGreater(OSFL, 8))) { + CreateQWordField(PBRS, ^PM02._MIN, P2MN) + Store(HMB0, P2MN) + CreateQWordField(PBRS, ^PM02._MAX, P2MX) + Store(HML0, P2MX) + CreateQWordField(PBRS, ^PM02._LEN, P2LN) + Subtract(P2MX, P2MN, P2LN) + Add(1, P2LN, P2LN) +// } + + Return(PBRS) +} + +Method(_STA,0) { + If (NPB0) { + Return(0x0F) + } + Return(0x00) +} + +OperationRegion(TMEM, PCI_Config, 0x52, 0x3) +Field(TMEM, ByteAcc, NoLock, Preserve) { + DIM0, 4, + DIM1, 4, + , 8, + DIM2, 4 +} + +Name(MTBL, Package(0x10) { + 0x0, + 0x20, + 0x20, + 0x30, + 0x40, + 0x40, + 0x60, + 0x80, + 0x80, + 0x80, + 0x80, + 0xc0, + 0x100, + 0x100, + 0x100, + 0x200 +}) + + +OperationRegion(PAMX, PCI_Config, 0x90, 0x7) +Field(PAMX, ByteAcc, NoLock, Preserve) { + , 4, + BSEG, 4, + PAMS, 48 +} + +Name(ERNG, Package(0xd) { + 0xc0000, + 0xc4000, + 0xc8000, + 0xcc000, + 0xd0000, + 0xd4000, + 0xd8000, + 0xdc000, + 0xe0000, + 0xe4000, + 0xe8000, + 0xec000, + 0xf0000 +}) + +Name(PAMB, Buffer(0x7) { +}) + +Method(EROM, 0x0, NotSerialized) { + CreateDWordField(PBRS, 0x5c, RMIN) + CreateDWordField(PBRS, 0x60, RMAX) + CreateDWordField(PBRS, 0x68, RLEN) + CreateByteField(PAMB, 0x6, BREG) + Store(PAMS, PAMB) + Store(BSEG, BREG) + Store(0x0, RMIN) + Store(0x0, RMAX) + Store(0x0, RLEN) + Store(0x0, Local0) + While(LLess(Local0, 0xd)) { + ShiftRight(Local0, 0x1, Local1) + Store(DerefOf(Index(PAMB, Local1, )), Local2) + If(And(Local0, 0x1, )) { + ShiftRight(Local2, 0x4, Local2) + } + And(Local2, 0x3, Local2) + If(RMIN) { + If(Local2) { + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX) + If(LEqual(RMAX, 0xf3fff)) { + Store(0xfffff, RMAX) + } + Subtract(RMAX, RMIN, RLEN) + Increment(RLEN) + } Else { + Store(0xc, Local0) + } + } Else { + If(Local2) { + Store(DerefOf(Index(ERNG, Local0, )), RMIN) + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX) + If(LEqual(RMAX, 0xf3fff)) { + Store(0xfffff, RMAX) + } + Subtract(RMAX, RMIN, RLEN) + Increment(RLEN) + } Else { + } + } + Increment(Local0) + } +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIr= q.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi new file mode 100644 index 0000000000..fe7c2b8753 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi @@ -0,0 +1,455 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +OperationRegion (PRR0, PCI_Config, 0x00, 0x100) +Field (PRR0, AnyAcc, NoLock, Preserve) { + Offset(0x60), + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8, + Offset(0x68), + PIRE, 8, + PIRF, 8, + PIRG, 8, + PIRH, 8 +} + +Device (LNKA) { // PCI IRQ link A + Name (_HID,EISAID("PNP0C0F")) + //Name(_UID, 1) + Method (_STA,0,NotSerialized) { + If(And(PIRA, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRA, 0x80, PIRA) + } + + Method (_CRS,0,Serialized) { + Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And(PIRA, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRA,0x0F),IRQW) // Save in buffer + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)){ + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRA) + } // End of _SRS Method +} + +Device(LNKB) { // PCI IRQ link B + Name (_HID,EISAID("PNP0C0F")) + //Name(_UID, 2) + Method (_STA,0,NotSerialized) { + If (And (PIRB, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRB, 0x80,PIRB) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRB, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRB,0x0F),IRQW) // Save in buffer + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual(IRQW,Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRB) + } // End of _SRS Method +} + +Device(LNKC) { // PCI IRQ link C + Name(_HID, EISAID("PNP0C0F")) + //Name(_UID, 3) + + Method (_STA,0,NotSerialized) { + If (And (PIRC, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or (PIRC, 0x80, PIRC) + } + + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRC, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRC,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRC) + } // End of _SRS Method +} + +Device (LNKD) { // PCI IRQ link D + Name (_HID,EISAID ("PNP0C0F")) + + //Name(_UID, 4) + + Method (_STA, 0, NotSerialized) { + If (And (PIRD, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or(PIRD, 0x80,PIRD) + } + + Method (_CRS,0,Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRD, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRD,0x0F), IRQW) + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW, Local0)// Set IRQ + If (LNotEqual (IRQW, Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store(Local0, PIRD) + } // End of _SRS Method +} + +Device(LNKE) { // PCI IRQ link E + Name(_HID,EISAID("PNP0C0F")) + + //Name(_UID, 5) + + Method (_STA,0,NotSerialized) { + If (And (PIRE, 0x80)) { + Return(0x9) + } Else { + Return(0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRE, 0x80, PIRE) + } + + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRE, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One, Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRE,0x0F), IRQW) + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW, Local0) // Set IRQ + If (LNotEqual (IRQW, Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRE) + } // End of _SRS Method +} + +Device(LNKF) { // PCI IRQ link F + Name (_HID,EISAID("PNP0C0F")) + + //Name(_UID, 6) + + Method (_STA,0,Serialized) { + If (And (PIRF, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRB, 0x80, PIRF) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRF, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One, Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRF, 0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRF) + } // End of _SRS Method +} + +Device(LNKG) { // PCI IRQ link G + Name(_HID,EISAID("PNP0C0F")) + //Name(_UID, 7) + Method(_STA,0,NotSerialized) { + If (And (PIRG, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or(PIRG, 0x80,PIRG) + } + + Method (_CRS,0,Serialized){ + Name(BUF0,ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And(PIRG, 0x80)) { + Store(Zero, Local0) + } Else { + Store(One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And(PIRG,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRG) + } // End of _SRS Method +} + +Device(LNKH) { // PCI IRQ link H + Name (_HID,EISAID("PNP0C0F")) + + //Name(_UID, 8) + + Method (_STA,0,Serialized) { + If (And(PIRH, 0x80)) { + Return(0x9) + } Else { + Return(0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or(PIRH, 0x80,PIRH) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRH, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And(PIRH,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW,Local0)// Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRH) + } +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieH= p.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi new file mode 100644 index 0000000000..ced2b3ecd1 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi @@ -0,0 +1,644 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + //=20 + // BIOS parameter + // The address will be fixed dynamically during boot.=20 + // Will be updated by ACPI platform driver as "FIX8" + // + OperationRegion (MCTL, SystemMemory, 0x38584946, 0x04) + Field (MCTL, ByteAcc, NoLock, Preserve) { + , 3, + HGPE, 1, + , 7, + , 8, + , 8 + } + +// +// No longer needed, See PPA4 +// +// OperationRegion (PSTS, PCI_Config, 0xB0, 0x04)=20 +// Field (PSTS, ByteAcc, NoLock, Preserve) { +// , 16, +// PMES, 1, // PME Status bit 16 =20 +// PMEP, 1, //PME Pending bit 17 =20 +// , 14 +// } + + + Method (_INI, 0, NotSerialized) { + Store (0x01, HGPE) //enable GPE message generation for ACPI h= otplug support + } + + Name(_HPP, Package(){0x08, 0x40, 1, 0}) + + // + // begin hotplug code + // + Name(SHPC, 0x40) // Slot Hot-plug Capable + + Name(SPDS, 0x040) // Slot Presence Detect State + + Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on + Name(CCOM, 0x010) // Command Complete + Name(SPDC, 0x08) // Slot Presence Detect Changes + Name(MRLC, 0x04) // Slot MRL Changed + Name(SPFD, 0x02) // Slot Power Fault Detected + Name(SABP, 0x01) // Slot Attention Button Pressed + + Name(SPOF, 0x10) // Slot Power Off + Name(SPON, 0x0F) // Slot Power On Mask + + Name(ALMK, 0x1C) // Slot Atten. LED Mask + Name(ALON, 0x01) // Slot Atten. LED On + Name(ALBL, 0x02) // Slot Atten LED Blink + Name(ALOF, 0x03) // Slot Atten LED Off + + Name(PLMK, 0x13) // Slot Pwr. LED Mask + Name(PLON, 0x04) // Slot Pwr. LED On + Name(PLBL, 0x08) // Slot Pwr. LED Blink + Name(PLOF, 0x0C) // Slot Pwr. LED Off + + //;************************************* + //; Bit 3 =3D Presence Detect Event + //; Bit 2 =3D MRL Sensor Event + //; Bit 1 =3D PWR Fault Event + //; Bit 0 =3D Attention Button Event + //;************************************* + Name(HPEV, 0xF) // Possible interrupt events (all) + + //;*********************************************************************= ***; + //; + //; PCIe Link Control Register A0-A1h + //; + //; Bit - 4 - Link disable. + //; + //;*********************************************************************= ***; +// +// No longer needed, see PPA4 +// +// OperationRegion(PPA0, PCI_Config, 0xA0, 0x02) +// Field(PPA0,ByteAcc,NoLock,Preserve) { +// ,4, +// LDIS,1, // Link Disable bit4. +// ,11, +// } + + //;*********************************************************************= ***; + //; + //; PCIe Slot Capabilities Register A4-A7h + //; Bit - 31-5 - Not used + //; Bit - 4 - Power Indicator Present. + //; Bit - 3 - Attention Indicator Present. + //; Bit - 2 - MRL Sensor Present. + //; Bit - 1 - Power Controller Present. + //; Bit - 0 - Attention Button Present. + //; + //; PCIe Slot control Register A8-A9h + //; + //; Bit - 10 - PWR Control Disable + //; Bit - 9:8 - Attn Indicator + //; Bit - 7:6 - PWR Indicator + //; Bit - 5 - Hot-Plug Interrupt Event Enable + //; Bit - 4 - Command Complete Interrupt enable + //; Bit - 3 - Presence Detect Changed Interrupt enable + //; Bit - 2 - MRL Sensor Changed Interrupt enable + //; Bit - 1 - PwrFault Detect Interrupt enable + //; Bit - 0 - Attention Button Pressed Interrupt Enable + //; + //; PCIe Slot Status Registers AA-ADh + //; + //; Bit - 6 - Presence Detect State. + //; Bit - 5 - MRL Sensor State. + //; Bit - 4 - Command Completed. + //; + //; RWC Status Bits + //; + //; Bit - 3 - Presence Detect Changed. + //; Bit - 2 - MRL Sensor Changed. + //; Bit - 1 - Power Fault Detected. + //; Bit - 0 - Attention Button Pressed. + //;*********************************************************************= ***; + OperationRegion(PPA4, PCI_Config, 0x00, 0x100) + Field(PPA4,ByteAcc,NoLock,Preserve) { + Offset (0xA0), // from PPA0 OpRegion + ,4, + LDIS,1, // Link Disable bit4. + ,11, + Offset(0xA4), // A4-A7h PCI Slot Capabilities Register + ATBP,1, // Attention Button Present + ,1, // Skip Power Controller Present + MRSP,1, // MRL Sensor Present + ATIP,1, // Attention Indicator Present + PWIP,1, // Power Indicator Present + ,14, + PSNM,13, // Physical Slot Number + Offset(0xA8), // PCIE Slot Control Register + ABIE,1, // Attention Button Pressed Interrupt Enable + PFIE,1, // Power Fault Detected Interrupt Enable + MSIE,1, // MRL Sensor Changed Interrupt Enable + PDIE,1, // Presence Detect Changed Interrupt Enable. + CCIE,1, // Command Complete Interrupt Enable. + HPIE,1, // Hot-plug Interrupt Enable. + SCTL,5, // Attn/Power indicator and Power controller. + ,5, // reserved + Offset(0xAA), // PCIE Slot Status Register + SSTS,7, // The status bits in Slot Status Reg + ,1, + Offset (0xB0), // from PSTS OpRegion + , 16, + PMES, 1, // PME Status bit 16 =20 + PMEP, 1, // PME Pending bit 17 =20 + , 14 + } + + // + // These Methods replace the bit field definitions in PPA8 + // that were bit fields within SCTL + // + Method (ATID, 0) { + Return (And (SCTL, 0x03)) + } + + Method (PWID, 0) { + Return (ShiftRight (And (SCTL, 0x0C), 2)) + } + + Method (PWCC, 0) { + Return (ShiftRight (And (SCTL, 0x10), 4)) + } + + // + // These methods replace the bit fields definitions in PPA8 + // that were bit fields within SSTS + // + Method (ABPS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x01, SSTS) + } + Return (And (SSTS, 0x01)) + } + + Method (PFDS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x02, SSTS) + } + Return (ShiftRight (And (SSTS, 0x02), 1)) + } + =20 + Method (MSCS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x04, SSTS) + } + Return (ShiftRight (And (SSTS, 0x04), 2)) + } + =20 + Method (PDCS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x08, SSTS) + } + Return (ShiftRight (And (SSTS, 0x08), 3)) + } + + Method (CMCS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x10, SSTS) + } + Return (ShiftRight (And (SSTS, 0x10), 4)) + } + + Method (MSSC, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x20, SSTS) + } + Return (ShiftRight (And (SSTS, 0x20), 5)) + } + + Method (PRDS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x40, SSTS) + } + Return (ShiftRight (And (SSTS, 0x40), 6)) + } + + +// OperationRegion(PPA8, PCI_Config, 0x00, 0x0ff) +// Field(PPA8,ByteAcc,NoLock,Preserve) { +// Offset(0xA8), // PCIE Slot Control Register +// ,6, +// ATID,2, // Attention Indicator Control. +// PWID,2, // Power Indicator Control. +// PWCC,1, // Power Controller Control. +// ,5, +// Offset(0xAA), // RWC status +// ABPS,1, // Attention Button Pressed Status (RWC) +// PFDS,1, // Power Fault Detect Status (RWC) +// MSCS,1, // MRL Sensor Changed Status +// PDCS,1, // Presence Detect Changed Status +// CMCS,1, // Command Complete Status +// MSSC,1, // MRL Sensor State +// PRDS,1, // Presence Detect State +// ,1, +// } + + //;*********************************************************************= ***; + //; This OSHP (Operating System Hot Plug) method is provided for each HPC + //; which is controlled by ACPI. This method disables ACPI access to the + //; HPC and restores the normal System Interrupt and Wakeup Signal + //; connection. + //;*********************************************************************= ***; + Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express = HP code. + Store(0, SSTS) // Clear any status + Store(0x0, HGPE) // Disable GPE generation + } + + //;*********************************************************************= ***; + //; Hot Plug Controller Command Method + //; + //; Input: Arg0 - Command to issue + //; + //;*********************************************************************= ***; + Method(HPCC,1) { + Store(SCTL, Local0) // get current command state + Store(0, Local1) // reset the timeout value + If(LNotEqual(Arg0, Local0)) { // see if state is different + Store(Arg0, SCTL) // Update the Slot Control + While(LAnd (LNot(CMCS(0)), LNotEqual(100, Local1))) { // spin while = CMD complete bit is not set, + // check for t= imeout to avoid dead loop + Store(0xFB, IO80) + Sleep(2) // allow processor time slice + Add(Local1, 2, Local1) + } + CMCS(1) // Clear the command complete status + } + } + + //;*********************************************************************= ***; + //; Attention Indicator Command + //; + //; Input: Arg0 - Command to issue + //; 1 =3D ON + //; 2 =3D Blink + //; 3 =3D OFF + //;*********************************************************************= ***; + Method(ATCM,1) { + Store(SCTL, Local0) // Get Slot Control + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits + If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?" + Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON" + } + If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?" + Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK" + } + If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?" + Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF" + } + HPCC(Local0) + } + + //;*********************************************************************= ***; + //; Power Indicator Command + //; + //; Input: Arg0 - Command to issue + //; 1 =3D ON + //; 2 =3D Blink + //; 3 =3D OFF + //;*********************************************************************= ***; + Method(PWCM,1){ + Store(SCTL, Local0) // Get Slot Control + And(Local0, PLMK, Local0) // Mask the Power Indicator Bits + If(LEqual(Arg0, 0x1)){ // Power indicator "ON?" + Or(Local0, PLON, Local0) // Set the Power Indicator to "ON" + } + If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?" + Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK" + } + If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?" + Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF" + } + HPCC(Local0) + } + + //;*********************************************************************= ***; + //; Power Slot Command + //; + //; Input: Arg0 - Command to issue + //; 1 =3D Slot Power ON + //; 2 =3D Slot Power Off + //;*********************************************************************= ***; + Method(PWSL,1){ + Store(SCTL, Local0) // Get Slot Control + If(Arg0){ // Power Slot "ON" Arg0 =3D 1 + And(Local0, SPON, Local0) // Turns the Power "ON" + } Else { // Power Slot "OFF" + Or(Local0, SPOF, Local0) // Turns the Power "OFF" + } + HPCC(Local0) + } + + //;*********************************************************************= ***; + //; _OST Methods to indicate that the device Eject/insert request is + //; pending, OS could not complete it + //; + //; Input: Arg0 - Value used in Notify to OS + //; 0x00 - card insert + //; 0x03 - card eject =20 + //; Arg1 - status of Notify + //; 0 - success + //; 0x80 - Ejection not supported by OSPM + //; 0x81 - Device in use + //; 0x82 - Device Busy + //; 0x84 - Ejection in progress-pending + //;*********************************************************************= ***; + Method(_OST,3,Serialized) { + Switch(And(Arg0,0xFF)) { // Mask to retain low byte + Case(0x03) { // Ejection Request + Switch(ToInteger(Arg1)) { + Case(Package() {0x80, 0x81, 0x82, 0x83}) { + // + // Ejection Failure for some reason + // + If (Lnot(PWCC())) { // if slot is powered + PWCM(0x1) // Set PowerIndicator to ON + Store(0x1,ABIE) // Set AttnBtn Interrupt ON + } + } + } + } + } + } // End _OST + + //;*********************************************************************= ***; + //; Eject Control Methods to indicate that the device is hot-ejectable a= nd + //; should "eject" the device. + //; + //; + //;*********************************************************************= ***; + Method(EJ0L){ + Store(0xFF, IO80) + Store(SCTL, Local0) // Get IIO Port Control state + if( LNot( LEqual( ATID(), 1))) { // Check if Attention LED is not sol= id "ON" + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits=20 + Or(Local0, ALBL, Local0) // Set the Attention Indicator to bli= nk + } + HPCC(Local0) // issue command + + Store(SCTL, Local0) // Get IIO Port Control state + Or(Local0, SPOF, Local0) // Set the Power Controller Control to= Power Off + HPCC(Local0) + + Store(SCTL, Local0) // Get IIO Port Control state + Or(Local0, PLOF, Local0) // Set the Power Indicator to Off. + HPCC(Local0) + + Store(SCTL, Local0) // Get IIO Port Control state + Or(Local0, ALOF, Local0) // Set the Attntion LED to Off. + HPCC(Local0) + + } // End of EJ0L + + //;*********************************************************************= ***; + //; PM_PME Wake Handler for All Slots=20 + //; + //; Input: Arg0 - Slot Numnber + //; + //;*********************************************************************= ***; + Method(PMEH,1){ // Handler for PCI-E PM_PME Wake Event= /Interupt (GPI xxh) + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events + If(ABPS(0)) { + Store (Arg0, IO80) // Send slot number to Port 80 + ABPS(1) // Clear the interrupt status + Sleep(200) // delay 200ms + } + } + Return (0xff) // Indicate that this controller did n= ot interrupt + } // End of Method PMEH + + //;*********************************************************************= ***; + //; Hot-Plug Handler for All Slots. + //; + //; Input: Arg0 - Slot Number + //; + //;*********************************************************************= ***; + Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/In= terupt (GPI xxh) + Store(0xFE, IO80) + Sleep(100) + Store(0,CCIE) // Disable command interrupt + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events + Store(0xFD, IO80) + Sleep(10) + Store (Arg0, IO80) // Send slot number to Port 80 + Sleep(10) + Store(PPXH(), Local0) // Call Hot plug Interrupt Handler + Return(Local0) // Return PPXH information + } + Else{ + Return (0xff) // Indicate that this controller did n= ot interrupt + } + Store(0xFC, IO80) + Sleep(10) + } // End of Method HPEH + + //;*********************************************************************= ***; + //; Interrut Event Handler + //; + //; + //;*********************************************************************= ***; + Method(PPXH){ // Hot plug Interrupt Handler + // + // Check for the Atention Button Press, Slot Empty/Presence, Power Con= troller Control. + // + Sleep(200) // HW Workaround for AttentionButton= Status to stabilise + If(ABPS(0)) { // Check if Attention Button Pressed=20 + If(LNot(PRDS(0))) { // See if nothing installed (no card= in slot) + Store(0x1, LDIS) // Disable the Link associated with = PCI-E port + PWSL(0x0) // make sure Power is Off + PWCM(0x3) // Set Power Indicator to "OFF" + // + // Check for MRL here and set attn indicator accordingly + // + If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed + ATCM(0x2) // Set Attention Indicator to "BLINK" + } else { // Standby power is off - MRL open + ATCM(0x3) // set attention indicator "OFF" + } + Store(0x0, ABIE) // set Attention Button Interrupt to= disable + ABPS(1) // Clear the interrupt status + Sleep(200) // delay 200ms + Return(0xff) // Attn Button pressed without card = in slot. Do nothing + } + // + // Card is present in slot so.... + // + Store(0x0, ABIE) // set Attention Button Interrupt to= disable + // Attn Btn Interrupt has to be enab= led only after an insert oprn + ABPS(1) // Clear the interrupt status + Sleep(200) // delay 200ms + // + // Check for MRL here - only if SPWR is OFF blink AttnInd and retun = 0xff + // + //If(LNot(LEqual(MSSC()),MRLS))) { // Standby power is off + // PWSL(0x0) // make sure Power is Off + // PWCM(0x3) // Set Power Indicator to "OFF" + // ATCM(0x2) // Set Attention Indicator to "BLI= NK" + // Return(0xff) // Attn Button pressed with card i= n slot, but MRL open. Do nothing + //} + //Card Present, if StandbyPwr is ON proceed as below with Eject Sequ= ence + If(PWCC()) { // Slot not Powered + PWCM(0x3) // Set Power Indicator to "OFF" + ATCM(0x2) // Set Attention Indicator to "BLINK" + Return(0xff) // Attn Button pressed with card in = slot, MRL closed, Slot not powered. Do nothing + } Else { // See if Slot is already Powered + PWCM(0x2) // Set power Indicator to BLINK + Sleep(600) // Wait 100ms + Store(600, Local0) // set 5 second accumulator to 0 + ABPS(1) // Clear the interrupt status + Sleep(200) // delay 200ms + While(LNot(ABPS(0))) { // check for someone pressing Att= ention + Sleep(200) // Wait 200ms + Add(Local0, 200, Local0) + If(LEqual(5000, Local0)) { // heck if 5sec has passed without p= ressing attnetion btn + ABPS(1) // Clear the interrupt status + Sleep(200) // delay 200ms=20 + Return (0x3) // continue with Eject request + } + } + PWCM(0x1) // Set power Indicator baCK "ON" + ABPS(1) // Clear the Attention status + Sleep(200) // delay 200ms + Store(0x1, ABIE) // set Attention Button Interrupt to= enable + Return (0xff) // do nothing and abort + } + } // End if for the Attention Button Hot Plug Interrupt. + + If(PFDS(0)) { // Check if Power Fault Detected + PFDS(1) // Clear the Power Fault Status + PWSL(0x0) // set Power Off + PWCM(0x3) // set power indicator to OFF + ATCM(0x1) // set attention indicator "ON" + Store(0x1, LDIS) // Disable the Link associated with = PCI-E port + Return(0x03) // Eject request. + } // End if for the Power Fault Interrupt. + + If(MSCS(0)) { // Check interrupt caused by the MRL= Sensor + MSCS(1) // Clear the MRL Status + If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed + If(PRDS(0)) { // Card is Present + + ATCM(0x3) // Set Attention Indicator to off + PWCM(0x2) // Set Power Indicator to Blink + Sleep(600) // Wait 100ms + Store(600, Local0) // set 5 second accumulator to 0 + ABPS(1) // Clear the interrupt status + While(LNot(ABPS(0))) { // check for someone pressing Att= ention + Sleep(200) // Wait 200ms + Add(Local0, 200, Local0) + If(LEqual(5000, Local0)) { // Check if 5 sec elapsed + Store(0x1, ABIE) // Enable Attention button interrupt + ATCM(0x3) // set attention indicator "OFF" + Store(0x0, LDIS) // Enable the Link associated with P= CI-E port + PWSL(0x1) // Power the Slot + Sleep(500) // Wait for .5 Sec for the Power to = Stabilize. + // Check for the Power Fault Detection + If(LNot(PFDS(0))) { // No Power Fault + PWCM(0x1) // Set Power Indicator to = "ON" + // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slo= t Clock (GPIO16) + // Notify the OS to load the Driver for the card + Store(0x00, Local1) + Store(0x1, ABIE) // Enable Attention button= interrupt + } Else { // Power Fault present + PWSL(0x0) // set Slot Power Off + PWCM(0x3) // set power indicator to = OFF + ATCM(0x1) // set attention indicator= "ON" + Store(0x1, LDIS) // Disable the Link associ= ated with PCI-E port + // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Sl= ot Clock (GPIO16) + Store(0x03, Local1) // Eject request. + } // End if for the Slot Pow= er Fault + ABPS(1) // Clear the Attention sta= tus + Sleep(200) // delay 200ms + Return(Local1) + } + } + // + // someone pressed Attention Button + // + ABPS(1) // Clear the Attention status + Sleep(200) // delay 200ms + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + ATCM(02) // Set Attention Indicator to "BLINK" + Store(0x1, LDIS) // Disable the Link associated with PC= I-E port + Return(0xff) // leave it off + // End of Insert sequence + } + //MRL is closed, Card is not present + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + ATCM(02) // Set Attention Indicator to "BLINK" + Store(0x1, LDIS) // Disable the Link associated with PC= I-E port + Return(0xff) // leave it off + } Else { // MRL is open i.e Stdby power is turn= ed off + If(PRDS(0)) { //card present MRL switched off + ATCM(0x2) // Set Attention Indicator to "BLINK" + If(Lnot(PWCC())) { // If slot is powered + // This event is not supported and someone has opened the MRL = and dumped the power + // on the slot with possible pending transactions. This could= hose the OS. + // Try to Notify the OS to unload the drivers. + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + Store(0x1, LDIS) // Disable the Link associated with PC= I-E port + Return(0x03) // Eject request. + } Else { // Slot not powered, MRL is opened, ca= rd still in slot - Eject not fully complete + Return(0xFF) + } + } + //no card present and Stdby power switched off, turn AI off + ATCM(0x3) // Set Attention Indicator to "OFF" + Return(0xff) // leave it off + } // End of MRL switch open/close state + } // End of MRL Sensor State Change + + If(PDCS(0)) { // Check if Presence Detect Changed St= atus + PDCS(1) // Clear the Presence Detect Changed S= tatus + If(LNot(PRDS(0))) { // Slot is Empty + PWSL(0x0) // Set Slot Power "OFF" + PWCM(0x3) // set power indicator to "OFF" + If(LEqual(MSSC(0),MRLS)) { // If Standby power is on + ATCM(0x2) // Set Attention Indicator to "Blink" + } else { + ATCM(0x3) // Set Attention Indicator to "OFF" + } + Store(0x1, LDIS) // Disable the Link associated with PC= I-E port + Return(0xFF) // Do nothing + } Else { // Slot Card is inserted + // Irrespective of MRL state, do the following + Store(0x0, LDIS) // Enable the Link associated with PCI= -E port + PWSL(0x1) // Set Slot Power ON + Sleep(500) // Wait for .5 Sec for the Power to St= abilize. + If(LNot(PFDS(0))) { // No Power Fault + PWCM(0x1) // Set Power Indicator to "ON" + Store(0x00, Local1) + Store(0x1, ABIE) // Enable Attention button interrupt + ATCM(0x3) // Set Attention Indicator to "OFF" + } Else { // Power Fault present + PWSL(0x0) // set Slot Power Off + PWCM(0x3) // set power indicator to OFF + ATCM(0x1) // set attention indicator "ON" + Store(0x1, LDIS) // Disable the Link associated with PC= I-E port + Store(0x03, Local1) // Eject request. + } // End if for the Slot Power Fault + ABPS(1) // Clear the Attention status + Sleep(200) // delay 200ms + Return(Local1) + } + } // End if for the Presence Detect Changed Hot Plug Interrupt. + Return(0xff) // should not get here, but do device check if it does. + } // End of method PP5H + // + // End of hotplug code + // diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieH= pDev.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpD= ev.asi new file mode 100644 index 0000000000..34feaa8137 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Method(SNUM, 0, Serialized) { + Store(PSNM, Local0) + Return(Local0) + } + + Method(_SUN, 0) { Return(SNUM) } // Slot User Number + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieN= onHpDev.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pcie= NonHpDev.asi new file mode 100644 index 0000000000..c990898e87 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev= .asi @@ -0,0 +1,16 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Method(SNUM, 0, Serialized) { + Store(PSNM, Local0) + Return(Local0) + } + + Method(_SUN, 0) {=20 + Return(SNUM)=20 + } // Slot User Number + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieS= eg.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.a= si new file mode 100644 index 0000000000..51c919f5e5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi @@ -0,0 +1,355 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MaxSocket.h" + + Scope(\) { + + // + // \SG00, SG01,... SG07 are defined to contain Segment # for Segment/soc= ket 0, 1, .... + // + // Create _SEG for each segment/socket + // + + // + // Debug method for use under BITS + // Example: Set SG01 to 5 SSEG(1,5) + // + Method(SSEG, 2) { + If (LEqual(Arg0, 0) ) { Store (Arg1, SG00) }=20 + If (LEqual(Arg0, 1) ) { Store (Arg1, SG01) }=20 + If (LEqual(Arg0, 2) ) { Store (Arg1, SG02) }=20 + If (LEqual(Arg0, 3) ) { Store (Arg1, SG03) }=20 + } + + +// ------------------------------------------------------ +// Socket 0 PC00 - PC05 share the same segment number SG00 +// ------------------------------------------------------ + + Scope(\_SB.PC00) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + + Scope(\_SB.PC01) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + + Scope(\_SB.PC02) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + + Scope(\_SB.PC03) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + + Scope(\_SB.PC04) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + + Scope(\_SB.PC05) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + +// ------------------------------------------------------ +// Socket 1 PC06 - PC11 share the same segment number SG01 +// ------------------------------------------------------ + + Scope(\_SB.PC06) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + + Scope(\_SB.PC07) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + + Scope(\_SB.PC08) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + + Scope(\_SB.PC09) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + + Scope(\_SB.PC10) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + + Scope(\_SB.PC11) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + +// ------------------------------------------------------ +// Socket 2 PC12 - PC17 share the same segment number SG02 +// ------------------------------------------------------ + + Scope(\_SB.PC12) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + Scope(\_SB.PC13) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + Scope(\_SB.PC14) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + Scope(\_SB.PC15) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + Scope(\_SB.PC16) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + Scope(\_SB.PC17) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + +// ------------------------------------------------------ +// Socket 3 PC18 - PC23 share the same segment number SG03 +// ------------------------------------------------------ + + Scope(\_SB.PC18) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + + Scope(\_SB.PC19) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + + Scope(\_SB.PC20) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + + Scope(\_SB.PC21) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + + Scope(\_SB.PC22) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + + Scope(\_SB.PC23) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + +#if MAX_SOCKET > 4 + +// ------------------------------------------------------ +// Socket 4 PC24 - PC29 share the same segment number SG03 +// ------------------------------------------------------ + + Scope(\_SB.PC24) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } + + Scope(\_SB.PC25) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } + + Scope(\_SB.PC26) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } + + Scope(\_SB.PC27) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } + + Scope(\_SB.PC28) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } + + Scope(\_SB.PC29) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } +=09 +// ------------------------------------------------------ +// Socket 5 PC30 - PC35 share the same segment number SG03 +// ------------------------------------------------------ + + Scope(\_SB.PC30) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + + Scope(\_SB.PC31) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + + Scope(\_SB.PC32) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + + Scope(\_SB.PC33) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + + Scope(\_SB.PC34) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + + Scope(\_SB.PC35) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + +// ------------------------------------------------------ +// Socket 6 PC36 - PC41 share the same segment number SG03 +// ------------------------------------------------------ + + Scope(\_SB.PC36) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + } + + Scope(\_SB.PC37) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + } + + Scope(\_SB.PC38) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + } + + Scope(\_SB.PC39) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + } + + Scope(\_SB.PC40) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + } + + Scope(\_SB.PC41) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + }=09 +=09 +// ------------------------------------------------------ +// Socket 7 PC42 - PC47 share the same segment number SG03 +// ------------------------------------------------------ + + Scope(\_SB.PC42) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + } + + Scope(\_SB.PC43) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + } + + Scope(\_SB.PC44) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + } + + Scope(\_SB.PC45) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + } + + Scope(\_SB.PC46) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + } + + Scope(\_SB.PC47) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + }=09 +#endif + +} // End Scope(\) + =20 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platf= orm.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform= .asl new file mode 100644 index 0000000000..40cc31b86a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl @@ -0,0 +1,79 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +// Interrupt specific registers +include("Itss.asl") +// +// Original file line: 163 +// + +Method(ADBG,1,Serialized) +{ + Return(0) +} + +// +// Original file line: 1460 +// +Scope (\) +{ + // + // Global Name, returns current Interrupt controller mode; + // updated from _PIC control method + // + + // + // Procedure: GPRW + // + // Description: Generic Wake up Control Method ("Big brother")=20 + // to detect the Max Sleep State available in ASL Name scope + // and Return the Package compatible with _PRW format. + // Input: Arg0 =3D bit offset within GPE register space device event wi= ll be triggered to. + // Arg1 =3D Max Sleep state, device can resume the System from. + // If Arg1 =3D 0, Update Arg1 with Max _Sx state enabled = in the System. + // Output: _PRW package + // + Name(PRWP, Package(){Zero, Zero}) // _PRW Package + =20 + Method(GPRW, 2) + { + Store(Arg0, Index(PRWP, 0)) // copy GPE# + // + // SS1-SS4 - enabled in BIOS Setup Sleep states + // + Store(ShiftLeft(SS1,1),Local0) // S1 ? + Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ? + Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ? + Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ? + // + // Local0 has a bit mask of enabled Sx(1 based) + // bit mask of enabled in BIOS Setup Sleep states(1 based) + // + If(And(ShiftLeft(1, Arg1), Local0)) + {=20 + // + // Requested wake up value (Arg1) is present in Sx list of available= Sleep states + // + Store(Arg1, Index(PRWP, 1)) // copy Sx# + }=20 + Else + { + // + // Not available -> match Wake up value to the higher Sx state + // + ShiftRight(Local0, 1, Local0)=20 + // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x + // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 =3D=3D Max Sx + // } Else { // ??? Win2k / XP + FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 =3D=3D Min Sx + // } + } + =20 + Return(PRWP) + } +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platf= ormGpe.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platf= ormGpe.asi new file mode 100644 index 0000000000..1f3087a7b3 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.= asi @@ -0,0 +1,78 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// General Purpose Event +#include "MaxSocket.h" + +Scope (\_GPE) { + + // + // ME HECI2 SCI handler + // Note: This SCI from HECI2 is routed to ICH9 over the DMI and it + // sets the DMISCI status bit in TCO block. From there it is routed + // to bit6 GPE0 status register. + // + OperationRegion (TCOS, SystemIO, 0x464, 2) // ICH_ACPI_BASE_ADDRESS + TC= O_BASE + R_TCO1_STS + Field (TCOS, ByteAcc, NoLock, WriteAsZeros) { + Offset (0x1), + , 1, + DSCI, 1, + } + + Method(NTFI, 2){ + If(And(Arg0, 0x01)){ + Notify(\_SB.PC06, Arg1) + Notify(\_SB.PC07, Arg1) + Notify(\_SB.PC08, Arg1) + Notify(\_SB.PC09, Arg1) + Notify(\_SB.PC10, Arg1) + Notify(\_SB.PC11, Arg1) =20 + } + If(And(Arg0, 0x02)){ + Notify(\_SB.PC12, Arg1) + Notify(\_SB.PC13, Arg1) + Notify(\_SB.PC14, Arg1) + Notify(\_SB.PC15, Arg1) + Notify(\_SB.PC16, Arg1) + Notify(\_SB.PC17, Arg1) =20 + } + If(And(Arg0, 0x04)){ + Notify(\_SB.PC18, Arg1) + Notify(\_SB.PC19, Arg1) + Notify(\_SB.PC20, Arg1) + Notify(\_SB.PC21, Arg1) + Notify(\_SB.PC22, Arg1) + Notify(\_SB.PC23, Arg1) =20 + } + } //End Method NTFI + + // Tell OS to run thru the new status of this device (Software SCI gener= ated from SMM for all Hot plug events) + Method (_L62, 0x0, NotSerialized) { + if(LEqual(SCI0, 3)) { // Device ejection (Invoked with _EJ0 method cal= led) + Store (0, SCI0) + } else { // Device check (OS can still reject online requ= est based on resources and capability) + NTFI (IIOP, 0) + Store (0, MEBC) + Store (0, CPHP) + Store (0, IIOP) + } + Store (0, SGPC) + Store (1, SGPS) + + } + + // PME supported for Slots, use GPE 9 for PME + // Hot plug on all slots for now, change later. + // Slot numbers on silk screen might be different than the port number, = currently use port numbers. + // + // IIO PCI_E Slot Hotplug GPE Event + // + Method (_L61, 0, NotSerialized) { + #include "IioPcieHotPlugGpeHandler.asl" + }// end of _L01 GPE Method + +}// end of _GPE scope. diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1E= jd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.a= si new file mode 100644 index 0000000000..2cbe3aa5cc --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi @@ -0,0 +1,9 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // Eject device if SCK1 is removed. + Name(_EJD,"\\_SB.SCK1") // Dependent on SCK1 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2E= jd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.a= si new file mode 100644 index 0000000000..4a89bb99d6 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi @@ -0,0 +1,9 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // Eject device if SCK2 is removed. + Name(_EJD,"\\_SB.SCK2") // Dependent on SCK2 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3E= jd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.a= si new file mode 100644 index 0000000000..8cbaeffeb5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi @@ -0,0 +1,9 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // Eject device if SCK3 is removed. + Name(_EJD,"\\_SB.SCK3") // Dependent on SCK3 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncor= e0.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.a= si new file mode 100644 index 0000000000..a5a447d037 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi @@ -0,0 +1,33 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (PRU0, Package() { + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 } + }) + + Name (ARU0, Package() { + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 } + }) + + + Device (UNC0) { + Name (_UID, "UNCORE0") + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PRU0) + } + Return (ARU0) + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncor= e1.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.a= si new file mode 100644 index 0000000000..a86aaa7b3f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi @@ -0,0 +1,175 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (PRU1, Package() { + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (ARU1, Package() { + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + // + // Devices 8 - 31 on PStack + // + Device (UNC1) { + Name (_UID, "UNCORE1") + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PRU1) + } + Return (ARU1) + } + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncor= e2.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.a= si new file mode 100644 index 0000000000..dc7453c294 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi @@ -0,0 +1,125 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (PRU2, Package() { + // + // PCIe2 PortA/NTB =20 + // + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + }) + + Name (ARU2, Package() { + // + // PCIe2 PortA/NTB =20 + // + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + + + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + + }) + + // + // Devices 8 - 31 on each stack + // + Device (UNC2) { + Name (_UID, "UNCORE2") + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PRU2) + } + Return (ARU2) + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncor= e3.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.a= si new file mode 100644 index 0000000000..f59e04539b --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi @@ -0,0 +1,98 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + Name (PRU3, Package() { + + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + + Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + }) + + Name (ARU3, Package() { + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + // + // Devices 8 - 31 on each stack + // + Device (UNC3) { + Name (_UID, "UNCORE3") + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PRU3) + } + Return (ARU3) + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPl= atform.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPl= atform.asl new file mode 100644 index 0000000000..254806cbc8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.= asl @@ -0,0 +1,189 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +DefinitionBlock ("WFPPlatform.asl","DSDT",2,"INTEL","PLATWFP ",3) +{ + + #include "CommonPlatform.asi" + #include "PlatformPciTree_WFP.asi" + #include "AMLUPD.asl" + #include "DSDT.ASL" + #include "Pch.asl" //This is in another package (PchPkg) + #include "Platform.asl" + #include "PlatformGpe.asi" + #include "PcieSeg.asi" +=20 + Scope (\_SB.PC00.XHCI.RHUB) { + + + + // + // Method for creating generic _PLD buffers + // _PLD contains lots of data, but for purpose of internal validation = we care only about + // ports' visibility and pairing (this requires group position) + // so these are the only 2 configurable parameters (User Visible, Grou= p Position) + // + Method(GPLD, 2, Serialized) { + Name(PCKG, Package() { Buffer(0x10) {} } ) + CreateField(DerefOf(Index(PCKG,0)), 0, 7, REV) + Store(1,REV) + CreateField(DerefOf(Index(PCKG,0)), 64, 1, VISI) + Store(Arg0, VISI) + CreateField(DerefOf(Index(PCKG,0)), 87, 8, GPOS) + Store(Arg1, GPOS) + + + return (PCKG) + } + + // + // Method for creating generic _UPC buffers + // Similar to _PLD, for internal testing we only care about 1 paramete= r (port connectable) + // + Method(GUPC, 1, Serialized) { + Name(PCKG, Package(4) { 0, 0xFF, 0, 0 } ) + Store(Arg0,Index(PCKG,0)) + + + return (PCKG) + } + + + + } //end scope RHUB + + Scope (\_SB.PC00.XHCI.RHUB.HS01) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,1)) } //Rear Panel A [CONN27] - Upper - = usb2 port=20 + } + + Scope (\_SB.PC00.XHCI.RHUB.HS02) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,2)) } //Rear Panel A [CONN27] - Center -= usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS03) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,3)) } //Rear Panel A [CONN27] - Bottom -= usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS04) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,4)) } //Internal A1 [CONN9] - Right - us= b2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS05) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,5)) } //Front Panel [CONN20] - Right - u= sb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS06) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,6)) } //Front Panel [CONN20] - Left - us= b2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS07) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,7)) } //Internal Type A3 [CONN4] - ? - u= sb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS08) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,8)) } //Internal Type A3 [CONN4] - ? - u= sb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS09) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,9)) } //Jacksonville [CONN22] - Bottom -= usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS10) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,10)) } //Usb daughter card [CONN14] - ? = - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS11) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(0,11)) } //Jacksonville [CONN22] - Center = - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS12) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(0,12)) } //Usb daughter card [CONN14] - ? = - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS13) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,13)) } //Internal A1 [CONN4] - Left - us= b2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS14) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,14)) } //Usb daughter card [CONN14] - ? = - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.USR1) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) } + } + + Scope (\_SB.PC00.XHCI.RHUB.USR2) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) }=20 + } + + Scope (\_SB.PC00.XHCI.RHUB.SS01) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,1)) } //Rear Panel A [CONN27] - Upper - = usb3 port=20 + } + + Scope (\_SB.PC00.XHCI.RHUB.SS02) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,2)) } //Rear Panel A [CONN27] - Center -= usb3 port + } + + Scope (\_SB.PC00.XHCI.RHUB.SS03) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,3)) } //Rear Panel A [CONN27] - Bottom -= usb3 port + } + + Scope (\_SB.PC00.XHCI.RHUB.SS04) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,4)) } //Internal A1 [CONN9] - Right - us= b3 port + } + + Scope (\_SB.PC00.XHCI.RHUB.SS05) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,5)) } //Front Panel [CONN20] - Right - u= sb3 port + } + + Scope (\_SB.PC00.XHCI.RHUB.SS06) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,6)) } //Front Panel [CONN20] - Left - us= b3 port + } + + Scope (\_SB.PC00.XHCI.RHUB.SS07) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) } //N/A + } + + Scope (\_SB.PC00.XHCI.RHUB.SS08) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) } //N/A + } + + Scope (\_SB.PC00.XHCI.RHUB.SS09) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) } //N/A + } + + Scope (\_SB.PC00.XHCI.RHUB.SS10) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) } //N/A + } + +} // end of DSDT --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Tue, 11 May 2021 02:48:59 -0700 IronPort-SDR: 6nMdICrpDLLIsLG9ZgnnzwvSc05iLjb68CRF5kzGvnQPTEKkqGdy7e9UNBMXaBWdd6d+GkAm2Y 3jizFWXimkng== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="178994725" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="178994725" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:55 -0700 IronPort-SDR: qqz3zuRXIWa4RUuWed04qkjaTFlsR2cMSaysEcRC/Ww32K8DJaJo1pX6Eba6Jf1+4GWgSTC8D4 UDf2C3i8PFJA== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436574022" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:54 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 13/18] PurleyOpenBoardPkg/Acpi: Add BoardAcpiDxe Date: Tue, 11 May 2021 02:48:21 -0700 Message-Id: <20210511094826.12495-14-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: eApNTLmo1SP2US5M6jrnZ6Kox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726541; bh=lOQvM1O82yN8+SKGuaUUo0jqG6L9AXRUR/hHZFuu39g=; h=Cc:Date:From:Reply-To:Subject:To; b=AzmknPXNd5u2ABUglglcpIrHBjUbwgw1fA2VLM/eR34oNh5+3jarROkiqFQYGeEfZRS o1xdgub/6oDlbxoqQoWCvcTluXSUx2cuLxAQSfsrMWQ8bw+/pS16gXUGAVN31sy5Zh7kZ xzVNE07IM0zQJOatxMzf0yDGJ7LlEcJ6DlI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../Acpi/BoardAcpiDxe/AmlOffsetTable.c | 290 ++++++++++ .../Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 547 ++++++++++++++++++ .../Acpi/BoardAcpiDxe/BoardAcpiDxe.h | 82 +++ .../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf | 71 +++ .../Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c | 516 +++++++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt.inf | 29 + 6 files changed, 1535 insertions(+) create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Aml= OffsetTable.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Boa= rdAcpiDxe.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Boa= rdAcpiDxe.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Boa= rdAcpiDxe.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Boa= rdAcpiDxeDsdt.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t.inf diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetT= able.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable= .c new file mode 100644 index 0000000000..abb484172e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c @@ -0,0 +1,290 @@ +/** @file + Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/* + *=20 + * Intel ACPI Component Architecture + *=20 + *=20 + */ +#ifndef __AML_OFFSET_TABLE_H +#define __AML_OFFSET_TABLE_H + +typedef struct { + char *Pathname; /* Full pathname (from root) to= the object */ + unsigned short ParentOpcode; /* AML opcode for the parent ob= ject */ + unsigned long NamesegOffset; /* Offset of last nameseg in th= e parent namepath */ + unsigned char Opcode; /* AML opcode for the data */ + unsigned long Offset; /* Offset for the data */ + unsigned long long Value; /* Original value of the data (= as applicable) */ +} AML_OFFSET_TABLE_ENTRY; + +#endif /* __AML_OFFSET_TABLE_H */ + +/* + * Information specific to the supported object types: + * + * Integers: + * Opcode is the integer prefix, indicates length of the data + * (One of: BYTE, WORD, DWORD, QWORD, ZERO, ONE, ONES) + * Offset points to the actual integer data + * Value is the existing value in the AML + * + * Packages: + * Opcode is the package or var_package opcode + * Offset points to the package opcode + * Value is the package element count + * + * Operation Regions: + * Opcode is the address integer prefix, indicates length of the data + * Offset points to the region address + * Value is the existing address value in the AML + * + * Control Methods: + * Offset points to the method flags byte + * Value is the existing flags value in the AML + * + * Processors: + * Offset points to the first byte of the PBlock Address + * + * Resource Descriptors: + * Opcode is the descriptor type + * Offset points to the start of the descriptor + * + * Scopes/Devices/ThermalZones: + * Nameseg offset only + */ +AML_OFFSET_TABLE_ENTRY DSDT_PLATWFP__OffsetTable[] =3D +{ + {"PSYS", 0x5B80, 0x0000038B, 0x0C, 0x00000391, 0= x0000000030584946}, /* OPERATIONREGION */ + {"_SB_.PC00.FIX1", 0x0011, 0x00000000, 0x88, 0x0000D187, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC00.FIX2", 0x0011, 0x00000000, 0x88, 0x0000D1AF, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC00.FIX5", 0x0011, 0x00000000, 0x87, 0x0000D1BF, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC00.FIX3", 0x0011, 0x00000000, 0x87, 0x0000D20D, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC00.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000D227, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC01.FIX1", 0x0011, 0x00000000, 0x88, 0x0000EA9B, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC01.FIX5", 0x0011, 0x00000000, 0x87, 0x0000EAAB, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC01.FIX2", 0x0011, 0x00000000, 0x88, 0x0000EAC5, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC01.FIX6", 0x0011, 0x00000000, 0x88, 0x0000EAD5, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC01.FIX7", 0x0011, 0x00000000, 0x88, 0x0000EAE5, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC01.FIX3", 0x0011, 0x00000000, 0x87, 0x0000EAF5, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC01.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000EB0F, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC01.BR1A.MCTL", 0x5B80, 0x0000EB91, 0x0C, 0x0000EB97, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC01.BR1B.MCTL", 0x5B80, 0x0000F3B2, 0x0C, 0x0000F3B8, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC01.BR1C.MCTL", 0x5B80, 0x0000FBD3, 0x0C, 0x0000FBD9, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC01.BR1D.MCTL", 0x5B80, 0x000103F4, 0x0C, 0x000103FA, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC02.FIX1", 0x0011, 0x00000000, 0x88, 0x00010E93, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC02.FIX5", 0x0011, 0x00000000, 0x87, 0x00010EA3, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC02.FIX2", 0x0011, 0x00000000, 0x88, 0x00010EBD, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC02.FIX6", 0x0011, 0x00000000, 0x88, 0x00010ECD, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC02.FIX7", 0x0011, 0x00000000, 0x88, 0x00010EDD, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC02.FIX3", 0x0011, 0x00000000, 0x87, 0x00010EED, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC02.FIX4", 0x0011, 0x00000000, 0x8A, 0x00010F07, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC02.BR2A.MCTL", 0x5B80, 0x00010F89, 0x0C, 0x00010F8F, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC02.BR2B.MCTL", 0x5B80, 0x00011969, 0x0C, 0x0001196F, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC02.BR2C.MCTL", 0x5B80, 0x0001218A, 0x0C, 0x00012190, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC02.BR2D.MCTL", 0x5B80, 0x000129AB, 0x0C, 0x000129B1, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC03.FIX1", 0x0011, 0x00000000, 0x88, 0x000133E4, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC03.FIX5", 0x0011, 0x00000000, 0x87, 0x000133F4, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC03.FIX2", 0x0011, 0x00000000, 0x88, 0x0001340E, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC03.FIX6", 0x0011, 0x00000000, 0x88, 0x0001341E, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC03.FIX7", 0x0011, 0x00000000, 0x88, 0x0001342E, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC03.FIX3", 0x0011, 0x00000000, 0x87, 0x0001343E, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC03.FIX4", 0x0011, 0x00000000, 0x8A, 0x00013458, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC03.BR3A.MCTL", 0x5B80, 0x000134DA, 0x0C, 0x000134E0, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC03.BR3B.MCTL", 0x5B80, 0x00013CFB, 0x0C, 0x00013D01, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC03.BR3C.MCTL", 0x5B80, 0x0001451C, 0x0C, 0x00014522, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC03.BR3D.MCTL", 0x5B80, 0x00014D3D, 0x0C, 0x00014D43, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC04.FIX1", 0x0011, 0x00000000, 0x88, 0x000156F0, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC04.FIX5", 0x0011, 0x00000000, 0x87, 0x00015700, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC04.FIX2", 0x0011, 0x00000000, 0x88, 0x0001571A, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC04.FIX6", 0x0011, 0x00000000, 0x88, 0x0001572A, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC04.FIX7", 0x0011, 0x00000000, 0x88, 0x0001573A, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC04.FIX3", 0x0011, 0x00000000, 0x87, 0x0001574A, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC04.FIX4", 0x0011, 0x00000000, 0x8A, 0x00015764, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC04.MCP0.MCTL", 0x5B80, 0x000157E6, 0x0C, 0x000157EC, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC05.FIX1", 0x0011, 0x00000000, 0x88, 0x0001612D, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC05.FIX5", 0x0011, 0x00000000, 0x87, 0x0001613D, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC05.FIX2", 0x0011, 0x00000000, 0x88, 0x00016157, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC05.FIX6", 0x0011, 0x00000000, 0x88, 0x00016167, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC05.FIX7", 0x0011, 0x00000000, 0x88, 0x00016177, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC05.FIX3", 0x0011, 0x00000000, 0x87, 0x00016187, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC05.FIX4", 0x0011, 0x00000000, 0x8A, 0x000161A1, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC05.MCP1.MCTL", 0x5B80, 0x00016223, 0x0C, 0x00016229, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC06.FIX1", 0x0011, 0x00000000, 0x88, 0x00016FD9, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC06.FIX5", 0x0011, 0x00000000, 0x87, 0x00016FE9, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC06.FIX2", 0x0011, 0x00000000, 0x88, 0x00017003, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC06.FIX6", 0x0011, 0x00000000, 0x88, 0x00017013, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC06.FIX7", 0x0011, 0x00000000, 0x88, 0x00017023, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC06.FIX3", 0x0011, 0x00000000, 0x87, 0x00017033, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC06.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001704D, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC06.QRP0.MCTL", 0x5B80, 0x00017149, 0x0C, 0x0001714F, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC07.FIX1", 0x0011, 0x00000000, 0x88, 0x00017BC4, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC07.FIX5", 0x0011, 0x00000000, 0x87, 0x00017BD4, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC07.FIX2", 0x0011, 0x00000000, 0x88, 0x00017BEE, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC07.FIX6", 0x0011, 0x00000000, 0x88, 0x00017BFE, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC07.FIX7", 0x0011, 0x00000000, 0x88, 0x00017C0E, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC07.FIX3", 0x0011, 0x00000000, 0x87, 0x00017C1E, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC07.FIX4", 0x0011, 0x00000000, 0x8A, 0x00017C38, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC07.QR1A.MCTL", 0x5B80, 0x00017CCA, 0x0C, 0x00017CD0, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC07.QR1B.MCTL", 0x5B80, 0x00018506, 0x0C, 0x0001850C, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC07.QR1C.MCTL", 0x5B80, 0x00018D42, 0x0C, 0x00018D48, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC07.QR1D.MCTL", 0x5B80, 0x0001957E, 0x0C, 0x00019584, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC08.FIX1", 0x0011, 0x00000000, 0x88, 0x0001A04E, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC08.FIX5", 0x0011, 0x00000000, 0x87, 0x0001A05E, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC08.FIX2", 0x0011, 0x00000000, 0x88, 0x0001A078, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC08.FIX6", 0x0011, 0x00000000, 0x88, 0x0001A088, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC08.FIX7", 0x0011, 0x00000000, 0x88, 0x0001A098, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC08.FIX3", 0x0011, 0x00000000, 0x87, 0x0001A0A8, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC08.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001A0C2, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC08.QR2A.MCTL", 0x5B80, 0x0001A154, 0x0C, 0x0001A15A, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC08.QR2B.MCTL", 0x5B80, 0x0001A990, 0x0C, 0x0001A996, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC08.QR2C.MCTL", 0x5B80, 0x0001B1CC, 0x0C, 0x0001B1D2, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC08.QR2D.MCTL", 0x5B80, 0x0001BA08, 0x0C, 0x0001BA0E, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC09.FIX1", 0x0011, 0x00000000, 0x88, 0x0001C461, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC09.FIX5", 0x0011, 0x00000000, 0x87, 0x0001C471, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC09.FIX2", 0x0011, 0x00000000, 0x88, 0x0001C48B, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC09.FIX6", 0x0011, 0x00000000, 0x88, 0x0001C49B, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC09.FIX7", 0x0011, 0x00000000, 0x88, 0x0001C4AB, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC09.FIX3", 0x0011, 0x00000000, 0x87, 0x0001C4BB, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC09.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001C4D5, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC09.QR3A.MCTL", 0x5B80, 0x0001C567, 0x0C, 0x0001C56D, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC09.QR3B.MCTL", 0x5B80, 0x0001CDA3, 0x0C, 0x0001CDA9, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC09.QR3C.MCTL", 0x5B80, 0x0001D5DF, 0x0C, 0x0001D5E5, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC09.QR3D.MCTL", 0x5B80, 0x0001DE1B, 0x0C, 0x0001DE21, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC10.FIX1", 0x0011, 0x00000000, 0x88, 0x0001E7EE, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC10.FIX5", 0x0011, 0x00000000, 0x87, 0x0001E7FE, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC10.FIX2", 0x0011, 0x00000000, 0x88, 0x0001E818, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC10.FIX6", 0x0011, 0x00000000, 0x88, 0x0001E828, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC10.FIX7", 0x0011, 0x00000000, 0x88, 0x0001E838, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC10.FIX3", 0x0011, 0x00000000, 0x87, 0x0001E848, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC10.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001E862, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC10.MCP2.MCTL", 0x5B80, 0x0001E8F4, 0x0C, 0x0001E8FA, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC11.FIX1", 0x0011, 0x00000000, 0x88, 0x0001F250, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC11.FIX5", 0x0011, 0x00000000, 0x87, 0x0001F260, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC11.FIX2", 0x0011, 0x00000000, 0x88, 0x0001F27A, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC11.FIX6", 0x0011, 0x00000000, 0x88, 0x0001F28A, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC11.FIX7", 0x0011, 0x00000000, 0x88, 0x0001F29A, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC11.FIX3", 0x0011, 0x00000000, 0x87, 0x0001F2AA, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC11.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001F2C4, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC11.MCP3.MCTL", 0x5B80, 0x0001F356, 0x0C, 0x0001F35C, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC12.FIX1", 0x0011, 0x00000000, 0x88, 0x0002011C, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC12.FIX5", 0x0011, 0x00000000, 0x87, 0x0002012C, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC12.FIX2", 0x0011, 0x00000000, 0x88, 0x00020146, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC12.FIX6", 0x0011, 0x00000000, 0x88, 0x00020156, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC12.FIX7", 0x0011, 0x00000000, 0x88, 0x00020166, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC12.FIX3", 0x0011, 0x00000000, 0x87, 0x00020176, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC12.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020190, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC12.RRP0.MCTL", 0x5B80, 0x0002028C, 0x0C, 0x00020292, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC13.FIX1", 0x0011, 0x00000000, 0x88, 0x00020D07, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC13.FIX5", 0x0011, 0x00000000, 0x87, 0x00020D17, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC13.FIX2", 0x0011, 0x00000000, 0x88, 0x00020D31, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC13.FIX6", 0x0011, 0x00000000, 0x88, 0x00020D41, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC13.FIX7", 0x0011, 0x00000000, 0x88, 0x00020D51, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC13.FIX3", 0x0011, 0x00000000, 0x87, 0x00020D61, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC13.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020D7B, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC13.RR1A.MCTL", 0x5B80, 0x00020E0D, 0x0C, 0x00020E13, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC13.RR1B.MCTL", 0x5B80, 0x00021649, 0x0C, 0x0002164F, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC13.RR1C.MCTL", 0x5B80, 0x00021E85, 0x0C, 0x00021E8B, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC13.RR1D.MCTL", 0x5B80, 0x000226C1, 0x0C, 0x000226C7, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC14.FIX1", 0x0011, 0x00000000, 0x88, 0x0002316F, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC14.FIX5", 0x0011, 0x00000000, 0x87, 0x0002317F, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC14.FIX2", 0x0011, 0x00000000, 0x88, 0x00023199, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC14.FIX6", 0x0011, 0x00000000, 0x88, 0x000231A9, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC14.FIX7", 0x0011, 0x00000000, 0x88, 0x000231B9, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC14.FIX3", 0x0011, 0x00000000, 0x87, 0x000231C9, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC14.FIX4", 0x0011, 0x00000000, 0x8A, 0x000231E3, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC14.RR2A.MCTL", 0x5B80, 0x00023275, 0x0C, 0x0002327B, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC14.RR2B.MCTL", 0x5B80, 0x00023AB1, 0x0C, 0x00023AB7, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC14.RR2C.MCTL", 0x5B80, 0x000242ED, 0x0C, 0x000242F3, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC14.RR2D.MCTL", 0x5B80, 0x00024B29, 0x0C, 0x00024B2F, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC15.FIX1", 0x0011, 0x00000000, 0x88, 0x00025582, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC15.FIX5", 0x0011, 0x00000000, 0x87, 0x00025592, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC15.FIX2", 0x0011, 0x00000000, 0x88, 0x000255AC, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC15.FIX6", 0x0011, 0x00000000, 0x88, 0x000255BC, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC15.FIX7", 0x0011, 0x00000000, 0x88, 0x000255CC, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC15.FIX3", 0x0011, 0x00000000, 0x87, 0x000255DC, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC15.FIX4", 0x0011, 0x00000000, 0x8A, 0x000255F6, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC15.RR3A.MCTL", 0x5B80, 0x00025688, 0x0C, 0x0002568E, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC15.RR3B.MCTL", 0x5B80, 0x00025EC4, 0x0C, 0x00025ECA, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC15.RR3C.MCTL", 0x5B80, 0x00026700, 0x0C, 0x00026706, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC15.RR3D.MCTL", 0x5B80, 0x00026F3C, 0x0C, 0x00026F42, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC16.FIX1", 0x0011, 0x00000000, 0x88, 0x0002790F, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC16.FIX5", 0x0011, 0x00000000, 0x87, 0x0002791F, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC16.FIX2", 0x0011, 0x00000000, 0x88, 0x00027939, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC16.FIX6", 0x0011, 0x00000000, 0x88, 0x00027949, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC16.FIX7", 0x0011, 0x00000000, 0x88, 0x00027959, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC16.FIX3", 0x0011, 0x00000000, 0x87, 0x00027969, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC16.FIX4", 0x0011, 0x00000000, 0x8A, 0x00027983, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC16.MCP4.MCTL", 0x5B80, 0x00027A15, 0x0C, 0x00027A1B, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC17.FIX1", 0x0011, 0x00000000, 0x88, 0x00028371, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC17.FIX5", 0x0011, 0x00000000, 0x87, 0x00028381, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC17.FIX2", 0x0011, 0x00000000, 0x88, 0x0002839B, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC17.FIX6", 0x0011, 0x00000000, 0x88, 0x000283AB, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC17.FIX7", 0x0011, 0x00000000, 0x88, 0x000283BB, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC17.FIX3", 0x0011, 0x00000000, 0x87, 0x000283CB, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC17.FIX4", 0x0011, 0x00000000, 0x8A, 0x000283E5, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC17.MCP5.MCTL", 0x5B80, 0x00028477, 0x0C, 0x0002847D, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC18.FIX1", 0x0011, 0x00000000, 0x88, 0x0002923D, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC18.FIX5", 0x0011, 0x00000000, 0x87, 0x0002924D, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC18.FIX2", 0x0011, 0x00000000, 0x88, 0x00029267, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC18.FIX6", 0x0011, 0x00000000, 0x88, 0x00029277, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC18.FIX7", 0x0011, 0x00000000, 0x88, 0x00029287, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC18.FIX3", 0x0011, 0x00000000, 0x87, 0x00029297, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC18.FIX4", 0x0011, 0x00000000, 0x8A, 0x000292B1, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC18.SRP0.MCTL", 0x5B80, 0x000293AD, 0x0C, 0x000293B3, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC19.FIX1", 0x0011, 0x00000000, 0x88, 0x00029E28, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC19.FIX5", 0x0011, 0x00000000, 0x87, 0x00029E38, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC19.FIX2", 0x0011, 0x00000000, 0x88, 0x00029E52, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC19.FIX6", 0x0011, 0x00000000, 0x88, 0x00029E62, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC19.FIX7", 0x0011, 0x00000000, 0x88, 0x00029E72, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC19.FIX3", 0x0011, 0x00000000, 0x87, 0x00029E82, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC19.FIX4", 0x0011, 0x00000000, 0x8A, 0x00029E9C, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC19.SR1A.MCTL", 0x5B80, 0x00029F2E, 0x0C, 0x00029F34, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC19.SR1B.MCTL", 0x5B80, 0x0002A76A, 0x0C, 0x0002A770, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC19.SR1C.MCTL", 0x5B80, 0x0002AFA6, 0x0C, 0x0002AFAC, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC19.SR1D.MCTL", 0x5B80, 0x0002B7E2, 0x0C, 0x0002B7E8, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC20.FIX1", 0x0011, 0x00000000, 0x88, 0x0002C2B2, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC20.FIX5", 0x0011, 0x00000000, 0x87, 0x0002C2C2, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC20.FIX2", 0x0011, 0x00000000, 0x88, 0x0002C2DC, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC20.FIX6", 0x0011, 0x00000000, 0x88, 0x0002C2EC, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC20.FIX7", 0x0011, 0x00000000, 0x88, 0x0002C2FC, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC20.FIX3", 0x0011, 0x00000000, 0x87, 0x0002C30C, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC20.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002C326, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC20.SR2A.MCTL", 0x5B80, 0x0002C3B8, 0x0C, 0x0002C3BE, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC20.SR2B.MCTL", 0x5B80, 0x0002CBF4, 0x0C, 0x0002CBFA, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC20.SR2C.MCTL", 0x5B80, 0x0002D430, 0x0C, 0x0002D436, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC20.SR2D.MCTL", 0x5B80, 0x0002DC6C, 0x0C, 0x0002DC72, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC21.FIX1", 0x0011, 0x00000000, 0x88, 0x0002E6C5, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC21.FIX5", 0x0011, 0x00000000, 0x87, 0x0002E6D5, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC21.FIX2", 0x0011, 0x00000000, 0x88, 0x0002E6EF, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC21.FIX6", 0x0011, 0x00000000, 0x88, 0x0002E6FF, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC21.FIX7", 0x0011, 0x00000000, 0x88, 0x0002E70F, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC21.FIX3", 0x0011, 0x00000000, 0x87, 0x0002E71F, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC21.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002E739, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC21.SR3A.MCTL", 0x5B80, 0x0002E7CB, 0x0C, 0x0002E7D1, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC21.SR3B.MCTL", 0x5B80, 0x0002F007, 0x0C, 0x0002F00D, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC21.SR3C.MCTL", 0x5B80, 0x0002F843, 0x0C, 0x0002F849, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC21.SR3D.MCTL", 0x5B80, 0x0003007F, 0x0C, 0x00030085, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC22.FIX1", 0x0011, 0x00000000, 0x88, 0x00030A52, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC22.FIX5", 0x0011, 0x00000000, 0x87, 0x00030A62, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC22.FIX2", 0x0011, 0x00000000, 0x88, 0x00030A7C, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC22.FIX6", 0x0011, 0x00000000, 0x88, 0x00030A8C, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC22.FIX7", 0x0011, 0x00000000, 0x88, 0x00030A9C, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC22.FIX3", 0x0011, 0x00000000, 0x87, 0x00030AAC, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC22.FIX4", 0x0011, 0x00000000, 0x8A, 0x00030AC6, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC22.MCP6.MCTL", 0x5B80, 0x00030B58, 0x0C, 0x00030B5E, 0= x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC23.FIX1", 0x0011, 0x00000000, 0x88, 0x000314B4, 0= x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC23.FIX5", 0x0011, 0x00000000, 0x87, 0x000314C4, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC23.FIX2", 0x0011, 0x00000000, 0x88, 0x000314DE, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC23.FIX6", 0x0011, 0x00000000, 0x88, 0x000314EE, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC23.FIX7", 0x0011, 0x00000000, 0x88, 0x000314FE, 0= x0000000000000000}, /* WORDIO */ + {"_SB_.PC23.FIX3", 0x0011, 0x00000000, 0x87, 0x0003150E, 0= x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC23.FIX4", 0x0011, 0x00000000, 0x8A, 0x00031528, 0= x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC23.MCP7.MCTL", 0x5B80, 0x000315BA, 0x0C, 0x000315C0, 0= x0000000038584946}, /* OPERATIONREGION */ + {NULL,0,0,0,0,0} /* Table terminator */ +}; + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiD= xe.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c new file mode 100644 index 0000000000..66da23c561 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c @@ -0,0 +1,547 @@ +/** @file + +Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "BoardAcpiDxe.h" + +EFI_STATUS +PatchDsdtTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table + ); + +#pragma optimize("",off) + +BIOS_ACPI_PARAM *mAcpiParameter; + +EFI_IIO_UDS_PROTOCOL *mIioUds; + +UINT32 mNumOfBitShift; +BOOLEAN mForceX2ApicId; +BOOLEAN mX2ApicEnabled; + +struct SystemMemoryMapHob *mSystemMemoryMap; + +SOCKET_MP_LINK_CONFIGURATION mSocketMpLinkConfiguration; +SOCKET_IIO_CONFIGURATION mSocketIioConfiguration; +SOCKET_POWERMANAGEMENT_CONFIGURATION mSocketPowermanagementConfiguration; + +BOOLEAN mFirstNotify; +PCH_RC_CONFIGURATION mPchRcConfiguration; + +UINT8 mKBPresent =3D 0; +UINT8 mMousePresent =3D 0; + +/** + + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI tab= le + storage file. + + @param Protocol - The protocol to find. + Instance - Return pointer to the first instance of the protocol. + Type - The type of protocol to locate. + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_NOT_FOUND - The protocol could not be located. + @retval EFI_OUT_OF_RESOURCES - There are not enough resources to find = the protocol. + +**/ +EFI_STATUS +LocateSupportProtocol ( + IN EFI_GUID *Protocol, + IN EFI_GUID *gEfiAcpiMultiTableStorageGuid, + OUT VOID **Instance, + IN UINT32 Type + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN Index; + + FvStatus =3D 0; + // + // Locate protocol. + // + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + Protocol, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + // + // Looking for FV with ACPI storage file + // + for (Index =3D 0; Index < NumberOfHandles; Index++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + Protocol, + Instance + ); + ASSERT (!EFI_ERROR (Status)); + + if (!Type) { + // + // Not looking for the FV protocol, so find the first instance of the + // protocol. There should not be any errors because our handle buff= er + // should always contain at least one or LocateHandleBuffer would ha= ve + // returned not found. + // + break; + } + // + // See if it has the ACPI storage file + // + Status =3D ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile ( + *Instance, + gEfiAcpiMult= iTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (!EFI_ERROR (Status)) { + break; + } + } + // + // Our exit status is determined by the success of the previous operatio= ns + // If the protocol was found, Instance already points to it. + // + // + // Free any allocated buffers + // + gBS->FreePool (HandleBuffer); + + return Status; +} + +/** + + GC_TODO: add routine description + + @param None + + @retval EFI_SUCCESS - GC_TODO: add retval description + +**/ +EFI_STATUS +PlatformHookInit ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS AcpiParameterAddr; + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + + CopyMem (&mSocketMpLinkConfiguration, PcdGetPtr(PcdSocketMpLinkConfigDat= a), sizeof(SOCKET_MP_LINK_CONFIGURATION)); + CopyMem (&mSocketPowermanagementConfiguration, PcdGetPtr(PcdSocketPowerM= anagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION)); + CopyMem (&mSocketIioConfiguration, PcdGetPtr(PcdSocketIioConfigData), si= zeof(SOCKET_IIO_CONFIGURATION)); + CopyMem (&mPchRcConfiguration, PcdGetPtr(PcdPchRcConfigurationData), siz= eof(PCH_RC_CONFIGURATION)); + + DEBUG ((DEBUG_INFO, "mX2ApicEnabled - 0x%x\n", mX2ApicEnabled)); + DEBUG ((DEBUG_INFO, "mForceX2ApicId - 0x%x\n", mForceX2ApicId)); + + { + UINT32 Index; + + for (Index =3D 0; Index < 4; Index++) { + AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, Index, &RegEax, &RegEbx, &RegEcx= , &RegEdx); + DEBUG ((DEBUG_INFO, "CPUID(0xB - %d) - 0x%08x.0x%08x.0x%08x.0x%08x\n= ", Index, RegEax, RegEbx, RegEcx, RegEdx)); + } + } + + // + // Allocate 256 runtime memory to pass ACPI parameter + // This Address must be < 4G because we only have 32bit in the dsdt + // + AcpiParameterAddr =3D 0xffffffff; + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + EFI_SIZE_TO_PAGES (sizeof(BIOS_ACPI_PARAM)), + &AcpiParameterAddr + ); + ASSERT_EFI_ERROR (Status); + mAcpiParameter =3D (BIOS_ACPI_PARAM *)AcpiParameterAddr; + + DEBUG ((EFI_D_ERROR, "ACPI Parameter Block Address: 0x%X\n", mAcpiParame= ter)); + Status =3D PcdSet64S (PcdAcpiGnvsAddress, (UINT64)(UINTN)mAcpiParameter); + ASSERT_EFI_ERROR (Status); + + ZeroMem (mAcpiParameter, sizeof (BIOS_ACPI_PARAM)); + mAcpiParameter->PlatformId =3D 0; +#if MAX_SOCKET > 4 + mAcpiParameter->IoApicEnable =3D PcdGet32 (PcdPcIoApicEnable); +#else + mAcpiParameter->IoApicEnable =3D (PcdGet32 (PcdPcIoApicEnable) << 1) | = 1; +#endif + DEBUG((EFI_D_ERROR, "io apic settings:%d\n", mAcpiParameter->IoApicEnabl= e)); + + AsmCpuid (CPUID_VERSION_INFO, &RegEax, &RegEbx, &RegEcx, &RegEdx); + mAcpiParameter->ProcessorId =3D (RegEax & 0xFFFF0); + + // support up to 64 threads/socket + AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NULL= ); + mNumOfBitShift &=3D 0x1F; + + // Set the bit shift value for CPU SKU + mAcpiParameter->CpuSkuNumOfBitShift =3D (UINT8) mNumOfBitShift; + + mAcpiParameter->ProcessorApicIdBase[0] =3D (UINT32) (0 << mNumOfBitShift= ); + mAcpiParameter->ProcessorApicIdBase[1] =3D (UINT32) (1 << mNumOfBitShift= ); + mAcpiParameter->ProcessorApicIdBase[2] =3D (UINT32) (2 << mNumOfBitShift= ); + mAcpiParameter->ProcessorApicIdBase[3] =3D (UINT32) (3 << mNumOfBitShift= ); + mAcpiParameter->ProcessorApicIdBase[4] =3D (UINT32) (4 << mNumOfBitShift= ); + mAcpiParameter->ProcessorApicIdBase[5] =3D (UINT32) (5 << mNumOfBitShift= ); + mAcpiParameter->ProcessorApicIdBase[6] =3D (UINT32) (6 << mNumOfBitShift= ); + mAcpiParameter->ProcessorApicIdBase[7] =3D (UINT32) (7 << mNumOfBitShift= ); + + if(mForceX2ApicId) { + mAcpiParameter->ProcessorApicIdBase[0] =3D 0x7F00; + mAcpiParameter->ProcessorApicIdBase[1] =3D 0x7F20; + mAcpiParameter->ProcessorApicIdBase[2] =3D 0x7F40; + mAcpiParameter->ProcessorApicIdBase[3] =3D 0x7F60; + mAcpiParameter->ProcessorApicIdBase[4] =3D 0x7F80; + mAcpiParameter->ProcessorApicIdBase[5] =3D 0x7Fa0; + mAcpiParameter->ProcessorApicIdBase[6] =3D 0x7Fc0; + mAcpiParameter->ProcessorApicIdBase[7] =3D 0x7Fe0; + + if (mNumOfBitShift =3D=3D 4) { + mAcpiParameter->ProcessorApicIdBase[0] =3D 0x7F00; + mAcpiParameter->ProcessorApicIdBase[1] =3D 0x7F10; + mAcpiParameter->ProcessorApicIdBase[2] =3D 0x7F20; + mAcpiParameter->ProcessorApicIdBase[3] =3D 0x7F30; + mAcpiParameter->ProcessorApicIdBase[4] =3D 0x7F40; + mAcpiParameter->ProcessorApicIdBase[5] =3D 0x7F50; + mAcpiParameter->ProcessorApicIdBase[6] =3D 0x7F60; + mAcpiParameter->ProcessorApicIdBase[7] =3D 0x7F70; + } else if(mNumOfBitShift =3D=3D 6) { + mAcpiParameter->ProcessorApicIdBase[0] =3D 0x7E00; + mAcpiParameter->ProcessorApicIdBase[1] =3D 0x7E20; + mAcpiParameter->ProcessorApicIdBase[2] =3D 0x7E40; + mAcpiParameter->ProcessorApicIdBase[3] =3D 0x7E60; + mAcpiParameter->ProcessorApicIdBase[4] =3D 0x7E80; + mAcpiParameter->ProcessorApicIdBase[5] =3D 0x7Ea0; + mAcpiParameter->ProcessorApicIdBase[6] =3D 0x7Ec0; + mAcpiParameter->ProcessorApicIdBase[7] =3D 0x7Ee0; + } + } + + // + // If SNC is enabled, and NumOfCluster is 2, set the ACPI variable for P= XM value + // + if(mIioUds->IioUdsPtr->SystemStatus.OutSncEn && (mIioUds->IioUdsPtr->Sys= temStatus.OutNumOfCluster =3D=3D 2)){ + mAcpiParameter->SncAnd2Cluster =3D 1; + } else { + mAcpiParameter->SncAnd2Cluster =3D 0; + } + + mAcpiParameter->MmCfg =3D (UINT32)mIioUds->IioUdsPtr->PlatformData.PciE= xpressBase; + mAcpiParameter->TsegSize =3D (UINT32)(mIioUds->IioUdsPtr->PlatformData.= MemTsegSize >> 20); + + return EFI_SUCCESS; +} + +/** + + This function will update any runtime platform specific information. + This currently includes: + Setting OEM table values, ID, table ID, creator ID and creator revisio= n. + Enabling the proper processor entries in the APIC tables. + + @param Table - The table to update + + @retval EFI_SUCCESS - The function completed successfully. + +**/ +EFI_STATUS +PlatformUpdateTables ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + // + // By default, a table belongs in all ACPI table versions published. + // Some tables will override this because they have different versions o= f the table. + // + *Version =3D EFI_ACPI_TABLE_VERSION_2_0; + // + // Update the processors in the APIC table + // + switch (Table->Signature) { + + case EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE: + // + // Patch the memory resource + // + Status =3D PatchDsdtTable(Table); + break; + + default: + ASSERT(FALSE); + break; + } + // + // + // Update the hardware signature in the FACS structure + // + // + // + return Status; +} + + + +/** + + GC_TODO: Add function description + + @param Event - GC_TODO: add argument description + @param Context - GC_TODO: add argument description + + @retval GC_TODO: add return values + +**/ +STATIC +VOID +EFIAPI +OnReadyToBoot ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + + if (mFirstNotify) { + return ; + } + + mFirstNotify =3D TRUE; + + CopyMem (&mSocketIioConfiguration, PcdGetPtr(PcdSocketIioConfigData), si= zeof(SOCKET_IIO_CONFIGURATION)); + CopyMem (&mSocketPowermanagementConfiguration,PcdGetPtr(PcdSocketPowerMa= nagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION)); + CopyMem (&mPchRcConfiguration, PcdGetPtr(PcdPchRcConfigurationData), siz= eof(PCH_RC_CONFIGURATION)); + + // CpuPm.Asl: External (CSEN, FieldUnitObj) + mAcpiParameter->CStateEnable =3D !mSocketPowermanagementConfiguration.Pr= ocessorAutonomousCstateEnable; + // CpuPm.Asl: External (C3EN, FieldUnitObj) + mAcpiParameter->C3Enable =3D mSocketPowermanagementConfiguration.C3E= nable; + // CpuPm.Asl: External (C6EN, FieldUnitObj) + if (mSocketPowermanagementConfiguration.C6Enable =3D=3D PPM_AUTO) { + mAcpiParameter->C6Enable =3D 1; //POR Default =3D Enabled + } else { + mAcpiParameter->C6Enable =3D mSocketPowermanagementConfiguration.C= 6Enable; + } + if(mAcpiParameter->C6Enable && mAcpiParameter->C3Enable) { //C3 and C6 = enable are exclusive + mAcpiParameter->C6Enable =3D 1; + mAcpiParameter->C3Enable =3D 0; + } + // CpuPm.Asl: External (C7EN, FieldUnitObj) + mAcpiParameter->C7Enable =3D 0; + // CpuPm.Asl: External (OSCX, FieldUnitObj) + mAcpiParameter->OSCX =3D mSocketPowermanagementConfiguration.OSC= x; + // CpuPm.Asl: External (MWOS, FieldUnitObj) + mAcpiParameter->MonitorMwaitEnable =3D 1; + // CpuPm.Asl: External (PSEN, FieldUnitObj) + mAcpiParameter->PStateEnable =3D mSocketPowermanagementConfiguration.Pro= cessorEistEnable; + // CpuPm.Asl: External (HWAL, FieldUnitObj) + mAcpiParameter->HWAllEnable =3D 0; //Update in PatchGv3SsdtTable + + mAcpiParameter->KBPresent =3D mKBPresent; + mAcpiParameter->MousePresent =3D mMousePresent; + mAcpiParameter->TStateEnable =3D mSocketPowermanagementConfiguration.TSt= ateEnable; + //Fine grained T state + AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &RegEax, &RegEbx, &RegEcx, &R= egEdx); + if ((RegEax & EFI_FINE_GRAINED_CLOCK_MODULATION) && (mSocketPowermanagem= entConfiguration.OnDieThermalThrottling > 0)){ + mAcpiParameter->TStateFineGrained =3D 1; + } + if(RegEax & B_CPUID_POWER_MANAGEMENT_EAX_HWP_LVT_INTERRUPT_SUPPORT) { + mAcpiParameter->HwpInterrupt =3D 1; + } + // CpuPm.Asl: External (HWEN, FieldUnitObj) + mAcpiParameter->HWPMEnable =3D mSocketPowermanagementConfiguration.Proce= ssorHWPMEnable; + // CpuPm.Asl: External (ACEN, FieldUnitObj) + mAcpiParameter->AutoCstate =3D mSocketPowermanagementConfiguration.Proce= ssorAutonomousCstateEnable; + + mAcpiParameter->EmcaEn =3D 0; + + mAcpiParameter->PcieAcpiHotPlugEnable =3D (UINT8) (BOOLEAN) (mSocketIioC= onfiguration.PcieAcpiHotPlugEnable !=3D 0); + // + // Initialize USB3 mode from setup data + // + // If mode !=3D manual control + // just copy mode from setup + if (mPchRcConfiguration.PchUsbManualMode !=3D 1) { + mAcpiParameter->XhciMode =3D mPchRcConfiguration.PchUsbManualMode; + } + +} + +/** + + Entry point for Acpi platform driver. + + @param ImageHandle - A handle for the image that is initializing this = driver. + @param SystemTable - A pointer to the EFI system table. + + @retval EFI_SUCCESS - Driver initialized successfully. + @retval EFI_LOAD_ERROR - Failed to Initialize or has been loaded. + @retval EFI_OUT_OF_RESOURCES - Could not allocate needed resources. + +**/ +EFI_STATUS +EFIAPI +InstallAcpiBoard ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_STATUS AcpiStatus; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + INTN Instance; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINTN TableHandle; + UINT32 FvStatus; + UINT32 Size; + EFI_EVENT Event; + EFI_ACPI_TABLE_VERSION TableVersion; + EFI_HOB_GUID_TYPE *GuidHob; + + mFirstNotify =3D FALSE; + + TableVersion =3D EFI_ACPI_TABLE_VERSION_NONE; + Instance =3D 0; + CurrentTable =3D NULL; + TableHandle =3D 0; + + // + // Locate the IIO Protocol Interface + // + Status =3D gBS->LocateProtocol (&gEfiIioUdsProtocolGuid,NULL,&mIioUds); + ASSERT_EFI_ERROR (Status); + + GuidHob =3D GetFirstGuidHob (&gEfiMemoryMapGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + mSystemMemoryMap =3D GET_GUID_HOB_DATA(GuidHob); + + PlatformHookInit (); + + // + // Find the AcpiTable protocol + // + Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, &AcpiT= able); + ASSERT_EFI_ERROR (Status); + + // + // Locate the firmware volume protocol + // + Status =3D LocateSupportProtocol ( + &gEfiFirmwareVolume2ProtocolGuid, + &gEfiCallerIdGuid, + &FwVol, + TRUE + ); + ASSERT_EFI_ERROR (Status); + + Status =3D EFI_SUCCESS; + Instance =3D 0; + + // + // Read tables from the storage file. + // + while (!EFI_ERROR (Status)) { + CurrentTable =3D NULL; + + Status =3D FwVol->ReadSection ( + FwVol, + &gEfiCallerIdGuid, + EFI_SECTION_RAW, + Instance, + &CurrentTable, + (UINTN *) &Size, + &FvStatus + ); + + if (!EFI_ERROR (Status)) { + // + // Allow platform specific code to reject the table or update it + // + { + // + // Perform any table specific updates. + // + AcpiStatus =3D PlatformUpdateTables (CurrentTable, &TableVersion); + if (!EFI_ERROR (AcpiStatus)) { + // + // Add the table + // + TableHandle =3D 0; + if (TableVersion !=3D EFI_ACPI_TABLE_VERSION_NONE) { + AcpiStatus =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + CurrentTable->Length, + &TableHandle + ); + } + ASSERT_EFI_ERROR (AcpiStatus); + } + } + // + // Increment the instance + // + Instance++; + } + } + + Status =3D EfiCreateEventReadyToBootEx( + TPL_NOTIFY, + OnReadyToBoot, + NULL, + &Event + ); + + // + // Finished + // + return EFI_SUCCESS; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiD= xe.h b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h new file mode 100644 index 0000000000..fbfd9abc7f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h @@ -0,0 +1,82 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _ACPI_PLATFORM_H_ +#define _ACPI_PLATFORM_H_ + +// +// Statements that include other header files +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "Platform.h" +#include "Register/PchRegsUsb.h" +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "Register/PchRegsUsb.h" + +#include +#define EFI_FINE_GRAINED_CLOCK_MODULATION BIT5 +#define B_CPUID_POWER_MANAGEMENT_EAX_HWP_LVT_INTERRUPT_SUPPORT BIT9 + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiD= xe.inf b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.i= nf new file mode 100644 index 0000000000..cd420b5b88 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf @@ -0,0 +1,71 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BoardAcpiDxe + FILE_GUID =3D F3253A17-2AFE-419E-A5DA-B95A3F7DAB25 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InstallAcpiBoard + +[Sources] + Dsdt/WFPPlatform.asl + AmlOffsetTable.c + BoardAcpiDxe.c + BoardAcpiDxeDsdt.c + +[Packages] + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + BaseMemoryLib + DebugLib + UefiLib + UefiRuntimeServicesTableLib + HobLib + PcdLib + BoardAcpiTableLib + +[Protocols] + gEfiMpServiceProtocolGuid + gEfiIioUdsProtocolGuid + gEfiGlobalNvsAreaProtocolGuid + gEfiPciIoProtocolGuid + gEfiFirmwareVolume2ProtocolGuid + gEfiAcpiTableProtocolGuid + gEfiPciRootBridgeIoProtocolGuid + +[Guids] + gEfiMemoryMapGuid + +[Pcd] + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable + +[Depex] + gEfiAcpiTableProtocolGuid AND + gEfiMpServiceProtocolGuid + +[BuildOptions] + # add -vr and -so to generate offset.h + *_*_*_ASL_FLAGS =3D -oi -vr -so + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiD= xeDsdt.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe= Dsdt.c new file mode 100644 index 0000000000..a4d58cab60 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c @@ -0,0 +1,516 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Statements that include other files +// + +// +// Statements that include other header files +// +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "Register/PchRegsUsb.h" + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +extern BOOLEAN mCpuOrderSorted; + +typedef struct { + char *Pathname; /* Full pathname (from root) to= the object */ + unsigned short ParentOpcode; /* AML opcode for the parent ob= ject */ + unsigned long NamesegOffset; /* Offset of last nameseg in th= e parent namepath */ + unsigned char Opcode; /* AML opcode for the data */ + unsigned long Offset; /* Offset for the data */ + unsigned long long Value; /* Original value of the data (= as applicable) */ +} AML_OFFSET_TABLE_ENTRY; + +extern AML_OFFSET_TABLE_ENTRY *mAmlOffsetTablePointer; +extern AML_OFFSET_TABLE_ENTRY DSDT_PLATWFP__OffsetTable[]; + +#define AML_NAME_OP 0x08 +#define AML_NAME_PREFIX_SIZE 0x06 +#define AML_NAME_DWORD_SIZE 0x0C + +#define MEM_ADDR_SHFT_VAL 26 // For 64 MB granularity + +#pragma pack(1) + +typedef struct { + UINT8 DescriptorType; + UINT16 ResourceLength; + UINT8 ResourceType; + UINT8 Flags; + UINT8 SpecificFlags; + UINT64 Granularity; + UINT64 Minimum; + UINT64 Maximum; + UINT64 TranslationOffset; + UINT64 AddressLength; +} AML_RESOURCE_ADDRESS64; + + +typedef struct { + UINT8 DescriptorType; + UINT16 ResourceLength; + UINT8 ResourceType; + UINT8 Flags; + UINT8 SpecificFlags; + UINT32 Granularity; + UINT32 Minimum; + UINT32 Maximum; + UINT32 TranslationOffset; + UINT32 AddressLength; +} AML_RESOURCE_ADDRESS32; + + +typedef struct { + UINT8 DescriptorType; + UINT16 ResourceLength; + UINT8 ResourceType; + UINT8 Flags; + UINT8 SpecificFlags; + UINT16 Granularity; + UINT16 Minimum; + UINT16 Maximum; + UINT16 TranslationOffset; + UINT16 AddressLength; +} AML_RESOURCE_ADDRESS16; + +#pragma pack() + +#define PCIE_PORT_4_DEV 0x00 +#define PCIE_PORT_5_DEV 0x00 + +#define PORTS_PER_SOCKET 0x0F +#define PCIE_PORT_ALL_FUNC 0x00 + +typedef struct _PCIE_PORT_INFO { + UINT8 Device; + UINT8 Stack; +} PCIE_PORT_INFO; + +#pragma optimize("",off) + +extern BIOS_ACPI_PARAM *mAcpiParameter; + +extern struct SystemMemoryMapHob *mSystemMemoryMap; +extern EFI_IIO_UDS_PROTOCOL *mIioUds; + + +extern SOCKET_MP_LINK_CONFIGURATION mSocketMpLinkConfiguration; +extern SOCKET_IIO_CONFIGURATION mSocketIioConfiguration; +extern SOCKET_POWERMANAGEMENT_CONFIGURATION mSocketPowermanagementConfigur= ation; + +extern UINT32 mNumOfBitShift; + +AML_OFFSET_TABLE_ENTRY *mAmlOffsetTablePointer =3D DSDT_PLATWFP= __OffsetTable; + +/** + + Update the DSDT table + + @param *TableHeader - The table to be set + + @retval EFI_SUCCESS - DSDT updated + @retval EFI_INVALID_PARAMETER - DSDT not updated + +**/ +EFI_STATUS +PatchDsdtTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table + ) +{ + PCIE_PORT_INFO PCIEPortDefaults[] =3D { + // DMI/PCIE 0 + { PCIE_PORT_0_DEV, IIO_CSTACK }, + //IOU0 + { PCIE_PORT_1A_DEV, IIO_PSTACK0 }, + { PCIE_PORT_1B_DEV, IIO_PSTACK0 }, + { PCIE_PORT_1C_DEV, IIO_PSTACK0 }, + { PCIE_PORT_1D_DEV, IIO_PSTACK0 }, + //IOU1 + { PCIE_PORT_2A_DEV, IIO_PSTACK1 }, + { PCIE_PORT_2B_DEV, IIO_PSTACK1 }, + { PCIE_PORT_2C_DEV, IIO_PSTACK1 }, + { PCIE_PORT_2D_DEV, IIO_PSTACK1 }, + //IOU2 + { PCIE_PORT_3A_DEV, IIO_PSTACK2 }, + { PCIE_PORT_3B_DEV, IIO_PSTACK2 }, + { PCIE_PORT_3C_DEV, IIO_PSTACK2 }, + { PCIE_PORT_3D_DEV, IIO_PSTACK2 }, + //MCP0 and MCP1 + { PCIE_PORT_4_DEV, IIO_PSTACK3 }, + { PCIE_PORT_5_DEV, IIO_PSTACK4 } + }; + EFI_STATUS Status; + UINT8 *DsdtPointer; + UINT32 *Signature; + UINT32 Fixes, NodeIndex; + UINT8 Counter; + UINT16 i; // DSDT_PLATEXRP_OffsetTable LUT entries extends beyond 256! + UINT64 MemoryBaseLimit =3D 0; + UINT64 PciHGPEAddr =3D 0; + UINT64 BusDevFunc =3D 0; + UINT64 PcieHpBus =3D 0; + UINT64 PcieHpDev =3D 0; + UINT64 PcieHpFunc=3D 0; + UINT8 PortCount =3D 0; + UINT8 StackNumBus =3D 0; + UINT8 StackNumIo =3D 0; + UINT8 StackNumMem32 =3D 0; + UINT8 StackNumMem64 =3D 0; + UINT8 StackNumVgaIo0 =3D 1; // Start looking for Stack 1 + UINT8 StackNumVgaIo1 =3D 1; // Start looking for Stack 1 + UINT8 StackNumVgaMmioL =3D 0; + UINT8 Stack =3D 0; + UINT8 CurrSkt =3D 0, CurrStack =3D 0; + UINT64 IioBusIndex =3D 0; + UINT8 BusBase =3D 0, BusLimit =3D 0; + UINT16 IoBase =3D 0, IoLimit =3D 0; + UINT32 MemBase32 =3D 0, MemLimit32 =3D 0; + UINT64 MemBase64 =3D 0, MemLimit64 =3D 0; + AML_RESOURCE_ADDRESS16 *AmlResourceAddress16Pointer; + AML_RESOURCE_ADDRESS32 *AmlResourceAddress32Pointer; + AML_RESOURCE_ADDRESS64 *AmlResourceAddress64Pointer; + EFI_ACPI_DESCRIPTION_HEADER *TableHeader; + + Status =3D EFI_SUCCESS; + TableHeader =3D (EFI_ACPI_DESCRIPTION_HEADER *)Table; + + if (mAmlOffsetTablePointer =3D=3D NULL) return EFI_INVALID_PARAMETER; + + mAcpiParameter->MemoryBoardBitMask =3D 0; + + for(Counter =3D 0; Counter < mSystemMemoryMap->numberEntries; Counter++)= { + NodeIndex =3D mSystemMemoryMap->Element[Counter].NodeId; + if((mAcpiParameter->MemoryBoardBitMask) & (1 << NodeIndex)){ + MemoryBaseLimit =3D mAcpiParameter->MemoryBoardRange[NodeIndex] + LS= hiftU64(mSystemMemoryMap->Element[Counter].ElementSize, MEM_ADDR_SHFT_VAL); + mAcpiParameter->MemoryBoardRange[NodeIndex] =3D MemoryBaseLimit; + } else { + mAcpiParameter->MemoryBoardBitMask |=3D 1 << NodeIndex; + MemoryBaseLimit =3D LShiftU64(mSystemMemoryMap->Element[Counter].Bas= eAddress, 30); + mAcpiParameter->MemoryBoardBase[NodeIndex] =3D MemoryBaseLimit; + MemoryBaseLimit =3D LShiftU64((mSystemMemoryMap->Element[Counter].Ba= seAddress + mSystemMemoryMap->Element[Counter].ElementSize), MEM_ADDR_SHFT_= VAL); + mAcpiParameter->MemoryBoardRange[NodeIndex] =3D MemoryBaseLimit; + } + } + + // + // Mark all spare memory controllers as 1 in MemSpareMask bitmap. + // + mAcpiParameter->MemSpareMask =3D ~mAcpiParameter->MemoryBoardBitMask; + + mAcpiParameter->IioPresentBitMask =3D 0; + mAcpiParameter->SocketBitMask =3D 0; + + for (Counter =3D 0; Counter < MAX_SOCKET; Counter++) { + if (!mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Counter].Valid) conti= nue; + mAcpiParameter->SocketBitMask |=3D 1 << Counter; + mAcpiParameter->IioPresentBitMask |=3D LShiftU64(mIioUds->IioUdsPtr->P= latformData.CpuQpiInfo[Counter].stackPresentBitmap, (Counter * 8)); + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + mAcpiParameter->BusBase[Counter * MAX_IIO_STACK + Stack] =3D mIioUds= ->IioUdsPtr->PlatformData.IIO_resource[Counter].StackRes[Stack].BusBase; + } + } + + PciHGPEAddr =3D mIioUds->IioUdsPtr->PlatformData.PciExpressBas= e + 0x188; + BusDevFunc =3D 0x00; + PcieHpBus =3D 0; + PcieHpDev =3D 0; + PcieHpFunc =3D 0; + + Fixes =3D 0; + // + // Loop through the AML looking for values that we must fix up. + // + for (i =3D 0; mAmlOffsetTablePointer[i].Pathname !=3D 0; i++) { + // + // Point to offset in DSDT for current item in AmlOffsetTable. + // + DsdtPointer =3D (UINT8 *) (TableHeader) + mAmlOffsetTablePointer[i].Of= fset; + + if (mAmlOffsetTablePointer[i].Opcode =3D=3D AML_DWORD_PREFIX) { + // + // If Opcode is 0x0C, then operator is Name() or OperationRegion(). + // (TableHeader + AmlOffsetTable.Offset) is at offset for value to c= hange. + // + // The assert below confirms that AML structure matches the offsets = table. + // If not then patching the AML would just corrupt it and result in = OS failure. + // If you encounter this assert something went wrong in *.offset.h f= iles + // generation. Remove the files and rebuild. + // + ASSERT(DsdtPointer[-1] =3D=3D mAmlOffsetTablePointer[i].Opcode); + // + // AmlOffsetTable.Value has FIX tag, so check that to decide what to= modify. + // + Signature =3D (UINT32 *) (&mAmlOffsetTablePointer[i].Value); + switch (*Signature) { + // + // PSYS - "FIX0" OperationRegion() in Acpi\AcpiTables\Dsdt\CommonP= latform.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '0')): + DEBUG ((DEBUG_INFO, "FIX0 - 0x%x\n", mAcpiParameter)); + * (UINT32 *) DsdtPointer =3D (UINT32) (UINTN) mAcpiParameter; + // + // "FIX8" OperationRegion() in Acpi\AcpiTables\Dsdt\PcieHp.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '8')): + Stack =3D PCIEPortDefaults[PortCount % PORTS_PER_SOCKET].Stack; + PcieHpBus =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioB= usIndex].StackRes[Stack].BusBase; + PcieHpDev =3D PCIEPortDefaults[PortCount % PORTS_PER_SOCKET].Dev= ice; + PcieHpFunc =3D PCIE_PORT_ALL_FUNC; + + //DEBUG((DEBUG_ERROR,"IioBus =3D %x, hpDev =3D %x, HpFunc=3D %x\= n",IioBusIndex, PcieHpDev,PcieHpFunc)); + PciHGPEAddr &=3D ~(0xFFFF000); // clear bus device func numbe= rs + BusDevFunc =3D (PcieHpBus << 8) | (PcieHpDev << 3) | PcieHpFunc; + * (UINT32 *) DsdtPointer =3D (UINT32) (UINTN) (PciHGPEAddr + (Bu= sDevFunc << 12)); + //DEBUG((DEBUG_ERROR,", BusDevFunc=3D %x, PortCount =3D %x\n",Bu= sDevFunc, PortCount)); + + PortCount++; + Fixes++; + break; + + default: + break; + } + } else if (mAmlOffsetTablePointer[i].Opcode =3D=3D AML_INDEX_OP) { + // + // If Opcode is 0x88, then operator is WORDBusNumber() or WORDIO(). + // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURC= E_ADDRESS16 to change values. + // + AmlResourceAddress16Pointer =3D (AML_RESOURCE_ADDRESS16 *) (DsdtPoin= ter); + // + // The assert below confirms that AML structure matches the offsets = table. + // If not then patching the AML would just corrupt it and result in = OS failure. + // If you encounter this assert something went wrong in *.offset.h f= iles + // generation. Remove the files and rebuild. + // + ASSERT(AmlResourceAddress16Pointer->DescriptorType =3D=3D mAmlOffset= TablePointer[i].Opcode); + + // + // Last 4 chars of AmlOffsetTable.Pathname has FIX tag. + // + Signature =3D (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + Ascii= StrLen(mAmlOffsetTablePointer[i].Pathname) - 4); + switch (*Signature) { + // + // "FIX1" BUS resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi= and PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '1')): + CurrSkt =3D StackNumBus / MAX_IIO_STACK; + CurrStack =3D StackNumBus % MAX_IIO_STACK; + BusBase =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSk= t].StackRes[CurrStack].BusBase; + BusLimit =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrS= kt].StackRes[CurrStack].BusLimit; + AmlResourceAddress16Pointer->Granularity =3D 0; + if (BusLimit > BusBase) { + AmlResourceAddress16Pointer->Minimum =3D (UINT16) BusBase; + AmlResourceAddress16Pointer->Maximum =3D (UINT16) BusLimit; + AmlResourceAddress16Pointer->AddressLength =3D (UINT16) (BusLi= mit - BusBase + 1); + } + //DEBUG((DEBUG_ERROR,", FIX1 BusBase =3D 0x%x, BusLimit =3D 0x%x= \n",BusBase, BusLimit)); + StackNumBus++; + Fixes++; + break; + + // + // "FIX2" IO resource for for PCXX in Acpi\AcpiTables\Dsdt\SysBus.= asi and PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '2')): + AmlResourceAddress16Pointer->Granularity =3D 0; + CurrSkt =3D StackNumIo / MAX_IIO_STACK; + CurrStack =3D StackNumIo % MAX_IIO_STACK; + IoBase =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt= ].StackRes[CurrStack].PciResourceIoBase; + IoLimit =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSk= t].StackRes[CurrStack].PciResourceIoLimit; + if (IoLimit > IoBase) { + AmlResourceAddress16Pointer->Minimum =3D (UINT16) IoBase; + AmlResourceAddress16Pointer->Maximum =3D (UINT16) IoLimit; + AmlResourceAddress16Pointer->AddressLength =3D (UINT16) (IoLim= it - IoBase + 1); + } + //DEBUG((DEBUG_ERROR,", FIX2 IoBase =3D 0x%x, IoLimit =3D 0x%x\n= ",IoBase, IoLimit)); + StackNumIo++; + Fixes++; + break; + + // + // "FIX6" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '6')): + AmlResourceAddress16Pointer->Granularity =3D 0; + CurrSkt =3D StackNumVgaIo0 / MAX_IIO_STACK; + CurrStack =3D StackNumVgaIo0 % MAX_IIO_STACK; + if ((mSocketMpLinkConfiguration.LegacyVgaSoc =3D=3D CurrSkt) && + (mSocketMpLinkConfiguration.LegacyVgaStack =3D=3D CurrStack)= ){ + AmlResourceAddress16Pointer->Minimum =3D (UINT16) 0x03b0; + AmlResourceAddress16Pointer->Maximum =3D (UINT16) 0x03bb; + AmlResourceAddress16Pointer->AddressLength =3D (UINT16) 0x00= 0C; + } + StackNumVgaIo0++; + Fixes++; + break; + + // + // "FIX7" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '7')): + AmlResourceAddress16Pointer->Granularity =3D 0; + CurrSkt =3D StackNumVgaIo1 / MAX_IIO_STACK; + CurrStack =3D StackNumVgaIo1 % MAX_IIO_STACK; + if ((mSocketMpLinkConfiguration.LegacyVgaSoc =3D=3D CurrSkt) && + (mSocketMpLinkConfiguration.LegacyVgaStack =3D=3D CurrStack)= ) { + AmlResourceAddress16Pointer->Minimum =3D (UINT16) 0x03c0; + AmlResourceAddress16Pointer->Maximum =3D (UINT16) 0x03df; + AmlResourceAddress16Pointer->AddressLength =3D (UINT16) 0x00= 20; + } + StackNumVgaIo1++; + Fixes++; + break; + + default: + break; + } + } else if (mAmlOffsetTablePointer[i].Opcode =3D=3D AML_SIZE_OF_OP) { + // + // If Opcode is 0x87, then operator is DWORDMemory(). + // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURC= E_ADDRESS32 to change values. + // + AmlResourceAddress32Pointer =3D (AML_RESOURCE_ADDRESS32 *) (DsdtPoin= ter); + // + // The assert below confirms that AML structure matches the offsets = table. + // If not then patching the AML would just corrupt it and result in = OS failure. + // If you encounter this assert something went wrong in *.offset.h f= iles + // generation. Remove the files and rebuild. + // + ASSERT(AmlResourceAddress32Pointer->DescriptorType =3D=3D mAmlOffset= TablePointer[i].Opcode); + // + // Last 4 chars of AmlOffsetTable.Pathname has FIX tag. + // + Signature =3D (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + Ascii= StrLen(mAmlOffsetTablePointer[i].Pathname) - 4); + switch (*Signature) { + // + // "FIX3" PCI32 resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.a= si and PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '3')): + AmlResourceAddress32Pointer->Granularity =3D 0; + CurrSkt =3D StackNumMem32 / MAX_IIO_STACK; + CurrStack =3D StackNumMem32 % MAX_IIO_STACK; + MemBase32 =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[Curr= Skt].StackRes[CurrStack].PciResourceMem32Base; + MemLimit32 =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[Cur= rSkt].StackRes[CurrStack].PciResourceMem32Limit; + if (MemLimit32 > MemBase32) { + AmlResourceAddress32Pointer->Minimum =3D (UINT32) MemBase32; + AmlResourceAddress32Pointer->Maximum =3D (UINT32) MemLimit32; + AmlResourceAddress32Pointer->AddressLength =3D (UINT32) (MemLi= mit32 - MemBase32 + 1); + } + //DEBUG((DEBUG_ERROR,", FIX3 MemBase32 =3D 0x%08x, MemLimit32 = =3D 0x%08x\n",MemBase32, MemLimit32)); + StackNumMem32++; + Fixes++; + break; + + // + // "FIX5" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '5')): + AmlResourceAddress32Pointer->Granularity =3D 0; + CurrSkt =3D StackNumVgaMmioL / MAX_IIO_STACK; + CurrStack =3D StackNumVgaMmioL % MAX_IIO_STACK; + if ((mSocketMpLinkConfiguration.LegacyVgaSoc =3D=3D CurrSkt) && + (mSocketMpLinkConfiguration.LegacyVgaStack =3D=3D CurrStack)= ) { + AmlResourceAddress32Pointer->Minimum =3D 0x000a0000; + AmlResourceAddress32Pointer->Maximum =3D 0x000bffff; + AmlResourceAddress32Pointer->AddressLength =3D 0x00020000; + } + StackNumVgaMmioL++; + Fixes++; + break; + + default: + break; + } + } else if (mAmlOffsetTablePointer[i].Opcode =3D=3D AML_CREATE_DWORD_FI= ELD_OP) { + // + // If Opcode is 0x8A, then operator is QWORDMemory(). + // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURC= E_ADDRESS64 to change values. + // + AmlResourceAddress64Pointer =3D (AML_RESOURCE_ADDRESS64 *) (DsdtPoin= ter); + // + // The assert below confirms that AML structure matches the offsets = table. + // If not then patching the AML would just corrupt it and result in = OS failure. + // If you encounter this assert something went wrong in *.offset.h f= iles + // generation. Remove the files and rebuild. + // + ASSERT(AmlResourceAddress64Pointer->DescriptorType =3D=3D mAmlOffset= TablePointer[i].Opcode); + // + // Last 4 chars of AmlOffsetTable.Pathname has FIX tag. + // + Signature =3D (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + Ascii= StrLen(mAmlOffsetTablePointer[i].Pathname) - 4); + switch (*Signature) { + // + // "FIX4" PCI64 resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.a= si and PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '4')): + DEBUG((DEBUG_ERROR,"Pci64BitResourceAllocation =3D 0x%x\n",mSock= etIioConfiguration.Pci64BitResourceAllocation)); + if (mSocketIioConfiguration.Pci64BitResourceAllocation) { + AmlResourceAddress64Pointer->Granularity =3D 0; + CurrSkt =3D StackNumMem64 / MAX_IIO_STACK; + CurrStack =3D StackNumMem64 % MAX_IIO_STACK; + MemBase64 =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[Cu= rrSkt].StackRes[CurrStack].PciResourceMem64Base; + MemLimit64 =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[C= urrSkt].StackRes[CurrStack].PciResourceMem64Limit; + if (MemLimit64 > MemBase64) { + AmlResourceAddress64Pointer->Minimum =3D (UINT64) MemBase64; + AmlResourceAddress64Pointer->Maximum =3D (UINT64) MemLimit64; + AmlResourceAddress64Pointer->AddressLength =3D (UINT64) (Mem= Limit64 - MemBase64 + 1); + } + DEBUG((DEBUG_ERROR,", FIX4 MemBase64 =3D 0x%x, MemLimit64 =3D = 0x%x\n",MemBase64, MemLimit64)); + StackNumMem64++; + Fixes++; + } + break; + default: + break; + } + } + } + + //return Status; + return EFI_SUCCESS; + +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf b= /Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf new file mode 100644 index 0000000000..fd1595017f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf @@ -0,0 +1,29 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D Dsdt + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Dsdt/WFPPlatform.asl + +[Packages] + MdePkg/MdePkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[BuildOptions] + # add -vr and -so to generate offset.h + *_*_*_ASL_FLAGS =3D -oi -vr -so + + --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Tue, 11 May 2021 02:49:04 -0700 IronPort-SDR: g4zhSOfnqN7PjsHyp+uv+xLHum3BT12X1Wcxtkqov+8ETo+3jmfhU3UJAI5Fz118y7yNy3ejm4 HO/Zv4zvuc/Q== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="178994727" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="178994727" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:56 -0700 IronPort-SDR: CPxwLY03JsTOLaxTH6GO3SyYq0NLPKER9SJJ1L+31sKEVEv/1U9kQ+fzehsQsrU/1L/RXk1B1C WUC8aR8PKsjw== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436574027" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:54 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 14/18] PurleyOpenBoardPkg: Add MtOlympus build files Date: Tue, 11 May 2021 02:48:22 -0700 Message-Id: <20210511094826.12495-15-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: wUHgvBFK82mYaoY6Z3g8posnx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726550; bh=X1GeMnQVlWIODSLRBVF5LmY276YuwmNg9gLWNhn16KY=; h=Cc:Date:From:Reply-To:Subject:To; b=L6J8hu7tlXfxSOBfqYqGCd7L4y5cd3xicVc/w6V94tmKMEd7Xc03NVVFFxImEgaVmup YzU8oIRFH3R6gnnsveBzFQ8kaUc1KpDsm30SriyLaRMfwvTEBauZkvqeIFhSxmgPHoB1e iAxX+Npj55gmyr1fIpgxd46j3gWW2XMRoGU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../BoardMtOlympus/GitEdk2MinMtOlympus.bat | 74 +++ .../BoardMtOlympus/OpenBoardPkg.dsc | 221 +++++++ .../BoardMtOlympus/OpenBoardPkg.fdf | 589 ++++++++++++++++++ .../BoardMtOlympus/PlatformPkgBuildOption.dsc | 81 +++ .../BoardMtOlympus/PlatformPkgConfig.dsc | 58 ++ .../BoardMtOlympus/PlatformPkgPcd.dsc | 389 ++++++++++++ .../PurleyOpenBoardPkg/BoardMtOlympus/bld.bat | 138 ++++ .../BoardMtOlympus/build_board.py | 177 ++++++ .../BoardMtOlympus/build_config.cfg | 32 + .../BoardMtOlympus/logo.txt | 11 + .../BoardMtOlympus/postbuild.bat | 95 +++ .../BoardMtOlympus/prebuild.bat | 197 ++++++ Platform/Intel/build.cfg | 1 + 13 files changed, 2063 insertions(+) create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk= 2MinMtOlympus.bat create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBo= ardPkg.dsc create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBo= ardPkg.fdf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Platfo= rmPkgBuildOption.dsc create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Platfo= rmPkgConfig.dsc create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Platfo= rmPkgPcd.dsc create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_= board.py create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_= config.cfg create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.t= xt create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbu= ild.bat create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebui= ld.bat diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtO= lympus.bat b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtO= lympus.bat new file mode 100644 index 0000000000..85ce5beaf8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.= bat @@ -0,0 +1,74 @@ +@REM @file +@REM +@REM Copyright (c) 2018, Intel Corporation. All rights reserved.
+@REM SPDX-License-Identifier: BSD-2-Clause-Patent +@REM + +@echo off + +pushd ..\..\..\..\..\ + +@REM Set WORKSPACE environment. +set WORKSPACE=3D%cd% +echo. +echo Set WORKSPACE as: %WORKSPACE% +echo. + +@REM Check whether Git has been installed and been added to system path. +git --help >nul 2>nul +if %ERRORLEVEL% NEQ 0 ( + echo. + echo The 'git' command is not recognized. + echo Please make sure that Git is installed and has been added to system= path. + echo. + goto :EOF +) + +@REM Create the Conf directory under WORKSPACE +if not exist %WORKSPACE%\Conf ( + mkdir Conf +) + +@REM Set other environments. +@REM Basic Rule: +@REM Platform override Silicon override Core +@REM Source override Binary + +set PACKAGES_PATH=3D%WORKSPACE%\edk2-platforms\Platform\Intel;%WORKSPACE%\= edk2-platforms\Silicon\Intel;%WORKSPACE%\edk2-platforms\Features\Intel;%WOR= KSPACE%\edk2-platforms\Features\Intel\Debugging;%WORKSPACE%\edk2-platforms\= Features\Intel\Network;%WORKSPACE%\edk2-platforms\Features\Intel\OutOfBandM= anagement;%WORKSPACE%\edk2-platforms\Features\Intel\PowerManagement;%WORKSP= ACE%\edk2-platforms\Features\Intel\SystemInformation;%WORKSPACE%\edk2-platf= orms\Features\Intel\UserInterface;%WORKSPACE%\edk2-non-osi\Silicon\Intel;%W= ORKSPACE%\edk2;%WORKSPACE% + +set EDK_TOOLS_BIN=3D%WORKSPACE%\edk2-BaseTools-win32 + +@if not defined PYTHON_HOME ( + @if exist C:\Python27 ( + set PYTHON_HOME=3DC:\Python27 + ) +) + +set EDK_SETUP_OPTION=3D +@rem if python is installed, disable the binary base tools. +if defined PYTHON_HOME ( + set EDK_TOOLS_BIN=3D + set EDK_SETUP_OPTION=3DRebuild +) +pushd %WORKSPACE%\edk2 +call edksetup.bat %EDK_SETUP_OPTION% +popd + +set openssl_path=3D%WORKSPACE% + +popd + +goto :EOF + +:Help +echo. +echo Usage: +echo GitEdk2.bat [-w Workspace_Directory] (optional) [-b Branch_Name] (opt= ional) +echo. +echo -w A absolute/relative path to be the workspace. +echo Default value is the current directory. +echo. +echo -b The branch name of the repository. Currently, only master, udk2= 015, +echo trunk (same as master) and bp13 (same as udk2015) are supported. +echo Default value is master. +echo. diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.= dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc new file mode 100644 index 0000000000..98e02f35e7 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc @@ -0,0 +1,221 @@ +## @file +# The main build description file for the MtOlympus board. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg + DEFINE PLATFORM_SI_PACKAGE =3D PurleyRefreshSiliconPkg + DEFINE PLATFORM_SI_BIN_PACKAGE =3D PurleySiliconBinPkg + DEFINE PLATFORM_BOARD_PACKAGE =3D PurleyOpenBoardPkg + DEFINE BOARD =3D BoardMtOlympus + DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE)/$(BOARD) + DEFINE PEI_ARCH =3D IA32 + DEFINE DXE_ARCH =3D X64 + + PLATFORM_NAME =3D PurleyOpenBoardPkg + PLATFORM_GUID =3D D7EAF54D-C9B9-4075-89F0-71943DBC= FA61 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 + OUTPUT_DIRECTORY =3D Build/$(PROJECT) + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPkg.fdf + + FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0 + + # + # Platform On/Off features are defined here + # + !include $(PROJECT)/PlatformPkgConfig.dsc + + # + # Include PCD configuration for this board. + # + !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc + + !include PlatformPkgPcd.dsc + !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc + + +##########################################################################= ###### +# +# SKU Identification section - list of all SKU IDs supported by this +# Platform. +# +##########################################################################= ###### +[SkuIds] + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always req= uired. + +[DefaultStores] + 0|STANDARD # UEFI Standard default 0|STANDARD is reserved. + 1|MANUFACTURING # UEFI Manufacturing default 1|MANUFACTURING is r= eserved. + +##########################################################################= ###### +# +# Includes section - other DSC file contents included for this board build. +# +##########################################################################= ###### + +####################################### +# Library Includes +####################################### +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + +####################################### +# Component Includes +####################################### + +[Components.$(PEI_ARCH)] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc + +[Components.$(DXE_ARCH)] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc + +####################################### +# Build Option Includes +####################################### +!include $(PROJECT)/PlatformPkgBuildOption.dsc + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### + +[LibraryClasses.common] +!if gPlatformTokenSpaceGuid.PcdFastBoot =3D=3D FALSE + PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa= nagerLib/DxePlatformBootManagerLib.inf +!else + PlatformBootManagerLib|$(PLATFORM_BOARD_PACKAGE)/Override/Platform/Intel= /MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManage= rLib.inf +!endif + + ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR= eportFvLib.inf + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf + + CompressLib|$(PLATFORM_PACKAGE)/Library/CompressLib/CompressLib.inf + + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf + AslUpdateLib|$(PLATFORM_PACKAGE)/Acpi/Library/DxeAslUpdateLib/DxeAslUpda= teLib.inf + + # + # Board + # + SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/SiliconPol= icyInitLib/SiliconPolicyInitLib.inf + SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/SiliconP= olicyUpdateLib/SiliconPolicyUpdateLib.inf + PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf + +[LibraryClasses.IA32] +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf +!endif + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf + SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrr= LibNull.inf + ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHobLib= /ReportCpuHobLib.inf + +[LibraryClasses.X64] + BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.i= nf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dxe= TestPointCheckLib.inf +!endif + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf + BoardBootManagerLib|BoardModulePkg/Library/BoardBootManagerLib/BoardBoot= ManagerLib.inf + +[LibraryClasses.X64.DXE_SMM_DRIVER] +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm= TestPointCheckLib.inf +!endif + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf + +[Components.IA32] + + $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempMemory= Silicon.inf + $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemorySi= licon.inf + $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMemory= Silicon.inf + + $(PLATFORM_BOARD_PACKAGE)/Policy/SystemBoard/SystemBoardPei.inf + + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.i= nf + } + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { + + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.= inf + } + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf + +[Components.X64] + + $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(TARGET)/FvLateSilicon.inf + $(PLATFORM_SI_BIN_PACKAGE)/Microcode/Microcode.inf + + $(PLATFORM_BOARD_PACKAGE)/Policy/IioUdsDataDxe/IioUdsDataDxe.inf + $(PLATFORM_BOARD_PACKAGE)/Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf + $(PLATFORM_BOARD_PACKAGE)/Pci/PciPlatform/PciPlatform.inf + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { + + MSFT:*_*_*_ASLCC_FLAGS =3D /D PURLEY_FLAG /D PCH_SPT + GCC:*_*_*_ASLCC_FLAGS =3D -D PURLEY_FLAG -D PCH_SPT + } + +# This is for prebuild only. No need to include in final FDF. + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/Dsdt.inf { + + MSFT:*_*_*_ASLCC_FLAGS =3D /D PURLEY_FLAG /D PCH_SPT + GCC:*_*_*_ASLCC_FLAGS =3D -D PURLEY_FLAG -D PCH_SPT + } + + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { + + BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnabl= eLib.inf + } + + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + + $(PLATFORM_BOARD_PACKAGE)/Policy/S3NvramSave/S3NvramSave.inf + + # + # Shell + # + ShellPkg/Application/Shell/Shell.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com= mandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1C= ommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C= ommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C= ommandsLib.inf + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommand= Lib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePars= ingLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg= CommandLib.inf + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib= .inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + } + + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.= fdf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf new file mode 100644 index 0000000000..7a3ffff7ff --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf @@ -0,0 +1,589 @@ +## @file +# FDF file for the MtOlympus board. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + +# Note: FlashNv PCD naming conventions are as follows: +# Note: This should be 100% true of all PCD's in the gCpPlatFlashTo= kenSpaceGuid space, and for +# Others should be examined with an effort to work toward thi= s guideline. +# PcdFlash*Base is an address, usually in the range of 0xf* of FD's,= note change in FDF spec +# PcdFlash*Size is a hex count of the length of the FD or FV +# All Fv will have the form 'PcdFlashFv', and all Fd will have the f= orm 'PcdFlashFd' +# +# Also all values will have a PCD assigned so that they can be used = in the system, and +# the FlashMap edit tool can be used to change the values here, with= out effecting the code. +# This requires all code to only use the PCD tokens to recover the v= alues. + +[FD.Platform] +BaseAddress =3D 0xFF000000 | gEfiPchTokenSpaceGuid.PcdFlashAreaBaseA= ddress +Size =3D 0x01000000 | gEfiPchTokenSpaceGuid.PcdFlashAreaSize +ErasePolarity =3D 1 +BlockSize =3D 0x10000 +NumBlocks =3D 0x100 + +0x00000000|0x00500000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvAdvancedSize +FV =3D FvAdvanced + +0x00500000|0x00100000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvSecuritySize +FV =3D FvSecurity + +0x00600000|0x00100000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvOsBootSize +FV =3D FvOsBoot + +0x00700000|0x00200000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspUSize +FV =3D FvLateSiliconCompressed + +0x00900000|0x00400000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvUefiBootSize +FV =3D FvUefiBoot + +0x00D00000|0x0007C000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0= x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x100000 + 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x1A, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 16 Blocks * 0x10000 Bytes / Block + 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, 0= x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } } + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + !else + # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x98= , 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + !endif + #Size: 0x7c000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable= Size) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x7BFFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xBF, 0x07, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x00D7C000|0x00002000 +#NV_EVENT_LOG + +0x00D7E000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x00D80000|0x00080000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE + + +0x00E00000|0x00010000 +gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|gCpuUncoreTokenSpa= ceGuid.PcdFlashNvStorageMicrocodeSize +FV =3D MICROCODE_FV + +0x00E10000|0x00010000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvPostMemorySize +FV =3D FvPostMemory + +0x00E20000|0x00030000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspSSize +FILE =3D $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPos= tMemorySilicon.Fv + +0x00E50000|0x00060000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgToken= SpaceGuid.PcdFlashFvPreMemorySize +FV =3D FvPreMemory + +0x00EB0000|0x00130000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspMSize +FILE =3D $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreM= emorySilicon.Fv + +0x00FE0000|0x00020000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspTSize +FILE =3D $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTem= pMemorySilicon.Fv + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gEfiPchTo= kenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvS= torageMicrocodeBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gCpuUncor= eTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize + +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D gEfiPchTo= kenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvS= torageMicrocodeBase + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D gCpuUncor= eTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60 + +SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D gEfiPchTo= kenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvS= torageMicrocodeBase + 0x60 +SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D gCpuUncor= eTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60 + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvLateSiliconCompressed] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D BA793112-EA2E-47C4-9AFE-A8FCFE603D6D + +FILE FV_IMAGE =3D A626BB34-2455-4FCA-8DFB-FEE96DB0DC5F { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { + SECTION FV_IMAGE =3D $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon= /$(TARGET)/FvLateSilicon.Fv + } + } + +[FV.MICROCODE_FV] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D FALSE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/Microc= ode.inf + +[FV.FvPreMemory] +FvAlignment =3D 16 +FvForceRebase =3D TRUE +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 6522280D-28F9-4131-ADC4-F40EBFA45864 + + ## + # PEI Apriori file example, more PEIM module added later. + ## +INF MdeModulePkg/Core/Pei/PeiMain.inf + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf + +INF $(PLATFORM_BOARD_PACKAGE)/Policy/SystemBoard/SystemBoardPei.inf + +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.i= nf +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPre= Mem.inf + +[FV.FvPostMemory] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D C54E3E8D-9FF5-4D52-AF03-58018EB55F63 + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf + +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.= inf +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPos= tMem.inf + +[FV.FvUefiBootUncompact] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 + + ## + # DXE Phase modules + ## + + ## + # DXE Apriori file example, more DXE module added later. + ## + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf + +INF PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf + +INF $(PLATFORM_BOARD_PACKAGE)/Policy/IioUdsDataDxe/IioUdsDataDxe.inf +INF $(PLATFORM_BOARD_PACKAGE)/Policy/PlatformCpuPolicy/PlatformCpuPolicy.= inf +INF $(PLATFORM_BOARD_PACKAGE)/Pci/PciPlatform/PciPlatform.inf + +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + +INF ShellPkg/Application/Shell/Shell.inf + +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + +[FV.FvUefiBoot] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 27A72E80-3118-4c0c-8673-AA5B4EFA9613 + +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { + SECTION FV_IMAGE =3D FvUefiBootUncompact + } + } + +[FV.FvOsBootUncompact] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 5AB52883-85DF-445B-99F7-E0C1D517A905 + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf + +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf + +INF RuleOverride =3D DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/Boar= dAcpiDxe/BoardAcpiDxe.inf + +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + +[FV.FvOsBoot] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 5e2363c4-3e9e-4203-b873-bb40df46c8e6 + +FILE FV_IMAGE =3D AC09A11F-BD9F-4C87-B656-F4868EEA89B8 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { + SECTION FV_IMAGE =3D FvOsBootUncompact + } + } + +[FV.FvSecurityPreMem] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D A91F91A0-0CCD-4E1C-9FD8-4DAE39F348FA + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf + +[FV.FvSecurityPostMem] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 04B00029-2391-44C1-97BA-3FA8A42E9D3A + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf +!endif + +[FV.FvSecurityLate] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D CCBC50ED-0902-413E-BC2C-409C906F4A80 + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +!endif + +[FV.FvSecurity] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 8CBBA80C-FE21-4749-B015-6EDFC34B6BE7 + +FILE FV_IMAGE =3D A63B2BBF-7A02-4862-BF22-A1BA5258DD68 { + SECTION FV_IMAGE =3D FvSecurityPreMem + } + +FILE FV_IMAGE =3D 47B40638-0087-4938-97CF-B56983A1A07B { + SECTION FV_IMAGE =3D FvSecurityPostMem + } + +FILE FV_IMAGE =3D 605CBDF4-61DB-4B77-BAED-65232B8EC6D6 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { + SECTION FV_IMAGE =3D FvSecurityLate + } + } + +[FV.FvAdvancedPreMem] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D EBC45843-B180-44D3-A485-0031A75DB16D + +!include AdvancedFeaturePkg/Include/PreMemory.fdf + +[FV.FvAdvancedUncompact] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 05411CAD-6C35-4675-B6CA-8748032144B4 + +!include AdvancedFeaturePkg/Include/PostMemory.fdf + +[FV.FvAdvanced] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 59584CB6-0740-4EE6-A335-A46B370A101A + +FILE FV_IMAGE =3D 0112F63C-E0EA-4CA7-BFAA-9574DB03B230 { + SECTION FV_IMAGE =3D FvAdvancedPreMem + } + +FILE FV_IMAGE =3D 07FC4960-5322-4DDC-A6A4-A17DE492DFE3 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { + SECTION FV_IMAGE =3D FvAdvancedUncompact + } + } + +[FV.FvDummy] +FvAlignment =3D 16 +FvForceRebase =3D FALSE +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +# Add dummy FV here to build the PCD in FV into PCD database. +INF RuleOverride =3D BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySili= con/$(TARGET)/FvTempMemorySilicon.inf +INF RuleOverride =3D BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilic= on/$(TARGET)/FvPreMemorySilicon.inf +INF RuleOverride =3D BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySili= con/$(TARGET)/FvPostMemorySilicon.inf +INF RuleOverride =3D BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(= TARGET)/FvLateSilicon.inf + + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgBu= ildOption.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPk= gBuildOption.dsc new file mode 100644 index 0000000000..eb282963e9 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgBuildOpti= on.dsc @@ -0,0 +1,81 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[BuildOptions.Common.EDKII] +# Append build options for EDK and EDKII drivers (=3D is Append, =3D=3D is= Replace) + + DEFINE CRB_EDKII_BUILD_OPTIONS =3D -D CRB_FLAG + DEFINE EDKII_CPU_BUILD_OPTIONS =3D -D PURLEY_FLAG + DEFINE TRAD_BUILD_OPTION =3D -D TRAD_FLAG=3D1 + DEFINE SUS_WELL_RESTORE_BUILD_OPTION =3D -D SUS_WELL_RESTORE=3D1 + DEFINE PCH_BUILD_OPTION =3D -D PCH_SERVER_BIOS_FLAG=3D1 + DEFINE SERVER_BUILD_OPTION =3D -D SERVER_BIOS_FLAG=3D1 + DEFINE PCH_PKG_OPTIONS =3D -D PCH_SPT + DEFINE MAX_SOCKET_OPTIONS =3D -D MAX_SOCKET=3D2 + + DEFINE EDKII_ALL_PPO_OPTIONS =3D $(EDKII_CPU_BUILD_OPTIONS) + DEFINE PCH_BIOS_BUILD_OPTIONS =3D $(TRAD_BUILD_OPTION) $(ULT_BU= ILD_OPTION) $(PCH_BUILD_OPTION) $(SUS_WELL_RESTORE_BUILD_OPTION) $(SERVER_B= UILD_OPTION) + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(CRB_EDKII_BUILD_OPTIONS) $(= PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(EDKII_ALL_PPO_OPTIONS) $(SPARI= NG_SCRATCHPAD_OPTION) $(TRACE_HUB_DEBUG_BUILD_OPTIONS) $(TRACE_HUB_INIT_BUI= LD_OPTIONS) $(MAX_SOCKET_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT -D= SKX_HOST -D CLX_HOST + +!if $(TARGET) =3D=3D "DEBUG" + DEFINE DEBUG_BUILD_FLAG =3D -D SERIAL_DBG_MSG=3D1 +!else + DEFINE DEBUG_BUILD_FLAG =3D -D MDEPKG_NDEBUG -D SILENT_MODE +!endif + + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(EDKII_DSC_FEATURE_BUILD= _OPTIONS) $(DEBUG_BUILD_FLAG) +# +# PC_BUILD_END +# + + + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(EDKII_DSC_FEATURE_BUILD= _OPTIONS) + + + *_*_*_CC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_VFRPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_APP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_PP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_ASLPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_ASLCC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + + +# +# Enable source level debugging for RELEASE build +# +!if $(TARGET) =3D=3D "RELEASE" + DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =3D /Zi + DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =3D /Zi /Gm + DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =3D /DEBUG + + MSFT:*_*_*_ASM_FLAGS =3D $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) + MSFT:*_*_*_CC_FLAGS =3D $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) + MSFT:*_*_*_DLINK_FLAGS =3D $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) +!endif + + +# +# Override the existing iasl path in tools_def.template +# +# MSFT:*_*_*_ASL_PATH =3D=3D c:/Iasl/iasl.exe + +# +# Override the VFR compile flags to speed the build time +# + +*_*_*_VFR_FLAGS =3D=3D -n + +# Force PE/COFF sections to be aligned at 4KB boundaries to support page l= evel protection +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_C= ORE] + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + +# Force PE/COFF sections to be aligned at 4KB boundaries to support Memory= Attribute table +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgCo= nfig.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgConf= ig.dsc new file mode 100644 index 0000000000..2bd714c01e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgConfig.dsc @@ -0,0 +1,58 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# TRUE is ENABLE. FALSE is DISABLE. +# + +[PcdsFixedAtBuild] + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + +[PcdsFeatureFlag] + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + + !if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + !else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|TRUE + + gPlatformTokenSpaceGuid.PcdFastBoot|FALSE +!if gPlatformTokenSpaceGuid.PcdFastBoot =3D=3D TRUE + gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable|FALSE + gPlatformTokenSpaceGuid.PcdUpdateConsoleInBds|FALSE +!endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPc= d.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc new file mode 100644 index 0000000000..6f6fb20d46 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc @@ -0,0 +1,389 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all PCD Entries defined by this board. +# +##########################################################################= ###### + +[PcdsFixedAtBuild.common] + ###################################### + # Key Boot Stage and FSP configuration + ###################################### + # + # Please select the Boot Stage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # Stage 6 - boot with advanced features enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + +[PcdsFeatureFlag.common] + gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|FALSE + # Server doesn't support capsle update on Reset. + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugSupport|TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + +#S3 add + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE +#S3 add + + gEfiCpuTokenSpaceGuid.PcdCpuConroeFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuCedarMillFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuPrescottFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuNehalemFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuIvyBridgeFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuSandyBridgeFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuHaswellFamilyFlag|TRUE + gEfiCpuTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE + + gEfiCpuTokenSpaceGuid.PcdCpuGateA20MDisableFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuSmmDebug|TRUE + gEfiCpuTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE + gEfiCpuTokenSpaceGuid.PcdCpuSocketIdReassignmentFlag|TRUE + + ## This PCD specified whether ACPI SDT protocol is installed. + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + +!if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE +!else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE +!endif + +[PcdsFeatureFlag.X64] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE + +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE + +[PcdsDynamicExDefault] +!include $(PROJECT)/StructureConfig.dsc + +[PcdsFixedAtBuild.X64] + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0= x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x01, 0x00, 0x00, 0x00, 0x01, 0x01= , 0x06, 0x00, 0x00, 0x01, 0x01, 0x01, 0x06, 0x00, 0x00, 0x01, 0x7F, 0xFF,= 0x04, 0x00} + +[PcdsFixedAtBuild.IA32] + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0x00FFA00000 + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x0000600000 + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE +!if $(TARGET) =3D=3D "RELEASE" + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!endif +!if $(TARGET) =3D=3D RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE +!endif + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 +#S3 modified + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000 + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE +#S3 modified + + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x1700000 + + gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000 + gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gEfiCpuTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gEfiCpuTokenSpaceGuid.PcdPlatformType|2 + gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000 + gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxFsbFrequency|1066 + gEfiCpuTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 + + ## Specifies delay value in microseconds after sending out an INIT IPI. + # @Prompt Configure delay value after send an INIT IPI + gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10 + + ## Specifies max supported number of Logical Processors. + # @Prompt Configure max supported number of Logical Processorss + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 +!endif + + gPlatformTokenSpaceGuid.PcdBusStack|0x06 + gPlatformTokenSpaceGuid.PcdUboDev|0x08 + gPlatformTokenSpaceGuid.PcdUboFunc|0x02 + gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC + + gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|TRUE + + ## Defines the ACPI register set base address. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Timer IO Port Address + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500 + + ## Defines the PCI Bus Number of the PCI device that contains the BAR an= d Enable for ACPI hardware registers. + # @Prompt ACPI Hardware PCI Bus Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x20091013 + + ## Defines the PCI Device Number of the PCI device that contains the BAR= and Enable for ACPI hardware registers. + # The invalid 0xFF is as its default value. It must be configured to th= e real value. + # @Prompt ACPI Hardware PCI Device Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F + + ## Defines the PCI Function Number of the PCI device that contains the B= AR and Enable for ACPI hardware registers. + # The invalid 0xFF is as its default value. It must be configured to th= e real value. + # @Prompt ACPI Hardware PCI Function Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02 + + ## Defines the PCI Register Offset of the PCI device that contains the E= nable for ACPI hardware registers. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Hardware PCI Register Offset + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044 + + ## Defines the bit mask that must be set to enable the APIC hardware reg= ister BAR. + # @Prompt ACPI Hardware PCI Bar Enable BitMask + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80 + + ## Defines the PCI Register Offset of the PCI device that contains the B= AR for ACPI hardware registers. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Hardware PCI Bar Register Offset + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040 + + ## Defines the offset to the 32-bit Timer Value register that resides wi= thin the ACPI BAR. + # @Prompt Offset to 32-bit Timer register in ACPI BAR + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008 + + ## Defines the bit mask to retrieve ACPI IO Port Base Address + # @Prompt ACPI IO Port Base Address Mask + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFC + + # Indicates the max nested level + gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000010 + + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET) + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET) + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28 + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x70 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x80 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x1470 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0xA0 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x80 + + # + # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags + # + # BIT0: If set, expresses that for all synchronous SMM entries,SMM will = validate that input and output buffers lie entirely within the expected fix= ed memory regions. + # BIT1: If set, expresses that for all synchronous SMM entries, SMM will= validate that input and output pointers embedded within the fixed communic= ation buffer only refer to address ranges \ + # that lie entirely within the expected fixed memory regions. + # BIT2: Firmware setting this bit is an indication that it will not allo= w reconfiguration of system resources via non-architectural mechanisms. + # BIT3-31: Reserved + # + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 + +[PcdsFixedAtBuild.X64] + gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015 + gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099 + # Change PcdBootManagerMenuFile to UiApp +## + + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + gEfiCpuTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE + + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04 + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000 + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5 + + gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1 + + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 + gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000 + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08 + + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24 + + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 + +[PcdsPatchableInModule.common] + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 + +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 +!endif + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000 + + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase |0x1000 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0x90000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit |0xFBFFFFFF + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase |0x38000000= 0000 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit |0x3803FFFF= FFFF + + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE + + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x01400000 + +[PcdsDynamicExDefault.common.DEFAULT] + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfiguration|0x002CF6CF + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfigurationEx1|0 + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000 + gEfiCpuTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000 + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE + + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0 + + gEfiPchTokenSpaceGuid.PcdWakeOnRTCS5|FALSE + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeHour|0 + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeMinute|0 + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeSecond|0 + + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0x5 + +[PcdsDynamicExHii.common.DEFAULT] +!if gPlatformTokenSpaceGuid.PcdFastBoot =3D=3D FALSE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|3 # Variable: L"Timeout" +!else + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|0 # Variable: L"Timeout" +!endif + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" + + +[PcdsDynamicExDefault] + + gOemSkuTokenSpaceGuid.PcdForceTo1SConfigMode|FALSE + +## *** PURLEY_PPO *** - Added in 8th segment in PcdPcieMmcfgTablePtr to fi= x size assert in PcieAddressLib.c +## | = MMCFG Table Header | = Segment 0 | = Segment 1 | = Segment 2 | = Segment 3 = | Segment 4 = | Segment 5 = | Segment 6 = | Segment 7 = | Segment 8 + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0} + + gEfiCpuTokenSpaceGuid.PcdCpuEnergyPolicy|0 + gEfiCpuTokenSpaceGuid.PcdCpuAcpiLvl2Addr|0 + gEfiCpuTokenSpaceGuid.PcdCpuPackageCStateLimit|0 + gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue|0 + gEfiCpuTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0 + gEfiCpuTokenSpaceGuid.PcdCpuHwCoordination|TRUE + gEfiCpuTokenSpaceGuid.PcdCpuDcuMode|0 + gEfiCpuTokenSpaceGuid.PcdCpuTurboOverride|0x0 + gEfiCpuTokenSpaceGuid.PcdCpuProcessorMsrLockCtrl|0 + gEfiCpuTokenSpaceGuid.PcdCpuIioLlcWaysBitMask|0x0 + gEfiCpuTokenSpaceGuid.PcdCpuExpandedIioLlcWaysBitMask|0x0 + gEfiCpuTokenSpaceGuid.PcdCpuRemoteWaysBitMask|0x0 + gEfiCpuTokenSpaceGuid.PcdPchTraceHubEn|0x0 + gEfiCpuTokenSpaceGuid.PcdCpuQlruCfgBitMask|0x0 + gEfiCpuTokenSpaceGuid.PcdSbspSelection|0xFF +# gEfiCpuTokenSpaceGuid.PcdCpuSocketId|{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0= x1,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x3,0x0,0x0,= 0x0,0x3,0x0,0x0,0x0} + gEfiCpuTokenSpaceGuid.PcdCpuPmStructAddr|0x0 + gEfiCpuTokenSpaceGuid.PcdCpuRRQCountThreshold|0x0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, 0x54, 0x= 45, 0x4C, 0x20} + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20465730303632= 53 + + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0 + +[PcdsDynamicExDefault.X64] + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600 + + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0 diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat b/Pla= tform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat new file mode 100644 index 0000000000..99c082b5f9 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat @@ -0,0 +1,138 @@ +@REM @file +@REM +@REM Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+@REM SPDX-License-Identifier: BSD-2-Clause-Patent +@REM + +@echo off + +REM Run setlocal to take a snapshot of the environment variables. endloca= l is called to restore the environment. +setlocal +set SCRIPT_ERROR=3D0 + +REM ---- Do NOT use :: for comments Inside of code blocks() ---- + +::********************************************************************** +:: Initial Setup +::********************************************************************** + +:parseCmdLine +if "%1"=3D=3D"" goto :argumentCheck + +if /I "%1"=3D=3D"debug" set TARGET=3DDEBUG +if /I "%1"=3D=3D"release" set TARGET=3DRELEASE + +if /I "%1"=3D=3D"clean" ( + set BUILD_TYPE=3Dcleantree + call :cleantree + goto :EOF +) + +shift +GOTO :parseCmdLine + +:argumentCheck: + +if /I "%TARGET%" =3D=3D "" ( + echo Info: debug/release argument is empty, use DEBUG as default + set TARGET=3DDEBUG +) + +REM Art to notify which board you're working on +echo. +type logo.txt +echo. + +:: +:: Build configuration +:: +set BUILD_REPORT_FLAGS=3D +set BUILD_CMD_LINE=3D +set BUILD_LOG=3D%WORKSPACE%\Build\build.log +set BUILD_REPORT=3D%WORKSPACE%\Build\BuildReport.txt + +del %BUILD_LOG% *.efi *.log 2>NUL + +echo ---------------------------------------------------------------------= ----------------------- +echo. +echo Purley Build Start +echo. +echo ---------------------------------------------------------------------= ----------------------- + + +:doPreBuild +echo. +echo -------------------------------------------------------------------- +echo. +echo Prebuild Start +echo. +echo -------------------------------------------------------------------- +call prebuild.bat +if %SCRIPT_ERROR% NEQ 0 EXIT /b %ERRORLEVEL% + +echo -------------------------------------------------------------------- +echo. +echo Prebuild End +echo. +echo -------------------------------------------------------------------- +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% +timeout 1 + +:buildBios +set BUILD_CMD_LINE=3D%BUILD_CMD_LINE% -D MAX_SOCKET=3D%MAX_SOCKET% -y %BUI= LD_REPORT% +echo -------------------------------------------------------------------- +echo. +echo Build Start +echo. +echo -------------------------------------------------------------------- +echo. +echo build %BUILD_CMD_LINE% --log=3D%BUILD_LOG% %BUILD_REPORT_FLAGS% +call build %BUILD_CMD_LINE% --log=3D%BUILD_LOG% %BUILD_REPORT_FLAGS% +echo -------------------------------------------------------------------- +echo. +echo Build End +echo. +echo -------------------------------------------------------------------- +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% +timeout 1 + +:postBuild + +echo -------------------------------------------------------------------- +echo. +echo PostBuild Start +echo. +echo -------------------------------------------------------------------- +echo. +call postbuild.bat +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% +timeout 1 +echo -------------------------------------------------------------------- +echo. +echo PostBuild End +echo. +echo -------------------------------------------------------------------- + +echo %date% %time% +echo. + +echo ---------------------------------------------------------------------= ----------------------- +echo. +echo Purley Build End +echo. +echo ---------------------------------------------------------------------= ----------------------- + +:done +endlocal & EXIT /b %SCRIPT_ERROR% + +::-------------------------------------------------------- +::-- Function section starts below here +::-------------------------------------------------------- +:cleantree +choice /t 3 /d y /m "Confirm: clean tree of intermediate files created in = tree during build" +if %ERRORLEVEL% EQU 2 goto :EOF +goto :EOF + + +:ErrorHandler: +echo Error handler \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_board.p= y b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_board.py new file mode 100644 index 0000000000..2ba615d3e4 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_board.py @@ -0,0 +1,177 @@ +# @ build_board.py +# This adds additional functions to the build_bios.py +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +""" +This module serves as an additional build steps for the Mt Olympus board +""" + +import os +import sys + + +def pre_build_ex(config, functions): + """Additional Pre BIOS build function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: nothing + """ + print("Info: re-generating PlatformOffset header files") + + execute_script =3D functions.get("execute_script") + + command =3D ["build", "-D", "MAX_SOCKET=3D" + config.get("MAX_SOCKET",= "1"), + "-m", + os.path.join(config["PLATFORM_BOARD_PACKAGE"], + "Acpi", "BoardAcpiDxe", "Dsdt.inf"), + "-y", + config.get("PRE_BUILD_REPORT", + os.path.join(config["WORKSPACE"], + "preBuildReport.txt")), + "--log=3D" + config.get("PRE_BUILD_LOG", + os.path.join(config["WORKSPACE"], + "prebuild.log"))] + + _, _, _, code =3D execute_script(command, config) + if code !=3D 0: + print(" ".join(command)) + print("Error re-generating PlatformOffset header files") + sys.exit(1) + + config["AML_FILTER"] =3D "\"PSYS\" .MCTL\" .FIX[0-9,A-Z]\"" + print("AML_FILTER=3D ", config.get("AML_FILTER")) + + # build the command with arguments + command =3D ["python", + os.path.join(config["MIN_PACKAGE_TOOLS"], + "AmlGenOffset", + "AmlGenOffset.py"), + "-d", "--aml_filter", config["AML_FILTER"], + "-o", os.path.join(config["WORKSPACE_PLATFORM"], + config["PLATFORM_BOARD_PACKAGE"], + "Acpi", "BoardAcpiDxe", + "AmlOffsetTable.c"), + os.path.join(config["BUILD_X64"], + "PurleyOpenBoardPkg", + "Acpi", + "BoardAcpiDxe", + "DSDT", + "OUTPUT", + "Dsdt", "WFPPlatform.offset.h")] + + # execute the command + _, _, _, code =3D execute_script(command, config) + if code !=3D 0: + print(" ".join(command)) + print("Error re-generating PlatformOffset header files") + sys.exit(1) + + print("GenOffset done") + return config + + +def build_ex(config, functions): + """Additional BIOS build function + + :param config: The environment variables to be used in + the build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("build_ex") + return None + + +def post_build_ex(config, functions): + """Additional Post BIOS build function + + :param config: The environment variables to be used in the post + build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("post_build_ex") + + execute_script =3D functions.get("execute_script") + + if not execute_script: + print("post_build_ex Error") + sys.exit(1) + + common_patch_command =3D [os.path.join(config["PYTHON_HOME"], "python"= ), + os.path.join(config["MIN_PACKAGE_TOOLS"], + "PatchFv", "PatchBinFv.py"), + config["TARGET"], + os.path.join(config["WORKSPACE_SILICON_BIN"], + "PurleySiliconBinPkg", "FV"), + os.path.join(config["WORKSPACE"], + "BuildReport.log")] + + fvs_to_patch =3D ["FvTempMemorySilicon", + "FvPreMemorySilicon", + "FvPostMemorySilicon", + "FvLateSilicon"] + for fv in fvs_to_patch: + patch_command =3D common_patch_command + [fv] + _, _, _, code =3D execute_script(patch_command, config) + if code !=3D 0: + print(" ".join(patch_command)) + print("Patch Error!") + sys.exit(1) + + common_rebase_command =3D [os.path.join(config["PYTHON_HOME"], "python= "), + os.path.join(config["MIN_PACKAGE_TOOLS"], + "PatchFv", "RebaseBinFv.py"), + config["TARGET"], + os.path.join(config["WORKSPACE_SILICON_BIN"], + "PurleySiliconBinPkg", "FV"), + os.path.join(config["WORKSPACE"], + "BuildReport.log")] + + rebase_command =3D common_rebase_command +\ + ["FvPreMemorySilicon", + "gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase"] + + _, _, _, code =3D execute_script(rebase_command, config) + if code !=3D 0: + print(" ".join(rebase_command)) + print("Patch Error!") + sys.exit(1) + + rebase_command =3D common_rebase_command +\ + ["FvPostMemorySilicon", + "gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase"] + + _, _, _, code =3D execute_script(rebase_command, config) + if code !=3D 0: + print(" ".join(rebase_command)) + print("Patch Error!") + sys.exit(1) + + return None + + +def clean_ex(config, functions): + """Additional clean function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("clean_ex") + return None diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_config.= cfg b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg new file mode 100644 index 0000000000..165c7db0e3 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg @@ -0,0 +1,32 @@ +# @ build_config.cfg +# This is the main/default build configuration file +# +# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[CONFIG] +WORKSPACE_PLATFORM_BIN =3D +EDK_SETUP_OPTION =3D +openssl_path =3D +PLATFORM_BOARD_PACKAGE =3D PurleyOpenBoardPkg +PROJECT =3D PurleyOpenBoardPkg/BoardMtOlympus +BOARD =3D BoardMtOlympus +FLASH_MAP_FDF =3D PurleyOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf +PROJECT_DSC =3D PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc +BOARD_PKG_PCD_DSC =3D PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc +ADDITIONAL_SCRIPTS =3D PurleyOpenBoardPkg/BoardMtOlympus/build_board.py +PRE_BUILD_LOG =3D prebuild.log +PRE_BUILD_REPORT =3D prebuildReport.log +PrepRELEASE =3D DEBUG +SILENT_MODE =3D FALSE +EXT_CONFIG_CLEAR =3D +CapsuleBuild =3D FALSE +EXT_BUILD_FLAGS =3D +CAPSULE_BUILD =3D 0 +TARGET =3D DEBUG +TARGET_SHORT =3D D +PERFORMANCE_BUILD =3D FALSE +FSP_WRAPPER_BUILD =3D FALSE +MAX_SOCKET =3D 2 diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt b/Pl= atform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt new file mode 100644 index 0000000000..979ddb6691 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt @@ -0,0 +1,11 @@ + + _____ ______ _________ ________ ___ ___ _= __ _____ ______ ________ ___ ___ ________ =20 +|\ _ \ _ \ |\___ ___\ |\ __ \ |\ \ |\ \ / = /||\ _ \ _ \ |\ __ \ |\ \|\ \ |\ ____\ =20 +\ \ \\\__\ \ \ \|___ \ \_| \ \ \|\ \ \ \ \ \ \ \/ = / /\ \ \\\__\ \ \ \ \ \|\ \ \ \ \\\ \ \ \ \___|_ =20 + \ \ \\|__| \ \ \ \ \ \ \ \\\ \ \ \ \ \ \ /= / \ \ \\|__| \ \ \ \ ____\ \ \ \\\ \ \ \_____ \ =20 + \ \ \ \ \ \ \ \ \ \ \ \\\ \ \ \ \____ \/ / = / \ \ \ \ \ \ \ \ \___| \ \ \\\ \ \|____|\ \ =20 + \ \__\ \ \__\ \ \__\ \ \_______\ \ \_______\ __/ / / = \ \__\ \ \__\ \ \__\ \ \_______\ ____\_\ \=20 + \|__| \|__| \|__| \|_______| \|_______||\___/ / = \|__| \|__| \|__| \|_______| |\_________\ + \|___|/ = \|_________| + = =20 + = =20 diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat= b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat new file mode 100644 index 0000000000..6393e4caec --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat @@ -0,0 +1,95 @@ +@REM @file +@REM +@REM Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+@REM SPDX-License-Identifier: BSD-2-Clause-Patent +@REM + +@set SCRIPT_ERROR=3D0 + +set /a postbuildstep=3D0 + +@echo. +@echo BoardPostBuild.%postbuildstep% python PatchBinFv.py +@set /a postbuildstep=3D%postbuildstep%+1 +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools= \PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\Purl= eySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvTempMemorySilicon +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\Mi= nPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\= Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvTe= mpMemorySilicon +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=3D1 + echo PatchBinFv Error. Exit + goto :EOF +) +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools= \PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\Purl= eySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\Mi= nPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\= Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPr= eMemorySilicon +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=3D1 + echo PatchBinFv Error. Exit + goto :EOF +) +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools= \PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\Purl= eySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\Mi= nPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\= Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPo= stMemorySilicon +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=3D1 + echo PatchBinFv Error. Exit + goto :EOF +) +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools= \PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\Purl= eySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvLateSilicon +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\Mi= nPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\= Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvLa= teSilicon +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=3D1 + echo PatchBinFv Error. Exit + goto :EOF +) + +@echo. +@echo BoardPostBuild.%postbuildstep% python RebaseBinFv.py +@set /a postbuildstep=3D%postbuildstep%+1 +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools= \PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\Pur= leySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\Mi= nPlatformPkg\Tools\PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi= \Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvP= reMemorySilicon gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=3D1 + echo RebaseBinFv Error. Exit + goto :EOF +) + +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools= \PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\Pur= leySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon g= MinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\Mi= nPlatformPkg\Tools\PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi= \Silicon\Intel\PurleySiliconBinPkg\FV %WORKSPACE%\Build\BuildReport.txt FvP= ostMemorySilicon gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=3D1 + echo RebaseBinFv Error. Exit + goto :EOF +) + +@echo. +@echo BoardPostBuild.%postbuildstep% re-generate FDS +@set /a postbuildstep=3D%postbuildstep%+1 +echo build fds +@REM call build fds +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=3D1 + echo gen FDS Error. Exit + goto :EOF +) + +@echo. +@echo BoardPostBuild.%postbuildstep% python PatchBfv.py +@set /a postbuildstep=3D%postbuildstep%+1 +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools= \PatchFv\PatchBfv.py %WORKSPACE%\Build\%BOARD_PKG%\%BOARD_NAME%\%TARGET%_%T= OOL_CHAIN_TAG%\FV\PLATFORM.fd %WORKSPACE%\Build\BuildReport.txt gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\Mi= nPlatformPkg\Tools\PatchFv\PatchBfv.py %WORKSPACE%\Build\%BOARD_PKG%\%BOARD= _NAME%\%TARGET%_%TOOL_CHAIN_TAG%\FV\PLATFORM.fd %WORKSPACE%\Build\BuildRepo= rt.txt gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=3D1 + echo PatchBfv Error. Exit + goto :EOF +) + +:_done + +@echo. +@cd %WORKSPACE% +@if "%SCRIPT_ERROR%" =3D=3D "0" ( + @echo PostBuild SUCCEEDED. +) else ( + @echo PostBuild FAILED. + Pause 0 +) + +EXIT /B %SCRIPT_ERROR% diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat = b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat new file mode 100644 index 0000000000..22eeac1e80 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat @@ -0,0 +1,197 @@ +@REM @file +@REM +@REM Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+@REM SPDX-License-Identifier: BSD-2-Clause-Patent +@REM + +@set SCRIPT_ERROR=3D0 + +set /a prebuildstep=3D0 + +call :check_BuildTools +if %SCRIPT_ERROR% NEQ 0 GOTO :done + +call :setBuildEnv +if %SCRIPT_ERROR% NEQ 0 GOTO :done + +call :createTargetTxt +if %SCRIPT_ERROR% NEQ 0 GOTO :done + +call :genPlatformOffsetHeaderFile +if %SCRIPT_ERROR% NEQ 0 GOTO :done + +:prebuildFinish +echo. +echo ACTIVE_PLATFORM =3D %WORKSPACE%\edk2-platforms\Platfor= m\Intel\%BOARD_PKG%\%BOARD_NAME%\OpenBoardPkg.dsc +echo EDK_TOOLS_PATH =3D %EDK_TOOLS_PATH% +echo TARGET =3D %TARGET% +echo TARGET_ARCH =3D IA32 X64 +echo TOOL_CHAIN_TAG =3D %TOOL_CHAIN_TAG% +echo WORKSPACE =3D %WORKSPACE% +echo PACKAGES_PATH =3D %PACKAGES_PATH% +echo MAX_CONCURRENT_THREAD_NUMBER =3D %BUILD_MAX_CON_THREAD_NUM% +echo. +echo Build Path =3D %OUTPUT_DIR% +echo. + +REM Remove environment variable because it's no longer needed. +set BUILD_MAX_CON_THREAD_NUM=3D + +:done +REM Use done label to exit batch file and run any final steps; GOTO :EOF i= mmediately exits. +EXIT /B %SCRIPT_ERROR% + +::-------------------------------------------------------- +::-- Function section starts below here +::-------------------------------------------------------- + +:cleanup_check_VSTools +set COMPILER_VERSION_STRING=3D +del cloutput.txt > nul +REM cleanup_check_VSTools is called below. When a label is called, 'GOTO := EOF' is used to return to caller. +GOTO :EOF + +:check_BuildTools +echo PreBuild.%prebuildstep% check_BuildTools +echo ..VSTools +set /a prebuildstep=3D%prebuildstep%+1 +set TOOL_CHAIN_TAG=3D +@if not defined TOOL_CHAIN_TAG ( + echo. + echo Prebuild: TOOL_CHAIN_TAG is not set before + echo. + + @if defined VS140COMNTOOLS ( + echo. + echo Set the VS2015 environment. + echo. + set CL_SEL=3DVS2015 + if /I "%VS140COMNTOOLS%" =3D=3D "C:\Program Files\Microsoft Visual Stu= dio 14.0\Common7\Tools\" ( + set TOOL_CHAIN_TAG=3DVS2015 + ) else ( + set TOOL_CHAIN_TAG=3DVS2015x86 + ) + if /I "%PROCESSOR_ARCHITECTURE%" =3D=3D "AMD64" ( + set CL_CMDLINE=3D"%VS140COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe" + ) else ( + set CL_CMDLINE=3D"%VS140COMNTOOLS:~0,-14%VC\bin\cl.exe" + ) + ) else if defined VS120COMNTOOLS ( + echo. + echo Set the VS2013 environment. + echo. + set CL_SEL=3DVS2013 + if /I "%VS120COMNTOOLS%" =3D=3D "C:\Program Files\Microsoft Visual Stu= dio 12.0\Common7\Tools\" ( + set TOOL_CHAIN_TAG=3DVS2013 + ) else ( + set TOOL_CHAIN_TAG=3DVS2013x86 + ) + if /I "%PROCESSOR_ARCHITECTURE%" =3D=3D "AMD64" ( + set CL_CMDLINE=3D"%VS120COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe" + ) else ( + set CL_CMDLINE=3D"%VS120COMNTOOLS:~0,-14%VC\bin\cl.exe" + ) + ) else ( + echo. + echo !!! ERROR !!! VS2015 or VS2013 not installed correctly. !!! + echo. + goto :ErrorExit + ) +) + +echo ..iASL +set CHECK_PATH_IASL=3D%IASL_PREFIX% +if not exist %CHECK_PATH_IASL%\iasl.exe ( + echo. + echo !!! ERROR !!! Could not find iASL compiler at %CHECK_PATH_IASL%\ias= l.exe. !!! + echo. + set SCRIPT_ERROR=3D1 +) +set CHECK_PATH_IASL=3D + +echo ..NASM +set CHECK_PATH_NASM=3Dc:\NASM +if not exist %CHECK_PATH_NASM%\nasm.exe ( + echo. + echo !!! ERROR !!! Could not find NASM compiler at %CHECK_PATH_NASM%\nas= m.exe. !!! + echo. + set SCRIPT_ERROR=3D1 +) +set CHECK_PATH_NASM=3D + +echo ..Python +set CHECK_PATH_PYTHON=3Dc:\Python27 +if not exist %CHECK_PATH_PYTHON%\python.exe ( + echo. + echo !!! ERROR !!! Could not find Python at %CHECK_PATH_PYTHON%\python.e= xe. !!! + echo. + set SCRIPT_ERROR=3D1 +) +set CHECK_PATH_PYTHON=3D +set PYTHON_HOME=3DC:\Python27 + +GOTO :EOF + +:setBuildEnv +echo PreBuild.%prebuildstep% SetBuildEnv +set /a prebuildstep=3D%prebuildstep%+1 + +@set BOARD_PKG=3DPurleyOpenBoardPkg +@set BOARD_NAME=3DBoardMtOlympus +@set MAX_SOCKET=3D2 + +echo. +echo BOARD_NAME=3D%BOARD_NAME% +echo BOARD_PKG=3D%BOARD_PKG% +echo MAX_SOCKET=3D%MAX_SOCKET% +echo TARGET=3D%TARGET% + +@set OUTPUT_DIR=3D%WORKSPACE%\Build\%BOARD_PKG%\%BOARD_NAME%\%TARGET%_%TOO= L_CHAIN_TAG% + +if not exist %OUTPUT_DIR% mkdir %OUTPUT_DIR% +GOTO :EOF + +:createTargetTxt +echo PreBuild.%prebuildstep% CreateTargetTxt +set /a prebuildstep=3D%prebuildstep%+1 +set /a BUILD_MAX_CON_THREAD_NUM =3D %NUMBER_OF_PROCESSORS%-1 +@REM set /a BUILD_MAX_CON_THREAD_NUM =3D 1 +findstr /V "ACTIVE_PLATFORM TARGET TARGET_ARCH TOOL_CHAIN_TAG BUILD_RULE_C= ONF MAX_CONCURRENT_THREAD_NUMBER" %WORKSPACE%\Conf\target.txt > %OUTPUT_DIR= %\target.txt 2>NUL +echo ACTIVE_PLATFORM =3D %WORKSPACE%/edk2-platforms/Platform/I= ntel/%BOARD_PKG%/%BOARD_NAME%/OpenBoardPkg.dsc >> %OUTPUT_DIR%\target.txt +echo TARGET =3D %TARGET% >> %OU= TPUT_DIR%\target.txt +echo TARGET_ARCH =3D IA32 X64 >> %OU= TPUT_DIR%\target.txt +echo TOOL_CHAIN_TAG =3D %TOOL_CHAIN_TAG% >> %OU= TPUT_DIR%\target.txt +echo BUILD_RULE_CONF =3D Conf/build_rule.txt >> %OU= TPUT_DIR%\target.txt +echo MAX_CONCURRENT_THREAD_NUMBER =3D %BUILD_MAX_CON_THREAD_NUM% >> %OU= TPUT_DIR%\target.txt +if exist %WORKSPACE%\Conf\target.txt ( + del /f %WORKSPACE%\Conf\target.txt +) +move /Y %OUTPUT_DIR%\target.txt %WORKSPACE%\Conf\ > nul +if not exist %OUTPUT_DIR%\X64 mkdir %OUTPUT_DIR%\X64 +GOTO :EOF + + +:genPlatformOffsetHeaderFile +echo. +echo PreBuild.%prebuildstep% GenPlatformOffsetHeaderFile +set /a prebuildstep=3D%prebuildstep%+1 + +echo Info: re-generating PlatformOffset header files + +set PRE_BUILD_CMD_LINE=3D%BUILD_CMD_LINE% -D MAX_SOCKET=3D%MAX_SOCKET% +set PRE_BUILD_LOG=3D%WORKSPACE%\Build\prebuild.log +set PRE_BUILD_REPORT=3D%WORKSPACE%\Build\preBuildReport.txt + +echo build %PRE_BUILD_CMD_LINE% -m %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf = -y %PRE_BUILD_REPORT% --log=3D%PRE_BUILD_LOG% +call build %PRE_BUILD_CMD_LINE% -m %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf = -y %PRE_BUILD_REPORT% --log=3D%PRE_BUILD_LOG% +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% + +@REM PSYS =3D=3D FIX0 +@REM MCTL =3D=3D FIX8 +set AML_FILTER=3D"\"PSYS\" .MCTL\" .FIX[0-9,A-Z]\"" +echo AML_FILTER=3D%AML_FILTER% +call %PYTHON_HOME%\python.exe %WORKSPACE%\edk2-platforms\Platform\Intel\Mi= nPlatformPkg\Tools\AmlGenOffset\AmlGenOffset.py -d --aml_filter %AML_FILTER= % -o %WORKSPACE%\edk2-platforms\Platform\Intel\%BOARD_PKG%\Acpi\BoardAcpiDx= e\AmlOffsetTable.c %OUTPUT_DIR%\X64\PurleyOpenBoardPkg\Acpi\BoardAcpiDxe\DS= DT\OUTPUT\Dsdt\WFPPlatform.offset.h +echo. +echo GenOffset done + +GOTO :EOF \ No newline at end of file diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index 97c5c9a290..ede542f9f5 100644 --- a/Platform/Intel/build.cfg +++ b/Platform/Intel/build.cfg @@ -54,6 +54,7 @@ BIOS_INFO_GUID =3D =20 [PLATFORMS] # board_name =3D path_to_board_build_config.cfg +BoardMtOlympus =3D PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg BoardX58Ich10 =3D SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg GalagoPro3 =3D KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg KabylakeRvp3 =3D KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74983): https://edk2.groups.io/g/devel/message/74983 Mute This Topic: https://groups.io/mt/82742444/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 12:00:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74984+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74984+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1620726557; cv=none; d=zohomail.com; s=zohoarc; b=JmVRR0uzWildB1ScWE8X1jMrhJXePZOZnEUCC0lzva8bQYNgeRsYbbUS5Xz3WDIqDFAblu7LuAvd5/92v+M58boqts2No5azyveKttQTR9tzAr/NtYc8ad1Ge4+K+srAEf09PQF77l5DvbGYTmnPhl0AvJrJgZyqfF8wdE9t4A8= ARC-Message-Signature: i=1; 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Tue, 11 May 2021 02:49:05 -0700 IronPort-SDR: Y/slON4TZb+PeK4CDZmu9bWE1bYeRjN1t+nq73x/6/SBpx/HJJmSIK/buzzljg1mWGZ/OWHPSu PW5P3iASYjRQ== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="178994728" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="178994728" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:56 -0700 IronPort-SDR: Bvr0YOVn/atGVtQsMOQQgtA+BbNOdxZeEp/y1SDwNQwbFjF+xDpXJmjHHBzuCBbQ3ae8DteVWW MHstwNmhH3IA== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436574039" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:55 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 15/18] PurleyOpenBoardPkg: Add StructureConfig.dsc Date: Tue, 11 May 2021 02:48:23 -0700 Message-Id: <20210511094826.12495-16-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: rBYH4Gs2PjRRJTktzrnayzjBx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726556; bh=0Vk1N6wWsB0d2PQ3yKW8IIO9KkeYzoxVFTWP2jDGCyQ=; h=Cc:Date:From:Reply-To:Subject:To; b=G9HBDTrCYjRKbOr8AKMf/4gS4oERYbpJT0IECZ0BDsPWvxhH22je6IL9BVh8NldMf84 3X5/m9VOdICF0B5hFdoIzNjYpOxwAB3ill9wS1ET8f2HQCaJd1ZzZe3QbS3DpOPWIUmUo NNcgre2jkbPmBbvkU1rC2Hk3InQFQk4Cqb8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../BoardMtOlympus/StructureConfig.dsc | 6203 +++++++++++++++++ 1 file changed, 6203 insertions(+) create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Struct= ureConfig.dsc diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/StructureConf= ig.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/StructureConfig.d= sc new file mode 100644 index 0000000000..84947cdc8f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/StructureConfig.dsc @@ -0,0 +1,6203 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +#[PcdsDynamicEx.common.DEFAULT.MANUFACTURING] +# gOemSkuTokenSpaceGuid.PcdSetupData|L"Setup"|ec87d643-eba4-4bb5-a1e5-3f3= e36b20da9|0x00 +# gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugMsgLvl|0x1 +# gOemSkuTokenSpaceGuid.PcdSetupData.TagecMem|0x1 +# gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData|L"PchRcConfiguration"|d= 19a26a3-17f1-48c3-8a1e-11eb0a7f6e4e|0x00 +# gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudio|0x0 +# gOemSkuTokenSpaceGuid.PcdSocketIioConfigData|L"SocketIioConfig"|dd84017= e-7f52-48f9-b16e-50ed9e0dbe27|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData|L"SocketCommonRcConfi= g"|4402ca38-808f-4279-bcec-5baf8d59092f|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData|L"SocketMpLinkConfig"|2= b9b22de-2ad4-4abc-957d-5f18c504a05c|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData|L"SocketMemoryConfig"|9= 8cf19ed-4109-4681-b79d-9196757c7824|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData|L"SocketPowerM= anagementConfig"|A1047342-BDBA-4DAE-A67A-40979B65C7F8|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProchotLock|0x1 +# gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PkgCstEntryVal= Ctl|0x0 +# gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboPowerLimi= tLock|0x1 +# gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData|L"SocketProcesso= rCoreConfig"|07013588-C789-4E12-A7C3-88FAFAE79F7C|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorVmxEnab= le|0x0 +# gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorMsrLock= Control|0x0 + +#[PcdsDynamicEx.common.DEFAULT.STANDARD] + #gOemSkuTokenSpaceGuid.PcdSetupData|L"Setup"|ec87d643-eba4-4bb5-a1e5-3f3= e36b20da9|0x00 + gOemSkuTokenSpaceGuid.PcdSetupData|{0x0} + gOemSkuTokenSpaceGuid.PcdSetupData.CloudProfile|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.Use1GPageTable|0x1 + #gOemSkuTokenSpaceGuid.PcdSetupData.ResetOnMemMapChange|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FanPwmOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.WakeOnLanSupport|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationBreakpointType|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.bsdBreakpoint|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ForceSetup|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.BiosGuardEnabled|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.RtoPopulateBGDirectory|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.EnableAntiFlashWearout|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.SkipXmlComprs|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.DfxAdvDebugJumper|0x2 + gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugMsgLvl|0x4 + gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugTrace|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugMsgLvlTrainResults|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.VideoSelect|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.Ps2PortSwap|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.Numlock|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.WakeOnLanS5|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.BootNetwork|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ARIEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SRIOVEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SystemPageSize|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.MRIOVEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.WakeOnRTCS4S5|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.RTCWakeupTimeHour|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.RTCWakeupTimeMinute|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.RTCWakeupTimeSecond|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.LegacyPxeRom|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.EfiNetworkSupport|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.LomDisableByGpio|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ReserveMem|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ReserveStartAddr|0x100000 + gOemSkuTokenSpaceGuid.PcdSetupData.TagecMem|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationResetType|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationCountOuter|0x1f4 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationCountInner|0x1f4 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationStopOnError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationBootWhenDone|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciLinkError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciLinkRecoveryCountErro= r|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciLinkRecoveryCountThre= shold|0x4 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationPchPciError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationKtiError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.XhciWakeOnUsbEnabled|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbLegacySupport|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmul6064|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbMassResetDelay|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbNonBoot|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu1|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu2|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu3|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu4|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu5|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu6|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu7|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu8|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu9|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu10|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu11|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu12|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu13|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu14|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu15|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu16|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieClockGating|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.GbePciePortNum|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.RamDebugInterface|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.TraceHubDebugInterface|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SystemErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PoisonEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ViralEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClearViralStatus|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CloakingEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UboxToPcuMcaEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.CaterrGpioSmiEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FatalErrSpinLoopEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.LmceEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaIgnOptin|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaCsmiEn|0x2 + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaMsmiEn|0x2 + gOemSkuTokenSpaceGuid.PcdSetupData.ElogCorrErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ElogMemErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ElogProcErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaSupportEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaLogMemoryEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaLogProcEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaLogPciEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.McaBankErrInjEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaErrorInjSupportEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaErrInjEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaPcieErrInjEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieErrInjActionTable|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.MeSegErrorInjEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ParityCheckEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.McBankWarmBootClearError|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.KTIFailoverSmiEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.MemErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.CorrMemErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.LeakyBktHiLeakyBktLo|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.SpareIntSelect|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FnvErrorEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FnvErrorLowPrioritySignal|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FnvErrorHighPrioritySignal|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IioErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IoMcaEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioErrorPinEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IioErrRegistersClearEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.LerEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.DisableMAerrorLoggingDueToLER|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioIrpErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_parityError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_qtOverflow|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_unexprsp|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_csraccunaligned|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_unceccCs0|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_unceccCs1|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_rcvdpoison|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_crreccCs0|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_crreccCs1|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioMiscErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioVtdErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioDmaErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioDmiErrorEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioPcieAddCorrErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioPcieAddUnCorrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioPcieAerSpecCompEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorrErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieUncorrErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieFatalErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorErrCntr|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorErrMaskBitMap|0x3f + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorErrThres|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerCorrErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerAdNfatErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerNfatErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerFatErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SerrPropEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PerrPropEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.OsSigOnSerrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.OsSigOnPerrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ConsoleRedirection|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.FlowControl|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.BaudRate|0x5 + gOemSkuTokenSpaceGuid.PcdSetupData.TerminalType|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.Parity|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.DataBits|0x8 + gOemSkuTokenSpaceGuid.PcdSetupData.StopBits|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.TerminalResolution|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.LegacyOsRedirection|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.BootAllOptions|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.OverclockingSupport|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FilterPll|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreMaxOcRatio|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageMode|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageOverride|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreExtraTurboVoltage|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageOffsetPrefix|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrMaxOcRatio|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageMode|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageOverride|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrExtraTurboVoltage|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageOffsetPrefix|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UncoreVoltageOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UncoreVoltageOffsetPrefix|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IoaVoltageOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IoaVoltageOffsetPrefix|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IodVoltageOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IodVoltageOffsetPrefix|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.VccIoVoltage|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.SvidEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SvidVoltageOverride|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CpuVccInVoltage|0x167 + gOemSkuTokenSpaceGuid.PcdSetupData.FivrFaultsEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.FivrEfficiencyEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SerialBaudRate|0x1c200 + gOemSkuTokenSpaceGuid.PcdSetupData.UefiOptimizedBootToggle|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.EfiWindowsInt10Workaround|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.SetShellFirst|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbStackSupport|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData|{0} + #gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData|L"PchRcConfiguration"|d= 19a26a3-17f1-48c3-8a1e-11eb0a7f6e4e|0x00 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.FirmwareConfiguration|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchDciEn|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchDciAutoDetect|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.BoardCapability|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DeepSxMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Gp27WakeFromDeepSx|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSmbus|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSerm|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchDisplay|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPciClockRun|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSirqMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableClockSpreadSpec|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.StateAfterG3|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.IchPort80Route|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchCrossThrottling|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchCrid|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PciePllSsc|0xff + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.UsbPrecondition|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbManualMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Btcg|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Usb3PinsTermination|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbPerPortCtl|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XhciIdleL1|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XhciDisMSICapability|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XhciOcMapEnabled|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudio|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudioCodecSelect|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudioPme|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RtoHdaVcType|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSata|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataInterfaceMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTestMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSalp|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataAlternateId|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidLoadEfiDriver|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemap[0]|0= x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemapPort[= 0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemap[1]|0= x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemapPort[= 1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemap[2]|0= x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemapPort[= 2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PxDevSlp[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHddlk|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataLedl|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR0|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR1|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR10|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR5|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidIrrt|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidOub|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidIooe|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidSrt|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidOromDelay|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchsSata|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataInterfaceMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTestMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSalp|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataAlternateId|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidLoadEfiDriver|0= x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHddlk|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataLedl|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR0|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR1|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR10|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR5|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidIrrt|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidOub|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidIooe|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidSrt|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidOromDelay|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchWakeOnLan|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSlpLanLowDc|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchLanK1Off|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PciDelayOptimizationEcr|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieComplianceTestMode|0= x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieGlobalAspm|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX16CompletionTim= eout|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX8CompletionTime= out|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX16MaxPayloadSiz= e|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX8MaxPayloadSize= |0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieDmiExtSync|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieDmiStopAndScreamEnab= le|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XTpmLen|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSBDE|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSBDEPort|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFunctionSwap= ping|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxReadReque= stSize|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[0]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[0]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[1]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[1]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[2]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[2]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[3]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[3]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[4]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[4]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[5]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[5]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[6]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[6]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[7]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[7]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[8]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[8]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[9]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[9]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[10]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[10]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[11]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[11]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[12]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[12]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[13]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[13]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[14]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[14]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[15]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[15]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[16]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[16]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[17]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[17]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[18]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[18]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[19]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[19]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqOverride|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[0]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[0]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[1]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[1]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[2]|0x8 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[2]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[4]|0xa + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[4]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 0]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 0]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[0]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[0]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[0]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[0]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[0]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[0]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[0]|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 1]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 1]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[1]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[1]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[1]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[1]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[1]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[1]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[1]|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 2]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 2]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[2]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[2]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[2]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[2]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[2]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[2]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[2]|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 3]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 3]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[3]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[3]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[3]|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 4]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 4]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[4]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[4]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[4]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[4]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[4]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[4]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[4]|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 5]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 5]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[5]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[5]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[5]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[5]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[5]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[5]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[5]|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 6]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 6]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[6]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[6]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[6]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[6]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[6]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[6]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[6]|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 7]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 7]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[7]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[7]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[7]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[7]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[7]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[7]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[7]|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 8]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 8]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[8]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[8]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[8]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[8]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[8]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[8]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[8]|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 9]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 9]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[9]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[9]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[9]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[9]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[9]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[9]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[9]|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 10]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 10]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[10]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[10]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[10]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[10]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[10]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[10]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[10]= |0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 11]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 11]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[11]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[11]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[11]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[11]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[11]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[11]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[11]= |0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 12]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 12]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[12]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[12]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[12]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[12]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[12]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[12]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[12]= |0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 13]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 13]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[13]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[13]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[13]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[13]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[13]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[13]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[13]= |0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 14]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 14]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[14]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[14]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[14]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[14]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[14]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[14]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[14]= |0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 15]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 15]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[15]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[15]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[15]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[15]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[15]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[15]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[15]= |0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 16]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 16]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[16]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[16]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[16]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[16]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[16]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[16]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[16]= |0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 17]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 17]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[17]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[17]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[17]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[17]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[17]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[17]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[17]= |0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[18]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 18]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 18]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[18]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[18]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[18]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[18]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[18]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[18]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[18]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[18]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[18]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[18]= |0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[19]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[= 19]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[= 19]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[19]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[19]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSi= ze[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTi= meout[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[19]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMode[19]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideValue[19]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverr= ideMultiplier[19]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMode[19]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideValue[19]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOv= errideMultiplier[19]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[19]= |0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSmmBwp|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.ThermalDeviceEnable|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.ThermalDeviceEnable|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TraceHubEnableMode|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.MemRegion0BufferSize|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.MemRegion1BufferSize|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Dwr_Enable|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Dwr_Stall|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PMCGBL|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_CPUTHRM|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PCHTHRM|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PBO|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_MEPBO|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_MEWDT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_MEGBL|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_CTWDT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PMCWDT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_ME_UERR|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_SYSPWR|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_OCWDT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IEPBO|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IEWDT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IEGBLN|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IE_UERRN|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_ACRU_ERR_2H_EN|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_HOST_RESET_TIME= OUT|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_SX_ENTRY_TIMEOU= T|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_HOST_RST_PROM|0= x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_HSMB_MSG|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_IE_MTP_TIMEOUT|= 0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_MTP_TIMEOUT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_ESPI_ERROR_DETE= CT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchP2sbDevReveal|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchP2sbUnlock|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TestDmiAspmCtrl|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PmcReadDisable|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TestSmbusSpdWriteDisable= |0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchAllUnLock|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchTraceHubHide|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchRtcLock|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchBiosLock|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchGbeFlashLockDown|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchThermalUnlock|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.FlashLockDown|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchEvaMrom0HookEnable|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchEvaMrom1HookEnable|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TestMctpBroadcastCycle|0= x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DmiLinkDownHangBypass|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchAdrEn|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrTimerEn|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrTimerVal|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrMultiplierVal|0x63 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrGpioSel|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataLtrEnable|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataLtrOverride|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataSnoopLatencyOverr= ideValue|0x28 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataSnoopLatencyOverr= ideMultiplier|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataLtrConfigLock|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataLtrEnable|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataLtrOverride|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataSnoopLatencyOver= rideValue|0x28 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataSnoopLatencyOver= rideMultiplier|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataLtrConfigLock|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[18]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[19]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[= 19]|0x0 + #gOemSkuTokenSpaceGuid.PcdSocketIioConfigData|L"SocketIioConfig"|dd84017= e-7f52-48f9-b16e-50ed9e0dbe27|0x00 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData|{0x0} + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Pci64BitResourceAllocation|= 0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieBiosTrainEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieHotPlugEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAcpiHotPlugEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MultiCastEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.McastBaseAddrRegion|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.McastIndexPosition|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.McastNumGroup|0x8 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[24]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[25]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[26]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[27]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[28]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[29]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[30]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[31]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[32]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[33]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[34]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[35]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[36]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[37]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[38]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[39]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[40]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[41]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[42]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[43]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[44]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[45]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[46]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[47]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[48]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[49]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[50]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[51]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[52]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[53]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[54]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[55]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[56]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[57]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[58]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[59]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[60]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[61]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[62]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[63]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[64]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[65]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[66]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[67]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[68]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[69]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[70]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[71]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[72]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[73]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[74]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[75]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[76]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[77]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[78]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[79]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[80]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[81]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[82]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[83]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NoSnoopRdCfg|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NoSnoopWrCfg|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MaxReadCompCombSize|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ProblematicPort|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DmiAllocatingFlow|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAllocatingFlow|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HaltOnDmiDegraded|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RxClockWA|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.GlobalPme2AckTOCtrl|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MctpEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PCUF6Hide|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EN1K|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DualCvIoFlow|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CoherentReadPart|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CoherentReadFull|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutGlobal|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutGlobalValu= e|0x9 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieGlobalAspm|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.StopAndScream|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SnoopResponseHoldOff|0xf + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PCIe_LTR|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieExtendedTagField|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PCIe_AtomicOpReq|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxReadRequestSize|0x7 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieRelaxedOrdering|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU0[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU1[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU2[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP0[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP1[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeout[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutValue[0]|0= x9 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpCorrectableErrorEsc[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableNonFatalErro= rEsc[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableFatalErrorEs= c[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU0[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU1[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU2[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP0[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP1[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeout[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutValue[1]|0= x9 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpCorrectableErrorEsc[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableNonFatalErro= rEsc[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableFatalErrorEs= c[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VTdSupport|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InterruptRemap|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PassThroughDma|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ATS|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IioPresent[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IioPresent[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PostedInterrupt|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CoherencySupport|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[0]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[0]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[0]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[0]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[0]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[1]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[1]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[1]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[1]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[1]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[2]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[2]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[2]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[2]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[2]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[3]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[3]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[3]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[3]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[3]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[4]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[4]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[4]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[4]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[4]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[5]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[5]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[5]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[5]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[5]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[6]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[6]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[6]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[6]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[6]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[7]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[7]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[7]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[7]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[7]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[8]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[8]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[8]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[8]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[8]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[9]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[9]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[9]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[9]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[9]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[10]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[10]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[10]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[10]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[10]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[11]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[11]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[11]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[11]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[11]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom1|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom2|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom3|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom4|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom5|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom6|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom7|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom8|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisableTPH|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PrioritizeTPH|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CbRelaxedOrdering|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[24]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[25]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[26]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[27]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[28]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[29]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[30]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[31]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLogger|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLoggerStop|0x99 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLoggerSpeed|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLoggerMask|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoJitterLogger|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[84]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[85]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[86]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[87]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[88]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[89]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[90]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[91]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[92]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[93]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[94]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[95]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[96]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[97]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[98]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[99]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[100]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[101]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[102]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[103]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[104]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[105]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[106]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[107]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[108]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[109]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[110]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[111]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[112]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[113]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[114]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[115]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[116]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[117]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[118]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[119]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[120]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[121]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[122]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[123]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[124]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[125]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[126]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[127]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[128]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[129]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[130]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[131]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[132]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[133]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[134]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[135]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[136]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[137]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[138]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[139]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[140]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[141]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[142]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[143]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[144]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[145]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[146]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[147]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[148]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[149]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[150]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[151]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[152]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[153]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[154]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[155]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[156]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[157]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[158]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[159]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[160]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[161]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[162]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[163]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[164]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[165]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[166]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[167]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[168]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[169]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[170]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[171]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[172]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[173]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[174]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[175]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[176]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[177]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[178]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[179]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[180]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[181]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[182]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[183]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[184]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[185]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[186]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[187]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[188]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[189]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[190]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[191]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 0]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[0]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [0]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 0]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[0]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [0]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 1]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[1]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [1]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 1]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[1]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [1]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 2]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[2]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [2]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 2]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[2]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [2]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 3]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[3]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [3]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 3]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[3]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [3]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 4]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[4]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [4]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 4]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[4]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [4]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[4]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[4]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[4]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 5]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[5]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [5]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 5]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[5]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [5]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[5]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[5]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[5]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 6]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[6]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [6]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 6]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[6]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [6]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[6]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[6]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[6]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 7]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[7]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [7]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 7]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[7]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [7]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[7]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[7]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[7]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 8]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[8]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [8]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 8]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[8]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [8]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[8]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[8]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[8]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 9]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[9]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [9]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 9]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[9]|= 0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [9]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[9]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[9]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[9]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 10]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[10]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [10]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 10]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[10]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [10]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[10]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[10]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[10]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 11]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[11]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [11]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 11]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[11]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [11]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[11]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[11]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[11]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 12]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[12]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [12]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 12]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[12]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [12]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[12]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[12]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[12]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 13]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[13]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [13]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 13]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[13]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [13]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[13]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[13]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[13]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 14]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[14]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [14]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 14]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[14]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [14]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[14]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[14]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[14]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 15]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[15]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [15]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 15]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[15]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [15]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[15]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[15]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[15]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 16]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[16]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [16]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 16]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[16]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [16]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[16]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[16]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[16]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 17]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[17]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [17]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 17]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[17]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [17]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[17]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[17]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[17]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 18]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[18]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [18]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 18]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[18]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [18]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[18]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[18]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[18]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 19]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[19]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [19]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 19]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[19]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [19]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[19]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[19]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[19]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 20]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[20]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [20]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 20]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[20]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [20]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[20]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[20]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[20]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 21]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[21]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [21]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 21]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[21]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [21]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[21]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[21]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[21]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 22]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[22]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [22]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 22]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[22]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [22]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[22]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[22]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[22]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 23]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[23]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [23]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 23]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[23]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [23]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[23]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[23]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[23]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 24]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[24]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [24]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 24]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[24]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [24]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[24]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[24]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[24]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 25]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[25]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [25]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 25]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[25]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [25]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[25]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[25]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[25]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 26]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[26]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [26]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 26]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[26]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [26]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[26]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[26]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[26]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 27]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[27]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [27]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 27]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[27]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [27]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[27]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[27]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[27]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 28]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[28]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [28]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 28]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[28]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [28]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[28]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[28]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[28]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 29]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[29]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [29]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 29]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[29]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [29]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[29]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[29]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[29]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 30]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[30]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [30]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 30]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[30]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [30]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[30]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[30]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[30]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 31]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[31]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [31]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 31]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[31]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [31]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[31]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[31]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[31]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 32]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[32]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [32]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 32]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[32]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [32]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[32]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[32]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[32]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 33]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[33]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [33]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 33]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[33]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [33]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[33]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[33]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[33]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 34]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[34]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [34]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 34]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[34]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [34]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[34]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[34]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[34]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 35]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[35]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [35]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 35]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[35]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [35]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[35]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[35]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[35]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 36]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[36]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [36]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 36]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[36]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [36]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[36]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[36]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[36]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 37]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[37]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [37]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 37]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[37]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [37]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[37]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[37]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[37]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 38]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[38]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [38]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 38]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[38]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [38]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[38]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[38]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[38]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 39]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[39]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [39]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 39]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[39]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [39]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[39]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[39]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[39]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 40]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[40]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [40]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 40]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[40]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [40]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[40]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[40]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[40]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 41]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[41]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [41]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 41]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[41]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [41]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[41]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[41]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[41]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 42]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[42]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [42]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 42]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[42]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [42]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[42]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[42]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[42]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 43]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[43]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [43]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 43]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[43]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [43]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[43]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[43]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[43]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 44]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[44]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [44]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 44]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[44]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [44]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[44]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[44]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[44]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 45]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[45]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [45]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 45]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[45]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [45]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[45]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[45]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[45]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 46]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[46]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [46]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 46]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[46]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [46]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[46]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[46]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[46]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 47]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[47]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [47]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 47]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[47]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [47]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[47]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[47]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[47]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 48]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[48]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [48]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 48]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[48]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [48]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[48]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[48]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[48]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 49]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[49]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [49]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 49]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[49]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [49]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[49]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[49]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[49]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 50]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[50]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [50]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 50]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[50]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [50]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[50]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[50]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[50]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 51]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[51]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [51]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 51]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[51]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [51]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[51]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[51]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[51]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 52]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[52]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [52]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 52]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[52]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [52]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[52]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[52]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[52]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 53]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[53]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [53]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 53]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[53]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [53]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[53]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[53]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[53]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 54]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[54]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [54]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 54]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[54]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [54]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[54]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[54]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[54]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 55]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[55]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [55]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 55]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[55]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [55]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[55]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[55]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[55]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 56]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[56]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [56]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 56]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[56]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [56]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[56]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[56]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[56]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 57]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[57]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [57]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 57]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[57]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [57]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[57]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[57]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[57]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 58]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[58]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [58]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 58]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[58]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [58]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[58]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[58]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[58]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 59]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[59]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [59]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 59]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[59]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [59]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[59]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[59]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[59]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 60]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[60]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [60]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 60]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[60]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [60]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[60]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[60]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[60]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 61]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[61]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [61]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 61]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[61]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [61]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[61]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[61]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[61]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 62]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[62]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [62]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 62]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[62]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [62]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[62]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[62]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[62]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 63]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[63]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [63]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 63]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[63]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [63]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[63]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[63]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[63]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 64]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[64]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [64]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 64]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[64]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [64]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[64]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[64]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[64]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 65]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[65]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [65]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 65]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[65]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [65]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[65]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[65]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[65]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 66]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[66]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [66]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 66]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[66]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [66]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[66]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[66]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[66]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 67]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[67]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [67]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 67]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[67]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [67]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[67]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[67]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[67]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 68]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[68]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [68]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 68]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[68]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [68]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[68]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[68]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[68]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 69]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[69]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [69]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 69]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[69]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [69]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[69]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[69]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[69]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 70]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[70]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [70]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 70]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[70]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [70]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[70]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[70]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[70]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 71]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[71]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [71]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 71]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[71]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [71]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[71]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[71]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[71]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 72]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[72]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [72]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 72]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[72]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [72]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[72]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[72]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[72]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 73]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[73]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [73]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 73]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[73]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [73]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[73]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[73]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[73]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 74]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[74]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [74]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 74]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[74]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [74]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[74]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[74]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[74]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 75]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[75]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [75]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 75]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[75]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [75]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[75]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[75]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[75]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 76]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[76]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [76]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 76]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[76]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [76]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[76]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[76]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[76]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 77]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[77]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [77]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 77]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[77]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [77]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[77]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[77]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[77]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 78]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[78]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [78]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 78]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[78]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [78]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[78]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[78]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[78]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 79]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[79]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [79]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 79]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[79]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [79]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[79]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[79]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[79]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 80]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[80]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [80]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 80]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[80]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [80]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[80]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[80]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[80]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 81]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[81]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [81]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 81]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[81]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [81]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[81]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[81]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[81]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 82]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[82]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [82]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 82]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[82]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [82]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[82]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[82]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[82]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[= 83]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[83]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor= [83]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[= 83]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[83]= |0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor= [83]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[83]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[83]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[83]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[0]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[0]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[0]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[0]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[0]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[0]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[1]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[1]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[1]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[1]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[1]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[1]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[1]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[0]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[0]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[0]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[0]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[0]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[0]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[0]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[0]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[0]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[2]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[2]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[2]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[2]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[2]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[2]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[2]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[3]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[3]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[3]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[3]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[3]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[3]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[3]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[4]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[4]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[4]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[4]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[4]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[4]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[4]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[5]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[5]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[5]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[5]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[5]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[5]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[5]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[1]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[1]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[1]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[1]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[1]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[1]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[1]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[1]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[1]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[6]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[6]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[6]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[6]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[6]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[6]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[6]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[7]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[7]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[7]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[7]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[7]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[7]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[7]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[8]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[8]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[8]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[8]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[8]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[8]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[8]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[9]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[9]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[9]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[9]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[9]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[9]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[9]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[2]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[2]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[2]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[2]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[2]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[2]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[2]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[2]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[2]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[10]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[10]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[10]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[10]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[10]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[10]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[10]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[11]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[11]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[11]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[11]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[11]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[11]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[11]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[12]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[12]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[12]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[12]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[12]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[12]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[12]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[13]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[13]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[13]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[13]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[13]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[13]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[13]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[14]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[14]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[14]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[14]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[14]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[14]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[14]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[15]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[15]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[15]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[15]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[15]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[15]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[15]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[16]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[16]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[16]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[16]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[16]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[16]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[16]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[17]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[17]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[17]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[17]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[17]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[17]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[17]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[18]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[18]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[18]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[18]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[18]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[18]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[18]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[19]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[19]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[19]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[19]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[19]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[19]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[19]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[20]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[20]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[20]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[20]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[20]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[20]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[20]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[21]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[21]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[21]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[21]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[21]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[21]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[21]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[22]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[22]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[22]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[22]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[22]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[22]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[22]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[3]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[3]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[3]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[3]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[3]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[3]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[3]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[3]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[3]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[23]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[23]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[23]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[23]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[23]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[23]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[23]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[24]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[24]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[24]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[24]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[24]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[24]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[24]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[24]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[24]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[24]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[25]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[25]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[25]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[25]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[25]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[25]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[25]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[25]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[25]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[25]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[26]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[26]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[26]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[26]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[26]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[26]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[26]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[26]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[26]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[26]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[4]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[4]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[4]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[4]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[4]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[4]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[4]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[4]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[4]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[27]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[27]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[27]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[27]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[27]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[27]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[27]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[27]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[27]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[27]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[28]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[28]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[28]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[28]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[28]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[28]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[28]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[28]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[28]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[28]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[29]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[29]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[29]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[29]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[29]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[29]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[29]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[29]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[29]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[29]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[30]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[30]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[30]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[30]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[30]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[30]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[30]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[30]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[30]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[30]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[5]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[5]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[5]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[5]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[5]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[5]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[5]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[5]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[5]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[31]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[31]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[31]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[31]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[31]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[31]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[31]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[31]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[31]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[31]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[32]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[32]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[32]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[32]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[32]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[32]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[32]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[32]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[32]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[32]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[33]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[33]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[33]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[33]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[33]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[33]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[33]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[33]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[33]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[33]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[34]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[34]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[34]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[34]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[34]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[34]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[34]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[34]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[34]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[34]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[35]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[35]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[35]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[35]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[35]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[35]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[35]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[35]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[35]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[35]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[36]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[36]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[36]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[36]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[36]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[36]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[36]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[36]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[36]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[36]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[37]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[37]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[37]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[37]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[37]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[37]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[37]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[37]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[37]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[37]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[38]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[38]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[38]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[38]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[38]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[38]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[38]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[38]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[38]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[38]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[39]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[39]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[39]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[39]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[39]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[39]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[39]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[39]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[39]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[39]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[40]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[40]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[40]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[40]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[40]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[40]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[40]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[40]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[40]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[40]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[41]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[41]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[41]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[41]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[41]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[41]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[41]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[41]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[41]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[41]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[42]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[42]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[42]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[42]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[42]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[42]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[42]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[42]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[42]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[42]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[43]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[43]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[43]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[43]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[43]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[43]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[43]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[43]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[43]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[43]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[6]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[6]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[6]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[6]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[6]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[6]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[6]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[6]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[6]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[44]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[44]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[44]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[44]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[44]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[44]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[44]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[44]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[44]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[44]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[45]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[45]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[45]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[45]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[45]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[45]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[45]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[45]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[45]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[45]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[46]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[46]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[46]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[46]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[46]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[46]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[46]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[46]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[46]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[46]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[47]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[47]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[47]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[47]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[47]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[47]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[47]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[47]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[47]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[47]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[7]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[7]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[7]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[7]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[7]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[7]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[7]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[7]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[7]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[48]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[48]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[48]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[48]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[48]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[48]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[48]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[48]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[48]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[48]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[49]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[49]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[49]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[49]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[49]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[49]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[49]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[49]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[49]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[49]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[50]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[50]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[50]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[50]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[50]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[50]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[50]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[50]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[50]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[50]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[51]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[51]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[51]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[51]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[51]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[51]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[51]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[51]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[51]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[51]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[8]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[8]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[8]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[8]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[8]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[8]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[8]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[8]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[8]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[52]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[52]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[52]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[52]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[52]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[52]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[52]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[52]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[52]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[52]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[53]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[53]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[53]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[53]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[53]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[53]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[53]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[53]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[53]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[53]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[54]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[54]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[54]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[54]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[54]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[54]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[54]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[54]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[54]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[54]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[55]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[55]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[55]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[55]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[55]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[55]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[55]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[55]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[55]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[55]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[56]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[56]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[56]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[56]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[56]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[56]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[56]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[56]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[56]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[56]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[57]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[57]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[57]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[57]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[57]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[57]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[57]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[57]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[57]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[57]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[58]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[58]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[58]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[58]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[58]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[58]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[58]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[58]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[58]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[58]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[59]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[59]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[59]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[59]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[59]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[59]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[59]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[59]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[59]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[59]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[60]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[60]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[60]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[60]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[60]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[60]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[60]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[60]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[60]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[60]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[61]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[61]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[61]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[61]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[61]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[61]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[61]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[61]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[61]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[61]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[62]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[62]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[62]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[62]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[62]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[62]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[62]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[62]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[62]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[62]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[63]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[63]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[63]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[63]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[63]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[63]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[63]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[63]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[63]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[63]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[64]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[64]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[64]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[64]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[64]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[64]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[64]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[64]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[64]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[64]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[9]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[9]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[9]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[9]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[9]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[9]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[9]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[9]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[9]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[65]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[65]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[65]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[65]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[65]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[65]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[65]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[65]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[65]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[65]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[66]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[66]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[66]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[66]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[66]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[66]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[66]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[66]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[66]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[66]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[67]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[67]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[67]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[67]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[67]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[67]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[67]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[67]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[67]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[67]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[68]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[68]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[68]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[68]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[68]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[68]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[68]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[68]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[68]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[68]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[10]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[10]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[10]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[10]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[10]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[10]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[10]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[10]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[10]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[69]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[69]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[69]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[69]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[69]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[69]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[69]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[69]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[69]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[69]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[70]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[70]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[70]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[70]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[70]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[70]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[70]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[70]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[70]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[70]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[71]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[71]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[71]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[71]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[71]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[71]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[71]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[71]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[71]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[71]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[72]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[72]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[72]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[72]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[72]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[72]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[72]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[72]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[72]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[72]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[11]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[11]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[11]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[11]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[11]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[11]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[11]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[11]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[11]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[73]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[73]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[73]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[73]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[73]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[73]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[73]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[73]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[73]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[73]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[74]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[74]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[74]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[74]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[74]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[74]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[74]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[74]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[74]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[74]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[75]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[75]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[75]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[75]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[75]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[75]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[75]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[75]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[75]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[75]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[76]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[76]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[76]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[76]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[76]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[76]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[76]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[76]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[76]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[76]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[77]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[77]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[77]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[77]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[77]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[77]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[77]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[77]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[77]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[77]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[78]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[78]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[78]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[78]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[78]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[78]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[78]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[78]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[78]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[78]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[79]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[79]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[79]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[79]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[79]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[79]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[79]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[79]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[79]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[79]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[80]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[80]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[80]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[80]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[80]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[80]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[80]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[80]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[80]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[80]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[81]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[81]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[81]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[81]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[81]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[81]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[81]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[81]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[81]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[81]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[82]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[82]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[82]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[82]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[82]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[82]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[82]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[82]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[82]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[82]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[83]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[83]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[83]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[83]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[83]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[83]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[83]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[83]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[83]= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[83]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[83]|0x0 + #gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData|L"SocketCommonRcConfi= g"|4402ca38-808f-4279-bcec-5baf8d59092f|0x00 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData|{0x0} + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmcfgBase|0x3 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmcfgSize|0x2 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmiohBase|0x0 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmiohSize|0x0 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.IsocEn|0x2 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.NumaEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.LockStep|0x0 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MirrorMode|0x0 + #gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData|L"SocketMpLinkConfig"|2= b9b22de-2ad4-4abc-957d-5f18c504a05c|0x00 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData|{0} + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.DegradePrecedence|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.QpiLinkSpeedMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.QpiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLinkL0pEn|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLinkL1En|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiFailoverEn|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.IoDcMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.DirectoryModeEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.SncEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.XptPrefetchEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiPrefetchEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.RdCurForXptPrefetchEn|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLinkVnaOverride|0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiCrcMode|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLbEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.LegacyVgaSoc|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.LegacyVgaStack|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.MmioP2pDis|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.QpiCpuSktHotPlugEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiCpuSktHotPlugTopology= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiSkuMismatchCheck|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.DebugPrintLevel|0xf + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.IrqThreshold|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.BusRatio[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.BusRatio[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P0KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P0KtiLinkVnaOverride= |0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P0KtiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P1KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P1KtiLinkVnaOverride= |0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P1KtiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P2KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P2KtiLinkVnaOverride= |0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P2KtiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P0KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P0KtiLinkVnaOverride= |0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P0KtiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P1KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P1KtiLinkVnaOverride= |0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P1KtiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P2KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P2KtiLinkVnaOverride= |0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P2KtiLinkSpeed|0x2 + #gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData|L"SocketMemoryConfig"|9= 8cf19ed-4109-4681-b79d-9196757c7824|0x00 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData|{0x0} + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Srat|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SratMemoryHotPlug|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SratCpuHotPlug|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EnforcePOR|0x3 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.pprType|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.pprErrInjTest|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrFreqLimit|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.imcBclk|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.promoteMrcWarnings|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.promoteWarnings|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.haltOnMemErr|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MultiThreaded|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EccSupport|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.spdCrcCheck|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.logParsing|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.lrdimmModuleDelay|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.HwMemTest|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MemTestLoops|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrMemoryType|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RankMargin|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EnableBacksideRMT|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EnableBacksideCMDRMT|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.rmtPatternLength|0x7fff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.rmtPatternLengthExt|0x7f= ff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.perbitmargin|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AttemptFastBoot|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AttemptFastBootCold|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MemTestOnFastBoot|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RmtOnColdFastBoot|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.bdatEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleEnDDRT|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleEn|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.allowCorrectableError|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.WrCRC|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.dimmIsolation|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.WritePreamble|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ReadPreamble|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleSeedLow|0xa02b + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleSeedHigh|0xd395 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ADREn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_12|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.check_pm_sts|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.check_platform_detect|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CustomRefreshRateEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CustomRefreshRate|0x14 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.mcBgfThreshold|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.dllResetTestLoops|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.oppReadInWmm|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.normOppInterval|0x400 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.caParity|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.smbSpeed|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.mrcRepeatTest|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memFlowsExt|0xffffffff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memFlows|0xffffffff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.rankMaskEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Blockgnt2cmd1cyc|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Disddrtopprd|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck4ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck5ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck6ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck7ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PagePolicy|0x3 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DutyCycleTraining|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.readVrefCenter|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.eyeDiagram|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.turnaroundOpt|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.oneRankTimingMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.pda|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.wrVrefCenter|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.thermalthrottlingsupport= |0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.thermalmemtrip|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memhotSupport|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CkeProgramming|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PkgcSrefEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CkeIdleTimer|0x14 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ApdEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PpdEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrtCkeEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OppSrefEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrtSrefEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MdllOffEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CkMode|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.XMPMode|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.XMPMode|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.XMPMode|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Vdd|0x4b0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.commandTiming|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tREFI|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tCAS|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRP|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRCD|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRAS|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tWR|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRFC|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRRD|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRTP|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tWTR|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tFAW|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRC|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tCWL|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.volMemMode|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memInterleaveGran1LM|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ImcInterleaving|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ChannelInterleaving|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RankInterleaving|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SocketInterleaveBelow4GB= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_1|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_7|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_2|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_3|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_4|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_5|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.FastGoConfig|0x6 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ADRDataSaveMode|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.eraseArmNVDIMMS|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.restoreNVDIMMS|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetTxDq|0x64 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetRxDq|0x64 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetTxVref|0x64 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetRxVref|0x64 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetCmdAll|0x64 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetCmdVref|0x64 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetCtlAll|0x64 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.turnaroundOptDdrt|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NgnEccExitCorr|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NgnArsPublish|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NgnAveragePower|0x3A98 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NgnThrottleTemp|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AppDirectMemoryHole|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.LatchSystemShutdownState= |0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EliminateDirectoryInFarM= emory|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NvmdimmPowerCyclePolicy|= 0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Force1ChWayFM|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DisableDirForAppDirect|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NvmMediaStatusException|= 0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.LsxImplementation|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NvdimmSmbusMaxAccessTime= |0x15E + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.NvdimmSmbusReleaseDelay|= 0x96 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.TrfcPerfEnable|0x64 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCondition|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCondVdd|0x4EC + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCondTwr|0xA + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCondTrefi|0x3C= F0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestCondPause|0x18= 6A0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OffsetRecEn|0x64 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RcvenAve|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.allowCorrectableMemTestE= rror|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PatrolErrorDowngradeEn|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdvMemTestRetryAfterRepa= ir|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseAllDIMMs|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[0]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[1]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[2]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[3]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[4]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[5]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[6]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[7]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[8]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[9]|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[10]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[11]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[12]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[13]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[14]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[15]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[16]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[17]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[18]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[19]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[20]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[21]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[22]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[23]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsad0|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirror|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PartialMirrorUefi|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PartialMirrorUefiPercent= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RankSparing|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.multiSparingRanks|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DemandScrubMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.spareErrTh|0x7fff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.leakyBktLo|0x28 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.leakyBktHi|0x29 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SddcPlusOneEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SddcPlusOneEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ADDDCEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdddcErrInjEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DieSparing|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved1|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PatrolScrub|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PatrolScrubDuration|0x18 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PatrolScrubAddrMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_11|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoMaxNodeInterleave|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoHighAddressStartBitPo= sition|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoLowMemChannel|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoCfgMask2LM|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_13|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.mdllSden|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.BwLimitTfOvrd|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DramRaplExtendedRange|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CmsEnableDramPm|0x1 + #gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData|L"SocketPowerM= anagementConfig"|A1047342-BDBA-4DAE-A67A-40979B65C7F8|0x00 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData|{0x0} + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SPTWorkaround|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.AcpiS3Enable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.AcpiS4Enable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorHWPMEn= able|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorHWPMIn= terrupt|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorEPPEna= ble|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorEppPro= file|0x55 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorAPSroc= keting|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorScalab= ility|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorRaplPr= ioritization|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.WFRWAEnable|0x2 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.UFSDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.AvxIccpLevel|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorEistEn= able|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ConfigTDPLevel|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PStateDomain|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorEistPs= dFunc|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorSingle= PCTLEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorSPD|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.BootPState|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorConfig= urePbf|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EETurboDisable|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EnableXe|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.OverclockingLoc= k|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Ratio[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Cores[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Ratio[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Cores[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Ratio[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Cores[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Ratio[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Cores[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Ratio[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Cores[4]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Ratio[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Cores[5]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Ratio[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Cores[6]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Ratio[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimit= Cores[7]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.LOT26UnusedVrPo= werDownEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorAutono= mousCstateEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.C6Enable|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorC1eEna= ble|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.OSCx|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PackageCState|0= xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.C2C3TT|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.DynamicL1|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PkgCLatNeg|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.LTRSwInput|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCt= rlValid[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCt= rlMultiplier[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCt= rlValue[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCt= rlValid[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCt= rlMultiplier[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCt= rlValue[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCt= rlValid[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCt= rlMultiplier[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCt= rlValue[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TStateEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.OnDieThermalThr= ottling|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProchotLock|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EnableProcHot|0= x3 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EnableThermalMo= nitor|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProchotResponse= Ratio|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TCCActivationOf= fset|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SAPMControl|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PwrPerfTuning|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorOutofB= andAlternateEPB|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.AltEngPerfBIAS|= 0x7 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PwrPerfSwitch|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.WorkLdConfig|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EngAvgTimeWdw1|= 0x17 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0TtlTimeLow1|0= x23 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0TtlTimeHigh1|= 0x3a + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CurrentConfig|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CurrentLimit|0x= 438 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PpcccLock|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PkgCstEntryValC= tl|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLatVld|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLatOvrd|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLatMult|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLatVal|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSnpLatVld|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSnpLatOvrd|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSnpLatMult|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSnpLatVal|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.UncrPerfPlmtOvr= dEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EetOverrideEn|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.IoBwPlmtOvrdEn|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.IomApmOvrdEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.QpiApmOvrdEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPlimitDiffe= rential|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPLimitClipC= |0x1f + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPLmtThshld|= 0xf + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPLimitEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.FastRaplDutyCyc= le|0x40 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboPowerLimit= Lock|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit1En|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit1Powe= r|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit1Time= |0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit2En|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit2Powe= r|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit2Time= |0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PmaxOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti0In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti1In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti2In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio0In[0]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio1In[0]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio2In[0]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio3In[0]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio4In[0]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio5In[0]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti0In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti1In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti2In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio0In[1]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio1In[1]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio2In[1]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio3In[1]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio4In[1]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio5In[1]|0= x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio0PkgcClkGate= Dis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio1PkgcClkGate= Dis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio2PkgcClkGate= Dis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01PkgcClkGat= eDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23PkgcClkGat= eDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1PkgcClkGateD= is[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0PkgcClkGateD= is[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01pllOffEna[= 0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23pllOffEna[= 0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0pllOffEna[0]|= 0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P1pllOffEna[0]|= 0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P2pllOffEna[0]|= 0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0pllOffEna[0]= |0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1pllOffEna[0]= |0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SetvidDecayDisa= ble[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SapmCtlLock[0]|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio0PkgcClkGate= Dis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio1PkgcClkGate= Dis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio2PkgcClkGate= Dis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01PkgcClkGat= eDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23PkgcClkGat= eDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1PkgcClkGateD= is[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0PkgcClkGateD= is[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01pllOffEna[= 1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23pllOffEna[= 1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0pllOffEna[1]|= 0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P1pllOffEna[1]|= 0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P2pllOffEna[1]|= 0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0pllOffEna[1]= |0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1pllOffEna[1]= |0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SetvidDecayDisa= ble[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SapmCtlLock[1]|= 0x0 + #gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData|L"SocketProcesso= rCoreConfig"|07013588-C789-4E12-A7C3-88FAFAE79F7C|0x00 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData|{0x0} + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PchTraceHubEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorHyperThr= eadingDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IedSize|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IedTraceSize|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.TsegSize|0x5 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.AllowMixedPowerOn= CpuRatio|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CheckCpuBist|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ThreeStrikeTimer|= 0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.FastStringEnable|= 0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MachineCheckEnabl= e|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CpuidMaxValue|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ExecuteDisableBit= |0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorLtsxEnab= le|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorVmxEnabl= e|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorSmxEnabl= e|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.LockChipset|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.BiosAcmErrorReset= |0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorMsrLockC= ontrol|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PpinControl|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DebugInterface|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MlcStreamerPrefet= cherEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MlcSpatialPrefetc= herEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DCUStreamerPrefet= cherEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DCUIPPrefetcherEn= able|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DCUModeSelection|= 0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.BspSelection|0xff + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.Reserved2|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorX2apic|0= x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ForceX2ApicIds|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.AesEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ForcePhysicalMode= Enable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorVirtualW= ireMode|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PCIeDownStreamPEC= IWrite|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PeciInTrustContro= lBit|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IioLlcWaysMask|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ExpandedIioLlcWay= sMask|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.RemoteWaysMask|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.QlruCfgMask_Hi|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.QlruCfgMask_Lo|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.TargetedSmi|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.eSmmSaveState|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.SmbusErrorRecover= y|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MonitorMwaitEnabl= ed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CoreDisableMask[0= ]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IotEn[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMinWay[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMaxTorEntry[0= ]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CoreDisableMask[1= ]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IotEn[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMinWay[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMaxTorEntry[1= ]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorFlexible= RatioOverrideEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorFlexible= Ratio|0x17 --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Tue, 11 May 2021 02:49:06 -0700 IronPort-SDR: TDVF4rXI3BIzW9HgdQBfY/kbW68/erj6KcQFK2PLsFZAEUZJTMtwI+55I3vvJAnXhTFnNylgtX lzE+378l3/Pg== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="199469685" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="199469685" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:57 -0700 IronPort-SDR: J5FOq5mIIZUcuPGOOmZLWXLq+/GRjQh1pIUI7qYgz0nuMxY6RVRtC1qKjuLNyNv+vn4XKv+KCk tC/PG5Ay3Pyw== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436574046" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:56 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 16/18] PurleyOpenBoardPkg: Add BoardMtOlympus Date: Tue, 11 May 2021 02:48:24 -0700 Message-Id: <20210511094826.12495-17-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: ZUEYuLF7aQPMJtQfPK4Ngz0ex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726548; bh=fM4SkF7mOS78ESZ7sYganvjKaO6p+Qp+35g6PcUfSt8=; h=Cc:Date:From:Reply-To:Subject:To; b=VoO1cXutfFDKnodek0/LMDJXrFZppGLcP8FJIl2iETaIRqK7KHQRLcyE3+VRypt+WP8 NMFx5z+OsdPip+hgXPeslzVUm6q4b4xNroSuyCsqJUBYAiXwk+4ob3eKLfr7h02D98pVU cv65Eqh4dtMuuRLpyw1YGNPmPM6MY1DiYvw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../BasePlatformHookLib/BasePlatformHookLib.c | 292 +++++++++ .../BasePlatformHookLib.inf | 36 + .../BoardAcpiLib/DxeBoardAcpiTableLib.c | 35 + .../BoardAcpiLib/DxeBoardAcpiTableLib.inf | 40 ++ .../BoardAcpiLib/DxeMtOlympusAcpiTableLib.c | 52 ++ .../BoardAcpiLib/SmmBoardAcpiEnableLib.c | 61 ++ .../BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 41 ++ .../BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c | 36 + .../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 119 ++++ .../Library/BoardInitLib/AllLanesEparam.c | 43 ++ .../Library/BoardInitLib/GpioTable.c | 296 +++++++++ .../Library/BoardInitLib/IioBifur.c | 88 +++ .../BoardInitLib/PeiBoardInitPostMemLib.c | 45 ++ .../BoardInitLib/PeiBoardInitPostMemLib.inf | 37 ++ .../BoardInitLib/PeiBoardInitPreMemLib.c | 111 ++++ .../BoardInitLib/PeiBoardInitPreMemLib.inf | 69 ++ .../Library/BoardInitLib/PeiMtOlympusDetect.c | 27 + .../BoardInitLib/PeiMtOlympusInitLib.h | 17 + .../BoardInitLib/PeiMtOlympusInitPostMemLib.c | 85 +++ .../BoardInitLib/PeiMtOlympusInitPreMemLib.c | 614 ++++++++++++++++++ .../Library/BoardInitLib/UsbOC.c | 45 ++ 21 files changed, 2189 insertions(+) create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BasePlatformHookLib/BasePlatformHookLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BasePlatformHookLib/BasePlatformHookLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardAcpiLib/DxeBoardAcpiTableLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardAcpiLib/DxeBoardAcpiTableLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardAcpiLib/SmmBoardAcpiEnableLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardAcpiLib/SmmBoardAcpiEnableLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardAcpiLib/SmmSiliconAcpiEnableLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/AllLanesEparam.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/GpioTable.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/IioBifur.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/PeiBoardInitPostMemLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/PeiBoardInitPostMemLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/PeiBoardInitPreMemLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/PeiBoardInitPreMemLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/PeiMtOlympusDetect.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/PeiMtOlympusInitLib.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/PeiMtOlympusInitPostMemLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/PeiMtOlympusInitPreMemLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Librar= y/BoardInitLib/UsbOC.c diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BaseP= latformHookLib/BasePlatformHookLib.c b/Platform/Intel/PurleyOpenBoardPkg/Bo= ardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c new file mode 100644 index 0000000000..4c539de755 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatform= HookLib/BasePlatformHookLib.c @@ -0,0 +1,292 @@ +/** @file + +Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#define R_ICH_IOPORT_PCI_INDEX 0xCF8 +#define R_ICH_IOPORT_PCI_DATA 0xCFC +#define R_ICH_LPC_IO_DEC 0x80 + +#define PCI_DEVICE_NUMBER_ICH_LPC 31 +#define PCI_FUNCTION_NUMBER_ICH_LPC 0 + +#define PCI_CF8_ADDR(Bus, Dev, Func, Off) \ + (((Off) & 0xFF) | (((Func) & 0x07) << 8) | (((Dev) & 0x1F) << 11= ) | (((Bus) & 0xFF) << 16) | (1 << 31)) +#define ICH_LPC_CF8_ADDR(Offset) PCI_CF8_ADDR(0, PCI_DEVICE_NUMBER_ICH_= LPC, PCI_FUNCTION_NUMBER_ICH_LPC, Offset) + +#include "SioRegs.h" + +#include +#include + +// +// --------------------------------------------- +// UART Register Offsets +// --------------------------------------------- +// +#define BAUD_LOW_OFFSET 0x00 +#define BAUD_HIGH_OFFSET 0x01 +#define IER_OFFSET 0x01 +#define LCR_SHADOW_OFFSET 0x01 +#define FCR_SHADOW_OFFSET 0x02 +#define IR_CONTROL_OFFSET 0x02 +#define FCR_OFFSET 0x02 +#define EIR_OFFSET 0x02 +#define BSR_OFFSET 0x03 +#define LCR_OFFSET 0x03 +#define MCR_OFFSET 0x04 +#define LSR_OFFSET 0x05 +#define MSR_OFFSET 0x06 + +// +// --------------------------------------------- +// UART Register Bit Defines +// --------------------------------------------- +// +#define LSR_TXRDY 0x20 +#define LSR_RXDA 0x01 +#define DLAB 0x01 + +#define UART_DATA 8 +#define UART_STOP 1 +#define UART_PARITY 0 +#define UART_BREAK_SET 0 + +UINT16 gComBase =3D 0x3f8; +UINTN gBps =3D 115200; +UINT8 gData =3D 8; +UINT8 gStop =3D 1; +UINT8 gParity =3D 0; +UINT8 gBreakSet =3D 0; + + +/** + + Read AHB register. + + @param RegIndex: register index. + + @retval value of register. + +**/ +UINT32 +ReadAHBDword( + UINT32 RegIndex +){ + UINT8 bValue; + UINT32 rdValue =3D 0; + + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, SIO_SMI); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (SIO_INDEX_PORT, 0x30); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, 1); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (SIO_INDEX_PORT, 0xf8); + bValue =3D IoRead8(SIO_DATA_PORT); + bValue &=3D 0xfc; + bValue |=3D 2; // 4 byte window. + IoWrite8 (SIO_DATA_PORT, bValue); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (SIO_INDEX_PORT, 0xf0); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 24)& 0xff)); + + IoWrite8 (SIO_INDEX_PORT, 0xf1); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 16)& 0xff)); + + IoWrite8 (SIO_INDEX_PORT, 0xf2); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 8) & 0xff)); + + IoWrite8 (SIO_INDEX_PORT, 0xf3); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex )& 0xff)); + + // trigger read + IoWrite8 (SIO_INDEX_PORT, 0xfe); + IoRead8 (SIO_DATA_PORT); + + + IoWrite8 (SIO_INDEX_PORT, 0xf4); + rdValue +=3D IoRead8 (SIO_DATA_PORT); + rdValue <<=3D 8; + + IoWrite8 (SIO_INDEX_PORT, 0xf5); + rdValue +=3D IoRead8 (SIO_DATA_PORT); + rdValue <<=3D 8; + + IoWrite8 (SIO_INDEX_PORT, 0xf6); + rdValue +=3D IoRead8 (SIO_DATA_PORT); + rdValue <<=3D 8; + + IoWrite8 (SIO_INDEX_PORT, 0xf7); + rdValue +=3D IoRead8 (SIO_DATA_PORT); + + + return rdValue; + +} + + +/** + + GC_TODO: add routine description + + @param Exist - GC_TODO: add arg description + + @retval RETURN_SUCCESS - GC_TODO: add retval description + +**/ +UINT32 +IsSioExist ( + VOID +) +{ + UINT32 SioExist; + + SioExist =3D 0; + + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (SIO_DATA_PORT, SIO_UART1); + + if (IoRead8 (SIO_DATA_PORT) =3D=3D SIO_UART1) { + SioExist |=3D EXIST; + } + + IoWrite8 (SIO_INDEX_PORT, SIO_LOCK); + + return SioExist; +} + +/** + + GC_TODO: add routine description + + @param None + + @retval None + +**/ +VOID +InitializeSio ( + VOID + ) +{ + + UINT32 SioExist; + UINT32 SioEnable; + UINT32 Decode; + UINT32 Enable; + + // + // Enable LPC decode + // Set COMA/COMB base + // + + Decode =3D ((V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA) | (V_PCH_L= PC_IOD_COMB_2F8 << N_PCH_LPC_IOD_COMB)); + Enable =3D ( B_PCH_LPC_IOE_ME2 | B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_ME1= \ + | B_PCH_LPC_IOE_KE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE); + IoWrite32 (R_ICH_IOPORT_PCI_INDEX, (UINT32) (ICH_LPC_CF8_ADDR (R_ICH_L= PC_IO_DEC))); + + IoWrite32 (R_ICH_IOPORT_PCI_DATA, Decode | (Enable << 16)); + + MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_PCR_DMI_LPCIOD), (UINT16)D= ecode); + MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_PCR_DMI_LPCIOE), (UINT16)E= nable); + SioExist =3D IsSioExist (); + SioEnable =3D SioExist; + + if (SioEnable =3D=3D EXIST) { + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + + // + //COM1 + // + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (SIO_DATA_PORT, SIO_UART1); + + // + //active COM1 + // + IoWrite8 (SIO_INDEX_PORT, ACTIVATE); + IoWrite8 (SIO_DATA_PORT, 1); + + IoWrite8 (SIO_INDEX_PORT, SIO_LOCK); + + } +} + +/** + Performs platform specific initialization required for the CPU to access + the hardware associated with a SerialPortLib instance. This function do= es + not initialize the serial port hardware itself. Instead, it initializes + hardware devices that are required for the CPU to access the serial port + hardware. This function may be called more than once. + + @retval RETURN_SUCCESS The platform specific initialization succee= ded. + @retval RETURN_DEVICE_ERROR The platform specific initialization could = not be completed. + +**/ +RETURN_STATUS +EFIAPI +PlatformHookSerialPortInitialize ( + VOID + ) +{ + UINTN Divisor; + UINT8 OutputData; + UINT8 Data; + + InitializeSio(); + // + // Some init is done by the platform status code initialization. + // + // + // Map 5..8 to 0..3 + // + Data =3D (UINT8) (gData - (UINT8) 5); + + // + // Calculate divisor for baud generator + // + Divisor =3D 115200 / gBps; + + // + // Set communications format + // + OutputData =3D (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3= ) | ((gStop << 2) | Data)))); + IoWrite8 (gComBase + LCR_OFFSET, OutputData); + + // + // Configure baud rate + // + IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8)); + IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff)); + + // + // Switch back to bank 0 + // + OutputData =3D (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << = 3) | ((gStop << 2) | Data)))); + IoWrite8 (gComBase + LCR_OFFSET, OutputData); + + return RETURN_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BaseP= latformHookLib/BasePlatformHookLib.inf b/Platform/Intel/PurleyOpenBoardPkg/= BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.inf new file mode 100644 index 0000000000..a645eb5ae7 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatform= HookLib/BasePlatformHookLib.inf @@ -0,0 +1,36 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BasePlatformHookLib + FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963D + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PlatformHookLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[FixedPcd] + +[Sources] + BasePlatformHookLib.c diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= AcpiLib/DxeBoardAcpiTableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtO= lympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c new file mode 100644 index 0000000000..ff497540de --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.c @@ -0,0 +1,35 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ); + +EFI_STATUS +EFIAPI +BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + MtOlympusBoardUpdateAcpiTable (Table, Version); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= AcpiLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/PurleyOpenBoardPkg/BoardM= tOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf new file mode 100644 index 0000000000..2b315028dc --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.inf @@ -0,0 +1,40 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D DxeBoardAcpiTableLib + FILE_GUID =3D 6562E0AE-90D8-4D41-8C97-81286B4BE7D2 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D BoardAcpiTableLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Pcd] + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress + +[Sources] + DxeMtOlympusAcpiTableLib.c + DxeBoardAcpiTableLib.c diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= AcpiLib/DxeMtOlympusAcpiTableLib.c b/Platform/Intel/PurleyOpenBoardPkg/Boar= dMtOlympus/Library/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c new file mode 100644 index 0000000000..297de88047 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib= /DxeMtOlympusAcpiTableLib.c @@ -0,0 +1,52 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED BIOS_ACPI_PARAM *mGlobalNvsArea; + +VOID +MtOlympusUpdateGlobalNvs ( + VOID + ) +{ + + // + // Allocate and initialize the NVS area for SMM and ASL communication. + // + mGlobalNvsArea =3D (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress); + + // + // Update global NVS area for ASL and SMM init code to use + // + + +} + +EFI_STATUS +EFIAPI +MtOlympusBoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + if (Table->Signature =3D=3D EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTI= ON_TABLE_SIGNATURE) { + MtOlympusUpdateGlobalNvs (); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= AcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMt= Olympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c new file mode 100644 index 0000000000..b2a82560b8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.c @@ -0,0 +1,61 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +MtOlympusBoardDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +BoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return MtOlympusBoardEnableAcpi (EnableSci); +} + +EFI_STATUS +EFIAPI +BoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return MtOlympusBoardDisableAcpi (DisableSci); +} + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= AcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/PurleyOpenBoardPkg/Board= MtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf new file mode 100644 index 0000000000..42c50b69c7 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.inf @@ -0,0 +1,41 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmBoardAcpiEnableLib + FILE_GUID =3D 549E69AE-D3B3-485B-9C17-AF16E20A58AD + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D BoardAcpiEnableLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + MmPciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Sources] + SmmMtOlympusAcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmBoardAcpiEnableLib.c + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= AcpiLib/SmmMtOlympusAcpiEnableLib.c b/Platform/Intel/PurleyOpenBoardPkg/Boa= rdMtOlympus/Library/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c new file mode 100644 index 0000000000..b97b2992cb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib= /SmmMtOlympusAcpiEnableLib.c @@ -0,0 +1,36 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MtOlympusBoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= AcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/PurleyOpenBoardPkg/Board= MtOlympus/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c new file mode 100644 index 0000000000..ff803aa5ce --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib= /SmmSiliconAcpiEnableLib.c @@ -0,0 +1,119 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Clear Port 80h + + SMI handler to enable ACPI mode + + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI + + Disables the SW SMI Timer. + ACPI events are disabled and ACPI event status is cleared. + SCI mode is then enabled. + + Clear SLP SMI status + Enable SLP SMI + + Disable SW SMI Timer + + Clear all ACPI event status and disable all ACPI events + + Disable PM sources except power button + Clear status bits + + Disable GPE0 sources + Clear status bits + + Disable GPE1 sources + Clear status bits + + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + + Enable SCI +**/ +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + UINT32 SmiEn; + UINT16 Pm1En; + UINT16 Pm1Cnt; + UINT16 PchPmBase; + + // + // Init Power Management I/O Base aka ACPI Base + // + PchAcpiBaseGet (&PchPmBase); + + SmiEn =3D IoRead32 (PchPmBase + R_PCH_SMI_EN); + + // + // Disable SW SMI Timer and legacy USB + // + SmiEn &=3D ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB | B_PCH_SM= I_EN_LEGACY_USB2); + + // + // And enable SMI on write to B_PCH_ACPI_PM1_CNT_SLP_EN when SLP_TYP is = written + // + SmiEn |=3D B_PCH_SMI_EN_ON_SLP_EN; + IoWrite32 (PchPmBase + R_PCH_SMI_EN, SmiEn); + + // + // Disable PM sources except power button + // + Pm1En =3D B_PCH_ACPI_PM1_EN_PWRBTN; + IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_EN, Pm1En); + + // + // Enable SCI + // + Pm1Cnt =3D IoRead16 (PchPmBase + R_PCH_ACPI_PM1_CNT); + Pm1Cnt |=3D B_PCH_ACPI_PM1_CNT_SCI_EN; + IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + UINT16 Pm1Cnt; + UINT16 PchPmBase; + + // + // Init Power Management I/O Base aka ACPI Base + // + PchAcpiBaseGet (&PchPmBase); + + Pm1Cnt =3D IoRead16 (PchPmBase + R_PCH_ACPI_PM1_CNT); + + // + // Disable SCI + // + Pm1Cnt &=3D ~B_PCH_ACPI_PM1_CNT_SCI_EN; + + IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/AllLanesEparam.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus= /Library/BoardInitLib/AllLanesEparam.c new file mode 100644 index 0000000000..a245721277 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /AllLanesEparam.c @@ -0,0 +1,43 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MINIBIOS_BUILD +#include +#include +#include +#include +#endif + +#include + +#define SPEED_REC_96GT 0 +#define SPEED_REC_104GT 1 +#define ADAPTIVE_CTLE 0x3f + +#pragma pack(1) + +ALL_LANES_EPARAM_LINK_INFO KtiMtOlympusAllLanesEparamTable[] =3D { + // + // SocketID, Freq, Link, TXEQL, CTLEPEAK + // + + // + // Socket 0 + // + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2E39343F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2F39353F, ADAPTIVE_CTLE}, + + // + // Socket 1 + // + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2D37353F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2F3A343F, ADAPTIVE_CTLE} +}; + +#pragma pack() + +UINT32 KtiMtOlympusAllLanesEparamTableSize =3D sizeof(KtiMtOlympusAllLanes= EparamTable); diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/GpioTable.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Libr= ary/BoardInitLib/GpioTable.c new file mode 100644 index 0000000000..21d83a0c02 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /GpioTable.c @@ -0,0 +1,296 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#include +#include +#include + +#include +#include +#include + +GPIO_INIT_CONFIG mGpioTableMicrosoftWcs[] =3D +{ +// Group A + {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInIn= v, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone }},//GPP_A_0_LPC= _RCIN_N_ESPI_ALERT1_N + { GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInO= ut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_1_L= AD_0_ESPI_IO_0 + { GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInO= ut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_2_L= AD_1_ESPI_IO_1 + { GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInO= ut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_3_L= AD_2_ESPI_IO_2 + { GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInO= ut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_4_L= AD_3_ESPI_IO_3 + { GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_5_LPC= _LFRAME_N_ESPI_CS0_N + { GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_6_IRQ_= LPC_SERIRQ_ESPI_CS1_N + { GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_7_IRQ_= LPC_PIRQA_N_ESPI_ALERT0_N + { GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_8_FM_L= PC_CLKRUN_N + { GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_9_CLK= _24M_66M_LPC0_ESPI + { GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_10_TP_PCH_G= PP_A_10 + { GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_11_FM= _LPC_PME_N + { GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv= , GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_A_12_= IRQ_PCH_SCI_WHEA_N + { GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_A_13_FM_EU= P_LOT6_N MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_A14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_14_ESPI_RES= ET_N + { GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_15_SUSAC= K_N + { GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_16_TP_PC= H_GPP_A_16 + { GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_17_FM_KT= I_SLOW_MODE_N + { GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_A_18_FM_= BIOS_ADV_FUNCTIONS + //{GPIO_SKL_H_GPP_A19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirI= n, GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_A_19_= FM_ME_RCVR_N + { GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_A_20_TP_PC= H_GPP_A_20 MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_21_TP_PC= H_GPP_A_21 + { GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_22_TP_PC= H_GPP_A_22 + { GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_23_TP_PC= H_GPP_A_23 + // Group B + { GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_0_COR= E_VID_0 + { GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_1_COR= E_VID_1 + { GPIO_SKL_H_GPP_B2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_2_VRAL= ERT_N + { GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_3_FM_QAT_= ENABLE_N + { GPIO_SKL_H_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_4_TP_PCH_= GPP_B_4 + { GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_5_PU_PCH_= GPP_B_5 + { GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_6_PU_PC= H_GPP_B_6 + { GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_7_PU_PC= H_GPP_B_7 + { GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_8_PU_PCH_= GPP_B_8 + { GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_9_PU_PCH_= GPP_B_9 + { GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_10_PU_PC= H_GPP_B_10 + { GPIO_SKL_H_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_11_FM_PMBUS= _ALERT_B_EN + { GPIO_SKL_H_GPP_B12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_12_TP_SLP_= S0_N + { GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_13_R= ST_PLTRST_N + { GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOu= t, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_14_FM_= PCH_BIOS_RCVR_SPKR + { GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_15_FM_CP= U_ERR0_LVT3_N + { GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_16_FM_CP= U_ERR1_LVT3_N + { GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_17_TP_PCH_G= PP_B_17 + { GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_B_18_PU_NO= _REBOOT MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_19_TP_PCH_G= PP_B_19 + { GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_20_FM_BI= OS_POST_CMPLT_N + { GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_21_TP_LINK_= WIDTH_ID5 + { GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_22_FM_PCH_B= OOT_BIOS_DEVICE + { GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_B_23_F= M_PCH_BMC_THERMTRIP_EXI_STRAP_N + // Group C + { GPIO_SKL_H_GPP_C0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_0_SMB= _HOST_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_C1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInO= ut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_1_S= MB_HOST_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_2_PU_PCH_= TLS_ENABLE_STRAP + { GPIO_SKL_H_GPP_C3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInO= ut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_3_S= MB_SMLINK0_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_C4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInO= ut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_4_S= MB_SMLINK0_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInO= ut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_C_= 5_IRQ_SML0_ALERT_N MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_C6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInO= ut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_6_S= MB_PMBUS_SML1_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_C7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInO= ut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_7_S= MB_PMBUS_SML1_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_8_FM_PA= SSWORD_CLEAR_N + { GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_9_FM_MFG_= MODE + { GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_10_FM_PCH= _SATA_RAID_KEY + { GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_11_TP_= FP_AUD_DETECT_N + { GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_12_FM_BO= ARD_REV_ID0 + { GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_13_FM_BO= ARD_REV_ID1 + { GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone = } },//GPP_C_14_FM_BMC_PCH_SCI_LPC_N + { GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_15_TP_= LINK_WIDTH_ID0 + { GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_16_TP_= LINK_WIDTH_ID1 + { GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_17_TP_= LINK_WIDTH_ID2 + { GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_18_TP_LIN= K_WIDTH_ID3 + { GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_19_TP_LINK= _WIDTH_ID4 , MSFT_WCS_override for AVA Slot3_PRSNT_N_2_4 + { GPIO_SKL_H_GPP_C20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_20_FM_TH= ROTTLE_N + { GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_21_RST_PC= H_MIC_MUX_N + { GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone = } },//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N + { GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone = } },//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N + // Group D + { GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutDefault, GpioIntLevel | GpioIntNmi, GpioResetNormal, GpioTermNone }= },//GPP_D_0_IRQ_BMC_PCH_NMI + { GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, G= pioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_1_FP_PWR_LED= _N + { GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_2_FM_TBT_FO= RCE_PWR + { GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_3 [PVDD= Q_KLM_PINALERT_N] + { GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_4_FM_PLD_= PCH_DATA + { GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_5_TP_PCH_= GPP_D_5 + { GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_6_TP_PCH_GPP= _D_6 + { GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_7_TP_PCH_GPP= _D_7 + { GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_8_TP_PCH_GPP= _D_8 + { GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_9_TP_PCH_GPP= _D_9 + { GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_10_FM_M2= _SSD_DEVSLP , MSFT_WCS_override for AVA Slot3_PRSNT_N_2_6 + { GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_11_FM_LA_TR= IGGER_N + { GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_12_SGPIO= _SSATA_DATA1 + { GPIO_SKL_H_GPP_D13, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_13_S= MB_SMLINK5_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_D14, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn= Out, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_14= _SMB_SMLINK5_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_15_SSATA_SDA= TAOUT0 + { GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_16_TP_PCH_G= PP_D_16 + { GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_17_TP_PCH_G= PP_D_17 + { GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_18_TP_PCH= _GPP_D_18 + { GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_19_FM_PS_= PWROK_DLY_SEL + { GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_20_TP_PC= H_GPP_D_20 + { GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_21_SPC_I= E_LVC3_RX + { GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_22_SPC_I= E_LVC3_TX + { GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_23_TP_PC= H_GPP_D_23 + // Group E + { GPIO_SKL_H_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_0_TP_PCH_= GPP_E_0 + { GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_1_TP_PCH_= GPP_E_1 + { GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_2_TP_PCH_= GPP_E_2 + { GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_3_FM_A= DR_TRIGGER_N + { GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_4_TP_PCH_= GPP_E_4 + { GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_5_TP_PCH_= GPP_E_5 + { GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_6_TP_PCH_GPP= _E_6 + { GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutLow, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone } },/= /GPP_E_7_FM_ADR_SMI_GPIO_N MSFT_WCS_override: INT config and reset type + { GPIO_SKL_H_GPP_E8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_8_LED= _PCH_SATA_HDD_N + { GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_9_FM_O= C0_USB_N + { GPIO_SKL_H_GPP_E10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_10_FM_OC1_U= SB_N + { GPIO_SKL_H_GPP_E11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_11_FM_OC2_U= SB_N + { GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_12_FM= _OC3_USB_N + // Group F + { GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_0_TP_PCH_= GPP_F_0 + { GPIO_SKL_H_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_1_TP_PCH_= GPP_F_1 + { GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_2_TP_PCH_= GPP_F_2 + { GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_3_TP_PCH_= GPP_F_3 + { GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_4_TP_PCH_= GPP_F_4 + { GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_5_IRQ_T= PM_SPI_N + { GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, G= pioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_6_JTAG_PCH= _PLD_TCK + { GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, G= pioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_7_JTAG_PCH= _PLD_TDI + { GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, G= pioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_8_JTAG_PCH= _PLD_TMS + { GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_9_JTAG_= PCH_PLD_TDO + { GPIO_SKL_H_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_10_SGPIO= _SATA_CLOCK + { GPIO_SKL_H_GPP_F11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_11_SGPIO= _SATA_LOAD, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_1 + { GPIO_SKL_H_GPP_F12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_12_SGPIO= _SATA_DATA1, MSFT_WCS_override for AVA Slot4_PRSNT_N_2_1 + { GPIO_SKL_H_GPP_F13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_13_SGPIO= _SATA_DATA0, MSFT_WCS_override for AVA Slot3_PRSNT_N_2_1 + { GPIO_SKL_H_GPP_F14, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_14_L= ED_PCH_SSATA_HDD_N + { GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_15_FM_OC4_U= SB_N + { GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_16_FM_OC= 5_USB_N + { GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_17_FM_OC6_US= B_N + { GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_18_FM_OC= 7_USB_N + { GPIO_SKL_H_GPP_F19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_19_SMB= _GBE_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_F20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_20_SMB= _GBE_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_21_TP_PCH_= GPP_F_21 + { GPIO_SKL_H_GPP_F22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_22_SGPIO= _SSATA_CLOCK + { GPIO_SKL_H_GPP_F23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_23_SGPIO= _SSATA_LOAD + // Group G + { GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_0_FAN_TAC= H_0_FAN_TACH0IE, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_3 + { GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_1_FAN_TAC= H_1_FAN_TACH1IE, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_4 + { GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_2_FAN_TAC= H_2_FAN_TACH2IE, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_6 + { GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_3_FAN_TAC= H_3_FAN_TACH3IE + { GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_4_FAN_TAC= H_4_FAN_TACH4IE + { GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_5_FAN_TAC= H_5_FAN_TACH5IE + { GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_6_FAN_TAC= H_6_FAN_TACH6IE + { GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_7_FAN_TACH_7= _FAN_TACH7IE + { GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_G_8_FAN_= PWM_0_FAN_PWM0IE MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_9_FAN_PWM= _1_FAN_PWM1IE + { GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_G_10_FA= N_PWM_2_FAN_PWM2IE MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_G_11_FA= N_PWM_3_FAN_PWM3IE MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_12_FM_BOAR= D_SKU_ID0 + { GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_13_FM_BOAR= D_SKU_ID1 + { GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_14_FM_BOAR= D_SKU_ID2 + { GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_15_FM_BOAR= D_SKU_ID3 + { GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_16_FM_BOAR= D_SKU_ID4 + { GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_17_AD= R_COMPLETE + { GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_18_F= M_NMI_EVENT_N + { GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_19_F= M_SMI_ACTIVE_N + { GPIO_SKL_H_GPP_G20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,= GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_20_IRQ_SML= 1_PMBUS_ALERT_N + { GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_21_FM_SATAEX= PRESS_DEVSLP + { GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_22_FM_BIOS= _IMAGE_SWAP_N + { GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_23_FM_SS= ATA_PCIE_SEL + // Group H + { GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_0_PU_PCH_= GPP_H_0 + { GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_1_FM_SWAP= _OVERRIDE_N + { GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_2_FM_PCH_M= GPIO_TEST0 + { GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_3_FM_PCH_M= GPIO_TEST1 + { GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_4_FM_PCH_M= GPIO_TEST4 + { GPIO_SKL_H_GPP_H5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_5_FM_CLKRE= Q_M2_SSD_N + { GPIO_SKL_H_GPP_H6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_6_FM_OCULI= NK1_PCIE_SSD0_PRSNT_N + { GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_7_FM_OCULI= NK1_PCIE_SSD1_PRSNT_N + { GPIO_SKL_H_GPP_H8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_8_FM_CLKRE= Q_NIC1_N + { GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_9_FM_PCH_M= GPIO_TEST5 + { GPIO_SKL_H_GPP_H10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_10_SMB_= SMLINK2_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_H11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn= Out, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_11_SM= B_SMLINK2_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_12_FM_ES= PI_FLASH_MODE + { GPIO_SKL_H_GPP_H13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_13_S= MB_SMLINK3_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_H14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn= Out, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_14= _SMB_SMLINK3_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_15_PU_= ADR_TIMER_HOLD_OFF_N + { GPIO_SKL_H_GPP_H16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_16_S= MB_SMLINK4_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_H17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn= Out, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_17= _SMB_SMLINK4_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_18_FM_= LT_KEY_DOWNGRADE_N + { GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_19_TP_= PCH_GPP_H_19 + { GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_20_FM_= PCH_MGPIO_TEST2 + { GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_H_21_FM= _PCH_MGPIO_TEST3 MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_22_TP_= PCH_GPP_H_22 + { GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_23_FM_SSAT= A_PCIE_M2_SEL , MSFT_WCS_override for AVA Slot4_PRSNT_N_2_3 + // Group I + { GPIO_SKL_H_GPP_I0, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_0_GBE= _TDO + { GPIO_SKL_H_GPP_I1, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_1_GBE= _TCK + { GPIO_SKL_H_GPP_I2, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_2_GBE= _TMS + { GPIO_SKL_H_GPP_I3, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_3_GBE_= TDI + { GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_4_FP_LED_STA= TUS_GREEN_PCH_N + { GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_5_FP_LED_STA= TUS_AMBER_PCH_N + { GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_6_FP_ID_LED_= PCH_N + { GPIO_SKL_H_GPP_I7, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_7_JTA= G_GBE_TRST_N + { GPIO_SKL_H_GPP_I8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_8_FP_ID_B= TN_PCH_N + { GPIO_SKL_H_GPP_I9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_9_FM_MEM_= THERM_EVENT_PCH_N + { GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_10_TP_PC= H_GPP_I_10 + // Group GPD + { GPIO_SKL_H_GPD0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gpi= oOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_0_FM_FIVRBRE= AK_N + { GPIO_SKL_H_GPD1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_1_ACPRESENT + { GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gpi= oOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_2_LAN_WAKEB + { GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_3_PWRBT= NB + { GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, = GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_4_SLP_= S3B + { GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, = GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_5_SLP_= S4B + { GPIO_SKL_H_GPD6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_6_SLP_AB + { GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_7_TP_GPD_7 + { GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_8_CLK_33K_= PCH_SUSCLK_PLD + { GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_9_TP_SLP_WLAN + { GPIO_SKL_H_GPD10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi= oOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_10_SLP_S5= B_N + { GPIO_SKL_H_GPD11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_11_FM_PHY_D= ISABLE_N + // Group J + { GPIO_SKL_H_GPP_J0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_0_LED= _GBE_0_ACTIVITY + { GPIO_SKL_H_GPP_J1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_1_LED= _GBE_0_SPEED + { GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_2_LED_GBE_1= _ACTIVITY + { GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_3_LED_GBE_1= _SPEED + { GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_4_LED_GBE_2_A= CTIVITY, MSFT_WCS_override for AVA Slot3_PRSNT_N_2_3 + { GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_5_LED_GBE= _2_SPEED, MSFT_WCS_override for AVA Slot4_PRSNT_N_2_6 + { GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_J_6_LED_= GBE_3_ACTIVITY MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_J_7_LED_= GBE_3_SPEED MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_J8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_8_SMB= _GBE0_LVC3_R_SCL + { GPIO_SKL_H_GPP_J9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInO= ut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_9_S= MB_GBE0_LVC3_R_SDA + { GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_10_S= MB_GBE1_LVC3_R_SCL + { GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn= Out, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_11= _SMB_GBE1_LVC3_R_SDA + { GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_12_SMB_G= BE2_LVC3_R_SCL + { GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_13_SMB_G= BE2_LVC3_R_SDA + { GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,= GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_14_SMB_GBE= 3_LVC3_R_SCL + { GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_15_SMB_GBE3_= LVC3_R_SDA, MSFT_WCS_override for AVA Slot4_PRSNT_N_2_4 + { GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_16_FM= _T1_LVC3_MOD_ABS0 + { GPIO_SKL_H_GPP_J17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_17_L= ED_GBE_0_LOW_SPEED + { GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_J_18_FM_L1_= LVC3_MOD_ABS0 MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_19_LED_G= BE_1_LOW_SPEED + { GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_20_FM_T2_LVC= 3_MOD_ABS0 + { GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_21_LED_GBE_= 2_LOW_SPEED + { GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_22_FM_L2_LV= C3_MOD_ABS0 + { GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_23_LED_GBE= _3_LOW_SPEED + // Group K + { GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_0_CLK_= 50M_CKMNG_PCH + { GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_1_RMI= I_PCH_BMC_RXD<0> + { GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_2_RMI= I_PCH_BMC_RXD<1> + { GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_3_GBE= _NCSI_CRS_DV_R + { GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_4_RMII= _BMC_PCH_TX_EN + { GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_5_RMII= _BMC_PCH_TXD<0> + { GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_6_RMII= _BMC_PCH_TXD<1> + { GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_7_RMI= I_PCH_BMC_RX_ER + { GPIO_SKL_H_GPP_K8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_8_PD_RM= II_PCH_ARB_IN + { GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_9_PU_= RMII_PCH_ARB_OUT + { GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_10_RS= T_PCIE_PCH_PERST_N + //{GPIO_SKL_H_GPP_K11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirI= n, GpioOutDefault, GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_K_11_= PD_1P8_3P3_RCOMP + // Group L + //{GPIO_SKL_H_GPP_L0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirN= one, GpioOutDefault, GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_L_0 + //{GPIO_SKL_H_GPP_L1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutHigh, GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_L_1 + { GPIO_SKL_H_GPP_L2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_2_VISA= 2CH0_D0 + { GPIO_SKL_H_GPP_L3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_3_VISA= 2CH0_D1 + { GPIO_SKL_H_GPP_L4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_4_VISA= 2CH0_D2 + { GPIO_SKL_H_GPP_L5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_5_VISA= 2CH0_D3 + { GPIO_SKL_H_GPP_L6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_6_VISA= 2CH0_D4 + { GPIO_SKL_H_GPP_L7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_7_VISA= 2CH0_D5 + { GPIO_SKL_H_GPP_L8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_8_VISA2C= H0_D6 + { GPIO_SKL_H_GPP_L9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_9_VISA2C= H0_D7 + { GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,= GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_10_VISA= 2CH0_CLK + { GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_11_VISA2C= H1_D0 + { GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_12_VI= SA2CH1_D1 + { GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_13_VI= SA2CH1_D2 + { GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_14_VI= SA2CH1_D3 + { GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_15_VI= SA2CH1_D4 + { GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_16_VI= SA2CH1_D5 + { GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_17_VI= SA2CH1_D6 + { GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_18_VI= SA2CH1_D7 + { GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_19_VI= SA2CH1_CLK +}; + +UINTN mGpioTableSizeMicrosoftWcs =3D sizeof(mGpioTableMicrosoftWcs); diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/IioBifur.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Libra= ry/BoardInitLib/IioBifur.c new file mode 100644 index 0000000000..fa2a4d36ce --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /IioBifur.c @@ -0,0 +1,88 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + + +IIO_BIFURCATION_ENTRY mIioBifurcationTable[] =3D +{ + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, //Slot3: skt0/Iou0 P= ort1A x16 + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, //PCH uplink x16 + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_x4x4x4x4 }, //Slot1: skt0/Iou2 P= ort3A/3B, Slot2: skt0/Iou Port3C/3D (x8 slots) + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, //MCP x16 + { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, //MCP x16 + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxx8xxx8 }, //Slot4: skt1/IOU0 x= 16 Port1A/1B, 1C/1D for 2 x8 FPGAs + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxx8x4x4 }, //OCulink x8: skt1/I= ou1 Port2C/2D, M.2 slots skt1/Iou1 Port1A, 2B (x4x4) + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, //Slot5: skt1/IOU2 x= 16 + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, //MCP + { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, //MCP +}; + +UINT8 mIioBifurcationTableEntries =3D sizeof(mIioBifurcationTable)/sizeof(= IIO_BIFURCATION_ENTRY); + +IIO_SLOT_CONFIG_ENTRY mIioSlotTable[] =3D { + // Port | Slot | Inter | Power Limit | Power Limit | H= ot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD = | Hidden + // Index | | lock | Scale | Value | P= lug | Port | Addr | Cap | VppPort | VppAddr = | + { PORT_1A_INDEX, 3, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT= _MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_0, VPP_ADDR_MAX, HIDE }, //S0Slt3 +// { PORT_1B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABL= E, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x4C, HIDE }, +// { PORT_1C_INDEX, 1, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PO= RT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, + { PORT_2A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE,= VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE = }, + // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 11= 8 (MRL in J65) + { PORT_3A_INDEX, 1, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, ENABLE, VPP_PORT_= 0, 0x40, ENABLE, VPP_PORT_0, 0x40, NOT_HIDE }, + { PORT_3B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE,= VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_1, 0x40, HIDE }, + { PORT_3C_INDEX, 2, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT= _MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_0, 0x42, HIDE }, + { PORT_3D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE,= VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_1, 0x42, HIDE }, + { SOCKET_1_INDEX + + PORT_0_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VP= P_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, + // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 12= 1 (MRL in J287) + { SOCKET_1_INDEX + + PORT_1A_INDEX, 4, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_M= AX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, //x16 +// { SOCKET_1_INDEX + +// PORT_1B_INDEX, NO_SLT_IMP, ENABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, = VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x40, HIDE }, +// { SOCKET_1_INDEX + +// PORT_1C_INDEX, NO_SLT_IMP, ENABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, = VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_0, 0x42, HIDE }, +// { SOCKET_1_INDEX + +// PORT_1D_INDEX, NO_SLT_IMP, ENABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, = VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x42, HIDE }, + { SOCKET_1_INDEX + + PORT_2A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, V= PP_PORT_1, VPP_ADDR_MAX, ENABLE, VPP_PORT_0, 0x44, NOT_HIDE }, //x4 + { SOCKET_1_INDEX + + PORT_2B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, V= PP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x44, HIDE }, //x4 + { SOCKET_1_INDEX + + PORT_2C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, V= PP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_0, 0x46, HIDE }, //x8 + { SOCKET_1_INDEX + +// PORT_2D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE,= VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x46, HIDE }, +// { SOCKET_1_INDEX + + PORT_3A_INDEX, 5, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_M= AX, VPP_ADDR_MAX, ENABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, //x16 +// { SOCKET_1_INDEX + +// PORT_3C_INDEX, 7, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT= _MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, + // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port +}; + +UINT8 mIioSlotTableEntries =3D sizeof(mIioSlotTable)/sizeof(IIO_SLOT_CONFI= G_ENTRY); \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardM= tOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.c new file mode 100644 index 0000000000..f04f1e7c40 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /PeiBoardInitPostMemLib.c @@ -0,0 +1,45 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardInitBeforeSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +MtOlympusBoardInitAfterSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardInitBeforeSiliconInit ( + VOID + ) +{ + MtOlympusBoardInitBeforeSiliconInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterSiliconInit ( + VOID + ) +{ + MtOlympusBoardInitAfterSiliconInit (); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/PurleyOpenBoardPkg/Boar= dMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.inf new file mode 100644 index 0000000000..e71766e911 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /PeiBoardInitPostMemLib.inf @@ -0,0 +1,37 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiBoardPostMemInitLib + FILE_GUID =3D 30F407D6-6B92-412A-B2DA-8E73E2B386E6 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Sources] + PeiMtOlympusInitPostMemLib.c + PeiBoardInitPostMemLib.c + +[FixedPcd] + +[Pcd] + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMt= Olympus/Library/BoardInitLib/PeiBoardInitPreMemLib.c new file mode 100644 index 0000000000..511bc01339 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /PeiBoardInitPreMemLib.c @@ -0,0 +1,111 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +MtOlympusBoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +MtOlympusBoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +MtOlympusBoardInitBeforeMemoryInit ( + VOID + ); + +EFI_STATUS +EFIAPI +MtOlympusBoardInitAfterMemoryInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardDetect ( + VOID + ) +{ + MtOlympusBoardDetect (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDebugInit ( + VOID + ) +{ + MtOlympusBoardDebugInit (); + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +BoardBootModeDetect ( + VOID + ) +{ + return MtOlympusBoardBootModeDetect (); +} + +EFI_STATUS +EFIAPI +BoardInitBeforeMemoryInit ( + VOID + ) +{ + MtOlympusBoardInitBeforeMemoryInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterMemoryInit ( + VOID + ) +{ + MtOlympusBoardInitAfterMemoryInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitBeforeTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/PurleyOpenBoardPkg/Board= MtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..7b52668e9f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf @@ -0,0 +1,69 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiBoardInitPreMemLib + FILE_GUID =3D 73AA24AE-FB20-43F9-A3BA-448953A03A78 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + GpioLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + PurleyOpenBoardPkg/OpenBoardPkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +[Sources] + PeiMtOlympusDetect.c + PeiMtOlympusInitPreMemLib.c + PeiBoardInitPreMemLib.c + GpioTable.c + UsbOC.c + IioBifur.c + AllLanesEparam.c + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable + gOemSkuTokenSpaceGuid.PcdMemTsegSize + gOemSkuTokenSpaceGuid.PcdMemIedSize + + gOemSkuTokenSpaceGuid.PcdSetupData + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData + + gOemSkuTokenSpaceGuid.PcdUsb20OverCurrentMappings + gOemSkuTokenSpaceGuid.PcdUsb30OverCurrentMappings + gOemSkuTokenSpaceGuid.PcdIioBifurcationTable + gOemSkuTokenSpaceGuid.PcdIioBifurcationTableEntries + gOemSkuTokenSpaceGuid.PcdIioSlotTable + gOemSkuTokenSpaceGuid.PcdIioSlotTableEntries + gOemSkuTokenSpaceGuid.PcdAllLanesEparamTable + gOemSkuTokenSpaceGuid.PcdAllLanesEparamTableSize + +[FixedPcd] + gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress + gEfiPchTokenSpaceGuid.PcdTcoBaseAddress + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/PeiMtOlympusDetect.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOly= mpus/Library/BoardInitLib/PeiMtOlympusDetect.c new file mode 100644 index 0000000000..11221828da --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /PeiMtOlympusDetect.c @@ -0,0 +1,27 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardDetect ( + VOID + ) +{ + DEBUG ((EFI_D_INFO, "MtOlympusBoardDetect\n")); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/PeiMtOlympusInitLib.h b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOl= ympus/Library/BoardInitLib/PeiMtOlympusInitLib.h new file mode 100644 index 0000000000..bada6aef36 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /PeiMtOlympusInitLib.h @@ -0,0 +1,17 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_MT_OLYMPUS_BOARD_INIT_LIB_H_ +#define _PEI_MT_OLYMPUS_BOARD_INIT_LIB_H_ + +#include +#include +#include +#include +#include + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/PeiMtOlympusInitPostMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/Bo= ardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPostMemLib.c new file mode 100644 index 0000000000..7bcbe6e4a4 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /PeiMtOlympusInitPostMemLib.c @@ -0,0 +1,85 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "PeiMtOlympusInitLib.h" + +VOID +GetIioUdsHob ( + IN IIO_UDS **UdsHobPtr + ) +{ + EFI_GUID UniversalDataGuid =3D IIO_UNIVERSAL_DATA_GUID; + EFI_HOB_GUID_TYPE *GuidHob; + + ASSERT(UdsHobPtr); + + *UdsHobPtr =3D NULL; + =20 + GuidHob =3D GetFirstGuidHob (&UniversalDataGuid); + if (GuidHob){ + *UdsHobPtr =3D GET_GUID_HOB_DATA (GuidHob); + return; + } + + ASSERT(FALSE); +} + +EFI_STATUS +EFIAPI +MtOlympusBoardInitBeforeSiliconInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MtOlympusBoardInitAfterSiliconInit ( + VOID + ) +{ + IIO_UDS *IioUds; + + DEBUG((EFI_D_ERROR, "MtOlympusBoardInitAfterSiliconInit\n")); + + GetIioUdsHob(&IioUds); + + DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", IioUds->PlatformData.MemTolm)); + DEBUG ( + (EFI_D_ERROR, + "PCIE BASE: %lX Size : %X\n", + IioUds->PlatformData.PciExpressBase, + IioUds->PlatformData.PciExpressSize) + ); + DEBUG ( + (EFI_D_ERROR, + "PCI32 BASE: %X Limit: %X\n", + IioUds->PlatformData.PlatGlobalMmiolBase, + IioUds->PlatformData.PlatGlobalMmiolLimit) + ); + DEBUG ( + (EFI_D_ERROR, + "PCI64 BASE: %lX Limit: %lX\n", + IioUds->PlatformData.PlatGlobalMmiohBase, + IioUds->PlatformData.PlatGlobalMmiohLimit) + ); + DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", IioUds->Platfo= rmData.PlatGlobalMmiohBase, (IioUds->PlatformData.PlatGlobalMmiohLimit + 1)= )); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/PeiMtOlympusInitPreMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/Boa= rdMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c new file mode 100644 index 0000000000..b4001fd112 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /PeiMtOlympusInitPreMemLib.c @@ -0,0 +1,614 @@ +/** @file + +Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiMtOlympusInitLib.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SioRegs.h" + +#define LEGACY_8259_MASK_REGISTER_MASTER 0x21 +#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1 + +extern GPIO_INIT_CONFIG mGpioTableMicrosoftWcs[]; +extern UINTN mGpioTableSizeMicrosoftWcs; + +extern PCH_USB_OVERCURRENT_PIN Usb20OverCurrentMappings[PCH_MAX_USB2_PORTS= ]; +extern PCH_USB_OVERCURRENT_PIN Usb30OverCurrentMappings[PCH_MAX_USB3_PORTS= ]; + +extern IIO_BIFURCATION_ENTRY mIioBifurcationTable[]; +extern UINT8 mIioBifurcationTableEntries; +extern IIO_SLOT_CONFIG_ENTRY mIioSlotTable[]; +extern UINT8 mIioSlotTableEntries; +extern ALL_LANES_EPARAM_LINK_INFO KtiMtOlympusAllLanesEparamTable[]; +extern UINT32 KtiMtOlympusAllLanesEparamTableSize; + +/** + + Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal in= version registers. + + @param PeiServices - PeiService point. + @param CpuIo - CpuIo PPI to read/write IO ports. + + @retval EFI_SUCCESS - Init succeed. + +**/ +VOID +LpcSioEarlyInit ( + VOID + ) +{ + PchLpcGenIoRangeSet ((0x600 & 0xFF0), 0x10, LPC_ESPI_FIRST_SLAVE); + + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + + // + //mailbox + // + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (SIO_DATA_PORT, SIO_MAILBOX); + + IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_HIGH0); + IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 >> 8)); + + IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_LOW0); + IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 & 0xFF)); + // + //active mailbox + // + IoWrite8 (SIO_INDEX_PORT, ACTIVATE); + IoWrite8 (SIO_DATA_PORT, 1); + + IoWrite8 (SIO_INDEX_PORT, SIO_LOCK); +} + + +VOID +EarlyPlatformPchInit ( + IN EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration, + IN PCH_RC_CONFIGURATION *PchRcConfiguration + ) +{ + UINT16 Data16; + UINT8 Data8; + //UINTN LpcBaseAddress; + UINT8 TcoRebootHappened; + //UINTN PmcBaseAddress; + UINTN SpiBaseAddress; + UINTN P2sbBase; + + DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - Start\n")); + + // LpcBaseAddress =3D MmPciBase ( + // DEFAULT_PCI_BUS_NUMBER_PCH, + // PCI_DEVICE_NUMBER_PCH_LPC, + // PCI_FUNCTION_NUMBER_PCH_LPC + // ); + // PmcBaseAddress =3D MmPciBase ( + // DEFAULT_PCI_BUS_NUMBER_PCH, + // PCI_DEVICE_NUMBER_PCH_PMC, + // PCI_FUNCTION_NUMBER_PCH_PMC + // ); + SpiBaseAddress =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI + ); + + // + // Program bar + // + P2sbBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBREG_BAR, PCH_PCR_BASE_ADDRESS); + MmioOr8 (P2sbBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE); + + // + // LPC I/O Configuration + // + PchLpcIoDecodeRangesSet ( + (V_PCH_LPC_IOD_LPT_378 << N_PCH_LPC_IOD_LPT) | + (V_PCH_LPC_IOD_COMB_3E8 << N_PCH_LPC_IOD_COMB) | + (V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA) + ); + + PchLpcIoEnableDecodingSet ( + B_PCH_LPC_IOE_ME2 | + B_PCH_LPC_IOE_SE | + B_PCH_LPC_IOE_ME1 | + B_PCH_LPC_IOE_KE | + B_PCH_LPC_IOE_HGE | + B_PCH_LPC_IOE_LGE | + B_PCH_LPC_IOE_FDE | + B_PCH_LPC_IOE_PPE | + B_PCH_LPC_IOE_CBE | + B_PCH_LPC_IOE_CAE, + LPC_ESPI_FIRST_SLAVE + ); + + // + // Enable the upper 128-byte bank of RTC RAM + // + PchPcrAndThenOr32 (PID_RTC, R_PCH_PCR_RTC_CONF, (UINT32)~0, B_PCH_PCR_RT= C_CONF_UCMOS_EN); + + // + // Disable the Watchdog timer expiration from causing a system reset + // + PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~0, B_PCH_PCR_I= TSS_GIC_AME); + + // + // Halt the TCO timer + // + Data16 =3D IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT); + Data16 |=3D B_PCH_TCO_CNT_TMR_HLT; + IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT, Data16); + + // + // Read the Second TO status bit + // + Data8 =3D IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS); + DEBUG((EFI_D_ERROR, "pre read:%x\n", Data8)); + + Data8 =3D IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS); + DEBUG((EFI_D_ERROR, "read:%x\n", Data8)); + if ((Data8 & B_PCH_TCO2_STS_SECOND_TO) =3D=3D B_PCH_TCO2_STS_SECOND_TO) { + TcoRebootHappened =3D 1; + } else { + TcoRebootHappened =3D 0; + } + if (TcoRebootHappened) { + DEBUG ((EFI_D_ERROR, "EarlyPlatformPchInit - TCO Second TO status bit = is set. This might be a TCO reboot\n")); + } + + // + // Clear the Second TO status bit + // + Data8 |=3D B_PCH_TCO2_STS_SECOND_TO; + IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS, Data8); + + // + // Disable SERR NMI and IOCHK# NMI in port 61 + // + Data8 =3D IoRead8 (R_PCH_NMI_SC); + Data8 |=3D (B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN); + IoWrite8 (R_PCH_NMI_SC, Data8); + + PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~B_PCH_PCR_ITSS= _GIC_AME, 0); + + // + // Clear EISS bit to allow for SPI use + // + MmioAnd8 (SpiBaseAddress + R_PCH_SPI_BC, (UINT8)~B_PCH_SPI_BC_EISS); + + DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - End\n")); +} + + +/** + + Initialize POC register by Variable. + + @param *SystemConfiguration - Pointer to SystemConfiguration variables. + + @retval EFI_SUCCESS - Success. + +**/ +EFI_STATUS +UpdatePlatformInfo ( + IN SYSTEM_CONFIGURATION *SystemConfiguration, + IN SOCKET_CONFIGURATION *SocketConfiguration + ) +{ + SOCKET_PROCESSORCORE_CONFIGURATION *SocketProcessorCoreConfig; + SOCKET_IIO_CONFIGURATION *SocketIioConfig; + EFI_STATUS Status; + UINT32 PcIoApicEnable; +#if MAX_SOCKET <=3D 4 + UINTN Index; +#endif + + DEBUG((EFI_D_ERROR, "platform update platform info entry\n")); + + SocketProcessorCoreConfig =3D &SocketConfiguration->SocketProcessorCoreC= onfiguration; + SocketIioConfig =3D &SocketConfiguration->IioConfig; + +#if MAX_SOCKET <=3D 4 + for (Index =3D 0; Index < 24; Index++) { + if (SocketIioConfig->DevPresIoApicIio[Index]) { + PcIoApicEnable |=3D (1 << Index); + } + } + +#else + // Enable all 32 IOxAPIC + PcIoApicEnable =3D 0xFFFFFFFF; +#endif + Status =3D PcdSet32S (PcdPcIoApicEnable, PcIoApicEnable); + ASSERT_EFI_ERROR (Status); + // + // Check to make sure TsegSize is in range, if not use default. + // + if (SocketProcessorCoreConfig->TsegSize > MAX_PROCESSOR_TSEG) { + SocketProcessorCoreConfig->TsegSize =3D MAX_PROCESSOR_TSEG; // if out = of range make default 64M + } + Status =3D PcdSet32S (PcdMemTsegSize, (0x400000 << SocketProcessorCoreCo= nfig->TsegSize)); + ASSERT_EFI_ERROR (Status); + if (SocketProcessorCoreConfig->IedSize > 0) { + Status =3D PcdSet32S (PcdMemIedSize, (0x400000 << (SocketProcessorCore= Config->IedSize - 1))); + ASSERT_EFI_ERROR (Status); + } else { + Status =3D PcdSet32S (PcdMemIedSize, 0); + ASSERT_EFI_ERROR (Status); + } + + // + // Minimum SMM range in TSEG should be larger than 3M + // + ASSERT (PcdGet32 (PcdMemTsegSize) - PcdGet32 (PcdMemIedSize) >=3D 0x3000= 00); + + return EFI_SUCCESS; +} + +/** + Clear any SMI status or wake status left from boot. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +ClearPchSmiAndWake ( + VOID + ) +{ + UINT16 ABase; + UINT16 Pm1Sts =3D 0; + + + // + // Clear any SMI or wake state from the boot + // + Pm1Sts |=3D + ( + B_PCH_ACPI_PM1_STS_PWRBTN + ); + PchAcpiBaseGet (&ABase); + // + // Write them back + // + IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, Pm1Sts); + + // + // Clear the GPE and PM enable + // + IoWrite16 (ABase + R_PCH_ACPI_PM1_EN, 0); + IoWrite32 (ABase + R_PCH_ACPI_GPE0_EN_127_96, 0); + + return EFI_SUCCESS; +} + +EFI_STATUS +PlatformInitGpios ( + VOID + ) +{ + EFI_STATUS Status; + GPIO_INIT_CONFIG *GpioTable; + UINTN TableSize; + + TableSize =3D mGpioTableSizeMicrosoftWcs; + DEBUG ((DEBUG_ERROR, "UBA:Size of GpioTable 0x%X, blocks: 0x%X.\n", Tabl= eSize, (TableSize/sizeof (GPIO_INIT_CONFIG)) )); + + GpioTable =3D mGpioTableMicrosoftWcs; + DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() MtOlympus Start.\n")); + Status =3D GpioConfigurePads (TableSize/sizeof (GPIO_INIT_CONFIG), GpioT= able); + DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() MtOlympus End. Status =3D %r\= n", Status)); + + return EFI_SUCCESS; +} + +VOID +SetUsbConfig ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D PcdSet64S (PcdUsb20OverCurrentMappings, (UINT64)(UINTN)Usb20O= verCurrentMappings); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet64S (PcdUsb30OverCurrentMappings, (UINT64)(UINTN)Usb30O= verCurrentMappings); + ASSERT_EFI_ERROR (Status); +} + +VOID +IioPortBifurcationConfig ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D PcdSet64S (PcdIioBifurcationTable, (UINT64)(UINTN)mIioBifurca= tionTable); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet8S (PcdIioBifurcationTableEntries, mIioBifurcationTable= Entries); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet64S (PcdIioSlotTable, (UINT64)(UINTN)mIioSlotTable); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet8S (PcdIioSlotTableEntries, mIioSlotTableEntries); + ASSERT_EFI_ERROR (Status); +} + +VOID +AllLanesEparamTableConfig ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D PcdSet64S (PcdAllLanesEparamTable, (UINT64)(UINTN)KtiMtOlympu= sAllLanesEparamTable); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet32S (PcdAllLanesEparamTableSize, KtiMtOlympusAllLanesEp= aramTableSize); + ASSERT_EFI_ERROR (Status); +} + +EFI_STATUS +PchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig + ) +{ + GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)SystemConfig->LomDisableB= yGpio); + + return EFI_SUCCESS; +} + +/** + Write to mask registers of master and slave 8259 PICs. + +**/ +VOID +STATIC +Mask8259Interrupts ( + VOID + ) +{ + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0xFF); + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0xFF); +} + +EFI_STATUS +EFIAPI +MtOlympusBoardInitBeforeMemoryInit ( + VOID + ) +{ + EFI_STATUS Status; + SETUP_DATA SetupData; + SYSTEM_CONFIGURATION SystemConfiguration; + PCH_RC_CONFIGURATION PchRcConfiguration; + SOCKET_CONFIGURATION SocketConfiguration; + UINT16 ABase; + UINT16 Pm1Sts; + UINT32 Pm1Cnt; + CONST EFI_PEI_SERVICES ** PeiServices; + + PeiServices =3D GetPeiServicesTablePointer (); + + ZeroMem (&SetupData, sizeof(SETUP_DATA)); + CopyMem (&SetupData.SocketConfig.IioConfig, PcdGetPtr(PcdSocketIioConfig= Data), sizeof(SOCKET_IIO_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.CommonRcConfig, PcdGetPtr(PcdSocketComm= onRcConfigData), sizeof(SOCKET_COMMONRC_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.CsiConfig, PcdGetPtr(PcdSocketMpLinkCon= figData), sizeof(SOCKET_MP_LINK_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.MemoryConfig, PcdGetPtr(PcdSocketMemory= ConfigData), sizeof(SOCKET_MEMORY_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.PowerManagementConfig, PcdGetPtr(PcdSoc= ketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION)= ); + CopyMem (&SetupData.SocketConfig.SocketProcessorCoreConfiguration, PcdGe= tPtr(PcdSocketProcessorCoreConfigData), sizeof(SOCKET_PROCESSORCORE_CONFIGU= RATION)); + CopyMem (&SetupData.SystemConfig, PcdGetPtr(PcdSetupData), sizeof(SYSTEM= _CONFIGURATION)); + CopyMem (&SetupData.PchRcConfig, PcdGetPtr(PcdPchRcConfigurationData), s= izeof(PCH_RC_CONFIGURATION)); + + CopyMem (&SocketConfiguration, &(SetupData.SocketConfig), sizeof (SOCKET= _CONFIGURATION)); + CopyMem (&PchRcConfiguration, &(SetupData.PchRcConfig), sizeof (PCH_RC_C= ONFIGURATION)); + CopyMem (&SystemConfiguration, &(SetupData.SystemConfig), sizeof (SYSTEM= _CONFIGURATION)); + + /// + /// Set LPC SIO + /// + MmioOr16( + (MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_= FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_IOE), + B_PCH_LPC_IOE_SE + ); + + LpcSioEarlyInit (); + + Status =3D PlatformInitGpios (); + ASSERT_EFI_ERROR (Status); + + SetUsbConfig (); + IioPortBifurcationConfig (); + AllLanesEparamTableConfig (); + + /// + /// Do Early PCH init + /// + EarlyPlatformPchInit ((EFI_PEI_SERVICES**)PeiServices, &SystemConfigurat= ion, &PchRcConfiguration); + + /// + /// Clear PCH SMI and Wake + /// Clear all pending SMI. On S3 clear power button enable so it will no= t generate an SMI. + /// + Status =3D ClearPchSmiAndWake(); + ASSERT_EFI_ERROR (Status); + ///---------------------------------------------------------------------= ------------- + /// + /// BIOS should check the WAK_STS bit in PM1_STS[15] (PCH register ABASE= +00h) before memory + /// initialization to determine if ME has reset the system while the hos= t was in a sleep state. + /// If WAK_STS is not set, BIOS should ensure a non-sleep exit path is t= aken by overwriting + /// PM1_CNT[12:10] (PCH register ABASE+04h) to 111b to force an s5 exit. + /// + PchAcpiBaseGet (&ABase); + Pm1Sts =3D IoRead16 (ABase + R_PCH_ACPI_PM1_STS); + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) =3D=3D 0) { + Pm1Cnt =3D IoRead32 (ABase + R_PCH_ACPI_PM1_CNT); + Pm1Cnt |=3D V_PCH_ACPI_PM1_CNT_S5; + IoWrite32 (ABase + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + } + + UpdatePlatformInfo (&SystemConfiguration, &SocketConfiguration); + + // + // Do platform specific on-board Zoar init + // + PchLanConfig (&SystemConfiguration); + + // + // The 8259 PIC is still functional and not masked by default even if AP= IC is + // enabled. So need to disable all 8259 interrupts. + // + Mask8259Interrupts (); + + return EFI_SUCCESS; +} + +/** + + Turn off system if needed. + + @param PeiServices Pointer to PEI Services + @param CpuIo Pointer to CPU I/O Protocol + + @retval None. + +**/ +VOID +CheckPowerOffNow ( + VOID + ) +{ + + UINT16 Pm1Sts; + + // + // Read and check the ACPI registers + // + Pm1Sts =3D IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI= _PM1_STS); + DEBUG ((EFI_D_ERROR, "CheckPowerOffNow()- Pm1Sts=3D 0x%04x\n", Pm1Sts )); + + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) =3D=3D B_PCH_ACPI_PM1_STS_PWRBT= N) { + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_STS= , B_PCH_ACPI_PM1_STS_PWRBTN); + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT= , V_PCH_ACPI_PM1_CNT_S5); + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT= , V_PCH_ACPI_PM1_CNT_S5 + B_PCH_ACPI_PM1_CNT_SLP_EN); + } +} + +EFI_STATUS +EFIAPI +MtOlympusBoardInitAfterMemoryInit ( + VOID + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINT16 Pm1Cnt; + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // + // Check if user wants to turn off in PEI phase + // + if (BootMode !=3D BOOT_ON_S3_RESUME) { + CheckPowerOffNow (); + } else { + Pm1Cnt =3D IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_A= CPI_PM1_CNT); + Pm1Cnt &=3D ~B_PCH_ACPI_PM1_CNT_SLP_TYP; + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT= , Pm1Cnt); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MtOlympusBoardDebugInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +MtOlympusBoardBootModeDetect ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/Board= InitLib/UsbOC.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/= BoardInitLib/UsbOC.c new file mode 100644 index 0000000000..a9375b116e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib= /UsbOC.c @@ -0,0 +1,45 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include + +PCH_USB_OVERCURRENT_PIN Usb20OverCurrentMappings[PCH_MAX_USB2_PORTS] =3D { + PchUsbOverCurrentPinSkip, //1 BMC,skip + PchUsbOverCurrentPinSkip, //2 BMC,skip + PchUsbOverCurrentPin0, //3 USB REAR PANEL, = OC0 + PchUsbOverCurrentPin1, //4 USB REAR PANEL, = OC1 + PchUsbOverCurrentPin1, //5 USB REAR PANEL, = OC1 + PchUsbOverCurrentPinSkip, //6 Internal USB3.0,= NC, skip(org OC2 in schematic) + PchUsbOverCurrentPinSkip, //7 NC, skip + PchUsbOverCurrentPin4, //8 Internal USB2.0,= OC4 + PchUsbOverCurrentPinSkip, //9 NC, skip + PchUsbOverCurrentPinSkip, //10 NC, skip + PchUsbOverCurrentPin6, //11 USB FRONT PANEL,= OC6 + PchUsbOverCurrentPin5, //12 USB STORAGE FRON= T PANNEL, OC5 + PchUsbOverCurrentPin6, //13 USB FRONT PANEL,= OC6 + PchUsbOverCurrentPin5, //14 USB STORAGE FRON= T PANNEL, OC5 + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinSkip + }; + +PCH_USB_OVERCURRENT_PIN Usb30OverCurrentMappings[PCH_MAX_USB3_PORTS] =3D { + PchUsbOverCurrentPin6, //1 USB FRONT PANEL, O= C6 + PchUsbOverCurrentPin6, //2 USB FRONT PANEL, O= C6 + PchUsbOverCurrentPin0, //3 USB REAR PANEL, OC0 + PchUsbOverCurrentPin1, //4 USB REAR PANEL, OC1 + PchUsbOverCurrentPin1, //5 USB REAR PANEL, OC1 + PchUsbOverCurrentPinSkip, //6 Internal USB3.0, N= C, skip(org OC2 in schematic) + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinSkip + }; + --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Tue, 11 May 2021 02:49:00 -0700 IronPort-SDR: xriFyzhEiMBkxjqNmzsjoIF6fE8Lw6M5khRnZxbFSRcZGBKjhYA4PTOHxmsxQLFz/pi1ecf6Rx RrPTRdJ68pSg== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="178994736" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="178994736" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:57 -0700 IronPort-SDR: 0CJTs2lWfuCET9nhjFBwY6cuiBw72R1L0U7AYjn59otziCtpORnpgsd9hGQqdlmAJDOUnOmnKH IBM0+ja9u9dQ== X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="436574052" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.66.229]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:56 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-devel] [edk2-platforms] [PATCH V1 17/18] Readme.md: Add PurleyOpenBoardPkg Date: Tue, 11 May 2021 02:48:25 -0700 Message-Id: <20210511094826.12495-18-nathaniel.l.desimone@intel.com> In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: IlXRVs6sHUIOXLjFSVWVSOthx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726546; bh=OHoPvEcNxtwusJbI0XQh/S/dJVb2xJ5+D94BStghTOo=; h=Cc:Date:From:Reply-To:Subject:To; b=SjsbI90rdgl2an6UztaQ1xLPO+DVhA1REr8xB6VJuTiKpdyPsUzy7yPmQKr5/iWgMBH qaj+WhleX06iPqPGMKMhiECoI0Ut1eQjge85KmjeEdQJvKCC2m84ilstmD3NgpzRnjJz9 ltyWBPGqJ9bkZvHMOymxXkyJa9kL+z2iFJA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- Platform/Intel/Readme.md | 34 ++++++++++++++++++++++++++++++++++ Readme.md | 1 + 2 files changed, 35 insertions(+) diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 41d39c8582..06c5f32b1e 100644 --- a/Platform/Intel/Readme.md +++ b/Platform/Intel/Readme.md @@ -54,6 +54,7 @@ A UEFI firmware implementation using MinPlatformPkg is co= nstructed using the fol =20 ## Board Support * The `KabylakeOpenBoardPkg` contains board implementations for KabyLake s= ystems. +* The `PurleyOpenBoardPkg` contains board implementations for Purley syste= ms. * The `SimicsOpenBoardPkg` contains board implementations for the Simics h= ardware simulator. * The `WhiskeylakeOpenBoardPkg` contains board implementations for Whiskey= Lake systems. * The `CometlakeOpenBoardPkg` contains board implementations for CometLake= systems. @@ -80,6 +81,12 @@ A UEFI firmware implementation using MinPlatformPkg is c= onstructed using the fol =20 *Note: RVP =3D Reference and Validation Platform* =20 +#### Microsoft + +| Machine Name | Supported Chipsets = | BoardPkg | Board Name | +----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| +| Mt. Olympus | Purley = | PurleyOpenBoardPkg | BoardMtOlympus | + #### Simics =20 | Machine Name | Supported Chipsets = | BoardPkg | Board Name | @@ -237,6 +244,13 @@ return back to the minimum platform caller. | | | |---build_board.py: Optional bo= ard-specific pre-build, build | | | and clean p= ost-build functions. | | | + | | |------PurleyOpenBoardPkg + | | | |------BoardMtOlympus + | | | |---build_config.cfg: BoardMtOl= ympus specific + | | | | build set= tings, environment variables. + | | | |---build_board.py: Optional bo= ard-specific pre-build, + | | | build, post= -build and clean functions. + | | | | | |------SimicsOpenBoardPkg | | | |------BoardX58Ich10 | | | |---build_config.cfg: BoardX58I= ch10 specific @@ -263,6 +277,21 @@ return back to the minimum platform caller. |------FSP =20 +**Building with the batch scripts** + +Only PurleyOpenBoardPkg still supports batch script build (in addition to = Python build). Batch scripts are deprecated +and will be removed from PurleyOpenBoardPkg in the future. All other board= packages must only use the Python build +infrastructure. + +For PurleyOpenBoardPkg +1. Open command window, go to the workspace directory, e.g. c:\Edk2Workspa= ce. +2. Type "cd edk2-platforms\Platform\Intel\PurleyOpenBoardPkg\BoardMtOlympu= s". +3. Type "GitEdk2MinMtOlympus.bat" to setup GIT environment. +4. Type "bld" to build Purley Mt Olympus board UEFI firmware image, "bld r= elease" for release build, "bld clean" to + remove intermediate files."bld cache-produce" Generate a cache of binar= y files in the specified directory, + "bld cache-consume" Consume a cache of binary files from the specified = directory, BINARY_CACHE_PATH is empty, + used "BinCache" as default path. + ### **Known limitations** =20 **KabylakeOpenBoardPkg** @@ -273,6 +302,11 @@ return back to the minimum platform caller. 1. This firmware project has only been tested for Microsoft Windows 10 x64= boot with AHCI mode and Integrated Graphic Device. =20 +**PurleyOpenBoardPkg** +1. This firmware project has only been tested booting to Microsoft Windows= Server 2016 with NVME on M.2 slot. +2. This firmware project does not build with the GCC compiler. +3. The validated version of iASL compiler that can build MinPurley is 2018= 0629. Older versions may generate ACPI build errors. + **SimicsOpenBoardPkg** 1. This firmware project has only been tested booting to Microsoft Windows= 10 x64 and Ubuntu 17.10 with AHCI mode. =20 diff --git a/Readme.md b/Readme.md index d00600d350..aba26e29a6 100644 --- a/Readme.md +++ b/Readme.md @@ -243,6 +243,7 @@ they will be documented with the platform. ## Intel ### [Minimum Platforms](Platform/Intel/Readme.md) * [Kaby Lake](Platform/Intel/KabylakeOpenBoardPkg) +* [Purley](Platform/Intel/PurleyOpenBoardPkg) * [Simics](Platform/Intel/SimicsOpenBoardPkg) * [Whiskey Lake](Platform/Intel/WhiskeylakeOpenBoardPkg) * [Comet Lake](Platform/Intel/CometlakeOpenBoardPkg) --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: UXn8EIKIzUbuR2IG5O7gGJiGx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1620726547; bh=k+aCjXKVeb8pFrPWg6OHJ7pA811Tt05si6LkqGlINKA=; h=Cc:Date:From:Reply-To:Subject:To; b=qKheSfLtgrlCu8cPvOu1jxOuIkcwXJjfNtvQTD1DXmM80fQnCy0XIsjYkIY4FBNuwLE 8kFcWHPwfn1kg9vsbYT2sRDmv5D6XYV0tKz4Y3/rAV3ebYpsIAvH4RYpwCvxRkS1Rcz1y HUYLgmHn9XKLxH7Dr0Gb4N8ejZRLUf5l+No= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- Maintainers.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index f6313b430c..10a9521ec3 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -195,6 +195,11 @@ M: Nate DeSimone R: Liming Gao R: Eric Dong =20 +Platform/Intel/PurleyOpenBoardPkg +F: Platform/Intel/PurleyOpenBoardPkg/ +M: Nate DeSimone +M: Chasel Chiu + Platform/Intel/WhiskeylakeOpenBoardPkg F: Platform/Intel/WhiskeylakeOpenBoardPkg/ M: Chasel Chiu @@ -263,6 +268,11 @@ F: Silicon/Intel/KabylakeSiliconPkg/ M: Chasel Chiu M: Sai Chaganty =20 +Silicon/Intel/PurleyRefreshSiliconPkg +F: Silicon/Intel/PurleyRefreshSiliconPkg/ +M: Chasel Chiu +M: Nate DeSimone + Silicon/Intel/TigerlakeSiliconPkg F: Silicon/Intel/TigerlakeSiliconPkg/ M: Sai Chaganty --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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