From nobody Fri Mar 29 13:23:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74533+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74533+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619611970; cv=none; d=zohomail.com; s=zohoarc; b=U5LvTJlG1w9WjlkD9nnLVcHEg71HD9y53G+H+9rCmRADxDhJENyXhF0okhb0k+2NYZEoDqvviDdVnm3ae8vd5+xvKXOKKFYjvno5Zl8F+pAlhNLpLxHWNbeXa7z2Adln01Z2KqdCE0D2ZeG/WY4V7EppPR4Grouc4NVT+8W557M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619611970; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=lEyB2BmZnw1LPcMf4rb3kOpYXQAcHC2R+HfzjMeXmVs=; b=Nzh7VmsXsaF30PsWBNRJbG6aLztGiml9F+xrBjO5RbGWtIID6GI7eGZbZ6WmxwbzBNnO06ZoQzT3ARG4P0igCzNPiyO89Hcp6ti9mhtpdv7cMwpVTp1mt8ie5t7B/Ez508LcxgjQUOTsI0cqJYYrjkfWh0rpa4ydj7TLtXAhSnI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74533+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1619611970236974.989048592077; Wed, 28 Apr 2021 05:12:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id SSTzYY1788612xIjHH9zx2NO; Wed, 28 Apr 2021 05:12:49 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.10786.1619611963196817349 for ; Wed, 28 Apr 2021 05:12:43 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ACE871042; Wed, 28 Apr 2021 05:12:42 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 48BE83F694; Wed, 28 Apr 2021 05:12:41 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 1/8] Platform/Sgi: Helper macros for PPTT Table Date: Wed, 28 Apr 2021 17:42:22 +0530 Message-Id: <20210428121229.32674-2-pranav.madhu@arm.com> In-Reply-To: <20210428121229.32674-1-pranav.madhu@arm.com> References: <20210428121229.32674-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: hMFIl0d5vfykxGI7CQcXpWGxx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1619611969; bh=/J/I4Zhkr1NaGdbrzJOU8Emi7Ep/NcZKCsLqlpUrxPY=; h=Cc:Date:From:Reply-To:Subject:To; b=A/Z77/oGjGS81EfDT4zW4tqfRYiE0jVS47Bd/iThiCajr8TnBKgrlsW1Xy7e+bErgxM gmiV/94/4PehROX3WgDQOKrF6DycGZ2eLWcTzMlUzlm+nKo/QwCAaFSrjsDGDAQ/qojjj EMfeFYBka4lUo6H1nrEDC3mdFcmADSj8Tx0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add helper macros for the creation for PPTT table. These macros help with initializing processor hierarchy node structure, cache type structure and ID structure. Signed-off-by: Pranav Madhu Reviewed-by: Pierre Gondois Reviewed-by: Thomas Abraham --- Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 160 ++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/Sgi= Pkg/Include/SgiAcpiHeader.h index dcb4e6c77a74..7bb8b6dec6a3 100644 --- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h +++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h @@ -20,6 +20,131 @@ #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ') #define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099 =20 +#define CORE_COUNT FixedPcdGet32 (PcdCoreCount) +#define CLUSTER_COUNT FixedPcdGet32 (PcdClusterCount) + +#pragma pack(1) +// PPTT processor core structure +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 ResourceOffset[2]; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache; +} RD_PPTT_CORE; + +// PPTT processor cluster structure +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 ResourceOffset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache; + RD_PPTT_CORE Core[CORE_COUNT]; +} RD_PPTT_CLUSTER; + +// PPTT processor cluster structure without cache +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + RD_PPTT_CORE Core[CORE_COUNT]; +} RD_PPTT_MINIMAL_CLUSTER; + +// PPTT processor package structure +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 ResourceOffset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT]; +} RD_PPTT_SLC_PACKAGE; +#pragma pack () + +// +// PPTT processor structure flags for different SoC components as defined = in +// ACPI 6.3 specification +// + +// Processor structure flags for SoC package +#define PPTT_PROCESSOR_PACKAGE_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ + } + +// Processor structure flags for cluster +#define PPTT_PROCESSOR_CLUSTER_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ + } + +// Processor structure flags for single-thread core +#define PPTT_PROCESSOR_CORE_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF = \ + } + +// Processor structure flags for multi-thread core +#define PPTT_PROCESSOR_CORE_THREADED_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ + } + +// Processor structure flags for CPU thread +#define PPTT_PROCESSOR_THREAD_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD, = \ + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF = \ + } + +// PPTT cache structure flags as defined in ACPI 6.3 Specification +#define PPTT_CACHE_STRUCTURE_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID, = \ + EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID, = \ + EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID, = \ + EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID, = \ + EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID, = \ + EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID, = \ + EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID = \ + } + +// PPTT cache attributes for data cache +#define PPTT_DATA_CACHE_ATTR = \ + { = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ + } + +// PPTT cache attributes for instruction cache +#define PPTT_INST_CACHE_ATTR = \ + { = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ + } + +// PPTT cache attributes for unified cache +#define PPTT_UNIFIED_CACHE_ATTR = \ + { = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ + } + // A macro to initialise the common header part of EFI ACPI tables as defi= ned by // EFI_ACPI_DESCRIPTION_HEADER structure. #define ARM_ACPI_HEADER(Signature, Type, Revision) { \ @@ -246,4 +371,39 @@ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLine= Size \ } =20 +// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR +#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent, = \ + ACPIProcessorID, NumberOfPrivateResource) = \ + { = \ + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type 0 */ = \ + Length, /* Length */ = \ + { = \ + EFI_ACPI_RESERVED_BYTE, = \ + EFI_ACPI_RESERVED_BYTE, = \ + }, = \ + Flag, /* Processor flags *= / \ + Parent, /* Ref to parent nod= e */ \ + ACPIProcessorID, /* UID, as per MADT = */ \ + NumberOfPrivateResource /* Resource count */= \ + } + +// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE +#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Size,= \ + NoOfSets, Associativity, Attributes, LineSize) = \ + { = \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, /* Type 1 */ = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), /* Length */ = \ + { = \ + EFI_ACPI_RESERVED_BYTE, = \ + EFI_ACPI_RESERVED_BYTE, = \ + }, = \ + Flag, /* Cache flags */ = \ + NextLevelCache, /* Ref to next level= */ \ + Size, /* Size in bytes */ = \ + NoOfSets, /* Num of sets */ = \ + Associativity, /* Num of ways */ = \ + Attributes, /* Cache attributes = */ \ + LineSize /* Line size in byte= s */ \ + } + #endif /* __SGI_ACPI_HEADER__ */ --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74533): https://edk2.groups.io/g/devel/message/74533 Mute This Topic: https://groups.io/mt/82427820/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:23:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74534+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74534+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619611968; cv=none; d=zohomail.com; s=zohoarc; b=fMvVwyGMO3Dr96X/EqsGKEKzxQIKCUJ+CsrJjsrm+IBOGjSBdRazA9pvP80bBqbJL2/WbYk3fRa64NkbUkBoNsKRjcg5LYamil0xXfXnjgVKenletlRdTwR0qIb6D4Aarm07BMi0pJ9QDlYxXZLUbHS0CO+ASjkTY9ylrjW/wHk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619611968; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=FhI7ORGR+aHZxdpKxNjXccuJmpA3nsiJn3tmZkT4coo=; b=KaQo/rSQK+nYkI7iKzgs9jY1cwIdX0a7jnkFCLAyLtRfgPwQuZOt4PYHBPWaDy6FwNk+wmWmvC/Pf8GNKuMYFr5N445I5AcUXwtEry5Wrl51CSrWrhh/62/ox+GoVDJ63XTuIInykS75ciHZqVucYjfz8fZnTWRLCayp22V7JXY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74534+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1619611968805719.5784350556031; Wed, 28 Apr 2021 05:12:48 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id p7fCYY1788612xX734WAGSqF; Wed, 28 Apr 2021 05:12:48 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.10788.1619611964990267788 for ; Wed, 28 Apr 2021 05:12:45 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 887791FB; Wed, 28 Apr 2021 05:12:44 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 233DF3F694; Wed, 28 Apr 2021 05:12:42 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform Date: Wed, 28 Apr 2021 17:42:23 +0530 Message-Id: <20210428121229.32674-3-pranav.madhu@arm.com> In-Reply-To: <20210428121229.32674-1-pranav.madhu@arm.com> References: <20210428121229.32674-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: eWa7S9x8OnyABWR8V28LmgB0x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1619611968; bh=vctGKTXYU9f4dhxPal9YWcmum0NyR8Nsv4jwbhQTEU0=; h=Cc:Date:From:Reply-To:Subject:To; b=U7WAjxIOnVfC+wbQl2UydecwhS380yOjTd/P/Syjrc3Ms8LbAoc9VcSoVxGPJaBvKpv ol/W0K7GeFU/KmCoZS8HWago17v4mDOq0FxOaSMO6f56mBez9OysDEXE48t8wrDTa8KjG LBLG+3dGxPZs+SeXAsfFob6swvDEd1Pauzk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pranav Madhu The SGI-575 platform includes two clusters with four single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. Add PPTT table for SGI-575 platform with this information. Signed-off-by: Pranav Madhu Reviewed-by: Pierre Gondois Reviewed-by: Thomas Abraham --- Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +- Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 161 ++++++++++++++++= ++++ 2 files changed, 163 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf b/Platform= /ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf index 2121fd39f2f0..b1ee16e98ea3 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2018, ARM Ltd. All rights reserved. +# Copyright (c) 2018 - 2021, ARM Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,7 @@ Mcfg.aslc Sgi575/Dsdt.asl Sgi575/Madt.aslc + Sgi575/Pptt.aslc Spcr.aslc Ssdt.asl =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc b/Platform/ARM= /SgiPkg/AcpiTables/Sgi575/Pptt.aslc new file mode 100644 index 000000000000..3388a012dd55 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc @@ -0,0 +1,161 @@ +/** @file +* Processor Properties Topology Table (PPTT) for SGI-575 platform +* +* This file describes the topological structure of the processor block on = the +* SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-575 +* platform includes two clusters with four single-thread CPUS. Each of the= CPUs +* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. +* Each cluster includes a 2MB L3 cache. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define PPTT_CORE_INIT(pid, cid, cpuid) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid]), /* Parent */ = \ + ((pid << 3) | (cid << 2) | cpuid), /* ACPI Id */ = \ + 2 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 64, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_512KB, /* Size */ = \ + 1024, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), = \ + /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].L3Cache), = \ + = \ + /* L3 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_2MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* Initialize child cores */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0), = \ + PPTT_CORE_INIT (pid, cid, 1), = \ + PPTT_CORE_INIT (pid, cid, 2), = \ + PPTT_CORE_INIT (pid, cid, 3) = \ + } = \ + } + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; +} SGI575_PPTT_PACKAGE; + +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + SGI575_PPTT_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + OFFSET_OF (SGI575_PPTT_PACKAGE, Cluster[0]), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0 + ), + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1) + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74534): https://edk2.groups.io/g/devel/message/74534 Mute This Topic: https://groups.io/mt/82427821/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:23:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74535+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74535+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619611972; cv=none; d=zohomail.com; s=zohoarc; b=MzIY0hKAZDUEG0i4En6VpbY+OM/Fd8ms0vwb38ruVYZ1EpiRRarylMPviUPsJKl2SHHKnFvfnhttTyNQA0ctVNFxB3zc+clzs5/vhXFANiRodFe1ohWEu9EcnBTRo+VVQz1u9WKYmjv5ueTwzO6HAQBqVnDrweUvlLIBdz+XzGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619611972; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=zZ4pqSwDlJ16jb7b3RZjObHIJVzAuHT1DEhNBB0XiWc=; b=O3NcS12Wy+F9guI+vBV4sDqv95SaocEEcpo3ATlpkGWCbfXsR3AfnVj6kTunEWSw4OLyl97YM4NjHPuQi9/785q6L2FioMPMBB+r0cC9SFB0PlfnpCEbEOpU7ew2kKScm8y6WSMuzC0g6C9mWmtweIFv4r5uupHMWAhe3FUd4Lg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74535+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1619611972204282.11968825025065; Wed, 28 Apr 2021 05:12:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id QVaLYY1788612x8mhwGZ1aE5; Wed, 28 Apr 2021 05:12:51 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.10604.1619611966755605129 for ; Wed, 28 Apr 2021 05:12:46 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6023A1042; Wed, 28 Apr 2021 05:12:46 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F1B5C3F694; Wed, 28 Apr 2021 05:12:44 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 3/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform Date: Wed, 28 Apr 2021 17:42:24 +0530 Message-Id: <20210428121229.32674-4-pranav.madhu@arm.com> In-Reply-To: <20210428121229.32674-1-pranav.madhu@arm.com> References: <20210428121229.32674-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: 07Qbqkq3lI81NS1hnB0axEPjx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1619611971; bh=gOOBB7LBP6Xp/+i1EvjYRDrCCyeQqN7jtAbF8URf1NE=; h=Cc:Date:From:Reply-To:Subject:To; b=LmsaOQi/7IkxDunlk7piBQd0h2vn2ffDR1mLcv/d2uucDhKTcWIiYiOtH2jNSXKT32A nrd3I/PXfK+nxmRl2LRsYGWB306EqZVqQLk5dWXHy87GtpXophMjSsPPv3sZQhlnRDbfp N6iCLSX1uz0ebLJOS491lehuWSyA/MGs7Hk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-N1-Edge platform includes two clusters with four single-thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. The platform also includes a system level cache of 8MB. Add PPTT table for RD-N1-Edge platform with this information. Signed-off-by: Pranav Madhu Reviewed-by: Pierre Gondois Reviewed-by: Thomas Abraham --- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +- Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 175 ++++++++++++++= ++++++ 2 files changed, 177 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf index 22e33239070b..eecb64186473 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2018-2020, ARM Ltd. All rights reserved. +# Copyright (c) 2018-2021, ARM Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,6 +23,7 @@ Mcfg.aslc RdN1Edge/Dsdt.asl RdN1Edge/Madt.aslc + RdN1Edge/Pptt.aslc Spcr.aslc Ssdt.asl =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc new file mode 100644 index 000000000000..1a9dc1762767 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc @@ -0,0 +1,175 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip pl= atform +* +* This file describes the topological structure of the processor block on = the +* RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT tabl= e. The +* RD-N1-Edge platform includes two clusters with four single-thread CPUS. = Each +* of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 51= 2KB L2 +* cache. Each cluster includes a 2MB L3 cache. The platform also includes a +* system level cache of 8MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define PPTT_CORE_INIT(pid, cid, cpuid) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid]), /* Parent */ = \ + ((pid << 3) | (cid << 2) | cpuid), /* ACPI Id */ = \ + 2 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_512KB, /* Size */ = \ + 1024, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].L3Cache), = \ + = \ + /* L3 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_2MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* Initialize child cores */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0), = \ + PPTT_CORE_INIT (pid, cid, 1), = \ + PPTT_CORE_INIT (pid, cid, 2), = \ + PPTT_CORE_INIT (pid, cid, 3) = \ + } = \ + } + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; +} RDN1EDGE_PPTT_PACKAGE ; + +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RDN1EDGE_PPTT_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + OFFSET_OF (RDN1EDGE_PPTT_PACKAGE , Slc), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), + + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + Package.Slc), + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ + 0, /* Next level of cache */ + SIZE_8MB, /* Size */ + 8192, /* Num of sets */ + 16, /* Associativity */ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ + 64 /* Line size */ + ), + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74535): https://edk2.groups.io/g/devel/message/74535 Mute This Topic: https://groups.io/mt/82427823/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:23:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74536+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74536+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619611976; cv=none; d=zohomail.com; s=zohoarc; b=PGlDxCIgyeTZ1MGJBlSy2iKbzc6zzF4qJD9ccPDl8bIQqXij0cH9XHfmYWy/exSzHbDOWutJTzRBaGDbS77ANTfUMSIPj/FwmdjSCDOQSsrjRgi0C9fYkdHNt5CG/3/my+eadxUtEzTVbc2p2X7ootXfipsu+0OJEo3ck5S8ibE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619611976; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=HC8etyxUgicDxmLaEasIP16zdDYfeIV9MqdzJKgj6Vw=; b=boqcP93FYg8DBst1e95XNCsL6t1TiGiCygSONouOoxeY1ZgVERmm8DqT8yF4Dji3fg5EWEnydcNEQw+P/Y0IG/C9WJKnG37CLWw5AM/7o4YNjdRdZlECl87IfdcKv3YKTxWYGAskY9mO3VgQruvkw29yfDnv3ziP8IFZwaxzdeE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74536+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1619611976810443.5012919922733; Wed, 28 Apr 2021 05:12:56 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id VjykYY1788612xglxq9siZqs; Wed, 28 Apr 2021 05:12:56 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10982.1619611968720146673 for ; Wed, 28 Apr 2021 05:12:49 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3AE9D1063; Wed, 28 Apr 2021 05:12:48 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CC15A3F694; Wed, 28 Apr 2021 05:12:46 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 4/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip Date: Wed, 28 Apr 2021 17:42:25 +0530 Message-Id: <20210428121229.32674-5-pranav.madhu@arm.com> In-Reply-To: <20210428121229.32674-1-pranav.madhu@arm.com> References: <20210428121229.32674-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: n27qLirwq18raOPRL28pHUUBx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1619611976; bh=B06S5D3wMaC9d84IV8jhy+0coJqi0BxKxdjV8dIOk9A=; h=Cc:Date:From:Reply-To:Subject:To; b=upr6xI21299DP0wUpUFmEFAiWmEo8EaNNt/LHiTfG6bX9y/Vrhaz03PlnVxcK/FdFd4 qKOVQfuegOL6W7ME2vCAueKvrGfbWnc39BPm+FwB0BNIHZN98BK0UebA6sDT7SAAci5Ok H7QytgKdRF/rlBHqGbKDRltKYoTCN04FvMA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platforms connected over cache coherent interconnect. Each of the RD-N1-Edge single-chip platform includes two clusters with four single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. The platform also includes a system level cache of 8MB per chip. Add PPTT table for RD-N1-Edge dual-chip platform with this information. Signed-off-by: Pranav Madhu Reviewed-by: Pierre Gondois Reviewed-by: Thomas Abraham --- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 192 ++++++++++++= ++++++++ 2 files changed, 193 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Plat= form/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf index 76886d1c6a17..91d219d14506 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf @@ -24,6 +24,7 @@ RdN1Edge/Dsdt.asl RdN1EdgeX2/Hmat.aslc RdN1EdgeX2/Madt.aslc + RdN1EdgeX2/Pptt.aslc RdN1EdgeX2/Srat.aslc Spcr.aslc Ssdt.asl diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc new file mode 100644 index 000000000000..d1bf30dc21c7 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc @@ -0,0 +1,192 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip plat= form +* +* This file describes the topological structure of the processor block on = the +* RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table.= The +* RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platfo= rms +* connected over cache coherent interconnect. Each of the RD-N1-Edge singl= e-chip +* platform includes two clusters with four single-thread CPUS. Each of the= CPUs +* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache= . Each +* cluster includes a 2MB L3 cache. Each instance of the chip includes a sy= stem +* level cache of 8MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define CHIP_COUNT FixedPcdGet32 (PcdChipCount) + +#define PPTT_CORE_INIT(pid, cid, cpuid) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid]), /* Parent */ = \ + ((pid << 3) | (cid << 2) | cpuid), /* ACPI Id */ = \ + 2 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_512KB, /* Size */ = \ + 1024, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid]), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].L3Cache), = \ + = \ + /* L3 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_2MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* Initialize child cores */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0), = \ + PPTT_CORE_INIT (pid, cid, 1), = \ + PPTT_CORE_INIT (pid, cid, 2), = \ + PPTT_CORE_INIT (pid, cid, 3) = \ + } = \ + } + +#define PPTT_PACKAGE_INIT(pid) = \ + { = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RDN1EDGEX2_PPTT_PACKAGE , Slc), /* Length */ = \ + PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ = \ + 0, /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Slc), = \ + = \ + /* SLC parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_8MB, /* Size */ = \ + 8192, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + { = \ + PPTT_CLUSTER_INIT (pid, 0), = \ + PPTT_CLUSTER_INIT (pid, 1), = \ + } = \ + } + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; +} RDN1EDGEX2_PPTT_PACKAGE; + +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RDN1EDGEX2_PPTT_PACKAGE Package[CHIP_CO= UNT]; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + PPTT_PACKAGE_INIT (0), + PPTT_PACKAGE_INIT (1) + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74536): https://edk2.groups.io/g/devel/message/74536 Mute This Topic: https://groups.io/mt/82427824/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:23:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74537+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74537+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619611972; cv=none; d=zohomail.com; s=zohoarc; b=g3RY+hP6BKFXCZdvCypREivnmIjjMFnO+NdP6U+d46Eg08jlwJGsI1SaQcpTwgeaSV9JeHXSrQ+ZpnbegI3ViUYUC0AOKlbnRVDMx3oQ39WuFsIy5D9x4WkQYwqYRKVwcScLWHgiBDXIY/jQt956XXgv5LJNSdpIij2jysDRo2o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619611972; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Q80X944XfIhMVNya/DkTYmW1/KUv/ve+GXd/4xhu50U=; b=YSTWGPNC9XUX3t7oCPlbZNWfBDBovZedCBcW7ewd9GH1QubLHnAaIea3TYyp/NmVyWU+9Z4vhCfSZOv7N2uxwSfTniQek2CnvrGxFdOuJPlUYmTBHWXnZMxr8iO7l++/aPFfWkDY1n+CfchqGu8uK01372jK19785BqLOP9e+o0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74537+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1619611972740645.0414341961189; Wed, 28 Apr 2021 05:12:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id iEVcYY1788612xKIHuO9XUdU; Wed, 28 Apr 2021 05:12:52 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10983.1619611970650961782 for ; Wed, 28 Apr 2021 05:12:50 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D4E01042; Wed, 28 Apr 2021 05:12:50 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A669D3F694; Wed, 28 Apr 2021 05:12:48 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Date: Wed, 28 Apr 2021 17:42:26 +0530 Message-Id: <20210428121229.32674-6-pranav.madhu@arm.com> In-Reply-To: <20210428121229.32674-1-pranav.madhu@arm.com> References: <20210428121229.32674-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: xFdPvxRGKk0o5vtfSpF4YuDTx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1619611972; bh=HTrogUdsnE6kxr1Fz4WY7z7MHaGCEsKgkwOsJ+cXvXg=; h=Cc:Date:From:Reply-To:Subject:To; b=CnsZMzuFqOJ/Tca9Akq7vuw6v4kCI4c4I+N99nguHtNTZb6kzJ7IVSnhiQWIAPdZnJC h5wZiblI5Jk67Qo4+cN6IoSzSLrrLa9Uc5ep+JfDd6uQzgSHmWOXZ5j6HVgG4Xy1cQq5N GCWvdIIPJp1gta1fL6xOI76DmpsxP8rqSSI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-E1-Edge platform includes two clusters with eight multi-thread CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The platform also includes a system level cache of 8MB. Add PPTT table for RD-E1-Edge platform with this information. Signed-off-by: Pranav Madhu Reviewed-by: Pierre Gondois Reviewed-by: Thomas Abraham --- Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +- Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 230 ++++++++++++++= ++++++ 2 files changed, 232 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf index 2dd2275665a2..04ef2bfcaa26 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2018-2020, ARM Ltd. All rights reserved. +# Copyright (c) 2018-2021, ARM Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,6 +23,7 @@ Mcfg.aslc RdE1Edge/Dsdt.asl RdE1Edge/Madt.aslc + RdE1Edge/Pptt.aslc Spcr.aslc Ssdt.asl =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc new file mode 100644 index 000000000000..d4c7b1613a28 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc @@ -0,0 +1,230 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform +* +* This file describes the topological structure of the processor block on = the +* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1= -Edge +* platform includes two clusters with eight dual-thread CPUS. Each of the = CPUs +* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache. +* Each cluster includes a 2MB L3 cache. The platform also includes a system +* level cache of 8MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define THREAD_PER_CORE_E1 2 + +#define PPTT_THREAD_INIT(pid, cid, cpuid, tid) = \ + { = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ = \ + PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid]), /* Parent */ = \ + ((pid << 5) | (cid << 4) | (cpuid << 1) | tid), = \ + /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ) = \ + } + +#define PPTT_CORE_INIT(pid, cid, cpuid) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid]), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 2 /* Num of private resource= */ \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_32KB, /* Size */ = \ + 128, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_32KB, /* Size */ = \ + 128, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_256KB, /* Size */ = \ + 1024, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* Thread Initialization */ = \ + { = \ + PPTT_THREAD_INIT (pid, cid, cpuid, 0), = \ + PPTT_THREAD_INIT (pid, cid, cpuid, 1) = \ + } = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].L3Cache), = \ + = \ + /* L3 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_2MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* Initialize child cores */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0), = \ + PPTT_CORE_INIT (pid, cid, 1), = \ + PPTT_CORE_INIT (pid, cid, 2), = \ + PPTT_CORE_INIT (pid, cid, 3), = \ + PPTT_CORE_INIT (pid, cid, 4), = \ + PPTT_CORE_INIT (pid, cid, 5), = \ + PPTT_CORE_INIT (pid, cid, 6), = \ + PPTT_CORE_INIT (pid, cid, 7) = \ + } = \ + } + +#define PPTT_PACKAGE_INIT(pid) = \ + { = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Slc), = \ + PPTT_PROCESSOR_PACKAGE_FLAGS, = \ + 0, = \ + 0, = \ + 1 = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Slc), = \ + = \ + /* SLC parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_8MB, /* Size */ = \ + 8192, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + { = \ + PPTT_CLUSTER_INIT (pid, 0), = \ + PPTT_CLUSTER_INIT (pid, 1), = \ + } = \ + } + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread; +} RDE1EDGE_PPTT_THREAD; + +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache; + RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE_E1]; +} RDE1EDGE_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache; + RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CORE= _E1]; +} RDE1EDGE_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; +} RDE1EDGE_PPTT_PACKAGE; + +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RDE1EDGE_PPTT_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + PPTT_PACKAGE_INIT (0) +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74537): https://edk2.groups.io/g/devel/message/74537 Mute This Topic: https://groups.io/mt/82427825/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:23:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74540+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74540+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619611984; cv=none; d=zohomail.com; s=zohoarc; b=e6fnc9rqsy/rF5HtRZ13ErMIMCNs37Ug6LJI7a2YQMQdk+59CmZNXJd4CHhpVAUf5C2knVNcDIhCI9SIhH50eUtT+0qbyyZowlqE+D6LhPrPygT2lw1mFTQR4Y31vI881sKByHfRCPoRBwWey6tpC3i+hE6KzeWwUMflHdrTTWc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619611984; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QQVr6xM/IDJRC8rhgQIXnErgiiHt0wLKv4/uecB3HdQ=; b=QqUzbK4nzfFEK4V1IrtF/uLu0gm33yjWnrVUZUKXJ9UD2CH6k4pDgvHmRQ4i4yRdvw2SLLrWhiP8sT4GPpMlLjxoAnIzH7NASXkjAdrQlNT2atcN3Cy1gzXPjfu5m3P+gHsjRBmIxkeXP4sv2ce8C6v/432uCgeSGDzdyoMnLMg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74540+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1619611984768858.3497719063641; Wed, 28 Apr 2021 05:13:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id tZVaYY1788612xP6kUgq9XZ4; Wed, 28 Apr 2021 05:13:01 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.10791.1619611977544393327 for ; Wed, 28 Apr 2021 05:12:57 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2CB7B1FB; Wed, 28 Apr 2021 05:12:52 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B8FD43F694; Wed, 28 Apr 2021 05:12:50 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 6/8] Platform/Sgi: ACPI PPTT Table for RD-V1 platform Date: Wed, 28 Apr 2021 17:42:27 +0530 Message-Id: <20210428121229.32674-7-pranav.madhu@arm.com> In-Reply-To: <20210428121229.32674-1-pranav.madhu@arm.com> References: <20210428121229.32674-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: GDfeXfU0YXtHKHfa0HL3TRnpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1619611981; bh=EsCKuNdUHsR9Xe/3th0MnbutdAxo5rouQzPUW8i8JPk=; h=Cc:Date:From:Reply-To:Subject:To; b=B+ORrqGQQ30o2l8wJq7QLzZVSCQm+k2zJOhtbpMiOVgFvG1lRyCw+3mxBLzzCQi7mFC 3SpHZ2AtnbojvPJKcMZSaH87aE4i4swPyL4I7Vwln7JUyE6wZM2V4HY0S44cXTj5MqCDj dLo1qtvVwnlHeq8TDHumeoPUXucujlERrts= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-V1 platform includes sixteen single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes a system level cache of 16MB. Add PPTT table for RD-V1 platform with this information. Signed-off-by: Pranav Madhu Reviewed-by: Pierre Gondois Reviewed-by: Thomas Abraham --- Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +- Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 164 ++++++++++++++++++= ++ 2 files changed, 166 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf b/Platform/A= RM/SgiPkg/AcpiTables/RdV1AcpiTables.inf index a21dcfafef1a..a3e558cf1535 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2020, Arm Ltd. All rights reserved. +# Copyright (c) 2020-2021, Arm Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,6 +23,7 @@ Mcfg.aslc RdV1/Dsdt.asl RdV1/Madt.aslc + RdV1/Pptt.aslc Spcr.aslc Ssdt.asl =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM/S= giPkg/AcpiTables/RdV1/Pptt.aslc new file mode 100644 index 000000000000..1c157e3bee2e --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc @@ -0,0 +1,164 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform +* +* This file describes the topological structure of the processor block on = the +* RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The +* RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of = the +* CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 ca= che. +* The platform also includes a system level cache of 16MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define PPTT_CORE_INIT(pid, cid, cpuid) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid]), /* Parent */ = \ + ((pid << 4) | cid), /* ACPI Id */ = \ + 2 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_1MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ), = \ + = \ + /* Initialize child core */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0) = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_SLC_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), + + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + Package.Slc), + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ + 0, /* Next level of cache */ + SIZE_16MB, /* Size */ + 16384, /* Num of sets */ + 16, /* Associativity */ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ + 64 /* Line size */ + ), + + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + PPTT_CLUSTER_INIT (0, 2), + PPTT_CLUSTER_INIT (0, 3), + PPTT_CLUSTER_INIT (0, 4), + PPTT_CLUSTER_INIT (0, 5), + PPTT_CLUSTER_INIT (0, 6), + PPTT_CLUSTER_INIT (0, 7), + PPTT_CLUSTER_INIT (0, 8), + PPTT_CLUSTER_INIT (0, 9), + PPTT_CLUSTER_INIT (0, 10), + PPTT_CLUSTER_INIT (0, 11), + PPTT_CLUSTER_INIT (0, 12), + PPTT_CLUSTER_INIT (0, 13), + PPTT_CLUSTER_INIT (0, 14), + PPTT_CLUSTER_INIT (0, 15) + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74540): https://edk2.groups.io/g/devel/message/74540 Mute This Topic: https://groups.io/mt/82427832/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:23:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74538+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74538+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619611977; cv=none; d=zohomail.com; s=zohoarc; b=iIzRRZV+1gUufwAquZ49d007KvhwED63/JZ6q2S6bkfJ6Wgq5x4TyWEq2tXA6LOVSEBnJ/Fl6yI1eVWMefsQZIURAuNa+u43SMiXBNnws/H4CycHjOu26771IQQOpZ4UC9WLQUivtGF1OL+rrXeFZEFbmCanXG3DLpcvRzxpw0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619611977; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=S156eKqOwW98LkLKM92pHM/X8wCLoX3v+n9J91eBDCw=; b=Qh7Z4eMq0m6We2qclsfuOQ2wDTckZH+UtF2HDRiGWj6nwnIL12BHuFxtqdbRpn2QPYIdMY5VPHRID3G9b5r05MpZdTNakdJdrRfdfp+/rdR1ARGKy2LPcwfsoEuq1wIqd8i+WA1ASCvDyNhiCeWvVLyTaSi4GClVbgQDvzyKUrk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74538+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1619611977553500.3757911331362; Wed, 28 Apr 2021 05:12:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id FAh6YY1788612xzKTMmY49qN; Wed, 28 Apr 2021 05:12:56 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10984.1619611974321192334 for ; Wed, 28 Apr 2021 05:12:54 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 01A0F1042; Wed, 28 Apr 2021 05:12:54 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 934883F694; Wed, 28 Apr 2021 05:12:52 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 7/8] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform Date: Wed, 28 Apr 2021 17:42:28 +0530 Message-Id: <20210428121229.32674-8-pranav.madhu@arm.com> In-Reply-To: <20210428121229.32674-1-pranav.madhu@arm.com> References: <20210428121229.32674-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: tSYln1J5AiJZoZyyEFbdJcYpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1619611976; bh=h7lFrIhUYbc0zAKxm8WlHA84dwV7TtqJQFp92g7pYQE=; h=Cc:Date:From:Reply-To:Subject:To; b=YbWySjq4JKPpb1lq/B4jff2HWzxlV6vc0Zb27ptildXIAzdBITzaU99jHLV+4UEtuXF pAP/mbTzuh0SAiS5BRLRW12suOcqdQElVMpWUN07qtv7nbINh719AYNxtscKhxj3f5Idm 8vw7fkArzKHHLwS4cFEQRC0WWeBHQSBK0uM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-V1 quad-chip platform consists of four chips connected over cache coherent interconnect. Each chip on the platform includes four single- thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes a system level cache of 16MB per chip. Add PPTT table for RD-V1 quad-chip platform with this information. Signed-off-by: Pranav Madhu Reviewed-by: Pierre Gondois Reviewed-by: Thomas Abraham --- Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 169 ++++++++++++++++= ++++ 2 files changed, 170 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platform= /ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf index c49546ec0b27..ffda4f925b19 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf @@ -24,6 +24,7 @@ RdV1Mc/Dsdt.asl RdV1Mc/Hmat.aslc RdV1Mc/Madt.aslc + RdV1Mc/Pptt.aslc RdV1Mc/Srat.aslc Spcr.aslc Ssdt.asl diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/ARM= /SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc new file mode 100644 index 000000000000..5e35871b068b --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc @@ -0,0 +1,169 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platform +* +* This file describes the topological structure of the processor block on = the +* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. The = RD-V1 +* quad-chip platform is composed of four identical chips connected over ca= che +* coherent interconnect. Each of the chip on the platform includes four si= ngle +* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instru= ction +* cache and 1MB L2 cache. The platform also includes a system level cache = of +* 16MB per chip. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define CHIP_COUNT FixedPcdGet32 (PcdChipCount) + +#define PPTT_CORE_INIT(pid, cid, cpuid) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid]), /* Parent */ = \ + ((pid << 2) | cid), /* ACPI Id */ = \ + 2 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_1MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid]), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ), = \ + = \ + /* Initialize child core */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0) = \ + } = \ + } + +#define PPTT_PACKAGE_INIT(pid) = \ + { = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), /* Length */ = \ + PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ = \ + 0, /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Slc), = \ + = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_16MB, /* Size */ = \ + 16384, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + { = \ + PPTT_CLUSTER_INIT (pid, 0), = \ + PPTT_CLUSTER_INIT (pid, 1), = \ + PPTT_CLUSTER_INIT (pid, 2), = \ + PPTT_CLUSTER_INIT (pid, 3), = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_SLC_PACKAGE Package[CHIP_CO= UNT]; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + PPTT_PACKAGE_INIT (0), + PPTT_PACKAGE_INIT (1), + PPTT_PACKAGE_INIT (2), + PPTT_PACKAGE_INIT (3) + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74538): https://edk2.groups.io/g/devel/message/74538 Mute This Topic: https://groups.io/mt/82427830/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:23:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74539+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74539+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619611984; cv=none; d=zohomail.com; s=zohoarc; b=SVVikZM62JOqiC/SdgeaB3k0/i25LVrSZjq/mALwJ4pL1MFLvQDLEMKRL1vdmzybPXuOrTGChEKvxXBJxvfLVs0FCPVXAt6u5gd3LumNTLt7zRJlnnKZ2RULusFP59VQnIg6eCONBJe30Mypm2UcDFF/1j61GO5KsWVh9U7oqY4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619611984; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vmk4QT2uIW24JvcHok80fQTzr/+qIqbn8n09oyDfBv4=; b=Go/Kmjvv5dVBLz1xe0mtMTifyo8uxDFfkNwBcWtC3/fr174s6zrMAHmvCssEOgdB7yTqtCCzJQrpU8lZkv80OHRbDb20n/EiYJ5zdtnrWmREC58eMqrg/j5ihVsg4+ULiiJpizbMtNRuehHhg5g+v8SaAug01bKYwJj795cJ0LM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74539+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1619611984774417.8966824321802; Wed, 28 Apr 2021 05:13:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id QSqAYY1788612xJAfCjhMmUk; Wed, 28 Apr 2021 05:12:59 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.10887.1619611976336726817 for ; Wed, 28 Apr 2021 05:12:56 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5EF91042; Wed, 28 Apr 2021 05:12:55 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6D7793F694; Wed, 28 Apr 2021 05:12:54 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 8/8] Platform/Sgi: ACPI PPTT table for RD-N2 platform Date: Wed, 28 Apr 2021 17:42:29 +0530 Message-Id: <20210428121229.32674-9-pranav.madhu@arm.com> In-Reply-To: <20210428121229.32674-1-pranav.madhu@arm.com> References: <20210428121229.32674-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: PmtvaLIH1nTBShyHBZY9YEQrx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1619611979; bh=nD35lJMBesMAfwOSNlCH29EjcJ2/DPQ9P0LJJt0DfUA=; h=Cc:Date:From:Reply-To:Subject:To; b=HfAsXFq88s6wmHODYPALFxe0l4ElXxxM8HVIndpoZC711i4EvLVyRKoskpnRSGaWtIy H4a6mia2mJS9Okvz2+HPyBe5DgG3VbciKQV9kggLnb8TD+WA3feIR7brmlv6d+TlJClDa 4VJ9UiuxSYddrTiAUhwoMactQBa0B06pkPQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-N2 platform includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes a system level cache of 32MB. Add PPTT table for RD-N2 platform with this information. Signed-off-by: Pranav Madhu Reviewed-by: Pierre Gondois Reviewed-by: Thomas Abraham --- Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +- Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 164 ++++++++++++++++++= ++ 2 files changed, 166 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/A= RM/SgiPkg/AcpiTables/RdN2AcpiTables.inf index 2ec3e42473a9..c1282a3422ab 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2020, Arm Ltd. All rights reserved. +# Copyright (c) 2020-2021, Arm Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,7 @@ Mcfg.aslc RdN2/Dsdt.asl RdN2/Madt.aslc + RdN2/Pptt.aslc Spcr.aslc Ssdt.asl SsdtRos.asl diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/S= giPkg/AcpiTables/RdN2/Pptt.aslc new file mode 100644 index 000000000000..1d00110311ab --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc @@ -0,0 +1,164 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-N2 platform +* +* This file describes the topological structure of the processor block on = the +* RD-N2 platform in the form as defined by ACPI PPTT table. The RD-N2 plat= form +* includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Da= ta +* cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also inc= ludes +* system level cache of 32MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define PPTT_CORE_INIT(pid, cid, cpuid) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid]), /* Parent */ = \ + ((pid << 4) | cid), /* ACPI Id */ = \ + 2 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_1MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ), = \ + = \ + /* Initialize child core */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0) = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_SLC_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), + + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + Package.Slc), + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ + 0, /* Next level of cache */ + SIZE_32MB, /* Size */ + 32768, /* Num of sets */ + 16, /* Associativity */ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ + 64 /* Line size */ + ), + + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + PPTT_CLUSTER_INIT (0, 2), + PPTT_CLUSTER_INIT (0, 3), + PPTT_CLUSTER_INIT (0, 4), + PPTT_CLUSTER_INIT (0, 5), + PPTT_CLUSTER_INIT (0, 6), + PPTT_CLUSTER_INIT (0, 7), + PPTT_CLUSTER_INIT (0, 8), + PPTT_CLUSTER_INIT (0, 9), + PPTT_CLUSTER_INIT (0, 10), + PPTT_CLUSTER_INIT (0, 11), + PPTT_CLUSTER_INIT (0, 12), + PPTT_CLUSTER_INIT (0, 13), + PPTT_CLUSTER_INIT (0, 14), + PPTT_CLUSTER_INIT (0, 15) + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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