From nobody Thu Apr 25 13:40:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74407+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74407+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1619361711; cv=none; d=zohomail.com; s=zohoarc; b=ifzm9voiuN3TTp3g7CZQvwYjOxoophv1/uJsKwEjOsQlr61/hvs9sePo9t6qM06898HkQpnZ5bkPJepKXmh4FX3FmxN4O+zakUmkvje2gHMh9jkJSin0syKj5VIqqACXrxDGbuq18Po7vRUnRVQukVlaF61AO7CLC13As+oXDeg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619361711; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=qeJ+6Y7OJFuafxhlTRdsoCGjshonFM6YiWd/WLmkfKE=; b=m7Eou2/YtE3aF5PbG5gcbg6bvOVmERblzNbyAHdBIukaHb4yQJlZ18B8ngB14/sbAnKAD7EO/tb64hCOg0Eul4yIUfJc7q3YnXrYoniTuQjxVp5za7tX3FEaIoL69MXUeb2Ry4xZVgaouQ6aGJkuTb5UqwIIPMSdYVMH7EyynoU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74407+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1619361711153534.154634882722; Sun, 25 Apr 2021 07:41:51 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id XaVqYY1788612x383kMwKvp7; Sun, 25 Apr 2021 07:41:50 -0700 X-Received: from mga01.intel.com (mga01.intel.com []) by mx.groups.io with SMTP id smtpd.web11.2187.1619361707983443525 for ; Sun, 25 Apr 2021 07:41:50 -0700 IronPort-SDR: 0PRk/jS5kcCh9N1yedbm6aAZ+M+GFzWAaLL2JGUVohFSpzE/mzzgEca7B+yF2BeSi1A107IV0E qYHW8jIxjlhw== X-IronPort-AV: E=McAfee;i="6200,9189,9965"; a="216931747" X-IronPort-AV: E=Sophos;i="5.82,250,1613462400"; d="scan'208";a="216931747" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2021 07:41:49 -0700 IronPort-SDR: U5FEbwVhrsO4TFv1BcOnPC20Zi9Qq+NiOerHUFhByjLJEVMr1F3bVYyVkd96r1s63zLx3setOX OYQPgZaQGiPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,250,1613462400"; d="scan'208";a="429053667" X-Received: from shwdeopenlab102.ccr.corp.intel.com ([10.239.183.74]) by orsmga008.jf.intel.com with ESMTP; 25 Apr 2021 07:41:47 -0700 From: "Jason Lou" To: devel@edk2.groups.io Cc: Jason Lou , Chasel Chiu , Nate DeSimone , Star Zeng , Ray Ni Subject: [edk2-devel] [PATCH v1] Intel/WhiskeylakeOpenBoardPkg: Simplify microcode related PCD usage Date: Sun, 25 Apr 2021 22:41:37 +0800 Message-Id: <20210425144137.16411-4-yun.lou@intel.com> In-Reply-To: <20210425144137.16411-1-yun.lou@intel.com> References: <20210425144137.16411-1-yun.lou@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yun.lou@intel.com X-Gm-Message-State: 8Tb2pOwRFM7GjnhRIwTtODh9x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1619361710; bh=mljjUgsYoLQYWDXEAR+XEfXaNtgMOuFpKz1DEnNXhr8=; h=Cc:Date:From:Reply-To:Subject:To; b=RpjjbFe4IpOPaQuxTDtFS2IUWgxxzOno8HG4xxTjADfVOCdFm6nriBEKReK2UGpHJxP qiP3IMix/nOwuBIR4aGWkEcfaoPdrjGz2jmv0vPrk0Czm0WLH9hNMnwVVDB1rs7uPCsl9 3dvvU+UeIR44wdwPN+BVM2x4RIF6xAnJEHs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Jason Lou REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3334 There are following PCDs in IntelFsp2WrapperPkg for microcode location: * IntelFsp2WrapperPkg: PcdCpuMicrocodePatchAddress PcdCpuMicrocodePatchRegionSize PcdFlashMicrocodeOffset The change simplify the platform code to use following PCDs instead: * MinPlatformPkg PcdFlashFvMicrocodeOffset PcdFlashFvMicrocodeBase =3D $(BIOS_BASE) + PcdFlashFvMicrocodeOffset PcdFlashFvMicrocodeSize PcdMicrocodeOffsetInFv Signed-off-by: Jason Lou Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni Reviewed-by: Chasel Chiu --- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspW= rapperPlatformSecLib/SecRamInitData.c | 6 +++--- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspW= rapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf | 8 ++++---- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf = | 6 ++---- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf = | 6 ++---- 4 files changed, 11 insertions(+), 15 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Lib= rary/SecFspWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/Whiskeyl= akeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Sec= RamInitData.c index 8442e5fbff..41a37f5da5 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se= cFspWrapperPlatformSecLib/SecRamInitData.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se= cFspWrapperPlatformSecLib/SecRamInitData.c @@ -1,7 +1,7 @@ /** @file Provide TempRamInitParams data. =20 -Copyright (c) 2020, Intel Corporation. All rights reserved.
+Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -24,8 +24,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD FsptUpdDataP= tr =3D { }, // FSPT_CORE_UPD { - ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 = (PcdFlashMicrocodeOffset)), - ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet= 32 (PcdFlashMicrocodeOffset)), + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(C= odeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used. FixedPcdGet32 (PcdFlashCodeCacheSize), { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Lib= rary/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform= /Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecFspWrapperPlatformSecLib.inf index b17226d43b..e7319cf9e7 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se= cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se= cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf @@ -1,7 +1,7 @@ ## @file # Provide FSP wrapper platform sec related function. # -# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -92,9 +92,9 @@ [FixedPcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## C= ONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## C= ONSUMES - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## C= ONSUMES - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## C= ONSUMES - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## C= ONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## C= ONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## C= ONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C= ONSUMES diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.f= df b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf index 0d99114961..22fbfc99f0 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf @@ -2,7 +2,7 @@ # FDF file for the UpXtreme. # # -# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gS= iPkgTokenSpaceGuid.PcdBio SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize) SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiP= kgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashM= icrocodeFvOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(g= SiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60 +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.fdf index ad32268a82..1ab8c13792 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.f= df +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.f= df @@ -2,7 +2,7 @@ # FDF file of Platform. # # -# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gS= iPkgTokenSpaceGuid.PcdBio SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize) SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiP= kgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashM= icrocodeFvOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(g= SiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60 +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset --=20 2.28.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74407): https://edk2.groups.io/g/devel/message/74407 Mute This Topic: https://groups.io/mt/82355107/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-