From nobody Sat Apr 20 10:25:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74219+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74219+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1618605793; cv=none; d=zohomail.com; s=zohoarc; b=cxkXg5WghCUYLsD4uqm3FgpP4JACk73K08eq2YccWlj14fnac354+nWLpsOoSyYJnE2lkZPyZEKOG373JJSBJFEbDd7Jb/SGwIZOqu3h+E1RRoSO7zAXl2JSyRB4WdwFx112VQBFpHWigJhpypNp6HMZWTS1IxH0SenSr3tm7ak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618605793; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=WjEwVAnQYcxJ7I3m6dSoDCzJdBuHuaFv8PxF4GDKcz8=; b=NKTq3nN+9JGh/92aMBIi41UsyQla1INwmhBbszlQQ/tZZBHDAWBWyM5jaB/L2LtMiT2PA4CV6uxhn+jGfhxauA9dKGLOqde9po72JXjk5VMZsBGAGxn2wjEpleKm4NFkYorxg6mOWEERPLuraz3IfsbPxQglnl13RE00YIwJRWA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74219+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1618605793607712.6999685774114; Fri, 16 Apr 2021 13:43:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3cogYY1788612xLMjigNfiBJ; Fri, 16 Apr 2021 13:43:13 -0700 X-Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) by mx.groups.io with SMTP id smtpd.web10.2538.1618605792041513547 for ; Fri, 16 Apr 2021 13:43:12 -0700 X-Received: by mail-lf1-f53.google.com with SMTP id i10so10802723lfe.11 for ; Fri, 16 Apr 2021 13:43:11 -0700 (PDT) X-Gm-Message-State: 1zu0DZ7ooGhLcX14qpSvASnYx1787277AA= X-Google-Smtp-Source: ABdhPJwVvnvUspDDMOVFDFHEMJEVj0g0zB882ySvhI/7vl+p/dKclb2CXUjcBGXf2KCnsajqx2B+Iw== X-Received: by 2002:a05:6512:969:: with SMTP id v9mr4155808lft.466.1618605790009; Fri, 16 Apr 2021 13:43:10 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (host-193.106.246.138.static.3s.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id h17sm1071346lfu.153.2021.04.16.13.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 13:43:09 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com Subject: [edk2-devel] [edk2-non-osi PATCH] Marvell: Update device trees Date: Fri, 16 Apr 2021 22:42:26 +0200 Message-Id: <20210416204226.354914-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1618605793; bh=GkfEZTz2q5l+GbAX705o3hqPx8DeRqMaayI7fEUZgnY=; h=Cc:Date:From:Reply-To:Subject:To; b=g/rfFcTvw5VKoYdrWUa6rRUUKUS6O/TC5nhIOsJpVw3LKASwa2ICVom9Zan+QnlQfNa 3XbSLu8QmvqgXQ4EjN5PAD4bO0lJHbCPA9UovER3ATr9BZH9Cx8wgUzQQ3PFnqesaiOg1 yxLZAK8KA12SZTM99F99Y4H9RevG6imv9Ig= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The recent device tree modifications for the platforms based on the Marvell SoCs were merged in their initial revision. Perform a desired update from the final version. Changes included: * Align DT sources to the upcoming Linux v5.12 * Revert ahci nodes changes for Armada7k8k and OcteonTx * Remove unused ICU-related defines and armada-ap807.dtsi from Armada7k8k DT sources * Enable 10G ports on Cn913xDB Signed-off-by: Marcin Wojtas Acked-by: Ard Biesheuvel --- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi | 3 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi | 33 --------= ------------ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi | 3 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi | 23 ++++++++= ------ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi | 4 ++- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi | 3 ++ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi | 18 ++++++++= --- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts | 3 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts | 2 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts | 2 +- 10 files changed, 43 insertions(+), 51 deletions(-) delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi index 970e875..4935e05 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi @@ -175,7 +175,8 @@ }; =20 &cp0_pcie0 { - compatible =3D "marvell,armada8k-pcie-ecam", "pci-host-ecam-generi= c"; + compatible =3D "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam", + "pci-host-ecam-generic"; reg =3D <0 0xe0000000 0 0xff00000>; bus-range =3D <0 0xfe>; pinctrl-names =3D "default"; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi deleted file mode 100644 index b42dc3a..0000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada AP807 - * - * Copyright (C) 2019 Marvell Technology Group Ltd. - */ - -#define AP_NAME ap807 -#include "armada-ap80x.dtsi" - -/ { - model =3D "Marvell Armada AP807"; - compatible =3D "marvell,armada-ap807"; -}; - -&ap_syscon0 { - ap_clk: clock { - compatible =3D "marvell,ap807-clock"; - #clock-cells =3D <1>; - }; -}; - -&ap_syscon1 { - cpu_clk: clock-cpu { - compatible =3D "marvell,ap807-cpu-clock"; - clocks =3D <&ap_clk 0>, <&ap_clk 1>; - #clock-cells =3D <1>; - }; -}; - -&ap_sdhci0 { - compatible =3D "marvell,armada-ap807-sdhci"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi index c2a7cef..805d782 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi @@ -290,6 +290,9 @@ gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>; + marvell,pwm-offset =3D <0x10c0>; + #pwm-cells =3D <2>; + clocks =3D <&ap_clk 3>; }; }; =20 diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi index 7f26842..c309aaa 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi @@ -5,11 +5,6 @@ * Device Tree file for Marvell Armada CP11x. */ =20 -#define ICU_GRP_NSR 0x0 -#define ICU_GRP_SR 0x1 -#define ICU_GRP_SEI 0x4 -#define ICU_GRP_REI 0x5 - #include "armada-common.dtsi" =20 #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) += CP11X_PCIEx_MEM_SIZE(iface)) @@ -61,7 +56,7 @@ =20 CP11X_LABEL(ethernet): ethernet@0 { compatible =3D "marvell,armada-7k-pp22"; - reg =3D <0x0 0x100000>, <0x129000 0xb000>; + reg =3D <0x0 0x100000>, <0x129000 0xb000>, <0x2200= 00 0x800>; clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>, <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(c= ore_clk)>, <&CP11X_LABEL(core_clk)>; @@ -238,12 +233,17 @@ gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 0= 32>; + marvell,pwm-offset =3D <0x1f0>; + #pwm-cells =3D <2>; interrupt-controller; interrupts =3D <86 IRQ_TYPE_LEVEL_HIGH>, <85 IRQ_TYPE_LEVEL_HIGH>, <84 IRQ_TYPE_LEVEL_HIGH>, <83 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <2>; + clock-names =3D "core", "axi"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; status =3D "disabled"; }; =20 @@ -254,12 +254,17 @@ gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 3= 2 31>; + marvell,pwm-offset =3D <0x1f0>; + #pwm-cells =3D <2>; interrupt-controller; interrupts =3D <82 IRQ_TYPE_LEVEL_HIGH>, <81 IRQ_TYPE_LEVEL_HIGH>, <80 IRQ_TYPE_LEVEL_HIGH>, <79 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <2>; + clock-names =3D "core", "axi"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; status =3D "disabled"; }; }; @@ -304,9 +309,11 @@ }; =20 CP11X_LABEL(sata0): sata@540000 { - compatible =3D "marvell,armada-8k-ahci"; + compatible =3D "marvell,armada-8k-ahci", + "generic-ahci"; reg =3D <0x540000 0x30000>; dma-coherent; + interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>; clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(core_clk)>; #address-cells =3D <1>; @@ -314,12 +321,10 @@ status =3D "disabled"; =20 sata-port@0 { - interrupts =3D <109 IRQ_TYPE_LEVEL_HIGH>; reg =3D <0>; }; =20 sata-port@1 { - interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>; reg =3D <1>; }; }; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi index b42dc3a..0b36eb8 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi @@ -29,5 +29,7 @@ }; =20 &ap_sdhci0 { - compatible =3D "marvell,armada-ap807-sdhci"; + compatible =3D "marvell,armada-ap807-sdhci", + "marvell,armada-ap806-sdhci"; /* Backward compatibili= ty */ }; + diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi index c2a7cef..805d782 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi @@ -290,6 +290,9 @@ gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>; + marvell,pwm-offset =3D <0x10c0>; + #pwm-cells =3D <2>; + clocks =3D <&ap_clk 3>; }; }; =20 diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi index 05b7627..c309aaa 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi @@ -56,7 +56,7 @@ =20 CP11X_LABEL(ethernet): ethernet@0 { compatible =3D "marvell,armada-7k-pp22"; - reg =3D <0x0 0x100000>, <0x129000 0xb000>; + reg =3D <0x0 0x100000>, <0x129000 0xb000>, <0x2200= 00 0x800>; clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>, <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(c= ore_clk)>, <&CP11X_LABEL(core_clk)>; @@ -233,12 +233,17 @@ gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 0= 32>; + marvell,pwm-offset =3D <0x1f0>; + #pwm-cells =3D <2>; interrupt-controller; interrupts =3D <86 IRQ_TYPE_LEVEL_HIGH>, <85 IRQ_TYPE_LEVEL_HIGH>, <84 IRQ_TYPE_LEVEL_HIGH>, <83 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <2>; + clock-names =3D "core", "axi"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; status =3D "disabled"; }; =20 @@ -249,12 +254,17 @@ gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 3= 2 31>; + marvell,pwm-offset =3D <0x1f0>; + #pwm-cells =3D <2>; interrupt-controller; interrupts =3D <82 IRQ_TYPE_LEVEL_HIGH>, <81 IRQ_TYPE_LEVEL_HIGH>, <80 IRQ_TYPE_LEVEL_HIGH>, <79 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <2>; + clock-names =3D "core", "axi"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; status =3D "disabled"; }; }; @@ -299,9 +309,11 @@ }; =20 CP11X_LABEL(sata0): sata@540000 { - compatible =3D "marvell,armada-8k-ahci"; + compatible =3D "marvell,armada-8k-ahci", + "generic-ahci"; reg =3D <0x540000 0x30000>; dma-coherent; + interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>; clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(core_clk)>; #address-cells =3D <1>; @@ -309,12 +321,10 @@ status =3D "disabled"; =20 sata-port@0 { - interrupts =3D <109 IRQ_TYPE_LEVEL_HIGH>; reg =3D <0>; }; =20 sata-port@1 { - interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>; reg =3D <1>; }; }; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts index 747bf88..7f54f36 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts @@ -127,7 +127,7 @@ =20 /* SLM-1521-V2, CON9 */ &cp0_eth0 { - status =3D "disabled"; + status =3D "okay"; phy-mode =3D "10gbase-kr"; /* Generic PHY, providing serdes lanes */ phys =3D <&cp0_comphy4 0>; @@ -306,6 +306,7 @@ =20 /* U55 */ &cp0_spi1 { + status =3D "disabled"; pinctrl-names =3D "default"; pinctrl-0 =3D <&cp0_spi0_pins>; reg =3D <0x700680 0x50>; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts index a321810..3d5a67e 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts @@ -85,7 +85,7 @@ =20 /* CON50 */ &cp1_eth0 { - status =3D "disabled"; + status =3D "okay"; phy-mode =3D "10gbase-kr"; /* Generic PHY, providing serdes lanes */ phys =3D <&cp1_comphy4 0>; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts index 8cb08ca..81ff188 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts @@ -103,7 +103,7 @@ =20 /* SLM-1521-V2, CON9 */ &cp2_eth0 { - status =3D "disabled"; + status =3D "okay"; phy-mode =3D "10gbase-kr"; /* Generic PHY, providing serdes lanes */ phys =3D <&cp2_comphy4 0>; --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74219): https://edk2.groups.io/g/devel/message/74219 Mute This Topic: https://groups.io/mt/82152570/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-