Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi | 3 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi | 33 -------------------- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi | 3 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi | 23 ++++++++------ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi | 4 ++- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi | 3 ++ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi | 18 ++++++++--- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts | 3 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts | 2 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts | 2 +- 10 files changed, 43 insertions(+), 51 deletions(-) delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi
The recent device tree modifications for the platforms
based on the Marvell SoCs were merged in their initial
revision. Perform a desired update from the final version.
Changes included:
* Align DT sources to the upcoming Linux v5.12
* Revert ahci nodes changes for Armada7k8k and OcteonTx
* Remove unused ICU-related defines and armada-ap807.dtsi
from Armada7k8k DT sources
* Enable 10G ports on Cn913xDB
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi | 3 +-
Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi | 33 --------------------
Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi | 3 ++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi | 23 ++++++++------
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi | 4 ++-
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi | 3 ++
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi | 18 ++++++++---
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts | 3 +-
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts | 2 +-
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts | 2 +-
10 files changed, 43 insertions(+), 51 deletions(-)
delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi
index 970e875..4935e05 100644
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi
@@ -175,7 +175,8 @@
};
&cp0_pcie0 {
- compatible = "marvell,armada8k-pcie-ecam", "pci-host-ecam-generic";
+ compatible = "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam",
+ "pci-host-ecam-generic";
reg = <0 0xe0000000 0 0xff00000>;
bus-range = <0 0xfe>;
pinctrl-names = "default";
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi
deleted file mode 100644
index b42dc3a..0000000
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree file for Marvell Armada AP807
- *
- * Copyright (C) 2019 Marvell Technology Group Ltd.
- */
-
-#define AP_NAME ap807
-#include "armada-ap80x.dtsi"
-
-/ {
- model = "Marvell Armada AP807";
- compatible = "marvell,armada-ap807";
-};
-
-&ap_syscon0 {
- ap_clk: clock {
- compatible = "marvell,ap807-clock";
- #clock-cells = <1>;
- };
-};
-
-&ap_syscon1 {
- cpu_clk: clock-cpu {
- compatible = "marvell,ap807-cpu-clock";
- clocks = <&ap_clk 0>, <&ap_clk 1>;
- #clock-cells = <1>;
- };
-};
-
-&ap_sdhci0 {
- compatible = "marvell,armada-ap807-sdhci";
-};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi
index c2a7cef..805d782 100644
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi
@@ -290,6 +290,9 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&ap_pinctrl 0 0 20>;
+ marvell,pwm-offset = <0x10c0>;
+ #pwm-cells = <2>;
+ clocks = <&ap_clk 3>;
};
};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi
index 7f26842..c309aaa 100644
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi
@@ -5,11 +5,6 @@
* Device Tree file for Marvell Armada CP11x.
*/
-#define ICU_GRP_NSR 0x0
-#define ICU_GRP_SR 0x1
-#define ICU_GRP_SEI 0x4
-#define ICU_GRP_REI 0x5
-
#include "armada-common.dtsi"
#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
@@ -61,7 +56,7 @@
CP11X_LABEL(ethernet): ethernet@0 {
compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>;
+ reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
clocks = <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(ppv2_clk)>,
<&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(core_clk)>,
<&CP11X_LABEL(core_clk)>;
@@ -238,12 +233,17 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
+ marvell,pwm-offset = <0x1f0>;
+ #pwm-cells = <2>;
interrupt-controller;
interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
<85 IRQ_TYPE_LEVEL_HIGH>,
<84 IRQ_TYPE_LEVEL_HIGH>,
<83 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
status = "disabled";
};
@@ -254,12 +254,17 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
+ marvell,pwm-offset = <0x1f0>;
+ #pwm-cells = <2>;
interrupt-controller;
interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
<81 IRQ_TYPE_LEVEL_HIGH>,
<80 IRQ_TYPE_LEVEL_HIGH>,
<79 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
status = "disabled";
};
};
@@ -304,9 +309,11 @@
};
CP11X_LABEL(sata0): sata@540000 {
- compatible = "marvell,armada-8k-ahci";
+ compatible = "marvell,armada-8k-ahci",
+ "generic-ahci";
reg = <0x540000 0x30000>;
dma-coherent;
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP11X_LABEL(core_clk)>,
<&CP11X_LABEL(core_clk)>;
#address-cells = <1>;
@@ -314,12 +321,10 @@
status = "disabled";
sata-port@0 {
- interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
reg = <0>;
};
sata-port@1 {
- interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
reg = <1>;
};
};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi
index b42dc3a..0b36eb8 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi
@@ -29,5 +29,7 @@
};
&ap_sdhci0 {
- compatible = "marvell,armada-ap807-sdhci";
+ compatible = "marvell,armada-ap807-sdhci",
+ "marvell,armada-ap806-sdhci"; /* Backward compatibility */
};
+
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi
index c2a7cef..805d782 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi
@@ -290,6 +290,9 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&ap_pinctrl 0 0 20>;
+ marvell,pwm-offset = <0x10c0>;
+ #pwm-cells = <2>;
+ clocks = <&ap_clk 3>;
};
};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi
index 05b7627..c309aaa 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi
@@ -56,7 +56,7 @@
CP11X_LABEL(ethernet): ethernet@0 {
compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>;
+ reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
clocks = <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(ppv2_clk)>,
<&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(core_clk)>,
<&CP11X_LABEL(core_clk)>;
@@ -233,12 +233,17 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
+ marvell,pwm-offset = <0x1f0>;
+ #pwm-cells = <2>;
interrupt-controller;
interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
<85 IRQ_TYPE_LEVEL_HIGH>,
<84 IRQ_TYPE_LEVEL_HIGH>,
<83 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
status = "disabled";
};
@@ -249,12 +254,17 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
+ marvell,pwm-offset = <0x1f0>;
+ #pwm-cells = <2>;
interrupt-controller;
interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
<81 IRQ_TYPE_LEVEL_HIGH>,
<80 IRQ_TYPE_LEVEL_HIGH>,
<79 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(slow_io_clk)>,
+ <&CP11X_LABEL(x2core_clk)>;
status = "disabled";
};
};
@@ -299,9 +309,11 @@
};
CP11X_LABEL(sata0): sata@540000 {
- compatible = "marvell,armada-8k-ahci";
+ compatible = "marvell,armada-8k-ahci",
+ "generic-ahci";
reg = <0x540000 0x30000>;
dma-coherent;
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP11X_LABEL(core_clk)>,
<&CP11X_LABEL(core_clk)>;
#address-cells = <1>;
@@ -309,12 +321,10 @@
status = "disabled";
sata-port@0 {
- interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
reg = <0>;
};
sata-port@1 {
- interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
reg = <1>;
};
};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts
index 747bf88..7f54f36 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts
@@ -127,7 +127,7 @@
/* SLM-1521-V2, CON9 */
&cp0_eth0 {
- status = "disabled";
+ status = "okay";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cp0_comphy4 0>;
@@ -306,6 +306,7 @@
/* U55 */
&cp0_spi1 {
+ status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>;
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts
index a321810..3d5a67e 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts
@@ -85,7 +85,7 @@
/* CON50 */
&cp1_eth0 {
- status = "disabled";
+ status = "okay";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cp1_comphy4 0>;
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts
index 8cb08ca..81ff188 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts
@@ -103,7 +103,7 @@
/* SLM-1521-V2, CON9 */
&cp2_eth0 {
- status = "disabled";
+ status = "okay";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cp2_comphy4 0>;
--
2.29.0
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On Fri, 16 Apr 2021 at 22:43, Marcin Wojtas <mw@semihalf.com> wrote: > > The recent device tree modifications for the platforms > based on the Marvell SoCs were merged in their initial > revision. Perform a desired update from the final version. > Changes included: > * Align DT sources to the upcoming Linux v5.12 > * Revert ahci nodes changes for Armada7k8k and OcteonTx > * Remove unused ICU-related defines and armada-ap807.dtsi > from Armada7k8k DT sources > * Enable 10G ports on Cn913xDB > > Signed-off-by: Marcin Wojtas <mw@semihalf.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Pushed as fdd2ef2b3edb..f9b9957d6609 > --- > Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi | 3 +- > Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi | 33 -------------------- > Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi | 3 ++ > Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi | 23 ++++++++------ > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi | 4 ++- > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi | 3 ++ > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi | 18 ++++++++--- > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts | 3 +- > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts | 2 +- > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts | 2 +- > 10 files changed, 43 insertions(+), 51 deletions(-) > delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi > > diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi > index 970e875..4935e05 100644 > --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi > +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi > @@ -175,7 +175,8 @@ > }; > > &cp0_pcie0 { > - compatible = "marvell,armada8k-pcie-ecam", "pci-host-ecam-generic"; > + compatible = "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam", > + "pci-host-ecam-generic"; > reg = <0 0xe0000000 0 0xff00000>; > bus-range = <0 0xfe>; > pinctrl-names = "default"; > diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi > deleted file mode 100644 > index b42dc3a..0000000 > --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi > +++ /dev/null > @@ -1,33 +0,0 @@ > -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > -/* > - * Device Tree file for Marvell Armada AP807 > - * > - * Copyright (C) 2019 Marvell Technology Group Ltd. > - */ > - > -#define AP_NAME ap807 > -#include "armada-ap80x.dtsi" > - > -/ { > - model = "Marvell Armada AP807"; > - compatible = "marvell,armada-ap807"; > -}; > - > -&ap_syscon0 { > - ap_clk: clock { > - compatible = "marvell,ap807-clock"; > - #clock-cells = <1>; > - }; > -}; > - > -&ap_syscon1 { > - cpu_clk: clock-cpu { > - compatible = "marvell,ap807-cpu-clock"; > - clocks = <&ap_clk 0>, <&ap_clk 1>; > - #clock-cells = <1>; > - }; > -}; > - > -&ap_sdhci0 { > - compatible = "marvell,armada-ap807-sdhci"; > -}; > diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi > index c2a7cef..805d782 100644 > --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi > +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi > @@ -290,6 +290,9 @@ > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&ap_pinctrl 0 0 20>; > + marvell,pwm-offset = <0x10c0>; > + #pwm-cells = <2>; > + clocks = <&ap_clk 3>; > }; > }; > > diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi > index 7f26842..c309aaa 100644 > --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi > +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi > @@ -5,11 +5,6 @@ > * Device Tree file for Marvell Armada CP11x. > */ > > -#define ICU_GRP_NSR 0x0 > -#define ICU_GRP_SR 0x1 > -#define ICU_GRP_SEI 0x4 > -#define ICU_GRP_REI 0x5 > - > #include "armada-common.dtsi" > > #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface)) > @@ -61,7 +56,7 @@ > > CP11X_LABEL(ethernet): ethernet@0 { > compatible = "marvell,armada-7k-pp22"; > - reg = <0x0 0x100000>, <0x129000 0xb000>; > + reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; > clocks = <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(ppv2_clk)>, > <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(core_clk)>, > <&CP11X_LABEL(core_clk)>; > @@ -238,12 +233,17 @@ > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; > + marvell,pwm-offset = <0x1f0>; > + #pwm-cells = <2>; > interrupt-controller; > interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, > <85 IRQ_TYPE_LEVEL_HIGH>, > <84 IRQ_TYPE_LEVEL_HIGH>, > <83 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <2>; > + clock-names = "core", "axi"; > + clocks = <&CP11X_LABEL(slow_io_clk)>, > + <&CP11X_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -254,12 +254,17 @@ > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; > + marvell,pwm-offset = <0x1f0>; > + #pwm-cells = <2>; > interrupt-controller; > interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, > <81 IRQ_TYPE_LEVEL_HIGH>, > <80 IRQ_TYPE_LEVEL_HIGH>, > <79 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <2>; > + clock-names = "core", "axi"; > + clocks = <&CP11X_LABEL(slow_io_clk)>, > + <&CP11X_LABEL(x2core_clk)>; > status = "disabled"; > }; > }; > @@ -304,9 +309,11 @@ > }; > > CP11X_LABEL(sata0): sata@540000 { > - compatible = "marvell,armada-8k-ahci"; > + compatible = "marvell,armada-8k-ahci", > + "generic-ahci"; > reg = <0x540000 0x30000>; > dma-coherent; > + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&CP11X_LABEL(core_clk)>, > <&CP11X_LABEL(core_clk)>; > #address-cells = <1>; > @@ -314,12 +321,10 @@ > status = "disabled"; > > sata-port@0 { > - interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; > reg = <0>; > }; > > sata-port@1 { > - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; > reg = <1>; > }; > }; > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi > index b42dc3a..0b36eb8 100644 > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi > @@ -29,5 +29,7 @@ > }; > > &ap_sdhci0 { > - compatible = "marvell,armada-ap807-sdhci"; > + compatible = "marvell,armada-ap807-sdhci", > + "marvell,armada-ap806-sdhci"; /* Backward compatibility */ > }; > + > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi > index c2a7cef..805d782 100644 > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi > @@ -290,6 +290,9 @@ > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&ap_pinctrl 0 0 20>; > + marvell,pwm-offset = <0x10c0>; > + #pwm-cells = <2>; > + clocks = <&ap_clk 3>; > }; > }; > > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi > index 05b7627..c309aaa 100644 > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi > @@ -56,7 +56,7 @@ > > CP11X_LABEL(ethernet): ethernet@0 { > compatible = "marvell,armada-7k-pp22"; > - reg = <0x0 0x100000>, <0x129000 0xb000>; > + reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; > clocks = <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(ppv2_clk)>, > <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(core_clk)>, > <&CP11X_LABEL(core_clk)>; > @@ -233,12 +233,17 @@ > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; > + marvell,pwm-offset = <0x1f0>; > + #pwm-cells = <2>; > interrupt-controller; > interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, > <85 IRQ_TYPE_LEVEL_HIGH>, > <84 IRQ_TYPE_LEVEL_HIGH>, > <83 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <2>; > + clock-names = "core", "axi"; > + clocks = <&CP11X_LABEL(slow_io_clk)>, > + <&CP11X_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -249,12 +254,17 @@ > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; > + marvell,pwm-offset = <0x1f0>; > + #pwm-cells = <2>; > interrupt-controller; > interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, > <81 IRQ_TYPE_LEVEL_HIGH>, > <80 IRQ_TYPE_LEVEL_HIGH>, > <79 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <2>; > + clock-names = "core", "axi"; > + clocks = <&CP11X_LABEL(slow_io_clk)>, > + <&CP11X_LABEL(x2core_clk)>; > status = "disabled"; > }; > }; > @@ -299,9 +309,11 @@ > }; > > CP11X_LABEL(sata0): sata@540000 { > - compatible = "marvell,armada-8k-ahci"; > + compatible = "marvell,armada-8k-ahci", > + "generic-ahci"; > reg = <0x540000 0x30000>; > dma-coherent; > + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&CP11X_LABEL(core_clk)>, > <&CP11X_LABEL(core_clk)>; > #address-cells = <1>; > @@ -309,12 +321,10 @@ > status = "disabled"; > > sata-port@0 { > - interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; > reg = <0>; > }; > > sata-port@1 { > - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; > reg = <1>; > }; > }; > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts > index 747bf88..7f54f36 100644 > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts > @@ -127,7 +127,7 @@ > > /* SLM-1521-V2, CON9 */ > &cp0_eth0 { > - status = "disabled"; > + status = "okay"; > phy-mode = "10gbase-kr"; > /* Generic PHY, providing serdes lanes */ > phys = <&cp0_comphy4 0>; > @@ -306,6 +306,7 @@ > > /* U55 */ > &cp0_spi1 { > + status = "disabled"; > pinctrl-names = "default"; > pinctrl-0 = <&cp0_spi0_pins>; > reg = <0x700680 0x50>; > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts > index a321810..3d5a67e 100644 > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts > @@ -85,7 +85,7 @@ > > /* CON50 */ > &cp1_eth0 { > - status = "disabled"; > + status = "okay"; > phy-mode = "10gbase-kr"; > /* Generic PHY, providing serdes lanes */ > phys = <&cp1_comphy4 0>; > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts > index 8cb08ca..81ff188 100644 > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts > @@ -103,7 +103,7 @@ > > /* SLM-1521-V2, CON9 */ > &cp2_eth0 { > - status = "disabled"; > + status = "okay"; > phy-mode = "10gbase-kr"; > /* Generic PHY, providing serdes lanes */ > phys = <&cp2_comphy4 0>; > -- > 2.29.0 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74248): https://edk2.groups.io/g/devel/message/74248 Mute This Topic: https://groups.io/mt/82152570/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
pon., 19 kwi 2021 o 09:38 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > On Fri, 16 Apr 2021 at 22:43, Marcin Wojtas <mw@semihalf.com> wrote: > > > > The recent device tree modifications for the platforms > > based on the Marvell SoCs were merged in their initial > > revision. Perform a desired update from the final version. > > Changes included: > > * Align DT sources to the upcoming Linux v5.12 > > * Revert ahci nodes changes for Armada7k8k and OcteonTx > > * Remove unused ICU-related defines and armada-ap807.dtsi > > from Armada7k8k DT sources > > * Enable 10G ports on Cn913xDB > > > > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > > Acked-by: Ard Biesheuvel <ardb@kernel.org> > > Pushed as fdd2ef2b3edb..f9b9957d6609 > Thanks! Marcin > > > --- > > Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi | 3 +- > > Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi | 33 -------------------- > > Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi | 3 ++ > > Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi | 23 ++++++++------ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi | 4 ++- > > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi | 3 ++ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi | 18 ++++++++--- > > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts | 3 +- > > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts | 2 +- > > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts | 2 +- > > 10 files changed, 43 insertions(+), 51 deletions(-) > > delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi > > > > diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi > > index 970e875..4935e05 100644 > > --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi > > +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi > > @@ -175,7 +175,8 @@ > > }; > > > > &cp0_pcie0 { > > - compatible = "marvell,armada8k-pcie-ecam", "pci-host-ecam-generic"; > > + compatible = "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam", > > + "pci-host-ecam-generic"; > > reg = <0 0xe0000000 0 0xff00000>; > > bus-range = <0 0xfe>; > > pinctrl-names = "default"; > > diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi > > deleted file mode 100644 > > index b42dc3a..0000000 > > --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi > > +++ /dev/null > > @@ -1,33 +0,0 @@ > > -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > -/* > > - * Device Tree file for Marvell Armada AP807 > > - * > > - * Copyright (C) 2019 Marvell Technology Group Ltd. > > - */ > > - > > -#define AP_NAME ap807 > > -#include "armada-ap80x.dtsi" > > - > > -/ { > > - model = "Marvell Armada AP807"; > > - compatible = "marvell,armada-ap807"; > > -}; > > - > > -&ap_syscon0 { > > - ap_clk: clock { > > - compatible = "marvell,ap807-clock"; > > - #clock-cells = <1>; > > - }; > > -}; > > - > > -&ap_syscon1 { > > - cpu_clk: clock-cpu { > > - compatible = "marvell,ap807-cpu-clock"; > > - clocks = <&ap_clk 0>, <&ap_clk 1>; > > - #clock-cells = <1>; > > - }; > > -}; > > - > > -&ap_sdhci0 { > > - compatible = "marvell,armada-ap807-sdhci"; > > -}; > > diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi > > index c2a7cef..805d782 100644 > > --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi > > +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi > > @@ -290,6 +290,9 @@ > > gpio-controller; > > #gpio-cells = <2>; > > gpio-ranges = <&ap_pinctrl 0 0 20>; > > + marvell,pwm-offset = <0x10c0>; > > + #pwm-cells = <2>; > > + clocks = <&ap_clk 3>; > > }; > > }; > > > > diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi > > index 7f26842..c309aaa 100644 > > --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi > > +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi > > @@ -5,11 +5,6 @@ > > * Device Tree file for Marvell Armada CP11x. > > */ > > > > -#define ICU_GRP_NSR 0x0 > > -#define ICU_GRP_SR 0x1 > > -#define ICU_GRP_SEI 0x4 > > -#define ICU_GRP_REI 0x5 > > - > > #include "armada-common.dtsi" > > > > #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface)) > > @@ -61,7 +56,7 @@ > > > > CP11X_LABEL(ethernet): ethernet@0 { > > compatible = "marvell,armada-7k-pp22"; > > - reg = <0x0 0x100000>, <0x129000 0xb000>; > > + reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; > > clocks = <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(ppv2_clk)>, > > <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(core_clk)>, > > <&CP11X_LABEL(core_clk)>; > > @@ -238,12 +233,17 @@ > > gpio-controller; > > #gpio-cells = <2>; > > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; > > + marvell,pwm-offset = <0x1f0>; > > + #pwm-cells = <2>; > > interrupt-controller; > > interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, > > <85 IRQ_TYPE_LEVEL_HIGH>, > > <84 IRQ_TYPE_LEVEL_HIGH>, > > <83 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <2>; > > + clock-names = "core", "axi"; > > + clocks = <&CP11X_LABEL(slow_io_clk)>, > > + <&CP11X_LABEL(x2core_clk)>; > > status = "disabled"; > > }; > > > > @@ -254,12 +254,17 @@ > > gpio-controller; > > #gpio-cells = <2>; > > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; > > + marvell,pwm-offset = <0x1f0>; > > + #pwm-cells = <2>; > > interrupt-controller; > > interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, > > <81 IRQ_TYPE_LEVEL_HIGH>, > > <80 IRQ_TYPE_LEVEL_HIGH>, > > <79 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <2>; > > + clock-names = "core", "axi"; > > + clocks = <&CP11X_LABEL(slow_io_clk)>, > > + <&CP11X_LABEL(x2core_clk)>; > > status = "disabled"; > > }; > > }; > > @@ -304,9 +309,11 @@ > > }; > > > > CP11X_LABEL(sata0): sata@540000 { > > - compatible = "marvell,armada-8k-ahci"; > > + compatible = "marvell,armada-8k-ahci", > > + "generic-ahci"; > > reg = <0x540000 0x30000>; > > dma-coherent; > > + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; > > clocks = <&CP11X_LABEL(core_clk)>, > > <&CP11X_LABEL(core_clk)>; > > #address-cells = <1>; > > @@ -314,12 +321,10 @@ > > status = "disabled"; > > > > sata-port@0 { > > - interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; > > reg = <0>; > > }; > > > > sata-port@1 { > > - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; > > reg = <1>; > > }; > > }; > > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi > > index b42dc3a..0b36eb8 100644 > > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi > > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi > > @@ -29,5 +29,7 @@ > > }; > > > > &ap_sdhci0 { > > - compatible = "marvell,armada-ap807-sdhci"; > > + compatible = "marvell,armada-ap807-sdhci", > > + "marvell,armada-ap806-sdhci"; /* Backward compatibility */ > > }; > > + > > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi > > index c2a7cef..805d782 100644 > > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi > > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi > > @@ -290,6 +290,9 @@ > > gpio-controller; > > #gpio-cells = <2>; > > gpio-ranges = <&ap_pinctrl 0 0 20>; > > + marvell,pwm-offset = <0x10c0>; > > + #pwm-cells = <2>; > > + clocks = <&ap_clk 3>; > > }; > > }; > > > > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi > > index 05b7627..c309aaa 100644 > > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi > > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi > > @@ -56,7 +56,7 @@ > > > > CP11X_LABEL(ethernet): ethernet@0 { > > compatible = "marvell,armada-7k-pp22"; > > - reg = <0x0 0x100000>, <0x129000 0xb000>; > > + reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; > > clocks = <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(ppv2_clk)>, > > <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(core_clk)>, > > <&CP11X_LABEL(core_clk)>; > > @@ -233,12 +233,17 @@ > > gpio-controller; > > #gpio-cells = <2>; > > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; > > + marvell,pwm-offset = <0x1f0>; > > + #pwm-cells = <2>; > > interrupt-controller; > > interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, > > <85 IRQ_TYPE_LEVEL_HIGH>, > > <84 IRQ_TYPE_LEVEL_HIGH>, > > <83 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <2>; > > + clock-names = "core", "axi"; > > + clocks = <&CP11X_LABEL(slow_io_clk)>, > > + <&CP11X_LABEL(x2core_clk)>; > > status = "disabled"; > > }; > > > > @@ -249,12 +254,17 @@ > > gpio-controller; > > #gpio-cells = <2>; > > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; > > + marvell,pwm-offset = <0x1f0>; > > + #pwm-cells = <2>; > > interrupt-controller; > > interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, > > <81 IRQ_TYPE_LEVEL_HIGH>, > > <80 IRQ_TYPE_LEVEL_HIGH>, > > <79 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <2>; > > + clock-names = "core", "axi"; > > + clocks = <&CP11X_LABEL(slow_io_clk)>, > > + <&CP11X_LABEL(x2core_clk)>; > > status = "disabled"; > > }; > > }; > > @@ -299,9 +309,11 @@ > > }; > > > > CP11X_LABEL(sata0): sata@540000 { > > - compatible = "marvell,armada-8k-ahci"; > > + compatible = "marvell,armada-8k-ahci", > > + "generic-ahci"; > > reg = <0x540000 0x30000>; > > dma-coherent; > > + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; > > clocks = <&CP11X_LABEL(core_clk)>, > > <&CP11X_LABEL(core_clk)>; > > #address-cells = <1>; > > @@ -309,12 +321,10 @@ > > status = "disabled"; > > > > sata-port@0 { > > - interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; > > reg = <0>; > > }; > > > > sata-port@1 { > > - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; > > reg = <1>; > > }; > > }; > > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts > > index 747bf88..7f54f36 100644 > > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts > > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts > > @@ -127,7 +127,7 @@ > > > > /* SLM-1521-V2, CON9 */ > > &cp0_eth0 { > > - status = "disabled"; > > + status = "okay"; > > phy-mode = "10gbase-kr"; > > /* Generic PHY, providing serdes lanes */ > > phys = <&cp0_comphy4 0>; > > @@ -306,6 +306,7 @@ > > > > /* U55 */ > > &cp0_spi1 { > > + status = "disabled"; > > pinctrl-names = "default"; > > pinctrl-0 = <&cp0_spi0_pins>; > > reg = <0x700680 0x50>; > > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts > > index a321810..3d5a67e 100644 > > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts > > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts > > @@ -85,7 +85,7 @@ > > > > /* CON50 */ > > &cp1_eth0 { > > - status = "disabled"; > > + status = "okay"; > > phy-mode = "10gbase-kr"; > > /* Generic PHY, providing serdes lanes */ > > phys = <&cp1_comphy4 0>; > > diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts > > index 8cb08ca..81ff188 100644 > > --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts > > +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts > > @@ -103,7 +103,7 @@ > > > > /* SLM-1521-V2, CON9 */ > > &cp2_eth0 { > > - status = "disabled"; > > + status = "okay"; > > phy-mode = "10gbase-kr"; > > /* Generic PHY, providing serdes lanes */ > > phys = <&cp2_comphy4 0>; > > -- > > 2.29.0 > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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