From nobody Sat Apr 27 04:16:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74115+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74115+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1618469337; cv=none; d=zohomail.com; s=zohoarc; b=CF5mbgqf8nTCli/UHqRCRYednwoYcH+/1WGysKajdMqiPN2RfvERQVaR1WM4NBQltt/0hlwQYzqm0Dag4UXfT/cWhXJwRJQzHkVaVmmRAqMgcRa/exHnqGtnH6EqYUOwrXHe+u8TZ7HFqLvvZ5JOpX5Gbz5u+eEbgs6REYkkvRw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618469337; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=dPXAOFdYJUR4VhLedTpydXelPH4tvo7lYjvYm6pZxOo=; b=KGwGnwCAh20uOY+IiF9Ioh7LkbUxF/OvRTT4SRHOol7WcPoZAvOe5nAlsSoRRmFJMjXOYbIICM8nsJH+b+lV6Gr924TIP/NXnNRcDumq2d/vSiRR+KO6sXtI9eQk8RW5KG0mxZKwI4j3EU5UnoPPRUHEMTs/SxNsP5IudwvWTMQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74115+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1618469337450851.1327902614821; Wed, 14 Apr 2021 23:48:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id KbhVYY1788612xa8n3Ju3f3I; Wed, 14 Apr 2021 23:48:57 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.3510.1618469335090632056 for ; Wed, 14 Apr 2021 23:48:56 -0700 IronPort-SDR: VnRUbn6UYqM3ELPTmJ5EmO8XpSxztq2JlOZoRNZCGKjveRp/w+b+2RJE4eXPB1mT/EtVN/WhCS rVJz5/ds1eLg== X-IronPort-AV: E=McAfee;i="6200,9189,9954"; a="174903306" X-IronPort-AV: E=Sophos;i="5.82,223,1613462400"; d="scan'208";a="174903306" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2021 23:48:51 -0700 IronPort-SDR: ZPgb7lLLlfb0/DchAZwNj6mNfENPWa3LhWCnkBXhLLkuKmOC9+8aDxaXt11Emd/vIrD36CznJR 6+OOQ08JKKQQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,223,1613462400"; d="scan'208";a="383928620" X-Received: from shwdeopenlab102.ccr.corp.intel.com ([10.239.183.74]) by orsmga006.jf.intel.com with ESMTP; 14 Apr 2021 23:48:49 -0700 From: "Jason Lou" To: devel@edk2.groups.io Cc: Jason , Chasel Chiu , Nate DeSimone , Star Zeng , Ray Ni Subject: [edk2-devel] [PATCH v2] IntelFsp2WrapperPkg: Remove microcode related PCDs Date: Thu, 15 Apr 2021 14:48:47 +0800 Message-Id: <20210415064847.15537-1-yun.lou@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yun.lou@intel.com X-Gm-Message-State: 4gXdmMOQEL6lebEmu7XUKEP1x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1618469337; bh=uabkeJ70vL7FW4++udS/sFo6H++I0GCPDnBzCZJSzns=; h=Cc:Date:From:Reply-To:Subject:To; b=IUJe7K31ofbZUAmQWv9q8BJ04UjVm7GZVOmb5otD5M1fnP+w6z9a/zX+XwRX3Jc0xZb rRtPx9jrr/w59hADTgWQkT+NOpPQdPU90j+dk1J64C0PWiReLwHu9Va6RA8897h/nAfa0 7eWem/1orI4gGXWnrD+O9eWWkEsZL6bmGvA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3334 IntelFsp2WrapperPkg defines following PCDs: PcdCpuMicrocodePatchAddress PcdCpuMicrocodePatchRegionSize PcdFlashMicrocodeOffset But the PCD name caused confusion because UefiCpuPkg defines: PcdCpuMicrocodePatchAddress PcdCpuMicrocodePatchRegionSize PcdCpuMicrocodePatchAddress in IntelFsp2WrapperPkg means the base address of the FV that holds the microcode. PcdCpuMicrocodePatchAddress in UefiCpuPkg means the address of the microcode. The relationship between the PCDs is: IntelFsp2WrapperPkg.PcdCpuMicrocodePatchAddress + IntelFsp2WrapperPkg.PcdFlashMicrocodeOffset =3D=3D UefiCpuPkg.PcdCpuMicrocodePatchAddress IntelFsp2WrapperPkg.PcdCpuMicrocodePatchRegionSize - IntelFsp2WrapperPkg.PcdFlashMicrocodeOffset =3D=3D UefiCpuPkg.PcdCpuMicrocodePatchRegionSize To avoid confusion and actually the PCDs in IntelFsp2WrapperPkg are only used by a sample FSP-T wrapper, this patch removes the 3 PCDs defined in IntelFsp2WrapperPkg. The FSP-T wrapper is updated to directly use the ones in UefiCpuPkg. Signed-off-by: Jason Lou Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni Reviewed-by: Nate DeSimone --- IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitDa= ta.c | 6 +++--- IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec = | 8 +------- IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrappe= rPlatformSecLibSample.inf | 7 +++---- 3 files changed, 7 insertions(+), 14 deletions(-) diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/= SecRamInitData.c b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibS= ample/SecRamInitData.c index 96b47e23da..e57b5b57be 100644 --- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c +++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c @@ -1,7 +1,7 @@ /** @file Sample to provide TempRamInitParams data. =20 - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -52,8 +52,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA Fs= ptUpdDataPtr =3D { } }, { - ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (= PcdFlashMicrocodeOffset)), - ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet3= 2 (PcdFlashMicrocodeOffset)), + FixedPcdGet32 (PcdCpuMicrocodePatchAddress), + FixedPcdGet32 (PcdCpuMicrocodePatchRegionSize), FixedPcdGet32 (PcdFlashCodeCacheAddress), FixedPcdGet32 (PcdFlashCodeCacheSize), } diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec b/IntelFsp2Wrapper= Pkg/IntelFsp2WrapperPkg.dec index 6852bf1271..a3b9363779 100644 --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec @@ -1,7 +1,7 @@ ## @file # Provides drivers and definitions to support fsp in EDKII bios. # -# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -56,12 +56,6 @@ ## Provides the size of the BIOS Flash Device. gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|= 0x10000002 =20 - ## Indicates the base address of the first Microcode Patch in the Microc= ode Region - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0= x10000005 - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT6= 4|0x10000006 - ## Indicates the offset of the Cpu Microcode. - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset|0x90|UINT32|0x10= 000007 - ## Indicate the PEI memory size platform want to report gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x4000= 0004 ## Indicate the PEI memory size platform want to report diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/= SecFspWrapperPlatformSecLibSample.inf b/IntelFsp2WrapperPkg/Library/SecFspW= rapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf index d7f8301bef..027b127724 100644 --- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspW= rapperPlatformSecLibSample.inf +++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspW= rapperPlatformSecLibSample.inf @@ -1,7 +1,7 @@ ## @file # Sample to provide FSP wrapper platform sec related function. # -# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -76,8 +76,7 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSU= MES =20 [FixedPcd] - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSU= MES - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSU= MES - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## CONSU= MES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSU= MES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSU= MES gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## CONSU= MES gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## CONSU= MES --=20 2.28.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#74115): https://edk2.groups.io/g/devel/message/74115 Mute This Topic: https://groups.io/mt/82111237/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-