From nobody Thu Apr 25 07:57:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74102+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74102+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618431961; cv=none; d=zohomail.com; s=zohoarc; b=cn9Yn19C5yVSUIqe+y495dUBrfp6M5JHXnfYEECaUisDm4W96ns66u+aZSX3W74kw21tOBYzgzhPHtgbgCfVjOvXPuPqQiqAdOfA0FQACljAgzDYYxRFaCAejLWe5q1wbgmwTRhnWS/+aJbbEk8yqNmweaYzNg/FuJED5E99fro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618431961; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=9cm4k5np55wvMqgKG9xh8ycFMGGstysjMg2F8klvA1M=; b=T+kQ+TNE1uWWmnhiSPWxZaTyGhNZ7Hw1/RhOoQH0U8uIzfAcUWYUfPH3xmGGfxggNHOO6p2mqB10+Y49us4cRD/lDpLMvEpA5FX4Fo8cckgc2p5PBh1VKRfD7GMqtsMN7wYbfTXFyZo4Cchv4LEKo9nNfU7ZFXKsbc6tO+h4wrE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74102+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1618431961376557.3976093678527; Wed, 14 Apr 2021 13:26:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id RoahYY1788612xmCjAO2ALDy; Wed, 14 Apr 2021 13:26:00 -0700 X-Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) by mx.groups.io with SMTP id smtpd.web11.19498.1618431960441338472 for ; Wed, 14 Apr 2021 13:26:00 -0700 X-Received: by mail-pl1-f173.google.com with SMTP id w8so8457295plg.9 for ; Wed, 14 Apr 2021 13:26:00 -0700 (PDT) X-Gm-Message-State: UWMnkOqZfsVoEVvqOnk5zizkx1787277AA= X-Google-Smtp-Source: ABdhPJyMc2nlZgIwovLNwUiDoEJq3xaIzl3zyLoQ/OhRQ3BK3hOG7+KBrA7KJS+YzLhqBaf2vSqvbQ== X-Received: by 2002:a17:90a:3183:: with SMTP id j3mr3712047pjb.228.1618431959687; Wed, 14 Apr 2021 13:25:59 -0700 (PDT) X-Received: from localhost.localdomain ([50.35.88.161]) by smtp.gmail.com with ESMTPSA id q19sm336524pgv.38.2021.04.14.13.25.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 13:25:59 -0700 (PDT) From: "Kun Qin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar Subject: [edk2-devel] [PATCH v2 1/1] UefiCpuPkg: PiSmmCpuDxeSmm: Not to Change Bitwidth During Static Paging Date: Wed, 14 Apr 2021 13:25:47 -0700 Message-Id: <20210414202547.394-2-kuqin12@gmail.com> In-Reply-To: <20210414202547.394-1-kuqin12@gmail.com> References: <20210414202547.394-1-kuqin12@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kuqin12@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1618431960; bh=2FY8sVnpJUnmrVotDZ9wOlH9NEYHd3u/EBLZmC1WkNQ=; h=Cc:Date:From:Reply-To:Subject:To; b=w7SgoW3fwS7PFpAuEx+3WkSvkyVLcnZuByfn8OndkF+Obv+H0qjkFp9bHZlsrcU5OPA oGvy9E5GK4iWtMS+QUzNIzkb42QKshkh7FfFX5mK4hztUL9UdeaDTqC4VuAj/DzeyJzSX kkR1ZILtIvROrCxcE7KEjQmAXaHU3pOi+Y4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3300 Current implementation of SetStaticPageTable routine in PiSmmCpuDxeSmm driver will check a global variable mPhysicalAddressBits, and eventually cap any value larger than 39 at 39. This global variable is used in ConvertMemoryPageAttributes, which backs SmmSetMemoryAttributes and SmmClearMemoryAttributes. Thus for a processor that supports more than 39 bits width, trying to mark page table regions higher than 39-bit will always return EFI_UNSUPPROTED. This change updated the interface of SetStaticPageTable function to take PhysicalAddressBits as an input parameter, in order to avoid changing/ accessing the global variable. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Fixes: 4eee0cc7cc0db74489b99c19eba056b53eda6358 Signed-off-by: Kun Qin Reviewed-by: Laszlo Ersek Reviewed-by: ray.ni@intel.com --- Notes: v2: - SetStaticPageTable interface update [Ray] - Commit message updates, variable type change [Laszlo] UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 30 +++++++++++--------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 6902584b1fbd..d6f8dd94d303 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -211,11 +211,13 @@ CalculateMaximumSupportAddress ( /** Set static page table. =20 - @param[in] PageTable Address of page table. + @param[in] PageTable Address of page table. + @param[in] PhysicalAddressBits The maximum physical address bits supp= orted. **/ VOID SetStaticPageTable ( - IN UINTN PageTable + IN UINTN PageTable, + IN UINT8 PhysicalAddressBits ) { UINT64 PageAddress; @@ -237,26 +239,26 @@ SetStaticPageTable ( // IA-32e paging translates 48-bit linear addresses to 52-bit physical a= ddresses // when 5-Level Paging is disabled. // - ASSERT (mPhysicalAddressBits <=3D 52); - if (!m5LevelPagingNeeded && mPhysicalAddressBits > 48) { - mPhysicalAddressBits =3D 48; + ASSERT (PhysicalAddressBits <=3D 52); + if (!m5LevelPagingNeeded && PhysicalAddressBits > 48) { + PhysicalAddressBits =3D 48; } =20 NumberOfPml5EntriesNeeded =3D 1; - if (mPhysicalAddressBits > 48) { - NumberOfPml5EntriesNeeded =3D (UINTN) LShiftU64 (1, mPhysicalAddressBi= ts - 48); - mPhysicalAddressBits =3D 48; + if (PhysicalAddressBits > 48) { + NumberOfPml5EntriesNeeded =3D (UINTN) LShiftU64 (1, PhysicalAddressBit= s - 48); + PhysicalAddressBits =3D 48; } =20 NumberOfPml4EntriesNeeded =3D 1; - if (mPhysicalAddressBits > 39) { - NumberOfPml4EntriesNeeded =3D (UINTN) LShiftU64 (1, mPhysicalAddressBi= ts - 39); - mPhysicalAddressBits =3D 39; + if (PhysicalAddressBits > 39) { + NumberOfPml4EntriesNeeded =3D (UINTN) LShiftU64 (1, PhysicalAddressBit= s - 39); + PhysicalAddressBits =3D 39; } =20 NumberOfPdpEntriesNeeded =3D 1; - ASSERT (mPhysicalAddressBits > 30); - NumberOfPdpEntriesNeeded =3D (UINTN) LShiftU64 (1, mPhysicalAddressBits = - 30); + ASSERT (PhysicalAddressBits > 30); + NumberOfPdpEntriesNeeded =3D (UINTN) LShiftU64 (1, PhysicalAddressBits -= 30); =20 // // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it. @@ -438,7 +440,7 @@ SmmInitPageTable ( // When access to non-SMRAM memory is restricted, create page table // that covers all memory space. // - SetStaticPageTable ((UINTN)PTEntry); + SetStaticPageTable ((UINTN)PTEntry, mPhysicalAddressBits); } else { // // Add pages to page pool --=20 2.31.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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