From nobody Wed May 15 00:48:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+74079+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74079+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618369175; cv=none; d=zohomail.com; s=zohoarc; b=Sm/kc9egVzYRKOKVuBeAyq+oOabOiyoipfmq6bvdfxjXIPi/ua/A+rHXrg0aSRQMBC8cyFt8YDG0mCpx9U7p4XRqLV8KHqietpKq2WXl40bhGPWPuNeE/3vmxvC5qdWfdwrcDYPIRyDk4XRgnqcSZugaEotZNAtlEYquU5lIL2E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618369175; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Qd8GBFDJ8+RYL2DPkXAiP0WVg+INhL8Ue+1J5Bef2xs=; b=J3bu3OQeZDW9YH5XxAyiIA1RfLiLxd5YUOrOeM6HHxhONIREmEH7ltzayz9MkZy/ijkx6ipl4uweGbtrT8tKJ+c/y9P/S8ehEM/6x/pzc40FXQRx+ERgtlXs6HvtPWGj0GNsTvliq5vcz1eEU+dVRJZYtHsiLVqfHwruTzVhHzQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+74079+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1618369175502882.9061440503526; Tue, 13 Apr 2021 19:59:35 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ExdDYY1788612xJWL2UHz3uo; Tue, 13 Apr 2021 19:59:35 -0700 X-Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) by mx.groups.io with SMTP id smtpd.web08.7778.1618369174551310002 for ; Tue, 13 Apr 2021 19:59:34 -0700 X-Received: by mail-pj1-f50.google.com with SMTP id cu16so7508493pjb.4 for ; Tue, 13 Apr 2021 19:59:34 -0700 (PDT) X-Gm-Message-State: 1KPWuldgskl3aXvRFZp575Afx1787277AA= X-Google-Smtp-Source: ABdhPJwbZT+v1ZLTmdqV3X3TCCgItNJLbS8eJx3xKHfHAamWDDI7/z3B6zf1CbJIKGIRfpHT0EbaCA== X-Received: by 2002:a17:90a:34c5:: with SMTP id m5mr1003252pjf.147.1618369173923; Tue, 13 Apr 2021 19:59:33 -0700 (PDT) X-Received: from localhost.localdomain ([50.35.88.161]) by smtp.gmail.com with ESMTPSA id q19sm15292442pgv.38.2021.04.13.19.59.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 19:59:33 -0700 (PDT) From: "Kun Qin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar Subject: [edk2-devel] [PATCH v1 1/1] UefiCpuPkg: PiSmmCpuDxeSmm: Not to Change Bitwidth During Static Paging Date: Tue, 13 Apr 2021 19:59:22 -0700 Message-Id: <20210414025922.850-2-kuqin12@gmail.com> In-Reply-To: <20210414025922.850-1-kuqin12@gmail.com> References: <20210414025922.850-1-kuqin12@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kuqin12@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1618369175; bh=S1QD6EQI4W/ggYmx6+1gUgUO/OzS6wyomYyAJK2goTY=; h=Cc:Date:From:Reply-To:Subject:To; b=if9ceIhlIceA/RXgLW48wEAHZI0QU4jjZTISjsF1RiF3rUI3tXdA9HbaOMqbzlw1Xss 79PsxXjrq5vFwjI02zfyxYdPkHwFRo5Y0JiJAFNhNj9+GUA8MhivxYfoTQ2BXotQmsWvg y+uw5Z3d9GVl7l/TTn5CWfE0pX6xPiDWRaY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3300 Current implementation of SetStaticPageTable routine in PiSmmCpuDxeSmm driver will check a global variable mPhysicalAddressBits, and eventually cap any value larger than 39 at 39. This global variable is used in ConvertMemoryPageAttributes, which backs SmmSetMemoryAttributes and SmmClearMemoryAttributes. Thus for a processor that supports more than 39 bits width, trying to mark page table regions higher than 39-bit will always return EFI_UNSUPPROTED. This change replaced the changed bitwidth to a stack based variable. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Signed-off-by: Kun Qin --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 25 +++++++++++--------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 6902584b1fbd..0caee8a27abe 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -226,6 +226,7 @@ SetStaticPageTable ( UINTN IndexOfPml4Entries; UINTN IndexOfPdpEntries; UINTN IndexOfPageDirectoryEntrie= s; + UINT64 PhysicalAddressBits; UINT64 *PageMapLevel5Entry; UINT64 *PageMapLevel4Entry; UINT64 *PageMap; @@ -237,26 +238,28 @@ SetStaticPageTable ( // IA-32e paging translates 48-bit linear addresses to 52-bit physical a= ddresses // when 5-Level Paging is disabled. // - ASSERT (mPhysicalAddressBits <=3D 52); - if (!m5LevelPagingNeeded && mPhysicalAddressBits > 48) { - mPhysicalAddressBits =3D 48; + PhysicalAddressBits =3D mPhysicalAddressBits; + + ASSERT (PhysicalAddressBits <=3D 52); + if (!m5LevelPagingNeeded && PhysicalAddressBits > 48) { + PhysicalAddressBits =3D 48; } =20 NumberOfPml5EntriesNeeded =3D 1; - if (mPhysicalAddressBits > 48) { - NumberOfPml5EntriesNeeded =3D (UINTN) LShiftU64 (1, mPhysicalAddressBi= ts - 48); - mPhysicalAddressBits =3D 48; + if (PhysicalAddressBits > 48) { + NumberOfPml5EntriesNeeded =3D (UINTN) LShiftU64 (1, PhysicalAddressBit= s - 48); + PhysicalAddressBits =3D 48; } =20 NumberOfPml4EntriesNeeded =3D 1; - if (mPhysicalAddressBits > 39) { - NumberOfPml4EntriesNeeded =3D (UINTN) LShiftU64 (1, mPhysicalAddressBi= ts - 39); - mPhysicalAddressBits =3D 39; + if (PhysicalAddressBits > 39) { + NumberOfPml4EntriesNeeded =3D (UINTN) LShiftU64 (1, PhysicalAddressBit= s - 39); + PhysicalAddressBits =3D 39; } =20 NumberOfPdpEntriesNeeded =3D 1; - ASSERT (mPhysicalAddressBits > 30); - NumberOfPdpEntriesNeeded =3D (UINTN) LShiftU64 (1, mPhysicalAddressBits = - 30); + ASSERT (PhysicalAddressBits > 30); + NumberOfPdpEntriesNeeded =3D (UINTN) LShiftU64 (1, PhysicalAddressBits -= 30); =20 // // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it. --=20 2.31.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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