MdePkg/Include/Register/Intel/Cpuid.h | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3309
Define new element(Hybird) in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
(07h) data structure.
Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
---
MdePkg/Include/Register/Intel/Cpuid.h | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Register/Intel/Cpuid.h
index 19af99b6af..25ec65a746 100644
--- a/MdePkg/Include/Register/Intel/Cpuid.h
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -6,7 +6,7 @@
If a register returned is a single 32-bit value, then a data structure is
not provided for that register.
- Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@@ -1550,9 +1550,17 @@ typedef union {
///
UINT32 AVX512_4FMAPS:1;
///
- /// [Bit 25:4] Reserved.
+ /// [Bit 14:4] Reserved.
///
- UINT32 Reserved2:22;
+ UINT32 Reserved4:11;
+ ///
+ /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part.
+ ///
+ UINT32 Hybrid:1;
+ ///
+ /// [Bit 25:16] Reserved.
+ ///
+ UINT32 Reserved5:10;
///
/// [Bit 26] Enumerates support for indirect branch restricted speculation
/// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors
@@ -1581,7 +1589,7 @@ typedef union {
///
/// [Bit 30] Reserved.
///
- UINT32 Reserved3:1;
+ UINT32 Reserved6:1;
///
/// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
/// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
--
2.28.0.windows.1
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Jason, Reserved3 doesn't need to change because its position and width are not changed. > -----Original Message----- > From: Lou, Yun <yun.lou@intel.com> > Sent: Thursday, April 8, 2021 10:51 PM > To: devel@edk2.groups.io > Cc: Lou, Yun <yun.lou@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; > Liu, Zhiguang <zhiguang.liu@intel.com>; Ni, Ray <ray.ni@intel.com> > Subject: [PATCH v3] MdePkg/Cpuid.h: Define new element in CPUID Leaf(07h) data structure. > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3309 > > Define new element(Hybird) in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS > (07h) data structure. > > Signed-off-by: Jason Lou <yun.lou@intel.com> > Cc: Michael D Kinney <michael.d.kinney@intel.com> > Cc: Liming Gao <gaoliming@byosoft.com.cn> > Cc: Zhiguang Liu <zhiguang.liu@intel.com> > Cc: Ray Ni <ray.ni@intel.com> > --- > MdePkg/Include/Register/Intel/Cpuid.h | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Register/Intel/Cpuid.h > index 19af99b6af..25ec65a746 100644 > --- a/MdePkg/Include/Register/Intel/Cpuid.h > +++ b/MdePkg/Include/Register/Intel/Cpuid.h > @@ -6,7 +6,7 @@ > If a register returned is a single 32-bit value, then a data structure is > > not provided for that register. > > > > - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR> > > + Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > @par Specification Reference: > > @@ -1550,9 +1550,17 @@ typedef union { > /// > > UINT32 AVX512_4FMAPS:1; > > /// > > - /// [Bit 25:4] Reserved. > > + /// [Bit 14:4] Reserved. > > /// > > - UINT32 Reserved2:22; > > + UINT32 Reserved4:11; > > + /// > > + /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part. > > + /// > > + UINT32 Hybrid:1; > > + /// > > + /// [Bit 25:16] Reserved. > > + /// > > + UINT32 Reserved5:10; > > /// > > /// [Bit 26] Enumerates support for indirect branch restricted speculation > > /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors > > @@ -1581,7 +1589,7 @@ typedef union { > /// > > /// [Bit 30] Reserved. > > /// > > - UINT32 Reserved3:1; > > + UINT32 Reserved6:1; > > /// > > /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD). > > /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow > > -- > 2.28.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73889): https://edk2.groups.io/g/devel/message/73889 Mute This Topic: https://groups.io/mt/81943824/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Hi Ray, the update will be included in the new patch(v4). Thanks! Jason Lou -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73890): https://edk2.groups.io/g/devel/message/73890 Mute This Topic: https://groups.io/mt/81943824/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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