From nobody Tue Apr 23 20:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73650+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73650+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1617354806; cv=none; d=zohomail.com; s=zohoarc; b=S51EIa8Gt3Kg3hJPpotxNvagbM3U2o36P8hFuxOHLWsL80/KVzU3whEdR3LOCdjBPHecGhkskC9y1cZUUvEPImnsgqBXWtZg/SJ2C8gFKxTSOBnI+jGrPYkt5757l0Bs6a48aTkq6XkKtwIcI4sf+JB6mKII1oDpfok7kYa4b3A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617354806; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jmRn8CSrEqfmlBnUz05sH/GJrHI2K+iOUZG5QE4MbiU=; b=IcDAKG/gDAdNWZLNaJYYlgb9wm+JdD9ZIbLzinjpKjZGMKwU04Fyb4pRvQIOc6tS2FL57uPIwZAiYZi2UeSJZ4eiW59H2l7TUDyQFwQth5AJjADs7662kfwIlrXqem5AEZkspi7mwDm9URcRvSTJ72BdfN/BlxaE9P6m94JtTLA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73650+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617354806453366.35696679046896; Fri, 2 Apr 2021 02:13:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 0dRHYY1788612xjvSN2UQvpT; Fri, 02 Apr 2021 02:13:26 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.13846.1617354804437675999 for ; Fri, 02 Apr 2021 02:13:24 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F100F11B3; Fri, 2 Apr 2021 02:13:18 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8CEC13F792; Fri, 2 Apr 2021 02:13:17 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 1/8] Platform/Sgi: Helper macros for PPTT Table Date: Fri, 2 Apr 2021 14:42:01 +0530 Message-Id: <20210402091208.16752-2-pranav.madhu@arm.com> In-Reply-To: <20210402091208.16752-1-pranav.madhu@arm.com> References: <20210402091208.16752-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: FVmC32YFCg6UWsJCNRoJf8Arx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617354806; bh=XdJlAFDR8R8U/2QHuIcmsfJ7CqhLGKW2KGBpcVs1D0s=; h=Cc:Date:From:Reply-To:Subject:To; b=Fa+FULtM11JxHElGybsOfBHgHWnyL2usmjOQzcmZkuuLTLsssTHT+BY3grzIOM/Gz0y Wx3hrRo3LjZeix5rGPHr+zoU0lDhm+tXAPZMZY6HEwIe7lhgdfFu81VwVTr8iNyf6368O yCoH1SrewyCxKNJRehjYM6rp52pXc7qrBME= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add helper macros for the creation for PPTT table. These macros help with initializing processor hierarchy node structure, cache type structure and ID structure. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 163 +++++++++++++++++++- 1 file changed, 162 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/Sgi= Pkg/Include/SgiAcpiHeader.h index 8d715de173c9..7ceb090a78e9 100644 --- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h +++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018-2020, ARM Limited. All rights reserved. +* Copyright (c) 2018-2021, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -20,6 +20,132 @@ #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ') #define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099 =20 +#define CORE_COUNT FixedPcdGet32 (PcdCoreCount) +#define CLUSTER_COUNT FixedPcdGet32 (PcdClusterCount) + +#pragma pack(1) +// PPTT processor core structure +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache; +} RD_PPTT_CORE; + +// PPTT processor cluster structure +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache; + RD_PPTT_CORE Core[CORE_COUNT]; +} RD_PPTT_CLUSTER; + +// PPTT processor cluster structure without cache +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset; + RD_PPTT_CORE Core[CORE_COUNT]; +} RD_PPTT_MINIMAL_CLUSTER; + +// PPTT processor package structure +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT]; +} RD_PPTT_SLC_PACKAGE; +#pragma pack () + +// +// PPTT processor structure flags for different SoC components as defined = in +// ACPI 6.3 specification +// + +// Processor structure flags for SoC package +#define PPTT_PROCESSOR_PACKAGE_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ + } + +// Processor structure flags for cluster +#define PPTT_PROCESSOR_CLUSTER_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ + } + +// Processor structure flags for single-thread core +#define PPTT_PROCESSOR_CORE_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF = \ + } + +// Processor structure flags for multi-thread core +#define PPTT_PROCESSOR_CORE_THREADED_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ + } + +// Processor structure flags for CPU thread +#define PPTT_PROCESSOR_THREAD_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD, = \ + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF = \ + } + +// PPTT cache structure flags as defined in ACPI 6.3 Specification +#define PPTT_CACHE_STRUCTURE_FLAGS = \ + { = \ + EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID, = \ + EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID, = \ + EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID, = \ + EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID, = \ + EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID, = \ + EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID, = \ + EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID = \ + } + +// PPTT cache attributes for data cache +#define PPTT_DATA_CACHE_ATTR = \ + { = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ + } + +// PPTT cache attributes for instruction cache +#define PPTT_INST_CACHE_ATTR = \ + { = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ + } + +// PPTT cache attributes for unified cache +#define PPTT_UNIFIED_CACHE_ATTR = \ + { = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ + } + // A macro to initialise the common header part of EFI ACPI tables as defi= ned by // EFI_ACPI_DESCRIPTION_HEADER structure. #define ARM_ACPI_HEADER(Signature, Type, Revision) { \ @@ -119,4 +245,39 @@ ACPIProcessorUID, Flags, ClockDomain = \ } =20 +// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR +#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent, = \ + ACPIProcessorID, NumberOfPrivateResource) = \ + { = \ + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type 0 */ = \ + Length, /* Length */ = \ + { = \ + EFI_ACPI_RESERVED_BYTE, = \ + EFI_ACPI_RESERVED_BYTE, = \ + }, = \ + Flag, /* Processor flags *= / \ + Parent, /* Ref to parent nod= e */ \ + ACPIProcessorID, /* UID, as per MADT = */ \ + NumberOfPrivateResource /* Resource count */= \ + } + +// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE +#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Size,= \ + NoOfSets, Associativity, Attributes, LineSize) = \ + { = \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, /* Type 1 */ = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), /* Length */ = \ + { = \ + EFI_ACPI_RESERVED_BYTE, = \ + EFI_ACPI_RESERVED_BYTE, = \ + }, = \ + Flag, /* Cache flags */ = \ + NextLevelCache, /* Ref to next level= */ \ + Size, /* Size in bytes */ = \ + NoOfSets, /* Num of sets */ = \ + Associativity, /* Num of ways */ = \ + Attributes, /* Cache attributes = */ \ + LineSize /* Line size in byte= s */ \ + } + #endif /* __SGI_ACPI_HEADER__ */ --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73650): https://edk2.groups.io/g/devel/message/73650 Mute This Topic: https://groups.io/mt/81798780/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 20:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73652+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73652+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1617354812; cv=none; d=zohomail.com; s=zohoarc; b=i/gL5Up03/CD023+IPMvj+clKmsZn+qzE+fBTNff6TgqZr7UZmFi+SEKU9XCsKSN89qiepVNxeCAWafTVFNuvIb4QIkgMqWSqp6011I4HUzgSZWwsYsM2xF3Wq3RSUBDl/RIP95Ssg3GNOM63Rx/7KkrLSstXF5LftG9Y/wc+vg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617354812; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=prd8dnQnkQZoklboXemjHQWIo5tVe9rU/NSUUM9jmL0=; b=nbq/5c3TgGFsCTjGsTbaAfoYR01Sa7UouDauZDlOK0sQaUZtKt/NTwJl08pE3sqc5tgjEddS3O3/PaKAsT10DBIvrFLcr0tbnqTzD44O9qHLsXK16Sa+6jtHJWwkWwvY0czo6VMwu0Z4itwfv6nGWdwwiHv/07NSDJkNddabAP4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73652+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16173548122231007.1906115758728; Fri, 2 Apr 2021 02:13:32 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id OrdRYY1788612xPf6JGpWHq5; Fri, 02 Apr 2021 02:13:31 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.13600.1617354806178514117 for ; Fri, 02 Apr 2021 02:13:26 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CA4AF11FB; Fri, 2 Apr 2021 02:13:20 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 679933F792; Fri, 2 Apr 2021 02:13:19 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform Date: Fri, 2 Apr 2021 14:42:02 +0530 Message-Id: <20210402091208.16752-3-pranav.madhu@arm.com> In-Reply-To: <20210402091208.16752-1-pranav.madhu@arm.com> References: <20210402091208.16752-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: 066xV8XUHMBhV60IcQpc8i8dx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617354811; bh=TKhhYeiAAlne80Z3ckDLwyVHTjs6Qu1k8pzlp3+v6Vw=; h=Cc:Date:From:Reply-To:Subject:To; b=HOTx1cYSO/WBQg5B1jaNUAX5yjJ336y+Fo67CQPhMtmvdXqI2AZg/nAWGX1RjGlhj1f odUiuHQfxK16BOIP3yJm0P7tINuJbLs9NzMeW8eFYGfOTV652jhjXgh8BFzZtUW6iincx EWyxsIEkSHpELp8iCPD+S10B8FAvKlvmxjA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pranav Madhu The SGI-575 platform includes two clusters with four single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. Add PPTT table for SGI-575 platform with this information. Signed-off-by: Pranav Madhu --- .../SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +- .../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 161 ++++++++++++++++++ 2 files changed, 163 insertions(+), 1 deletion(-) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf b/Platform= /ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf index 2121fd39f2f0..b1ee16e98ea3 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2018, ARM Ltd. All rights reserved. +# Copyright (c) 2018 - 2021, ARM Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,7 @@ Mcfg.aslc Sgi575/Dsdt.asl Sgi575/Madt.aslc + Sgi575/Pptt.aslc Spcr.aslc Ssdt.asl =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc b/Platform/ARM= /SgiPkg/AcpiTables/Sgi575/Pptt.aslc new file mode 100644 index 000000000000..043482ee3b9a --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc @@ -0,0 +1,161 @@ +/** @file +* Processor Properties Topology Table (PPTT) for SGI-575 platform +* +* This file describes the topological structure of the processor block on = the +* SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-575 +* platform includes two clusters with four single-thread CPUS. Each of the= CPUs +* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. +* Each cluster includes a 2MB L3 cache. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define PPTT_CORE_INIT(pid, cid, coreId) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid]), /* Parent */ = \ + ((pid << 3) | (cid << 2) | coreId), /* ACPI Id */ = \ + 2 /* Num of private resour= ce */\ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].DCache), = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].ICache) = \ + }, = \ + = \ + /* L1 Data Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 64, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 Instruction Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_512KB, /* Size */ = \ + 1024, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_CLUSTER, L3Cache), = \ + /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].L3Cache), = \ + = \ + /* L3 Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_2MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* Initialize child cores */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0), = \ + PPTT_CORE_INIT (pid, cid, 1), = \ + PPTT_CORE_INIT (pid, cid, 2), = \ + PPTT_CORE_INIT (pid, cid, 3) = \ + } = \ + } + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; +} SGI575_PPTT_PACKAGE; + +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + SGI575_PPTT_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + __builtin_offsetof (SGI575_PPTT_PACKAGE, Cluster[0]), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0 + ), + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1) + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73652): https://edk2.groups.io/g/devel/message/73652 Mute This Topic: https://groups.io/mt/81798784/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 20:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73654+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73654+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1617354809; cv=none; d=zohomail.com; s=zohoarc; b=UOZoB0gwZO3zy8DjhgrAspBkIX/6ZusD5OjdSwuMnBDbsId8JiuMHc1tz3tAeRFwAwWWn7pUFHaBsSNnHa2v+kn3/gQ0ti8jafndG0VkABLaUZ7s74thXP5JIk/PaQbQ45DUMPjeVnQJdc8RjMUZTNJHlsvzrUSLLEITRNS1p+w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617354809; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=oIlfPjYW5kmwVj9EGHpqlS96xj24EuI1x6S3AFCiCK8=; b=hc8dw1dIUK6U9cx2cgQ5OOgl5yBW/tPBWG79Tz3RRNKx7cSkGQh0NKVl5UEd0a1TeTRXNOkm+yXz0my6fjrSXC7/WZCcnL9AU2vncg5G1l4MEKAmZgsXtn86+NUChXBklXwSRJ6o0M6/4GzxfJmnmF0uR40Q/OogxFhlceQLIQU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73654+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617354809079886.530049826978; Fri, 2 Apr 2021 02:13:29 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ktCKYY1788612x0h5HYPyYMz; Fri, 02 Apr 2021 02:13:28 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.13850.1617354808155779920 for ; Fri, 02 Apr 2021 02:13:28 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A71E41424; Fri, 2 Apr 2021 02:13:22 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 428A13F792; Fri, 2 Apr 2021 02:13:21 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 3/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform Date: Fri, 2 Apr 2021 14:42:03 +0530 Message-Id: <20210402091208.16752-4-pranav.madhu@arm.com> In-Reply-To: <20210402091208.16752-1-pranav.madhu@arm.com> References: <20210402091208.16752-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: Gsep9jhD0vrdfozSiLnV5EKfx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617354808; bh=pmAB8P0UJ2L8GKFv63M1BAWZqlhBppKwqfVl2tpK6MM=; h=Cc:Date:From:Reply-To:Subject:To; b=DAJps+iV9kEitb668dfRFOORcgsJBwIgoqPAi+Ej2W6dmk4nKPWeDD/rTLUDOgV3pno VjtbqPu2t9uav+Mp46yX1YUYXN6F1cUag006uCAHakEFclcZM7PZnIa/uLL6NtHBPRBrY Bw+DOHqMafrjc0jnCZzNX5Ec/IESCe14rAM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-N1-Edge platform includes two clusters with four single-thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. The platform also includes a system level cache of 8MB. Add PPTT table for RD-N1-Edge platform with this information. Signed-off-by: Pranav Madhu --- .../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +- .../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 173 ++++++++++++++++++ 2 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf index 22e33239070b..eecb64186473 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2018-2020, ARM Ltd. All rights reserved. +# Copyright (c) 2018-2021, ARM Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,6 +23,7 @@ Mcfg.aslc RdN1Edge/Dsdt.asl RdN1Edge/Madt.aslc + RdN1Edge/Pptt.aslc Spcr.aslc Ssdt.asl =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc new file mode 100644 index 000000000000..e5bc7305444d --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc @@ -0,0 +1,173 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip pl= atform +* +* This file describes the topological structure of the processor block on = the +* RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT tabl= e. The +* RD-N1-Edge platform includes two clusters with four single-thread CPUS. = Each +* of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 51= 2KB L2 +* cache. Each cluster includes a 2MB L3 cache. The platform also includes a +* system level cache of 8MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define PPTT_CORE_INIT(pid, cid, coreId) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid]), /* Parent */ = \ + ((pid << 3) | (cid << 2) | coreId), /* ACPI Id */ = \ + 2 /* Num of private resour= ce */\ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].DCache), = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].ICache) = \ + }, = \ + = \ + /* L1 Data Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 Instruction Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_512KB, /* Size */ = \ + 1024, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_CLUSTER, L3Cache), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].L3Cache), = \ + = \ + /* L3 Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_2MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0), = \ + PPTT_CORE_INIT (pid, cid, 1), = \ + PPTT_CORE_INIT (pid, cid, 2), = \ + PPTT_CORE_INIT (pid, cid, 3) = \ + } = \ + } + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; +} RDN1EDGE_PPTT_PACKAGE ; + +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RDN1EDGE_PPTT_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + __builtin_offsetof (RDN1EDGE_PPTT_PACKAGE , Slc), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), + + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + Package.Slc), + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ + 0, /* Next level of cache */ + SIZE_8MB, /* Size */ + 8192, /* Num of sets */ + 16, /* Associativity */ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ + 64 /* Line size */ + ), + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73654): https://edk2.groups.io/g/devel/message/73654 Mute This Topic: https://groups.io/mt/81798786/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 20:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73651+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73651+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1617354810; cv=none; d=zohomail.com; s=zohoarc; b=F5DRVlrxxqQWJvALmIwOmg4mV5kE8sj8ykENu742+3ZQIDArxOVZaPzVQHGQyCj/US83/TSRfhYGtrbfWp+QGvvqVd1q/0lzG8iVXbnvd61OAs81WZfLECz6VQB9vBn10U1Afk0aRdMfT4JHxQzXbGX8eXApN5jaMlAEtgCePUw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617354810; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=s2kklgfnURbW+VKw9/X+Tf3N40GivBMiuZC2UAFfyx4=; b=dza1d1VHuOUJXOpVsH8oPdJX3/O5MWHawWIKscx+/9wEOoJAWwOXrwtmJG1eyanEPOg9jlu+MLQa4QBfp0tx/xadjzi4CYzd27CuZOKDhJ/luMmTRG+Ku92k2TJX29qQSGJQwPciISnNWPQo0RdedyjibiKWbpmttHSGQAjQwwI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73651+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617354810752273.2599892003668; Fri, 2 Apr 2021 02:13:30 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id prH9YY1788612xpdFafrTZMB; Fri, 02 Apr 2021 02:13:30 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.13848.1617354804867299922 for ; Fri, 02 Apr 2021 02:13:25 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 805C81435; Fri, 2 Apr 2021 02:13:24 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1E24E3F792; Fri, 2 Apr 2021 02:13:22 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 4/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip Date: Fri, 2 Apr 2021 14:42:04 +0530 Message-Id: <20210402091208.16752-5-pranav.madhu@arm.com> In-Reply-To: <20210402091208.16752-1-pranav.madhu@arm.com> References: <20210402091208.16752-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: QmNN3ehwGbPEHSCDcK4haRA4x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617354810; bh=vJ+ZoLVHXGKJ37cQ/g/iqcAKAnblxdBcqmoNSCAmKD0=; h=Cc:Date:From:Reply-To:Subject:To; b=KQ24yiI9lSV8RpZADJHOK7G5afF7ienk3L8RzGDlYbK9chqemBjCOP3u9Z0xd/ooiR3 Sfe3LKLccm2/BHe3saJp3TC2VA04TgHFVYCswYMoUdOvCnBhzWSfR5+VA8A715TRu4Kd0 hAUDeEa1KRCfUaVAqQEAZG9xIOuRUjBHarM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platforms connected over cache coherent interconnect. Each of the RD-N1-Edge single-chip platform includes two clusters with four single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. The platform also includes a system level cache of 8MB per chip. Add PPTT table for RD-N1-Edge dual-chip platform with this information. Signed-off-by: Pranav Madhu --- .../AcpiTables/RdN1EdgeX2AcpiTables.inf | 3 +- .../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 191 ++++++++++++++++++ 2 files changed, 193 insertions(+), 1 deletion(-) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Plat= form/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf index ba400de0454b..ebb77979606e 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2020, ARM Ltd. All rights reserved. +# Copyright (c) 2021, ARM Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,6 +23,7 @@ Mcfg.aslc RdN1Edge/Dsdt.asl RdN1EdgeX2/Madt.aslc + RdN1EdgeX2/Pptt.aslc RdN1EdgeX2/Srat.aslc Spcr.aslc Ssdt.asl diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc new file mode 100644 index 000000000000..3cdcd7714c1f --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc @@ -0,0 +1,191 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip plat= form +* +* This file describes the topological structure of the processor block on = the +* RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table.= The +* RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platfo= rms +* connected over cache coherent interconnect. Each of the RD-N1-Edge singl= e-chip +* platform includes two clusters with four single-thread CPUS. Each of the= CPUs +* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache= . Each +* cluster includes a 2MB L3 cache. Each instance of the chip includes a sy= stem +* level cache of 8MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define CHIP_COUNT FixedPcdGet32 (PcdChipCount) + +#define PPTT_CORE_INIT(pid, cid, coreId) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid].Cluster[cid]), /* Parent */ = \ + ((pid << 3) | (cid << 2) | coreId), /* ACPI Id */ = \ + 2 /* Num of private resour= ce */\ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid].Cluster[cid].Core[coreId].DCache), = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid].Cluster[cid].Core[coreId].ICache) = \ + }, = \ + = \ + /* L1 Data Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid].Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 Instruction Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid].Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_512KB, /* Size */ = \ + 1024, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_CLUSTER, L3Cache), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid]), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].L3Cache), = \ + = \ + /* L3 Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_2MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0), = \ + PPTT_CORE_INIT (pid, cid, 1), = \ + PPTT_CORE_INIT (pid, cid, 2), = \ + PPTT_CORE_INIT (pid, cid, 3) = \ + } = \ + } + +#define PPTT_PACKAGE_INIT(pid) = \ + { = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RDN1EDGEX2_PPTT_PACKAGE , Slc), /* Length */ = \ + PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ = \ + 0, /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Slc), = \ + = \ + /* SLC Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_8MB, /* Size */ = \ + 8192, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + { = \ + PPTT_CLUSTER_INIT (pid, 0), = \ + PPTT_CLUSTER_INIT (pid, 1), = \ + } = \ + } + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; +} RDN1EDGEX2_PPTT_PACKAGE; + +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RDN1EDGEX2_PPTT_PACKAGE Package[CHIP_CO= UNT]; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + PPTT_PACKAGE_INIT (0), + PPTT_PACKAGE_INIT (1) + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73651): https://edk2.groups.io/g/devel/message/73651 Mute This Topic: https://groups.io/mt/81798781/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 20:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73655+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73655+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1617354814; cv=none; d=zohomail.com; s=zohoarc; b=nJAqUQTxhDO3O/YzushuIp7cyUBqkc5quWTVwwBmovIPux2dPpbWtF/usuOp0B5bkFP/BaROdLMeHskSOfFh4Y6ixt429M4LZL7Cddvvzp9AD/MK/+Oqc1/nlmDhN3P19r9nWIQIs8cdx5RannxXSDT1JYNwaWCOug2HSAPAaco= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617354814; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xaTwnF+UaJF7bsY1QdT5bE3KQRmpAZH/czbPXjDXJWw=; b=HAn2vKLtMQpD+jlv50gp+/SOL03Apg9qVqun8EL9jHEY+E1YtlTYPMc3utd3OYwNHj6q/8V/hrBznLc62kZo5gu3ewNVdiNiIKfqMx75NZiSAezWxjeKjE6x82wACCloWG4GLRJhy0SBk6XyshuRGtOcL1e9OKO8JjBfojTSuTs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73655+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617354814132217.61075524120758; Fri, 2 Apr 2021 02:13:34 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id BAF3YY1788612xRxeVFYZhzg; Fri, 02 Apr 2021 02:13:33 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.13601.1617354808099585905 for ; Fri, 02 Apr 2021 02:13:28 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 95ECA11B3; Fri, 2 Apr 2021 02:13:26 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id ECEE73F792; Fri, 2 Apr 2021 02:13:24 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Date: Fri, 2 Apr 2021 14:42:05 +0530 Message-Id: <20210402091208.16752-6-pranav.madhu@arm.com> In-Reply-To: <20210402091208.16752-1-pranav.madhu@arm.com> References: <20210402091208.16752-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: 05qr0wv1cs0pHFobE8p813xkx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617354813; bh=8sOHO75wsW7bwK6+khj/xNgSpqe+l5JCa3ynRvEcTf0=; h=Cc:Date:From:Reply-To:Subject:To; b=AvuFpsMpNabUfAvCJ/BeKNtQE7lajOFkhOtD0WEYmPTohoaDD43kLghCQWFqlGfq/9D 0Qag3tfR1ZRUXDGc3br4tSjyaC0JIY4Ra8FGV0MMdHRBh4IwSLYKA6m3hDWA1XlRfPP58 fZEnTG+eeIeFjE7agBkIANNcsLVdlXBX2hc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-E1-Edge platform includes two clusters with eight multi-thread CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The platform also includes a system level cache of 8MB. Add PPTT table for RD-E1-Edge platform with this information. Signed-off-by: Pranav Madhu --- .../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +- .../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 230 ++++++++++++++++++ 2 files changed, 232 insertions(+), 1 deletion(-) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf index 2dd2275665a2..04ef2bfcaa26 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2018-2020, ARM Ltd. All rights reserved. +# Copyright (c) 2018-2021, ARM Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,6 +23,7 @@ Mcfg.aslc RdE1Edge/Dsdt.asl RdE1Edge/Madt.aslc + RdE1Edge/Pptt.aslc Spcr.aslc Ssdt.asl =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc new file mode 100644 index 000000000000..da0fa3e3f628 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc @@ -0,0 +1,230 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform +* +* This file describes the topological structure of the processor block on = the +* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1= -Edge +* platform includes two clusters with eight dual-thread CPUS. Each of the = CPUs +* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache. +* Each cluster includes a 2MB L3 cache. The platform also includes a system +* level cache of 8MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define THREAD_PER_CORE 2 + +#define PPTT_THREAD_INIT(pid, cid, coreId, tid) = \ + { = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ = \ + PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId]), /* Parent */ = \ + ((pid << 5) | (cid << 4) | (coreId << 1) | tid), = \ + /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ) = \ + } + +#define PPTT_CORE_INIT(pid, cid, coreId) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RDE1EDGE_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid]), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 2 /* Num of private resour= ce */\ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].DCache), = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].ICache) = \ + }, = \ + = \ + /* L1 Data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_32KB, /* Size */ = \ + 128, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 Instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_32KB, /* Size */ = \ + 128, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_256KB, /* Size */ = \ + 1024, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* Thread Initialization */ = \ + { = \ + PPTT_THREAD_INIT (pid, cid, coreId, 0), = \ + PPTT_THREAD_INIT (pid, cid, coreId, 1) = \ + } = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].L3Cache), = \ + = \ + /* L3 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_2MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* Core Initialization */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0), = \ + PPTT_CORE_INIT (pid, cid, 1), = \ + PPTT_CORE_INIT (pid, cid, 2), = \ + PPTT_CORE_INIT (pid, cid, 3), = \ + PPTT_CORE_INIT (pid, cid, 4), = \ + PPTT_CORE_INIT (pid, cid, 5), = \ + PPTT_CORE_INIT (pid, cid, 6), = \ + PPTT_CORE_INIT (pid, cid, 7) = \ + } = \ + } + +#define PPTT_PACKAGE_INIT(pid) = \ + { = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RDE1EDGE_PPTT_PACKAGE, Slc), = \ + PPTT_PROCESSOR_PACKAGE_FLAGS, = \ + 0, = \ + 0, = \ + 1 = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Slc), = \ + = \ + /* SLC parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_8MB, /* Size */ = \ + 8192, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + { = \ + PPTT_CLUSTER_INIT (pid, 0), = \ + PPTT_CLUSTER_INIT (pid, 1), = \ + } = \ + } + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread; +} RDE1EDGE_PPTT_THREAD; + +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache; + RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE]; +} RDE1EDGE_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache; + RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CORE= ]; +} RDE1EDGE_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; +} RDE1EDGE_PPTT_PACKAGE; + +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RDE1EDGE_PPTT_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + PPTT_PACKAGE_INIT (0) +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73655): https://edk2.groups.io/g/devel/message/73655 Mute This Topic: https://groups.io/mt/81798787/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 20:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73656+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73656+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1617354815; cv=none; d=zohomail.com; s=zohoarc; b=CIR8TQ0dPMfkhNF7C1u3l2nFPLh6hOIzdgep71bsqJSBH0m/JfwBQf9xH8NRMFK7d32Ik6Rd2O+EReUivqzHTiQofdHD57G4/H3wNcmcW38uVky6gzoZcIbj1OMnvuxtLZuNxoVU+i3dfmIqk30iQk1v23S28a6wGu/18mYBGR4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617354815; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vgOrFAIPwSLcLRuqrQa/6BfEpnbZbRdVrtx6JzaoXNo=; b=NEHMAlBWsrN4356KpTtoOa8i5nADoFwgaEbmO/z/114sopWpe58lzhEtgdVIxZFD1Blo4TwWkXSPRz7YeGZOIabOHnz+sOdL2iA2g/Noudbl5ieyVN/M5sPL5ZQwjoRGaSqVhGfqJt/LTd8yqGmrroCQSpKKBKxbY4Bf+QvVUmo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73656+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617354815259611.1350415649624; Fri, 2 Apr 2021 02:13:35 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id S1PCYY1788612xgAvlbh4l0w; Fri, 02 Apr 2021 02:13:34 -0700 X-Received: from foss.arm.com (foss.arm.com []) by mx.groups.io with SMTP id smtpd.web08.13601.1617354808099585905 for ; Fri, 02 Apr 2021 02:13:29 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6FF9331B; Fri, 2 Apr 2021 02:13:28 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0BFB63F792; Fri, 2 Apr 2021 02:13:26 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 6/8] Platform/Sgi: ACPI PPTT Table for RD-V1 platform Date: Fri, 2 Apr 2021 14:42:06 +0530 Message-Id: <20210402091208.16752-7-pranav.madhu@arm.com> In-Reply-To: <20210402091208.16752-1-pranav.madhu@arm.com> References: <20210402091208.16752-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: d4RGAt9JGIsJWxcykroQmqdrx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617354814; bh=8MlDnr2ylT58fJx9Ilo01u4le+8o2d1ZxzGBHNt9qh0=; h=Cc:Date:From:Reply-To:Subject:To; b=hm8zz4UT3cctxDZIn4l2wUSdZdLq7XwAZi0vi05NQJ+62RQtghUp5lkKApGWVKftxDq CqSWenz/0LvqawMHq0K2YmYJKX+w5NkRQmCyO0xovV1/QQ05z60iXNW/bSmqqb4HQyk2N Tg35FIrCTJbkQ0ejGFoL3fpZaDLCC/tkIh0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-V1 platform includes sixteen single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes a system level cache of 16MB. Add PPTT table for RD-V1 platform with this information. Signed-off-by: Pranav Madhu --- .../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +- Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 168 ++++++++++++++++++ 2 files changed, 170 insertions(+), 1 deletion(-) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf b/Platform/A= RM/SgiPkg/AcpiTables/RdV1AcpiTables.inf index a21dcfafef1a..a3e558cf1535 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2020, Arm Ltd. All rights reserved. +# Copyright (c) 2020-2021, Arm Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,6 +23,7 @@ Mcfg.aslc RdV1/Dsdt.asl RdV1/Madt.aslc + RdV1/Pptt.aslc Spcr.aslc Ssdt.asl =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM/S= giPkg/AcpiTables/RdV1/Pptt.aslc new file mode 100644 index 000000000000..8d95d834af4d --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc @@ -0,0 +1,168 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform +* +* This file describes the topological structure of the processor block on = the +* RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The +* RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of = the +* CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 ca= che. +* The platform also includes a system level cache of 16MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define PPTT_CORE_INIT(pid, cid, coreId) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid]), /* Parent */ = \ + ((pid << 4) | cid), /* ACPI Id */ = \ + 2 /* Num of private resour= ce */\ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].DCache), = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].ICache) = \ + }, = \ + = \ + /* L1 Data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 Instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_1MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core), = \ + = \ + /* Core initilization */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0) = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_SLC_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + __builtin_offsetof (RD_PPTT_SLC_PACKAGE, Slc), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), + + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + Package.Slc), + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ + 0, /* Next level of cache */ + SIZE_16MB, /* Size */ + 16384, /* Num of sets */ + 16, /* Associativity */ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ + 64 /* Line size */ + ), + + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + PPTT_CLUSTER_INIT (0, 2), + PPTT_CLUSTER_INIT (0, 3), + PPTT_CLUSTER_INIT (0, 4), + PPTT_CLUSTER_INIT (0, 5), + PPTT_CLUSTER_INIT (0, 6), + PPTT_CLUSTER_INIT (0, 7), + PPTT_CLUSTER_INIT (0, 8), + PPTT_CLUSTER_INIT (0, 9), + PPTT_CLUSTER_INIT (0, 10), + PPTT_CLUSTER_INIT (0, 11), + PPTT_CLUSTER_INIT (0, 12), + PPTT_CLUSTER_INIT (0, 13), + PPTT_CLUSTER_INIT (0, 14), + PPTT_CLUSTER_INIT (0, 15) + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73656): https://edk2.groups.io/g/devel/message/73656 Mute This Topic: https://groups.io/mt/81798788/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 20:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73657+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73657+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1617354816; cv=none; d=zohomail.com; s=zohoarc; b=oHjOG7jJP1XlGg1A1sz9l9RqxijDyYcgNnFG9yW9OWu9qOsv3t2KtbwDV/6ST3svyHYLGvoEje05FFQIYOsY5aUXsEWpmh8m23bIyJxpQAblZhzUN+js0PjOHi8dey+a4ceb0g+HMmHvcTsXRnXNRP6CBPsygLXR+YKf3HY4spE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617354816; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=CGtKLqWbaCqci0Pz195nnFrwamovqU4B7MZ8j8PV4Qk=; b=nH2Y1mkxZWL0VP2VPJ8wC6laR+qlNB/TGqF2g112CicMPictSn381RvQ/ZAonD6rmlzMFwVtTplUpJ04zvgyiMFNPLIkVuOlzoz0SQXJF8zqSc/JTFj7EMMMakrxAAqUTQsM8/3Ivtht7RpZfymWspeceVLgEA4Rs7A9njel7tU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73657+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617354816647619.341600341558; Fri, 2 Apr 2021 02:13:36 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id SOgeYY1788612xobFUOJ8CjK; Fri, 02 Apr 2021 02:13:36 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.13820.1617354810642187541 for ; Fri, 02 Apr 2021 02:13:30 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4C63511B3; Fri, 2 Apr 2021 02:13:30 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DC8313F792; Fri, 2 Apr 2021 02:13:28 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 7/8] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform Date: Fri, 2 Apr 2021 14:42:07 +0530 Message-Id: <20210402091208.16752-8-pranav.madhu@arm.com> In-Reply-To: <20210402091208.16752-1-pranav.madhu@arm.com> References: <20210402091208.16752-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: CqpfyxzerQZeAPVgLHhdhp1Cx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617354816; bh=XtKDVHAjxgvUoJAm/b/JGYvd6ecM8bJTNIkpO4KV1uk=; h=Cc:Date:From:Reply-To:Subject:To; b=nrUpryfa2Asbcn392vux74JA6pQallXcy8uPseYHABZBKUEM4YLH4tAutRR1kMTjeYR U3ALLJTFa/hbpzuaOS98guFh3VkmB8PEpDiU6nrt/5A5hydebzqdkvoJyQtSghlJnFOHg IV1yfdOZ2R0qOYbVwXLfOvmWePM3+AIfw5c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-V1 quad-chip platform consists of four chips connected over cache coherent interconnect. Each chip on the platform includes four single- thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes a system level cache of 16MB per chip. Add PPTT table for RD-V1 quad-chip platform with this information. Signed-off-by: Pranav Madhu --- .../SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 3 +- .../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 172 ++++++++++++++++++ 2 files changed, 174 insertions(+), 1 deletion(-) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platform= /ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf index 08351b1e98e6..40fd6ae00270 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2020, Arm Ltd. All rights reserved. +# Copyright (c) 2020-2021, Arm Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,6 +23,7 @@ Mcfg.aslc RdV1Mc/Dsdt.asl RdV1Mc/Madt.aslc + RdV1Mc/Pptt.aslc RdV1Mc/Srat.aslc Spcr.aslc Ssdt.asl diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/ARM= /SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc new file mode 100644 index 000000000000..f5c7b0f61d94 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc @@ -0,0 +1,172 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platform +* +* This file describes the topological structure of the processor block on = the +* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. The = RD-V1 +* quad-chip platform is composed of four identical chips connected over ca= che +* coherent interconnect. Each of the chip on the platform includes four si= ngle +* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instru= ction +* cache and 1MB L2 cache. The platform also includes a system level cache = of +* 16MB per chip. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define CHIP_COUNT FixedPcdGet32 (PcdChipCount) + +#define PPTT_CORE_INIT(pid, cid, coreId) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid].Cluster[cid]), /* Parent */ = \ + ((pid << 2) | cid), /* ACPI Id */ = \ + 2 /* Num of private resour= ce */\ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid].Cluster[cid].Core[coreId].DCache), = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid].Cluster[cid].Core[coreId].ICache) = \ + }, = \ + = \ + /* L1 Data cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid].Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 Instruction cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid].Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 Cache Parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_1MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package[pid]), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core), = \ + = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0) = \ + } = \ + } + +#define PPTT_PACKAGE_INIT(pid) = \ + { = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_SLC_PACKAGE, Slc), /* Length */ = \ + PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ = \ + 0, /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resour= ce */\ + ), = \ + = \ + /* Offsets of the private resources */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Slc), = \ + = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_16MB, /* Size */ = \ + 16384, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + { = \ + PPTT_CLUSTER_INIT (pid, 0), = \ + PPTT_CLUSTER_INIT (pid, 1), = \ + PPTT_CLUSTER_INIT (pid, 2), = \ + PPTT_CLUSTER_INIT (pid, 3), = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_SLC_PACKAGE Package[CHIP_CO= UNT]; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + PPTT_PACKAGE_INIT (0), + PPTT_PACKAGE_INIT (1), + PPTT_PACKAGE_INIT (2), + PPTT_PACKAGE_INIT (3) + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73657): https://edk2.groups.io/g/devel/message/73657 Mute This Topic: https://groups.io/mt/81798790/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 20:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73658+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73658+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1617354819; cv=none; d=zohomail.com; s=zohoarc; b=KiqKbSR4DTWEI6TDjSalZH2EcKcPBdvrxBV1heEHUNyjpePa0/98EPXXVSJZPpafm3pRs199OuLj14qJOny4/6kd49IYZ9AEx4MR04mYWnClNdhP0WyM5/UD1NYMsLCIkuw2ULRYUI8WmvxCCwUOhtghcNoPsDzzAiZjQueHr7Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617354819; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Jh3GuNketEolmLLuyVZTkz/zTlXL9wfijNqAcpP3I/E=; b=ZMyXIQTaWQz0nkYCc+FjUMAOYYCyEbfrvZAibUEYLAvKkbAnanQmdyjFFq/4gl7PvJyZns9LzMon4RJU0+KWPWmCZpPyekAyuXy2aSbBHpcB9qndsDtSc5qeBy+tD7D13MZ8NH4XEhp2J4ZPcmbzaTa741VuTFGeCPYG7ER2WF8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73658+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617354819073366.59159728272573; Fri, 2 Apr 2021 02:13:39 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id kjcTYY1788612xyRZqTHW2A4; Fri, 02 Apr 2021 02:13:38 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.13509.1617354812534394948 for ; Fri, 02 Apr 2021 02:13:32 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 271BB31B; Fri, 2 Apr 2021 02:13:32 -0700 (PDT) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B8C463F792; Fri, 2 Apr 2021 02:13:30 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 8/8] Platform/Sgi: ACPI PPTT table for RD-N2 platform Date: Fri, 2 Apr 2021 14:42:08 +0530 Message-Id: <20210402091208.16752-9-pranav.madhu@arm.com> In-Reply-To: <20210402091208.16752-1-pranav.madhu@arm.com> References: <20210402091208.16752-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: CJnGGGG3SXB3ruG0yGUb9xK6x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617354818; bh=5NF8qYglADXOf5QUvHsnPu2fUCWH1eSb2s7PxZxyDRM=; h=Cc:Date:From:Reply-To:Subject:To; b=Qt1Qc3Hxry6vgPyx1t3+Uz4+fTp/NBZzHrMvVWeShcld9tKOd4eYn3syEc1Of5C+9GO B5PEc6zIiTVIYT4NMilGRQ45lz6ZKwrxgcV8S0wRTsKvtDNEBOnPjiv25AsorKeLQopzz c7pKtyjB7UU5fSMh6u2Hs2Hw05E81Nx8dPQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RD-N2 platform includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes a system level cache of 32MB. Add PPTT table for RD-N2 platform with this information. Signed-off-by: Pranav Madhu --- .../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +- Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 166 ++++++++++++++++++ 2 files changed, 168 insertions(+), 1 deletion(-) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/A= RM/SgiPkg/AcpiTables/RdN2AcpiTables.inf index 2ec3e42473a9..c1282a3422ab 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2020, Arm Ltd. All rights reserved. +# Copyright (c) 2020-2021, Arm Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,7 @@ Mcfg.aslc RdN2/Dsdt.asl RdN2/Madt.aslc + RdN2/Pptt.aslc Spcr.aslc Ssdt.asl SsdtRos.asl diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/S= giPkg/AcpiTables/RdN2/Pptt.aslc new file mode 100644 index 000000000000..1073c8b1d4f5 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc @@ -0,0 +1,166 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-N2 platform +* +* This file describes the topological structure of the processor block on = the +* RD-N2 platform in the form as defined by ACPI PPTT table. The RD-N2 plat= form +* includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Da= ta +* cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also inc= ludes +* system level cache of 32MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define PPTT_CORE_INIT(pid, cid, coreId) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid]), /* Parent */ = \ + ((pid << 4) | cid), /* ACPI Id */ = \ + 2 /* Num of private resour= ce */\ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].DCache), = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].ICache) = \ + }, = \ + = \ + /* L1 Data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 Instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package.Cluster[cid].Core[coreId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_1MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + __builtin_offsetof (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE= , \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core), = \ + = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0) = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_SLC_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + __builtin_offsetof (RD_PPTT_SLC_PACKAGE, Slc), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), + + __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + Package.Slc), + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ + 0, /* Next level of cache */ + SIZE_32MB, /* Size */ + 32768, /* Num of sets */ + 16, /* Associativity */ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ + 64), /* Line size */ + + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + PPTT_CLUSTER_INIT (0, 2), + PPTT_CLUSTER_INIT (0, 3), + PPTT_CLUSTER_INIT (0, 4), + PPTT_CLUSTER_INIT (0, 5), + PPTT_CLUSTER_INIT (0, 6), + PPTT_CLUSTER_INIT (0, 7), + PPTT_CLUSTER_INIT (0, 8), + PPTT_CLUSTER_INIT (0, 9), + PPTT_CLUSTER_INIT (0, 10), + PPTT_CLUSTER_INIT (0, 11), + PPTT_CLUSTER_INIT (0, 12), + PPTT_CLUSTER_INIT (0, 13), + PPTT_CLUSTER_INIT (0, 14), + PPTT_CLUSTER_INIT (0, 15) + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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