From nobody Fri Apr 19 08:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73638+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73638+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1617343101; cv=none; d=zohomail.com; s=zohoarc; b=eA9yAQk8bkwsh1ZwwOWQSd6vcUz0B87v6MNg+MS4J6/b8mtb/4GuDhZaTV1R5m2Ixr8MwInUttdMgqk/HvnHfOFE5rJaLyEw28b20K5L5VKb3YvcLY5fhG03dQH0TtEDwSS/j6MB+O+pIydNaF+BJRkaYEOyvs926t96LXKCqU8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617343101; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=nB33GvDx3Ud8RecHg/5jNREUvYSE9q8h0tvNC1xTKlU=; b=eJNzBo1FxKLA8q2sJGBWV77fMqGOao2S2IMz/ckI6e70KeOP0Xh49ujz1DB7iW8o5nbnLv9DF3YQPTSiiq4Kp4XNFdj3d21KGCPFPhcRvMltCqILhDvMcluUye097WabR0/S6Dslo0/q1RomXs0qilA2AydKyXJxh2s2TidF3sk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73638+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617343101209798.5324521306248; Thu, 1 Apr 2021 22:58:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7GA3YY1788612xdx9TKV5aDe; Thu, 01 Apr 2021 22:58:20 -0700 X-Received: from mga09.intel.com (mga09.intel.com []) by mx.groups.io with SMTP id smtpd.web08.12337.1617343099200294881 for ; Thu, 01 Apr 2021 22:58:20 -0700 IronPort-SDR: YxL0YhiCemVbKSseRbQEVrp9m97hKE1QeE5bO4/fB9f1cIlIq0RxMfI8yKRKBGR2P6VjytsQ9m XwmSFIx9M67g== X-IronPort-AV: E=McAfee;i="6000,8403,9941"; a="192501517" X-IronPort-AV: E=Sophos;i="5.81,298,1610438400"; d="scan'208";a="192501517" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2021 22:58:19 -0700 IronPort-SDR: yJTCLfCAeGjNMlYpoQfqDxXJEZymiBXfyDx9DMBziLEOxOoTbdN8UinJQwgn6qx7OAgLSSmbWp A9WkiuwB0Sfw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,298,1610438400"; d="scan'208";a="413029588" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.158.87]) by fmsmga008.fm.intel.com with ESMTP; 01 Apr 2021 22:58:18 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Laszlo Ersek , Rahul Kumar Subject: [edk2-devel] [PATCH 1/4] UefiCpuPkg: Add MicrocodeLib for loading microcode Date: Fri, 2 Apr 2021 13:58:04 +0800 Message-Id: <20210402055807.858-2-ray.ni@intel.com> In-Reply-To: <20210402055807.858-1-ray.ni@intel.com> References: <20210402055807.858-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: hTLTM6ZhQJuvzDhljbCGzLP7x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617343100; bh=2Ms58K06guW5c1p0XWGAzixbM1GmOrLnLRYJ5Q76ZU4=; h=Cc:Date:From:Reply-To:Subject:To; b=j+pEiE7Xq1mNQ0hI5zd31W0m8unzr2Hwmug8VU+NfKbKtoobrj/mNNgxijuOmhef+9z iBMiqPyKRSIsx0H2iWqYhy3BKJzoltwaMSyPeB0Wg1oKGRGk+wPqLOwhRo27AHKWLDHYW lT2Us/+kzQFv4qt854pszprh2ZJDTs+0VPM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Cc: Rahul Kumar Acked-by: Laszlo Ersek Reviewed-by: Eric Dong --- UefiCpuPkg/Include/Library/MicrocodeLib.h | 120 +++++++ .../Library/MicrocodeLib/MicrocodeLib.c | 322 ++++++++++++++++++ .../Library/MicrocodeLib/MicrocodeLib.inf | 32 ++ UefiCpuPkg/UefiCpuPkg.dec | 5 +- UefiCpuPkg/UefiCpuPkg.dsc | 1 + 5 files changed, 479 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/Include/Library/MicrocodeLib.h create mode 100644 UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c create mode 100644 UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf diff --git a/UefiCpuPkg/Include/Library/MicrocodeLib.h b/UefiCpuPkg/Include= /Library/MicrocodeLib.h new file mode 100644 index 0000000000..2570c43cce --- /dev/null +++ b/UefiCpuPkg/Include/Library/MicrocodeLib.h @@ -0,0 +1,120 @@ +/** @file + Public include file for Microcode library. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MICROCODE_LIB_H__ +#define __MICROCODE_LIB_H__ + +#include +#include + +/** + Get microcode update signature of currently loaded microcode update. + + @return Microcode signature. +**/ +UINT32 +EFIAPI +GetProcessorMicrocodeSignature ( + VOID + ); + +/** + Get the processor signature and platform ID for current processor. + + @param MicrocodeCpuId Return the processor signature and platform ID. +**/ +VOID +EFIAPI +GetProcessorMicrocodeCpuId ( + EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId + ); + +/** + Return the total size of the microcode entry. + + Logic follows pseudo code in SDM as below: + + N =3D 512 + If (Update.DataSize !=3D 00000000H) + N =3D Update.TotalSize / 4 + + If Microcode is NULL, then ASSERT. + + @param Microcode Pointer to the microcode entry. + + @return The microcode total size. +**/ +UINT32 +EFIAPI +GetMicrocodeLength ( + IN CPU_MICROCODE_HEADER *Microcode + ); + +/** + Load the microcode to the processor. + + If Microcode is NULL, then ASSERT. + + @param Microcode Pointer to the microcode entry. +**/ +VOID +EFIAPI +LoadMicrocode ( + IN CPU_MICROCODE_HEADER *Microcode + ); + +/** + Detect whether specified processor can find matching microcode patch and= load it. + + Microcode format is as below: + +----------------------------------------+------------------------------= -------------------+ + | CPU_MICROCODE_HEADER | = | + +----------------------------------------+ = V + | Update Data | = CPU_MICROCODE_HEADER.Checksum + +----------------------------------------+-------+ = ^ + | CPU_MICROCODE_EXTENDED_TABLE_HEADER | | = | + +----------------------------------------+ V = | + | CPU_MICROCODE_EXTENDED_TABLE[0] | CPU_MICROCODE_EXTENDED_TABLE= _HEADER.Checksum | + | CPU_MICROCODE_EXTENDED_TABLE[1] | ^ = | + | ... | | = | + +----------------------------------------+-------+----------------------= -------------------+ + + There may by multiple CPU_MICROCODE_EXTENDED_TABLE in this format. + The count of CPU_MICROCODE_EXTENDED_TABLE is indicated by ExtendedSignat= ureCount + of CPU_MICROCODE_EXTENDED_TABLE_HEADER structure. + + If Microcode is NULL, then ASSERT. + + @param Microcode Pointer to a microcode entry. + @param MicrocodeLength The total length of the microcode entry. + @param MinimumRevision The microcode whose revision <=3D MinimumRev= ision is treated as invalid. + Caller can supply value get from GetProcesso= rMicrocodeSignature() to check + whether the microcode is newer than loaded o= ne. + Caller can supply 0 to treat any revision (e= xcept 0) microcode as valid. + @param MicrocodeCpuIds Pointer to an array of processor signature a= nd platform ID that represents + a set of processors. + Caller can supply zero-element array to skip= the processor signature and + platform ID check. + @param MicrocodeCpuIdCount The number of elements in MicrocodeCpuIds. + @param VerifyChecksum FALSE to skip all the checksum verifications. + + @retval TRUE The microcode is valid. + @retval FALSE The microcode is invalid. +**/ +BOOLEAN +EFIAPI +IsValidMicrocode ( + IN CPU_MICROCODE_HEADER *Microcode, + IN UINTN MicrocodeLength, + IN UINT32 MinimumRevision, + IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds, + IN UINTN MicrocodeCpuIdCount, + IN BOOLEAN VerifyChecksum + ); + +#endif \ No newline at end of file diff --git a/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c b/UefiCpuPkg/Li= brary/MicrocodeLib/MicrocodeLib.c new file mode 100644 index 0000000000..03a43fdae7 --- /dev/null +++ b/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c @@ -0,0 +1,322 @@ +/** @file + Implementation of MicrocodeLib. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Get microcode update signature of currently loaded microcode update. + + @return Microcode signature. +**/ +UINT32 +EFIAPI +GetProcessorMicrocodeSignature ( + VOID + ) +{ + MSR_IA32_BIOS_SIGN_ID_REGISTER BiosSignIdMsr; + + AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0); + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL); + BiosSignIdMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID); + return BiosSignIdMsr.Bits.MicrocodeUpdateSignature; +} + +/** + Get the processor signature and platform ID for current processor. + + @param MicrocodeCpuId Return the processor signature and platform ID. +**/ +VOID +EFIAPI +GetProcessorMicrocodeCpuId ( + EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId + ) +{ + MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; + + ASSERT (MicrocodeCpuId !=3D NULL); + + PlatformIdMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_PLATFORM_ID); + MicrocodeCpuId->PlatformId =3D (UINT8) PlatformIdMsr.Bits.PlatformId; + AsmCpuid (CPUID_VERSION_INFO, &MicrocodeCpuId->ProcessorSignature, NULL,= NULL, NULL); +} + +/** + Return the total size of the microcode entry. + + Logic follows pseudo code in SDM as below: + + N =3D 512 + If (Update.DataSize !=3D 00000000H) + N =3D Update.TotalSize / 4 + + If Microcode is NULL, then ASSERT. + + @param Microcode Pointer to the microcode entry. + + @return The microcode total size. +**/ +UINT32 +EFIAPI +GetMicrocodeLength ( + IN CPU_MICROCODE_HEADER *Microcode + ) +{ + UINT32 TotalSize; + + ASSERT (Microcode !=3D NULL); + + TotalSize =3D 2048; + if (Microcode->DataSize !=3D 0) { + TotalSize =3D Microcode->TotalSize; + } + return TotalSize; +} + +/** + Load the microcode to the processor. + + If Microcode is NULL, then ASSERT. + + @param Microcode Pointer to the microcode entry. +**/ +VOID +EFIAPI +LoadMicrocode ( + IN CPU_MICROCODE_HEADER *Microcode + ) +{ + ASSERT (Microcode !=3D NULL); + + AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, (UINT64) (UINTN) (Microcode + 1)= ); +} + +/** + Determine if a microcode patch matchs the specific processor signature a= nd flag. + + @param[in] ProcessorSignature The processor signature field value in= a + microcode patch. + @param[in] ProcessorFlags The processor flags field value in a + microcode patch. + @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_MIC= ROCODE_CPU_ID + structures. + @param[in] MicrocodeCpuIdCount Number of elements in MicrocodeCpuId a= rray. + + @retval TRUE The specified microcode patch matches to one of the Mic= rocodeCpuId. + @retval FALSE The specified microcode patch doesn't match to any of t= he MicrocodeCpuId. +**/ +BOOLEAN +IsProcessorMatchedMicrocode ( + IN UINT32 ProcessorSignature, + IN UINT32 ProcessorFlags, + IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, + IN UINTN MicrocodeCpuIdCount + ) +{ + UINTN Index; + + if (MicrocodeCpuIdCount =3D=3D 0) { + return TRUE; + } + + for (Index =3D 0; Index < MicrocodeCpuIdCount; Index++) { + if ((ProcessorSignature =3D=3D MicrocodeCpuId[Index].ProcessorSignatur= e) && + (ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) !=3D 0)= { + return TRUE; + } + } + + return FALSE; +} + +/** + Detect whether specified processor can find matching microcode patch and= load it. + + Microcode format is as below: + +----------------------------------------+------------------------------= -------------------+ + | CPU_MICROCODE_HEADER | = | + +----------------------------------------+ = V + | Update Data | = CPU_MICROCODE_HEADER.Checksum + +----------------------------------------+-------+ = ^ + | CPU_MICROCODE_EXTENDED_TABLE_HEADER | | = | + +----------------------------------------+ V = | + | CPU_MICROCODE_EXTENDED_TABLE[0] | CPU_MICROCODE_EXTENDED_TABLE= _HEADER.Checksum | + | CPU_MICROCODE_EXTENDED_TABLE[1] | ^ = | + | ... | | = | + +----------------------------------------+-------+----------------------= -------------------+ + + There may by multiple CPU_MICROCODE_EXTENDED_TABLE in this format. + The count of CPU_MICROCODE_EXTENDED_TABLE is indicated by ExtendedSignat= ureCount + of CPU_MICROCODE_EXTENDED_TABLE_HEADER structure. + + If Microcode is NULL, then ASSERT. + + @param Microcode Pointer to a microcode entry. + @param MicrocodeLength The total length of the microcode entry. + @param MinimumRevision The microcode whose revision <=3D MinimumRev= ision is treated as invalid. + Caller can supply value get from GetProcesso= rMicrocodeSignature() to check + whether the microcode is newer than loaded o= ne. + Caller can supply 0 to treat any revision (e= xcept 0) microcode as valid. + @param MicrocodeCpuIds Pointer to an array of processor signature a= nd platform ID that represents + a set of processors. + Caller can supply zero-element array to skip= the processor signature and + platform ID check. + @param MicrocodeCpuIdCount The number of elements in MicrocodeCpuIds. + @param VerifyChecksum FALSE to skip all the checksum verifications. + + @retval TRUE The microcode is valid. + @retval FALSE The microcode is invalid. +**/ +BOOLEAN +EFIAPI +IsValidMicrocode ( + IN CPU_MICROCODE_HEADER *Microcode, + IN UINTN MicrocodeLength, + IN UINT32 MinimumRevision, + IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds, + IN UINTN MicrocodeCpuIdCount, + IN BOOLEAN VerifyChecksum + ) +{ + UINTN Index; + UINT32 DataSize; + UINT32 TotalSize; + CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; + CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; + UINT32 ExtendedTableLength; + UINT32 Sum32; + BOOLEAN Match; + + ASSERT (Microcode !=3D NULL); + + // + // It's invalid when: + // the input microcode buffer is so small that even cannot contain the= header. + // the input microcode buffer is so large that exceeds MAX_ADDRESS. + // + if ((MicrocodeLength < sizeof (CPU_MICROCODE_HEADER)) || (MicrocodeLengt= h > (MAX_ADDRESS - (UINTN) Microcode))) { + return FALSE; + } + + // + // Per SDM, HeaderVersion and LoaderRevision should both be 1. + // + if ((Microcode->HeaderVersion !=3D 1) || (Microcode->LoaderRevision !=3D= 1)) { + return FALSE; + } + + // + // The microcode revision should be larger than the minimum revision. + // + if (Microcode->UpdateRevision <=3D MinimumRevision) { + return FALSE; + } + + DataSize =3D Microcode->DataSize; + if (DataSize =3D=3D 0) { + DataSize =3D 2000; + } + + // + // Per SDM, DataSize should be multiple of DWORDs. + // + if ((DataSize % 4) !=3D 0) { + return FALSE; + } + + TotalSize =3D GetMicrocodeLength (Microcode); + + // + // Check whether the whole microcode is within the buffer. + // TotalSize should be multiple of 1024. + // + if (((TotalSize % SIZE_1KB) !=3D 0) || (TotalSize > MicrocodeLength)) { + return FALSE; + } + + // + // The summation of all DWORDs in microcode should be zero. + // + if (VerifyChecksum && (CalculateSum32 ((UINT32 *) Microcode, TotalSize) = !=3D 0)) { + return FALSE; + } + + Sum32 =3D Microcode->ProcessorSignature.Uint32 + Microcode->ProcessorFla= gs + Microcode->Checksum; + + // + // Check the processor signature and platform ID in the primary header. + // + Match =3D IsProcessorMatchedMicrocode ( + Microcode->ProcessorSignature.Uint32, + Microcode->ProcessorFlags, + MicrocodeCpuIds, + MicrocodeCpuIdCount + ); + if (Match) { + return TRUE; + } + + ExtendedTableLength =3D TotalSize - (DataSize + sizeof (CPU_MICROCODE_HE= ADER)); + if ((ExtendedTableLength < sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER))= || ((ExtendedTableLength % 4) !=3D 0)) { + return FALSE; + } + // + // Extended Table exist, check if the CPU in support list + // + ExtendedTableHeader =3D (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINTN)= (Microcode + 1) + DataSize); + if (ExtendedTableHeader->ExtendedSignatureCount > MAX_UINT32 / sizeof (C= PU_MICROCODE_EXTENDED_TABLE)) { + return FALSE; + } + if (ExtendedTableHeader->ExtendedSignatureCount * sizeof (CPU_MICROCODE_= EXTENDED_TABLE) + > ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)= ) { + return FALSE; + } + // + // Check the extended table checksum + // + if (VerifyChecksum && (CalculateSum32 ((UINT32 *) ExtendedTableHeader, E= xtendedTableLength) !=3D 0)) { + return FALSE; + } + + ExtendedTable =3D (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTableHeader = + 1); + for (Index =3D 0; Index < ExtendedTableHeader->ExtendedSignatureCount; I= ndex ++) { + if (VerifyChecksum && + (ExtendedTable[Index].ProcessorSignature.Uint32 + ExtendedTable[In= dex].ProcessorFlag + + ExtendedTable[Index].Checksum !=3D Sum32)) { + // + // The extended table entry is valid when the summation of Processor= Signature, Processor Flags + // and Checksum equal to the coresponding summation from primary hea= der. Because: + // CalculateSum32 (Header + Update Binary) =3D=3D 0 + // CalculateSum32 (Header + Update Binary) + // - (Header.ProcessorSignature + Header.ProcessorFlag + Head= er.Checksum) + // + (Extended.ProcessorSignature + Extended.ProcessorFlag + = Extended.Checksum) =3D=3D 0 + // So, + // (Header.ProcessorSignature + Header.ProcessorFlag + Header.Che= cksum) + // =3D=3D (Extended.ProcessorSignature + Extended.ProcessorFlag = + Extended.Checksum) + // + continue; + } + Match =3D IsProcessorMatchedMicrocode ( + ExtendedTable[Index].ProcessorSignature.Uint32, + ExtendedTable[Index].ProcessorFlag, + MicrocodeCpuIds, + MicrocodeCpuIdCount + ); + if (Match) { + return TRUE; + } + } + return FALSE; +} diff --git a/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf b/UefiCpuPkg/= Library/MicrocodeLib/MicrocodeLib.inf new file mode 100644 index 0000000000..c6f8f52e95 --- /dev/null +++ b/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf @@ -0,0 +1,32 @@ +## @file +# Library for microcode verification and load. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010006 + BASE_NAME =3D MicrocodeLib + FILE_GUID =3D EB8C72BC-8A48-4F80-996B-E52F68416D57 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MicrocodeLib + +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# + +[Sources.common] + MicrocodeLib.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + DebugLib diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index a639ce5412..62acb291f3 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -1,7 +1,7 @@ ## @file UefiCpuPkg.dec # This Package provides UEFI compatible CPU modules and libraries. # -# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -59,6 +59,9 @@ [LibraryClasses.IA32, LibraryClasses.X64] ## @libraryclass Provides function to get CPU cache information. CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h =20 + ## @libraryclass Provides function for loading microcode. + MicrocodeLib|Include/Library/MicrocodeLib.h + [Guids] gUefiCpuPkgTokenSpaceGuid =3D { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa,= 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }} gMsegSmramGuid =3D { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1,= 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }} diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 98c4c53465..b932cf63ec 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -60,6 +60,7 @@ [LibraryClasses] PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf =20 [LibraryClasses.common.SEC] PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.= inf --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73638): https://edk2.groups.io/g/devel/message/73638 Mute This Topic: https://groups.io/mt/81796731/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 19 08:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73639+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73639+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1617343107; cv=none; d=zohomail.com; s=zohoarc; b=bQhZJEpYTph8UVgpCkG0/cFXPh4fXq1GMNXzcPDEy9iqHLZ3KSNBIbz/UvNhJzNyPrsvOt5wPpboZ9LKgdbYESB+NKI+kUa1Vmo4tAeAI0Oui3g5Y66kz45FWh0SU1yryZbNs+VPmYvmXlAWeZaTTE0Zwc8yOSVmvfOfsE5gTKw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617343107; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=OkH+cWrZ3Td7cTeQU1kFS2y2FpHmT5J6ZINVmn3tMX8=; b=QUDnbSG35CAvfwtwn/CFN4yPfVZG63lUk+ReX64bpbIYUYxdPpuNwtVi2ChQvMbAbhKFIDWO/bu5JxEvHHNC0SGSu1zk66ESOI/EA2hLrOmmXwu/i9B9CziV4JX3u8yEXdT9gDrgyaZNREmgGTjjyUENuCOwkjiBfp9wU4wl+fY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73639+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617343107707325.12042543905363; Thu, 1 Apr 2021 22:58:27 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id nG3uYY1788612xUuEtACRKgz; Thu, 01 Apr 2021 22:58:27 -0700 X-Received: from mga09.intel.com (mga09.intel.com []) by mx.groups.io with SMTP id smtpd.web08.12337.1617343099200294881 for ; Thu, 01 Apr 2021 22:58:22 -0700 IronPort-SDR: uiAdMtIC98FDX/pRLcX+cOa1WKL5jqS49kbcr5eciCzMzJBUSgJY/RpGdaRyYmC97arcOI8SjM 9K8J+a+M/xqQ== X-IronPort-AV: E=McAfee;i="6000,8403,9941"; a="192501538" X-IronPort-AV: E=Sophos;i="5.81,298,1610438400"; d="scan'208";a="192501538" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2021 22:58:21 -0700 IronPort-SDR: 4ICPVCvqLnFM6Q8Dr0hp59uK3uV09tukUwXZzcrlFjlDH0zOgSJ7OTkyYzWF8D9yAp3YhmR8nJ nNmkKddfctOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,298,1610438400"; d="scan'208";a="413029602" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.158.87]) by fmsmga008.fm.intel.com with ESMTP; 01 Apr 2021 22:58:20 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Laszlo Ersek , Ard Biesheuvel , Jordan Justen Subject: [edk2-devel] [PATCH 2/4] OvmfPkg: Add MicrocodeLib in DSC files. Date: Fri, 2 Apr 2021 13:58:05 +0800 Message-Id: <20210402055807.858-3-ray.ni@intel.com> In-Reply-To: <20210402055807.858-1-ray.ni@intel.com> References: <20210402055807.858-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: S73uu4BjcNPzFOpbIqhEtyuHx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617343107; bh=9OwcTQ2EA6Ic/NlMSrxvaj5LZtPyPFQ3+8z1a1FILYk=; h=Cc:Date:From:Reply-To:Subject:To; b=brh7MMUXct0BwufgWtXWk0ogaaFSoH9cVugLGnqzrG6w2hYwYo+3F75ZSQKYgncRN40 sm8615QmJei1atWQhRy6788uMW5IrhW1GULPiuhwOMBOGwtTsD6yK+E7ZFzGyLMY6I2W9 kAPaZ+6V2WCT6UJ7cDoU/DYnxBzqM/K3fho= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Ray Ni Cc: Laszlo Ersek Cc: Ard Biesheuvel Cc: Jordan Justen Reviewed-by: Laszlo Ersek --- OvmfPkg/AmdSev/AmdSevX64.dsc | 1 + OvmfPkg/Bhyve/BhyveX64.dsc | 1 + OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + OvmfPkg/OvmfXen.dsc | 1 + 6 files changed, 6 insertions(+) diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index de21312e6f..cdb29d5314 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -153,6 +153,7 @@ [LibraryClasses] OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf + MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf diff --git a/OvmfPkg/Bhyve/BhyveX64.dsc b/OvmfPkg/Bhyve/BhyveX64.dsc index 52cbed9c2e..7d9e880400 100644 --- a/OvmfPkg/Bhyve/BhyveX64.dsc +++ b/OvmfPkg/Bhyve/BhyveX64.dsc @@ -152,6 +152,7 @@ [LibraryClasses] OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf + MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 396159ebe2..1730b6558b 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -158,6 +158,7 @@ [LibraryClasses] OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf + MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 21d58dca98..78a559da0d 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -162,6 +162,7 @@ [LibraryClasses] OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf + MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 2d61926dab..a7d747f6b4 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -162,6 +162,7 @@ [LibraryClasses] OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf + MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index 0336a74e70..86abe277c3 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -151,6 +151,7 @@ [LibraryClasses] OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf + MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73639): https://edk2.groups.io/g/devel/message/73639 Mute This Topic: https://groups.io/mt/81796733/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 19 08:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73640+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73640+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1617343103; cv=none; d=zohomail.com; s=zohoarc; b=SgvcAjJ39AQ4V8Buz9izh4P/xHOaAkmThQtJ661oCA0HhpMfvHi15ZwczkRNu97paZTSq7LUvEWOmldUiqGTm1jldaddyB6e1iANdEFgr4tIeMzgYx4C5Bb5T2g2oAafGVjg+n/VIBJ8fAvCVVL//Y8ENXCLzzCxiRay1MimBtU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617343103; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=tf/CbP0VOG/a//5EraW4avtfO1nsEGAhuMtPLLRrRK4=; b=nUwPfFFF2xct7m9nYhOclm3sRK8tqkO/0uLXJfRPxV1DwBIGyiH81Yh+o0x3noTTS2cQ23OwnTw02pS3Az62mIbCfr6U1bkBYFVrPZt32h3fB36kTxMJD/YKyNYQDahwapHq4kafiYhB+ifpTcRIoy4YcbhJjmCXpqe5D98ti58= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73640+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617343103736510.22554306804875; Thu, 1 Apr 2021 22:58:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id foOSYY1788612xN6Mw9hN4bE; Thu, 01 Apr 2021 22:58:23 -0700 X-Received: from mga09.intel.com (mga09.intel.com []) by mx.groups.io with SMTP id smtpd.web08.12337.1617343099200294881 for ; Thu, 01 Apr 2021 22:58:22 -0700 IronPort-SDR: Q/DHoNjIIYT1uzc1/NcofaWi8EKnYfQEwd3ba01JCb2cLDSFNxsqfd279ksNp8sz49cXS9Z6Zg 4BNrvtKIOqFQ== X-IronPort-AV: E=McAfee;i="6000,8403,9941"; a="192501541" X-IronPort-AV: E=Sophos;i="5.81,298,1610438400"; d="scan'208";a="192501541" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2021 22:58:22 -0700 IronPort-SDR: DqUe+zEuLJWIBtyiXgFiBMgiTFGYFPzLFFAUK5RMgJp7RGUkMQyug9qfWWRuOkWYguudSOhP2Q dkYAfaor0YYA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,298,1610438400"; d="scan'208";a="413029627" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.158.87]) by fmsmga008.fm.intel.com with ESMTP; 01 Apr 2021 22:58:21 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Maurice Ma , Guo Dong , Benjamin You Subject: [edk2-devel] [PATCH 3/4] UefiPayloadPkg/UefiPayloadPkg.dsc: Consume MicrocodeLib Date: Fri, 2 Apr 2021 13:58:06 +0800 Message-Id: <20210402055807.858-4-ray.ni@intel.com> In-Reply-To: <20210402055807.858-1-ray.ni@intel.com> References: <20210402055807.858-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: wxKwxXhAbyBSUNrWIl6RAWU2x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617343103; bh=WJuYTjoGiB0p002Eal++Xr9c3qK8+9kb08H3dxziRbE=; h=Cc:Date:From:Reply-To:Subject:To; b=Qn5LZyUOmgfMM3X5K8RsjDzhBuHn0NQl8Trg7O8c49lcQeUUj3l6tsQFML5MKRd6uVi cX/NUp4Qz19hHHPAGMMV9BsfTrPLRb/FKTrzH3Z8kX2fje7kO83Ki5nxTue6vKY1uCS3F 6iWREbZ+sGdbSX93imY29XyT4sFZta1RYvU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Ray Ni Cc: Maurice Ma Cc: Guo Dong Cc: Benjamin You Reviewed-by: Maurice Ma --- UefiPayloadPkg/UefiPayloadPkg.dsc | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload= Pkg.dsc index e3b017858e..37ad5a0ae7 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -180,6 +180,7 @@ [LibraryClasses] # MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf + MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf =20 # # Platform --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 01 Apr 2021 22:58:24 -0700 IronPort-SDR: okGGpaZ6rQ/hE6HDGhAKzd80oGgliKx8TwLeY9S7vvSVBaLkCxjxhagh94dsiFDYPlbi6Fanp9 MRNFKfmXkpRQ== X-IronPort-AV: E=McAfee;i="6000,8403,9941"; a="192501556" X-IronPort-AV: E=Sophos;i="5.81,298,1610438400"; d="scan'208";a="192501556" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2021 22:58:24 -0700 IronPort-SDR: SDPNpfm78uISlygaeVlUr0tO+kN5qMAw9wpI1aOegPOgslztPLJDxnpL+N2uySuGwknOMiwRaz p4I0rNbZGyuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,298,1610438400"; d="scan'208";a="413029646" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.158.87]) by fmsmga008.fm.intel.com with ESMTP; 01 Apr 2021 22:58:22 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Laszlo Ersek , Rahul Kumar Subject: [edk2-devel] [PATCH 4/4] UefiCpuPkg/MpInitLib: Consume MicrocodeLib to remove duplicated code Date: Fri, 2 Apr 2021 13:58:07 +0800 Message-Id: <20210402055807.858-5-ray.ni@intel.com> In-Reply-To: <20210402055807.858-1-ray.ni@intel.com> References: <20210402055807.858-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: FRdQyfxTeyMUEsMWT2C5lcBgx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617343105; bh=A3JyY23D4FsCqieldsSyU57ffckv0ukuqVifeusYt7c=; h=Cc:Date:From:Reply-To:Subject:To; b=m3AwOJh7l/LOgxrOkWGDWX+WdD9o566EBxa7o3CtxxH0Bv4x1McjGcL/T+JM586fv27 6bFe3/tTW53HkeSHBJENguOYhTRhW3QL+HsQpoJr8qQrrlxh0lw590RdMyqkZPNGfz8P+ i8ZUNzwUD6hjVxyxHqj+B0I+SgsiofnZR1I= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Cc: Rahul Kumar Acked-by: Laszlo Ersek Reviewed-by: Eric Dong --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 1 + UefiCpuPkg/Library/MpInitLib/Microcode.c | 484 ++++-------------- UefiCpuPkg/Library/MpInitLib/MpLib.h | 1 + UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 1 + 4 files changed, 96 insertions(+), 391 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index 860a9750e2..d34419c2a5 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -52,6 +52,7 @@ [LibraryClasses] SynchronizationLib PcdLib VmgExitLib + MicrocodeLib =20 [Protocols] gEfiTimerArchProtocolGuid ## SOMETIMES_CONSUMES diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index 297c2abcd1..105a9f84bf 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -1,70 +1,16 @@ /** @file Implementation of loading microcode on processors. =20 - Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 #include "MpLib.h" =20 -/** - Get microcode update signature of currently loaded microcode update. - - @return Microcode signature. -**/ -UINT32 -GetCurrentMicrocodeSignature ( - VOID - ) -{ - MSR_IA32_BIOS_SIGN_ID_REGISTER BiosSignIdMsr; - - AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0); - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL); - BiosSignIdMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID); - return BiosSignIdMsr.Bits.MicrocodeUpdateSignature; -} - /** Detect whether specified processor can find matching microcode patch and= load it. =20 - Microcode Payload as the following format: - +----------------------------------------+------------------+ - | CPU_MICROCODE_HEADER | | - +----------------------------------------+ CheckSum Part1 | - | Microcode Binary | | - +----------------------------------------+------------------+ - | CPU_MICROCODE_EXTENDED_TABLE_HEADER | | - +----------------------------------------+ CheckSum Part2 | - | CPU_MICROCODE_EXTENDED_TABLE | | - | ... | | - +----------------------------------------+------------------+ - - There may by multiple CPU_MICROCODE_EXTENDED_TABLE in this format. - The count of CPU_MICROCODE_EXTENDED_TABLE is indicated by ExtendedSignat= ureCount - of CPU_MICROCODE_EXTENDED_TABLE_HEADER structure. - - When we are trying to verify the CheckSum32 with extended table. - We should use the fields of exnteded table to replace the corresponding - fields in CPU_MICROCODE_HEADER structure, and recalculate the - CheckSum32 with CPU_MICROCODE_HEADER + Microcode Binary. We named - it as CheckSum Part3. - - The CheckSum Part2 is used to verify the CPU_MICROCODE_EXTENDED_TABLE_HE= ADER - and CPU_MICROCODE_EXTENDED_TABLE parts. We should make sure CheckSum Par= t2 - is correct before we are going to verify each CPU_MICROCODE_EXTENDED_TAB= LE. - - Only ProcessorSignature, ProcessorFlag and CheckSum are different between - CheckSum Part1 and CheckSum Part3. To avoid multiple computing CheckSum = Part3. - Save an in-complete CheckSum32 from CheckSum Part1 for common parts. - When we are going to calculate CheckSum32, just should use the correspon= ding part - of the ProcessorSignature, ProcessorFlag and CheckSum with in-complete C= heckSum32. - - Notes: CheckSum32 is not a strong verification. - It does not guarantee that the data has not been modified. - CPU has its own mechanism to verify Microcode Binary part. - @param[in] CpuMpData The pointer to CPU MP Data structure. @param[in] ProcessorNumber The handle number of the processor. The ran= ge is from 0 to the total number of logical proce= ssors @@ -76,26 +22,13 @@ MicrocodeDetect ( IN UINTN ProcessorNumber ) { - UINT32 ExtendedTableLength; - UINT32 ExtendedTableCount; - CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; - CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; - CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + CPU_MICROCODE_HEADER *Microcode; UINTN MicrocodeEnd; - UINTN Index; - UINT8 PlatformId; - CPUID_VERSION_INFO_EAX Eax; - CPU_AP_DATA *CpuData; - UINT32 CurrentRevision; + CPU_AP_DATA *BspData; UINT32 LatestRevision; - UINTN TotalSize; - UINT32 CheckSum32; - UINT32 InCompleteCheckSum32; - BOOLEAN CorrectMicrocode; - VOID *MicrocodeData; - MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; + CPU_MICROCODE_HEADER *LatestMicrocode; UINT32 ThreadId; - BOOLEAN IsBspCallIn; + EDKII_PEI_MICROCODE_CPU_ID MicrocodeCpuId; =20 if (CpuMpData->MicrocodePatchRegionSize =3D=3D 0) { // @@ -104,9 +37,6 @@ MicrocodeDetect ( return; } =20 - CurrentRevision =3D GetCurrentMicrocodeSignature (); - IsBspCallIn =3D (ProcessorNumber =3D=3D (UINTN)CpuMpData->BspNumber)= ? TRUE : FALSE; - GetProcessorLocationByApicId (GetInitialApicId (), NULL, NULL, &ThreadId= ); if (ThreadId !=3D 0) { // @@ -115,156 +45,35 @@ MicrocodeDetect ( return; } =20 - ExtendedTableLength =3D 0; - // - // Here data of CPUID leafs have not been collected into context buffer,= so - // GetProcessorCpuid() cannot be used here to retrieve CPUID data. - // - AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); + GetProcessorMicrocodeCpuId (&MicrocodeCpuId); =20 - // - // The index of platform information resides in bits 50:52 of MSR IA32_P= LATFORM_ID - // - PlatformIdMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_PLATFORM_ID); - PlatformId =3D (UINT8) PlatformIdMsr.Bits.PlatformId; - - - // - // Check whether AP has same processor with BSP. - // If yes, direct use microcode info saved by BSP. - // - if (!IsBspCallIn) { + if (ProcessorNumber !=3D (UINTN) CpuMpData->BspNumber) { // - // Get the CPU data for BSP + // Direct use microcode of BSP if AP is the same as BSP. + // Assume BSP calls this routine() before AP. // - CpuData =3D &(CpuMpData->CpuData[CpuMpData->BspNumber]); - if ((CpuData->ProcessorSignature =3D=3D Eax.Uint32) && - (CpuData->PlatformId =3D=3D PlatformId) && - (CpuData->MicrocodeEntryAddr !=3D 0)) { - MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *)(UINTN) CpuData->Mic= rocodeEntryAddr; - MicrocodeData =3D (VOID *) (MicrocodeEntryPoint + 1); - LatestRevision =3D MicrocodeEntryPoint->UpdateRevision; - goto Done; + BspData =3D &(CpuMpData->CpuData[CpuMpData->BspNumber]); + if ((BspData->ProcessorSignature =3D=3D MicrocodeCpuId.ProcessorSignat= ure) && + (BspData->PlatformId =3D=3D MicrocodeCpuId.PlatformId) && + (BspData->MicrocodeEntryAddr !=3D 0)) { + LatestMicrocode =3D (CPU_MICROCODE_HEADER *)(UINTN) BspData->Microco= deEntryAddr; + LatestRevision =3D LatestMicrocode->UpdateRevision; + goto LoadMicrocode; } } =20 - LatestRevision =3D 0; - MicrocodeData =3D NULL; - MicrocodeEnd =3D (UINTN) (CpuMpData->MicrocodePatchAddress + CpuMpData->= MicrocodePatchRegionSize); - MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->Micr= ocodePatchAddress; + // + // BSP or AP which is different from BSP runs here + // Use 0 as the starting revision to search for microcode because Microc= odePatchInfo HOB needs + // the latest microcode location even it's loaded to the processor. + // + LatestRevision =3D 0; + LatestMicrocode =3D NULL; + Microcode =3D (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->Microcod= ePatchAddress; + MicrocodeEnd =3D (UINTN) Microcode + (UINTN) CpuMpData->MicrocodePatc= hRegionSize; =20 do { - // - // Check if the microcode is for the Cpu and the version is newer - // and the update can be processed on the platform - // - CorrectMicrocode =3D FALSE; - - if (MicrocodeEntryPoint->DataSize =3D=3D 0) { - TotalSize =3D sizeof (CPU_MICROCODE_HEADER) + 2000; - } else { - TotalSize =3D sizeof (CPU_MICROCODE_HEADER) + MicrocodeEntryPoint->D= ataSize; - } - - /// - /// 0x0 MicrocodeBegin MicrocodeEntry MicrocodeEnd 0xffff= ffff - /// |--------------|---------------|---------------|---------------| - /// valid TotalSize - /// TotalSize is only valid between 0 and (MicrocodeEnd - MicrocodeEnt= ry). - /// And it should be aligned with 4 bytes. - /// If the TotalSize is invalid, skip 1KB to check next entry. - /// - if ( (UINTN)MicrocodeEntryPoint > (MAX_ADDRESS - TotalSize) || - ((UINTN)MicrocodeEntryPoint + TotalSize) > MicrocodeEnd || - (TotalSize & 0x3) !=3D 0 - ) { - MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) Microcode= EntryPoint) + SIZE_1KB); - continue; - } - - // - // Save an in-complete CheckSum32 from CheckSum Part1 for common parts. - // - InCompleteCheckSum32 =3D CalculateSum32 ( - (UINT32 *) MicrocodeEntryPoint, - TotalSize - ); - InCompleteCheckSum32 -=3D MicrocodeEntryPoint->ProcessorSignature.Uint= 32; - InCompleteCheckSum32 -=3D MicrocodeEntryPoint->ProcessorFlags; - InCompleteCheckSum32 -=3D MicrocodeEntryPoint->Checksum; - - if (MicrocodeEntryPoint->HeaderVersion =3D=3D 0x1) { - // - // It is the microcode header. It is not the padding data between mi= crocode patches - // because the padding data should not include 0x00000001 and it sho= uld be the repeated - // byte format (like 0xXYXYXYXY....). - // - if (MicrocodeEntryPoint->ProcessorSignature.Uint32 =3D=3D Eax.Uint32= && - MicrocodeEntryPoint->UpdateRevision > LatestRevision && - (MicrocodeEntryPoint->ProcessorFlags & (1 << PlatformId)) - ) { - // - // Calculate CheckSum Part1. - // - CheckSum32 =3D InCompleteCheckSum32; - CheckSum32 +=3D MicrocodeEntryPoint->ProcessorSignature.Uint32; - CheckSum32 +=3D MicrocodeEntryPoint->ProcessorFlags; - CheckSum32 +=3D MicrocodeEntryPoint->Checksum; - if (CheckSum32 =3D=3D 0) { - CorrectMicrocode =3D TRUE; - } - } else if ((MicrocodeEntryPoint->DataSize !=3D 0) && - (MicrocodeEntryPoint->UpdateRevision > LatestRevision)) { - ExtendedTableLength =3D MicrocodeEntryPoint->TotalSize - (Microcod= eEntryPoint->DataSize + - sizeof (CPU_MICROCODE_HEADER)); - if (ExtendedTableLength !=3D 0) { - // - // Extended Table exist, check if the CPU in support list - // - ExtendedTableHeader =3D (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) = ((UINT8 *) (MicrocodeEntryPoint) - + MicrocodeEntryPoint->DataSize + sizeof= (CPU_MICROCODE_HEADER)); - // - // Calculate Extended Checksum - // - if ((ExtendedTableLength % 4) =3D=3D 0) { - // - // Calculate CheckSum Part2. - // - CheckSum32 =3D CalculateSum32 ((UINT32 *) ExtendedTableHeader,= ExtendedTableLength); - if (CheckSum32 =3D=3D 0) { - // - // Checksum correct - // - ExtendedTableCount =3D ExtendedTableHeader->ExtendedSignatur= eCount; - ExtendedTable =3D (CPU_MICROCODE_EXTENDED_TABLE *) (Ext= endedTableHeader + 1); - for (Index =3D 0; Index < ExtendedTableCount; Index ++) { - // - // Calculate CheckSum Part3. - // - CheckSum32 =3D InCompleteCheckSum32; - CheckSum32 +=3D ExtendedTable->ProcessorSignature.Uint32; - CheckSum32 +=3D ExtendedTable->ProcessorFlag; - CheckSum32 +=3D ExtendedTable->Checksum; - if (CheckSum32 =3D=3D 0) { - // - // Verify Header - // - if ((ExtendedTable->ProcessorSignature.Uint32 =3D=3D Eax= .Uint32) && - (ExtendedTable->ProcessorFlag & (1 << PlatformId)) )= { - // - // Find one - // - CorrectMicrocode =3D TRUE; - break; - } - } - ExtendedTable ++; - } - } - } - } - } - } else { + if (!IsValidMicrocode (Microcode, MicrocodeEnd - (UINTN) Microcode, La= testRevision, &MicrocodeCpuId, 1, TRUE)) { // // It is the padding data between the microcode patches for microcod= e patches alignment. // Because the microcode patch is the multiple of 1-KByte, the paddi= ng data should not @@ -272,156 +81,40 @@ MicrocodeDetect ( // alignment value should be larger than 1-KByte. We could skip SIZE= _1KB padding data to // find the next possible microcode patch header. // - MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) Microcode= EntryPoint) + SIZE_1KB); + Microcode =3D (CPU_MICROCODE_HEADER *) ((UINTN) Microcode + SIZE_1KB= ); continue; } - // - // Get the next patch. - // - if (MicrocodeEntryPoint->DataSize =3D=3D 0) { - TotalSize =3D 2048; - } else { - TotalSize =3D MicrocodeEntryPoint->TotalSize; - } + LatestMicrocode =3D Microcode; + LatestRevision =3D LatestMicrocode->UpdateRevision; =20 - if (CorrectMicrocode) { - LatestRevision =3D MicrocodeEntryPoint->UpdateRevision; - MicrocodeData =3D (VOID *) ((UINTN) MicrocodeEntryPoint + sizeof (CP= U_MICROCODE_HEADER)); - } - - MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEn= tryPoint) + TotalSize); - } while (((UINTN) MicrocodeEntryPoint < MicrocodeEnd)); + Microcode =3D (CPU_MICROCODE_HEADER *) (((UINTN) Microcode) + GetMicro= codeLength (Microcode)); + } while ((UINTN) Microcode < MicrocodeEnd); =20 -Done: +LoadMicrocode: if (LatestRevision !=3D 0) { // - // Save the detected microcode patch entry address (including the - // microcode patch header) for each processor. + // Save the detected microcode patch entry address (including the micr= ocode + // patch header) for each processor even it's the same as the loaded o= ne. // It will be used when building the microcode patch cache HOB. // - CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr =3D - (UINTN) MicrocodeData - sizeof (CPU_MICROCODE_HEADER); + CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr =3D (UINTN) Lat= estMicrocode; } =20 - if (LatestRevision > CurrentRevision) { + if (LatestRevision > GetProcessorMicrocodeSignature ()) { // // BIOS only authenticate updates that contain a numerically larger re= vision // than the currently loaded revision, where Current Signature < New U= pdate // Revision. A processor with no loaded update is considered to have a // revision equal to zero. // - ASSERT (MicrocodeData !=3D NULL); - AsmWriteMsr64 ( - MSR_IA32_BIOS_UPDT_TRIG, - (UINT64) (UINTN) MicrocodeData - ); - } - CpuMpData->CpuData[ProcessorNumber].MicrocodeRevision =3D GetCurrentMicr= ocodeSignature (); -} - -/** - Determine if a microcode patch matchs the specific processor signature a= nd flag. - - @param[in] CpuMpData The pointer to CPU MP Data structure. - @param[in] ProcessorSignature The processor signature field value - supported by a microcode patch. - @param[in] ProcessorFlags The prcessor flags field value support= ed by - a microcode patch. - - @retval TRUE The specified microcode patch will be loaded. - @retval FALSE The specified microcode patch will not be loaded. -**/ -BOOLEAN -IsProcessorMatchedMicrocodePatch ( - IN CPU_MP_DATA *CpuMpData, - IN UINT32 ProcessorSignature, - IN UINT32 ProcessorFlags - ) -{ - UINTN Index; - CPU_AP_DATA *CpuData; - - for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { - CpuData =3D &CpuMpData->CpuData[Index]; - if ((ProcessorSignature =3D=3D CpuData->ProcessorSignature) && - (ProcessorFlags & (1 << CpuData->PlatformId)) !=3D 0) { - return TRUE; - } + LoadMicrocode (LatestMicrocode); } - - return FALSE; -} - -/** - Check the 'ProcessorSignature' and 'ProcessorFlags' of the microcode - patch header with the CPUID and PlatformID of the processors within - system to decide if it will be copied into memory. - - @param[in] CpuMpData The pointer to CPU MP Data structure. - @param[in] MicrocodeEntryPoint The pointer to the microcode patch hea= der. - - @retval TRUE The specified microcode patch need to be loaded. - @retval FALSE The specified microcode patch dosen't need to be loaded. -**/ -BOOLEAN -IsMicrocodePatchNeedLoad ( - IN CPU_MP_DATA *CpuMpData, - CPU_MICROCODE_HEADER *MicrocodeEntryPoint - ) -{ - BOOLEAN NeedLoad; - UINTN DataSize; - UINTN TotalSize; - CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; - UINT32 ExtendedTableCount; - CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; - UINTN Index; - // - // Check the 'ProcessorSignature' and 'ProcessorFlags' in microcode patc= h header. + // It's possible that the microcode fails to load. Just capture the CPU = microcode revision after loading. // - NeedLoad =3D IsProcessorMatchedMicrocodePatch ( - CpuMpData, - MicrocodeEntryPoint->ProcessorSignature.Uint32, - MicrocodeEntryPoint->ProcessorFlags - ); - - // - // If the Extended Signature Table exists, check if the processor is in = the - // support list - // - DataSize =3D MicrocodeEntryPoint->DataSize; - TotalSize =3D (DataSize =3D=3D 0) ? 2048 : MicrocodeEntryPoint->TotalSiz= e; - if ((!NeedLoad) && (DataSize !=3D 0) && - (TotalSize - DataSize > sizeof (CPU_MICROCODE_HEADER) + - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)= )) { - ExtendedTableHeader =3D (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINT= 8 *) (MicrocodeEntryPoint) - + DataSize + sizeof (CPU_MICROCODE_HEADER)); - ExtendedTableCount =3D ExtendedTableHeader->ExtendedSignatureCount; - ExtendedTable =3D (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTabl= eHeader + 1); - - for (Index =3D 0; Index < ExtendedTableCount; Index ++) { - // - // Check the 'ProcessorSignature' and 'ProcessorFlag' of the Extended - // Signature Table entry with the CPUID and PlatformID of the proces= sors - // within system to decide if it will be copied into memory - // - NeedLoad =3D IsProcessorMatchedMicrocodePatch ( - CpuMpData, - ExtendedTable->ProcessorSignature.Uint32, - ExtendedTable->ProcessorFlag - ); - if (NeedLoad) { - break; - } - ExtendedTable ++; - } - } - - return NeedLoad; + CpuMpData->CpuData[ProcessorNumber].MicrocodeRevision =3D GetProcessorMi= crocodeSignature (); } =20 - /** Actual worker function that shadows the required microcode patches into = memory. =20 @@ -491,14 +184,16 @@ ShadowMicrocodePatchByPcd ( IN OUT CPU_MP_DATA *CpuMpData ) { + UINTN Index; CPU_MICROCODE_HEADER *MicrocodeEntryPoint; UINTN MicrocodeEnd; - UINTN DataSize; UINTN TotalSize; MICROCODE_PATCH_INFO *PatchInfoBuffer; UINTN MaxPatchNumber; UINTN PatchCount; UINTN TotalLoadSize; + EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds; + BOOLEAN Valid; =20 // // Initialize the microcode patch related fields in CpuMpData as the val= ues @@ -526,12 +221,34 @@ ShadowMicrocodePatchByPcd ( return; } =20 + MicrocodeCpuIds =3D AllocatePages ( + EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * sizeof (EDK= II_PEI_MICROCODE_CPU_ID)) + ); + if (MicrocodeCpuIds =3D=3D NULL) { + FreePool (PatchInfoBuffer); + return; + } + + for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { + MicrocodeCpuIds[Index].PlatformId =3D CpuMpData->CpuData[Index= ].PlatformId; + MicrocodeCpuIds[Index].ProcessorSignature =3D CpuMpData->CpuData[Index= ].ProcessorSignature; + } + // // Process the header of each microcode patch within the region. // The purpose is to decide which microcode patch(es) will be loaded int= o memory. + // Microcode checksum is not verified because it's slow when performing = on flash. // do { - if (MicrocodeEntryPoint->HeaderVersion !=3D 0x1) { + Valid =3D IsValidMicrocode ( + MicrocodeEntryPoint, + MicrocodeEnd - (UINTN) MicrocodeEntryPoint, + 0, + MicrocodeCpuIds, + CpuMpData->CpuCount, + FALSE + ); + if (!Valid) { // // Padding data between the microcode patches, skip 1KB to check nex= t entry. // @@ -539,59 +256,44 @@ ShadowMicrocodePatchByPcd ( continue; } =20 - DataSize =3D MicrocodeEntryPoint->DataSize; - TotalSize =3D (DataSize =3D=3D 0) ? 2048 : MicrocodeEntryPoint->TotalS= ize; - if ( (UINTN)MicrocodeEntryPoint > (MAX_ADDRESS - TotalSize) || - ((UINTN)MicrocodeEntryPoint + TotalSize) > MicrocodeEnd || - (DataSize & 0x3) !=3D 0 || - (TotalSize & (SIZE_1KB - 1)) !=3D 0 || - TotalSize < DataSize - ) { + PatchCount++; + if (PatchCount > MaxPatchNumber) { // - // Not a valid microcode header, skip 1KB to check next entry. + // Current 'PatchInfoBuffer' cannot hold the information, double the= size + // and allocate a new buffer. // - MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) Microcode= EntryPoint) + SIZE_1KB); - continue; - } - - if (IsMicrocodePatchNeedLoad (CpuMpData, MicrocodeEntryPoint)) { - PatchCount++; - if (PatchCount > MaxPatchNumber) { + if (MaxPatchNumber > MAX_UINTN / 2 / sizeof (MICROCODE_PATCH_INFO)) { // - // Current 'PatchInfoBuffer' cannot hold the information, double t= he size - // and allocate a new buffer. + // Overflow check for MaxPatchNumber // - if (MaxPatchNumber > MAX_UINTN / 2 / sizeof (MICROCODE_PATCH_INFO)= ) { - // - // Overflow check for MaxPatchNumber - // - goto OnExit; - } - - PatchInfoBuffer =3D ReallocatePool ( - MaxPatchNumber * sizeof (MICROCODE_PATCH_INFO), - 2 * MaxPatchNumber * sizeof (MICROCODE_PATCH_I= NFO), - PatchInfoBuffer - ); - if (PatchInfoBuffer =3D=3D NULL) { - goto OnExit; - } - MaxPatchNumber =3D MaxPatchNumber * 2; + goto OnExit; } =20 - // - // Store the information of this microcode patch - // - PatchInfoBuffer[PatchCount - 1].Address =3D (UINTN) MicrocodeEntryPo= int; - PatchInfoBuffer[PatchCount - 1].Size =3D TotalSize; - TotalLoadSize +=3D TotalSize; + PatchInfoBuffer =3D ReallocatePool ( + MaxPatchNumber * sizeof (MICROCODE_PATCH_INFO), + 2 * MaxPatchNumber * sizeof (MICROCODE_PATCH_INF= O), + PatchInfoBuffer + ); + if (PatchInfoBuffer =3D=3D NULL) { + goto OnExit; + } + MaxPatchNumber =3D MaxPatchNumber * 2; } =20 + TotalSize =3D GetMicrocodeLength (MicrocodeEntryPoint); + + // + // Store the information of this microcode patch + // + PatchInfoBuffer[PatchCount - 1].Address =3D (UINTN) MicrocodeEntryPoin= t; + PatchInfoBuffer[PatchCount - 1].Size =3D TotalSize; + TotalLoadSize +=3D TotalSize; + // // Process the next microcode patch // - MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEn= tryPoint) + TotalSize); - } while (((UINTN) MicrocodeEntryPoint < MicrocodeEnd)); + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) ((UINTN) MicrocodeEnt= ryPoint + TotalSize); + } while ((UINTN) MicrocodeEntryPoint < MicrocodeEnd); =20 if (PatchCount !=3D 0) { DEBUG (( @@ -607,7 +309,7 @@ OnExit: if (PatchInfoBuffer !=3D NULL) { FreePool (PatchInfoBuffer); } - return; + FreePages (MicrocodeCpuIds, EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * siz= eof (EDKII_PEI_MICROCODE_CPU_ID))); } =20 /** diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 66f9eb2304..e88a5355c9 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -32,6 +32,7 @@ #include #include #include +#include =20 #include =20 diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index 49b0ffe8be..36fcb96b58 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -51,6 +51,7 @@ [LibraryClasses] PeiServicesLib PcdLib VmgExitLib + MicrocodeLib =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONS= UMES --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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