From nobody Tue Feb 10 09:10:50 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73613+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73613+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1617287766; cv=none; d=zohomail.com; s=zohoarc; b=FdPSF4O96OaBRqeYDgR5B4fMgTpWw9V19NF8wTCcA9GQr6Z1D065ECUIAd+bbqPBeuUzkSTqJ5Wv92aYNwPz6tu6ae1QgllqISVJlxvVHnXFn6fhfA+wy1n7aFnl5nzVIdEYQJzx0IuIpe7eCV8WOTGmo/o7jygt1aO4EYl46d8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617287766; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=J425TJ8TUQH+msYKdPSETRYXUXDDNZdC+6LH6+Wm5Do=; b=iCi0TH7aUD1U0GBcA6eg7KFRq2aAoL4/7hBV296e/scGcOTVRR+GzCGiwZbVemC+atduhRU1/QfK10OpEjduulmdfK93xQSLhrDmITlU4tkEZ/icBE3k9XkaZZ50QGDXJSxmNE0+DpNcylzEDwL2K9RhGsWKFRkpPW7YaoK9Lcs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73613+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161728776645762.91097526633189; Thu, 1 Apr 2021 07:36:06 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id pFsmYY1788612xZj8X78rv8o; Thu, 01 Apr 2021 07:36:06 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.70.1617287763496692234 for ; Thu, 01 Apr 2021 07:36:03 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1FF1315BE; Thu, 1 Apr 2021 07:36:03 -0700 (PDT) X-Received: from usa.arm.com (a074744.blr.arm.com [10.162.17.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 75D0E3F719; Thu, 1 Apr 2021 07:36:01 -0700 (PDT) From: "chandni cherukuri" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Chandni Cherukuri Subject: [edk2-devel] [edk2-platforms][PATCH V2 5/7] Platform/ARM/Morello: Add initial support for Morello Platform Date: Thu, 1 Apr 2021 20:05:35 +0530 Message-Id: <20210401143537.4799-6-chandni.cherukuri@arm.com> In-Reply-To: <20210401143537.4799-1-chandni.cherukuri@arm.com> References: <20210401143537.4799-1-chandni.cherukuri@arm.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chandni.cherukuri@arm.com X-Gm-Message-State: J8cUQCKU00YyFPGi6ymx4PJQx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617287766; bh=bBcwCts1pXbdo+vRrQjxyvV6NWT0p3TBcr1330wIdyI=; h=Cc:Date:From:Reply-To:Subject:To; b=d5YdP1YFkuzgWDq8PrDlFtuGDUry3DjtK43oZ4C8c37cOmODvKMFMX4pyGeuYlHNYaR PbV7Y8yOOU2+4SpRypmDTH92zQAZ9WkMgR/9RbQSPNI2XnVceMuyNnfRbriQJ2O2GMV5R L0b6nu1CGWK0kg3rSA85wSCgZQeyPrwVkHA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Anurag Koul This patch adds the initial support for Morello FVP platform. Co-authored-by: Chandni Cherukuri Signed-off-by: Chandni Cherukuri Reviewed-by: Sami Mujawar --- Platform/ARM/Morello/MorelloPlatform.dec | 60 ++++ Platform/ARM/Morello/MorelloPlatform.dsc.inc | 236 +++++++++++++++ Platform/ARM/Morello/MorelloPlatformFvp.dsc | 61 ++++ Platform/ARM/Morello/MorelloPlatformFvp.fdf | 303 ++++++++++++++++++++ 4 files changed, 660 insertions(+) diff --git a/Platform/ARM/Morello/MorelloPlatform.dec b/Platform/ARM/Morell= o/MorelloPlatform.dec new file mode 100644 index 000000000000..9a674593cb3c --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatform.dec @@ -0,0 +1,60 @@ +## @file +# Describes the entire platform configuration. +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + PACKAGE_NAME =3D Morello + PACKAGE_GUID =3D F09A2C11-7864-4B1D-869E-03EE2AD79288 + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package + +[Guids.common] + gArmMorelloTokenSpaceGuid =3D { 0x0A8C3A78, 0xA56F, 0x4788, { 0x83, 0xB= 4, 0xCD, 0x29, 0x62, 0x96, 0x77, 0x51 } } + +[PcdsFixedAtBuild] + # Ramdisk + gArmMorelloTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 + gArmMorelloTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 + + # Secondary DDR memory + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000003 + + # Virtio Block device + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x00000000|UINT32|0x00= 000004 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize|0x00000000|UINT32|0x00000005 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt|0x00000000|UINT32|0x0000= 0006 + + # PCIe + gArmMorelloTokenSpaceGuid.PcdPciBusMin|0|UINT32|0x00000009 + gArmMorelloTokenSpaceGuid.PcdPciBusMax|15|UINT32|0x0000000A + gArmMorelloTokenSpaceGuid.PcdPciBusCount|16|UINT32|0x0000000B + gArmMorelloTokenSpaceGuid.PcdPciIoBase|0x0|UINT32|0x0000000C + gArmMorelloTokenSpaceGuid.PcdPciIoSize|0x00800000|UINT32|0x0000000D + gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase|0x007FFFFF|UINT32|0x0000000E + gArmMorelloTokenSpaceGuid.PcdPciIoTranslation|0x67800000|UINT32|0x000000= 0F + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base|0x60000000|UINT32|0x00000010 + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size|0x07800000|UINT32|0x00000011 + gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase|0x677FFFFF|UINT32|0x000000= 12 + gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT32|0x00000013 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base|0x900000000|UINT64|0x00000014 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size|0x2000000000|UINT64|0x00000015 + gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase|0x28FFFFFFFF|UINT64|0x0000= 0016 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000017 + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000|UINT64|0x0= 0000018 + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|FALSE|BOOLEAN|0x00000007 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000008 diff --git a/Platform/ARM/Morello/MorelloPlatform.dsc.inc b/Platform/ARM/Mo= rello/MorelloPlatform.dsc.inc new file mode 100644 index 000000000000..dccd22248318 --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatform.dsc.inc @@ -0,0 +1,236 @@ +## @file +# Component description file for Morello Platform +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmPlatformLib|Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf + BasePathLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + # Ramdisk Support + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + +[LibraryClasses.common.SEC] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + +[LibraryClasses.common.PEI_CORE, LibraryClasses.common.PEIM] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf + +[LibraryClasses.common.PEI_CORE] + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + +[LibraryClasses.common.PEIM] + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[LibraryClasses.common.DXE_CORE] + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +[LibraryClasses.common.DXE_DRIVER] + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf +!if $(TARGET) !=3D RELEASE + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibS= erialPort.inf +!endif + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION= , LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVE= R] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0 + + # System Memory (2GB - 16MB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 + + # Secondary DDR memory + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base|0x8080000000 + + # GIC Base Addresses + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000 + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 + + # PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2A400000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|50000000 + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95 + + # PL011 Serial Debug UART (DBG2) + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x1C0A0000 + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200 + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000 + + # SBSA Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93 + + # PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C100000 + + # ARM Architectural Timer Frequency + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000 + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1000 + + # ARM Cores and Clusters + gArmPlatformTokenSpaceGuid.PcdCoreCount|2 + gArmPlatformTokenSpaceGuid.PcdClusterCount|2 + + # ACPI Table Version + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + + # Runtime Variable storage + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + + # RAM Disk + gArmMorelloTokenSpaceGuid.PcdRamDiskBase|0x88000000 + gArmMorelloTokenSpaceGuid.PcdRamDiskSize|0x18000000 + + # PCIe + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000 + +[PcdsDynamicHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|0 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # PEI Phase modules + ArmPkg/Drivers/CpuPei/CpuPei.inf + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } + + # DXE + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + } + + # Architectural Protocols + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + + # ACPI Support + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # FAT filesystem + GPT/MBR partitioning + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # Bds + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + + # RAM Disk + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # Required by PCI + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # PCI Support + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F + } + + # AHCI Support + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # SATA Controller + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.dsc b/Platform/ARM/Mor= ello/MorelloPlatformFvp.dsc new file mode 100644 index 000000000000..35e02be5d5ab --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatformFvp.dsc @@ -0,0 +1,61 @@ +## @file +# Compoenent description file specific for Morello FVP Platform +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D morellofvp + PLATFORM_GUID =3D CB995FFD-EAEF-4d5E-8A4B-3213B39CD14A + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001B +!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY =3D $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) +!endif + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D NOOPT|DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/ARM/Morello/MorelloPlatformF= vp.fdf + BUILD_NUMBER =3D 1 + + # Network definition + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + +!include Platform/ARM/Morello/MorelloPlatform.dsc.inc +!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc +!include DynamicTablesPkg/DynamicTables.dsc.inc +!include Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp= .dsc.inc + +[LibraryClasses.common] + # Virtio Support + VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf + VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDevice= Lib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + +[LibraryClasses.common.DXE_DRIVER] + PciHostBridgeLib|Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBr= idgeLibFvp.inf + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|TRUE + +[PcdsFixedAtBuild.common] + # Virtio Disk + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x1C170000 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize|0x200 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt|128 + +[Components.common] + OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + + # Platform driver + Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.fdf b/Platform/ARM/Mor= ello/MorelloPlatformFvp.fdf new file mode 100644 index 000000000000..dc3eccd2f3ba --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatformFvp.fdf @@ -0,0 +1,303 @@ +## @file +# FDF file of Morello FVP platform +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.BL33_AP_UEFI] +BaseAddress =3D 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The ba= se address of the Firmware in NOR Flash. +Size =3D 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The si= ze in bytes of the FLASH Device +ErasePolarity =3D 1 + +# This one is tricky, it must be: BlockSize * NumBlocks =3D Size +BlockSize =3D 0x00001000 +NumBlocks =3D 0x200 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of +# different images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) +# followed by the pipe "|" character, followed by the size of the region, = also +# in hex with the leading "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### + +0x00000000|0x00200000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a +# flash device file. This section also defines order the components and mo= dules +# are positioned within the image. The [FV] section consists of define +# statements, set statements and module statements. +# +##########################################################################= ###### + +[FV.FvMain] +BlockSize =3D 0x40 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 8 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # PI DXE Drivers producing Architectural Protocols (EFI Services) + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + # ACPI Support + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # Configuration Manager + INF Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Co= nfigurationManagerDxeFvp.inf + + # Dynamic Table fdf + !include DynamicTablesPkg/DynamicTables.fdf.inc + + # Multiple Console IO support + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # Virtio Block Device support + INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + + # FAT filesystem + GPT/MBR partitioning + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + + # FV FileSystem + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.i= nf + INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # UEFI applications + INF ShellPkg/Application/Shell/Shell.inf + + # Platform driver + INF Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf + + # Bds + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + # Required by PCI + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # PCI Support + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # AHCI Support + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # SATA Controller + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 8 +BlockSize =3D 0x1000 +NumBlocks =3D 0x200 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } + + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + + +##########################################################################= ## +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section = # +##########################################################################= ## +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER =3D $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING=3D"$(MODULE_NAME)" Optional +# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N= UMBER) +# } +# } +# } +# +##########################################################################= ## + +# +# These SEC rules are used for ArmPlatformPkg/PrePeiCore module. +# ArmPlatformPkg/PrePeiCore is declared as a SEC module to make GenFv patch +# the UEFI Firmware to jump to ArmPlatformPkg/PrePeiCore entrypoint +# + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR= UE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + UI STRING =3D"$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73613): https://edk2.groups.io/g/devel/message/73613 Mute This Topic: https://groups.io/mt/81778210/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-