From nobody Tue Feb 10 09:02:02 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73609+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73609+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1617287759; cv=none; d=zohomail.com; s=zohoarc; b=mKxNEuFdk7NdWxrQA5wRXpZ/Rv3VoPhOxYqZLUqlJgOfBUscgH8+Fc20rQZo3Kkg7DDQDlGmFMlxMx5q2mYHF5LamIu5ABxqQT84gf8tuqKzr9XCgwzih3+IpPxnYVDdV4yp9CtHppbVKpYut5HgDN+LVIA0oXvYofGjtlqhSNM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617287759; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=0zfZzYEJ7im8dghOrQFkffwg8sow9PwwkwnQ8mZk5CA=; b=GVdfPo/DjDU6S0IF3Tkp2sWnl9gFqt/jdf+gM8sWlTxI2TLLeAfNAiDj0UrA/216uq6uhXYIjgvPbxNa0QoR4+/eFjBZL7FRMKmiprBPUBH3cUSqg2xLi9W/LU5LSZZA/3lkuoR/fULMlbFBOlauZo3YlxCCeGiL/LfZAPKbVYc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73609+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617287759127765.7666384118808; Thu, 1 Apr 2021 07:35:59 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id yDnaYY1788612xVd1naHf7BY; Thu, 01 Apr 2021 07:35:58 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.76.1617287754673008780 for ; Thu, 01 Apr 2021 07:35:54 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4301315BE; Thu, 1 Apr 2021 07:35:54 -0700 (PDT) X-Received: from usa.arm.com (a074744.blr.arm.com [10.162.17.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5FAA13F719; Thu, 1 Apr 2021 07:35:52 -0700 (PDT) From: "chandni cherukuri" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Chandni Cherukuri Subject: [edk2-devel] [edk2-platforms][PATCH V2 1/7] Platform/ARM/Morello: Add Platform library implementation Date: Thu, 1 Apr 2021 20:05:31 +0530 Message-Id: <20210401143537.4799-2-chandni.cherukuri@arm.com> In-Reply-To: <20210401143537.4799-1-chandni.cherukuri@arm.com> References: <20210401143537.4799-1-chandni.cherukuri@arm.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chandni.cherukuri@arm.com X-Gm-Message-State: e2WVrzf4kQiWmffTHseOuwyOx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617287758; bh=k4kQt4rBirR/mfoB09Zq2GpBmMJSCoeVG9ohwerzVLI=; h=Cc:Date:From:Reply-To:Subject:To; b=GuqpAMarVyF2YOlPpYr0x9WkATIRBU/zA53UXZp4qqv6Oc+auGMhCOnJOrOUJbB6WNJ P8NfG+8JzVPd8MjSVHy4FvMXXTYtw1hqa+IoSfLEVnLWda821opONbIBI6jyqmx/0i61D a+r5I/Itvs28r8z/v3PlsiyXsRyjuBuv3xU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Anurag Koul This patch adds initial Morello Platform Library support. It includes virtual memory map and helper functions for platform initialization. Co-authored-by: Chandni Cherukuri Signed-off-by: Chandni Cherukuri Reviewed-by: Sami Mujawar --- Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf | 52 +++++ Platform/ARM/Morello/Include/MorelloPlatform.h | 63 +++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c | 99 ++++++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c | 198 ++++++++++= ++++++++++ Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S | 83 ++++++++ 5 files changed, 495 insertions(+) diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf b/Pla= tform/ARM/Morello/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 000000000000..c2d7da3701d2 --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,52 @@ +## @file +# Platform Library for Morello platform. +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D ArmMorelloLib + FILE_GUID =3D 36853D86-7200-47B4-9408-E962A00963FD + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[Sources.common] + PlatformLib.c + PlatformLibMem.c + +[Sources.AARCH64] + AArch64/Helper.S | GCC + +[FixedPcd] + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress + gArmMorelloTokenSpaceGuid.PcdPciIoSize + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[Guids] + gEfiHobListGuid ## CONSUMES ## SystemTable + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/Morello/Include/MorelloPlatform.h b/Platform/ARM/= Morello/Include/MorelloPlatform.h new file mode 100644 index 000000000000..8b3233025958 --- /dev/null +++ b/Platform/ARM/Morello/Include/MorelloPlatform.h @@ -0,0 +1,63 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef MORELLO_PLATFORM_H_ +#define MORELLO_PLATFORM_H_ + +#define MORELLO_DRAM_BLOCK1_SIZE SIZE_2GB + +// ***********************************************************************= ***** +// Platform Memory Map +// ***********************************************************************= ***** + +// SubSystem Peripherals - UART0 +#define MORELLO_UART0_BASE 0x2A400000 +#define MORELLO_UART0_SZ SIZE_64KB + +// SubSystem Peripherals - UART1 +#define MORELLO_UART1_BASE 0x2A410000 +#define MORELLO_UART1_SZ SIZE_64KB + +// SubSystem Peripherals - Generic Watchdog +#define MORELLO_GENERIC_WDOG_BASE 0x2A440000 +#define MORELLO_GENERIC_WDOG_SZ SIZE_128KB + +// SubSystem Peripherals - GIC(600) +#define MORELLO_GIC_BASE 0x30000000 +#define MORELLO_GICR_BASE 0x300C0000 +#define MORELLO_GIC_SZ SIZE_256KB +#define MORELLO_GICR_SZ SIZE_1MB + +// SubSystem non-secure SRAM +#define MORELLO_NON_SECURE_SRAM_BASE 0x06000000 +#define MORELLO_NON_SECURE_SRAM_SZ SIZE_64KB + +// AXI Expansion peripherals +#define MORELLO_EXP_PERIPH_BASE 0x1C000000 +#define MORELLO_EXP_PERIPH_BASE_SZ 0x1300000 + +// Platform information structure base address +#define MORELLO_PLAT_INFO_STRUCT_BASE MORELLO_NON_SECURE_SRAM_BASE + +/* + * Platform information structure stored in Non-secure SRAM. Platform + * information are passed from the trusted firmware with the below structu= re + * format. The elements of MORELLO_PLAT_INFO should be always in sync with + * the lower level firmware. + */ +#pragma pack(1) + +typedef struct { + UINT64 LocalDdrSize; ///< Local DDR memory size in Bytes + UINT64 RemoteDdrSize; ///< Remote DDR memory size in Bytes + UINT8 SlaveCount; ///< Slave count in C2C mode + UINT8 Mode; ///< 0 - Single Chip, 1 - Chip to Chip (C2C) +} MORELLO_PLAT_INFO; + +#pragma pack() + +#endif //MORELLO_PLATFORM_H_ diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c b/Platf= orm/ARM/Morello/Library/PlatformLib/PlatformLib.c new file mode 100644 index 000000000000..52318a62911a --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,99 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +STATIC ARM_CORE_INFO mCoreInfoTable[] =3D { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 + { 0x1, 0x0 }, // Cluster 1, Core 0 + { 0x1, 0x1 } // Cluster 1, Core 1 +}; + +/** + Return the current Boot Mode. + + This function returns the boot reason on the platform. + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must be setup in the normal world. + + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/= PlatformPeim + in the PEI phase. + + @param[in] MpId Processor ID + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +/** + Populate the Platform core information. + + This function populates the ARM_MP_CORE_INFO_PPI with information about = the cores. + + @param[out] CoreCount Number of cores + @param[out] ArmCoreTable Table containing information about the cores + +**/ +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); + *ArmCoreTable =3D mCoreInfoTable; + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { + PrePeiCoreGetMpCoreInfo +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +/** + Return the Platform specific PPIs + + This function exposes the Morello Platform Specific PPIs. + + @param[out] PpiListSize Size in Bytes of the Platform PPI List + @param[out] PpiList Platform PPI List + +**/ +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c b/Pl= atform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 000000000000..54a870cfb3ba --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,198 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +// The total number of descriptors, including the final "end-of-table" des= criptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 + +#if !defined(MDEPKG_NDEBUG) +STATIC CONST CHAR8 *gTblAttrDesc[] =3D { + "UNCACHED_UNBUFFERED ", + "NONSECURE_UNCACHED_UNBUFFERED", + "WRITE_BACK ", + "NONSECURE_WRITE_BACK ", + "WB_NONSHAREABLE ", + "NONSECURE_WB_NONSHAREABLE ", + "WRITE_THROUGH ", + "NONSECURE_WRITE_THROUGH ", + "DEVICE ", + "NONSECURE_DEVICE " +}; +#endif + +#define LOG_MEM(desc) DEBUG (( = \ + DEBUG_ERROR, = \ + desc, = \ + VirtualMemoryTable[Index].PhysicalBase, = \ + (VirtualMemoryTable[Index].PhysicalBase + = \ + VirtualMemoryTable[Index].Length - 1), = \ + VirtualMemoryTable[Index].Length, = \ + gTblAttrDesc[VirtualMemoryTable[Index].Attributes]= \ + )); + +/** + Returns the Virtual Memory Map of the platform. + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing + a Physical-to-Virtual Memory mapping. This = array + must be ended by a zero-filled entry. +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + OUT ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + UINTN Index; + ARM_MEMORY_REGION_DESCRIPTOR * VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + MORELLO_PLAT_INFO * PlatInfo; + UINT64 DramBlock2Size; + + Index =3D 0; + DramBlock2Size =3D 0; + + PlatInfo =3D (MORELLO_PLAT_INFO *)MORELLO_PLAT_INFO_STRUCT_BASE; + if (PlatInfo->LocalDdrSize > MORELLO_DRAM_BLOCK1_SIZE) { + DramBlock2Size =3D PlatInfo->LocalDdrSize - MORELLO_DRAM_BLOCK1_SIZE; + } + + if (DramBlock2Size !=3D 0) { + ResourceAttributes =3D + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdDramBlock2Base), + DramBlock2Size + ); + } + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTO= R) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + DEBUG (( + DEBUG_ERROR, + " Memory Map\n--------------------------------------------------------= --\n" + )); + DEBUG (( + DEBUG_ERROR, + "Description : START - END = " \ + "[ SIZE ] { ATTR }\n" + )); + + // SubSystem Peripherals - Generic Watchdog + VirtualMemoryTable[Index].PhysicalBase =3D MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_GENERIC_WDOG_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("Generic Watchdog : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem Peripherals - GIC-600 + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_GIC_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_GIC_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_GIC_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("GIC-600 : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem Peripherals - GICR-600 + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_GICR_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_GICR_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_GICR_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("GICR-600 : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_NON_SECURE_SRAM_BA= SE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_NON_SECURE_SRAM_BA= SE; + VirtualMemoryTable[Index].Length =3D MORELLO_NON_SECURE_SRAM_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_UNCACHED_UNBUFFERED; + LOG_MEM ("non-secure SRAM : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem Pheripherals - UART0 + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_UART0_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_UART0_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_UART0_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("UART0 : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // DDR Primary + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemoryS= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_WRITE_BACK; + LOG_MEM ("DDR Primary : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // DDR Secondary + if (DramBlock2Size !=3D 0) { + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdDramBlock2B= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdDramBlock2B= ase); + VirtualMemoryTable[Index].Length =3D DramBlock2Size; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_WRITE_BACK; + LOG_MEM ("DDR Secondary : 0x%016lx - 0x%016lx [ 0x%0= 16lx ] { %a }\n"); + } + + // Expansion Peripherals + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_EXP_PERIPH_BASE_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("Expansion Peripherals : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // PCI Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciExpressBas= eAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciExpressBas= eAddress); + VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdPciBusM= ax) - + FixedPcdGet32 (PcdPciBusMin= ) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("PCI Configuration Space : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // PCI MMIO32/IO Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdPciMmio32Base= ); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdPciMmio32Base= ); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdPciMmio32Size= ) + + PcdGet32 (PcdPciIoSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("PCI MMIO32 & IO Region : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // PCI MMIO64 Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciMmio64Base= ); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciMmio64Base= ); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdPciMmio64Size= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("PCI MMIO64 Region : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBU= TES)0; + + ASSERT ((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S b/Pl= atform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S new file mode 100644 index 000000000000..f6cc087a132c --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S @@ -0,0 +1,83 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + ret + +// +// Return the core position from the value of its MpId register +// +// This function returns core position from the position 0 in the processo= r. +// This function might be called from assembler before any stack is set. +// +// @return Return the core position +// +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +// +// Return the MpId of the primary core +// +// This function returns the MpId of the primary core. +// This function might be called from assembler before any stack is set. +// +// @return Return the MpId of the primary core +// +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +// +// Return a non-zero value if the callee is the primary core +// +// This function returns a non-zero value if the callee is the primary cor= e. +// Primary core is the core responsible to initialize hardware and run UEF= I. +// This function might be called from assembler before any stack is set. +// +// @return Return a non-zero value if the callee is the primary core. +// +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73609): https://edk2.groups.io/g/devel/message/73609 Mute This Topic: https://groups.io/mt/81778203/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-