From nobody Fri Apr 26 03:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73578+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73578+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1617177241; cv=none; d=zohomail.com; s=zohoarc; b=DtQxt5OAve4oPdfxGk7bQH9Jd5kUIFcXlBcQol5e+GUzVtE9vcyhL7mNqjPhrtVwTyrEeFpkiDaAZYtmeuhK1L2oMsdcLVVFiqX0QlnBGV890WUR8HLr/FaDNVbUyqGuJ17z7dKk5a5PXwKSLlhdn8CL7sn3HXz56Ao0uxrVPFI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617177241; h=Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=KWjgMlpXgOHTiobiwSxSmiSqkFGXWje8bt8IFLL6ZMY=; b=noRR8wkUEYbSIm2Wl1kXIu/VN/eEX9ST1k5d4FuqnDNvYO77tzkAjwCVglDMTwof2VyLOVr064kpOH58rkTvs/ZH8I2aRGj+WUKiZCSaSiPD+hJEkhjP9+Bix2ILKExK81NZVCp/4na7ZUw+fpJeVkmnV0Jh1Q7mHN8Uigwzse0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73578+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161717724147848.619724489865575; Wed, 31 Mar 2021 00:54:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id LhlCYY1788612xszm48PGOJi; Wed, 31 Mar 2021 00:54:01 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.3501.1617177235178296640 for ; Wed, 31 Mar 2021 00:53:55 -0700 IronPort-SDR: Cl7ThiucxlrUSMHabAv1tHtkGCeiTuYYzUD5eljkEM6N8Q1swxScSBpf6pQyFbnV/ijyJ8LNnZ 38z5hs1z2DSg== X-IronPort-AV: E=McAfee;i="6000,8403,9939"; a="171969202" X-IronPort-AV: E=Sophos;i="5.81,293,1610438400"; d="scan'208";a="171969202" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2021 00:53:53 -0700 IronPort-SDR: mIXDECLpD6nPVIQqSE89V8M6KcxpBJ/IiWM4Z8jKgqENsxf9oUx+lO3/78uYL6yny7HmFGrw/f Jwyti/B02SPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,293,1610438400"; d="scan'208";a="418547141" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga008.jf.intel.com with ESMTP; 31 Mar 2021 00:53:50 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Yao Jiewen , Zhang Hongbin1 Subject: [edk2-devel] [PATCH v1] MdePkg/BaseLib: Add support for the XSETBV instruction Date: Wed, 31 Mar 2021 15:53:47 +0800 Message-Id: <20210331075347.11136-1-Jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: RylOd6O5zxgASTWzyuJAPfpwx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617177241; bh=z2ql7e6dKlVFfc4WjOjGbtgkGa0FO0BEGSarfd4PJmo=; h=Cc:Date:From:Reply-To:Subject:To; b=QFzOAGakR3+3NAFHGFyWPzZn/R249s52NHGtz65oKuJWZuWDSBqcY1/AHJOgvUpTAZy ZAhedkCXviil6eE3R5SGFr6uU/9lvqeceWdYHWNxptaCp1ox0uCe7t9fBBalIFYiDS22r +yPMzErb86wvak/Z6YolrS0dyxbTW//4mXc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" https://bugzilla.tianocore.org/show_bug.cgi?id=3D3284 This patch is to support XSETBV instruction so as to support Extended Control Register(XCR) write. Extended Control Register(XCR) read has already been supported by below commit to support XGETBV instruction: 9b3ca509abd4e45439bbdfe2c2fa8780c950320a Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Yao Jiewen Signed-off-by: Jiaxin Wu Signed-off-by: Zhang Hongbin1 --- MdePkg/Include/Library/BaseLib.h | 25 +++++++++++++++++++++++- MdePkg/Library/BaseLib/BaseLib.inf | 4 +++- MdePkg/Library/BaseLib/Ia32/XSetBv.nasm | 34 +++++++++++++++++++++++++++++= ++++ MdePkg/Library/BaseLib/X64/XSetBv.nasm | 34 +++++++++++++++++++++++++++++= ++++ 4 files changed, 95 insertions(+), 2 deletions(-) create mode 100644 MdePkg/Library/BaseLib/Ia32/XSetBv.nasm create mode 100644 MdePkg/Library/BaseLib/X64/XSetBv.nasm diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 1171a0ffb5..035d6b655d 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -1,10 +1,10 @@ /** @file Provides string functions, linked list functions, math functions, synchr= onization functions, file path functions, and CPU architecture-specific functions. =20 -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) Microsoft Corporation.
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -7436,10 +7436,33 @@ UINT64 EFIAPI AsmXGetBv ( IN UINT32 Index ); =20 +/** + Executes a XSETBV instruction to write a 64-bit value to a Extended Cont= rol Register(XCR), + and returns the value. + + Writes the 64-bit value specified by Value to the XCR specified by Index= . The + 64-bit value written to the XCR is returned. No parameter checking is + performed on Index or Value, and some of these may cause CPU exceptions.= The + caller must either guarantee that Index and Value are valid, or the call= er + must establish proper exception handlers. This function is only availabl= e on + IA-32 and x64. + + @param Index The 32-bit XCR index to write. + @param Value The 64-bit value to write to the XCR. + + @return Value + +**/ +UINT64 +EFIAPI +AsmXSetBv ( + IN UINT32 Index, + IN UINT64 Value + ); =20 /** Executes a VMGEXIT instruction (VMMCALL with a REP prefix) =20 Executes a VMGEXIT instruction. This function is only available on IA-32= and diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 3b85c56c3c..fe8f68bbcf 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -1,9 +1,9 @@ ## @file # Base Library implementation. # -# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -182,10 +182,11 @@ Ia32/LShiftU64.nasm| GCC Ia32/EnableCache.nasm| GCC Ia32/DisableCache.nasm| GCC Ia32/RdRand.nasm Ia32/XGetBv.nasm + Ia32/XSetBv.nasm Ia32/VmgExit.nasm =20 Ia32/DivS64x64Remainder.c Ia32/InternalSwitchStack.c | MSFT Ia32/InternalSwitchStack.nasm | GCC @@ -316,10 +317,11 @@ X64/GccInlinePriv.c | GCC X64/EnableDisableInterrupts.nasm X64/DisablePaging64.nasm X64/RdRand.nasm X64/XGetBv.nasm + X64/XSetBv.nasm X64/VmgExit.nasm ChkStkGcc.c | GCC =20 [Sources.EBC] Ebc/CpuBreakpoint.c diff --git a/MdePkg/Library/BaseLib/Ia32/XSetBv.nasm b/MdePkg/Library/BaseL= ib/Ia32/XSetBv.nasm new file mode 100644 index 0000000000..9fa2f761cd --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/XSetBv.nasm @@ -0,0 +1,34 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; XSetBv.nasm +; +; Abstract: +; +; AsmXSetBv function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + SECTION .text + +;-------------------------------------------------------------------------= ----- +; UINT64 +; EFIAPI +; AsmXSetBv ( +; IN UINT32 Index, +; IN UINT64 Value +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmXSetBv) +ASM_PFX(AsmXSetBv): + mov edx, [esp + 12] + mov eax, [esp + 8] + mov ecx, [esp + 4] + xsetbv + ret \ No newline at end of file diff --git a/MdePkg/Library/BaseLib/X64/XSetBv.nasm b/MdePkg/Library/BaseLi= b/X64/XSetBv.nasm new file mode 100644 index 0000000000..aa72419e7f --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/XSetBv.nasm @@ -0,0 +1,34 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; XSetBv.nasm +; +; Abstract: +; +; AsmXSetBv function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + DEFAULT REL + SECTION .text + +;-------------------------------------------------------------------------= ----- +; UINT64 +; EFIAPI +; AsmXSetBv ( +; IN UINT32 Index, +; IN UINT64 Value +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmXSetBv) +ASM_PFX(AsmXSetBv): + mov rax, rdx ; meanwhile, rax <- return value + shr rdx, 0x20 ; edx:eax contains the value to w= rite + xsetbv + ret \ No newline at end of file --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73578): https://edk2.groups.io/g/devel/message/73578 Mute This Topic: https://groups.io/mt/81744813/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-