From nobody Thu Apr 25 23:34:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73313+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73313+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1616741277; cv=none; d=zohomail.com; s=zohoarc; b=Kwho+x3BXHKwkxaH859bpH/wG/U5+SUOJS2AOOTIo9DV+Yn/7A8xIXLzA2iLGcrt6KZ0ixjkslzd37qslnBGbeaf+d80rSyrb+B8V9uZjPIUL4UmNta4kRoVak6N+mjtnJlcdIk+hNSkIAUPNhm1a19cOsilzdMf7VgDgACgqak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616741277; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=Kl6Rb/T4LTlCd5+fDHuNj2HyNsNPsCU7jLP0O8GURGk=; b=S8XKYxNMRD7xHyQC0YDvOYPV0X1WEJds3S69GGPP7wMoOJ0kgMYKzYl0hbpD/BgVaWU3/WLhGUkrMIcRbOcq/PgqrmfQyBmutHFfjQGtpa/+KtYRXcMTn1XB6iorgU2RvJPhFQoqcQcFVW6fIcBl3igqZg5Mu9gO/TTvLJMvjXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73313+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616741277043476.5329366578412; Thu, 25 Mar 2021 23:47:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id CsH8YY1788612xcFLPbHd5H6; Thu, 25 Mar 2021 23:47:54 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web09.8927.1616741273807615722 for ; Thu, 25 Mar 2021 23:47:53 -0700 IronPort-SDR: xdTnZCdCzZoHDH5GWvKaVujh/PkQul5cD4xkP4/sqMezmqq2bb8btYXLLaZW8K5fpJxj89OPCv 0HNeuPSc7ZXQ== X-IronPort-AV: E=McAfee;i="6000,8403,9934"; a="252444637" X-IronPort-AV: E=Sophos;i="5.81,279,1610438400"; d="scan'208";a="252444637" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2021 23:47:52 -0700 IronPort-SDR: cIPJVrpLV2B1Yj+6Djb/Wr4lEhayATWxW6UUzvAMrTIELKpMlWxBu7oovv8+L3CUk1DIipPsVX 5ddacEEd/atA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,279,1610438400"; d="scan'208";a="377143108" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.158.87]) by orsmga006.jf.intel.com with ESMTP; 25 Mar 2021 23:47:51 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Rangasai V Chaganty Subject: [edk2-devel] [PATCH] IntelSiliconPkg: Define PCDs for microcode location in flash Date: Fri, 26 Mar 2021 14:47:41 +0800 Message-Id: <20210326064741.1937-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: jpvKkN9vh39gsiCg2S31uHv4x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616741274; bh=vI6uLZ+jBKQYhKz+aIXl+cZsFMQdoHKsLKK3m3YwxUw=; h=Cc:Date:From:Reply-To:Subject:To; b=XDuW2HFBBzeryDDQcSHsj5i/OP1TbyP/KoCsaoZKuaYNjpK921UYbiMnw+6/HsA/EaN 9s4uEus/ffZlGCEGaOBAuXFulTXF/JxDYZMrX6Jqzmx2HI2VC26wR4S8D1xUPIr9+uBrr Q+cZdZUoUUEmcDFjE3sflPoi9IVhF7DfHQk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" 3 PCDs are defined assuming that microcode is put in the end of a FV: PcdFlashFvMicrocodeBase: The base address of the microcode FV PcdFlashFvMicrocodeSize: The size of the microcode FV PcdFlashMicrocodeOffset: The microcode offset relative to the FV base address The 3 new PCDs are to replace the following existing PCDs in MinPlatformPkg and IntelFsp2WrapperPkg. The ones in MinPlatformPkg will be removed in a separate patch. The ones in IntelFsp2WrapperPkg will be re-positioned as only using inside IntelFsp2WrapperPkg\Library\SecFspWrapperPlatformSecLibSample. Defining PCDs in IntelSiliconPkg is because certain close-source silicon code depends on these PCDs but the silicon code cannot depend on MinPlatformPkg. MinPlatformPkg contains the below 3 PCDs: PcdFlashFvMicrocodeBase: Same meaning as IntelSiliconPkg.PcdFlashFvMicrocodeBase PcdFlashFvMicrocodeSize: Same meaning as IntelSiliconPkg.PcdFlashFvMicrocodeSize PcdFlashFvMicrocodeOffset: The FV offset relative to the firmware base address. Note: MinPlatformPkg doesn't contain the PCD that tells the microcode offset relative to the FV base address. IntelFsp2WrapperPkg contains the below 3 PCDs: PcdCpuMicrocodePatchAddress: Same meaning as IntelSiliconPkg.PcdFlashFvMicrocodeBase PcdCpuMicrocodePatchRegionSize: Same meaning as IntelSiliconPkg.PcdFlashFvMicrocodeSize PcdFlashMicrocodeOffset: Same meaning as IntelSiliconPkg.PcdFlashMicrocodeOffset Change-Id: I708abfa4a9309cbaedd5c4e4f483ec9f0d5e7625 Reviewed-by: Ray Ni Cc: Rangasai V Chaganty --- Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index 4a2cbca5..6611c3af 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -3,7 +3,7 @@ # # This package provides common open source Intel silicon modules. # -# Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -90,6 +90,13 @@ # @Prompt Error code for VTd error. gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x= 00000005 =20 + gIntelSiliconPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0|UINT32|0x000000= 07 + gIntelSiliconPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0|UINT32|0x000000= 08 + + ## This is the microcode offset relative to the FV base address. + # Microcode address equals to PcdFlashFvMicrocodeBase + PcdFlashMicroco= deOffset. + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeOffset|0|UINT32|0x000000= 0A + [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## This is the GUID of the FFS which contains the Graphics Video BIOS Ta= ble (VBT) # The VBT content is stored as a RAW section which is consumed by GOP PE= I/UEFI driver. --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73313): https://edk2.groups.io/g/devel/message/73313 Mute This Topic: https://groups.io/mt/81622347/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-