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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id g10sm1153794lfu.265.2021.03.21.18.32.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Mar 2021 18:32:47 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ard.biesheuvel@arm.com, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com, jon@solid-run.com Subject: [edk2-devel] [edk2-platforms PATCH v2 1/4] Marvell/Armada7k8k: Remove device tree sources from edk2-platforms Date: Mon, 22 Mar 2021 02:32:29 +0100 Message-Id: <20210322013231.3216058-3-mw@semihalf.com> In-Reply-To: <20210322013231.3216058-1-mw@semihalf.com> References: <20210322013231.3216058-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616376777; bh=7c6H2P/FSKbJixHJuQQgzgUCHEMFzAZFGECSVcIADaQ=; h=Cc:Date:From:Reply-To:Subject:To; b=bj5XWw3Vj3xq97UsmAH2bGYi6XnizorarTtLncAaDGYb6/5NNDxHWJuQiwCkyfksnDD QbIHNQxwa5K0GdhM5lXd8it+L6G1f4NbWgWYlLffr/ilhx6P9VF90a67JHS5x4onc4vYZ lU2Nuhd53kacmOWawlH+NdwrTC2HTmqu7+4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" edk2-non-osi project is a more proper place for keeping the device tree sources, so move it there. It is a preparation for the DT upgrade for the Armada 7k8k SoC family. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf | 22 - Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf | 22 - Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf | 22 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi | 16 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 267 -------= --- Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 16 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 64 --- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi | 26 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 336 -------= ----- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 377 -------= ------ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 25 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 108 ---- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 31 -- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 43 -- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 264 -------= -- Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 10 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 560 -------= ------------- 17 files changed, 2209 deletions(-) delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.i= nf delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin= .dts delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual= .dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad= .dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf b/Silic= on/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf deleted file mode 100644 index b533578a89..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf +++ /dev/null @@ -1,22 +0,0 @@ -## @file -# -# Device tree description of the Marvell Armada 7040 DB platform -# -# Copyright (c) 2018, Marvell International Ltd. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x0001001A - BASE_NAME =3D Armada70x0DbDeviceTree - FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid - MODULE_TYPE =3D USER_DEFINED - VERSION_STRING =3D 1.0 - -[Sources] - armada-7040-db.dts - -[Packages] - MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf b/Silic= on/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf deleted file mode 100644 index 378fad240b..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf +++ /dev/null @@ -1,22 +0,0 @@ -## @file -# -# Device tree description of the Marvell Armada 8040 DB platform -# -# Copyright (c) 2018, Marvell International Ltd. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x0001001A - BASE_NAME =3D Armada80x0DbDeviceTree - FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid - MODULE_TYPE =3D USER_DEFINED - VERSION_STRING =3D 1.0 - -[Sources] - armada-8040-db.dts - -[Packages] - MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf b/Si= licon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf deleted file mode 100644 index 540e1a79f3..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf +++ /dev/null @@ -1,22 +0,0 @@ -## @file -# -# Device tree description of the Marvell Armada 8040 MacchiatoBin platform -# -# Copyright (c) 2018, Marvell International Ltd. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x0001001A - BASE_NAME =3D Armada80x0McBinDeviceTree - FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid - MODULE_TYPE =3D USER_DEFINED - VERSION_STRING =3D 1.0 - -[Sources] - armada-8040-mcbin.dts - -[Packages] - MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi deleted file mode 100644 index e2edc26271..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and - * one CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-70x0.dtsi" - -/ { - model =3D "Marvell Armada 7020"; - compatible =3D "marvell,armada7020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts deleted file mode 100644 index f5878efc06..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada 7040 Development board platform - */ - -#include "armada-7040.dtsi" - -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - -/ { - model =3D "Marvell Armada 7040 DB board"; - compatible =3D "marvell,armada7040-db", "marvell,armada7040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - memory@0 { - device_type =3D "memory"; - reg =3D <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 =3D &cp0_eth0; - ethernet1 =3D &cp0_eth1; - ethernet2 =3D &cp0_eth2; - }; - - cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { - compatible =3D "regulator-fixed"; - regulator-name =3D "usb3h0-vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - enable-active-high; - gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; - }; - - cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { - compatible =3D "regulator-fixed"; - regulator-name =3D "usb3h1-vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - enable-active-high; - gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; - }; - - cp0_usb3_0_phy: cp0-usb3-0-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp0_reg_usb3_0_vbus>; - }; - - cp0_usb3_1_phy: cp0-usb3-1-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp0_reg_usb3_1_vbus>; - }; -}; - -&i2c0 { - status =3D "okay"; - clock-frequency =3D <100000>; -}; - -&spi0 { - status =3D "okay"; - - spi-flash@0 { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "jedec,spi-nor"; - reg =3D <0>; - spi-max-frequency =3D <10000000>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0 0x200000>; - }; - partition@400000 { - label =3D "Filesystem"; - reg =3D <0x200000 0xce0000>; - }; - }; - }; -}; - -&uart0 { - status =3D "okay"; - pinctrl-0 =3D <&uart0_pins>; - pinctrl-names =3D "default"; -}; - - -&cp0_pcie2 { - status =3D "okay"; -}; - -&cp0_i2c0 { - status =3D "okay"; - clock-frequency =3D <100000>; - - expander0: pca9555@21 { - compatible =3D "nxp,pca9555"; - pinctrl-names =3D "default"; - gpio-controller; - #gpio-cells =3D <2>; - reg =3D <0x21>; - /* - * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect - * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit - * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN - * IO0_3: USB2_DEVICE_DETECT - * IO0_4: GPIO_0 IO1_4: SD_Status - * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable - * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC - * IO0_7: IO1_7: SDIO_Vcntrl - */ - }; -}; - -&cp0_nand_controller { - /* - * SPI on CPM and NAND have common pins on this board. We can - * use only one at a time. To enable the NAND (which will - * disable the SPI), the "status =3D "okay";" line have to be - * added here. - */ - pinctrl-0 =3D <&nand_pins>, <&nand_rb>; - pinctrl-names =3D "default"; - - nand@0 { - reg =3D <0>; - label =3D "pxa3xx_nand-0"; - nand-rb =3D <0>; - nand-on-flash-bbt; - nand-ecc-strength =3D <4>; - nand-ecc-step-size =3D <512>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0 0x200000>; - }; - - partition@200000 { - label =3D "Linux"; - reg =3D <0x200000 0xe00000>; - }; - - partition@1000000 { - label =3D "Filesystem"; - reg =3D <0x1000000 0x3f000000>; - }; - - }; - }; -}; - -&cp0_spi1 { - status =3D "disabled"; - - spi-flash@0 { - #address-cells =3D <0x1>; - #size-cells =3D <0x1>; - compatible =3D "jedec,spi-nor"; - reg =3D <0x0>; - spi-max-frequency =3D <20000000>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0x0 0x200000>; - }; - - partition@400000 { - label =3D "Filesystem"; - reg =3D <0x200000 0xe00000>; - }; - }; - }; -}; - -&cp0_sata0 { - status =3D "okay"; -}; - -&cp0_usb3_0 { - usb-phy =3D <&cp0_usb3_0_phy>; - status =3D "okay"; -}; - -&cp0_usb3_1 { - usb-phy =3D <&cp0_usb3_1_phy>; - status =3D "okay"; -}; - -&ap_sdhci0 { - status =3D "okay"; - bus-width =3D <4>; - no-1-8-v; - non-removable; -}; - -&cp0_sdhci0 { - status =3D "okay"; - bus-width =3D <4>; - no-1-8-v; - cd-gpios =3D <&expander0 12 GPIO_ACTIVE_LOW>; -}; - -&cp0_mdio { - status =3D "okay"; - - phy0: ethernet-phy@0 { - reg =3D <0>; - }; - phy1: ethernet-phy@1 { - reg =3D <1>; - }; -}; - -&cp0_ethernet { - status =3D "okay"; -}; - -&cp0_eth0 { - status =3D "okay"; - /* Network PHY */ - phy-mode =3D "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp0_comphy2 0>; - - fixed-link { - speed =3D <10000>; - full-duplex; - }; -}; - -&cp0_eth1 { - status =3D "okay"; - /* Network PHY */ - phy =3D <&phy0>; - phy-mode =3D "sgmii"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp0_comphy0 1>; -}; - -&cp0_eth2 { - status =3D "okay"; - phy =3D <&phy1>; - phy-mode =3D "rgmii-id"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi deleted file mode 100644 index 03109b2bb7..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and - * one CP110. - */ - -#include "armada-ap806-quad.dtsi" -#include "armada-70x0.dtsi" - -/ { - model =3D "Marvell Armada 7040"; - compatible =3D "marvell,armada7040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi deleted file mode 100644 index 78f9d874c6..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 70x0 SoC - */ - -/ { - aliases { - gpio1 =3D &cp0_gpio1; - gpio2 =3D &cp0_gpio2; - spi1 =3D &cp0_spi0; - spi2 =3D &cp0_spi1; - }; -}; - -/* - * Instantiate the CP110 - */ -#define CP110_NAME cp0 -#define CP110_BASE f2000000 -#define CP110_PCIE_IO_BASE 0xf9000000 -#define CP110_PCIE_MEM_BASE 0xf6000000 -#define CP110_PCIE0_BASE f2600000 -#define CP110_PCIE1_BASE f2620000 -#define CP110_PCIE2_BASE f2640000 - -#include "armada-cp110.dtsi" - -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE_IO_BASE -#undef CP110_PCIE_MEM_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE - -&cp0_gpio1 { - status =3D "okay"; -}; - -&cp0_gpio2 { - status =3D "okay"; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible =3D "marvell,armada-7k-pinctrl"; - - nand_pins: nand-pins { - marvell,pins =3D - "mpp15", "mpp16", "mpp17", "mpp18", - "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27"; - marvell,function =3D "dev"; - }; - - nand_rb: nand-rb { - marvell,pins =3D "mpp13"; - marvell,function =3D "nf"; - }; - }; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi deleted file mode 100644 index 5d763450c5..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and - * two CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-80x0.dtsi" - -/ { - model =3D "Marvell Armada 8020"; - compatible =3D "marvell,armada8020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; - -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock - * in CP master is not connected (by package) to the oscillator. So - * disable it. However, the RTC clock in CP slave is connected to the - * oscillator so this one is let enabled. - */ - -&cp0_rtc { - status =3D "disabled"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts deleted file mode 100644 index e81392241c..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts +++ /dev/null @@ -1,336 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada 8040 Development board platform - */ - -#include "armada-8040.dtsi" - -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - -/ { - model =3D "Marvell Armada 8040 DB board"; - compatible =3D "marvell,armada8040-db", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - memory@0 { - device_type =3D "memory"; - reg =3D <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 =3D &cp0_eth0; - ethernet1 =3D &cp0_eth2; - ethernet2 =3D &cp1_eth0; - ethernet3 =3D &cp1_eth1; - }; - - cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { - compatible =3D "regulator-fixed"; - regulator-name =3D "cp0-usb3h0-vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - enable-active-high; - gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; - }; - - cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { - compatible =3D "regulator-fixed"; - regulator-name =3D "cp0-usb3h1-vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - enable-active-high; - gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; - }; - - cp0_usb3_0_phy: cp0-usb3-0-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp0_reg_usb3_0_vbus>; - }; - - cp0_usb3_1_phy: cp0-usb3-1-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp0_reg_usb3_1_vbus>; - }; - - cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { - compatible =3D "regulator-fixed"; - regulator-name =3D "cp1-usb3h0-vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - enable-active-high; - gpio =3D <&expander1 0 GPIO_ACTIVE_HIGH>; - }; - - cp1_usb3_0_phy: cp1-usb3-0-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp1_reg_usb3_0_vbus>; - }; -}; - -&i2c0 { - status =3D "okay"; - clock-frequency =3D <100000>; -}; - -&spi0 { - status =3D "okay"; - - spi-flash@0 { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "jedec,spi-nor"; - reg =3D <0>; - spi-max-frequency =3D <10000000>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0 0x200000>; - }; - partition@400000 { - label =3D "Filesystem"; - reg =3D <0x200000 0xce0000>; - }; - }; - }; -}; - -/* Accessible over the mini-USB CON9 connector on the main board */ -&uart0 { - status =3D "okay"; - pinctrl-0 =3D <&uart0_pins>; - pinctrl-names =3D "default"; -}; - -/* CON6 on CP0 expansion */ -&cp0_pcie0 { - status =3D "okay"; -}; - -/* CON5 on CP0 expansion */ -&cp0_pcie2 { - status =3D "okay"; -}; - -&cp0_i2c0 { - status =3D "okay"; - clock-frequency =3D <100000>; - - /* U31 */ - expander0: pca9555@21 { - compatible =3D "nxp,pca9555"; - pinctrl-names =3D "default"; - gpio-controller; - #gpio-cells =3D <2>; - reg =3D <0x21>; - }; - - /* U25 */ - expander1: pca9555@25 { - compatible =3D "nxp,pca9555"; - pinctrl-names =3D "default"; - gpio-controller; - #gpio-cells =3D <2>; - reg =3D <0x25>; - }; - -}; - -/* CON4 on CP0 expansion */ -&cp0_sata0 { - status =3D "okay"; -}; - -/* CON9 on CP0 expansion */ -&cp0_usb3_0 { - usb-phy =3D <&cp0_usb3_0_phy>; - status =3D "okay"; -}; - -/* CON10 on CP0 expansion */ -&cp0_usb3_1 { - usb-phy =3D <&cp0_usb3_1_phy>; - status =3D "okay"; -}; - -&cp0_mdio { - status =3D "okay"; - - phy1: ethernet-phy@1 { - reg =3D <1>; - }; -}; - -&cp0_ethernet { - status =3D "okay"; -}; - -&cp0_eth0 { - status =3D "okay"; - phy-mode =3D "10gbase-kr"; - - fixed-link { - speed =3D <10000>; - full-duplex; - }; -}; - -&cp0_eth2 { - status =3D "okay"; - phy =3D <&phy1>; - phy-mode =3D "rgmii-id"; -}; - -/* CON6 on CP1 expansion */ -&cp1_pcie0 { - status =3D "okay"; -}; - -/* CON7 on CP1 expansion */ -&cp1_pcie1 { - status =3D "okay"; -}; - -/* CON5 on CP1 expansion */ -&cp1_pcie2 { - status =3D "okay"; -}; - -&cp1_i2c0 { - status =3D "okay"; - clock-frequency =3D <100000>; -}; - -&cp1_spi1 { - status =3D "disabled"; - - spi-flash@0 { - #address-cells =3D <0x1>; - #size-cells =3D <0x1>; - compatible =3D "jedec,spi-nor"; - reg =3D <0x0>; - spi-max-frequency =3D <20000000>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "Boot"; - reg =3D <0x0 0x200000>; - }; - partition@200000 { - label =3D "Filesystem"; - reg =3D <0x200000 0xd00000>; - }; - partition@f00000 { - label =3D "Boot_2nd"; - reg =3D <0xf00000 0x100000>; - }; - }; - }; -}; - -/* - * Proper NAND usage will require DPR-76 to be in position 1-2, which disa= bles - * MDIO signal of CP1. - */ -&cp1_nand_controller { - pinctrl-0 =3D <&nand_pins>, <&nand_rb>; - pinctrl-names =3D "default"; - - nand@0 { - reg =3D <0>; - nand-rb =3D <0>; - nand-on-flash-bbt; - nand-ecc-strength =3D <4>; - nand-ecc-step-size =3D <512>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0 0x200000>; - }; - partition@200000 { - label =3D "Linux"; - reg =3D <0x200000 0xe00000>; - }; - partition@1000000 { - label =3D "Filesystem"; - reg =3D <0x1000000 0x3f000000>; - }; - }; - }; -}; - -/* CON4 on CP1 expansion */ -&cp1_sata0 { - status =3D "okay"; -}; - -/* CON9 on CP1 expansion */ -&cp1_usb3_0 { - usb-phy =3D <&cp1_usb3_0_phy>; - status =3D "okay"; -}; - -/* CON10 on CP1 expansion */ -&cp1_usb3_1 { - status =3D "okay"; -}; - -&cp1_mdio { - status =3D "okay"; - - phy0: ethernet-phy@0 { - reg =3D <0>; - }; -}; - -&cp1_ethernet { - status =3D "okay"; -}; - -&cp1_eth0 { - status =3D "okay"; - phy-mode =3D "10gbase-kr"; - - fixed-link { - speed =3D <10000>; - full-duplex; - }; -}; - -&cp1_eth1 { - status =3D "okay"; - phy =3D <&phy0>; - phy-mode =3D "rgmii-id"; -}; - -&ap_sdhci0 { - status =3D "okay"; - bus-width =3D <4>; - non-removable; -}; - -&cp0_sdhci0 { - status =3D "okay"; - bus-width =3D <8>; - non-removable; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/= Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts deleted file mode 100644 index d9c9348b53..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts +++ /dev/null @@ -1,377 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for MACCHIATOBin Armada 8040 community board platform - */ - -#include "armada-8040.dtsi" - -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - -/ { - model =3D "Marvell 8040 MACCHIATOBin"; - compatible =3D "marvell,armada8040-mcbin", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806= "; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - memory@0 { - device_type =3D "memory"; - reg =3D <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 =3D &cp0_eth0; - ethernet1 =3D &cp1_eth0; - ethernet2 =3D &cp1_eth1; - ethernet3 =3D &cp1_eth2; - }; - - /* Regulator labels correspond with schematics */ - v_3_3: regulator-3-3v { - compatible =3D "regulator-fixed"; - regulator-name =3D "v_3_3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - status =3D "okay"; - }; - - v_vddo_h: regulator-1-8v { - compatible =3D "regulator-fixed"; - regulator-name =3D "v_vddo_h"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-always-on; - status =3D "okay"; - }; - - v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { - compatible =3D "regulator-fixed"; - enable-active-high; - gpio =3D <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_xhci_vbus_pins>; - regulator-name =3D "v_5v0_usb3_hst_vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - status =3D "okay"; - }; - - usb3h0_phy: usb3_phy0 { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&v_5v0_usb3_hst_vbus>; - }; - - sfp_eth0: sfp-eth0 { - /* CON15,16 - CPM lane 4 */ - compatible =3D "sff,sfp"; - i2c-bus =3D <&sfpp0_i2c>; - los-gpio =3D <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio =3D <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; - tx-disable-gpio =3D <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; - tx-fault-gpio =3D <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_sfpp0_pins>; - }; - - sfp_eth1: sfp-eth1 { - /* CON17,18 - CPS lane 4 */ - compatible =3D "sff,sfp"; - i2c-bus =3D <&sfpp1_i2c>; - los-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; - mod-def0-gpio =3D <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; - tx-disable-gpio =3D <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; - tx-fault-gpio =3D <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_sfpp1_pins &cp0_sfpp1_pins>; - }; - - sfp_eth3: sfp-eth3 { - /* CON3,4 - CPS lane 5 */ - compatible =3D "sff,sfp"; - i2c-bus =3D <&sfp_1g_i2c>; - los-gpio =3D <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio =3D <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; - tx-disable-gpio =3D <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; - tx-fault-gpio =3D <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; - }; -}; - -&uart0 { - status =3D "okay"; - pinctrl-0 =3D <&uart0_pins>; - pinctrl-names =3D "default"; -}; - -&ap_sdhci0 { - bus-width =3D <8>; - /* - * Not stable in HS modes - phy needs "more calibration", so add - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. - */ - marvell,xenon-phy-slow-mode; - no-1-8-v; - no-sd; - no-sdio; - non-removable; - status =3D "okay"; - vqmmc-supply =3D <&v_vddo_h>; -}; - -&cp0_i2c0 { - clock-frequency =3D <100000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_i2c0_pins>; - status =3D "okay"; -}; - -&cp0_i2c1 { - clock-frequency =3D <100000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_i2c1_pins>; - status =3D "okay"; - - i2c-switch@70 { - compatible =3D "nxp,pca9548"; - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0x70>; - - sfpp0_i2c: i2c@0 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0>; - }; - sfpp1_i2c: i2c@1 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <1>; - }; - sfp_1g_i2c: i2c@2 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <2>; - }; - }; -}; - -/* J25 UART header */ -&cp0_uart1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_uart1_pins>; - status =3D "okay"; -}; - -&cp0_mdio { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_ge_mdio_pins>; - status =3D "okay"; - - ge_phy: ethernet-phy@0 { - reg =3D <0>; - }; -}; - -&cp0_pcie0 { - compatible =3D "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam"; - reg =3D <0 0xe0000000 0 0xff00000>; - bus-range =3D <0 0xfe>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_pcie_pins>; - num-lanes =3D <4>; - num-viewport =3D <8>; - reset-gpio =3D <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; - ranges =3D <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000= >, - <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>, - <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>; - status =3D "okay"; -}; - -&cp0_pinctrl { - cp0_ge_mdio_pins: ge-mdio-pins { - marvell,pins =3D "mpp32", "mpp34"; - marvell,function =3D "ge"; - }; - cp0_i2c1_pins: i2c1-pins { - marvell,pins =3D "mpp35", "mpp36"; - marvell,function =3D "i2c1"; - }; - cp0_i2c0_pins: i2c0-pins { - marvell,pins =3D "mpp37", "mpp38"; - marvell,function =3D "i2c0"; - }; - cp0_uart1_pins: uart1-pins { - marvell,pins =3D "mpp40", "mpp41"; - marvell,function =3D "uart1"; - }; - cp0_xhci_vbus_pins: xhci0-vbus-pins { - marvell,pins =3D "mpp47"; - marvell,function =3D "gpio"; - }; - cp0_sfp_1g_pins: sfp-1g-pins { - marvell,pins =3D "mpp51", "mpp53", "mpp54"; - marvell,function =3D "gpio"; - }; - cp0_pcie_pins: pcie-pins { - marvell,pins =3D "mpp52"; - marvell,function =3D "gpio"; - }; - cp0_sdhci_pins: sdhci-pins { - marvell,pins =3D "mpp55", "mpp56", "mpp57", "mpp58", "mpp5= 9", - "mpp60", "mpp61"; - marvell,function =3D "sdio"; - }; - cp0_sfpp1_pins: sfpp1-pins { - marvell,pins =3D "mpp62"; - marvell,function =3D "gpio"; - }; -}; - -&cp0_xmdio { - status =3D "okay"; - - phy0: ethernet-phy@0 { - compatible =3D "ethernet-phy-ieee802.3-c45"; - reg =3D <0>; - sfp =3D <&sfp_eth0>; - }; - - phy8: ethernet-phy@8 { - compatible =3D "ethernet-phy-ieee802.3-c45"; - reg =3D <8>; - sfp =3D <&sfp_eth1>; - }; -}; - -&cp0_ethernet { - status =3D "okay"; -}; - -&cp0_eth0 { - status =3D "okay"; - /* Network PHY */ - phy =3D <&phy0>; - phy-mode =3D "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp0_comphy4 0>; -}; - -&cp0_sata0 { - /* CPM Lane 0 - U29 */ - status =3D "okay"; -}; - -&cp0_sdhci0 { - /* U6 */ - broken-cd; - bus-width =3D <4>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_sdhci_pins>; - status =3D "okay"; - vqmmc-supply =3D <&v_3_3>; -}; - -&cp0_usb3_0 { - /* J38? - USB2.0 only */ - status =3D "okay"; -}; - -&cp0_usb3_1 { - /* J38? - USB2.0 only */ - status =3D "okay"; -}; - -&cp1_ethernet { - status =3D "okay"; -}; - -&cp1_eth0 { - status =3D "okay"; - /* Network PHY */ - phy =3D <&phy8>; - phy-mode =3D "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy4 0>; -}; - -&cp1_eth1 { - /* CPS Lane 0 - J5 (Gigabit RJ45) */ - status =3D "okay"; - /* Network PHY */ - phy =3D <&ge_phy>; - phy-mode =3D "sgmii"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy0 1>; -}; - -&cp1_eth2 { - /* CPS Lane 5 */ - status =3D "okay"; - /* Network PHY */ - phy-mode =3D "2500base-x"; - managed =3D "in-band-status"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy5 2>; - sfp =3D <&sfp_eth3>; -}; - -&cp1_pinctrl { - cp1_sfpp1_pins: sfpp1-pins { - marvell,pins =3D "mpp8", "mpp10", "mpp11"; - marvell,function =3D "gpio"; - }; - cp1_spi1_pins: spi1-pins { - marvell,pins =3D "mpp12", "mpp13", "mpp14", "mpp15", "mpp1= 6"; - marvell,function =3D "spi1"; - }; - cp1_uart0_pins: uart0-pins { - marvell,pins =3D "mpp6", "mpp7"; - marvell,function =3D "uart0"; - }; - cp1_sfp_1g_pins: sfp-1g-pins { - marvell,pins =3D "mpp24"; - marvell,function =3D "gpio"; - }; - cp1_sfpp0_pins: sfpp0-pins { - marvell,pins =3D "mpp26", "mpp27", "mpp28", "mpp29"; - marvell,function =3D "gpio"; - }; -}; - -/* J27 UART header */ -&cp1_uart0 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_uart0_pins>; - status =3D "okay"; -}; - -&cp1_sata0 { - /* CPS Lane 1 - U32 */ - /* CPS Lane 3 - U31 */ - status =3D "okay"; -}; - -&cp1_spi1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_spi1_pins>; - status =3D "disabled"; - - spi-flash@0 { - compatible =3D "st,w25q32"; - spi-max-frequency =3D <50000000>; - reg =3D <0>; - }; -}; - -&cp1_usb3_0 { - /* CPS Lane 2 - CON7 */ - usb-phy =3D <&usb3h0_phy>; - status =3D "okay"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi deleted file mode 100644 index 784ef3f311..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and - * two CP110. - */ - -#include "armada-ap806-quad.dtsi" -#include "armada-80x0.dtsi" - -/ { - model =3D "Marvell Armada 8040"; - compatible =3D "marvell,armada8040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; - -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock - * in CP master is not connected (by package) to the oscillator. So - * disable it. However, the RTC clock in CP slave is connected to the - * oscillator so this one is let enabled. - */ -&cp0_rtc { - status =3D "disabled"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi deleted file mode 100644 index 81967e20d3..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 80x0 SoC family - */ - -/ { - aliases { - gpio1 =3D &cp1_gpio1; - gpio2 =3D &cp0_gpio2; - spi1 =3D &cp0_spi0; - spi2 =3D &cp0_spi1; - spi3 =3D &cp1_spi0; - spi4 =3D &cp1_spi1; - }; -}; - -/* - * Instantiate the master CP110 - */ -#define CP110_NAME cp0 -#define CP110_BASE f2000000 -#define CP110_PCIE_IO_BASE 0xf9000000 -#define CP110_PCIE_MEM_BASE 0xf6000000 -#define CP110_PCIE0_BASE f2600000 -#define CP110_PCIE1_BASE f2620000 -#define CP110_PCIE2_BASE f2640000 - -#include "armada-cp110.dtsi" - -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE_IO_BASE -#undef CP110_PCIE_MEM_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE - -/* - * Instantiate the slave CP110 - */ -#define CP110_NAME cp1 -#define CP110_BASE f4000000 -#define CP110_PCIE_IO_BASE 0xfd000000 -#define CP110_PCIE_MEM_BASE 0xfa000000 -#define CP110_PCIE0_BASE f4600000 -#define CP110_PCIE1_BASE f4620000 -#define CP110_PCIE2_BASE f4640000 - -#include "armada-cp110.dtsi" - -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE_IO_BASE -#undef CP110_PCIE_MEM_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE - -/* The 80x0 has two CP blocks, but uses only one block from each. */ -&cp1_gpio1 { - status =3D "okay"; -}; - -&cp0_gpio2 { - status =3D "okay"; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible =3D "marvell,armada-8k-cpm-pinctrl"; - }; -}; - -&cp1_syscon0 { - cp1_pinctrl: pinctrl { - compatible =3D "marvell,armada-8k-cps-pinctrl"; - - nand_pins: nand-pins { - marvell,pins =3D - "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11", - "mpp15", "mpp16", "mpp17", "mpp18", - "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27"; - marvell,function =3D "dev"; - }; - - nand_rb: nand-rb { - marvell,pins =3D "mpp13", "mpp12"; - marvell,function =3D "nf"; - }; - }; -}; - -&cp1_crypto { - /* - * The cryptographic engine found on the cp110 - * master is enabled by default at the SoC - * level. Because it is not possible as of now - * to enable two cryptographic engines in - * parallel, disable this one by default. - */ - status =3D "disabled"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi deleted file mode 100644 index 5985843fcc..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#include "armada-ap806.dtsi" - -/ { - model =3D "Marvell Armada AP806 Dual"; - compatible =3D "marvell,armada-ap806-dual", "marvell,armada-ap806"; - - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - - cpu@0 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x000>; - enable-method =3D "psci"; - }; - cpu@1 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x001>; - enable-method =3D "psci"; - }; - }; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi deleted file mode 100644 index bae0ed9ca7..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#include "armada-ap806.dtsi" - -/ { - model =3D "Marvell Armada AP806 Quad"; - compatible =3D "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - - cpu@0 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x000>; - enable-method =3D "psci"; - }; - cpu@1 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x001>; - enable-method =3D "psci"; - }; - cpu@100 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x100>; - enable-method =3D "psci"; - }; - cpu@101 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x101>; - enable-method =3D "psci"; - }; - }; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi deleted file mode 100644 index 66124bf483..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#define IRQ_TYPE_LEVEL_HIGH (1 << 2) -#define IRQ_TYPE_LEVEL_LOW (1 << 3) - -#define GIC_SPI 0 -#define GIC_PPI 1 - -#define GIC_CPU_MASK_RAW(x) ((x) << 8) -#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) - -/dts-v1/; - -/ { - model =3D "Marvell Armada AP806"; - compatible =3D "marvell,armada-ap806"; - #address-cells =3D <2>; - #size-cells =3D <2>; - - aliases { - serial0 =3D &uart0; - serial1 =3D &uart1; - gpio0 =3D &ap_gpio; - spi0 =3D &spi0; - }; - - psci { - compatible =3D "arm,psci-0.2"; - method =3D "smc"; - }; - - ap806 { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "simple-bus"; - interrupt-parent =3D <&gic>; - ranges; - - config-space@f0000000 { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "simple-bus"; - ranges =3D <0x0 0x0 0xf0000000 0x1000000>; - - gic: interrupt-controller@210000 { - compatible =3D "arm,gic-400"; - #interrupt-cells =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - interrupt-controller; - interrupts =3D ; - reg =3D <0x210000 0x10000>, - <0x220000 0x20000>, - <0x240000 0x20000>, - <0x260000 0x20000>; - - gic_v2m0: v2m@280000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x280000 0x1000>; - arm,msi-base-spi =3D <160>; - arm,msi-num-spis =3D <32>; - }; - gic_v2m1: v2m@290000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x290000 0x1000>; - arm,msi-base-spi =3D <192>; - arm,msi-num-spis =3D <32>; - }; - gic_v2m2: v2m@2a0000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x2a0000 0x1000>; - arm,msi-base-spi =3D <224>; - arm,msi-num-spis =3D <32>; - }; - gic_v2m3: v2m@2b0000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x2b0000 0x1000>; - arm,msi-base-spi =3D <256>; - arm,msi-num-spis =3D <32>; - }; - }; - - timer { - compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; - }; - - pmu { - compatible =3D "arm,cortex-a72-pmu"; - interrupt-parent =3D <&pic>; - interrupts =3D <17>; - }; - - odmi: odmi@300000 { - compatible =3D "marvell,odmi-controller"; - interrupt-controller; - msi-controller; - marvell,odmi-frames =3D <4>; - reg =3D <0x300000 0x4000>, - <0x304000 0x4000>, - <0x308000 0x4000>, - <0x30C000 0x4000>; - marvell,spi-base =3D <128>, <136>, <144>, = <152>; - }; - - gicp: gicp@3f0040 { - compatible =3D "marvell,ap806-gicp"; - reg =3D <0x3f0040 0x10>; - marvell,spi-ranges =3D <64 64>, <288 64>; - msi-controller; - }; - - pic: interrupt-controller@3f0100 { - compatible =3D "marvell,armada-8k-pic"; - reg =3D <0x3f0100 0x10>; - #interrupt-cells =3D <1>; - interrupt-controller; - interrupts =3D ; - }; - - xor@400000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x400000 0x1000>, - <0x410000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - xor@420000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x420000 0x1000>, - <0x430000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - xor@440000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x440000 0x1000>, - <0x450000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - xor@460000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x460000 0x1000>, - <0x470000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - spi0: spi@510600 { - compatible =3D "marvell,armada-380-spi"; - reg =3D <0x510600 0x50>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - }; - - i2c0: i2c@511000 { - compatible =3D "marvell,mv78230-i2c"; - reg =3D <0x511000 0x20>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - timeout-ms =3D <1000>; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - }; - - uart0: serial@512000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x512000 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - }; - - uart1: serial@512100 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x512100 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - - }; - - watchdog: watchdog@610000 { - compatible =3D "arm,sbsa-gwdt"; - reg =3D <0x610000 0x1000>, <0x600000 0x100= 0>; - interrupts =3D ; - }; - - ap_sdhci0: sdhci@6e0000 { - compatible =3D "marvell,armada-ap806-sdhci= "; - reg =3D <0x6e0000 0x300>; - interrupts =3D ; - clock-names =3D "core"; - clocks =3D <&ap_clk 4>; - dma-coherent; - marvell,xenon-phy-slow-mode; - status =3D "disabled"; - }; - - ap_syscon: system-controller@6f4000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x6f4000 0x2000>; - - ap_clk: clock { - compatible =3D "marvell,ap806-cloc= k"; - #clock-cells =3D <1>; - }; - - ap_pinctrl: pinctrl { - compatible =3D "marvell,ap806-pinc= trl"; - - uart0_pins: uart0-pins { - marvell,pins =3D "mpp11", = "mpp19"; - marvell,function =3D "uart= 0"; - }; - }; - - ap_gpio: gpio@1040 { - compatible =3D "marvell,armada-8k-= gpio"; - offset =3D <0x1040>; - ngpios =3D <20>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>; - }; - }; - - ap_thermal: thermal@6f808c { - compatible =3D "marvell,armada-ap806-therm= al"; - reg =3D <0x6f808c 0x4>, - <0x6f8084 0x8>; - }; - }; - }; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi deleted file mode 100644 index 8b610fd2b3..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - */ - -/* Common definitions used by Armada 7K/8K DTs */ -#define PASTER(x, y) x ## y -#define EVALUATOR(x, y) PASTER(x, y) -#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name)) -#define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi deleted file mode 100644 index 5e8e524cf7..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi +++ /dev/null @@ -1,560 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada CP110. - */ - -#include "armada-common.dtsi" - -#define ICU_GRP_NSR 0x0 -#define ICU_GRP_SR 0x1 -#define ICU_GRP_SEI 0x4 -#define ICU_GRP_REI 0x5 - -#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * = 0x10000)) -#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface *= 0x1000000)) -#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) += 0xf00000) - -/ { - /* - * The contents of the node are defined below, in order to - * save one indentation level - */ - CP110_NAME: CP110_NAME { }; -}; - -&CP110_NAME { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "simple-bus"; - interrupt-parent =3D <&CP110_LABEL(icu)>; - ranges; - - config-space@CP110_BASE { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "simple-bus"; - ranges =3D <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; - - CP110_LABEL(ethernet): ethernet@0 { - compatible =3D "marvell,armada-7k-pp22"; - reg =3D <0x0 0x100000>, <0x129000 0xb000>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(c= ore_clk)>, - <&CP110_LABEL(core_clk)>; - clock-names =3D "pp_clk", "gop_clk", - "mg_clk", "mg_core_clk", "axi_clk"; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - status =3D "disabled"; - dma-coherent; - - CP110_LABEL(eth0): eth0 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <0>; - gop-port-id =3D <0>; - status =3D "disabled"; - }; - - CP110_LABEL(eth1): eth1 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <1>; - gop-port-id =3D <2>; - status =3D "disabled"; - }; - - CP110_LABEL(eth2): eth2 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <2>; - gop-port-id =3D <3>; - status =3D "disabled"; - }; - }; - - CP110_LABEL(comphy): phy@120000 { - compatible =3D "marvell,comphy-cp110"; - reg =3D <0x120000 0x6000>; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - CP110_LABEL(comphy0): phy@0 { - reg =3D <0>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy1): phy@1 { - reg =3D <1>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy2): phy@2 { - reg =3D <2>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy3): phy@3 { - reg =3D <3>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy4): phy@4 { - reg =3D <4>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy5): phy@5 { - reg =3D <5>; - #phy-cells =3D <1>; - }; - }; - - CP110_LABEL(mdio): mdio@12a200 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "marvell,orion-mdio"; - reg =3D <0x12a200 0x10>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(core_clk)>, <&CP110_LABEL(c= ore_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(xmdio): mdio@12a600 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "marvell,xmdio"; - reg =3D <0x12a600 0x10>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(icu): interrupt-controller@1e0000 { - compatible =3D "marvell,cp110-icu"; - reg =3D <0x1e0000 0x440>; - #interrupt-cells =3D <3>; - interrupt-controller; - msi-parent =3D <&gicp>; - }; - - CP110_LABEL(rtc): rtc@284000 { - compatible =3D "marvell,armada-8k-rtc"; - reg =3D <0x284000 0x20>, <0x284080 0x24>; - reg-names =3D "rtc", "rtc-soc"; - interrupts =3D ; - status =3D "disabled"; - }; - - CP110_LABEL(thermal): thermal@400078 { - compatible =3D "marvell,armada-cp110-thermal"; - reg =3D <0x400078 0x4>, - <0x400070 0x8>; - }; - - CP110_LABEL(syscon0): system-controller@440000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x440000 0x2000>; - - CP110_LABEL(clk): clock { - compatible =3D "marvell,cp110-clock"; - status =3D "disabled"; - #clock-cells =3D <2>; - }; - - CP110_LABEL(gpio1): gpio@100 { - compatible =3D "marvell,armada-8k-gpio"; - offset =3D <0x100>; - ngpios =3D <32>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 0= 32>; - interrupt-controller; - interrupts =3D , - , - , - ; - status =3D "disabled"; - }; - - CP110_LABEL(gpio2): gpio@140 { - compatible =3D "marvell,armada-8k-gpio"; - offset =3D <0x140>; - ngpios =3D <31>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 3= 2 31>; - interrupt-controller; - interrupts =3D , - , - , - ; - status =3D "disabled"; - }; - }; - - CP110_LABEL(usb3_0): usb3@500000 { - compatible =3D "marvell,armada-8k-xhci", - "generic-xhci"; - reg =3D <0x500000 0x4000>; - dma-coherent; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(usb3_1): usb3@510000 { - compatible =3D "marvell,armada-8k-xhci", - "generic-xhci"; - reg =3D <0x510000 0x4000>; - dma-coherent; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(sata0): sata@540000 { - compatible =3D "marvell,armada-8k-ahci", - "generic-ahci"; - reg =3D <0x540000 0x30000>; - dma-coherent; - interrupts =3D ; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(xor0): xor@6a0000 { - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; - reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(x2core_clk)>; - }; - - CP110_LABEL(xor1): xor@6c0000 { - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; - reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(x2core_clk)>; - }; - - CP110_LABEL(spi0): spi@700600 { - compatible =3D "marvell,armada-380-spi"; - reg =3D <0x700600 0x50>; - #address-cells =3D <0x1>; - #size-cells =3D <0x0>; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(spi1): spi@700680 { - compatible =3D "marvell,armada-380-spi"; - reg =3D <0x700680 0x50>; - #address-cells =3D <1>; - #size-cells =3D <0>; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(i2c0): i2c@701000 { - compatible =3D "marvell,mv78230-i2c"; - reg =3D <0x701000 0x20>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(i2c1): i2c@701100 { - compatible =3D "marvell,mv78230-i2c"; - reg =3D <0x701100 0x20>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart0): serial@702000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702000 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart1): serial@702100 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702100 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart2): serial@702200 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702200 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart3): serial@702300 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702300 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(nand_controller): nand@720000 { - /* - * Due to the limitation of the pins available - * this controller is only usable on the CPM - * for A7K and on the CPS for A8K. - */ - compatible =3D "marvell,armada-8k-nand-controller", - "marvell,armada370-nand-controller"; - reg =3D <0x720000 0x54>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(nand_clk)>, - <&CP110_LABEL(x2core_clk)>; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - status =3D "disabled"; - }; - - CP110_LABEL(trng): trng@760000 { - compatible =3D "marvell,armada-8k-rng", - "inside-secure,safexcel-eip76"; - reg =3D <0x760000 0x7d>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(x2core_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "okay"; - }; - - CP110_LABEL(sdhci0): sdhci@780000 { - compatible =3D "marvell,armada-cp110-sdhci"; - reg =3D <0x780000 0x300>; - interrupts =3D ; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL= (core_clk)>; - dma-coherent; - status =3D "disabled"; - }; - - CP110_LABEL(crypto): crypto@800000 { - compatible =3D "inside-secure,safexcel-eip197"; - reg =3D <0x800000 0x200000>; - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(x2core_clk)>, - <&CP110_LABEL(x2core_clk)>; - dma-coherent; - }; - }; - - CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* downstream I/O */ - <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BAS= E(0) 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BA= SE(0) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 2 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* downstream I/O */ - <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BAS= E(1) 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BA= SE(1) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 4 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* downstream I/O */ - <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BAS= E(2) 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BA= SE(2) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 3 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - /* 1 GHz fixed main PLL */ - CP110_LABEL(mainpll): CP110_LABEL(mainpll) { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <1000000000>; - }; - - CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <2>; - }; - - CP110_LABEL(core_clk): CP110_LABEL(core_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <2>; - }; - - CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <2>; - clock-div =3D <5>; - }; - - CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <2>; - clock-div =3D <5>; - }; - - CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <3>; - }; - - CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <4>; - }; -}; --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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