From nobody Sun Apr 28 21:13:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73022+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73022+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616097508; cv=none; d=zohomail.com; s=zohoarc; b=edbuYItmrvB+l4z90x3LsYIexW+CPU9Zhyp1dNllSlkiFt7t6ZlhzZMZoJvOXTiuOgGXr7/JNElhTOMja2DvYIhFghVbwbExLengDCXdPwyw24gBqthryX27M4SU7H16TzRyPMtjed51Z4rBYcEWtYHltgB3M7twstebNbAd3RE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616097508; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=9k0kqG+sUj9Fo4UMa3nFbNdDSIRD9s/w1Kt0DqoOvO4=; b=fTnRdC/oNkOJcQmp7WJo8Hm36WCsAyS4AhwcMINFtnVaKQCgcchjj1oiPN2uw3GHMFkY44mtcfEoVeF/F48YtilXd7BTHr8y40TfKzO8ULEV08OO1U1nn47VxJFoWF4stirNd/M+qwLvJflXjDTA08aRHrlBmlFwrPbtlurf/ug= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73022+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616097508813597.9627407671187; Thu, 18 Mar 2021 12:58:28 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id rMaYYY1788612xKeMHSiu6da; Thu, 18 Mar 2021 12:58:27 -0700 X-Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) by mx.groups.io with SMTP id smtpd.web11.218.1616097506162117319 for ; Thu, 18 Mar 2021 12:58:26 -0700 X-Received: by mail-lj1-f180.google.com with SMTP id a1so9084174ljp.2 for ; Thu, 18 Mar 2021 12:58:25 -0700 (PDT) X-Gm-Message-State: VsIposWPWoq01z3ZEGcGdoO2x1787277AA= X-Google-Smtp-Source: ABdhPJwAL7kW81PHnyPEAKy+xS/CPyfMjuxvoIP08JkyF5c9FUZ45ownunSWzPyjfFDmZLmHhyRGTw== X-Received: by 2002:a2e:94c8:: with SMTP id r8mr6401505ljh.332.1616097503973; Thu, 18 Mar 2021 12:58:23 -0700 (PDT) X-Received: from gilgamesh.int.semihalf.com (host-193.106.246.138.static.3s.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id b30sm344622lfj.101.2021.03.18.12.58.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 12:58:23 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ard.biesheuvel@arm.com, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com, jon@solid-run.com Subject: [edk2-devel] [edk2-platforms PATCH 1/4] Marvell/Armada7k8k: Remove device tree sources from edk2-platforms Date: Thu, 18 Mar 2021 20:57:55 +0100 Message-Id: <20210318195757.2974226-3-mw@semihalf.com> In-Reply-To: <20210318195757.2974226-1-mw@semihalf.com> References: <20210318195757.2974226-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616097507; bh=MvjFbxmq/8u15nstQFU+F0iE6ax+WXCerXkzBT2Efms=; h=Cc:Date:From:Reply-To:Subject:To; b=Uf0SWnA7S4yJ9TvGr1JJ/Z4Z7yphSlmcXWebYa2dCFtALUPMy18LPcs1KXsmm8q2Noa yr2oGFjBpBGCZzRsVPmPAi4b5B3pbaO8v8Wp177SRs13rm4bYdQ82I371Dqv3ZlgCnke4 d3PMe/3TR3iakjww+zA0jZR5zl2YhI1Muko= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" edk2-non-osi project is a more proper place for keeping the device tree sources, so move it there. It is a preparation for the DT upgrade for the Armada 7k8k SoC family. Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf | 22 - Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf | 22 - Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf | 22 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi | 16 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 267 -------= --- Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 16 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 64 --- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi | 26 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 336 -------= ----- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 377 -------= ------ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 25 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 108 ---- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 31 -- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 43 -- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 264 -------= -- Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 10 - Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 560 -------= ------------- 17 files changed, 2209 deletions(-) delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.i= nf delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin= .dts delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual= .dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad= .dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf b/Silic= on/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf deleted file mode 100644 index b533578a89..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf +++ /dev/null @@ -1,22 +0,0 @@ -## @file -# -# Device tree description of the Marvell Armada 7040 DB platform -# -# Copyright (c) 2018, Marvell International Ltd. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x0001001A - BASE_NAME =3D Armada70x0DbDeviceTree - FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid - MODULE_TYPE =3D USER_DEFINED - VERSION_STRING =3D 1.0 - -[Sources] - armada-7040-db.dts - -[Packages] - MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf b/Silic= on/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf deleted file mode 100644 index 378fad240b..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf +++ /dev/null @@ -1,22 +0,0 @@ -## @file -# -# Device tree description of the Marvell Armada 8040 DB platform -# -# Copyright (c) 2018, Marvell International Ltd. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x0001001A - BASE_NAME =3D Armada80x0DbDeviceTree - FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid - MODULE_TYPE =3D USER_DEFINED - VERSION_STRING =3D 1.0 - -[Sources] - armada-8040-db.dts - -[Packages] - MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf b/Si= licon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf deleted file mode 100644 index 540e1a79f3..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf +++ /dev/null @@ -1,22 +0,0 @@ -## @file -# -# Device tree description of the Marvell Armada 8040 MacchiatoBin platform -# -# Copyright (c) 2018, Marvell International Ltd. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x0001001A - BASE_NAME =3D Armada80x0McBinDeviceTree - FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid - MODULE_TYPE =3D USER_DEFINED - VERSION_STRING =3D 1.0 - -[Sources] - armada-8040-mcbin.dts - -[Packages] - MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi deleted file mode 100644 index e2edc26271..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and - * one CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-70x0.dtsi" - -/ { - model =3D "Marvell Armada 7020"; - compatible =3D "marvell,armada7020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts deleted file mode 100644 index f5878efc06..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada 7040 Development board platform - */ - -#include "armada-7040.dtsi" - -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - -/ { - model =3D "Marvell Armada 7040 DB board"; - compatible =3D "marvell,armada7040-db", "marvell,armada7040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - memory@0 { - device_type =3D "memory"; - reg =3D <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 =3D &cp0_eth0; - ethernet1 =3D &cp0_eth1; - ethernet2 =3D &cp0_eth2; - }; - - cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { - compatible =3D "regulator-fixed"; - regulator-name =3D "usb3h0-vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - enable-active-high; - gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; - }; - - cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { - compatible =3D "regulator-fixed"; - regulator-name =3D "usb3h1-vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - enable-active-high; - gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; - }; - - cp0_usb3_0_phy: cp0-usb3-0-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp0_reg_usb3_0_vbus>; - }; - - cp0_usb3_1_phy: cp0-usb3-1-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp0_reg_usb3_1_vbus>; - }; -}; - -&i2c0 { - status =3D "okay"; - clock-frequency =3D <100000>; -}; - -&spi0 { - status =3D "okay"; - - spi-flash@0 { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "jedec,spi-nor"; - reg =3D <0>; - spi-max-frequency =3D <10000000>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0 0x200000>; - }; - partition@400000 { - label =3D "Filesystem"; - reg =3D <0x200000 0xce0000>; - }; - }; - }; -}; - -&uart0 { - status =3D "okay"; - pinctrl-0 =3D <&uart0_pins>; - pinctrl-names =3D "default"; -}; - - -&cp0_pcie2 { - status =3D "okay"; -}; - -&cp0_i2c0 { - status =3D "okay"; - clock-frequency =3D <100000>; - - expander0: pca9555@21 { - compatible =3D "nxp,pca9555"; - pinctrl-names =3D "default"; - gpio-controller; - #gpio-cells =3D <2>; - reg =3D <0x21>; - /* - * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect - * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit - * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN - * IO0_3: USB2_DEVICE_DETECT - * IO0_4: GPIO_0 IO1_4: SD_Status - * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable - * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC - * IO0_7: IO1_7: SDIO_Vcntrl - */ - }; -}; - -&cp0_nand_controller { - /* - * SPI on CPM and NAND have common pins on this board. We can - * use only one at a time. To enable the NAND (which will - * disable the SPI), the "status =3D "okay";" line have to be - * added here. - */ - pinctrl-0 =3D <&nand_pins>, <&nand_rb>; - pinctrl-names =3D "default"; - - nand@0 { - reg =3D <0>; - label =3D "pxa3xx_nand-0"; - nand-rb =3D <0>; - nand-on-flash-bbt; - nand-ecc-strength =3D <4>; - nand-ecc-step-size =3D <512>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0 0x200000>; - }; - - partition@200000 { - label =3D "Linux"; - reg =3D <0x200000 0xe00000>; - }; - - partition@1000000 { - label =3D "Filesystem"; - reg =3D <0x1000000 0x3f000000>; - }; - - }; - }; -}; - -&cp0_spi1 { - status =3D "disabled"; - - spi-flash@0 { - #address-cells =3D <0x1>; - #size-cells =3D <0x1>; - compatible =3D "jedec,spi-nor"; - reg =3D <0x0>; - spi-max-frequency =3D <20000000>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0x0 0x200000>; - }; - - partition@400000 { - label =3D "Filesystem"; - reg =3D <0x200000 0xe00000>; - }; - }; - }; -}; - -&cp0_sata0 { - status =3D "okay"; -}; - -&cp0_usb3_0 { - usb-phy =3D <&cp0_usb3_0_phy>; - status =3D "okay"; -}; - -&cp0_usb3_1 { - usb-phy =3D <&cp0_usb3_1_phy>; - status =3D "okay"; -}; - -&ap_sdhci0 { - status =3D "okay"; - bus-width =3D <4>; - no-1-8-v; - non-removable; -}; - -&cp0_sdhci0 { - status =3D "okay"; - bus-width =3D <4>; - no-1-8-v; - cd-gpios =3D <&expander0 12 GPIO_ACTIVE_LOW>; -}; - -&cp0_mdio { - status =3D "okay"; - - phy0: ethernet-phy@0 { - reg =3D <0>; - }; - phy1: ethernet-phy@1 { - reg =3D <1>; - }; -}; - -&cp0_ethernet { - status =3D "okay"; -}; - -&cp0_eth0 { - status =3D "okay"; - /* Network PHY */ - phy-mode =3D "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp0_comphy2 0>; - - fixed-link { - speed =3D <10000>; - full-duplex; - }; -}; - -&cp0_eth1 { - status =3D "okay"; - /* Network PHY */ - phy =3D <&phy0>; - phy-mode =3D "sgmii"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp0_comphy0 1>; -}; - -&cp0_eth2 { - status =3D "okay"; - phy =3D <&phy1>; - phy-mode =3D "rgmii-id"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi deleted file mode 100644 index 03109b2bb7..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and - * one CP110. - */ - -#include "armada-ap806-quad.dtsi" -#include "armada-70x0.dtsi" - -/ { - model =3D "Marvell Armada 7040"; - compatible =3D "marvell,armada7040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi deleted file mode 100644 index 78f9d874c6..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 70x0 SoC - */ - -/ { - aliases { - gpio1 =3D &cp0_gpio1; - gpio2 =3D &cp0_gpio2; - spi1 =3D &cp0_spi0; - spi2 =3D &cp0_spi1; - }; -}; - -/* - * Instantiate the CP110 - */ -#define CP110_NAME cp0 -#define CP110_BASE f2000000 -#define CP110_PCIE_IO_BASE 0xf9000000 -#define CP110_PCIE_MEM_BASE 0xf6000000 -#define CP110_PCIE0_BASE f2600000 -#define CP110_PCIE1_BASE f2620000 -#define CP110_PCIE2_BASE f2640000 - -#include "armada-cp110.dtsi" - -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE_IO_BASE -#undef CP110_PCIE_MEM_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE - -&cp0_gpio1 { - status =3D "okay"; -}; - -&cp0_gpio2 { - status =3D "okay"; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible =3D "marvell,armada-7k-pinctrl"; - - nand_pins: nand-pins { - marvell,pins =3D - "mpp15", "mpp16", "mpp17", "mpp18", - "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27"; - marvell,function =3D "dev"; - }; - - nand_rb: nand-rb { - marvell,pins =3D "mpp13"; - marvell,function =3D "nf"; - }; - }; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi deleted file mode 100644 index 5d763450c5..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and - * two CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-80x0.dtsi" - -/ { - model =3D "Marvell Armada 8020"; - compatible =3D "marvell,armada8020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; - -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock - * in CP master is not connected (by package) to the oscillator. So - * disable it. However, the RTC clock in CP slave is connected to the - * oscillator so this one is let enabled. - */ - -&cp0_rtc { - status =3D "disabled"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts deleted file mode 100644 index e81392241c..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts +++ /dev/null @@ -1,336 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada 8040 Development board platform - */ - -#include "armada-8040.dtsi" - -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - -/ { - model =3D "Marvell Armada 8040 DB board"; - compatible =3D "marvell,armada8040-db", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - memory@0 { - device_type =3D "memory"; - reg =3D <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 =3D &cp0_eth0; - ethernet1 =3D &cp0_eth2; - ethernet2 =3D &cp1_eth0; - ethernet3 =3D &cp1_eth1; - }; - - cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { - compatible =3D "regulator-fixed"; - regulator-name =3D "cp0-usb3h0-vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - enable-active-high; - gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; - }; - - cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { - compatible =3D "regulator-fixed"; - regulator-name =3D "cp0-usb3h1-vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - enable-active-high; - gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; - }; - - cp0_usb3_0_phy: cp0-usb3-0-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp0_reg_usb3_0_vbus>; - }; - - cp0_usb3_1_phy: cp0-usb3-1-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp0_reg_usb3_1_vbus>; - }; - - cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { - compatible =3D "regulator-fixed"; - regulator-name =3D "cp1-usb3h0-vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - enable-active-high; - gpio =3D <&expander1 0 GPIO_ACTIVE_HIGH>; - }; - - cp1_usb3_0_phy: cp1-usb3-0-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp1_reg_usb3_0_vbus>; - }; -}; - -&i2c0 { - status =3D "okay"; - clock-frequency =3D <100000>; -}; - -&spi0 { - status =3D "okay"; - - spi-flash@0 { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "jedec,spi-nor"; - reg =3D <0>; - spi-max-frequency =3D <10000000>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0 0x200000>; - }; - partition@400000 { - label =3D "Filesystem"; - reg =3D <0x200000 0xce0000>; - }; - }; - }; -}; - -/* Accessible over the mini-USB CON9 connector on the main board */ -&uart0 { - status =3D "okay"; - pinctrl-0 =3D <&uart0_pins>; - pinctrl-names =3D "default"; -}; - -/* CON6 on CP0 expansion */ -&cp0_pcie0 { - status =3D "okay"; -}; - -/* CON5 on CP0 expansion */ -&cp0_pcie2 { - status =3D "okay"; -}; - -&cp0_i2c0 { - status =3D "okay"; - clock-frequency =3D <100000>; - - /* U31 */ - expander0: pca9555@21 { - compatible =3D "nxp,pca9555"; - pinctrl-names =3D "default"; - gpio-controller; - #gpio-cells =3D <2>; - reg =3D <0x21>; - }; - - /* U25 */ - expander1: pca9555@25 { - compatible =3D "nxp,pca9555"; - pinctrl-names =3D "default"; - gpio-controller; - #gpio-cells =3D <2>; - reg =3D <0x25>; - }; - -}; - -/* CON4 on CP0 expansion */ -&cp0_sata0 { - status =3D "okay"; -}; - -/* CON9 on CP0 expansion */ -&cp0_usb3_0 { - usb-phy =3D <&cp0_usb3_0_phy>; - status =3D "okay"; -}; - -/* CON10 on CP0 expansion */ -&cp0_usb3_1 { - usb-phy =3D <&cp0_usb3_1_phy>; - status =3D "okay"; -}; - -&cp0_mdio { - status =3D "okay"; - - phy1: ethernet-phy@1 { - reg =3D <1>; - }; -}; - -&cp0_ethernet { - status =3D "okay"; -}; - -&cp0_eth0 { - status =3D "okay"; - phy-mode =3D "10gbase-kr"; - - fixed-link { - speed =3D <10000>; - full-duplex; - }; -}; - -&cp0_eth2 { - status =3D "okay"; - phy =3D <&phy1>; - phy-mode =3D "rgmii-id"; -}; - -/* CON6 on CP1 expansion */ -&cp1_pcie0 { - status =3D "okay"; -}; - -/* CON7 on CP1 expansion */ -&cp1_pcie1 { - status =3D "okay"; -}; - -/* CON5 on CP1 expansion */ -&cp1_pcie2 { - status =3D "okay"; -}; - -&cp1_i2c0 { - status =3D "okay"; - clock-frequency =3D <100000>; -}; - -&cp1_spi1 { - status =3D "disabled"; - - spi-flash@0 { - #address-cells =3D <0x1>; - #size-cells =3D <0x1>; - compatible =3D "jedec,spi-nor"; - reg =3D <0x0>; - spi-max-frequency =3D <20000000>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "Boot"; - reg =3D <0x0 0x200000>; - }; - partition@200000 { - label =3D "Filesystem"; - reg =3D <0x200000 0xd00000>; - }; - partition@f00000 { - label =3D "Boot_2nd"; - reg =3D <0xf00000 0x100000>; - }; - }; - }; -}; - -/* - * Proper NAND usage will require DPR-76 to be in position 1-2, which disa= bles - * MDIO signal of CP1. - */ -&cp1_nand_controller { - pinctrl-0 =3D <&nand_pins>, <&nand_rb>; - pinctrl-names =3D "default"; - - nand@0 { - reg =3D <0>; - nand-rb =3D <0>; - nand-on-flash-bbt; - nand-ecc-strength =3D <4>; - nand-ecc-step-size =3D <512>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0 0x200000>; - }; - partition@200000 { - label =3D "Linux"; - reg =3D <0x200000 0xe00000>; - }; - partition@1000000 { - label =3D "Filesystem"; - reg =3D <0x1000000 0x3f000000>; - }; - }; - }; -}; - -/* CON4 on CP1 expansion */ -&cp1_sata0 { - status =3D "okay"; -}; - -/* CON9 on CP1 expansion */ -&cp1_usb3_0 { - usb-phy =3D <&cp1_usb3_0_phy>; - status =3D "okay"; -}; - -/* CON10 on CP1 expansion */ -&cp1_usb3_1 { - status =3D "okay"; -}; - -&cp1_mdio { - status =3D "okay"; - - phy0: ethernet-phy@0 { - reg =3D <0>; - }; -}; - -&cp1_ethernet { - status =3D "okay"; -}; - -&cp1_eth0 { - status =3D "okay"; - phy-mode =3D "10gbase-kr"; - - fixed-link { - speed =3D <10000>; - full-duplex; - }; -}; - -&cp1_eth1 { - status =3D "okay"; - phy =3D <&phy0>; - phy-mode =3D "rgmii-id"; -}; - -&ap_sdhci0 { - status =3D "okay"; - bus-width =3D <4>; - non-removable; -}; - -&cp0_sdhci0 { - status =3D "okay"; - bus-width =3D <8>; - non-removable; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/= Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts deleted file mode 100644 index d9c9348b53..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts +++ /dev/null @@ -1,377 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for MACCHIATOBin Armada 8040 community board platform - */ - -#include "armada-8040.dtsi" - -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - -/ { - model =3D "Marvell 8040 MACCHIATOBin"; - compatible =3D "marvell,armada8040-mcbin", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806= "; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - memory@0 { - device_type =3D "memory"; - reg =3D <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 =3D &cp0_eth0; - ethernet1 =3D &cp1_eth0; - ethernet2 =3D &cp1_eth1; - ethernet3 =3D &cp1_eth2; - }; - - /* Regulator labels correspond with schematics */ - v_3_3: regulator-3-3v { - compatible =3D "regulator-fixed"; - regulator-name =3D "v_3_3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - status =3D "okay"; - }; - - v_vddo_h: regulator-1-8v { - compatible =3D "regulator-fixed"; - regulator-name =3D "v_vddo_h"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-always-on; - status =3D "okay"; - }; - - v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { - compatible =3D "regulator-fixed"; - enable-active-high; - gpio =3D <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_xhci_vbus_pins>; - regulator-name =3D "v_5v0_usb3_hst_vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - status =3D "okay"; - }; - - usb3h0_phy: usb3_phy0 { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&v_5v0_usb3_hst_vbus>; - }; - - sfp_eth0: sfp-eth0 { - /* CON15,16 - CPM lane 4 */ - compatible =3D "sff,sfp"; - i2c-bus =3D <&sfpp0_i2c>; - los-gpio =3D <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio =3D <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; - tx-disable-gpio =3D <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; - tx-fault-gpio =3D <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_sfpp0_pins>; - }; - - sfp_eth1: sfp-eth1 { - /* CON17,18 - CPS lane 4 */ - compatible =3D "sff,sfp"; - i2c-bus =3D <&sfpp1_i2c>; - los-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; - mod-def0-gpio =3D <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; - tx-disable-gpio =3D <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; - tx-fault-gpio =3D <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_sfpp1_pins &cp0_sfpp1_pins>; - }; - - sfp_eth3: sfp-eth3 { - /* CON3,4 - CPS lane 5 */ - compatible =3D "sff,sfp"; - i2c-bus =3D <&sfp_1g_i2c>; - los-gpio =3D <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio =3D <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; - tx-disable-gpio =3D <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; - tx-fault-gpio =3D <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; - }; -}; - -&uart0 { - status =3D "okay"; - pinctrl-0 =3D <&uart0_pins>; - pinctrl-names =3D "default"; -}; - -&ap_sdhci0 { - bus-width =3D <8>; - /* - * Not stable in HS modes - phy needs "more calibration", so add - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. - */ - marvell,xenon-phy-slow-mode; - no-1-8-v; - no-sd; - no-sdio; - non-removable; - status =3D "okay"; - vqmmc-supply =3D <&v_vddo_h>; -}; - -&cp0_i2c0 { - clock-frequency =3D <100000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_i2c0_pins>; - status =3D "okay"; -}; - -&cp0_i2c1 { - clock-frequency =3D <100000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_i2c1_pins>; - status =3D "okay"; - - i2c-switch@70 { - compatible =3D "nxp,pca9548"; - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0x70>; - - sfpp0_i2c: i2c@0 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0>; - }; - sfpp1_i2c: i2c@1 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <1>; - }; - sfp_1g_i2c: i2c@2 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <2>; - }; - }; -}; - -/* J25 UART header */ -&cp0_uart1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_uart1_pins>; - status =3D "okay"; -}; - -&cp0_mdio { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_ge_mdio_pins>; - status =3D "okay"; - - ge_phy: ethernet-phy@0 { - reg =3D <0>; - }; -}; - -&cp0_pcie0 { - compatible =3D "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam"; - reg =3D <0 0xe0000000 0 0xff00000>; - bus-range =3D <0 0xfe>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_pcie_pins>; - num-lanes =3D <4>; - num-viewport =3D <8>; - reset-gpio =3D <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; - ranges =3D <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000= >, - <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>, - <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>; - status =3D "okay"; -}; - -&cp0_pinctrl { - cp0_ge_mdio_pins: ge-mdio-pins { - marvell,pins =3D "mpp32", "mpp34"; - marvell,function =3D "ge"; - }; - cp0_i2c1_pins: i2c1-pins { - marvell,pins =3D "mpp35", "mpp36"; - marvell,function =3D "i2c1"; - }; - cp0_i2c0_pins: i2c0-pins { - marvell,pins =3D "mpp37", "mpp38"; - marvell,function =3D "i2c0"; - }; - cp0_uart1_pins: uart1-pins { - marvell,pins =3D "mpp40", "mpp41"; - marvell,function =3D "uart1"; - }; - cp0_xhci_vbus_pins: xhci0-vbus-pins { - marvell,pins =3D "mpp47"; - marvell,function =3D "gpio"; - }; - cp0_sfp_1g_pins: sfp-1g-pins { - marvell,pins =3D "mpp51", "mpp53", "mpp54"; - marvell,function =3D "gpio"; - }; - cp0_pcie_pins: pcie-pins { - marvell,pins =3D "mpp52"; - marvell,function =3D "gpio"; - }; - cp0_sdhci_pins: sdhci-pins { - marvell,pins =3D "mpp55", "mpp56", "mpp57", "mpp58", "mpp5= 9", - "mpp60", "mpp61"; - marvell,function =3D "sdio"; - }; - cp0_sfpp1_pins: sfpp1-pins { - marvell,pins =3D "mpp62"; - marvell,function =3D "gpio"; - }; -}; - -&cp0_xmdio { - status =3D "okay"; - - phy0: ethernet-phy@0 { - compatible =3D "ethernet-phy-ieee802.3-c45"; - reg =3D <0>; - sfp =3D <&sfp_eth0>; - }; - - phy8: ethernet-phy@8 { - compatible =3D "ethernet-phy-ieee802.3-c45"; - reg =3D <8>; - sfp =3D <&sfp_eth1>; - }; -}; - -&cp0_ethernet { - status =3D "okay"; -}; - -&cp0_eth0 { - status =3D "okay"; - /* Network PHY */ - phy =3D <&phy0>; - phy-mode =3D "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp0_comphy4 0>; -}; - -&cp0_sata0 { - /* CPM Lane 0 - U29 */ - status =3D "okay"; -}; - -&cp0_sdhci0 { - /* U6 */ - broken-cd; - bus-width =3D <4>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_sdhci_pins>; - status =3D "okay"; - vqmmc-supply =3D <&v_3_3>; -}; - -&cp0_usb3_0 { - /* J38? - USB2.0 only */ - status =3D "okay"; -}; - -&cp0_usb3_1 { - /* J38? - USB2.0 only */ - status =3D "okay"; -}; - -&cp1_ethernet { - status =3D "okay"; -}; - -&cp1_eth0 { - status =3D "okay"; - /* Network PHY */ - phy =3D <&phy8>; - phy-mode =3D "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy4 0>; -}; - -&cp1_eth1 { - /* CPS Lane 0 - J5 (Gigabit RJ45) */ - status =3D "okay"; - /* Network PHY */ - phy =3D <&ge_phy>; - phy-mode =3D "sgmii"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy0 1>; -}; - -&cp1_eth2 { - /* CPS Lane 5 */ - status =3D "okay"; - /* Network PHY */ - phy-mode =3D "2500base-x"; - managed =3D "in-band-status"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy5 2>; - sfp =3D <&sfp_eth3>; -}; - -&cp1_pinctrl { - cp1_sfpp1_pins: sfpp1-pins { - marvell,pins =3D "mpp8", "mpp10", "mpp11"; - marvell,function =3D "gpio"; - }; - cp1_spi1_pins: spi1-pins { - marvell,pins =3D "mpp12", "mpp13", "mpp14", "mpp15", "mpp1= 6"; - marvell,function =3D "spi1"; - }; - cp1_uart0_pins: uart0-pins { - marvell,pins =3D "mpp6", "mpp7"; - marvell,function =3D "uart0"; - }; - cp1_sfp_1g_pins: sfp-1g-pins { - marvell,pins =3D "mpp24"; - marvell,function =3D "gpio"; - }; - cp1_sfpp0_pins: sfpp0-pins { - marvell,pins =3D "mpp26", "mpp27", "mpp28", "mpp29"; - marvell,function =3D "gpio"; - }; -}; - -/* J27 UART header */ -&cp1_uart0 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_uart0_pins>; - status =3D "okay"; -}; - -&cp1_sata0 { - /* CPS Lane 1 - U32 */ - /* CPS Lane 3 - U31 */ - status =3D "okay"; -}; - -&cp1_spi1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_spi1_pins>; - status =3D "disabled"; - - spi-flash@0 { - compatible =3D "st,w25q32"; - spi-max-frequency =3D <50000000>; - reg =3D <0>; - }; -}; - -&cp1_usb3_0 { - /* CPS Lane 2 - CON7 */ - usb-phy =3D <&usb3h0_phy>; - status =3D "okay"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi deleted file mode 100644 index 784ef3f311..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and - * two CP110. - */ - -#include "armada-ap806-quad.dtsi" -#include "armada-80x0.dtsi" - -/ { - model =3D "Marvell Armada 8040"; - compatible =3D "marvell,armada8040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; - -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock - * in CP master is not connected (by package) to the oscillator. So - * disable it. However, the RTC clock in CP slave is connected to the - * oscillator so this one is let enabled. - */ -&cp0_rtc { - status =3D "disabled"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi deleted file mode 100644 index 81967e20d3..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 80x0 SoC family - */ - -/ { - aliases { - gpio1 =3D &cp1_gpio1; - gpio2 =3D &cp0_gpio2; - spi1 =3D &cp0_spi0; - spi2 =3D &cp0_spi1; - spi3 =3D &cp1_spi0; - spi4 =3D &cp1_spi1; - }; -}; - -/* - * Instantiate the master CP110 - */ -#define CP110_NAME cp0 -#define CP110_BASE f2000000 -#define CP110_PCIE_IO_BASE 0xf9000000 -#define CP110_PCIE_MEM_BASE 0xf6000000 -#define CP110_PCIE0_BASE f2600000 -#define CP110_PCIE1_BASE f2620000 -#define CP110_PCIE2_BASE f2640000 - -#include "armada-cp110.dtsi" - -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE_IO_BASE -#undef CP110_PCIE_MEM_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE - -/* - * Instantiate the slave CP110 - */ -#define CP110_NAME cp1 -#define CP110_BASE f4000000 -#define CP110_PCIE_IO_BASE 0xfd000000 -#define CP110_PCIE_MEM_BASE 0xfa000000 -#define CP110_PCIE0_BASE f4600000 -#define CP110_PCIE1_BASE f4620000 -#define CP110_PCIE2_BASE f4640000 - -#include "armada-cp110.dtsi" - -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE_IO_BASE -#undef CP110_PCIE_MEM_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE - -/* The 80x0 has two CP blocks, but uses only one block from each. */ -&cp1_gpio1 { - status =3D "okay"; -}; - -&cp0_gpio2 { - status =3D "okay"; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible =3D "marvell,armada-8k-cpm-pinctrl"; - }; -}; - -&cp1_syscon0 { - cp1_pinctrl: pinctrl { - compatible =3D "marvell,armada-8k-cps-pinctrl"; - - nand_pins: nand-pins { - marvell,pins =3D - "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11", - "mpp15", "mpp16", "mpp17", "mpp18", - "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27"; - marvell,function =3D "dev"; - }; - - nand_rb: nand-rb { - marvell,pins =3D "mpp13", "mpp12"; - marvell,function =3D "nf"; - }; - }; -}; - -&cp1_crypto { - /* - * The cryptographic engine found on the cp110 - * master is enabled by default at the SoC - * level. Because it is not possible as of now - * to enable two cryptographic engines in - * parallel, disable this one by default. - */ - status =3D "disabled"; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi deleted file mode 100644 index 5985843fcc..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#include "armada-ap806.dtsi" - -/ { - model =3D "Marvell Armada AP806 Dual"; - compatible =3D "marvell,armada-ap806-dual", "marvell,armada-ap806"; - - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - - cpu@0 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x000>; - enable-method =3D "psci"; - }; - cpu@1 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x001>; - enable-method =3D "psci"; - }; - }; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi deleted file mode 100644 index bae0ed9ca7..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#include "armada-ap806.dtsi" - -/ { - model =3D "Marvell Armada AP806 Quad"; - compatible =3D "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - - cpu@0 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x000>; - enable-method =3D "psci"; - }; - cpu@1 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x001>; - enable-method =3D "psci"; - }; - cpu@100 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x100>; - enable-method =3D "psci"; - }; - cpu@101 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x101>; - enable-method =3D "psci"; - }; - }; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi deleted file mode 100644 index 66124bf483..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#define IRQ_TYPE_LEVEL_HIGH (1 << 2) -#define IRQ_TYPE_LEVEL_LOW (1 << 3) - -#define GIC_SPI 0 -#define GIC_PPI 1 - -#define GIC_CPU_MASK_RAW(x) ((x) << 8) -#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) - -/dts-v1/; - -/ { - model =3D "Marvell Armada AP806"; - compatible =3D "marvell,armada-ap806"; - #address-cells =3D <2>; - #size-cells =3D <2>; - - aliases { - serial0 =3D &uart0; - serial1 =3D &uart1; - gpio0 =3D &ap_gpio; - spi0 =3D &spi0; - }; - - psci { - compatible =3D "arm,psci-0.2"; - method =3D "smc"; - }; - - ap806 { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "simple-bus"; - interrupt-parent =3D <&gic>; - ranges; - - config-space@f0000000 { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "simple-bus"; - ranges =3D <0x0 0x0 0xf0000000 0x1000000>; - - gic: interrupt-controller@210000 { - compatible =3D "arm,gic-400"; - #interrupt-cells =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - interrupt-controller; - interrupts =3D ; - reg =3D <0x210000 0x10000>, - <0x220000 0x20000>, - <0x240000 0x20000>, - <0x260000 0x20000>; - - gic_v2m0: v2m@280000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x280000 0x1000>; - arm,msi-base-spi =3D <160>; - arm,msi-num-spis =3D <32>; - }; - gic_v2m1: v2m@290000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x290000 0x1000>; - arm,msi-base-spi =3D <192>; - arm,msi-num-spis =3D <32>; - }; - gic_v2m2: v2m@2a0000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x2a0000 0x1000>; - arm,msi-base-spi =3D <224>; - arm,msi-num-spis =3D <32>; - }; - gic_v2m3: v2m@2b0000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x2b0000 0x1000>; - arm,msi-base-spi =3D <256>; - arm,msi-num-spis =3D <32>; - }; - }; - - timer { - compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; - }; - - pmu { - compatible =3D "arm,cortex-a72-pmu"; - interrupt-parent =3D <&pic>; - interrupts =3D <17>; - }; - - odmi: odmi@300000 { - compatible =3D "marvell,odmi-controller"; - interrupt-controller; - msi-controller; - marvell,odmi-frames =3D <4>; - reg =3D <0x300000 0x4000>, - <0x304000 0x4000>, - <0x308000 0x4000>, - <0x30C000 0x4000>; - marvell,spi-base =3D <128>, <136>, <144>, = <152>; - }; - - gicp: gicp@3f0040 { - compatible =3D "marvell,ap806-gicp"; - reg =3D <0x3f0040 0x10>; - marvell,spi-ranges =3D <64 64>, <288 64>; - msi-controller; - }; - - pic: interrupt-controller@3f0100 { - compatible =3D "marvell,armada-8k-pic"; - reg =3D <0x3f0100 0x10>; - #interrupt-cells =3D <1>; - interrupt-controller; - interrupts =3D ; - }; - - xor@400000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x400000 0x1000>, - <0x410000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - xor@420000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x420000 0x1000>, - <0x430000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - xor@440000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x440000 0x1000>, - <0x450000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - xor@460000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x460000 0x1000>, - <0x470000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - spi0: spi@510600 { - compatible =3D "marvell,armada-380-spi"; - reg =3D <0x510600 0x50>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - }; - - i2c0: i2c@511000 { - compatible =3D "marvell,mv78230-i2c"; - reg =3D <0x511000 0x20>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - timeout-ms =3D <1000>; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - }; - - uart0: serial@512000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x512000 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - }; - - uart1: serial@512100 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x512100 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - - }; - - watchdog: watchdog@610000 { - compatible =3D "arm,sbsa-gwdt"; - reg =3D <0x610000 0x1000>, <0x600000 0x100= 0>; - interrupts =3D ; - }; - - ap_sdhci0: sdhci@6e0000 { - compatible =3D "marvell,armada-ap806-sdhci= "; - reg =3D <0x6e0000 0x300>; - interrupts =3D ; - clock-names =3D "core"; - clocks =3D <&ap_clk 4>; - dma-coherent; - marvell,xenon-phy-slow-mode; - status =3D "disabled"; - }; - - ap_syscon: system-controller@6f4000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x6f4000 0x2000>; - - ap_clk: clock { - compatible =3D "marvell,ap806-cloc= k"; - #clock-cells =3D <1>; - }; - - ap_pinctrl: pinctrl { - compatible =3D "marvell,ap806-pinc= trl"; - - uart0_pins: uart0-pins { - marvell,pins =3D "mpp11", = "mpp19"; - marvell,function =3D "uart= 0"; - }; - }; - - ap_gpio: gpio@1040 { - compatible =3D "marvell,armada-8k-= gpio"; - offset =3D <0x1040>; - ngpios =3D <20>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>; - }; - }; - - ap_thermal: thermal@6f808c { - compatible =3D "marvell,armada-ap806-therm= al"; - reg =3D <0x6f808c 0x4>, - <0x6f8084 0x8>; - }; - }; - }; -}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi deleted file mode 100644 index 8b610fd2b3..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - */ - -/* Common definitions used by Armada 7K/8K DTs */ -#define PASTER(x, y) x ## y -#define EVALUATOR(x, y) PASTER(x, y) -#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name)) -#define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi deleted file mode 100644 index 5e8e524cf7..0000000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi +++ /dev/null @@ -1,560 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada CP110. - */ - -#include "armada-common.dtsi" - -#define ICU_GRP_NSR 0x0 -#define ICU_GRP_SR 0x1 -#define ICU_GRP_SEI 0x4 -#define ICU_GRP_REI 0x5 - -#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * = 0x10000)) -#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface *= 0x1000000)) -#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) += 0xf00000) - -/ { - /* - * The contents of the node are defined below, in order to - * save one indentation level - */ - CP110_NAME: CP110_NAME { }; -}; - -&CP110_NAME { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "simple-bus"; - interrupt-parent =3D <&CP110_LABEL(icu)>; - ranges; - - config-space@CP110_BASE { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "simple-bus"; - ranges =3D <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; - - CP110_LABEL(ethernet): ethernet@0 { - compatible =3D "marvell,armada-7k-pp22"; - reg =3D <0x0 0x100000>, <0x129000 0xb000>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(c= ore_clk)>, - <&CP110_LABEL(core_clk)>; - clock-names =3D "pp_clk", "gop_clk", - "mg_clk", "mg_core_clk", "axi_clk"; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - status =3D "disabled"; - dma-coherent; - - CP110_LABEL(eth0): eth0 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <0>; - gop-port-id =3D <0>; - status =3D "disabled"; - }; - - CP110_LABEL(eth1): eth1 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <1>; - gop-port-id =3D <2>; - status =3D "disabled"; - }; - - CP110_LABEL(eth2): eth2 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <2>; - gop-port-id =3D <3>; - status =3D "disabled"; - }; - }; - - CP110_LABEL(comphy): phy@120000 { - compatible =3D "marvell,comphy-cp110"; - reg =3D <0x120000 0x6000>; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - CP110_LABEL(comphy0): phy@0 { - reg =3D <0>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy1): phy@1 { - reg =3D <1>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy2): phy@2 { - reg =3D <2>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy3): phy@3 { - reg =3D <3>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy4): phy@4 { - reg =3D <4>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy5): phy@5 { - reg =3D <5>; - #phy-cells =3D <1>; - }; - }; - - CP110_LABEL(mdio): mdio@12a200 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "marvell,orion-mdio"; - reg =3D <0x12a200 0x10>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(core_clk)>, <&CP110_LABEL(c= ore_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(xmdio): mdio@12a600 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "marvell,xmdio"; - reg =3D <0x12a600 0x10>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(icu): interrupt-controller@1e0000 { - compatible =3D "marvell,cp110-icu"; - reg =3D <0x1e0000 0x440>; - #interrupt-cells =3D <3>; - interrupt-controller; - msi-parent =3D <&gicp>; - }; - - CP110_LABEL(rtc): rtc@284000 { - compatible =3D "marvell,armada-8k-rtc"; - reg =3D <0x284000 0x20>, <0x284080 0x24>; - reg-names =3D "rtc", "rtc-soc"; - interrupts =3D ; - status =3D "disabled"; - }; - - CP110_LABEL(thermal): thermal@400078 { - compatible =3D "marvell,armada-cp110-thermal"; - reg =3D <0x400078 0x4>, - <0x400070 0x8>; - }; - - CP110_LABEL(syscon0): system-controller@440000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x440000 0x2000>; - - CP110_LABEL(clk): clock { - compatible =3D "marvell,cp110-clock"; - status =3D "disabled"; - #clock-cells =3D <2>; - }; - - CP110_LABEL(gpio1): gpio@100 { - compatible =3D "marvell,armada-8k-gpio"; - offset =3D <0x100>; - ngpios =3D <32>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 0= 32>; - interrupt-controller; - interrupts =3D , - , - , - ; - status =3D "disabled"; - }; - - CP110_LABEL(gpio2): gpio@140 { - compatible =3D "marvell,armada-8k-gpio"; - offset =3D <0x140>; - ngpios =3D <31>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 3= 2 31>; - interrupt-controller; - interrupts =3D , - , - , - ; - status =3D "disabled"; - }; - }; - - CP110_LABEL(usb3_0): usb3@500000 { - compatible =3D "marvell,armada-8k-xhci", - "generic-xhci"; - reg =3D <0x500000 0x4000>; - dma-coherent; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(usb3_1): usb3@510000 { - compatible =3D "marvell,armada-8k-xhci", - "generic-xhci"; - reg =3D <0x510000 0x4000>; - dma-coherent; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(sata0): sata@540000 { - compatible =3D "marvell,armada-8k-ahci", - "generic-ahci"; - reg =3D <0x540000 0x30000>; - dma-coherent; - interrupts =3D ; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(xor0): xor@6a0000 { - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; - reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(x2core_clk)>; - }; - - CP110_LABEL(xor1): xor@6c0000 { - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; - reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(x2core_clk)>; - }; - - CP110_LABEL(spi0): spi@700600 { - compatible =3D "marvell,armada-380-spi"; - reg =3D <0x700600 0x50>; - #address-cells =3D <0x1>; - #size-cells =3D <0x0>; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(spi1): spi@700680 { - compatible =3D "marvell,armada-380-spi"; - reg =3D <0x700680 0x50>; - #address-cells =3D <1>; - #size-cells =3D <0>; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(i2c0): i2c@701000 { - compatible =3D "marvell,mv78230-i2c"; - reg =3D <0x701000 0x20>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(i2c1): i2c@701100 { - compatible =3D "marvell,mv78230-i2c"; - reg =3D <0x701100 0x20>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart0): serial@702000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702000 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart1): serial@702100 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702100 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart2): serial@702200 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702200 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart3): serial@702300 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702300 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(nand_controller): nand@720000 { - /* - * Due to the limitation of the pins available - * this controller is only usable on the CPM - * for A7K and on the CPS for A8K. - */ - compatible =3D "marvell,armada-8k-nand-controller", - "marvell,armada370-nand-controller"; - reg =3D <0x720000 0x54>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(nand_clk)>, - <&CP110_LABEL(x2core_clk)>; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - status =3D "disabled"; - }; - - CP110_LABEL(trng): trng@760000 { - compatible =3D "marvell,armada-8k-rng", - "inside-secure,safexcel-eip76"; - reg =3D <0x760000 0x7d>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(x2core_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "okay"; - }; - - CP110_LABEL(sdhci0): sdhci@780000 { - compatible =3D "marvell,armada-cp110-sdhci"; - reg =3D <0x780000 0x300>; - interrupts =3D ; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL= (core_clk)>; - dma-coherent; - status =3D "disabled"; - }; - - CP110_LABEL(crypto): crypto@800000 { - compatible =3D "inside-secure,safexcel-eip197"; - reg =3D <0x800000 0x200000>; - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(x2core_clk)>, - <&CP110_LABEL(x2core_clk)>; - dma-coherent; - }; - }; - - CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* downstream I/O */ - <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BAS= E(0) 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BA= SE(0) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 2 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* downstream I/O */ - <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BAS= E(1) 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BA= SE(1) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 4 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* downstream I/O */ - <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BAS= E(2) 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BA= SE(2) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 3 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - /* 1 GHz fixed main PLL */ - CP110_LABEL(mainpll): CP110_LABEL(mainpll) { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <1000000000>; - }; - - CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <2>; - }; - - CP110_LABEL(core_clk): CP110_LABEL(core_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <2>; - }; - - CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <2>; - clock-div =3D <5>; - }; - - CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <2>; - clock-div =3D <5>; - }; - - CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <3>; - }; - - CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <4>; - }; -}; --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73022): https://edk2.groups.io/g/devel/message/73022 Mute This Topic: https://groups.io/mt/81438843/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 21:13:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73021+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73021+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616097506; cv=none; d=zohomail.com; s=zohoarc; b=BES7D3QPCOQ4Z83e04SsW4E6C1R/kme/lKQQ6DTABnR+kjX6wntUQykS3WbhYf2cqwhqe3rcsQFyMUM+W9cK4FlwSQV+1Ln4Bi/fM9yK9SLCsU6CwoeKCDOyZ9I08E3zSMtFQ1cgujS/rwet+vY0N8m19vl6ZjQNF3W+ZZQi60I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616097506; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Bu1MxxOk3907T9KauxdGet+os9e5ARSplogtPFJVR+g=; b=mOsENd1ehc0Z8M9FyjbAIU7noA+I3cC1fsAvx/4+s1T75X0M/xHEC5TPkO/OFNz8yDfZ1rJNfYb1Udm6zNJ/WNRPKhJEO4Jm1lAEtug3ohECa0jmeBoDJ/bYR8vTOAph8BDf2WHBCQHMEvVGS+hkWuYPO+4wOh0nk2kRURKpN78= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73021+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616097506648918.1459641174282; Thu, 18 Mar 2021 12:58:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id HIXGYY1788612xZbbHLBGxvA; Thu, 18 Mar 2021 12:58:26 -0700 X-Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by mx.groups.io with SMTP id smtpd.web09.214.1616097504883624403 for ; Thu, 18 Mar 2021 12:58:25 -0700 X-Received: by mail-lj1-f181.google.com with SMTP id f26so9048754ljp.8 for ; Thu, 18 Mar 2021 12:58:24 -0700 (PDT) X-Gm-Message-State: tqCsKD1ixfBGDiItIAP32KRCx1787277AA= X-Google-Smtp-Source: ABdhPJzTW/LwhVnlAioMgYk1iLDO413H10YkBESZmyjeOAlPwsc4O/5PSl/fFL1mhJXsI/ZtKeWGsg== X-Received: by 2002:a2e:95d2:: with SMTP id y18mr6703460ljh.353.1616097502650; Thu, 18 Mar 2021 12:58:22 -0700 (PDT) X-Received: from gilgamesh.int.semihalf.com (host-193.106.246.138.static.3s.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id b30sm344622lfj.101.2021.03.18.12.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 12:58:22 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ard.biesheuvel@arm.com, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com, jon@solid-run.com Subject: [edk2-devel] [edk2-non-osi PATCH 2/4] Marvell/Armada7k8k: Move device tree sources from edk2-platforms Date: Thu, 18 Mar 2021 20:57:54 +0100 Message-Id: <20210318195757.2974226-2-mw@semihalf.com> In-Reply-To: <20210318195757.2974226-1-mw@semihalf.com> References: <20210318195757.2974226-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616097506; bh=MRu7MUnz+3XPeCcc0sXDtdaAFKV5EkPOxsRJGHr0x5c=; h=Cc:Date:From:Reply-To:Subject:To; b=RrEw/l2zKXDOIoL81oit6vzwboYarNHym24P9oPHaam/+7/qUKJkBs1rA8mR8mI+p0X K0XTLj04a5cy9NEIw/PKz/8dpyTFiVE8R9dRTFlKIBJ9NWVRDyQf3xwvXItCbyA/IaABa UaOvdINtwJmk8ZMgwpJO7sABMXX1wbPRdn8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" edk2-non-osi project is a more proper place for keeping the device tree sources, so keep it here from now on. Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf | 22 + Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf | 22 + Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf | 22 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi | 16 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 267 +++++++= +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 16 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 64 +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi | 26 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 336 +++++++= +++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 377 +++++++= ++++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 25 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 108 ++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 31 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 43 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 264 +++++++= ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 10 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 560 +++++++= +++++++++++++ 17 files changed, 2209 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.i= nf create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin= .dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual= .dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad= .dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf b/Silic= on/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf new file mode 100644 index 0000000..b533578 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell Armada 7040 DB platform +# +# Copyright (c) 2018, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Armada70x0DbDeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + armada-7040-db.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf b/Silic= on/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf new file mode 100644 index 0000000..378fad2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell Armada 8040 DB platform +# +# Copyright (c) 2018, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Armada80x0DbDeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + armada-8040-db.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf b/Si= licon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf new file mode 100644 index 0000000..540e1a7 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell Armada 8040 MacchiatoBin platform +# +# Copyright (c) 2018, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Armada80x0McBinDeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + armada-8040-mcbin.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi new file mode 100644 index 0000000..e2edc26 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and + * one CP110. + */ + +#include "armada-ap806-dual.dtsi" +#include "armada-70x0.dtsi" + +/ { + model =3D "Marvell Armada 7020"; + compatible =3D "marvell,armada7020", "marvell,armada-ap806-dual", + "marvell,armada-ap806"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts new file mode 100644 index 0000000..f5878ef --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada 7040 Development board platform + */ + +#include "armada-7040.dtsi" + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + model =3D "Marvell Armada 7040 DB board"; + compatible =3D "marvell,armada7040-db", "marvell,armada7040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x80000000>; + }; + + aliases { + ethernet0 =3D &cp0_eth0; + ethernet1 =3D &cp0_eth1; + ethernet2 =3D &cp0_eth2; + }; + + cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb3h0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb3h1-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy: cp0-usb3-0-phy { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_0_vbus>; + }; + + cp0_usb3_1_phy: cp0-usb3-1-phy { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_1_vbus>; + }; +}; + +&i2c0 { + status =3D "okay"; + clock-frequency =3D <100000>; +}; + +&spi0 { + status =3D "okay"; + + spi-flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0 0x200000>; + }; + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xce0000>; + }; + }; + }; +}; + +&uart0 { + status =3D "okay"; + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; +}; + + +&cp0_pcie2 { + status =3D "okay"; +}; + +&cp0_i2c0 { + status =3D "okay"; + clock-frequency =3D <100000>; + + expander0: pca9555@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + /* + * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect + * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit + * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN + * IO0_3: USB2_DEVICE_DETECT + * IO0_4: GPIO_0 IO1_4: SD_Status + * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable + * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC + * IO0_7: IO1_7: SDIO_Vcntrl + */ + }; +}; + +&cp0_nand_controller { + /* + * SPI on CPM and NAND have common pins on this board. We can + * use only one at a time. To enable the NAND (which will + * disable the SPI), the "status =3D "okay";" line have to be + * added here. + */ + pinctrl-0 =3D <&nand_pins>, <&nand_rb>; + pinctrl-names =3D "default"; + + nand@0 { + reg =3D <0>; + label =3D "pxa3xx_nand-0"; + nand-rb =3D <0>; + nand-on-flash-bbt; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0 0x200000>; + }; + + partition@200000 { + label =3D "Linux"; + reg =3D <0x200000 0xe00000>; + }; + + partition@1000000 { + label =3D "Filesystem"; + reg =3D <0x1000000 0x3f000000>; + }; + + }; + }; +}; + +&cp0_spi1 { + status =3D "disabled"; + + spi-flash@0 { + #address-cells =3D <0x1>; + #size-cells =3D <0x1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-max-frequency =3D <20000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0x0 0x200000>; + }; + + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xe00000>; + }; + }; + }; +}; + +&cp0_sata0 { + status =3D "okay"; +}; + +&cp0_usb3_0 { + usb-phy =3D <&cp0_usb3_0_phy>; + status =3D "okay"; +}; + +&cp0_usb3_1 { + usb-phy =3D <&cp0_usb3_1_phy>; + status =3D "okay"; +}; + +&ap_sdhci0 { + status =3D "okay"; + bus-width =3D <4>; + no-1-8-v; + non-removable; +}; + +&cp0_sdhci0 { + status =3D "okay"; + bus-width =3D <4>; + no-1-8-v; + cd-gpios =3D <&expander0 12 GPIO_ACTIVE_LOW>; +}; + +&cp0_mdio { + status =3D "okay"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + phy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; + +&cp0_ethernet { + status =3D "okay"; +}; + +&cp0_eth0 { + status =3D "okay"; + /* Network PHY */ + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy2 0>; + + fixed-link { + speed =3D <10000>; + full-duplex; + }; +}; + +&cp0_eth1 { + status =3D "okay"; + /* Network PHY */ + phy =3D <&phy0>; + phy-mode =3D "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy0 1>; +}; + +&cp0_eth2 { + status =3D "okay"; + phy =3D <&phy1>; + phy-mode =3D "rgmii-id"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi new file mode 100644 index 0000000..03109b2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and + * one CP110. + */ + +#include "armada-ap806-quad.dtsi" +#include "armada-70x0.dtsi" + +/ { + model =3D "Marvell Armada 7040"; + compatible =3D "marvell,armada7040", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi new file mode 100644 index 0000000..78f9d87 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 70x0 SoC + */ + +/ { + aliases { + gpio1 =3D &cp0_gpio1; + gpio2 =3D &cp0_gpio2; + spi1 =3D &cp0_spi0; + spi2 =3D &cp0_spi1; + }; +}; + +/* + * Instantiate the CP110 + */ +#define CP110_NAME cp0 +#define CP110_BASE f2000000 +#define CP110_PCIE_IO_BASE 0xf9000000 +#define CP110_PCIE_MEM_BASE 0xf6000000 +#define CP110_PCIE0_BASE f2600000 +#define CP110_PCIE1_BASE f2620000 +#define CP110_PCIE2_BASE f2640000 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE_IO_BASE +#undef CP110_PCIE_MEM_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE + +&cp0_gpio1 { + status =3D "okay"; +}; + +&cp0_gpio2 { + status =3D "okay"; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible =3D "marvell,armada-7k-pinctrl"; + + nand_pins: nand-pins { + marvell,pins =3D + "mpp15", "mpp16", "mpp17", "mpp18", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function =3D "dev"; + }; + + nand_rb: nand-rb { + marvell,pins =3D "mpp13"; + marvell,function =3D "nf"; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi new file mode 100644 index 0000000..5d76345 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and + * two CP110. + */ + +#include "armada-ap806-dual.dtsi" +#include "armada-80x0.dtsi" + +/ { + model =3D "Marvell Armada 8020"; + compatible =3D "marvell,armada8020", "marvell,armada-ap806-dual", + "marvell,armada-ap806"; +}; + +/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock + * in CP master is not connected (by package) to the oscillator. So + * disable it. However, the RTC clock in CP slave is connected to the + * oscillator so this one is let enabled. + */ + +&cp0_rtc { + status =3D "disabled"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts new file mode 100644 index 0000000..e813922 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada 8040 Development board platform + */ + +#include "armada-8040.dtsi" + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + model =3D "Marvell Armada 8040 DB board"; + compatible =3D "marvell,armada8040-db", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x80000000>; + }; + + aliases { + ethernet0 =3D &cp0_eth0; + ethernet1 =3D &cp0_eth2; + ethernet2 =3D &cp1_eth0; + ethernet3 =3D &cp1_eth1; + }; + + cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0-usb3h0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0-usb3h1-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy: cp0-usb3-0-phy { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_0_vbus>; + }; + + cp0_usb3_1_phy: cp0-usb3-1-phy { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_1_vbus>; + }; + + cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp1-usb3h0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander1 0 GPIO_ACTIVE_HIGH>; + }; + + cp1_usb3_0_phy: cp1-usb3-0-phy { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp1_reg_usb3_0_vbus>; + }; +}; + +&i2c0 { + status =3D "okay"; + clock-frequency =3D <100000>; +}; + +&spi0 { + status =3D "okay"; + + spi-flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0 0x200000>; + }; + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xce0000>; + }; + }; + }; +}; + +/* Accessible over the mini-USB CON9 connector on the main board */ +&uart0 { + status =3D "okay"; + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; +}; + +/* CON6 on CP0 expansion */ +&cp0_pcie0 { + status =3D "okay"; +}; + +/* CON5 on CP0 expansion */ +&cp0_pcie2 { + status =3D "okay"; +}; + +&cp0_i2c0 { + status =3D "okay"; + clock-frequency =3D <100000>; + + /* U31 */ + expander0: pca9555@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + }; + + /* U25 */ + expander1: pca9555@25 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x25>; + }; + +}; + +/* CON4 on CP0 expansion */ +&cp0_sata0 { + status =3D "okay"; +}; + +/* CON9 on CP0 expansion */ +&cp0_usb3_0 { + usb-phy =3D <&cp0_usb3_0_phy>; + status =3D "okay"; +}; + +/* CON10 on CP0 expansion */ +&cp0_usb3_1 { + usb-phy =3D <&cp0_usb3_1_phy>; + status =3D "okay"; +}; + +&cp0_mdio { + status =3D "okay"; + + phy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; + +&cp0_ethernet { + status =3D "okay"; +}; + +&cp0_eth0 { + status =3D "okay"; + phy-mode =3D "10gbase-kr"; + + fixed-link { + speed =3D <10000>; + full-duplex; + }; +}; + +&cp0_eth2 { + status =3D "okay"; + phy =3D <&phy1>; + phy-mode =3D "rgmii-id"; +}; + +/* CON6 on CP1 expansion */ +&cp1_pcie0 { + status =3D "okay"; +}; + +/* CON7 on CP1 expansion */ +&cp1_pcie1 { + status =3D "okay"; +}; + +/* CON5 on CP1 expansion */ +&cp1_pcie2 { + status =3D "okay"; +}; + +&cp1_i2c0 { + status =3D "okay"; + clock-frequency =3D <100000>; +}; + +&cp1_spi1 { + status =3D "disabled"; + + spi-flash@0 { + #address-cells =3D <0x1>; + #size-cells =3D <0x1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-max-frequency =3D <20000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "Boot"; + reg =3D <0x0 0x200000>; + }; + partition@200000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xd00000>; + }; + partition@f00000 { + label =3D "Boot_2nd"; + reg =3D <0xf00000 0x100000>; + }; + }; + }; +}; + +/* + * Proper NAND usage will require DPR-76 to be in position 1-2, which disa= bles + * MDIO signal of CP1. + */ +&cp1_nand_controller { + pinctrl-0 =3D <&nand_pins>, <&nand_rb>; + pinctrl-names =3D "default"; + + nand@0 { + reg =3D <0>; + nand-rb =3D <0>; + nand-on-flash-bbt; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0 0x200000>; + }; + partition@200000 { + label =3D "Linux"; + reg =3D <0x200000 0xe00000>; + }; + partition@1000000 { + label =3D "Filesystem"; + reg =3D <0x1000000 0x3f000000>; + }; + }; + }; +}; + +/* CON4 on CP1 expansion */ +&cp1_sata0 { + status =3D "okay"; +}; + +/* CON9 on CP1 expansion */ +&cp1_usb3_0 { + usb-phy =3D <&cp1_usb3_0_phy>; + status =3D "okay"; +}; + +/* CON10 on CP1 expansion */ +&cp1_usb3_1 { + status =3D "okay"; +}; + +&cp1_mdio { + status =3D "okay"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&cp1_ethernet { + status =3D "okay"; +}; + +&cp1_eth0 { + status =3D "okay"; + phy-mode =3D "10gbase-kr"; + + fixed-link { + speed =3D <10000>; + full-duplex; + }; +}; + +&cp1_eth1 { + status =3D "okay"; + phy =3D <&phy0>; + phy-mode =3D "rgmii-id"; +}; + +&ap_sdhci0 { + status =3D "okay"; + bus-width =3D <4>; + non-removable; +}; + +&cp0_sdhci0 { + status =3D "okay"; + bus-width =3D <8>; + non-removable; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/= Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts new file mode 100644 index 0000000..d9c9348 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for MACCHIATOBin Armada 8040 community board platform + */ + +#include "armada-8040.dtsi" + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + model =3D "Marvell 8040 MACCHIATOBin"; + compatible =3D "marvell,armada8040-mcbin", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806= "; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x80000000>; + }; + + aliases { + ethernet0 =3D &cp0_eth0; + ethernet1 =3D &cp1_eth0; + ethernet2 =3D &cp1_eth1; + ethernet3 =3D &cp1_eth2; + }; + + /* Regulator labels correspond with schematics */ + v_3_3: regulator-3-3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "v_3_3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + status =3D "okay"; + }; + + v_vddo_h: regulator-1-8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "v_vddo_h"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + status =3D "okay"; + }; + + v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_xhci_vbus_pins>; + regulator-name =3D "v_5v0_usb3_hst_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + status =3D "okay"; + }; + + usb3h0_phy: usb3_phy0 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&v_5v0_usb3_hst_vbus>; + }; + + sfp_eth0: sfp-eth0 { + /* CON15,16 - CPM lane 4 */ + compatible =3D "sff,sfp"; + i2c-bus =3D <&sfpp0_i2c>; + los-gpio =3D <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_sfpp0_pins>; + }; + + sfp_eth1: sfp-eth1 { + /* CON17,18 - CPS lane 4 */ + compatible =3D "sff,sfp"; + i2c-bus =3D <&sfpp1_i2c>; + los-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_sfpp1_pins &cp0_sfpp1_pins>; + }; + + sfp_eth3: sfp-eth3 { + /* CON3,4 - CPS lane 5 */ + compatible =3D "sff,sfp"; + i2c-bus =3D <&sfp_1g_i2c>; + los-gpio =3D <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; + }; +}; + +&uart0 { + status =3D "okay"; + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; +}; + +&ap_sdhci0 { + bus-width =3D <8>; + /* + * Not stable in HS modes - phy needs "more calibration", so add + * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. + */ + marvell,xenon-phy-slow-mode; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + status =3D "okay"; + vqmmc-supply =3D <&v_vddo_h>; +}; + +&cp0_i2c0 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_i2c0_pins>; + status =3D "okay"; +}; + +&cp0_i2c1 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_i2c1_pins>; + status =3D "okay"; + + i2c-switch@70 { + compatible =3D "nxp,pca9548"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + + sfpp0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + sfpp1_i2c: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + sfp_1g_i2c: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + }; +}; + +/* J25 UART header */ +&cp0_uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_uart1_pins>; + status =3D "okay"; +}; + +&cp0_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_ge_mdio_pins>; + status =3D "okay"; + + ge_phy: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&cp0_pcie0 { + compatible =3D "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam"; + reg =3D <0 0xe0000000 0 0xff00000>; + bus-range =3D <0 0xfe>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_pcie_pins>; + num-lanes =3D <4>; + num-viewport =3D <8>; + reset-gpio =3D <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; + ranges =3D <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000= >, + <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>, + <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>; + status =3D "okay"; +}; + +&cp0_pinctrl { + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins =3D "mpp32", "mpp34"; + marvell,function =3D "ge"; + }; + cp0_i2c1_pins: i2c1-pins { + marvell,pins =3D "mpp35", "mpp36"; + marvell,function =3D "i2c1"; + }; + cp0_i2c0_pins: i2c0-pins { + marvell,pins =3D "mpp37", "mpp38"; + marvell,function =3D "i2c0"; + }; + cp0_uart1_pins: uart1-pins { + marvell,pins =3D "mpp40", "mpp41"; + marvell,function =3D "uart1"; + }; + cp0_xhci_vbus_pins: xhci0-vbus-pins { + marvell,pins =3D "mpp47"; + marvell,function =3D "gpio"; + }; + cp0_sfp_1g_pins: sfp-1g-pins { + marvell,pins =3D "mpp51", "mpp53", "mpp54"; + marvell,function =3D "gpio"; + }; + cp0_pcie_pins: pcie-pins { + marvell,pins =3D "mpp52"; + marvell,function =3D "gpio"; + }; + cp0_sdhci_pins: sdhci-pins { + marvell,pins =3D "mpp55", "mpp56", "mpp57", "mpp58", "mpp5= 9", + "mpp60", "mpp61"; + marvell,function =3D "sdio"; + }; + cp0_sfpp1_pins: sfpp1-pins { + marvell,pins =3D "mpp62"; + marvell,function =3D "gpio"; + }; +}; + +&cp0_xmdio { + status =3D "okay"; + + phy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c45"; + reg =3D <0>; + sfp =3D <&sfp_eth0>; + }; + + phy8: ethernet-phy@8 { + compatible =3D "ethernet-phy-ieee802.3-c45"; + reg =3D <8>; + sfp =3D <&sfp_eth1>; + }; +}; + +&cp0_ethernet { + status =3D "okay"; +}; + +&cp0_eth0 { + status =3D "okay"; + /* Network PHY */ + phy =3D <&phy0>; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy4 0>; +}; + +&cp0_sata0 { + /* CPM Lane 0 - U29 */ + status =3D "okay"; +}; + +&cp0_sdhci0 { + /* U6 */ + broken-cd; + bus-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_sdhci_pins>; + status =3D "okay"; + vqmmc-supply =3D <&v_3_3>; +}; + +&cp0_usb3_0 { + /* J38? - USB2.0 only */ + status =3D "okay"; +}; + +&cp0_usb3_1 { + /* J38? - USB2.0 only */ + status =3D "okay"; +}; + +&cp1_ethernet { + status =3D "okay"; +}; + +&cp1_eth0 { + status =3D "okay"; + /* Network PHY */ + phy =3D <&phy8>; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy4 0>; +}; + +&cp1_eth1 { + /* CPS Lane 0 - J5 (Gigabit RJ45) */ + status =3D "okay"; + /* Network PHY */ + phy =3D <&ge_phy>; + phy-mode =3D "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy0 1>; +}; + +&cp1_eth2 { + /* CPS Lane 5 */ + status =3D "okay"; + /* Network PHY */ + phy-mode =3D "2500base-x"; + managed =3D "in-band-status"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy5 2>; + sfp =3D <&sfp_eth3>; +}; + +&cp1_pinctrl { + cp1_sfpp1_pins: sfpp1-pins { + marvell,pins =3D "mpp8", "mpp10", "mpp11"; + marvell,function =3D "gpio"; + }; + cp1_spi1_pins: spi1-pins { + marvell,pins =3D "mpp12", "mpp13", "mpp14", "mpp15", "mpp1= 6"; + marvell,function =3D "spi1"; + }; + cp1_uart0_pins: uart0-pins { + marvell,pins =3D "mpp6", "mpp7"; + marvell,function =3D "uart0"; + }; + cp1_sfp_1g_pins: sfp-1g-pins { + marvell,pins =3D "mpp24"; + marvell,function =3D "gpio"; + }; + cp1_sfpp0_pins: sfpp0-pins { + marvell,pins =3D "mpp26", "mpp27", "mpp28", "mpp29"; + marvell,function =3D "gpio"; + }; +}; + +/* J27 UART header */ +&cp1_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_uart0_pins>; + status =3D "okay"; +}; + +&cp1_sata0 { + /* CPS Lane 1 - U32 */ + /* CPS Lane 3 - U31 */ + status =3D "okay"; +}; + +&cp1_spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_spi1_pins>; + status =3D "disabled"; + + spi-flash@0 { + compatible =3D "st,w25q32"; + spi-max-frequency =3D <50000000>; + reg =3D <0>; + }; +}; + +&cp1_usb3_0 { + /* CPS Lane 2 - CON7 */ + usb-phy =3D <&usb3h0_phy>; + status =3D "okay"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi new file mode 100644 index 0000000..784ef3f --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and + * two CP110. + */ + +#include "armada-ap806-quad.dtsi" +#include "armada-80x0.dtsi" + +/ { + model =3D "Marvell Armada 8040"; + compatible =3D "marvell,armada8040", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; + +/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock + * in CP master is not connected (by package) to the oscillator. So + * disable it. However, the RTC clock in CP slave is connected to the + * oscillator so this one is let enabled. + */ +&cp0_rtc { + status =3D "disabled"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi new file mode 100644 index 0000000..81967e2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 80x0 SoC family + */ + +/ { + aliases { + gpio1 =3D &cp1_gpio1; + gpio2 =3D &cp0_gpio2; + spi1 =3D &cp0_spi0; + spi2 =3D &cp0_spi1; + spi3 =3D &cp1_spi0; + spi4 =3D &cp1_spi1; + }; +}; + +/* + * Instantiate the master CP110 + */ +#define CP110_NAME cp0 +#define CP110_BASE f2000000 +#define CP110_PCIE_IO_BASE 0xf9000000 +#define CP110_PCIE_MEM_BASE 0xf6000000 +#define CP110_PCIE0_BASE f2600000 +#define CP110_PCIE1_BASE f2620000 +#define CP110_PCIE2_BASE f2640000 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE_IO_BASE +#undef CP110_PCIE_MEM_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE + +/* + * Instantiate the slave CP110 + */ +#define CP110_NAME cp1 +#define CP110_BASE f4000000 +#define CP110_PCIE_IO_BASE 0xfd000000 +#define CP110_PCIE_MEM_BASE 0xfa000000 +#define CP110_PCIE0_BASE f4600000 +#define CP110_PCIE1_BASE f4620000 +#define CP110_PCIE2_BASE f4640000 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE_IO_BASE +#undef CP110_PCIE_MEM_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE + +/* The 80x0 has two CP blocks, but uses only one block from each. */ +&cp1_gpio1 { + status =3D "okay"; +}; + +&cp0_gpio2 { + status =3D "okay"; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible =3D "marvell,armada-8k-cpm-pinctrl"; + }; +}; + +&cp1_syscon0 { + cp1_pinctrl: pinctrl { + compatible =3D "marvell,armada-8k-cps-pinctrl"; + + nand_pins: nand-pins { + marvell,pins =3D + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11", + "mpp15", "mpp16", "mpp17", "mpp18", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function =3D "dev"; + }; + + nand_rb: nand-rb { + marvell,pins =3D "mpp13", "mpp12"; + marvell,function =3D "nf"; + }; + }; +}; + +&cp1_crypto { + /* + * The cryptographic engine found on the cp110 + * master is enabled by default at the SoC + * level. Because it is not possible as of now + * to enable two cryptographic engines in + * parallel, disable this one by default. + */ + status =3D "disabled"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi new file mode 100644 index 0000000..5985843 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#include "armada-ap806.dtsi" + +/ { + model =3D "Marvell Armada AP806 Dual"; + compatible =3D "marvell,armada-ap806-dual", "marvell,armada-ap806"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x000>; + enable-method =3D "psci"; + }; + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x001>; + enable-method =3D "psci"; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi new file mode 100644 index 0000000..bae0ed9 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#include "armada-ap806.dtsi" + +/ { + model =3D "Marvell Armada AP806 Quad"; + compatible =3D "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x000>; + enable-method =3D "psci"; + }; + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x001>; + enable-method =3D "psci"; + }; + cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x100>; + enable-method =3D "psci"; + }; + cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x101>; + enable-method =3D "psci"; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi new file mode 100644 index 0000000..66124bf --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#define IRQ_TYPE_LEVEL_HIGH (1 << 2) +#define IRQ_TYPE_LEVEL_LOW (1 << 3) + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define GIC_CPU_MASK_RAW(x) ((x) << 8) +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) + +/dts-v1/; + +/ { + model =3D "Marvell Armada AP806"; + compatible =3D "marvell,armada-ap806"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + gpio0 =3D &ap_gpio; + spi0 =3D &spi0; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + ap806 { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + ranges; + + config-space@f0000000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 0xf0000000 0x1000000>; + + gic: interrupt-controller@210000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + interrupt-controller; + interrupts =3D ; + reg =3D <0x210000 0x10000>, + <0x220000 0x20000>, + <0x240000 0x20000>, + <0x260000 0x20000>; + + gic_v2m0: v2m@280000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x280000 0x1000>; + arm,msi-base-spi =3D <160>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m1: v2m@290000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x290000 0x1000>; + arm,msi-base-spi =3D <192>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m2: v2m@2a0000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x2a0000 0x1000>; + arm,msi-base-spi =3D <224>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m3: v2m@2b0000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x2b0000 0x1000>; + arm,msi-base-spi =3D <256>; + arm,msi-num-spis =3D <32>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + pmu { + compatible =3D "arm,cortex-a72-pmu"; + interrupt-parent =3D <&pic>; + interrupts =3D <17>; + }; + + odmi: odmi@300000 { + compatible =3D "marvell,odmi-controller"; + interrupt-controller; + msi-controller; + marvell,odmi-frames =3D <4>; + reg =3D <0x300000 0x4000>, + <0x304000 0x4000>, + <0x308000 0x4000>, + <0x30C000 0x4000>; + marvell,spi-base =3D <128>, <136>, <144>, = <152>; + }; + + gicp: gicp@3f0040 { + compatible =3D "marvell,ap806-gicp"; + reg =3D <0x3f0040 0x10>; + marvell,spi-ranges =3D <64 64>, <288 64>; + msi-controller; + }; + + pic: interrupt-controller@3f0100 { + compatible =3D "marvell,armada-8k-pic"; + reg =3D <0x3f0100 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts =3D ; + }; + + xor@400000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x400000 0x1000>, + <0x410000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@420000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x420000 0x1000>, + <0x430000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@440000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x440000 0x1000>, + <0x450000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@460000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x460000 0x1000>, + <0x470000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + spi0: spi@510600 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x510600 0x50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + i2c0: i2c@511000 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x511000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + timeout-ms =3D <1000>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + uart0: serial@512000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x512000 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + uart1: serial@512100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x512100 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + + }; + + watchdog: watchdog@610000 { + compatible =3D "arm,sbsa-gwdt"; + reg =3D <0x610000 0x1000>, <0x600000 0x100= 0>; + interrupts =3D ; + }; + + ap_sdhci0: sdhci@6e0000 { + compatible =3D "marvell,armada-ap806-sdhci= "; + reg =3D <0x6e0000 0x300>; + interrupts =3D ; + clock-names =3D "core"; + clocks =3D <&ap_clk 4>; + dma-coherent; + marvell,xenon-phy-slow-mode; + status =3D "disabled"; + }; + + ap_syscon: system-controller@6f4000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x6f4000 0x2000>; + + ap_clk: clock { + compatible =3D "marvell,ap806-cloc= k"; + #clock-cells =3D <1>; + }; + + ap_pinctrl: pinctrl { + compatible =3D "marvell,ap806-pinc= trl"; + + uart0_pins: uart0-pins { + marvell,pins =3D "mpp11", = "mpp19"; + marvell,function =3D "uart= 0"; + }; + }; + + ap_gpio: gpio@1040 { + compatible =3D "marvell,armada-8k-= gpio"; + offset =3D <0x1040>; + ngpios =3D <20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>; + }; + }; + + ap_thermal: thermal@6f808c { + compatible =3D "marvell,armada-ap806-therm= al"; + reg =3D <0x6f808c 0x4>, + <0x6f8084 0x8>; + }; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi new file mode 100644 index 0000000..8b610fd --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + */ + +/* Common definitions used by Armada 7K/8K DTs */ +#define PASTER(x, y) x ## y +#define EVALUATOR(x, y) PASTER(x, y) +#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name)) +#define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi new file mode 100644 index 0000000..5e8e524 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi @@ -0,0 +1,560 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada CP110. + */ + +#include "armada-common.dtsi" + +#define ICU_GRP_NSR 0x0 +#define ICU_GRP_SR 0x1 +#define ICU_GRP_SEI 0x4 +#define ICU_GRP_REI 0x5 + +#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * = 0x10000)) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface *= 0x1000000)) +#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) += 0xf00000) + +/ { + /* + * The contents of the node are defined below, in order to + * save one indentation level + */ + CP110_NAME: CP110_NAME { }; +}; + +&CP110_NAME { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&CP110_LABEL(icu)>; + ranges; + + config-space@CP110_BASE { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; + + CP110_LABEL(ethernet): ethernet@0 { + compatible =3D "marvell,armada-7k-pp22"; + reg =3D <0x0 0x100000>, <0x129000 0xb000>; + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, + <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(c= ore_clk)>, + <&CP110_LABEL(core_clk)>; + clock-names =3D "pp_clk", "gop_clk", + "mg_clk", "mg_core_clk", "axi_clk"; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + status =3D "disabled"; + dma-coherent; + + CP110_LABEL(eth0): eth0 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <0>; + gop-port-id =3D <0>; + status =3D "disabled"; + }; + + CP110_LABEL(eth1): eth1 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <1>; + gop-port-id =3D <2>; + status =3D "disabled"; + }; + + CP110_LABEL(eth2): eth2 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <2>; + gop-port-id =3D <3>; + status =3D "disabled"; + }; + }; + + CP110_LABEL(comphy): phy@120000 { + compatible =3D "marvell,comphy-cp110"; + reg =3D <0x120000 0x6000>; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + CP110_LABEL(comphy0): phy@0 { + reg =3D <0>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy1): phy@1 { + reg =3D <1>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy2): phy@2 { + reg =3D <2>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy3): phy@3 { + reg =3D <3>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy4): phy@4 { + reg =3D <4>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy5): phy@5 { + reg =3D <5>; + #phy-cells =3D <1>; + }; + }; + + CP110_LABEL(mdio): mdio@12a200 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,orion-mdio"; + reg =3D <0x12a200 0x10>; + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, + <&CP110_LABEL(core_clk)>, <&CP110_LABEL(c= ore_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(xmdio): mdio@12a600 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,xmdio"; + reg =3D <0x12a600 0x10>; + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(icu): interrupt-controller@1e0000 { + compatible =3D "marvell,cp110-icu"; + reg =3D <0x1e0000 0x440>; + #interrupt-cells =3D <3>; + interrupt-controller; + msi-parent =3D <&gicp>; + }; + + CP110_LABEL(rtc): rtc@284000 { + compatible =3D "marvell,armada-8k-rtc"; + reg =3D <0x284000 0x20>, <0x284080 0x24>; + reg-names =3D "rtc", "rtc-soc"; + interrupts =3D ; + status =3D "disabled"; + }; + + CP110_LABEL(thermal): thermal@400078 { + compatible =3D "marvell,armada-cp110-thermal"; + reg =3D <0x400078 0x4>, + <0x400070 0x8>; + }; + + CP110_LABEL(syscon0): system-controller@440000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x440000 0x2000>; + + CP110_LABEL(clk): clock { + compatible =3D "marvell,cp110-clock"; + status =3D "disabled"; + #clock-cells =3D <2>; + }; + + CP110_LABEL(gpio1): gpio@100 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x100>; + ngpios =3D <32>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 0= 32>; + interrupt-controller; + interrupts =3D , + , + , + ; + status =3D "disabled"; + }; + + CP110_LABEL(gpio2): gpio@140 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x140>; + ngpios =3D <31>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 3= 2 31>; + interrupt-controller; + interrupts =3D , + , + , + ; + status =3D "disabled"; + }; + }; + + CP110_LABEL(usb3_0): usb3@500000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x500000 0x4000>; + dma-coherent; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(usb3_1): usb3@510000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x510000 0x4000>; + dma-coherent; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(sata0): sata@540000 { + compatible =3D "marvell,armada-8k-ahci", + "generic-ahci"; + reg =3D <0x540000 0x30000>; + dma-coherent; + interrupts =3D ; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(xor0): xor@6a0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(x2core_clk)>; + }; + + CP110_LABEL(xor1): xor@6c0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(x2core_clk)>; + }; + + CP110_LABEL(spi0): spi@700600 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700600 0x50>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(spi1): spi@700680 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700680 0x50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(i2c0): i2c@701000 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(i2c1): i2c@701100 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701100 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart0): serial@702000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702000 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart1): serial@702100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702100 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart2): serial@702200 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702200 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart3): serial@702300 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702300 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(nand_controller): nand@720000 { + /* + * Due to the limitation of the pins available + * this controller is only usable on the CPM + * for A7K and on the CPS for A8K. + */ + compatible =3D "marvell,armada-8k-nand-controller", + "marvell,armada370-nand-controller"; + reg =3D <0x720000 0x54>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(nand_clk)>, + <&CP110_LABEL(x2core_clk)>; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + status =3D "disabled"; + }; + + CP110_LABEL(trng): trng@760000 { + compatible =3D "marvell,armada-8k-rng", + "inside-secure,safexcel-eip76"; + reg =3D <0x760000 0x7d>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(x2core_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "okay"; + }; + + CP110_LABEL(sdhci0): sdhci@780000 { + compatible =3D "marvell,armada-cp110-sdhci"; + reg =3D <0x780000 0x300>; + interrupts =3D ; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL= (core_clk)>; + dma-coherent; + status =3D "disabled"; + }; + + CP110_LABEL(crypto): crypto@800000 { + compatible =3D "inside-secure,safexcel-eip197"; + reg =3D <0x800000 0x200000>; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "mem", "ring0", "ring1", + "ring2", "ring3", "eip"; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(x2core_clk)>, + <&CP110_LABEL(x2core_clk)>; + dma-coherent; + }; + }; + + CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* downstream I/O */ + <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BAS= E(0) 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BA= SE(0) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 2 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* downstream I/O */ + <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BAS= E(1) 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BA= SE(1) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 4 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* downstream I/O */ + <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BAS= E(2) 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BA= SE(2) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 3 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + /* 1 GHz fixed main PLL */ + CP110_LABEL(mainpll): CP110_LABEL(mainpll) { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1000000000>; + }; + + CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + CP110_LABEL(core_clk): CP110_LABEL(core_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <2>; + clock-div =3D <5>; + }; + + CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <2>; + clock-div =3D <5>; + }; + + CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <3>; + }; + + CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <4>; + }; +}; --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73021): https://edk2.groups.io/g/devel/message/73021 Mute This Topic: https://groups.io/mt/81438842/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 21:13:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73023+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73023+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616097509; cv=none; d=zohomail.com; s=zohoarc; b=XngIcuAew3H7L/RHK6nRRKyDTf0OYfMTIEaiBuul9MvhtKcW+Zw0MpPDmfO0e1nJSn9ER0dWDrDv46OQ5IjAfw66B/SeEdtr/YtcJLHpIGVEddkErZFxBu42dywcXAZvxdwqfEUjLLtwfX+3CVuoLoPKMFqheuHhpxegwKu2YI0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616097509; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ESQRe6HapFb2gLsH+N9+0H4BK9eziRleNd4EqzQ7EYA=; b=aFTXNkbBr+j7jubaknkPVa3zE38wVEY3fjWTNyTbuRYx0wy3PcFFSCBchJGkDS9OpdR6tpfLGN4dj8iHricuPmtvSbOXvcEELlwv7E8SemZOgMJlFIi20H+tkCrvfqxXTfLruZQkpPjSrTB9LBDzFKlPf5tIp7Ape+0EiwJuU00= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73023+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616097509700602.3851618180361; Thu, 18 Mar 2021 12:58:29 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id N569YY1788612xJ6xW9w0WHb; Thu, 18 Mar 2021 12:58:29 -0700 X-Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mx.groups.io with SMTP id smtpd.web10.233.1616097507633159418 for ; Thu, 18 Mar 2021 12:58:28 -0700 X-Received: by mail-lf1-f44.google.com with SMTP id z7so6488720lfd.5 for ; Thu, 18 Mar 2021 12:58:27 -0700 (PDT) X-Gm-Message-State: sm4FUhM01uiM4XCSubryKCxex1787277AA= X-Google-Smtp-Source: ABdhPJyL300tkBATjzuJwYaNK3WZRUqsXMDCxIlF4avbmZ6RBhip97os20Jpsr9mLZwL3zzIDiGvoA== X-Received: by 2002:a05:6512:20c7:: with SMTP id u7mr6501564lfr.410.1616097505412; Thu, 18 Mar 2021 12:58:25 -0700 (PDT) X-Received: from gilgamesh.int.semihalf.com (host-193.106.246.138.static.3s.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id b30sm344622lfj.101.2021.03.18.12.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 12:58:24 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ard.biesheuvel@arm.com, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com, jon@solid-run.com Subject: [edk2-devel] [edk2-non-osi PATCH 3/4] Marvell/Armada7k8k: Update device trees Date: Thu, 18 Mar 2021 20:57:56 +0100 Message-Id: <20210318195757.2974226-4-mw@semihalf.com> In-Reply-To: <20210318195757.2974226-1-mw@semihalf.com> References: <20210318195757.2974226-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616097509; bh=tNyFYURAv3aQVwDrlGBeePZBG/gQm2rc5X3SnBovzJE=; h=Cc:Date:From:Reply-To:Subject:To; b=h9TQxZUWrvSdZzAN9TCzNIoCxX4op53Fc0Go+yQ+Oz0JZEfwdgnbR/GK0ksofz9EVyt UFBkxxbWfKbR4CJ0cXzM4LRBY+8+6kor8PYKQtsm+ZKP06Q+7JJT5QXyjaVCBRld3zeCY GuKhAPaSF29gbj9FRMGSOK5eINR/a0/V5CI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This patch updates the Armada7k8k device trees to the version found in Linux v5.11. All previous modifications, compared to vanilla files, are kept, i.e. disabled SPI flashes & RTC, fixed clock tree and generic PCIE for MacchiatoBin board. Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 72 ++- Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 24 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 28 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 57 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 344 +------= ---- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi | 374 +++++++= +++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 36 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 56 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 38 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 66 ++- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 262 +------- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807-quad.dtsi | 93 +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi | 33 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi | 470 +++++++= ++++++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 3 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 556 +------= ---------- Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp115.dtsi | 12 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi | 627 +++++++= +++++++++++++ 18 files changed, 1921 insertions(+), 1230 deletions(-) create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin= .dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807-quad= .dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp115.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts index f5878ef..a578b5a 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts @@ -7,9 +7,6 @@ =20 #include "armada-7040.dtsi" =20 -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - / { model =3D "Marvell Armada 7040 DB board"; compatible =3D "marvell,armada7040-db", "marvell,armada7040", @@ -30,6 +27,32 @@ ethernet2 =3D &cp0_eth2; }; =20 + cp0_exp_usb3_0_current_regulator: gpio-regulator { + compatible =3D "regulator-gpio"; + regulator-name =3D "cp0-usb3-0-current-regulator"; + regulator-type =3D "current"; + regulator-min-microamp =3D <500000>; + regulator-max-microamp =3D <900000>; + gpios =3D <&expander0 4 GPIO_ACTIVE_HIGH>; + states =3D <500000 0x0 + 900000 0x1>; + enable-active-high; + gpios-states =3D <0>; + }; + + cp0_exp_usb3_1_current_regulator: gpio-regulator { + compatible =3D "regulator-gpio"; + regulator-name =3D "cp0-usb3-1-current-regulator"; + regulator-type =3D "current"; + regulator-min-microamp =3D <500000>; + regulator-max-microamp =3D <900000>; + gpios =3D <&expander0 5 GPIO_ACTIVE_HIGH>; + states =3D <500000 0x0 + 900000 0x1>; + enable-active-high; + gpios-states =3D <0>; + }; + cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { compatible =3D "regulator-fixed"; regulator-name =3D "usb3h0-vbus"; @@ -37,6 +60,7 @@ regulator-max-microvolt =3D <5000000>; enable-active-high; gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&cp0_exp_usb3_0_current_regulator>; }; =20 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { @@ -46,16 +70,7 @@ regulator-max-microvolt =3D <5000000>; enable-active-high; gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; - }; - - cp0_usb3_0_phy: cp0-usb3-0-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp0_reg_usb3_0_vbus>; - }; - - cp0_usb3_1_phy: cp0-usb3-1-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp0_reg_usb3_1_vbus>; + vin-supply =3D <&cp0_exp_usb3_1_current_regulator>; }; }; =20 @@ -68,8 +83,6 @@ status =3D "okay"; =20 spi-flash@0 { - #address-cells =3D <1>; - #size-cells =3D <1>; compatible =3D "jedec,spi-nor"; reg =3D <0>; spi-max-frequency =3D <10000000>; @@ -100,6 +113,8 @@ =20 &cp0_pcie2 { status =3D "okay"; + phys =3D <&cp0_comphy5 2>; + phy-names =3D "cp0-pcie2-x1-phy"; }; =20 &cp0_i2c0 { @@ -171,8 +186,6 @@ status =3D "disabled"; =20 spi-flash@0 { - #address-cells =3D <0x1>; - #size-cells =3D <0x1>; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-max-frequency =3D <20000000>; @@ -197,15 +210,36 @@ =20 &cp0_sata0 { status =3D "okay"; + + sata-port@1 { + phys =3D <&cp0_comphy3 1>; + phy-names =3D "cp0-sata0-1-phy"; + }; +}; + +&cp0_comphy1 { + cp0_usbh0_con: connector { + compatible =3D "usb-a-connector"; + phy-supply =3D <&cp0_reg_usb3_0_vbus>; + }; }; =20 &cp0_usb3_0 { - usb-phy =3D <&cp0_usb3_0_phy>; + phys =3D <&cp0_comphy1 0>; + phy-names =3D "cp0-usb3h0-comphy"; status =3D "okay"; }; =20 +&cp0_comphy4 { + cp0_usbh1_con: connector { + compatible =3D "usb-a-connector"; + phy-supply =3D <&cp0_reg_usb3_1_vbus>; + }; +}; + &cp0_usb3_1 { - usb-phy =3D <&cp0_usb3_1_phy>; + phys =3D <&cp0_comphy4 1>; + phy-names =3D "cp0-usb3h1-comphy"; status =3D "okay"; }; =20 diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi index 03109b2..30c2e4e 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi @@ -14,3 +14,27 @@ compatible =3D "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; }; + +&cp0_pcie0 { + iommu-map =3D + <0x0 &smmu 0x480 0x20>, + <0x100 &smmu 0x4a0 0x20>, + <0x200 &smmu 0x4c0 0x20>; + iommu-map-mask =3D <0x031f>; +}; + +&cp0_sata0 { + iommus =3D <&smmu 0x444>; +}; + +&cp0_sdhci0 { + iommus =3D <&smmu 0x445>; +}; + +&cp0_usb3_0 { + iommus =3D <&smmu 0x440>; +}; + +&cp0_usb3_1 { + iommus =3D <&smmu 0x441>; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi index 78f9d87..0fdcb35 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi @@ -17,23 +17,23 @@ /* * Instantiate the CP110 */ -#define CP110_NAME cp0 -#define CP110_BASE f2000000 -#define CP110_PCIE_IO_BASE 0xf9000000 -#define CP110_PCIE_MEM_BASE 0xf6000000 -#define CP110_PCIE0_BASE f2600000 -#define CP110_PCIE1_BASE f2620000 -#define CP110_PCIE2_BASE f2640000 +#define CP11X_NAME cp0 +#define CP11X_BASE f2000000 +#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +#define CP11X_PCIE0_BASE f2600000 +#define CP11X_PCIE1_BASE f2620000 +#define CP11X_PCIE2_BASE f2640000 =20 #include "armada-cp110.dtsi" =20 -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE_IO_BASE -#undef CP110_PCIE_MEM_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE +#undef CP11X_NAME +#undef CP11X_BASE +#undef CP11X_PCIEx_MEM_BASE +#undef CP11X_PCIEx_MEM_SIZE +#undef CP11X_PCIE0_BASE +#undef CP11X_PCIE1_BASE +#undef CP11X_PCIE2_BASE =20 &cp0_gpio1 { status =3D "okay"; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts index e813922..9fea84f 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts @@ -7,9 +7,6 @@ =20 #include "armada-8040.dtsi" =20 -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - / { model =3D "Marvell Armada 8040 DB board"; compatible =3D "marvell,armada8040-db", "marvell,armada8040", @@ -29,6 +26,8 @@ ethernet1 =3D &cp0_eth2; ethernet2 =3D &cp1_eth0; ethernet3 =3D &cp1_eth1; + i2c1 =3D &cp0_i2c0; + i2c2 =3D &cp1_i2c0; }; =20 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { @@ -54,11 +53,6 @@ vcc-supply =3D <&cp0_reg_usb3_0_vbus>; }; =20 - cp0_usb3_1_phy: cp0-usb3-1-phy { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&cp0_reg_usb3_1_vbus>; - }; - cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { compatible =3D "regulator-fixed"; regulator-name =3D "cp1-usb3h0-vbus"; @@ -74,17 +68,10 @@ }; }; =20 -&i2c0 { - status =3D "okay"; - clock-frequency =3D <100000>; -}; - &spi0 { status =3D "okay"; =20 spi-flash@0 { - #address-cells =3D <1>; - #size-cells =3D <1>; compatible =3D "jedec,spi-nor"; reg =3D <0>; spi-max-frequency =3D <10000000>; @@ -115,11 +102,15 @@ =20 /* CON6 on CP0 expansion */ &cp0_pcie0 { + phys =3D <&cp0_comphy0 0>; + phy-names =3D "cp0-pcie0-x1-phy"; status =3D "okay"; }; =20 /* CON5 on CP0 expansion */ &cp0_pcie2 { + phys =3D <&cp0_comphy5 2>; + phy-names =3D "cp0-pcie2-x1-phy"; status =3D "okay"; }; =20 @@ -150,6 +141,15 @@ /* CON4 on CP0 expansion */ &cp0_sata0 { status =3D "okay"; + + sata-port@0 { + phys =3D <&cp0_comphy1 0>; + phy-names =3D "cp0-sata0-0-phy"; + }; + sata-port@1 { + phys =3D <&cp0_comphy3 1>; + phy-names =3D "cp0-sata0-1-phy"; + }; }; =20 /* CON9 on CP0 expansion */ @@ -158,9 +158,17 @@ status =3D "okay"; }; =20 +&cp0_comphy4 { + cp0_usbh1_con: connector { + compatible =3D "usb-a-connector"; + phy-supply =3D <&cp0_reg_usb3_1_vbus>; + }; +}; + /* CON10 on CP0 expansion */ &cp0_usb3_1 { - usb-phy =3D <&cp0_usb3_1_phy>; + phys =3D <&cp0_comphy4 1>; + phy-names =3D "cp0-usb3h1-comphy"; status =3D "okay"; }; =20 @@ -194,16 +202,22 @@ =20 /* CON6 on CP1 expansion */ &cp1_pcie0 { + phys =3D <&cp1_comphy0 0>; + phy-names =3D "cp1-pcie0-x1-phy"; status =3D "okay"; }; =20 /* CON7 on CP1 expansion */ &cp1_pcie1 { + phys =3D <&cp1_comphy4 1>; + phy-names =3D "cp1-pcie1-x1-phy"; status =3D "okay"; }; =20 /* CON5 on CP1 expansion */ &cp1_pcie2 { + phys =3D <&cp1_comphy5 2>; + phy-names =3D "cp1-pcie2-x1-phy"; status =3D "okay"; }; =20 @@ -216,8 +230,6 @@ status =3D "disabled"; =20 spi-flash@0 { - #address-cells =3D <0x1>; - #size-cells =3D <0x1>; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-max-frequency =3D <20000000>; @@ -282,6 +294,15 @@ /* CON4 on CP1 expansion */ &cp1_sata0 { status =3D "okay"; + + sata-port@0 { + phys =3D <&cp1_comphy1 0>; + phy-names =3D "cp1-sata0-0-phy"; + }; + sata-port@1 { + phys =3D <&cp1_comphy3 1>; + phy-names =3D "cp1-sata0-1-phy"; + }; }; =20 /* CON9 on CP1 expansion */ diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/= Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts index d9c9348..740bdaf 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts @@ -5,233 +5,13 @@ * Device Tree file for MACCHIATOBin Armada 8040 community board platform */ =20 -#include "armada-8040.dtsi" - -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 +#include "armada-8040-mcbin.dtsi" =20 / { - model =3D "Marvell 8040 MACCHIATOBin"; - compatible =3D "marvell,armada8040-mcbin", "marvell,armada8040", + model =3D "Marvell 8040 MACCHIATOBin Double-shot"; + compatible =3D "marvell,armada8040-mcbin-doubleshot", + "marvell,armada8040-mcbin", "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806= "; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - memory@0 { - device_type =3D "memory"; - reg =3D <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 =3D &cp0_eth0; - ethernet1 =3D &cp1_eth0; - ethernet2 =3D &cp1_eth1; - ethernet3 =3D &cp1_eth2; - }; - - /* Regulator labels correspond with schematics */ - v_3_3: regulator-3-3v { - compatible =3D "regulator-fixed"; - regulator-name =3D "v_3_3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - status =3D "okay"; - }; - - v_vddo_h: regulator-1-8v { - compatible =3D "regulator-fixed"; - regulator-name =3D "v_vddo_h"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-always-on; - status =3D "okay"; - }; - - v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { - compatible =3D "regulator-fixed"; - enable-active-high; - gpio =3D <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_xhci_vbus_pins>; - regulator-name =3D "v_5v0_usb3_hst_vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - status =3D "okay"; - }; - - usb3h0_phy: usb3_phy0 { - compatible =3D "usb-nop-xceiv"; - vcc-supply =3D <&v_5v0_usb3_hst_vbus>; - }; - - sfp_eth0: sfp-eth0 { - /* CON15,16 - CPM lane 4 */ - compatible =3D "sff,sfp"; - i2c-bus =3D <&sfpp0_i2c>; - los-gpio =3D <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio =3D <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; - tx-disable-gpio =3D <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; - tx-fault-gpio =3D <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_sfpp0_pins>; - }; - - sfp_eth1: sfp-eth1 { - /* CON17,18 - CPS lane 4 */ - compatible =3D "sff,sfp"; - i2c-bus =3D <&sfpp1_i2c>; - los-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; - mod-def0-gpio =3D <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; - tx-disable-gpio =3D <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; - tx-fault-gpio =3D <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_sfpp1_pins &cp0_sfpp1_pins>; - }; - - sfp_eth3: sfp-eth3 { - /* CON3,4 - CPS lane 5 */ - compatible =3D "sff,sfp"; - i2c-bus =3D <&sfp_1g_i2c>; - los-gpio =3D <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio =3D <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; - tx-disable-gpio =3D <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; - tx-fault-gpio =3D <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; - }; -}; - -&uart0 { - status =3D "okay"; - pinctrl-0 =3D <&uart0_pins>; - pinctrl-names =3D "default"; -}; - -&ap_sdhci0 { - bus-width =3D <8>; - /* - * Not stable in HS modes - phy needs "more calibration", so add - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. - */ - marvell,xenon-phy-slow-mode; - no-1-8-v; - no-sd; - no-sdio; - non-removable; - status =3D "okay"; - vqmmc-supply =3D <&v_vddo_h>; -}; - -&cp0_i2c0 { - clock-frequency =3D <100000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_i2c0_pins>; - status =3D "okay"; -}; - -&cp0_i2c1 { - clock-frequency =3D <100000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_i2c1_pins>; - status =3D "okay"; - - i2c-switch@70 { - compatible =3D "nxp,pca9548"; - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0x70>; - - sfpp0_i2c: i2c@0 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0>; - }; - sfpp1_i2c: i2c@1 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <1>; - }; - sfp_1g_i2c: i2c@2 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <2>; - }; - }; -}; - -/* J25 UART header */ -&cp0_uart1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_uart1_pins>; - status =3D "okay"; -}; - -&cp0_mdio { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_ge_mdio_pins>; - status =3D "okay"; - - ge_phy: ethernet-phy@0 { - reg =3D <0>; - }; -}; - -&cp0_pcie0 { - compatible =3D "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam"; - reg =3D <0 0xe0000000 0 0xff00000>; - bus-range =3D <0 0xfe>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_pcie_pins>; - num-lanes =3D <4>; - num-viewport =3D <8>; - reset-gpio =3D <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; - ranges =3D <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000= >, - <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>, - <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>; - status =3D "okay"; -}; - -&cp0_pinctrl { - cp0_ge_mdio_pins: ge-mdio-pins { - marvell,pins =3D "mpp32", "mpp34"; - marvell,function =3D "ge"; - }; - cp0_i2c1_pins: i2c1-pins { - marvell,pins =3D "mpp35", "mpp36"; - marvell,function =3D "i2c1"; - }; - cp0_i2c0_pins: i2c0-pins { - marvell,pins =3D "mpp37", "mpp38"; - marvell,function =3D "i2c0"; - }; - cp0_uart1_pins: uart1-pins { - marvell,pins =3D "mpp40", "mpp41"; - marvell,function =3D "uart1"; - }; - cp0_xhci_vbus_pins: xhci0-vbus-pins { - marvell,pins =3D "mpp47"; - marvell,function =3D "gpio"; - }; - cp0_sfp_1g_pins: sfp-1g-pins { - marvell,pins =3D "mpp51", "mpp53", "mpp54"; - marvell,function =3D "gpio"; - }; - cp0_pcie_pins: pcie-pins { - marvell,pins =3D "mpp52"; - marvell,function =3D "gpio"; - }; - cp0_sdhci_pins: sdhci-pins { - marvell,pins =3D "mpp55", "mpp56", "mpp57", "mpp58", "mpp5= 9", - "mpp60", "mpp61"; - marvell,function =3D "sdio"; - }; - cp0_sfpp1_pins: sfpp1-pins { - marvell,pins =3D "mpp62"; - marvell,function =3D "gpio"; - }; }; =20 &cp0_xmdio { @@ -250,128 +30,16 @@ }; }; =20 -&cp0_ethernet { - status =3D "okay"; -}; - &cp0_eth0 { status =3D "okay"; /* Network PHY */ phy =3D <&phy0>; - phy-mode =3D "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp0_comphy4 0>; -}; - -&cp0_sata0 { - /* CPM Lane 0 - U29 */ - status =3D "okay"; -}; - -&cp0_sdhci0 { - /* U6 */ - broken-cd; - bus-width =3D <4>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_sdhci_pins>; - status =3D "okay"; - vqmmc-supply =3D <&v_3_3>; -}; - -&cp0_usb3_0 { - /* J38? - USB2.0 only */ - status =3D "okay"; -}; - -&cp0_usb3_1 { - /* J38? - USB2.0 only */ - status =3D "okay"; -}; - -&cp1_ethernet { - status =3D "okay"; + phy-mode =3D "10gbase-r"; }; =20 &cp1_eth0 { status =3D "okay"; /* Network PHY */ phy =3D <&phy8>; - phy-mode =3D "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy4 0>; -}; - -&cp1_eth1 { - /* CPS Lane 0 - J5 (Gigabit RJ45) */ - status =3D "okay"; - /* Network PHY */ - phy =3D <&ge_phy>; - phy-mode =3D "sgmii"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy0 1>; -}; - -&cp1_eth2 { - /* CPS Lane 5 */ - status =3D "okay"; - /* Network PHY */ - phy-mode =3D "2500base-x"; - managed =3D "in-band-status"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy5 2>; - sfp =3D <&sfp_eth3>; -}; - -&cp1_pinctrl { - cp1_sfpp1_pins: sfpp1-pins { - marvell,pins =3D "mpp8", "mpp10", "mpp11"; - marvell,function =3D "gpio"; - }; - cp1_spi1_pins: spi1-pins { - marvell,pins =3D "mpp12", "mpp13", "mpp14", "mpp15", "mpp1= 6"; - marvell,function =3D "spi1"; - }; - cp1_uart0_pins: uart0-pins { - marvell,pins =3D "mpp6", "mpp7"; - marvell,function =3D "uart0"; - }; - cp1_sfp_1g_pins: sfp-1g-pins { - marvell,pins =3D "mpp24"; - marvell,function =3D "gpio"; - }; - cp1_sfpp0_pins: sfpp0-pins { - marvell,pins =3D "mpp26", "mpp27", "mpp28", "mpp29"; - marvell,function =3D "gpio"; - }; -}; - -/* J27 UART header */ -&cp1_uart0 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_uart0_pins>; - status =3D "okay"; -}; - -&cp1_sata0 { - /* CPS Lane 1 - U32 */ - /* CPS Lane 3 - U31 */ - status =3D "okay"; -}; - -&cp1_spi1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp1_spi1_pins>; - status =3D "disabled"; - - spi-flash@0 { - compatible =3D "st,w25q32"; - spi-max-frequency =3D <50000000>; - reg =3D <0>; - }; -}; - -&cp1_usb3_0 { - /* CPS Lane 2 - CON7 */ - usb-phy =3D <&usb3h0_phy>; - status =3D "okay"; + phy-mode =3D "10gbase-r"; }; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi new file mode 100644 index 0000000..970e875 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for MACCHIATOBin Armada 8040 community board platform + */ + +#include "armada-8040.dtsi" + +/ { + model =3D "Marvell 8040 MACCHIATOBin"; + compatible =3D "marvell,armada8040-mcbin", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806= "; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x80000000>; + }; + + aliases { + ethernet0 =3D &cp0_eth0; + ethernet1 =3D &cp1_eth0; + ethernet2 =3D &cp1_eth1; + ethernet3 =3D &cp1_eth2; + }; + + /* Regulator labels correspond with schematics */ + v_3_3: regulator-3-3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "v_3_3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + status =3D "okay"; + }; + + v_vddo_h: regulator-1-8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "v_vddo_h"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + status =3D "okay"; + }; + + v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_xhci_vbus_pins>; + regulator-name =3D "v_5v0_usb3_hst_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + status =3D "okay"; + }; + + sfp_eth0: sfp-eth0 { + /* CON15,16 - CPM lane 4 */ + compatible =3D "sff,sfp"; + i2c-bus =3D <&sfpp0_i2c>; + los-gpio =3D <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_sfpp0_pins>; + maximum-power-milliwatt =3D <2000>; + }; + + sfp_eth1: sfp-eth1 { + /* CON17,18 - CPS lane 4 */ + compatible =3D "sff,sfp"; + i2c-bus =3D <&sfpp1_i2c>; + los-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_sfpp1_pins &cp0_sfpp1_pins>; + maximum-power-milliwatt =3D <2000>; + }; + + sfp_eth3: sfp-eth3 { + /* CON13,14 - CPS lane 5 */ + compatible =3D "sff,sfp"; + i2c-bus =3D <&sfp_1g_i2c>; + los-gpio =3D <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; + maximum-power-milliwatt =3D <2000>; + }; +}; + +&uart0 { + status =3D "okay"; + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; +}; + +&ap_sdhci0 { + bus-width =3D <8>; + /* + * Not stable in HS modes - phy needs "more calibration", so add + * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. + */ + marvell,xenon-phy-slow-mode; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + status =3D "okay"; + vqmmc-supply =3D <&v_vddo_h>; +}; + +&cp0_i2c0 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_i2c0_pins>; + status =3D "okay"; +}; + +&cp0_i2c1 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_i2c1_pins>; + status =3D "okay"; + + i2c-switch@70 { + compatible =3D "nxp,pca9548"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + + sfpp0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + sfpp1_i2c: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + sfp_1g_i2c: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + }; +}; + +/* J25 UART header */ +&cp0_uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_uart1_pins>; + status =3D "okay"; +}; + +&cp0_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_ge_mdio_pins>; + status =3D "okay"; + + ge_phy: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&cp0_pcie0 { + compatible =3D "marvell,armada8k-pcie-ecam", "pci-host-ecam-generi= c"; + reg =3D <0 0xe0000000 0 0xff00000>; + bus-range =3D <0 0xfe>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_pcie_pins>; + num-lanes =3D <4>; + num-viewport =3D <8>; + reset-gpios =3D <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; + ranges =3D <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000= >, + <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>, + <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>; + phys =3D <&cp0_comphy0 0>, <&cp0_comphy1 0>, + <&cp0_comphy2 0>, <&cp0_comphy3 0>; + phy-names =3D "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy", + "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy"; + status =3D "okay"; +}; + +&cp0_pinctrl { + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins =3D "mpp32", "mpp34"; + marvell,function =3D "ge"; + }; + cp0_i2c1_pins: i2c1-pins { + marvell,pins =3D "mpp35", "mpp36"; + marvell,function =3D "i2c1"; + }; + cp0_i2c0_pins: i2c0-pins { + marvell,pins =3D "mpp37", "mpp38"; + marvell,function =3D "i2c0"; + }; + cp0_uart1_pins: uart1-pins { + marvell,pins =3D "mpp40", "mpp41"; + marvell,function =3D "uart1"; + }; + cp0_xhci_vbus_pins: xhci0-vbus-pins { + marvell,pins =3D "mpp47"; + marvell,function =3D "gpio"; + }; + cp0_sfp_1g_pins: sfp-1g-pins { + marvell,pins =3D "mpp51", "mpp53", "mpp54"; + marvell,function =3D "gpio"; + }; + cp0_pcie_pins: pcie-pins { + marvell,pins =3D "mpp52"; + marvell,function =3D "gpio"; + }; + cp0_sdhci_pins: sdhci-pins { + marvell,pins =3D "mpp55", "mpp56", "mpp57", "mpp58", "mpp5= 9", + "mpp60", "mpp61"; + marvell,function =3D "sdio"; + }; + cp0_sfpp1_pins: sfpp1-pins { + marvell,pins =3D "mpp62"; + marvell,function =3D "gpio"; + }; +}; + +&cp0_ethernet { + status =3D "okay"; +}; + +&cp0_eth0 { + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy4 0>; +}; + +&cp0_sata0 { + status =3D "okay"; + + /* CPM Lane 5 - U29 */ + sata-port@1 { + phys =3D <&cp0_comphy5 1>; + phy-names =3D "cp0-sata0-1-phy"; + }; +}; + +&cp0_sdhci0 { + /* U6 */ + broken-cd; + bus-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_sdhci_pins>; + status =3D "okay"; + vqmmc-supply =3D <&v_3_3>; +}; + +&cp0_usb3_0 { + /* J38? - USB2.0 only */ + status =3D "okay"; +}; + +&cp0_usb3_1 { + /* J38? - USB2.0 only */ + status =3D "okay"; +}; + +&cp1_ethernet { + status =3D "okay"; +}; + +&cp1_eth0 { + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy4 0>; +}; + +&cp1_eth1 { + /* CPS Lane 0 - J5 (Gigabit RJ45) */ + status =3D "okay"; + /* Network PHY */ + phy =3D <&ge_phy>; + phy-mode =3D "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy0 1>; +}; + +&cp1_eth2 { + /* CPS Lane 5 */ + status =3D "okay"; + /* Network PHY */ + phy-mode =3D "2500base-x"; + managed =3D "in-band-status"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy5 2>; + sfp =3D <&sfp_eth3>; +}; + +&cp1_pinctrl { + cp1_sfpp1_pins: sfpp1-pins { + marvell,pins =3D "mpp8", "mpp10", "mpp11"; + marvell,function =3D "gpio"; + }; + cp1_spi1_pins: spi1-pins { + marvell,pins =3D "mpp12", "mpp13", "mpp14", "mpp15", "mpp1= 6"; + marvell,function =3D "spi1"; + }; + cp1_uart0_pins: uart0-pins { + marvell,pins =3D "mpp6", "mpp7"; + marvell,function =3D "uart0"; + }; + cp1_sfp_1g_pins: sfp-1g-pins { + marvell,pins =3D "mpp24"; + marvell,function =3D "gpio"; + }; + cp1_sfpp0_pins: sfpp0-pins { + marvell,pins =3D "mpp26", "mpp27", "mpp28", "mpp29"; + marvell,function =3D "gpio"; + }; +}; + +/* J27 UART header */ +&cp1_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_uart0_pins>; + status =3D "okay"; +}; + +&cp1_sata0 { + status =3D "okay"; + + /* CPS Lane 1 - U32 */ + sata-port@0 { + phys =3D <&cp1_comphy1 0>; + phy-names =3D "cp1-sata0-0-phy"; + }; + + /* CPS Lane 3 - U31 */ + sata-port@1 { + phys =3D <&cp1_comphy3 1>; + phy-names =3D "cp1-sata0-1-phy"; + }; +}; + +&cp1_spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_spi1_pins>; + + spi-flash@0 { + compatible =3D "st,w25q32"; + spi-max-frequency =3D <50000000>; + reg =3D <0>; + }; +}; + +&cp1_comphy2 { + cp1_usbh0_con: connector { + compatible =3D "usb-a-connector"; + phy-supply =3D <&v_5v0_usb3_hst_vbus>; + }; +}; + +&cp1_usb3_0 { + /* CPS Lane 2 - CON7 */ + phys =3D <&cp1_comphy2 0>; + phy-names =3D "cp1-usb3h0-comphy"; + status =3D "okay"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi index 784ef3f..0a676df 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi @@ -15,6 +15,14 @@ "marvell,armada-ap806"; }; =20 +&cp0_pcie0 { + iommu-map =3D + <0x0 &smmu 0x480 0x20>, + <0x100 &smmu 0x4a0 0x20>, + <0x200 &smmu 0x4c0 0x20>; + iommu-map-mask =3D <0x031f>; +}; + /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock * in CP master is not connected (by package) to the oscillator. So * disable it. However, the RTC clock in CP slave is connected to the @@ -23,3 +31,31 @@ &cp0_rtc { status =3D "disabled"; }; + +&cp0_sata0 { + iommus =3D <&smmu 0x444>; +}; + +&cp0_sdhci0 { + iommus =3D <&smmu 0x445>; +}; + +&cp0_usb3_0 { + iommus =3D <&smmu 0x440>; +}; + +&cp0_usb3_1 { + iommus =3D <&smmu 0x441>; +}; + +&cp1_sata0 { + iommus =3D <&smmu 0x454>; +}; + +&cp1_usb3_0 { + iommus =3D <&smmu 0x450>; +}; + +&cp1_usb3_1 { + iommus =3D <&smmu 0x451>; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi index 81967e2..2ee35fa 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi @@ -19,44 +19,44 @@ /* * Instantiate the master CP110 */ -#define CP110_NAME cp0 -#define CP110_BASE f2000000 -#define CP110_PCIE_IO_BASE 0xf9000000 -#define CP110_PCIE_MEM_BASE 0xf6000000 -#define CP110_PCIE0_BASE f2600000 -#define CP110_PCIE1_BASE f2620000 -#define CP110_PCIE2_BASE f2640000 +#define CP11X_NAME cp0 +#define CP11X_BASE f2000000 +#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +#define CP11X_PCIE0_BASE f2600000 +#define CP11X_PCIE1_BASE f2620000 +#define CP11X_PCIE2_BASE f2640000 =20 #include "armada-cp110.dtsi" =20 -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE_IO_BASE -#undef CP110_PCIE_MEM_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE +#undef CP11X_NAME +#undef CP11X_BASE +#undef CP11X_PCIEx_MEM_BASE +#undef CP11X_PCIEx_MEM_SIZE +#undef CP11X_PCIE0_BASE +#undef CP11X_PCIE1_BASE +#undef CP11X_PCIE2_BASE =20 /* * Instantiate the slave CP110 */ -#define CP110_NAME cp1 -#define CP110_BASE f4000000 -#define CP110_PCIE_IO_BASE 0xfd000000 -#define CP110_PCIE_MEM_BASE 0xfa000000 -#define CP110_PCIE0_BASE f4600000 -#define CP110_PCIE1_BASE f4620000 -#define CP110_PCIE2_BASE f4640000 +#define CP11X_NAME cp1 +#define CP11X_BASE f4000000 +#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000)) +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +#define CP11X_PCIE0_BASE f4600000 +#define CP11X_PCIE1_BASE f4620000 +#define CP11X_PCIE2_BASE f4640000 =20 #include "armada-cp110.dtsi" =20 -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE_IO_BASE -#undef CP110_PCIE_MEM_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE +#undef CP11X_NAME +#undef CP11X_BASE +#undef CP11X_PCIEx_MEM_BASE +#undef CP11X_PCIEx_MEM_SIZE +#undef CP11X_PCIE0_BASE +#undef CP11X_PCIE1_BASE +#undef CP11X_PCIE2_BASE =20 /* The 80x0 has two CP blocks, but uses only one block from each. */ &cp1_gpio1 { diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi index 5985843..0cd8e7e 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi @@ -15,17 +15,47 @@ #address-cells =3D <1>; #size-cells =3D <0>; =20 - cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; + compatible =3D "arm,cortex-a72"; reg =3D <0x000>; enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 0>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2>; }; - cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; + compatible =3D "arm,cortex-a72"; reg =3D <0x001>; enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 0>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2>; }; + + l2: l2-cache { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; + }; + + thermal-zones { + /delete-node/ ap-thermal-cpu2; + /delete-node/ ap-thermal-cpu3; }; }; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi index bae0ed9..3b48a13 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi @@ -15,29 +15,79 @@ #address-cells =3D <1>; #size-cells =3D <0>; =20 - cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; + compatible =3D "arm,cortex-a72"; reg =3D <0x000>; enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 0>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_0>; }; - cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; + compatible =3D "arm,cortex-a72"; reg =3D <0x001>; enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 0>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_0>; }; - cpu@100 { + cpu2: cpu@100 { device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; + compatible =3D "arm,cortex-a72"; reg =3D <0x100>; enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 1>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; }; - cpu@101 { + cpu3: cpu@101 { device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; + compatible =3D "arm,cortex-a72"; reg =3D <0x101>; enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 1>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; }; }; }; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi index 66124bf..59641de 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi @@ -5,260 +5,26 @@ * Device Tree file for Marvell Armada AP806. */ =20 -#define IRQ_TYPE_LEVEL_HIGH (1 << 2) -#define IRQ_TYPE_LEVEL_LOW (1 << 3) - -#define GIC_SPI 0 -#define GIC_PPI 1 - -#define GIC_CPU_MASK_RAW(x) ((x) << 8) -#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) - -/dts-v1/; +#define AP_NAME ap806 +#include "armada-ap80x.dtsi" =20 / { model =3D "Marvell Armada AP806"; compatible =3D "marvell,armada-ap806"; - #address-cells =3D <2>; - #size-cells =3D <2>; - - aliases { - serial0 =3D &uart0; - serial1 =3D &uart1; - gpio0 =3D &ap_gpio; - spi0 =3D &spi0; - }; +}; =20 - psci { - compatible =3D "arm,psci-0.2"; - method =3D "smc"; +&ap_syscon0 { + ap_clk: clock { + compatible =3D "marvell,ap806-clock"; + #clock-cells =3D <1>; }; +}; =20 - ap806 { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "simple-bus"; - interrupt-parent =3D <&gic>; - ranges; - - config-space@f0000000 { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "simple-bus"; - ranges =3D <0x0 0x0 0xf0000000 0x1000000>; - - gic: interrupt-controller@210000 { - compatible =3D "arm,gic-400"; - #interrupt-cells =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - interrupt-controller; - interrupts =3D ; - reg =3D <0x210000 0x10000>, - <0x220000 0x20000>, - <0x240000 0x20000>, - <0x260000 0x20000>; - - gic_v2m0: v2m@280000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x280000 0x1000>; - arm,msi-base-spi =3D <160>; - arm,msi-num-spis =3D <32>; - }; - gic_v2m1: v2m@290000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x290000 0x1000>; - arm,msi-base-spi =3D <192>; - arm,msi-num-spis =3D <32>; - }; - gic_v2m2: v2m@2a0000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x2a0000 0x1000>; - arm,msi-base-spi =3D <224>; - arm,msi-num-spis =3D <32>; - }; - gic_v2m3: v2m@2b0000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x2b0000 0x1000>; - arm,msi-base-spi =3D <256>; - arm,msi-num-spis =3D <32>; - }; - }; - - timer { - compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; - }; - - pmu { - compatible =3D "arm,cortex-a72-pmu"; - interrupt-parent =3D <&pic>; - interrupts =3D <17>; - }; - - odmi: odmi@300000 { - compatible =3D "marvell,odmi-controller"; - interrupt-controller; - msi-controller; - marvell,odmi-frames =3D <4>; - reg =3D <0x300000 0x4000>, - <0x304000 0x4000>, - <0x308000 0x4000>, - <0x30C000 0x4000>; - marvell,spi-base =3D <128>, <136>, <144>, = <152>; - }; - - gicp: gicp@3f0040 { - compatible =3D "marvell,ap806-gicp"; - reg =3D <0x3f0040 0x10>; - marvell,spi-ranges =3D <64 64>, <288 64>; - msi-controller; - }; - - pic: interrupt-controller@3f0100 { - compatible =3D "marvell,armada-8k-pic"; - reg =3D <0x3f0100 0x10>; - #interrupt-cells =3D <1>; - interrupt-controller; - interrupts =3D ; - }; - - xor@400000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x400000 0x1000>, - <0x410000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - xor@420000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x420000 0x1000>, - <0x430000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - xor@440000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x440000 0x1000>, - <0x450000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - xor@460000 { - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; - reg =3D <0x460000 0x1000>, - <0x470000 0x1000>; - msi-parent =3D <&gic_v2m0>; - clocks =3D <&ap_clk 3>; - dma-coherent; - }; - - spi0: spi@510600 { - compatible =3D "marvell,armada-380-spi"; - reg =3D <0x510600 0x50>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - }; - - i2c0: i2c@511000 { - compatible =3D "marvell,mv78230-i2c"; - reg =3D <0x511000 0x20>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - timeout-ms =3D <1000>; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - }; - - uart0: serial@512000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x512000 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - }; - - uart1: serial@512100 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x512100 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clocks =3D <&ap_clk 3>; - status =3D "disabled"; - - }; - - watchdog: watchdog@610000 { - compatible =3D "arm,sbsa-gwdt"; - reg =3D <0x610000 0x1000>, <0x600000 0x100= 0>; - interrupts =3D ; - }; - - ap_sdhci0: sdhci@6e0000 { - compatible =3D "marvell,armada-ap806-sdhci= "; - reg =3D <0x6e0000 0x300>; - interrupts =3D ; - clock-names =3D "core"; - clocks =3D <&ap_clk 4>; - dma-coherent; - marvell,xenon-phy-slow-mode; - status =3D "disabled"; - }; - - ap_syscon: system-controller@6f4000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x6f4000 0x2000>; - - ap_clk: clock { - compatible =3D "marvell,ap806-cloc= k"; - #clock-cells =3D <1>; - }; - - ap_pinctrl: pinctrl { - compatible =3D "marvell,ap806-pinc= trl"; - - uart0_pins: uart0-pins { - marvell,pins =3D "mpp11", = "mpp19"; - marvell,function =3D "uart= 0"; - }; - }; - - ap_gpio: gpio@1040 { - compatible =3D "marvell,armada-8k-= gpio"; - offset =3D <0x1040>; - ngpios =3D <20>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>; - }; - }; - - ap_thermal: thermal@6f808c { - compatible =3D "marvell,armada-ap806-therm= al"; - reg =3D <0x6f808c 0x4>, - <0x6f8084 0x8>; - }; - }; +&ap_syscon1 { + cpu_clk: clock-cpu@278 { + compatible =3D "marvell,ap806-cpu-clock"; + clocks =3D <&ap_clk 0>, <&ap_clk 1>; + #clock-cells =3D <1>; + reg =3D <0x278 0xa30>; }; }; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807-quad.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807-quad.dtsi new file mode 100644 index 0000000..6222569 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807-quad.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada AP807 Quad + * + * Copyright (C) 2019 Marvell Technology Group Ltd. + */ + +#include "armada-ap807.dtsi" + +/ { + model =3D "Marvell Armada AP807 Quad"; + compatible =3D "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x000>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 0>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_0>; + }; + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x001>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 0>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_0>; + }; + cpu2: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x100>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 1>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + }; + cpu3: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x101>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 1>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi new file mode 100644 index 0000000..b42dc3a --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada AP807 + * + * Copyright (C) 2019 Marvell Technology Group Ltd. + */ + +#define AP_NAME ap807 +#include "armada-ap80x.dtsi" + +/ { + model =3D "Marvell Armada AP807"; + compatible =3D "marvell,armada-ap807"; +}; + +&ap_syscon0 { + ap_clk: clock { + compatible =3D "marvell,ap807-clock"; + #clock-cells =3D <1>; + }; +}; + +&ap_syscon1 { + cpu_clk: clock-cpu { + compatible =3D "marvell,ap807-cpu-clock"; + clocks =3D <&ap_clk 0>, <&ap_clk 1>; + #clock-cells =3D <1>; + }; +}; + +&ap_sdhci0 { + compatible =3D "marvell,armada-ap807-sdhci"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi new file mode 100644 index 0000000..c2a7cef --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi @@ -0,0 +1,470 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP80x. + */ + +#define IRQ_TYPE_LEVEL_HIGH (1 << 2) +#define IRQ_TYPE_LEVEL_LOW (1 << 3) + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define GIC_CPU_MASK_RAW(x) ((x) << 8) +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/dts-v1/; + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + gpio0 =3D &ap_gpio; + spi0 =3D &spi0; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * This area matches the mapping done with a + * mainline U-Boot, and should be updated by the + * bootloader. + */ + + psci-area@4000000 { + reg =3D <0x0 0x4000000 0x0 0x200000>; + no-map; + }; + }; + + AP_NAME { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + ranges; + + config-space@f0000000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 0xf0000000 0x1000000>; + + smmu: iommu@5000000 { + compatible =3D "marvell,ap806-smmu-500", "= arm,mmu-500"; + reg =3D <0x100000 0x100000>; + dma-coherent; + #iommu-cells =3D <1>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + ; + status =3D "disabled"; + }; + + gic: interrupt-controller@210000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + interrupt-controller; + interrupts =3D ; + reg =3D <0x210000 0x10000>, + <0x220000 0x20000>, + <0x240000 0x20000>, + <0x260000 0x20000>; + + gic_v2m0: v2m@280000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x280000 0x1000>; + arm,msi-base-spi =3D <160>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m1: v2m@290000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x290000 0x1000>; + arm,msi-base-spi =3D <192>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m2: v2m@2a0000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x2a0000 0x1000>; + arm,msi-base-spi =3D <224>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m3: v2m@2b0000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x2b0000 0x1000>; + arm,msi-base-spi =3D <256>; + arm,msi-num-spis =3D <32>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + pmu { + compatible =3D "arm,cortex-a72-pmu"; + interrupt-parent =3D <&pic>; + interrupts =3D <17>; + }; + + odmi: odmi@300000 { + compatible =3D "marvell,odmi-controller"; + interrupt-controller; + msi-controller; + marvell,odmi-frames =3D <4>; + reg =3D <0x300000 0x4000>, + <0x304000 0x4000>, + <0x308000 0x4000>, + <0x30C000 0x4000>; + marvell,spi-base =3D <128>, <136>, <144>, = <152>; + }; + + gicp: gicp@3f0040 { + compatible =3D "marvell,ap806-gicp"; + reg =3D <0x3f0040 0x10>; + marvell,spi-ranges =3D <64 64>, <288 64>; + msi-controller; + }; + + pic: interrupt-controller@3f0100 { + compatible =3D "marvell,armada-8k-pic"; + reg =3D <0x3f0100 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts =3D ; + }; + + sei: interrupt-controller@3f0200 { + compatible =3D "marvell,ap806-sei"; + reg =3D <0x3f0200 0x40>; + interrupts =3D ; + #interrupt-cells =3D <1>; + interrupt-controller; + msi-controller; + }; + + xor@400000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x400000 0x1000>, + <0x410000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@420000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x420000 0x1000>, + <0x430000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@440000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x440000 0x1000>, + <0x450000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@460000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x460000 0x1000>, + <0x470000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + spi0: spi@510600 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x510600 0x50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + i2c0: i2c@511000 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x511000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + uart0: serial@512000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x512000 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + uart1: serial@512100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x512100 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + + }; + + watchdog: watchdog@610000 { + compatible =3D "arm,sbsa-gwdt"; + reg =3D <0x610000 0x1000>, <0x600000 0x100= 0>; + interrupts =3D ; + }; + + ap_sdhci0: sdhci@6e0000 { + compatible =3D "marvell,armada-ap806-sdhci= "; + reg =3D <0x6e0000 0x300>; + interrupts =3D ; + clock-names =3D "core"; + clocks =3D <&ap_clk 4>; + dma-coherent; + marvell,xenon-phy-slow-mode; + status =3D "disabled"; + }; + + ap_syscon0: system-controller@6f4000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x6f4000 0x2000>; + + ap_pinctrl: pinctrl { + compatible =3D "marvell,ap806-pinc= trl"; + + uart0_pins: uart0-pins { + marvell,pins =3D "mpp11", = "mpp19"; + marvell,function =3D "uart= 0"; + }; + }; + + ap_gpio: gpio@1040 { + compatible =3D "marvell,armada-8k-= gpio"; + offset =3D <0x1040>; + ngpios =3D <20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>; + }; + }; + + ap_syscon1: system-controller@6f8000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x6f8000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + ap_thermal: thermal-sensor@80 { + compatible =3D "marvell,armada-ap8= 06-thermal"; + reg =3D <0x80 0x10>; + interrupt-parent =3D <&sei>; + interrupts =3D <18>; + #thermal-sensor-cells =3D <1>; + }; + }; + }; + }; + + /* + * The thermal IP features one internal sensor plus, if applicable= , one + * remote channel wired to one sensor per CPU. + * + * Only one thermal zone per AP/CP may trigger interrupts at a tim= e, the + * first one that will have a critical trip point will be chosen. + */ + thermal-zones { + ap_thermal_ic: ap-thermal-ic { + polling-delay-passive =3D <0>; /* Interrupt driven= */ + polling-delay =3D <0>; /* Interrupt driven */ + + thermal-sensors =3D <&ap_thermal 0>; + + trips { + ap_crit: ap-crit { + temperature =3D <100000>; /* mC de= grees */ + hysteresis =3D <2000>; /* mC degre= es */ + type =3D "critical"; + }; + }; + + cooling-maps { }; + }; + + ap_thermal_cpu0: ap-thermal-cpu0 { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&ap_thermal 1>; + + trips { + cpu0_hot: cpu0-hot { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu0_emerg: cpu0-emerg { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map0_hot: map0-hot { + trip =3D <&cpu0_hot>; + cooling-device =3D <&cpu0 1 2>, + <&cpu1 1 2>; + }; + map0_emerg: map0-ermerg { + trip =3D <&cpu0_emerg>; + cooling-device =3D <&cpu0 3 3>, + <&cpu1 3 3>; + }; + }; + }; + + ap_thermal_cpu1: ap-thermal-cpu1 { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&ap_thermal 2>; + + trips { + cpu1_hot: cpu1-hot { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu1_emerg: cpu1-emerg { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map1_hot: map1-hot { + trip =3D <&cpu1_hot>; + cooling-device =3D <&cpu0 1 2>, + <&cpu1 1 2>; + }; + map1_emerg: map1-emerg { + trip =3D <&cpu1_emerg>; + cooling-device =3D <&cpu0 3 3>, + <&cpu1 3 3>; + }; + }; + }; + + ap_thermal_cpu2: ap-thermal-cpu2 { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&ap_thermal 3>; + + trips { + cpu2_hot: cpu2-hot { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu2_emerg: cpu2-emerg { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map2_hot: map2-hot { + trip =3D <&cpu2_hot>; + cooling-device =3D <&cpu2 1 2>, + <&cpu3 1 2>; + }; + map2_emerg: map2-emerg { + trip =3D <&cpu2_emerg>; + cooling-device =3D <&cpu2 3 3>, + <&cpu3 3 3>; + }; + }; + }; + + ap_thermal_cpu3: ap-thermal-cpu3 { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&ap_thermal 4>; + + trips { + cpu3_hot: cpu3-hot { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu3_emerg: cpu3-emerg { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map3_hot: map3-bhot { + trip =3D <&cpu3_hot>; + cooling-device =3D <&cpu2 1 2>, + <&cpu3 1 2>; + }; + map3_emerg: map3-emerg { + trip =3D <&cpu3_emerg>; + cooling-device =3D <&cpu2 3 3>, + <&cpu3 3 3>; + }; + }; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi index 8b610fd..f002499 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi @@ -6,5 +6,6 @@ /* Common definitions used by Armada 7K/8K DTs */ #define PASTER(x, y) x ## y #define EVALUATOR(x, y) PASTER(x, y) -#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name)) +#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name)) +#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name)) #define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi index 5e8e524..5799e98 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi @@ -1,560 +1,12 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (C) 2016 Marvell Technology Group Ltd. + * Copyright (C) 2019 Marvell Technology Group Ltd. * * Device Tree file for Marvell Armada CP110. */ =20 -#include "armada-common.dtsi" +#define CP11X_TYPE cp110 =20 -#define ICU_GRP_NSR 0x0 -#define ICU_GRP_SR 0x1 -#define ICU_GRP_SEI 0x4 -#define ICU_GRP_REI 0x5 +#include "armada-cp11x.dtsi" =20 -#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * = 0x10000)) -#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface *= 0x1000000)) -#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) += 0xf00000) - -/ { - /* - * The contents of the node are defined below, in order to - * save one indentation level - */ - CP110_NAME: CP110_NAME { }; -}; - -&CP110_NAME { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "simple-bus"; - interrupt-parent =3D <&CP110_LABEL(icu)>; - ranges; - - config-space@CP110_BASE { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "simple-bus"; - ranges =3D <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; - - CP110_LABEL(ethernet): ethernet@0 { - compatible =3D "marvell,armada-7k-pp22"; - reg =3D <0x0 0x100000>, <0x129000 0xb000>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(c= ore_clk)>, - <&CP110_LABEL(core_clk)>; - clock-names =3D "pp_clk", "gop_clk", - "mg_clk", "mg_core_clk", "axi_clk"; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - status =3D "disabled"; - dma-coherent; - - CP110_LABEL(eth0): eth0 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <0>; - gop-port-id =3D <0>; - status =3D "disabled"; - }; - - CP110_LABEL(eth1): eth1 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <1>; - gop-port-id =3D <2>; - status =3D "disabled"; - }; - - CP110_LABEL(eth2): eth2 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <2>; - gop-port-id =3D <3>; - status =3D "disabled"; - }; - }; - - CP110_LABEL(comphy): phy@120000 { - compatible =3D "marvell,comphy-cp110"; - reg =3D <0x120000 0x6000>; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - CP110_LABEL(comphy0): phy@0 { - reg =3D <0>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy1): phy@1 { - reg =3D <1>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy2): phy@2 { - reg =3D <2>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy3): phy@3 { - reg =3D <3>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy4): phy@4 { - reg =3D <4>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy5): phy@5 { - reg =3D <5>; - #phy-cells =3D <1>; - }; - }; - - CP110_LABEL(mdio): mdio@12a200 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "marvell,orion-mdio"; - reg =3D <0x12a200 0x10>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(core_clk)>, <&CP110_LABEL(c= ore_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(xmdio): mdio@12a600 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "marvell,xmdio"; - reg =3D <0x12a600 0x10>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(icu): interrupt-controller@1e0000 { - compatible =3D "marvell,cp110-icu"; - reg =3D <0x1e0000 0x440>; - #interrupt-cells =3D <3>; - interrupt-controller; - msi-parent =3D <&gicp>; - }; - - CP110_LABEL(rtc): rtc@284000 { - compatible =3D "marvell,armada-8k-rtc"; - reg =3D <0x284000 0x20>, <0x284080 0x24>; - reg-names =3D "rtc", "rtc-soc"; - interrupts =3D ; - status =3D "disabled"; - }; - - CP110_LABEL(thermal): thermal@400078 { - compatible =3D "marvell,armada-cp110-thermal"; - reg =3D <0x400078 0x4>, - <0x400070 0x8>; - }; - - CP110_LABEL(syscon0): system-controller@440000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x440000 0x2000>; - - CP110_LABEL(clk): clock { - compatible =3D "marvell,cp110-clock"; - status =3D "disabled"; - #clock-cells =3D <2>; - }; - - CP110_LABEL(gpio1): gpio@100 { - compatible =3D "marvell,armada-8k-gpio"; - offset =3D <0x100>; - ngpios =3D <32>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 0= 32>; - interrupt-controller; - interrupts =3D , - , - , - ; - status =3D "disabled"; - }; - - CP110_LABEL(gpio2): gpio@140 { - compatible =3D "marvell,armada-8k-gpio"; - offset =3D <0x140>; - ngpios =3D <31>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 3= 2 31>; - interrupt-controller; - interrupts =3D , - , - , - ; - status =3D "disabled"; - }; - }; - - CP110_LABEL(usb3_0): usb3@500000 { - compatible =3D "marvell,armada-8k-xhci", - "generic-xhci"; - reg =3D <0x500000 0x4000>; - dma-coherent; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(usb3_1): usb3@510000 { - compatible =3D "marvell,armada-8k-xhci", - "generic-xhci"; - reg =3D <0x510000 0x4000>; - dma-coherent; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(sata0): sata@540000 { - compatible =3D "marvell,armada-8k-ahci", - "generic-ahci"; - reg =3D <0x540000 0x30000>; - dma-coherent; - interrupts =3D ; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(xor0): xor@6a0000 { - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; - reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(x2core_clk)>; - }; - - CP110_LABEL(xor1): xor@6c0000 { - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; - reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(x2core_clk)>; - }; - - CP110_LABEL(spi0): spi@700600 { - compatible =3D "marvell,armada-380-spi"; - reg =3D <0x700600 0x50>; - #address-cells =3D <0x1>; - #size-cells =3D <0x0>; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(spi1): spi@700680 { - compatible =3D "marvell,armada-380-spi"; - reg =3D <0x700680 0x50>; - #address-cells =3D <1>; - #size-cells =3D <0>; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(i2c0): i2c@701000 { - compatible =3D "marvell,mv78230-i2c"; - reg =3D <0x701000 0x20>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(i2c1): i2c@701100 { - compatible =3D "marvell,mv78230-i2c"; - reg =3D <0x701100 0x20>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart0): serial@702000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702000 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart1): serial@702100 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702100 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart2): serial@702200 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702200 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart3): serial@702300 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702300 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(nand_controller): nand@720000 { - /* - * Due to the limitation of the pins available - * this controller is only usable on the CPM - * for A7K and on the CPS for A8K. - */ - compatible =3D "marvell,armada-8k-nand-controller", - "marvell,armada370-nand-controller"; - reg =3D <0x720000 0x54>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(nand_clk)>, - <&CP110_LABEL(x2core_clk)>; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - status =3D "disabled"; - }; - - CP110_LABEL(trng): trng@760000 { - compatible =3D "marvell,armada-8k-rng", - "inside-secure,safexcel-eip76"; - reg =3D <0x760000 0x7d>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(x2core_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "okay"; - }; - - CP110_LABEL(sdhci0): sdhci@780000 { - compatible =3D "marvell,armada-cp110-sdhci"; - reg =3D <0x780000 0x300>; - interrupts =3D ; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL= (core_clk)>; - dma-coherent; - status =3D "disabled"; - }; - - CP110_LABEL(crypto): crypto@800000 { - compatible =3D "inside-secure,safexcel-eip197"; - reg =3D <0x800000 0x200000>; - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(x2core_clk)>, - <&CP110_LABEL(x2core_clk)>; - dma-coherent; - }; - }; - - CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* downstream I/O */ - <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BAS= E(0) 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BA= SE(0) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 2 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* downstream I/O */ - <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BAS= E(1) 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BA= SE(1) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 4 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* downstream I/O */ - <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BAS= E(2) 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BA= SE(2) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 3 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - /* 1 GHz fixed main PLL */ - CP110_LABEL(mainpll): CP110_LABEL(mainpll) { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <1000000000>; - }; - - CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <2>; - }; - - CP110_LABEL(core_clk): CP110_LABEL(core_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <2>; - }; - - CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <2>; - clock-div =3D <5>; - }; - - CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <2>; - clock-div =3D <5>; - }; - - CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <3>; - }; - - CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <4>; - }; -}; +#undef CP11X_TYPE diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp115.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp115.dtsi new file mode 100644 index 0000000..f57860f --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp115.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada CP115. + */ + +#define CP11X_TYPE cp115 + +#include "armada-cp11x.dtsi" + +#undef CP11X_TYPE diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi new file mode 100644 index 0000000..7f26842 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada CP11x. + */ + +#define ICU_GRP_NSR 0x0 +#define ICU_GRP_SR 0x1 +#define ICU_GRP_SEI 0x4 +#define ICU_GRP_REI 0x5 + +#include "armada-common.dtsi" + +#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) += CP11X_PCIEx_MEM_SIZE(iface)) + +/ { + /* + * The contents of the node are defined below, in order to + * save one indentation level + */ + CP11X_NAME: CP11X_NAME { }; + + /* + * CPs only have one sensor in the thermal IC. + * + * The cooling maps are empty as there are no cooling devices. + */ + thermal-zones { + CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) { + polling-delay-passive =3D <0>; /* Interrupt driven= */ + polling-delay =3D <0>; /* Interrupt driven */ + + thermal-sensors =3D <&CP11X_LABEL(thermal) 0>; + + trips { + CP11X_LABEL(crit): crit { + temperature =3D <100000>; /* mC de= grees */ + hysteresis =3D <2000>; /* mC degre= es */ + type =3D "critical"; + }; + }; + + cooling-maps { }; + }; + }; +}; + +&CP11X_NAME { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&CP11X_LABEL(icu_nsr)>; + ranges; + + config-space@CP11X_BASE { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>; + + CP11X_LABEL(ethernet): ethernet@0 { + compatible =3D "marvell,armada-7k-pp22"; + reg =3D <0x0 0x100000>, <0x129000 0xb000>; + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>, + <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(c= ore_clk)>, + <&CP11X_LABEL(core_clk)>; + clock-names =3D "pp_clk", "gop_clk", + "mg_clk", "mg_core_clk", "axi_clk"; + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>; + status =3D "disabled"; + dma-coherent; + + CP11X_LABEL(eth0): eth0 { + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>, + <43 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <51 IRQ_TYPE_LEVEL_HIGH>, + <55 IRQ_TYPE_LEVEL_HIGH>, + <59 IRQ_TYPE_LEVEL_HIGH>, + <63 IRQ_TYPE_LEVEL_HIGH>, + <67 IRQ_TYPE_LEVEL_HIGH>, + <71 IRQ_TYPE_LEVEL_HIGH>, + <129 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "hif0", "hif1", "hif2", + "hif3", "hif4", "hif5", "hif6", "h= if7", + "hif8", "link"; + port-id =3D <0>; + gop-port-id =3D <0>; + status =3D "disabled"; + }; + + CP11X_LABEL(eth1): eth1 { + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH>, + <44 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>, + <52 IRQ_TYPE_LEVEL_HIGH>, + <56 IRQ_TYPE_LEVEL_HIGH>, + <60 IRQ_TYPE_LEVEL_HIGH>, + <64 IRQ_TYPE_LEVEL_HIGH>, + <68 IRQ_TYPE_LEVEL_HIGH>, + <72 IRQ_TYPE_LEVEL_HIGH>, + <128 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "hif0", "hif1", "hif2", + "hif3", "hif4", "hif5", "hif6", "h= if7", + "hif8", "link"; + port-id =3D <1>; + gop-port-id =3D <2>; + status =3D "disabled"; + }; + + CP11X_LABEL(eth2): eth2 { + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH>, + <45 IRQ_TYPE_LEVEL_HIGH>, + <49 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>, + <57 IRQ_TYPE_LEVEL_HIGH>, + <61 IRQ_TYPE_LEVEL_HIGH>, + <65 IRQ_TYPE_LEVEL_HIGH>, + <69 IRQ_TYPE_LEVEL_HIGH>, + <73 IRQ_TYPE_LEVEL_HIGH>, + <127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "hif0", "hif1", "hif2", + "hif3", "hif4", "hif5", "hif6", "h= if7", + "hif8", "link"; + port-id =3D <2>; + gop-port-id =3D <3>; + status =3D "disabled"; + }; + }; + + CP11X_LABEL(comphy): phy@120000 { + compatible =3D "marvell,comphy-cp110"; + reg =3D <0x120000 0x6000>; + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>; + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (core_clk)>, + <&CP11X_LABEL(core_clk)>; + clock-names =3D "mg_clk", "mg_core_clk", "axi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + CP11X_LABEL(comphy0): phy@0 { + reg =3D <0>; + #phy-cells =3D <1>; + }; + + CP11X_LABEL(comphy1): phy@1 { + reg =3D <1>; + #phy-cells =3D <1>; + }; + + CP11X_LABEL(comphy2): phy@2 { + reg =3D <2>; + #phy-cells =3D <1>; + }; + + CP11X_LABEL(comphy3): phy@3 { + reg =3D <3>; + #phy-cells =3D <1>; + }; + + CP11X_LABEL(comphy4): phy@4 { + reg =3D <4>; + #phy-cells =3D <1>; + }; + + CP11X_LABEL(comphy5): phy@5 { + reg =3D <5>; + #phy-cells =3D <1>; + }; + }; + + CP11X_LABEL(mdio): mdio@12a200 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,orion-mdio"; + reg =3D <0x12a200 0x10>; + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>, + <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(c= ore_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(xmdio): mdio@12a600 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,xmdio"; + reg =3D <0x12a600 0x10>; + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>, + <&CP11X_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(icu): interrupt-controller@1e0000 { + compatible =3D "marvell,cp110-icu"; + reg =3D <0x1e0000 0x440>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + CP11X_LABEL(icu_nsr): interrupt-controller@10 { + compatible =3D "marvell,cp110-icu-nsr"; + reg =3D <0x10 0x20>; + #interrupt-cells =3D <2>; + interrupt-controller; + msi-parent =3D <&gicp>; + }; + + CP11X_LABEL(icu_sei): interrupt-controller@50 { + compatible =3D "marvell,cp110-icu-sei"; + reg =3D <0x50 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + msi-parent =3D <&sei>; + }; + }; + + CP11X_LABEL(rtc): rtc@284000 { + compatible =3D "marvell,armada-8k-rtc"; + reg =3D <0x284000 0x20>, <0x284080 0x24>; + reg-names =3D "rtc", "rtc-soc"; + interrupts =3D <77 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + CP11X_LABEL(syscon0): system-controller@440000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x440000 0x2000>; + + CP11X_LABEL(clk): clock { + compatible =3D "marvell,cp110-clock"; + status =3D "disabled"; + #clock-cells =3D <2>; + }; + + CP11X_LABEL(gpio1): gpio@100 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x100>; + ngpios =3D <32>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 0= 32>; + interrupt-controller; + interrupts =3D <86 IRQ_TYPE_LEVEL_HIGH>, + <85 IRQ_TYPE_LEVEL_HIGH>, + <84 IRQ_TYPE_LEVEL_HIGH>, + <83 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + + CP11X_LABEL(gpio2): gpio@140 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x140>; + ngpios =3D <31>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 3= 2 31>; + interrupt-controller; + interrupts =3D <82 IRQ_TYPE_LEVEL_HIGH>, + <81 IRQ_TYPE_LEVEL_HIGH>, + <80 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + }; + + CP11X_LABEL(syscon1): system-controller@400000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x400000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + CP11X_LABEL(thermal): thermal-sensor@70 { + compatible =3D "marvell,armada-cp110-therm= al"; + reg =3D <0x70 0x10>; + interrupts-extended =3D + <&CP11X_LABEL(icu_sei) 116 IRQ_TYP= E_LEVEL_HIGH>; + #thermal-sensor-cells =3D <1>; + }; + }; + + CP11X_LABEL(usb3_0): usb@500000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x500000 0x4000>; + dma-coherent; + interrupts =3D <106 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, + <&CP11X_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(usb3_1): usb@510000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x510000 0x4000>; + dma-coherent; + interrupts =3D <105 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, + <&CP11X_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(sata0): sata@540000 { + compatible =3D "marvell,armada-8k-ahci"; + reg =3D <0x540000 0x30000>; + dma-coherent; + clocks =3D <&CP11X_LABEL(core_clk)>, + <&CP11X_LABEL(core_clk)>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + sata-port@0 { + interrupts =3D <109 IRQ_TYPE_LEVEL_HIGH>; + reg =3D <0>; + }; + + sata-port@1 { + interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>; + reg =3D <1>; + }; + }; + + CP11X_LABEL(xor0): xor@6a0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, + <&CP11X_LABEL(x2core_clk)>; + }; + + CP11X_LABEL(xor1): xor@6c0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, + <&CP11X_LABEL(x2core_clk)>; + }; + + CP11X_LABEL(spi0): spi@700600 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700600 0x50>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(spi1): spi@700680 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700680 0x50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(i2c0): i2c@701000 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <120 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(i2c1): i2c@701100 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701100 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <121 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(uart0): serial@702000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702000 0x100>; + reg-shift =3D <2>; + interrupts =3D <122 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(uart1): serial@702100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702100 0x100>; + reg-shift =3D <2>; + interrupts =3D <123 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(uart2): serial@702200 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702200 0x100>; + reg-shift =3D <2>; + interrupts =3D <124 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(uart3): serial@702300 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702300 0x100>; + reg-shift =3D <2>; + interrupts =3D <125 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(nand_controller): nand@720000 { + /* + * Due to the limitation of the pins available + * this controller is only usable on the CPM + * for A7K and on the CPS for A8K. + */ + compatible =3D "marvell,armada-8k-nand-controller", + "marvell,armada370-nand-controller"; + reg =3D <0x720000 0x54>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <115 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(nand_clk)>, + <&CP11X_LABEL(x2core_clk)>; + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>; + status =3D "disabled"; + }; + + CP11X_LABEL(trng): trng@760000 { + compatible =3D "marvell,armada-8k-rng", + "inside-secure,safexcel-eip76"; + reg =3D <0x760000 0x7d>; + interrupts =3D <95 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(x2core_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "okay"; + }; + + CP11X_LABEL(sdhci0): sdhci@780000 { + compatible =3D "marvell,armada-cp110-sdhci"; + reg =3D <0x780000 0x300>; + interrupts =3D <27 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "axi"; + clocks =3D <&CP11X_LABEL(sdio_clk)>, <&CP11X_LABEL= (core_clk)>; + dma-coherent; + status =3D "disabled"; + }; + + CP11X_LABEL(crypto): crypto@800000 { + compatible =3D "inside-secure,safexcel-eip197b"; + reg =3D <0x800000 0x200000>; + interrupts =3D <87 IRQ_TYPE_LEVEL_HIGH>, + <88 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <90 IRQ_TYPE_LEVEL_HIGH>, + <91 IRQ_TYPE_LEVEL_HIGH>, + <92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "mem", "ring0", "ring1", + "ring2", "ring3", "eip"; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(x2core_clk)>, + <&CP11X_LABEL(x2core_clk)>; + dma-coherent; + }; + }; + + CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>, + <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + /* non-prefetchable memory */ + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_= PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TY= PE_LEVEL_HIGH>; + interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>, + <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + /* non-prefetchable memory */ + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_= PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TY= PE_LEVEL_HIGH>; + interrupts =3D <24 IRQ_TYPE_LEVEL_HIGH>; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>, + <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + /* non-prefetchable memory */ + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_= PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TY= PE_LEVEL_HIGH>; + interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH>; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + /* 1 GHz fixed main PLL */ + CP11X_LABEL(mainpll): CP11X_LABEL(mainpll) { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1000000000>; + }; + + CP11X_LABEL(x2core_clk): CP11X_LABEL(x2core_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + CP11X_LABEL(core_clk): CP11X_LABEL(core_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + CP11X_LABEL(sdio_clk): CP11X_LABEL(sdio_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <2>; + clock-div =3D <5>; + }; + + CP11X_LABEL(nand_clk): CP11X_LABEL(nand_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <2>; + clock-div =3D <5>; + }; + + CP11X_LABEL(ppv2_clk): CP11X_LABEL(ppv2_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <3>; + }; + + CP11X_LABEL(slow_io_clk): CP11X_LABEL(slow_io_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <4>; + }; +}; --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73023): https://edk2.groups.io/g/devel/message/73023 Mute This Topic: https://groups.io/mt/81438844/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 21:13:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73024+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73024+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616097510; cv=none; d=zohomail.com; s=zohoarc; b=Vl9B/gt6BL3vT2wytvQ6OmXd3jNPom3aQJxo53R9E86Ds/Vo4I0JdQ+uDRO889uOt/HJCLlpxRoTyCO1OgJUs+OR2xT3z5+VHN9oC1RGpejzNWZGGMs/UGcy6rES1KX3pjZVT35q8osnmsgFzbypyAo9J0eFS3Ir2B3AH7UiEjw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616097510; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=N6f0hcoZX5xKkr6oaa+GzNSwobX4KQSUz5BXVAqXSPc=; b=GmY9BaZqx849ivQ59c9QBM2a+aBWasf300emBEfY4IbhkRT8J0O7hbpCLgOojgeSeNipG5/RPvowtyCQdAMn4rPnkm/NZgDsVSofgCDfwhS5315GbTNaC9GWCZDLjVD02VJbwnGeXGL1FiR2BJZayvwllv6K+x9f3Q0BBYjeXRE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73024+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616097510875859.2860842217466; Thu, 18 Mar 2021 12:58:30 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id zlyXYY1788612xqF3H7aGSL5; Thu, 18 Mar 2021 12:58:30 -0700 X-Received: from mail-lj1-f173.google.com (mail-lj1-f173.google.com [209.85.208.173]) by mx.groups.io with SMTP id smtpd.web12.231.1616097509109176570 for ; Thu, 18 Mar 2021 12:58:29 -0700 X-Received: by mail-lj1-f173.google.com with SMTP id z25so9062834lja.3 for ; Thu, 18 Mar 2021 12:58:28 -0700 (PDT) X-Gm-Message-State: GiPAoS4FiIyeeK26GzxPnZuAx1787277AA= X-Google-Smtp-Source: ABdhPJzXf5KE9uffdQhs/WOnuy9lzEFG0vQtbN/b3gvLThusxRWiU5FXH5slr2Wmlt1dX+r7W9shaQ== X-Received: by 2002:a2e:7610:: with SMTP id r16mr6377930ljc.472.1616097506871; Thu, 18 Mar 2021 12:58:26 -0700 (PDT) X-Received: from gilgamesh.int.semihalf.com (host-193.106.246.138.static.3s.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id b30sm344622lfj.101.2021.03.18.12.58.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 12:58:26 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ard.biesheuvel@arm.com, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com, jon@solid-run.com Subject: [edk2-devel] [edk2-non-osi PATCH 4/4] Marvell/OcteonTx: Update device trees Date: Thu, 18 Mar 2021 20:57:57 +0100 Message-Id: <20210318195757.2974226-5-mw@semihalf.com> In-Reply-To: <20210318195757.2974226-1-mw@semihalf.com> References: <20210318195757.2974226-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616097510; bh=9WOd8IwKTUzBP0yN4iInQc2bCQ6Pkch2OPJSQr03/Go=; h=Cc:Date:From:Reply-To:Subject:To; b=DrAZglgljEM85yrKH3c8VnLQFkVCUg7ESRwr0ol/uz5F792URvID7p2hDKLHPR1xqBX InwKRqhRUxJt95Jt/ZnDOVomm3WsrX6UkfTrpjtYJedcPVWOlv2JRgVM9EegS7aRuEBXT 3g3oBy1UZDwn9yIJU9p37ADk81xpzm6KXBc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This patch updates the OcteonTx device trees to the version found in Linux v5.11. All previous modifications, compared to vanilla files, are kept, i.e. disabled SPI flashes & RTC and fixed-clock tree. Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf = | 2 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf = | 2 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf = | 2 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi = | 43 -- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi = | 93 +++ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi = | 33 ++ Silicon/Marvell/OcteonTx/DeviceTree/T91/{armada-ap806.dtsi =3D> armada-ap8= 0x.dtsi} | 238 +++++++- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi = | 3 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi = | 552 ----------------- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi = | 12 + Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi = | 622 ++++++++++++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts = | 185 ------ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts = | 402 +++++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi = | 143 +---- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts = | 29 - Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9131-db.dtsi =3D> cn9131-db.dts= } | 93 +-- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts = | 70 --- Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9132-db.dtsi =3D> cn9132-db.dts= } | 126 +++- 18 files changed, 1570 insertions(+), 1080 deletions(-) delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-qu= ad.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-qu= ad.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dt= si rename Silicon/Marvell/OcteonTx/DeviceTree/T91/{armada-ap806.dtsi =3D> arm= ada-ap80x.dtsi} (52%) delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dt= si create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dt= si create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dt= si delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts rename Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9131-db.dtsi =3D> cn9131= -db.dts} (66%) delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts rename Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9132-db.dtsi =3D> cn9132= -db.dts} (54%) diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf index 091a5b4..dfc6c32 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf @@ -16,7 +16,7 @@ VERSION_STRING =3D 1.0 =20 [Sources] - cn9130-db-A.dts + cn9130-db.dts =20 [Packages] MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf index 8108197..f5c26a8 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf @@ -16,7 +16,7 @@ VERSION_STRING =3D 1.0 =20 [Sources] - cn9131-db-A.dts + cn9131-db.dts =20 [Packages] MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf index c9e3b04..2796541 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf @@ -16,7 +16,7 @@ VERSION_STRING =3D 1.0 =20 [Sources] - cn9132-db-A.dts + cn9132-db.dts =20 [Packages] MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi= b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi deleted file mode 100644 index bae0ed9..0000000 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#include "armada-ap806.dtsi" - -/ { - model =3D "Marvell Armada AP806 Quad"; - compatible =3D "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - - cpu@0 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x000>; - enable-method =3D "psci"; - }; - cpu@1 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x001>; - enable-method =3D "psci"; - }; - cpu@100 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x100>; - enable-method =3D "psci"; - }; - cpu@101 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72", "arm,armv8"; - reg =3D <0x101>; - enable-method =3D "psci"; - }; - }; -}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi= b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi new file mode 100644 index 0000000..6222569 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada AP807 Quad + * + * Copyright (C) 2019 Marvell Technology Group Ltd. + */ + +#include "armada-ap807.dtsi" + +/ { + model =3D "Marvell Armada AP807 Quad"; + compatible =3D "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x000>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 0>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_0>; + }; + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x001>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 0>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_0>; + }; + cpu2: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x100>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 1>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + }; + cpu3: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x101>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + clocks =3D <&cpu_clk 1>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; + }; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi new file mode 100644 index 0000000..b42dc3a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada AP807 + * + * Copyright (C) 2019 Marvell Technology Group Ltd. + */ + +#define AP_NAME ap807 +#include "armada-ap80x.dtsi" + +/ { + model =3D "Marvell Armada AP807"; + compatible =3D "marvell,armada-ap807"; +}; + +&ap_syscon0 { + ap_clk: clock { + compatible =3D "marvell,ap807-clock"; + #clock-cells =3D <1>; + }; +}; + +&ap_syscon1 { + cpu_clk: clock-cpu { + compatible =3D "marvell,ap807-cpu-clock"; + clocks =3D <&ap_clk 0>, <&ap_clk 1>; + #clock-cells =3D <1>; + }; +}; + +&ap_sdhci0 { + compatible =3D "marvell,armada-ap807-sdhci"; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi similarity index 52% rename from Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi rename to Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi index 66124bf..c2a7cef 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (C) 2016 Marvell Technology Group Ltd. + * Copyright (C) 2019 Marvell Technology Group Ltd. * - * Device Tree file for Marvell Armada AP806. + * Device Tree file for Marvell Armada AP80x. */ =20 #define IRQ_TYPE_LEVEL_HIGH (1 << 2) @@ -14,11 +14,12 @@ #define GIC_CPU_MASK_RAW(x) ((x) << 8) #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) =20 +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + /dts-v1/; =20 / { - model =3D "Marvell Armada AP806"; - compatible =3D "marvell,armada-ap806"; #address-cells =3D <2>; #size-cells =3D <2>; =20 @@ -34,7 +35,24 @@ method =3D "smc"; }; =20 - ap806 { + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * This area matches the mapping done with a + * mainline U-Boot, and should be updated by the + * bootloader. + */ + + psci-area@4000000 { + reg =3D <0x0 0x4000000 0x0 0x200000>; + no-map; + }; + }; + + AP_NAME { #address-cells =3D <2>; #size-cells =3D <2>; compatible =3D "simple-bus"; @@ -47,6 +65,24 @@ compatible =3D "simple-bus"; ranges =3D <0x0 0x0 0xf0000000 0x1000000>; =20 + smmu: iommu@5000000 { + compatible =3D "marvell,ap806-smmu-500", "= arm,mmu-500"; + reg =3D <0x100000 0x100000>; + dma-coherent; + #iommu-cells =3D <1>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + ; + status =3D "disabled"; + }; + gic: interrupt-controller@210000 { compatible =3D "arm,gic-400"; #interrupt-cells =3D <3>; @@ -131,6 +167,15 @@ interrupts =3D ; }; =20 + sei: interrupt-controller@3f0200 { + compatible =3D "marvell,ap806-sei"; + reg =3D <0x3f0200 0x40>; + interrupts =3D ; + #interrupt-cells =3D <1>; + interrupt-controller; + msi-controller; + }; + xor@400000 { compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; reg =3D <0x400000 0x1000>, @@ -183,7 +228,6 @@ #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; - timeout-ms =3D <1000>; clocks =3D <&ap_clk 3>; status =3D "disabled"; }; @@ -226,15 +270,10 @@ status =3D "disabled"; }; =20 - ap_syscon: system-controller@6f4000 { + ap_syscon0: system-controller@6f4000 { compatible =3D "syscon", "simple-mfd"; reg =3D <0x6f4000 0x2000>; =20 - ap_clk: clock { - compatible =3D "marvell,ap806-cloc= k"; - #clock-cells =3D <1>; - }; - ap_pinctrl: pinctrl { compatible =3D "marvell,ap806-pinc= trl"; =20 @@ -254,10 +293,177 @@ }; }; =20 - ap_thermal: thermal@6f808c { - compatible =3D "marvell,armada-ap806-therm= al"; - reg =3D <0x6f808c 0x4>, - <0x6f8084 0x8>; + ap_syscon1: system-controller@6f8000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x6f8000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + ap_thermal: thermal-sensor@80 { + compatible =3D "marvell,armada-ap8= 06-thermal"; + reg =3D <0x80 0x10>; + interrupt-parent =3D <&sei>; + interrupts =3D <18>; + #thermal-sensor-cells =3D <1>; + }; + }; + }; + }; + + /* + * The thermal IP features one internal sensor plus, if applicable= , one + * remote channel wired to one sensor per CPU. + * + * Only one thermal zone per AP/CP may trigger interrupts at a tim= e, the + * first one that will have a critical trip point will be chosen. + */ + thermal-zones { + ap_thermal_ic: ap-thermal-ic { + polling-delay-passive =3D <0>; /* Interrupt driven= */ + polling-delay =3D <0>; /* Interrupt driven */ + + thermal-sensors =3D <&ap_thermal 0>; + + trips { + ap_crit: ap-crit { + temperature =3D <100000>; /* mC de= grees */ + hysteresis =3D <2000>; /* mC degre= es */ + type =3D "critical"; + }; + }; + + cooling-maps { }; + }; + + ap_thermal_cpu0: ap-thermal-cpu0 { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&ap_thermal 1>; + + trips { + cpu0_hot: cpu0-hot { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu0_emerg: cpu0-emerg { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map0_hot: map0-hot { + trip =3D <&cpu0_hot>; + cooling-device =3D <&cpu0 1 2>, + <&cpu1 1 2>; + }; + map0_emerg: map0-ermerg { + trip =3D <&cpu0_emerg>; + cooling-device =3D <&cpu0 3 3>, + <&cpu1 3 3>; + }; + }; + }; + + ap_thermal_cpu1: ap-thermal-cpu1 { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&ap_thermal 2>; + + trips { + cpu1_hot: cpu1-hot { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu1_emerg: cpu1-emerg { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map1_hot: map1-hot { + trip =3D <&cpu1_hot>; + cooling-device =3D <&cpu0 1 2>, + <&cpu1 1 2>; + }; + map1_emerg: map1-emerg { + trip =3D <&cpu1_emerg>; + cooling-device =3D <&cpu0 3 3>, + <&cpu1 3 3>; + }; + }; + }; + + ap_thermal_cpu2: ap-thermal-cpu2 { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&ap_thermal 3>; + + trips { + cpu2_hot: cpu2-hot { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu2_emerg: cpu2-emerg { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map2_hot: map2-hot { + trip =3D <&cpu2_hot>; + cooling-device =3D <&cpu2 1 2>, + <&cpu3 1 2>; + }; + map2_emerg: map2-emerg { + trip =3D <&cpu2_emerg>; + cooling-device =3D <&cpu2 3 3>, + <&cpu3 3 3>; + }; + }; + }; + + ap_thermal_cpu3: ap-thermal-cpu3 { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&ap_thermal 4>; + + trips { + cpu3_hot: cpu3-hot { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu3_emerg: cpu3-emerg { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map3_hot: map3-bhot { + trip =3D <&cpu3_hot>; + cooling-device =3D <&cpu2 1 2>, + <&cpu3 1 2>; + }; + map3_emerg: map3-emerg { + trip =3D <&cpu3_emerg>; + cooling-device =3D <&cpu2 3 3>, + <&cpu3 3 3>; + }; }; }; }; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi b/S= ilicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi index 8b610fd..f002499 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi @@ -6,5 +6,6 @@ /* Common definitions used by Armada 7K/8K DTs */ #define PASTER(x, y) x ## y #define EVALUATOR(x, y) PASTER(x, y) -#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name)) +#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name)) +#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name)) #define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi deleted file mode 100644 index b6e5ded..0000000 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi +++ /dev/null @@ -1,552 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada CP110. - */ - -#include "armada-common.dtsi" - -#define ICU_GRP_NSR 0x0 -#define ICU_GRP_SR 0x1 -#define ICU_GRP_SEI 0x4 -#define ICU_GRP_REI 0x5 - -#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0= xf00000) - -/ { - /* - * The contents of the node are defined below, in order to - * save one indentation level - */ - CP110_NAME: CP110_NAME { }; -}; - -&CP110_NAME { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "simple-bus"; - interrupt-parent =3D <&CP110_LABEL(icu)>; - ranges; - - config-space@CP110_BASE { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "simple-bus"; - ranges =3D <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; - - CP110_LABEL(ethernet): ethernet@0 { - compatible =3D "marvell,armada-7k-pp22"; - reg =3D <0x0 0x100000>, <0x129000 0xb000>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(c= ore_clk)>, - <&CP110_LABEL(core_clk)>; - clock-names =3D "pp_clk", "gop_clk", - "mg_clk", "mg_core_clk", "axi_clk"; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - status =3D "disabled"; - dma-coherent; - - CP110_LABEL(eth0): eth0 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <0>; - gop-port-id =3D <0>; - status =3D "disabled"; - }; - - CP110_LABEL(eth1): eth1 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <1>; - gop-port-id =3D <2>; - status =3D "disabled"; - }; - - CP110_LABEL(eth2): eth2 { - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", - "tx-cpu3", "rx-shared", "link"; - port-id =3D <2>; - gop-port-id =3D <3>; - status =3D "disabled"; - }; - }; - - CP110_LABEL(comphy): phy@120000 { - compatible =3D "marvell,comphy-cp110"; - reg =3D <0x120000 0x6000>; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - CP110_LABEL(comphy0): phy@0 { - reg =3D <0>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy1): phy@1 { - reg =3D <1>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy2): phy@2 { - reg =3D <2>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy3): phy@3 { - reg =3D <3>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy4): phy@4 { - reg =3D <4>; - #phy-cells =3D <1>; - }; - - CP110_LABEL(comphy5): phy@5 { - reg =3D <5>; - #phy-cells =3D <1>; - }; - }; - - CP110_LABEL(mdio): mdio@12a200 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "marvell,orion-mdio"; - reg =3D <0x12a200 0x10>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(core_clk)>, <&CP110_LABEL(c= ore_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(xmdio): mdio@12a600 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "marvell,xmdio"; - reg =3D <0x12a600 0x10>; - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(icu): interrupt-controller@1e0000 { - compatible =3D "marvell,cp110-icu"; - reg =3D <0x1e0000 0x440>; - #interrupt-cells =3D <3>; - interrupt-controller; - msi-parent =3D <&gicp>; - }; - - CP110_LABEL(rtc): rtc@284000 { - compatible =3D "marvell,armada-8k-rtc"; - reg =3D <0x284000 0x20>, <0x284080 0x24>; - reg-names =3D "rtc", "rtc-soc"; - interrupts =3D ; - status =3D "disabled"; - }; - - CP110_LABEL(thermal): thermal@400078 { - compatible =3D "marvell,armada-cp110-thermal"; - reg =3D <0x400078 0x4>, - <0x400070 0x8>; - }; - - CP110_LABEL(syscon0): system-controller@440000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x440000 0x2000>; - - CP110_LABEL(clk): clock { - compatible =3D "marvell,cp110-clock"; - status =3D "disabled"; - #clock-cells =3D <2>; - }; - - CP110_LABEL(gpio1): gpio@100 { - compatible =3D "marvell,armada-8k-gpio"; - offset =3D <0x100>; - ngpios =3D <32>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 0= 32>; - interrupt-controller; - interrupts =3D , - , - , - ; - status =3D "disabled"; - }; - - CP110_LABEL(gpio2): gpio@140 { - compatible =3D "marvell,armada-8k-gpio"; - offset =3D <0x140>; - ngpios =3D <31>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 3= 2 31>; - interrupt-controller; - interrupts =3D , - , - , - ; - status =3D "disabled"; - }; - }; - - CP110_LABEL(usb3_0): usb3@500000 { - compatible =3D "marvell,armada-8k-xhci", - "generic-xhci"; - reg =3D <0x500000 0x4000>; - dma-coherent; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(usb3_1): usb3@510000 { - compatible =3D "marvell,armada-8k-xhci", - "generic-xhci"; - reg =3D <0x510000 0x4000>; - dma-coherent; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(sata0): sata@540000 { - compatible =3D "marvell,armada-8k-ahci", - "generic-ahci"; - reg =3D <0x540000 0x30000>; - dma-coherent; - interrupts =3D ; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(xor0): xor@6a0000 { - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; - reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(x2core_clk)>; - }; - - CP110_LABEL(xor1): xor@6c0000 { - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; - reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, - <&CP110_LABEL(x2core_clk)>; - }; - - CP110_LABEL(spi0): spi@700600 { - compatible =3D "marvell,armada-380-spi"; - reg =3D <0x700600 0x50>; - #address-cells =3D <0x1>; - #size-cells =3D <0x0>; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(spi1): spi@700680 { - compatible =3D "marvell,armada-380-spi"; - reg =3D <0x700680 0x50>; - #address-cells =3D <1>; - #size-cells =3D <0>; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(i2c0): i2c@701000 { - compatible =3D "marvell,mv78230-i2c"; - reg =3D <0x701000 0x20>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(i2c1): i2c@701100 { - compatible =3D "marvell,mv78230-i2c"; - reg =3D <0x701100 0x20>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart0): serial@702000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702000 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart1): serial@702100 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702100 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart2): serial@702200 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702200 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(uart3): serial@702300 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x702300 0x100>; - reg-shift =3D <2>; - interrupts =3D ; - reg-io-width =3D <1>; - clock-names =3D "baudclk", "apb_pclk"; - clocks =3D <&CP110_LABEL(slow_io_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(nand_controller): nand@720000 { - /* - * Due to the limitation of the pins available - * this controller is only usable on the CPM - * for A7K and on the CPS for A8K. - */ - compatible =3D "marvell,armada-8k-nand-controller", - "marvell,armada370-nand-controller"; - reg =3D <0x720000 0x54>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(nand_clk)>, - <&CP110_LABEL(x2core_clk)>; - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; - status =3D "disabled"; - }; - - CP110_LABEL(trng): trng@760000 { - compatible =3D "marvell,armada-8k-rng", - "inside-secure,safexcel-eip76"; - reg =3D <0x760000 0x7d>; - interrupts =3D ; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(x2core_clk)>, - <&CP110_LABEL(x2core_clk)>; - status =3D "okay"; - }; - - CP110_LABEL(sdhci0): sdhci@780000 { - compatible =3D "marvell,armada-cp110-sdhci"; - reg =3D <0x780000 0x300>; - interrupts =3D ; - clock-names =3D "core", "axi"; - clocks =3D <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL= (core_clk)>; - dma-coherent; - status =3D "disabled"; - }; - - CP110_LABEL(crypto): crypto@800000 { - compatible =3D "inside-secure,safexcel-eip197"; - reg =3D <0x800000 0x200000>; - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(x2core_clk)>, - <&CP110_LABEL(x2core_clk)>; - dma-coherent; - }; - }; - - CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* non-prefetchable memory */ - <0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_B= ASE(0) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 2 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* non-prefetchable memory */ - <0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_B= ASE(1) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 4 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; - reg =3D <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, - <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; - reg-names =3D "ctrl", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - dma-coherent; - msi-parent =3D <&gic_v2m0>; - - bus-range =3D <0 0xff>; - ranges =3D - /* non-prefetchable memory */ - <0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_B= ASE(2) 0 0xf00000>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 3 IRQ_TYPE_LEVEL_HIGH>; - interrupts =3D ; - - num-lanes =3D <1>; - clock-names =3D "core", "reg"; - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; - status =3D "disabled"; - }; - - /* 1 GHz fixed main PLL */ - CP110_LABEL(mainpll): CP110_LABEL(mainpll) { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <1000000000>; - }; - - CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <2>; - }; - - CP110_LABEL(core_clk): CP110_LABEL(core_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <2>; - }; - - CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <2>; - clock-div =3D <5>; - }; - - CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <2>; - clock-div =3D <5>; - }; - - CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <3>; - }; - - CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) { - compatible =3D "fixed-factor-clock"; - clocks =3D <&CP110_LABEL(mainpll)>; - #clock-cells =3D <0>; - clock-mult =3D <1>; - clock-div =3D <4>; - }; -}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi new file mode 100644 index 0000000..f57860f --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada CP115. + */ + +#define CP11X_TYPE cp115 + +#include "armada-cp11x.dtsi" + +#undef CP11X_TYPE diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi new file mode 100644 index 0000000..05b7627 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada CP11x. + */ + +#include "armada-common.dtsi" + +#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) += CP11X_PCIEx_MEM_SIZE(iface)) + +/ { + /* + * The contents of the node are defined below, in order to + * save one indentation level + */ + CP11X_NAME: CP11X_NAME { }; + + /* + * CPs only have one sensor in the thermal IC. + * + * The cooling maps are empty as there are no cooling devices. + */ + thermal-zones { + CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) { + polling-delay-passive =3D <0>; /* Interrupt driven= */ + polling-delay =3D <0>; /* Interrupt driven */ + + thermal-sensors =3D <&CP11X_LABEL(thermal) 0>; + + trips { + CP11X_LABEL(crit): crit { + temperature =3D <100000>; /* mC de= grees */ + hysteresis =3D <2000>; /* mC degre= es */ + type =3D "critical"; + }; + }; + + cooling-maps { }; + }; + }; +}; + +&CP11X_NAME { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&CP11X_LABEL(icu_nsr)>; + ranges; + + config-space@CP11X_BASE { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>; + + CP11X_LABEL(ethernet): ethernet@0 { + compatible =3D "marvell,armada-7k-pp22"; + reg =3D <0x0 0x100000>, <0x129000 0xb000>; + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>, + <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(c= ore_clk)>, + <&CP11X_LABEL(core_clk)>; + clock-names =3D "pp_clk", "gop_clk", + "mg_clk", "mg_core_clk", "axi_clk"; + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>; + status =3D "disabled"; + dma-coherent; + + CP11X_LABEL(eth0): eth0 { + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>, + <43 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <51 IRQ_TYPE_LEVEL_HIGH>, + <55 IRQ_TYPE_LEVEL_HIGH>, + <59 IRQ_TYPE_LEVEL_HIGH>, + <63 IRQ_TYPE_LEVEL_HIGH>, + <67 IRQ_TYPE_LEVEL_HIGH>, + <71 IRQ_TYPE_LEVEL_HIGH>, + <129 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "hif0", "hif1", "hif2", + "hif3", "hif4", "hif5", "hif6", "h= if7", + "hif8", "link"; + port-id =3D <0>; + gop-port-id =3D <0>; + status =3D "disabled"; + }; + + CP11X_LABEL(eth1): eth1 { + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH>, + <44 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>, + <52 IRQ_TYPE_LEVEL_HIGH>, + <56 IRQ_TYPE_LEVEL_HIGH>, + <60 IRQ_TYPE_LEVEL_HIGH>, + <64 IRQ_TYPE_LEVEL_HIGH>, + <68 IRQ_TYPE_LEVEL_HIGH>, + <72 IRQ_TYPE_LEVEL_HIGH>, + <128 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "hif0", "hif1", "hif2", + "hif3", "hif4", "hif5", "hif6", "h= if7", + "hif8", "link"; + port-id =3D <1>; + gop-port-id =3D <2>; + status =3D "disabled"; + }; + + CP11X_LABEL(eth2): eth2 { + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH>, + <45 IRQ_TYPE_LEVEL_HIGH>, + <49 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>, + <57 IRQ_TYPE_LEVEL_HIGH>, + <61 IRQ_TYPE_LEVEL_HIGH>, + <65 IRQ_TYPE_LEVEL_HIGH>, + <69 IRQ_TYPE_LEVEL_HIGH>, + <73 IRQ_TYPE_LEVEL_HIGH>, + <127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "hif0", "hif1", "hif2", + "hif3", "hif4", "hif5", "hif6", "h= if7", + "hif8", "link"; + port-id =3D <2>; + gop-port-id =3D <3>; + status =3D "disabled"; + }; + }; + + CP11X_LABEL(comphy): phy@120000 { + compatible =3D "marvell,comphy-cp110"; + reg =3D <0x120000 0x6000>; + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>; + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (core_clk)>, + <&CP11X_LABEL(core_clk)>; + clock-names =3D "mg_clk", "mg_core_clk", "axi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + CP11X_LABEL(comphy0): phy@0 { + reg =3D <0>; + #phy-cells =3D <1>; + }; + + CP11X_LABEL(comphy1): phy@1 { + reg =3D <1>; + #phy-cells =3D <1>; + }; + + CP11X_LABEL(comphy2): phy@2 { + reg =3D <2>; + #phy-cells =3D <1>; + }; + + CP11X_LABEL(comphy3): phy@3 { + reg =3D <3>; + #phy-cells =3D <1>; + }; + + CP11X_LABEL(comphy4): phy@4 { + reg =3D <4>; + #phy-cells =3D <1>; + }; + + CP11X_LABEL(comphy5): phy@5 { + reg =3D <5>; + #phy-cells =3D <1>; + }; + }; + + CP11X_LABEL(mdio): mdio@12a200 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,orion-mdio"; + reg =3D <0x12a200 0x10>; + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>, + <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(c= ore_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(xmdio): mdio@12a600 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,xmdio"; + reg =3D <0x12a600 0x10>; + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>, + <&CP11X_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(icu): interrupt-controller@1e0000 { + compatible =3D "marvell,cp110-icu"; + reg =3D <0x1e0000 0x440>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + CP11X_LABEL(icu_nsr): interrupt-controller@10 { + compatible =3D "marvell,cp110-icu-nsr"; + reg =3D <0x10 0x20>; + #interrupt-cells =3D <2>; + interrupt-controller; + msi-parent =3D <&gicp>; + }; + + CP11X_LABEL(icu_sei): interrupt-controller@50 { + compatible =3D "marvell,cp110-icu-sei"; + reg =3D <0x50 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + msi-parent =3D <&sei>; + }; + }; + + CP11X_LABEL(rtc): rtc@284000 { + compatible =3D "marvell,armada-8k-rtc"; + reg =3D <0x284000 0x20>, <0x284080 0x24>; + reg-names =3D "rtc", "rtc-soc"; + interrupts =3D <77 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + CP11X_LABEL(syscon0): system-controller@440000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x440000 0x2000>; + + CP11X_LABEL(clk): clock { + compatible =3D "marvell,cp110-clock"; + status =3D "disabled"; + #clock-cells =3D <2>; + }; + + CP11X_LABEL(gpio1): gpio@100 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x100>; + ngpios =3D <32>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 0= 32>; + interrupt-controller; + interrupts =3D <86 IRQ_TYPE_LEVEL_HIGH>, + <85 IRQ_TYPE_LEVEL_HIGH>, + <84 IRQ_TYPE_LEVEL_HIGH>, + <83 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + + CP11X_LABEL(gpio2): gpio@140 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x140>; + ngpios =3D <31>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 3= 2 31>; + interrupt-controller; + interrupts =3D <82 IRQ_TYPE_LEVEL_HIGH>, + <81 IRQ_TYPE_LEVEL_HIGH>, + <80 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + }; + + CP11X_LABEL(syscon1): system-controller@400000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x400000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + CP11X_LABEL(thermal): thermal-sensor@70 { + compatible =3D "marvell,armada-cp110-therm= al"; + reg =3D <0x70 0x10>; + interrupts-extended =3D + <&CP11X_LABEL(icu_sei) 116 IRQ_TYP= E_LEVEL_HIGH>; + #thermal-sensor-cells =3D <1>; + }; + }; + + CP11X_LABEL(usb3_0): usb@500000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x500000 0x4000>; + dma-coherent; + interrupts =3D <106 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, + <&CP11X_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(usb3_1): usb@510000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x510000 0x4000>; + dma-coherent; + interrupts =3D <105 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, + <&CP11X_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(sata0): sata@540000 { + compatible =3D "marvell,armada-8k-ahci"; + reg =3D <0x540000 0x30000>; + dma-coherent; + clocks =3D <&CP11X_LABEL(core_clk)>, + <&CP11X_LABEL(core_clk)>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + sata-port@0 { + interrupts =3D <109 IRQ_TYPE_LEVEL_HIGH>; + reg =3D <0>; + }; + + sata-port@1 { + interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>; + reg =3D <1>; + }; + }; + + CP11X_LABEL(xor0): xor@6a0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, + <&CP11X_LABEL(x2core_clk)>; + }; + + CP11X_LABEL(xor1): xor@6c0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, + <&CP11X_LABEL(x2core_clk)>; + }; + + CP11X_LABEL(spi0): spi@700600 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700600 0x50>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(spi1): spi@700680 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700680 0x50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(i2c0): i2c@701000 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <120 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(i2c1): i2c@701100 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701100 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <121 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(uart0): serial@702000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702000 0x100>; + reg-shift =3D <2>; + interrupts =3D <122 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(uart1): serial@702100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702100 0x100>; + reg-shift =3D <2>; + interrupts =3D <123 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(uart2): serial@702200 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702200 0x100>; + reg-shift =3D <2>; + interrupts =3D <124 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(uart3): serial@702300 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702300 0x100>; + reg-shift =3D <2>; + interrupts =3D <125 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP11X_LABEL(slow_io_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(nand_controller): nand@720000 { + /* + * Due to the limitation of the pins available + * this controller is only usable on the CPM + * for A7K and on the CPS for A8K. + */ + compatible =3D "marvell,armada-8k-nand-controller", + "marvell,armada370-nand-controller"; + reg =3D <0x720000 0x54>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <115 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(nand_clk)>, + <&CP11X_LABEL(x2core_clk)>; + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>; + status =3D "disabled"; + }; + + CP11X_LABEL(trng): trng@760000 { + compatible =3D "marvell,armada-8k-rng", + "inside-secure,safexcel-eip76"; + reg =3D <0x760000 0x7d>; + interrupts =3D <95 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(x2core_clk)>, + <&CP11X_LABEL(x2core_clk)>; + status =3D "okay"; + }; + + CP11X_LABEL(sdhci0): sdhci@780000 { + compatible =3D "marvell,armada-cp110-sdhci"; + reg =3D <0x780000 0x300>; + interrupts =3D <27 IRQ_TYPE_LEVEL_HIGH>; + clock-names =3D "core", "axi"; + clocks =3D <&CP11X_LABEL(sdio_clk)>, <&CP11X_LABEL= (core_clk)>; + dma-coherent; + status =3D "disabled"; + }; + + CP11X_LABEL(crypto): crypto@800000 { + compatible =3D "inside-secure,safexcel-eip197b"; + reg =3D <0x800000 0x200000>; + interrupts =3D <87 IRQ_TYPE_LEVEL_HIGH>, + <88 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <90 IRQ_TYPE_LEVEL_HIGH>, + <91 IRQ_TYPE_LEVEL_HIGH>, + <92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "mem", "ring0", "ring1", + "ring2", "ring3", "eip"; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(x2core_clk)>, + <&CP11X_LABEL(x2core_clk)>; + dma-coherent; + }; + }; + + CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>, + <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + /* non-prefetchable memory */ + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_= PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TY= PE_LEVEL_HIGH>; + interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>, + <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + /* non-prefetchable memory */ + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_= PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TY= PE_LEVEL_HIGH>; + interrupts =3D <24 IRQ_TYPE_LEVEL_HIGH>; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>, + <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + /* non-prefetchable memory */ + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_= PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TY= PE_LEVEL_HIGH>; + interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH>; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + /* 1 GHz fixed main PLL */ + CP11X_LABEL(mainpll): CP11X_LABEL(mainpll) { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1000000000>; + }; + + CP11X_LABEL(x2core_clk): CP11X_LABEL(x2core_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + CP11X_LABEL(core_clk): CP11X_LABEL(core_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + CP11X_LABEL(sdio_clk): CP11X_LABEL(sdio_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <2>; + clock-div =3D <5>; + }; + + CP11X_LABEL(nand_clk): CP11X_LABEL(nand_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <2>; + clock-div =3D <5>; + }; + + CP11X_LABEL(ppv2_clk): CP11X_LABEL(ppv2_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <3>; + }; + + CP11X_LABEL(slow_io_clk): CP11X_LABEL(slow_io_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP11X_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <4>; + }; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts deleted file mode 100644 index 9e4aa51..0000000 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (C) 2018 Marvell International Ltd. - * - * SPDX-License-Identifier: GPL-2.0 - * https://spdx.org/licenses - */ - -#include "cn9130-db.dtsi" - -/ { - model =3D "Model: Marvell CN9130 development board (CP NOR) setup(= A)"; - compatible =3D "marvell,cn9130-db-A", "marvell,armada-ap807-quad", - "marvell,armada-ap807"; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - aliases { - i2c0 =3D &cp0_i2c0; - ethernet0 =3D &cp0_eth0; - ethernet1 =3D &cp0_eth1; - ethernet2 =3D &cp0_eth2; - }; - - memory@00000000 { - device_type =3D "memory"; - reg =3D <0x0 0x0 0x0 0x80000000>; - }; -}; - -&uart0 { - status =3D "okay"; -}; - -/* on-board eMMC - U9 */ -&ap_sdhci0 { - pinctrl-names =3D "default"; - bus-width =3D <8>; - status =3D "okay"; - vqmmc-supply =3D <&ap0_reg_sd_vccq>; -}; - -/* - * CP related configuration - */ -&cp0_i2c0 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_i2c0_pins>; - status =3D "okay"; - clock-frequency =3D <100000>; -}; - -&cp0_i2c1 { - status =3D "okay"; -}; - -/* CON 28 */ -&cp0_sdhci0 { - status =3D "okay"; -}; - -/* U54 */ -&cp0_nand_controller { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&nand_pins>; - - nand@0 { - reg =3D <0>; - label =3D "main-storage"; - nand-rb =3D <0>; - nand-ecc-mode =3D "hw"; - nand-on-flash-bbt; - nand-ecc-strength =3D <8>; - nand-ecc-step-size =3D <512>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0 0x200000>; - }; - partition@200000 { - label =3D "Linux"; - reg =3D <0x200000 0xd00000>; - }; - partition@1000000 { - label =3D "Filesystem"; - reg =3D <0x1000000 0x3f000000>; - }; - }; - }; -}; - -/* U55 */ -&cp0_spi1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp0_spi0_pins>; - reg =3D <0x700680 0x50>, /* control */ - <0x2000000 0x1000000>; /* CS0 */ - status =3D "disabled"; - - spi-flash@0 { - #address-cells =3D <0x1>; - #size-cells =3D <0x1>; - compatible =3D "jedec,spi-nor"; - reg =3D <0x0>; - /* On-board MUX does not allow higher frequencies */ - spi-max-frequency =3D <40000000>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "U-Boot"; - reg =3D <0x0 0x200000>; - }; - - partition@400000 { - label =3D "Filesystem"; - reg =3D <0x200000 0xe00000>; - }; - }; - }; -}; - -/* SLM-1521-V2, CON6 */ -&cp0_pcie0 { - status =3D "okay"; - num-lanes =3D <4>; - num-viewport =3D <8>; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp0_comphy0 0 - &cp0_comphy1 0 - &cp0_comphy2 0 - &cp0_comphy3 0>; -}; - -&cp0_sata0 { - status =3D "okay"; - /* SLM-1521-V2, CON2 */ -}; - -&cp0_mdio { - status =3D "okay"; - phy0: ethernet-phy@0 { - reg =3D <0>; - }; - phy1: ethernet-phy@1 { - reg =3D <1>; - }; -}; - -&cp0_ethernet { - status =3D "okay"; -}; - -/* SLM-1521-V2, CON9 */ -&cp0_eth0 { - status =3D "okay"; - phy-mode =3D "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp0_comphy4 0>; - managed =3D "in-band-status"; - sfp =3D <&cp0_sfp_eth0>; -}; - -/* CON56 */ -&cp0_eth1 { - status =3D "okay"; - phy =3D <&phy0>; - phy-mode =3D "rgmii-id"; -}; - -/* CON57 */ -&cp0_eth2 { - status =3D "okay"; - phy =3D <&phy1>; - phy-mode =3D "rgmii-id"; -}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts new file mode 100644 index 0000000..747bf88 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marvell International Ltd. + * + * Device tree for the CN9130-DB board. + */ + +#include "cn9130.dtsi" + +/ { + model =3D "Marvell Armada CN9130-DB"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + gpio1 =3D &cp0_gpio1; + gpio2 =3D &cp0_gpio2; + i2c0 =3D &cp0_i2c0; + ethernet0 =3D &cp0_eth0; + ethernet1 =3D &cp0_eth1; + ethernet2 =3D &cp0_eth2; + spi1 =3D &cp0_spi0; + spi2 =3D &cp0_spi1; + }; + + memory@00000000 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x80000000>; + }; + + ap0_reg_sd_vccq: ap0_sd_vccq@0 { + compatible =3D "regulator-gpio"; + regulator-name =3D "ap0_sd_vccq"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&expander0 8 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x1 3300000 0x0>; + }; + + cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0-xhci0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy0: cp0_usb3_phy@0 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_vbus0>; + }; + + cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0-xhci1-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy1: cp0_usb3_phy@1 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_vbus1>; + }; + + cp0_reg_sd_vccq: cp0_sd_vccq@0 { + compatible =3D "regulator-gpio"; + regulator-name =3D "cp0_sd_vccq"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&expander0 15 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x1 + 3300000 0x0>; + }; + + cp0_reg_sd_vcc: cp0_sd_vcc@0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0_sd_vcc"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&expander0 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + cp0_sfp_eth0: sfp-eth@0 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&cp0_sfpp0_i2c>; + los-gpio =3D <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp0_module_expander1 10 GPIO_ACTIVE_LO= W>; + tx-disable-gpio =3D <&cp0_module_expander1 9 GPIO_ACTIVE_H= IGH>; + tx-fault-gpio =3D <&cp0_module_expander1 8 GPIO_ACTIVE_HIG= H>; + /* + * SFP cages are unconnected on early PCBs because of an t= he I2C + * lanes not being connected. Prevent the port for being + * unusable by disabling the SFP node. + */ + status =3D "disabled"; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +/* on-board eMMC - U9 */ +&ap_sdhci0 { + pinctrl-names =3D "default"; + bus-width =3D <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + vqmmc-supply =3D <&ap0_reg_sd_vccq>; + status =3D "okay"; +}; + +&cp0_crypto { + status =3D "disabled"; +}; + +&cp0_ethernet { + status =3D "okay"; +}; + +/* SLM-1521-V2, CON9 */ +&cp0_eth0 { + status =3D "disabled"; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy4 0>; + managed =3D "in-band-status"; + sfp =3D <&cp0_sfp_eth0>; +}; + +/* CON56 */ +&cp0_eth1 { + status =3D "okay"; + phy =3D <&phy0>; + phy-mode =3D "rgmii-id"; +}; + +/* CON57 */ +&cp0_eth2 { + status =3D "okay"; + phy =3D <&phy1>; + phy-mode =3D "rgmii-id"; +}; + +&cp0_gpio1 { + status =3D "okay"; +}; + +&cp0_gpio2 { + status =3D "okay"; +}; + +&cp0_i2c0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_i2c0_pins>; + clock-frequency =3D <100000>; + + /* U36 */ + expander0: pca953x@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + status =3D "okay"; + }; + + /* U42 */ + eeprom0: eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + pagesize =3D <0x20>; + }; + + /* U38 */ + eeprom1: eeprom@57 { + compatible =3D "atmel,24c64"; + reg =3D <0x57>; + pagesize =3D <0x20>; + }; +}; + +&cp0_i2c1 { + status =3D "okay"; + clock-frequency =3D <100000>; + + /* SLM-1521-V2 - U3 */ + i2c-mux@72 { /* verify address - depends on dpr */ + compatible =3D "nxp,pca9544"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x72>; + cp0_sfpp0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + /* U12 */ + cp0_module_expander1: pca9555@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + }; + + }; + }; +}; + +&cp0_mdio { + status =3D "okay"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + + phy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; + +/* U54 */ +&cp0_nand_controller { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nand_pins &nand_rb>; + + nand@0 { + reg =3D <0>; + label =3D "main-storage"; + nand-rb =3D <0>; + nand-ecc-mode =3D "hw"; + nand-on-flash-bbt; + nand-ecc-strength =3D <8>; + nand-ecc-step-size =3D <512>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0 0x200000>; + }; + partition@200000 { + label =3D "Linux"; + reg =3D <0x200000 0xd00000>; + }; + partition@1000000 { + label =3D "Filesystem"; + reg =3D <0x1000000 0x3f000000>; + }; + }; + }; +}; + +/* SLM-1521-V2, CON6 */ +&cp0_pcie0 { + status =3D "okay"; + num-lanes =3D <4>; + num-viewport =3D <8>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy0 0 + &cp0_comphy1 0 + &cp0_comphy2 0 + &cp0_comphy3 0>; +}; + +&cp0_sata0 { + status =3D "okay"; + + /* SLM-1521-V2, CON2 */ + sata-port@1 { + status =3D "okay"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy5 1>; + }; +}; + +/* CON 28 */ +&cp0_sdhci0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_sdhci_pins + &cp0_sdhci_cd_pins>; + bus-width =3D <4>; + cd-gpios =3D <&cp0_gpio2 11 GPIO_ACTIVE_LOW>; + no-1-8-v; + vqmmc-supply =3D <&cp0_reg_sd_vccq>; + vmmc-supply =3D <&cp0_reg_sd_vcc>; +}; + +/* U55 */ +&cp0_spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_spi0_pins>; + reg =3D <0x700680 0x50>; + + spi-flash@0 { + #address-cells =3D <0x1>; + #size-cells =3D <0x1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + /* On-board MUX does not allow higher frequencies */ + spi-max-frequency =3D <40000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot-0"; + reg =3D <0x0 0x200000>; + }; + + partition@400000 { + label =3D "Filesystem-0"; + reg =3D <0x200000 0xe00000>; + }; + }; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible =3D "marvell,cp115-standalone-pinctrl"; + + cp0_i2c0_pins: cp0-i2c-pins-0 { + marvell,pins =3D "mpp37", "mpp38"; + marvell,function =3D "i2c0"; + }; + cp0_i2c1_pins: cp0-i2c-pins-1 { + marvell,pins =3D "mpp35", "mpp36"; + marvell,function =3D "i2c1"; + }; + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { + marvell,pins =3D "mpp0", "mpp1", "mpp2", + "mpp3", "mpp4", "mpp5", + "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11"; + marvell,function =3D "ge0"; + }; + cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { + marvell,pins =3D "mpp44", "mpp45", "mpp46", + "mpp47", "mpp48", "mpp49", + "mpp50", "mpp51", "mpp52", + "mpp53", "mpp54", "mpp55"; + marvell,function =3D "ge1"; + }; + cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 { + marvell,pins =3D "mpp43"; + marvell,function =3D "gpio"; + }; + cp0_sdhci_pins: cp0-sdhi-pins-0 { + marvell,pins =3D "mpp56", "mpp57", "mpp58", + "mpp59", "mpp60", "mpp61"; + marvell,function =3D "sdio"; + }; + cp0_spi0_pins: cp0-spi-pins-0 { + marvell,pins =3D "mpp13", "mpp14", "mpp15", "mpp16= "; + marvell,function =3D "spi1"; + }; + nand_pins: nand-pins { + marvell,pins =3D "mpp15", "mpp16", "mpp17", "mpp18= ", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function =3D "dev"; + }; + nand_rb: nand-rb { + marvell,pins =3D "mpp13"; + marvell,function =3D "nf"; + }; + }; +}; + +&cp0_usb3_0 { + status =3D "okay"; + usb-phy =3D <&cp0_usb3_0_phy0>; + phy-names =3D "usb"; +}; + +&cp0_usb3_1 { + status =3D "okay"; + usb-phy =3D <&cp0_usb3_0_phy1>; + phy-names =3D "usb"; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi b/Silicon/= Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi index 97ea923..6187a34 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi @@ -1,126 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (C) 2018 Marvell International Ltd. + * Copyright (C) 2019 Marvell International Ltd. * - * SPDX-License-Identifier: GPL-2.0 - * https://spdx.org/licenses + * Device tree for the CN9130 SoC. */ =20 -/* - * Device Tree file for the CN 9130 SoC, made of an AP807 Quad and - * three CP110. - */ - -#include "armada-ap806-quad.dtsi" - -/ { - aliases { - gpio1 =3D &cp0_gpio1; - gpio2 =3D &cp0_gpio2; - spi1 =3D &cp0_spi0; - spi2 =3D &cp0_spi1; - }; -}; - -/* This defines used to calculate the base address of each CP */ -#define CP110_PCIE_MEM_SIZE(iface) ((iface =3D=3D 0) ? 0x1ff00000 : = 0xf00000) -#define CP110_PCIE_BUS_MEM_CFG (0x82000000) - -/* CP110-0 Settings */ -#define CP110_NAME cp0 -#define CP110_NUM 0 -#define CP110_BASE f2000000 -#define CP110_PCIE0_BASE f2600000 -#define CP110_PCIE1_BASE f2620000 -#define CP110_PCIE2_BASE f2640000 -#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface =3D=3D 0) ? 0xc0000000 : \ - (0xe0000000 + (iface - 1) * 0x100= 0000)) -#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) - -#include "armada-cp110.dtsi" - -#undef CP110_NUM -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE +#include "armada-ap807-quad.dtsi" =20 / { - model =3D "Marvell CN 9130"; + model =3D "Marvell Armada CN9130 SoC"; compatible =3D "marvell,cn9130", "marvell,armada-ap807-quad", - "marvell,armada-ap806"; + "marvell,armada-ap807"; }; =20 -&cp0_crypto { - status =3D "okay"; -}; - -&cp0_gpio1 { - status =3D "okay"; -}; - -&cp0_gpio2 { - status =3D "okay"; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible =3D "marvell,armada-7k-pinctrl"; - - cp0_devbus_pins: cp0-devbus-pins { - marvell,pins =3D "mpp15", "mpp16", "mpp17", - "mpp18", "mpp19", "mpp20", - "mpp21", "mpp22", "mpp23", - "mpp24", "mpp25", "mpp26", - "mpp27"; - marvell,function =3D "dev"; - }; +/* + * Instantiate the internal CP115 + */ =20 - cp0_i2c0_pins: cp0-i2c-pins-0 { - marvell,pins =3D "mpp37", "mpp38"; - marvell,function =3D "i2c0"; - }; - cp0_i2c1_pins: cp0-i2c-pins-1 { - marvell,pins =3D "mpp35", "mpp36"; - marvell,function =3D "i2c1"; - }; - cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { - marvell,pins =3D "mpp0", "mpp1", "mpp2", - "mpp3", "mpp4", "mpp5", - "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11"; - marvell,function =3D "ge0"; - }; - cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { - marvell,pins =3D "mpp44", "mpp45", "mpp46", - "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52", - "mpp53", "mpp54", "mpp55"; - marvell,function =3D "ge1"; - }; - cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 { - marvell,pins =3D "mpp43"; - marvell,function =3D "gpio"; - }; - cp0_sdhci_pins: cp0-sdhi-pins-0 { - marvell,pins =3D "mpp56", "mpp57", "mpp58", - "mpp59", "mpp60", "mpp61"; - marvell,function =3D "sdio"; - }; - cp0_spi0_pins: cp0-spi-pins-0 { - marvell,pins =3D "mpp13", "mpp14", "mpp15", "mpp16= "; - marvell,function =3D "spi1"; - }; - nand_pins: nand-pins { - marvell,pins =3D - "mpp15", "mpp16", "mpp17", "mpp18", "mpp19", - "mpp20", "mpp21", "mpp22", "mpp23", "mpp24", - "mpp25", "mpp26", "mpp27"; - marvell,function =3D "dev"; - }; - nand_rb: nand-rb { - marvell,pins =3D "mpp13"; - marvell,function =3D "nf"; - }; - }; -}; +#define CP11X_NAME cp0 +#define CP11X_BASE f2000000 +#define CP11X_PCIEx_MEM_BASE(iface) ((iface =3D=3D 0) ? 0xc0000000 : \ + 0xe0000000 + ((iface -= 1) * 0x1000000)) +#define CP11X_PCIEx_MEM_SIZE(iface) ((iface =3D=3D 0) ? 0x1ff00000 : 0xf00= 000) +#define CP11X_PCIE0_BASE f2600000 +#define CP11X_PCIE1_BASE f2620000 +#define CP11X_PCIE2_BASE f2640000 + +#include "armada-cp115.dtsi" + +#undef CP11X_NAME +#undef CP11X_BASE +#undef CP11X_PCIEx_MEM_BASE +#undef CP11X_PCIEx_MEM_SIZE +#undef CP11X_PCIE0_BASE +#undef CP11X_PCIE1_BASE +#undef CP11X_PCIE2_BASE diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts deleted file mode 100644 index f08a748..0000000 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2018 Marvell International Ltd. - * - * SPDX-License-Identifier: GPL-2.0 - * https://spdx.org/licenses - */ - -#include "cn9130-db-A.dts" -#include "cn9131-db.dtsi" - -/ { - model =3D "Marvell CN9131 development board (CP NOR) setup(A)"; - compatible =3D "marvell,cn9131-db-A", "marvell,armada-ap807-quad", - "marvell,armada-ap807"; -}; - -&cp1_ethernet { - status =3D "okay"; -}; - -/* CON50 */ -&cp1_eth0 { - status =3D "okay"; - phy-mode =3D "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy4 0>; - managed =3D "in-band-status"; - sfp =3D <&cp1_sfp_eth1>; -}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts similarity index 66% rename from Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi rename to Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts index 9c9dfb6..a321810 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts @@ -1,35 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (C) 2018 Marvell International Ltd. + * Copyright (C) 2019 Marvell International Ltd. * - * SPDX-License-Identifier: GPL-2.0 - * https://spdx.org/licenses + * Device tree for the CN9131-DB board. */ =20 -#undef CP110_NUM -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE -#undef CP110_PCIEx_CPU_MEM_BASE -#undef CP110_PCIEx_MEM_BASE - -/* CP110-1 Settings */ -#define CP110_NAME cp1 -#define CP110_NUM 1 -#define CP110_BASE f4000000 -#define CP110_PCIE0_BASE f4600000 -#define CP110_PCIE1_BASE f4620000 -#define CP110_PCIE2_BASE f4640000 -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000) -#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) - -#include "armada-cp110.dtsi" +#include "cn9130-db.dts" =20 / { - model =3D "Marvell CN9131 development board"; - compatible =3D "marvell,cn9131-db", "marvell,armada-ap807-quad", - "marvell,armada-ap807"; + model =3D "Marvell Armada CN9131-DB"; + compatible =3D "marvell,cn9131", "marvell,cn9130", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; =20 aliases { gpio3 =3D &cp1_gpio1; @@ -63,14 +44,55 @@ tx-fault-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; pinctrl-names =3D "default"; pinctrl-0 =3D <&cp1_sfp_pins>; + /* + * SFP cages are unconnected on early PCBs because of an t= he I2C + * lanes not being connected. Prevent the port for being + * unusable by disabling the SFP node. + */ status =3D "disabled"; }; }; =20 +/* + * Instantiate the first slave CP115 + */ + +#define CP11X_NAME cp1 +#define CP11X_BASE f4000000 +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +#define CP11X_PCIE0_BASE f4600000 +#define CP11X_PCIE1_BASE f4620000 +#define CP11X_PCIE2_BASE f4640000 + +#include "armada-cp115.dtsi" + +#undef CP11X_NAME +#undef CP11X_BASE +#undef CP11X_PCIEx_MEM_BASE +#undef CP11X_PCIEx_MEM_SIZE +#undef CP11X_PCIE0_BASE +#undef CP11X_PCIE1_BASE +#undef CP11X_PCIE2_BASE + &cp1_crypto { + status =3D "disabled"; +}; + +&cp1_ethernet { status =3D "okay"; }; =20 +/* CON50 */ +&cp1_eth0 { + status =3D "disabled"; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy4 0>; + managed =3D "in-band-status"; + sfp =3D <&cp1_sfp_eth1>; +}; + &cp1_gpio1 { status =3D "okay"; }; @@ -80,9 +102,9 @@ }; =20 &cp1_i2c0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&cp1_i2c0_pins>; - status =3D "okay"; clock-frequency =3D <100000>; }; =20 @@ -101,15 +123,20 @@ =20 &cp1_sata0 { status =3D "okay"; + + /* CON32 */ + sata-port@1 { + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy5 1>; + }; }; =20 /* U24 */ &cp1_spi1 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&cp1_spi0_pins>; - reg =3D <0x700680 0x50>, /* control */ - <0x2000000 0x1000000>; /* CS0 */ - status =3D "okay"; + reg =3D <0x700680 0x50>; =20 spi-flash@0 { #address-cells =3D <0x1>; @@ -125,12 +152,12 @@ #size-cells =3D <1>; =20 partition@0 { - label =3D "U-Boot"; + label =3D "U-Boot-1"; reg =3D <0x0 0x200000>; }; =20 partition@400000 { - label =3D "Filesystem"; + label =3D "Filesystem-1"; reg =3D <0x200000 0xe00000>; }; }; @@ -140,7 +167,7 @@ =20 &cp1_syscon0 { cp1_pinctrl: pinctrl { - compatible =3D "marvell,armada-7k-pinctrl"; + compatible =3D "marvell,cp115-standalone-pinctrl"; =20 cp1_i2c0_pins: cp1-i2c-pins-0 { marvell,pins =3D "mpp37", "mpp38"; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts deleted file mode 100644 index 724d7dc..0000000 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* - * copyright (c) 2019 marvell international ltd. - * - * spdx-license-identifier: gpl-2.0 - * https://spdx.org/licenses - */ - -#include "cn9131-db-A.dts" -#include "cn9132-db.dtsi" - -/ { - model =3D "Model: Marvell CN9132 development board (CP NOR) setup(= A)"; - compatible =3D "marvell,cn9132-db-A", "marvell,armada-ap807-quad", - "marvell,armada-ap807"; - - aliases { - gpio5 =3D &cp2_gpio1; - gpio6 =3D &cp2_gpio2; - ethernet5 =3D &cp2_eth0; - }; -}; - -&cp2_ethernet { - status =3D "okay"; -}; - -/* SLM-1521-V2, CON9 */ -&cp2_eth0 { - status =3D "okay"; - phy-mode =3D "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp2_comphy4 0>; - managed =3D "in-band-status"; - sfp =3D <&cp2_sfp_eth0>; -}; - -/* SLM-1521-V2, CON6 */ -&cp2_pcie0 { - status =3D "okay"; - num-lanes =3D <2>; - num-viewport =3D <8>; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp2_comphy0 0 - &cp2_comphy1 0>; -}; - -/* SLM-1521-V2, CON8 */ -&cp2_pcie2 { - status =3D "okay"; - num-lanes =3D <1>; - num-viewport =3D <8>; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp2_comphy5 2>; -}; - -&cp2_sata0 { - status =3D "okay"; -}; - -/* CON 2 on SLM-1683 - microSD */ -&cp2_sdhci0 { - status =3D "okay"; -}; - -/* SLM-1521-V2, CON11 */ -&cp2_usb3_1 { - status =3D "okay"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp2_comphy3 1>; -}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts similarity index 54% rename from Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi rename to Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts index 7dc6c6e..8cb08ca 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts @@ -1,35 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * copyright (c) 2019 marvell international ltd. + * Copyright (C) 2019 Marvell International Ltd. * - * spdx-license-identifier: gpl-2.0 - * https://spdx.org/licenses + * Device tree for the CN9132-DB board. */ =20 -#undef CP110_NUM -#undef CP110_NAME -#undef CP110_BASE -#undef CP110_PCIE0_BASE -#undef CP110_PCIE1_BASE -#undef CP110_PCIE2_BASE -#undef CP110_PCIEx_CPU_MEM_BASE -#undef CP110_PCIEx_MEM_BASE - -/* CP110-1 Settings */ -#define CP110_NAME cp2 -#define CP110_NUM 2 -#define CP110_BASE f6000000 -#define CP110_PCIE0_BASE f6600000 -#define CP110_PCIE1_BASE f6620000 -#define CP110_PCIE2_BASE f6640000 -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000) -#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) - -#include "armada-cp110.dtsi" +#include "cn9131-db.dts" =20 / { - model =3D "DB-CN-9132"; - compatible =3D "marvell,cn9132", "marvell,armada-ap807-quad", - "marvell,armada-ap807"; + model =3D "Marvell Armada CN9132-DB"; + compatible =3D "marvell,cn9132", "marvell,cn9131", "marvell,cn9130= ", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + aliases { + gpio5 =3D &cp2_gpio1; + gpio6 =3D &cp2_gpio2; + ethernet5 =3D &cp2_eth0; + }; =20 cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { compatible =3D "regulator-fixed"; @@ -71,18 +58,59 @@ cp2_sfp_eth0: sfp-eth0 { compatible =3D "sff,sfp"; i2c-bus =3D <&cp2_sfpp0_i2c>; - los-gpio =3D <&cp2_moudle_expander1 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio =3D <&cp2_moudle_expander1 10 GPIO_ACTIVE_LO= W>; - tx-disable-gpio =3D <&cp2_moudle_expander1 9 GPIO_ACTIVE_H= IGH>; - tx-fault-gpio =3D <&cp2_moudle_expander1 8 GPIO_ACTIVE_HIG= H>; + los-gpio =3D <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp2_module_expander1 10 GPIO_ACTIVE_LO= W>; + tx-disable-gpio =3D <&cp2_module_expander1 9 GPIO_ACTIVE_H= IGH>; + tx-fault-gpio =3D <&cp2_module_expander1 8 GPIO_ACTIVE_HIG= H>; + /* + * SFP cages are unconnected on early PCBs because of an t= he I2C + * lanes not being connected. Prevent the port for being + * unusable by disabling the SFP node. + */ status =3D "disabled"; }; }; =20 +/* + * Instantiate the second slave CP115 + */ + +#define CP11X_NAME cp2 +#define CP11X_BASE f6000000 +#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000)) +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +#define CP11X_PCIE0_BASE f6600000 +#define CP11X_PCIE1_BASE f6620000 +#define CP11X_PCIE2_BASE f6640000 + +#include "armada-cp115.dtsi" + +#undef CP11X_NAME +#undef CP11X_BASE +#undef CP11X_PCIEx_MEM_BASE +#undef CP11X_PCIEx_MEM_SIZE +#undef CP11X_PCIE0_BASE +#undef CP11X_PCIE1_BASE +#undef CP11X_PCIE2_BASE + &cp2_crypto { + status =3D "disabled"; +}; + +&cp2_ethernet { status =3D "okay"; }; =20 +/* SLM-1521-V2, CON9 */ +&cp2_eth0 { + status =3D "disabled"; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy4 0>; + managed =3D "in-band-status"; + sfp =3D <&cp2_sfp_eth0>; +}; + &cp2_gpio1 { status =3D "okay"; }; @@ -111,7 +139,7 @@ #size-cells =3D <0>; reg =3D <1>; /* U12 */ - cp2_moudle_expander1: pca9555@21 { + cp2_module_expander1: pca9555@21 { compatible =3D "nxp,pca9555"; pinctrl-names =3D "default"; gpio-controller; @@ -122,7 +150,38 @@ }; }; =20 +/* SLM-1521-V2, CON6 */ +&cp2_pcie0 { + status =3D "okay"; + num-lanes =3D <2>; + num-viewport =3D <8>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy0 0 + &cp2_comphy1 0>; +}; + +/* SLM-1521-V2, CON8 */ +&cp2_pcie2 { + status =3D "okay"; + num-lanes =3D <1>; + num-viewport =3D <8>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy5 2>; +}; + +&cp2_sata0 { + status =3D "okay"; + + /* SLM-1521-V2, CON4 */ + sata-port@0 { + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy2 0>; + }; +}; + +/* CON 2 on SLM-1683 - microSD */ &cp2_sdhci0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&cp2_sdhci_pins>; bus-width =3D <4>; @@ -132,7 +191,7 @@ =20 &cp2_syscon0 { cp2_pinctrl: pinctrl { - compatible =3D "marvell,armada-7k-pinctrl"; + compatible =3D "marvell,cp115-standalone-pinctrl"; =20 cp2_i2c0_pins: cp2-i2c-pins-0 { marvell,pins =3D "mpp37", "mpp38"; @@ -152,8 +211,11 @@ phy-names =3D "usb"; }; =20 +/* SLM-1521-V2, CON11 */ &cp2_usb3_1 { status =3D "okay"; usb-phy =3D <&cp2_usb3_0_phy1>; phy-names =3D "usb"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy3 1>; }; --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73024): https://edk2.groups.io/g/devel/message/73024 Mute This Topic: https://groups.io/mt/81438845/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-