From nobody Wed May 1 10:07:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72984+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72984+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616006560; cv=none; d=zohomail.com; s=zohoarc; b=ekcjApMJ/v5Y3chaonzLPoQY/cpbZfgobXd9G1fp6VuQAtghDs2ihf8zmWjX+Ww9hwsuHU+RZUFjniidTi+woGhet8v1c5EyWW1rXFXKNxuNx+xQImSqGULh7hv3hIRNxMKN202YqUgUm5PfJ4IcPPg/CT0LCanlVufQ2yrRwYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616006560; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=iN/tFkI6Z0O6Dt+F4ecHkl+qaA0/gBzGe7ztP7XRkc8=; b=KLPaDxSWyXssjks9nWAve8DovktGGRmTSpng0cJKkNfi69E+OTxhQj3yZj4J2juHjTeJOMSLgvOX79ToFZ3TTIr46JBSCI/ylycbKdX3G2z7NIz9dUMDqu7I8jORhi/CoWTwF+7AHBCnBE9TVWiJ5rqilfjcGhoV2JMq6pDCqUs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72984+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616006560803763.7415346806646; Wed, 17 Mar 2021 11:42:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id tjmjYY1788612xCdDKkzpwC1; Wed, 17 Mar 2021 11:42:40 -0700 X-Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by mx.groups.io with SMTP id smtpd.web08.3266.1615966021461984350 for ; Wed, 17 Mar 2021 00:27:03 -0700 X-Received: from localhost.localdomain (unknown [223.153.147.73]) by c1app7 (Coremail) with SMTP id BwINCgB3HOE4r1FgGIYZAA--.29335S3; Wed, 17 Mar 2021 15:26:55 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [edk2-devel] [PATCH v3 01/10] Silicon/Phytium: Added PlatformLib to FT2000/4 Date: Wed, 17 Mar 2021 15:26:38 +0800 Message-Id: <20210317072647.77340-2-jialing@phytium.com.cn> In-Reply-To: <20210317072647.77340-1-jialing@phytium.com.cn> References: <20210317072647.77340-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BwINCgB3HOE4r1FgGIYZAA--.29335S3 X-Coremail-Antispam: 1UD129KBjvAXoWDJr47XrW5tr17CF13tFW7twb_yoWxGry7Co WxGr10qr45Kr48A3y8GrsrKryxZwsIqF4jqr1rZ34xJF4ktrnxtryDtwnxXrs0y34qyr1D GrWrAa48JFW7tas7n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYZ7AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r18M28IrcIa0x kI8VCY1x0267AKxVWUXVWUCwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK67AK6r4xMxAIw2 8IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4l x2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwIxGrw CI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI 42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z2 80aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUYdbbDUUUU X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: tn81YN8XjJrhgFGHYkuIhc7fx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616006560; bh=io1I2IwaV7pXsWtB/atzOtvTxsl4P/Ew1b2eucQqHXw=; h=Cc:Date:From:Reply-To:Subject:To; b=rUtsMX8e+iGZBfR1i+WuYJpHYTzBfASgH+d1pA6AJz6sNkQJ+B1EI03GBab3Ug4dr0F B7froGWiNWcsMUnggKII+6rOP7LvKlpACLHqDXZnjUNyAtHJFk+esDol7n1xbe+sOPq7E axzLyBCqQUBPAuLlA6P/hQPYH6DJCOMgaUk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The PlatformLib supported the system library for FT2000/4 chip. Platform/Phytium: Added the dsc and fdf files of DurianPkg. v3: DurianPkg.dsc:Added OrderedCollectionLib to upstream changes in edk2, and some parameters omitted in V2 version. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm Reviewed-by: Leif Lindholm --- Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec = | 41 +++ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc = | 345 ++++++++++++++++++++ Platform/Phytium/DurianPkg/DurianPkg.dsc = | 298 +++++++++++++++++ Platform/Phytium/DurianPkg/DurianPkg.fdf = | 210 ++++++++++++ Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf = | 55 ++++ Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h = | 112 +++++++ Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c = | 137 ++++++++ Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c = | 156 +++++++++ Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHel= per.S | 76 +++++ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc = | 119 +++++++ 10 files changed, 1549 insertions(+) diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silico= n/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec new file mode 100644 index 0000000000..48f430c88d --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec @@ -0,0 +1,41 @@ +## @file +# This package provides common Phytium silicon modules. +# +# Copyright (C) 2020, Phytium Technology Co,Ltd. All rights reserved. +# +# SPDX-License-Identifier:BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x0001001b + PACKAGE_NAME =3D PhytiumCommnonPkg + PACKAGE_GUID =3D b34af0b4-3e7c-11eb-a9d0-0738806d2dec + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes] + Include # Root include for the package + +[Guids.common] + gPhytiumPlatformTokenSpaceGuid =3D { 0x8c3abed4, 0x1fc8, 0x46d3, { 0xb4,= 0x17, 0xa3, 0x22, 0x38, 0x14, 0xde, 0x76 } } + +[PcdsFixedAtBuild.common] + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0|UINT64|0x00000000 + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x0|UINT64|0x00000001 + + # + # PCI configuration address space + # + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x0|UINT64|0x00000002 + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x0|UINT64|0x00000003 + +[Protocols] diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc b/Si= licon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc new file mode 100644 index 0000000000..121fe0e7c5 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc @@ -0,0 +1,345 @@ +## @file +# This package provides common open source Phytium silicon modules. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved. +# +# SPDX-License-Identifier:BSD-2-Clause-Patent +# +## + + +[LibraryClasses.common] + # + # ARM Architectural Libraries + # + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.= inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatfo= rmStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/Ar= mGenericTimerPhyCounterLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + + AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.i= nf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMainte= nanceLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + !if $(TARGET) =3D=3D RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.= inf + !endif + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/Def= aultExceptionHandlerLib.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgent= TimerLibNull.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsing= Lib.inf + + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecu= reLibNull.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBoo= tManagerLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + + RngLib|MdePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf + + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib= .inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf + + # + # Scsi Requirements + # + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + + # + # USB Requirements + # + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + + # + # Networking Requirements + # + DpcLib|NetworkPkg/Library/DxeDpcLib/DxeDpcLib.inf + IpIoLib|NetworkPkg/Library/DxeIpIoLib/DxeIpIoLib.inf + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf + UdpIoLib|NetworkPkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + HttpLib|NetworkPkg/Library/DxeHttpLib/DxeHttpLib.inf + +[LibraryClasses.common.SEC] + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsB= aseLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCusto= mDecompressLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/Pre= PiHobListPointerLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM] + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + +[LibraryClasses.common.DXE_CORE] + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + + # + # UiApp dependencies + # + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + +[LibraryClasses.common.UEFI_DRIVER] + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + !if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf + !endif + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + + !if $(TARGET) !=3D RELEASE + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLi= bSerialPort.inf + !endif + + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R= untimeDxeReportStatusCodeLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf + +[LibraryClasses.AARCH64.DXE_RUNTIME_DRIVER] + EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSyste= mLib.inf + +[LibraryClasses.ARM, LibraryClasses.AARCH64] + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # + # Add support for GCC stack protector + # + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION= , LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVE= R] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + +[BuildOptions] + RVCT:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG + +[BuildOptions.AARCH64.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_AARCH64_DLINK_FLAGS =3D -z common-page-size=3D0x10000 + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|FALSE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + + # Use the Vector Table location in CpuDxe. We will not copy the Vector T= able at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangDeprecate|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + +[PcdsFixedAtBuild.common] + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE + +!if $(TARGET) =3D=3D RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free's + # DEBUG_PAGE 0x00000020 // Alloc & Free's + # DEBUG_INFO 0x00000040 // Verbose + # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNI Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // UNDI Driver + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|200000 + + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0= x04 +!endif + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000 +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000 +!endif + + # Default platform supported RFC 4646 languages: English & French & Chin= ese Simplified. + # Default Value of PlatformLangCodes Variable. + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US;= zh-Hans" + + # Default current RFC 4646 language: Chinese Simplified. + # Default Value of PlatformLang Variable. + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang|"en-US" + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + # + # ACPI Table Version + # + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|67 + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE + +[PcdsDynamicDefault.common.DEFAULT] + ## This PCD defines the video horizontal resolution. + # This PCD could be set to 0 then video resolution could be at highest = resolution. + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|640 + ## This PCD defines the video vertical resolution. + # This PCD could be set to 0 then video resolution could be at highest = resolution. + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|480 + + ## This PCD defines the Console output row and the default value is 80 a= ccording to UEFI spec. + # This PCD could be set to 0 then console output could be at max column= and max row. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|128 + ## This PCD defines the Console output column and the default value is 2= 5 according to UEFI spec. + # This PCD could be set to 0 then console output could be at max column= and max row. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|40 + + ## Specify the video horizontal resolution of text setup. + # @Prompt Video Horizontal Resolution of Text Setup + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + + ## Specify the video vertical resolution of text setup. + # @Prompt Video Vertical Resolution of Text Setup + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + + ## Specify the console output column of text setup. + # @Prompt Console Output Column of Text Setup + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|128 + ## Specify the console output row of text setup. + # @Prompt Console Output Row of Text Setup + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|40 + + ## The number of seconds that the firmware will wait before initiating t= he original default boot selection. + # A value of 0 indicates that the default boot selection is to be initi= ated immediately on boot. + # The value of 0xFFFF then firmware will wait for user input before boo= ting. + # @Prompt Boot Timeout (s) + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|5 diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc new file mode 100644 index 0000000000..b523ecd658 --- /dev/null +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -0,0 +1,298 @@ +## @file +# This package provides common open source Phytium Platform modules. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved. +# +# SPDX-License-Identifier:BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D DurianPkg + PLATFORM_GUID =3D 8f7ac876-3e7c-11eb-86cb-33f68535d613 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001c + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/Phytium/DurianPkg/DurianPkg.= fdf + +!include Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc + +[LibraryClasses.common] + # Phytium Platform library + ArmPlatformLib|Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformL= ib.inf + + # PL011 UART Driver and Dependency Libraries + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortL= ib.inf + PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartCloc= kLib.inf + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf + +[LibraryClasses.common.DXE_DRIVER] + + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Durian Platform" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"V1.0" + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0x101 + gArmTokenSpaceGuid.PcdArmPrimaryCore|0x0 + gArmPlatformTokenSpaceGuid.PcdCoreCount|4 + + # + # NV Storage PCDs. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xe00000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xe10000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xe20000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 + + # Size of the region used by UEFI in permanent memory (Reserved 64MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 + + # + # PL011 - Serial Terminal + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x28001000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|48000000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + + # + # ARM General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x29900000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x29980000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x29c00000 + + # System IO space + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0 + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x40000000 + + # + # System Memory (2GB ~ 4GB - 64MB), the top 64MB is reserved for + # PBF(the processor basic firmware, Mainly deals the initialization + # of the chip). + # + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7B000000 + + # Stack Size + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + + # + # Designware PCI Root Complex + # + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|28 + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x40000000 + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x10000000 + gArmTokenSpaceGuid.PcdPciBusMin|0 + gArmTokenSpaceGuid.PcdPciBusMax|255 + gArmTokenSpaceGuid.PcdPciIoBase|0x00000 + gArmTokenSpaceGuid.PcdPciIoSize|0xf00000 + gArmTokenSpaceGuid.PcdPciIoTranslation|0x50000000 + gArmTokenSpaceGuid.PcdPciMmio32Base|0x58000000 + gArmTokenSpaceGuid.PcdPciMmio32Size|0x28000000 + gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0 + gArmTokenSpaceGuid.PcdPciMmio64Base|0x1000000000 + gArmTokenSpaceGuid.PcdPciMmio64Size|0x1000000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # PCD database + # + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewC= ommandLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTre= eLib/BaseOrderedCollectionRedBlackTreeLib.inf + } + + ArmPlatformPkg/PrePi/PeiMPCore.inf { + + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + } + + # + # Dxe core entry + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + } + + # + # DXE driver + # + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + + # + # Common Arm Timer and Gic Components + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + # + # security system + # + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf + } + + # + # network, mod for https boot. + # + NetworkPkg/SnpDxe/SnpDxe.inf + NetworkPkg/DpcDxe/DpcDxe.inf + NetworkPkg/MnpDxe/MnpDxe.inf + NetworkPkg/ArpDxe/ArpDxe.inf + NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf + NetworkPkg/Ip4Dxe/Ip4Dxe.inf + NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf + NetworkPkg/Udp4Dxe/Udp4Dxe.inf + NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf + + NetworkPkg/Ip6Dxe/Ip6Dxe.inf + NetworkPkg/Udp6Dxe/Udp6Dxe.inf + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + NetworkPkg/TcpDxe/TcpDxe.inf + + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + + NetworkPkg/DnsDxe/DnsDxe.inf + NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + NetworkPkg/HttpDxe/HttpDxe.inf + + # + # FV Filesystem + # + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + + # + # Common Console Components + # ConIn,ConOut,StdErr + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf + + # + # Hii database init + # + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # + # Generic Watchdog Timer + # + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + # + # Usb Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # IDE/AHCI Support + # + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + + # + # PCI Support + # + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic= eDxe.inf + + # + # The following 2 module perform the same work except one operate variab= le. + # Only one of both should be put into fdf. + # + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + + # + # NVME Support + # + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf + diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf new file mode 100644 index 0000000000..9d75b072c6 --- /dev/null +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -0,0 +1,210 @@ +## @file +# This package provides common open source Phytium Platform modules. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved. +# +# SPDX-License-Identifier:BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.PHYTIUM] +BaseAddress =3D 0x88000000|gArmTokenSpaceGuid.PcdFdBaseAddress +Size =3D 0x01000000|gArmTokenSpaceGuid.PcdFdSize +ErasePolarity =3D 1 + +# This one is tricky, it must be: BlockSize * NumBlocks =3D Size +BlockSize =3D 0x10000 +NumBlocks =3D 0x100 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### + +0x00000000|0x200000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +BlockSize =3D 0x40 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 16 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + } + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + # + # Variable services + # + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i= nf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + + # + # SATA Controller + # + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + + # + # NVMe boot devices + # + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # Usb Support + # + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # NetWork + # + INF NetworkPkg/SnpDxe/SnpDxe.inf + INF NetworkPkg/DpcDxe/DpcDxe.inf + INF NetworkPkg/MnpDxe/MnpDxe.inf + INF NetworkPkg/ArpDxe/ArpDxe.inf + INF NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf + INF NetworkPkg/Ip4Dxe/Ip4Dxe.inf + INF NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf + INF NetworkPkg/Udp4Dxe/Udp4Dxe.inf + INF NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf + + # + # UEFI applications + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmPlatformPkg/PrePi/PeiMPCore.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } + +!include Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.in= f b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 0000000000..40c070767a --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,55 @@ +#/** @file +# Library for Phytium Platform. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D PlatformLib + FILE_GUID =3D fac08f56-40fe-11eb-a2a3-27b46864b1f3 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + ArmSmcLib + HobLib + +[Sources.common] + PlatformLib.c + PlatformLibMem.c + +[Sources.AARCH64] + AArch64/PhytiumPlatformHelper.S + +[Guids] + +[FixedPcd] + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax + gArmTokenSpaceGuid.PcdPciIoBase + gArmTokenSpaceGuid.PcdPciIoSize + gArmTokenSpaceGuid.PcdPciIoTranslation + gArmTokenSpaceGuid.PcdPciMmio32Base + gArmTokenSpaceGuid.PcdPciMmio32Size + gArmTokenSpaceGuid.PcdPciMmio32Translation + gArmTokenSpaceGuid.PcdPciMmio64Base + gArmTokenSpaceGuid.PcdPciMmio64Size + +[Pcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterfac= e.h b/Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h new file mode 100644 index 0000000000..c4395153a3 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h @@ -0,0 +1,112 @@ +/** @file + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SYSTEM_SERVICE_INTERFACE_H_ +#define SYSTEM_SERVICE_INTERFACE_H_ + +/* SMC function IDs for OEM Service queries */ +#define PHYTIUM_OEM_SVC_PSSI_VERSION 0x8200ff03 +#define PHYTIUM_OEM_SVC_PBF_VERSION 0x82000001 +#define PHYTIUM_OEM_SVC_CPU_VERSION 0xc2000002 +#define PHYTIUM_OEM_SVC_CPU_MAPS 0xc2000003 +#define PHYTIUM_OEM_SVC_CPU_CONF 0xc2000004 +#define PHYTIUM_OEM_SVC_MEM_REGIONS 0xc2000005 +#define PHYTIUM_OEM_SVC_MCU_DIMMS 0xc2000006 +#define PHYTIUM_OEM_SVC_PCI_CONTROLLER 0xc2000007 +#define PHYTIUM_OEM_SVC_HOST_BRIDGE 0xc2000008 +#define PHYTIUM_OEM_SVC_GET_FLASH_CMD 0xC200000C + +#define PHYTIUM_IOBASE_MASK 0xfffffff +#define PHYTIUM_MEMIO32_MASK 0xffffffff +#define PHYTIUM_MEMIO64_MASK 0xffffffffff + +#pragma pack(1) + +typedef struct { + UINT64 CpuMapCount; + UINT64 CpuMap[1]; +} PHYTIUM_CPU_MAP_INFO; + + +typedef struct { + UINT64 CpuFreq; // Hz + UINT64 CpuL3CacheSize; // Byte + UINT64 CpuL3CacheLineSize; // Byte +} PHYTIUM_CPU_COURE_INFO; + +typedef struct { + UINT64 CupVersion; //cpu version + PHYTIUM_CPU_COURE_INFO CpuCoreInfo; //cpu core info + PHYTIUM_CPU_MAP_INFO CpuMapInfo; //cpu map info +}PHYTIUM_CPU_INFO; + +typedef struct { + UINT64 MemSize; // MB + UINT64 MemDramId; + UINT64 MemModuleId; + UINT64 MemSerial; + UINT64 MemSlotNumber; + UINT64 MemFeatures; +} MCU_DIMM; + +#define MCU_DIMM_MAXCOUNT 2 + +typedef struct { + UINT64 MemFreq; // MHz + UINT64 MemDimmCount; + MCU_DIMM McuDimm[1]; +} MCU_DIMMS; + +typedef struct { + UINT64 MemStart; + UINT64 MemSize; + UINT64 MemNodeId; +} MEMORY_BLOCK; + +typedef struct { + UINT64 MemBlockCount; + MEMORY_BLOCK MemBlock[1]; +} MEMORY_INFO; + +typedef struct { + UINT8 PciLane; + UINT8 PciSpeed; + UINT8 Reserved[6]; +} PCI_BLOCK; + +typedef struct { + UINT64 PciCount; + PCI_BLOCK PciBlock[1]; +} PHYTIUM_PCI_CONTROLLER; + +typedef struct { + UINT8 BusStart; + UINT8 BusEnd; + UINT8 Reserved[6]; + UINT64 PciConfigBase; + UINT64 IoBase; + UINT64 IoSize; + UINT64 Mem32Base; + UINT64 Mem32Size; + UINT64 Mem64Base; + UINT64 Mem64Size; + UINT16 IntA; + UINT16 IntB; + UINT16 IntC; + UINT16 IntD; +} PCI_HOST_BLOCK; + +typedef struct { + UINT64 PciHostCount; + PCI_HOST_BLOCK PciHostBlock[1]; +} PHYTIUM_PCI_HOST_BRIDGE; + +#pragma pack () + + +#endif // SYSTEM_SERVICE_INTERFACE_H_ diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c = b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c new file mode 100644 index 0000000000..6a8d226574 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,137 @@ +/** @file + Library for Phytium platform. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +ARM_CORE_INFO mPhytiumMpCoreInfoTable[] =3D { + { + 0x0, 0x0, // Cluster 0, Core 0 + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + } +}; + +/* + This function geted the current Boot Mode. + + This function returns the boot reason on the platform. + + @return Return the current Boot Mode of the platform. + +*/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + + +/** + Initialize controllers that must setup in the normal world. + + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/= PlatformPeim + in the PEI phase. + + @retval EFI_SUCCESS ArmPlatformInitialize() is executed successf= ully. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + + +/** + This function Inited the system (or sometimes called permanent) memory. + + This memory is generally represented by the DRAM. + + @param[in] None. + + @retval None. + +**/ +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ + // Nothing to do here +} + + +/** + This function geted the information of core. + + @param[out] CoreCount The count of CoreInfoTable. + @param[out] ArmCoreTable The pointer of CoreInfoTable. + + @retval EFI_SUCCESS PrePeiCoreGetMpCoreInfo() is executed succes= sfully. + +**/ +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D PcdGet32 (PcdCoreCount); + *ArmCoreTable =3D mPhytiumMpCoreInfoTable; + + return EFI_SUCCESS; +} + +// +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is +// undefined in the contect of PrePeiCore +// +EFI_GUID mArmMpCoreInfoPpiGuid =3D ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D +{ + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + + +/** + This function geted the information of Ppitable. + + @param[out] PpiListSize The size of Ppitable. + @param[out] PpiList The pointer of Ppitable. + + @retval None. + +**/ +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem= .c b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 0000000000..7e54cb6e74 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,156 @@ +/** @file + Library of memory map for Phytium platform. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +// Number of Virtual Memory Map Descriptors +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 32 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UN= BUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR des= cribing a Physical-to- + Virtual Memory mapping. This array must b= e ended by a zero-filled + entry +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + MEMORY_BLOCK *MemBlock; + MEMORY_INFO *MemInfo; + ARM_SMC_ARGS ArmSmcArgs; + UINT32 MemBlockCnt; + UINT32 Index1; + UINT32 Index2; + + MemBlock =3D NULL; + MemInfo =3D NULL; + MemBlockCnt =3D 0; + Index1 =3D 0; + Index2 =3D 0; + CacheAttributes =3D ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + + ASSERT (VirtualMemoryMap !=3D NULL); + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages \ + (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DES= CRIPTOR) * \ + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + ResourceAttributes =3D + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + MemInfo =3D AllocatePages (1); + ASSERT (MemInfo !=3D NULL); + + ArmSmcArgs.Arg0 =3D PHYTIUM_OEM_SVC_MEM_REGIONS; + ArmSmcArgs.Arg1 =3D (UINTN) MemInfo; + ArmSmcArgs.Arg2 =3D EFI_PAGE_SIZE; + ArmCallSmc (&ArmSmcArgs); + if (ArmSmcArgs.Arg0 =3D=3D 0) { + MemBlockCnt =3D MemInfo->MemBlockCount; + MemBlock =3D MemInfo->MemBlock; + } else { + ASSERT (FALSE); + } + + //Soc Io Space + VirtualMemoryTable[Index1].PhysicalBase =3D PcdGet64 (PcdSystemIoBase); + VirtualMemoryTable[Index1].VirtualBase =3D PcdGet64 (PcdSystemIoBase); + VirtualMemoryTable[Index1].Length =3D PcdGet64 (PcdSystemIoSize); + VirtualMemoryTable[Index1].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // + // PCI Configuration Space + // + VirtualMemoryTable[++Index1].PhysicalBase =3D PcdGet64 (PcdPciConfigBas= e); + VirtualMemoryTable[Index1].VirtualBase =3D PcdGet64 (PcdPciConfigBas= e); + VirtualMemoryTable[Index1].Length =3D PcdGet64 (PcdPciConfigSiz= e); + VirtualMemoryTable[Index1].Attributes =3D ARM_MEMORY_REGION_ATTRIBU= TE_DEVICE; + + // + // PCI Memory Space + // + VirtualMemoryTable[++Index1].PhysicalBase =3D PcdGet64 (PcdPciIoBase) += PcdGet64 (PcdPciIoTranslation); + VirtualMemoryTable[Index1].VirtualBase =3D PcdGet64 (PcdPciIoBase) += PcdGet64 (PcdPciIoTranslation); + VirtualMemoryTable[Index1].Length =3D PcdGet64 (PcdPciIoSize); + VirtualMemoryTable[Index1].Attributes =3D ARM_MEMORY_REGION_ATTRIBU= TE_DEVICE; + + // + // PCI Memory Space + // + VirtualMemoryTable[++Index1].PhysicalBase =3D PcdGet32 (PcdPciMmio32Bas= e); + VirtualMemoryTable[Index1].VirtualBase =3D PcdGet32 (PcdPciMmio32Bas= e); + VirtualMemoryTable[Index1].Length =3D PcdGet32 (PcdPciMmio32Siz= e); + VirtualMemoryTable[Index1].Attributes =3D ARM_MEMORY_REGION_ATTRIBU= TE_DEVICE; + + // + // 64-bit PCI Memory Space + // + VirtualMemoryTable[++Index1].PhysicalBase =3D PcdGet64 (PcdPciMmio64Bas= e); + VirtualMemoryTable[Index1].VirtualBase =3D PcdGet64 (PcdPciMmio64Bas= e); + VirtualMemoryTable[Index1].Length =3D PcdGet64 (PcdPciMmio64Siz= e); + VirtualMemoryTable[Index1].Attributes =3D ARM_MEMORY_REGION_ATTRIBU= TE_DEVICE; + + //DDR + for (Index2 =3D 0; Index2 < MemBlockCnt; Index2++) { + VirtualMemoryTable[++Index1].PhysicalBase =3D MemBlock->MemStart; + VirtualMemoryTable[Index1].VirtualBase =3D MemBlock->MemStart; + VirtualMemoryTable[Index1].Length =3D MemBlock->MemSize; + VirtualMemoryTable[Index1].Attributes =3D CacheAttributes; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + MemBlock->MemStart, + MemBlock->MemSize + ); + + MemBlock++; + } + + // End of Table + VirtualMemoryTable[++Index1].PhysicalBase =3D 0; + VirtualMemoryTable[Index1].VirtualBase =3D 0; + VirtualMemoryTable[Index1].Length =3D 0; + VirtualMemoryTable[Index1].Attributes =3D (ARM_MEMORY_REGION_ATTRIBU= TES)0; + + + for (Index2 =3D 0; Index2 < Index1; Index2++) { + DEBUG ((DEBUG_ERROR, "PhysicalBase %12lx VirtualBase %12lx Length %12l= x Attributes %12lx\n",\ + VirtualMemoryTable[Index2].PhysicalBase, VirtualMemoryTable[Index2].= VirtualBase, \ + VirtualMemoryTable[Index2].Length, VirtualMemoryTable[Index2].Attrib= utes)); + } + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/Phytiu= mPlatformHelper.S b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64= /PhytiumPlatformHelper.S new file mode 100644 index 0000000000..cce23b7861 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatfo= rmHelper.S @@ -0,0 +1,76 @@ +# +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +#include +#include +#include +#include +#include + +.text +.align 2 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) + +PrimaryCoreMpid: .word 0x0 + + +ASM_PFX(ArmPlatformPeiBootAction): + // Save MPIDR_EL1[23:0] in a variable. + mov x20, x30 + bl ASM_PFX(ArmReadMpidr) + lsl w0, w0, #8 + lsr w0, w0, #8 + ldr x1, =3DPrimaryCoreMpid + str w0, [x1] + ret x20 + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + ldr x0, =3DPrimaryCoreMpid + ldr w0, [x0] + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + mov x20, x30 + bl ASM_PFX(ArmReadMpidr) + lsl w0, w0, #8 + lsr w0, w0, #8 + ldr x1, =3DPrimaryCoreMpid + ldr w1, [x1] + cmp w0, w1 + cset x0, eq + ret x20 + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 4) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc b/Si= licon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc new file mode 100644 index 0000000000..641266c601 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc @@ -0,0 +1,119 @@ +## @file +# This package provides common open source Phytium silicon modules. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved. +# +# SPDX-License-Identifier:BSD-2-Clause-Patent +# +## + +##########################################################################= ## +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section = # +##########################################################################= ## +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER =3D $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING=3D"$(MODULE_NAME)" Optional +# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N= UMBER) +# } +# } +# } +# +##########################################################################= ## + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR= UE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + UI STRING =3D"$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.BIOSINFO] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW BIN Align =3D 16 $(INF_OUTPUT)/$(MODULE_NAME).acpi + } + +[Rule.Common.UEFI_APPLICATION.UI] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"Enter Setup" + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72984): https://edk2.groups.io/g/devel/message/72984 Mute This Topic: https://groups.io/mt/81410916/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 10:07:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72981+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72981+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616006563; cv=none; d=zohomail.com; s=zohoarc; b=ihf/JoUrhfUzuCLz8gHme7HA4Nm1xgs+ncUrg30FafE8CNx429UPDXNX5KbxJuypa3giDM1u2dERY2deWU3GDrEpW7QyD6DpgPKD3xVNCIgYbbkHe4FyQgjDWzbAvD0GVBAJmZ853jhMG28Paz+Tupnp7W7SdB0DwOoikjvG/H8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616006563; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=84FOKqHL/gHkOddcHK4YKYMve3C3rKFEeehZ9GO/ZFI=; b=T74iMpU8pht60kP5SE9pcjomdXBGgyOWhcxIiVZhoBGI+OrBQcTlFmNGRkikSJZWvdlkgP7KY7eVNEQOXcCcS13uTYgQ1DzLwuw2YqWDydvOzgmQn9GbNJIldpbSLrPUzup+MPi35FIbkoQJUmPPV+z3YF8siWdIcGmuqgHRpgY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72981+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616006563071116.94831242153998; Wed, 17 Mar 2021 11:42:43 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id FwcGYY1788612xpGbrQF0VCz; Wed, 17 Mar 2021 11:42:42 -0700 X-Received: from zg8tmty1ljiyny4xntqumjca.icoremail.net (zg8tmty1ljiyny4xntqumjca.icoremail.net [165.227.154.27]) by mx.groups.io with SMTP id smtpd.web09.3181.1615966021037427322 for ; Wed, 17 Mar 2021 00:27:03 -0700 X-Received: from localhost.localdomain (unknown [223.153.147.73]) by c1app7 (Coremail) with SMTP id BwINCgB3HOE4r1FgGIYZAA--.29335S4; Wed, 17 Mar 2021 15:26:57 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [edk2-devel] [PATCH v3 02/10] Silicon/Phytium: Added Acpi support to FT2000/4 Date: Wed, 17 Mar 2021 15:26:39 +0800 Message-Id: <20210317072647.77340-3-jialing@phytium.com.cn> In-Reply-To: <20210317072647.77340-1-jialing@phytium.com.cn> References: <20210317072647.77340-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BwINCgB3HOE4r1FgGIYZAA--.29335S4 X-Coremail-Antispam: 1UD129KBjvAXoWDCryktF43ZF1xKr4xKFyDJrb_yoW7Jw1kJo WI93Z2g3y8Gr4kZw40v3yDKFWUur1fuayYywn3u398ZF9xXw13tF97Xa13Xryaqr1DKrnx GrWxta4rAF4xK34kn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYZ7AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r15M28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK67AK6r4xMxAIw2 8IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4l x2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwIxGrw CI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI 42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z2 80aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUeDGYDUUUU X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: qiNRnZaubauR5ppQhMufRvOsx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616006562; bh=DmUbt6KNgx8syedgYLAiFkfgqdQ//BkElSiuTmaQ+a0=; h=Cc:Date:From:Reply-To:Subject:To; b=aoWqKuzbFSqW1qMcW8MvkCrJEGcI8d87GvhCdScy1WRbcDMxGiaDx4OerFQk7RxGOlQ A/PaoqnHPXu7YwXo0R1xCAQ3r4ckCcVoKSn6gKO2L5MxMCbbGK8mgT8btExdYg3a3sSot o+5QKjrBwPsVkFSdzd8xZtLqZAY3dIL3gOs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Added Acpi driver and table to FT2000/4, the ACPI Tables providing library AcpiTables.inf uses a lot of information that is available in the form of PCDs for differnt platforms. v3: Optimize code to conform to specifications. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Platform/Phytium/DurianPkg/DurianPkg.dsc = | 6 + Platform/Phytium/DurianPkg/DurianPkg.fdf = | 7 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf = | 56 +++++ Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.i= nf | 53 +++++ Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h = | 80 +++++++ Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c = | 250 ++++++++++++++++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl = | 209 ++++++++++++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc = | 80 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl = | 85 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl = | 15 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl = | 65 +++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc = | 77 ++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc = | 83 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc = | 89 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc = | 67 ++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc = | 65 +++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc = | 219 +++++++++++++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc = | 73 ++++++ 18 files changed, 1579 insertions(+) diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index b523ecd658..6f38acb636 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -279,6 +279,12 @@ # MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf =20 + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf + Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe= .inf =20 # # Bds diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf index 9d75b072c6..f435f7cb51 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -111,6 +111,13 @@ READ_LOCK_STATUS =3D TRUE =20 INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf =20 + # + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF RuleOverride=3DACPITABLE Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTab= les/AcpiTables.inf + INF Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatfor= mDxe.inf + # # Multiple Console IO support # diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf = b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000000..e3fd86f197 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf @@ -0,0 +1,56 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D AcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + AcpiSsdtRootPci.asl + Dsdt/Dsdt.asl + Fadt.aslc + Iort.aslc + Gtdt.aslc + Madt.aslc + Mcfg.aslc + Pptt.aslc + Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gArmPlatformTokenSpaceGuid.PL011UartClkInHz + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PcdWatchdogCount diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiP= latformDxe.inf b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/A= cpiPlatformDxe.inf new file mode 100644 index 0000000000..0f6d46fdba --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform= Dxe.inf @@ -0,0 +1,53 @@ +#/** @file +# Sample ACPI Platform Driver. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D AcpiPlatform + FILE_GUID =3D d51068e8-40dc-11eb-9322-1f6d234e9e6e + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D AcpiPlatformEntryPoint + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Sources] + AcpiPlatform.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + DxeServicesLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Guids] + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicRedistributorsBase + +[Depex] + gEfiAcpiTableProtocolGuid diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h b/Silicon/= Phytium/PhytiumCommonPkg/Include/Platform.h new file mode 100644 index 0000000000..e34df30aa0 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h @@ -0,0 +1,80 @@ +/** @file + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PLATFORM_H_ +#define PLATFORM_H_ + +#include + +#define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) = \ + { = \ + EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACP= I_RESERVED_WORD, \ + GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD = \ + } + +#define EFI_ACPI_5_1_GICR_STRUCTURE_INIT( = \ + GicRBase, GicRlength) = \ + { = \ + EFI_ACPI_5_1_GICR, sizeof (EFI_ACPI_5_1_GICR_STRUCTURE), EFI_ACPI_RESE= RVED_WORD, \ + GicRBase, GicRlength = \ + } + +#define EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT( = \ + ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) = \ + { = \ + 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , = \ + ACPIProcessorUID, Flags, ClockDomain = \ + } + +#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( = \ + ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHig= h, Flags) \ + { = \ + 1, sizeof (EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , E= FI_ACPI_RESERVED_WORD, \ + AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESER= VED_DWORD, Flags, \ + EFI_ACPI_RESERVED_QWORD = \ + } + +#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, = PmuIrq, \ + GicBase, GicVBase, GicHBase, GsivId, GicRBase, ProcessorPowerEfficienc= yClass) \ + { = \ + EFI_ACPI_6_1_GIC, sizeof (EFI_ACPI_6_1_GIC_STRUCTURE), EFI_ACPI_RESERV= ED_WORD, \ + GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, = \ + GsivId, GicRBase, Mpidr, ProcessorPowerEfficiencyClass, {0, 0, 0} = \ + } + +#define EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDis= tVector, GicVersion) \ + { = \ + EFI_ACPI_6_1_GICD, sizeof (EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE), EF= I_ACPI_RESERVED_WORD, \ + GicDistHwId, GicDistBase, GicDistVector, GicVersion, = \ + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYT= E} \ + } + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_PHYTIUM_OEM_ID 'F','T','-','L','T','D' = // OEMID 6 bytes long +#define EFI_ACPI_PHYTIUM_OEM_TABLE_ID SIGNATURE_64('P','H','Y','T','I'= ,'U','M',' ') // OEM table id 8 bytes long +#define EFI_ACPI_PHYTIUM_OEM_REVISION 0x20201111 +#define EFI_ACPI_PHYTIUM_CREATOR_ID SIGNATURE_32('P','H','Y','T') +#define EFI_ACPI_PHYTIUM_CREATOR_REVISION 0x20201111 + +// A macro to initialise the common header part of EFI ACPI tables as defi= ned by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define PHYTIUM_ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + { EFI_ACPI_PHYTIUM_OEM_ID }, /* UINT8 OemId[6] */ \ + EFI_ACPI_PHYTIUM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_PHYTIUM_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_PHYTIUM_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_PHYTIUM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#endif // PLATFORM_H_ diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiP= latform.c b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPl= atform.c new file mode 100644 index 0000000000..c48ed74f53 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform= .c @@ -0,0 +1,250 @@ +/** @file + Sample ACPI Platform Driver. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI tab= le + storage file. + + @param[out] Instance Return pointer to the first instance of th= e protocol. + + @return EFI_SUCCESS The function completed successfully. + + @return EFI_NOT_FOUND The protocol could not be located. + + @return EFI_OUT_OF_RESOURCES There are not enough resources to find the= protocol. + +**/ +EFI_STATUS +LocateFvInstanceWithTables ( + OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN Index; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance; + + FvStatus =3D 0; + + // + // Locate protocol. + // + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + + // + // Looking for FV with ACPI storage file + // + + for (Index =3D 0; Index < NumberOfHandles; Index++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **)&FvInstance + ); + ASSERT_EFI_ERROR (Status); + + // + // See if it has the ACPI storage file + // + Status =3D FvInstance->ReadFile ( + FvInstance, + (EFI_GUID *)PcdGetPtr (PcdAcpiTableStorageFile), + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (Status =3D=3D EFI_SUCCESS) { + *Instance =3D FvInstance; + break; + } + } + + // + // Free any allocated buffers + // + gBS->FreePool (HandleBuffer); + + return Status; +} + + +/** + This function calculates and updates an UINT8 checksum. + + @param[in] Buffer Pointer to buffer to checksum. + + @param[in] Size Number of bytes to checksum. + +**/ +VOID +AcpiPlatformChecksum ( + IN UINT8 *Buffer, + IN UINTN Size + ) +{ + UINTN ChecksumOffset; + + ChecksumOffset =3D OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); + + // + // Set checksum to 0 first + // + Buffer[ChecksumOffset] =3D 0; + + // + // Update checksum value + // + Buffer[ChecksumOffset] =3D CalculateCheckSum8 (Buffer, Size); +} + + +/** + This function is the entrypoint of the acpi platform. + + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. + + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + + @retval other Some error occurs when executing this entry po= int. + +**/ +EFI_STATUS +EFIAPI +AcpiPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + INTN Instance; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINTN TableHandle; + UINT32 FvStatus; + UINTN TableSize; + UINTN Size; + + Instance =3D 0; + CurrentTable =3D NULL; + TableHandle =3D 0; + + // + // Find the AcpiTable protocol + // + Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID = **)&AcpiTable); + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + + // + // Locate the firmware volume protocol + // + Status =3D LocateFvInstanceWithTables (&FwVol); + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + // + // Read tables from the storage file. + // + while (Status =3D=3D EFI_SUCCESS) { + + Status =3D FwVol->ReadSection ( + FwVol, + (EFI_GUID *)PcdGetPtr (PcdAcpiTableStorageFile), + EFI_SECTION_RAW, + Instance, + (VOID **)&CurrentTable, + &Size, + &FvStatus + ); + if ( ! EFI_ERROR (Status)) { + // + // Add the table + // + TableHandle =3D 0; + + TableSize =3D ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length; + ASSERT (Size >=3D TableSize); + + // + // Checksum ACPI table + // + AcpiPlatformChecksum ((UINT8 *)CurrentTable, TableSize); + + // + // Install ACPI table + // + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + TableSize, + &TableHandle + ); + + // + // Free memory allocated by ReadSection + // + gBS->FreePool (CurrentTable); + + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + + // + // Increment the instance + // + Instance++; + CurrentTable =3D NULL; + } + } + + return EFI_SUCCESS; +} + diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci= .asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl new file mode 100644 index 0000000000..667f8cc8fb --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl @@ -0,0 +1,209 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#define LNK_DEVICE(Unique_Id, Link_Name, irq) = \ + Device (Link_Name) { = \ + Name (_HID, EISAID ("PNP0C0F")) = \ + Name (_UID, Unique_Id) = \ + Name (_PRS, ResourceTemplate () { = \ + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { irq }= \ + }) = \ + Method (_CRS, 0) { Return (_PRS) } = \ + Method (_SRS, 1) { } = \ + Method (_DIS) { } = \ + } + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ + Address, \ + Pin, \ + Link, \ + Zero \ + } + +#define ROOT_PRT_ENTRY(Dev, Pin, Link) PRT_ENTRY(Dev * 0x10000 + 0xFFFF,= Pin, Link) + + +DefinitionBlock ("SsdtPci.aml", "SSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACPI_= PHYTIUM_OEM_REVISION) { + Scope (_SB) { + // + // PCI Root Complex + // + LNK_DEVICE (1, LNKA, 60) + LNK_DEVICE (2, LNKB, 61) + LNK_DEVICE (3, LNKC, 62) + LNK_DEVICE (4, LNKD, 63) + + // reserve ECAM memory range + Device (RES0) + { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 0) + Name (_CRS, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, Cach= eable, ReadWrite, + 0x0, // Granularity + 0x40000000, // Range Minimum + 0x4FFFFFFF, // Range Maximum + 0, // Translation Offset + 0x10000000, // Length + ,,) + }) + } + + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, 0) // PCI Base Bus Number + Name (_CCA, 1) + + // Root Complex + Device (RP0) { + Name (_ADR, 0x00000000) // Dev 0, Func 0 + } + // PCI Routing Table + Name (_PRT, Package () { + ROOT_PRT_ENTRY (0, 0, LNKA), // INTA + ROOT_PRT_ENTRY (0, 1, LNKB), // INTB + ROOT_PRT_ENTRY (0, 2, LNKC), // INTC + ROOT_PRT_ENTRY (0, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (1, 0, LNKA), // INTA + ROOT_PRT_ENTRY (1, 1, LNKB), // INTB + ROOT_PRT_ENTRY (1, 2, LNKC), // INTC + ROOT_PRT_ENTRY (1, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (2, 0, LNKA), // INTA + ROOT_PRT_ENTRY (2, 1, LNKB), // INTB + ROOT_PRT_ENTRY (2, 2, LNKC), // INTC + ROOT_PRT_ENTRY (2, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (3, 0, LNKA), // INTA + ROOT_PRT_ENTRY (3, 1, LNKB), // INTB + ROOT_PRT_ENTRY (3, 2, LNKC), // INTC + ROOT_PRT_ENTRY (3, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (4, 0, LNKA), // INTA + ROOT_PRT_ENTRY (4, 1, LNKB), // INTB + ROOT_PRT_ENTRY (4, 2, LNKC), // INTC + ROOT_PRT_ENTRY (4, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (5, 0, LNKA), // INTA + ROOT_PRT_ENTRY (5, 1, LNKB), // INTB + ROOT_PRT_ENTRY (5, 2, LNKC), // INTC + ROOT_PRT_ENTRY (5, 3, LNKD), // INTD + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x58000000, // Min Base Address + 0x7FFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x28000000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x1000000000, // Min Base Address + 0x1FFFFFFFFF, // Max Base Address + 0x0000000000, // Translate + 0x1000000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x00000000, // Min Base Address + 0x00efffff, // Max Base Address + 0x50000000, // Translate + 0x00f00000, // Length + ,,, TypeTranslation + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + // + // OS Control Handoff + // + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + /* + See [1] 6.2.10, [2] 4.5 + */ + Method (_OSC, 4) { + // Check for proper UUID + If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))= ) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3, 0, CDW1) + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // Save Capabilities DWord2 & 3 + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + And (CTRL, 0x1E, CTRL) // Mask bit 0 (and undefined bits) + } + + // Do not allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And (CTRL, 0x10, CTRL) + + If (LNotEqual (Arg1, One)) { // Unknown revision + Or (CDW1, 0x08, CDW1) + } + + If (LNotEqual (CDW3, CTRL)) { // Capabilities bits were masked + Or (CDW1, 0x10, CDW1) + } + // Update DWORD3 in the buffer + Store (CTRL, CDW3) + Return (Arg3) + } Else { + Or (CDW1, 4, CDW1) // Unrecognized UUID + Return (Arg3) + } + } + } + } +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc b/Sil= icon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc new file mode 100644 index 0000000000..5349f6364b --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc @@ -0,0 +1,80 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +#define NUMBER_DEBUG_DEVICE_INFO 1 +#define NUMBER_OF_GENERIC_ADDRESS 1 +#define NAMESPACE_STRING_SIZE 8 + +#pragma pack(1) + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS= ]; + UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS]; + CHAR8 NamespaceString[NAMESPACE_STRING_SIZE]; +} EFI_ACPI_DBG2_DDI_STRUCT; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc; + EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO]; +} EFI_ACPI_DEBUG_PORT_2_TABLE; + +#pragma pack() + +EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 =3D { + { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_DEBUG_PORT_2_TABLE, + EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION + ), + OFFSET_OF (EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi), + NUMBER_DEBUG_DEVICE_INFO + }, + { + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (EFI_ACPI_DBG2_DDI_STRUCT), + NUMBER_OF_GENERIC_ADDRESS, + NAMESPACE_STRING_SIZE, + OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString), + 0, + 0, + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART, + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, + OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, Address), + OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, AddressSize), + }, + { + { + EFI_ACPI_6_1_SYSTEM_MEMORY, + 32, + 0, + EFI_ACPI_6_1_DWORD, + FixedPcdGet64 (PcdSerialRegisterBase) + } + }, + { + 0x1000 + }, + "COM0" + } + } +}; + +VOID * CONST ReferenceAcpiTable =3D &Dbg2; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl b/= Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl new file mode 100644 index 0000000000..219a129fa5 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl @@ -0,0 +1,85 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope (_SB) +{ + Device (CLU0) { + Name (_HID, "ACPI0010") + Name (_UID, 0) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c0"}, + Package () {"clock-domain", 0}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c0"}, + Package () {"clock-domain", 0}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + } + + Device (CLU1) { + Name (_HID, "ACPI0010") + Name (_UID, 1) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c1"}, + Package () {"clock-domain", 1}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c1"}, + Package () {"clock-domain", 1}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + } +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl b= /Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl new file mode 100644 index 0000000000..b21431ca36 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl @@ -0,0 +1,15 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACP= I_PHYTIUM_OEM_REVISION) { + include ("Cpu.asl") + include ("Uart.asl") +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl b= /Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl new file mode 100644 index 0000000000..25752036b5 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl @@ -0,0 +1,65 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope (_SB) +{ + //UART 0 + Device (UAR0) { + Name (_HID, "ARMH0011") + Name (_UID, 0) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28000000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 38 } + }) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + //UART 1 + Device (UAR1) { + Name (_HID, "ARMH0011") + Name (_UID, 1) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28001000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {39} + }) + + Method (_STA, 0, NotSerialized) { Return (0x0F) } + } + + //UART 2 + Device (UAR2) { + Name (_HID, "ARMH0011") + Name (_UID, 2) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28002000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {40} + }) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + //UART 3 + Device (UAR3) { + Name (_HID, "ARMH0011") + Name (_UID, 3) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28003000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {41} + }) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc b/Sil= icon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc new file mode 100644 index 0000000000..10612c1368 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc @@ -0,0 +1,77 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, = // UINT32 FirmwareCtrl + 0, = // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, = // UINT8 Reserved0 + EFI_ACPI_6_1_PM_PROFILE_ENTERPRISE_SERVER, = // UINT8 PreferredPmProfile + 0, = // UINT16 SciInt + 0, = // UINT32 SmiCmd + 0, = // UINT8 AcpiEnable + 0, = // UINT8 AcpiDisable + 0, = // UINT8 S4BiosReq + 0, = // UINT8 PstateCnt + 0, = // UINT32 Pm1aEvtBlk + 0, = // UINT32 Pm1bEvtBlk + 0, = // UINT32 Pm1aCntBlk + 0, = // UINT32 Pm1bCntBlk + 0, = // UINT32 Pm2CntBlk + 0, = // UINT32 PmTmrBlk + 0, = // UINT32 Gpe0Blk + 0, = // UINT32 Gpe1Blk + 0, = // UINT8 Pm1EvtLen + 0, = // UINT8 Pm1CntLen + 0, = // UINT8 Pm2CntLen + 0, = // UINT8 PmTmrLen + 0, = // UINT8 Gpe0BlkLen + 0, = // UINT8 Gpe1BlkLen + 0, = // UINT8 Gpe1Base + 0, = // UINT8 CstCnt + 0, = // UINT16 PLvl2Lat + 0, = // UINT16 PLvl3Lat + 0, = // UINT16 FlushSize + 0, = // UINT16 FlushStride + 0, = // UINT8 DutyOffset + 0, = // UINT8 DutyWidth + 0, = // UINT8 DayAlrm + 0, = // UINT8 MonAlrm + 0, = // UINT8 Century + 0, = // UINT16 IaPcBootArch + 0, = // UINT8 Reserved1 + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, = // UINT32 Flags + NULL_GAS, // EFI_A= CPI_6_1__GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8= ResetValue + EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT1= 6 ArmBootArchFlags + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8= MinorRevision + 0, // UINT6= 4 XFirmwareCtrl + 0, // UINT6= 4 XDsdt + NULL_GAS, // EFI_ACPI_6= _1__GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6= _1__GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6= _1__GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6= _1__GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6= _1__GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6= _1__GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6= _1__GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6= _1__GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6= _1__GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6= _1__GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0 // UINT64 = Hypervisor Vendor Identify +}; + +VOID * CONST ReferenceAcpiTable =3D &Fadt; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc b/Sil= icon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc new file mode 100644 index 0000000000..67468db2d4 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc @@ -0,0 +1,83 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY= _MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERR= UPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INT= ERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INT= ERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_ALWAYS_ON_CAPABILITY EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAY= S_ON_CAPABILITY + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LE= VEL_TRIGGERED \ + | EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_= ON_CAPABILITY) + +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[2]; +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES; + +#pragma pack () + +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt =3D { + { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddre= ss + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1Time= rGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1Time= rFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1T= imerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1T= imerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerG= SIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerF= lags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2T= imerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2T= imerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePh= ysicalAddress + 2, + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) + }, + + { + { + 1, //Type + 28, //Size of this structure + 0, //reserved + 0x2800a000, //RefreshFrame Physical Address + 0x2800b000, //WatchdogControlFrame Physical Address + 48, //Watchdog Timer GSIV + 0, //Watchdog Timer Flags high level + }, + + { + 1, + 28, + 0, + 0x28016000, + 0x28017000, + 49, + 0, + } + } +}; + +VOID * CONST ReferenceAcpiTable =3D &Gtdt; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc b/Sil= icon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc new file mode 100644 index 0000000000..4239499b68 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc @@ -0,0 +1,89 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node; + UINT32 Identifiers[1]; +} PHYTIUM_ITS_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; +} PHYTIUM_RC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; + PHYTIUM_ITS_NODE ItsNode; + PHYTIUM_RC_NODE RcNode[1]; +} PHYTIUM_IO_REMAPPING_STRUCTURE; + +#define __PHYTIUM_ID_MAPPING(In, Num, Out, Ref, Flags) \ + { \ + In, \ + Num, \ + Out, \ + FIELD_OFFSET (PHYTIUM_IO_REMAPPING_STRUCTURE, Ref), \ + Flags \ + } + +STATIC PHYTIUM_IO_REMAPPING_STRUCTURE Iort =3D { + { + PHYTIUM_ACPI_HEADER (EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, + PHYTIUM_IO_REMAPPING_STRUCTURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION), + 2, // NumNodes + sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0 // Reserved + }, { + // ItsNode + { + { + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type + sizeof (PHYTIUM_ITS_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x0, // NumIdMappin= gs + 0x0, // IdReference + }, + 1, + }, { + 0x0 + }, + }, { + { + // PciRcNode + { + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type + sizeof (PHYTIUM_RC_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x1, // NumIdMapp= ings + FIELD_OFFSET (PHYTIUM_RC_NODE, RcIdMapping), // IdReferen= ce + }, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCohe= rent + 0x0, // Allocatio= nHints + 0x0, // Reserved + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM, // MemoryAcc= essFlags + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttrib= ute + 0x0, // PciSegmen= tNumber + }, + __PHYTIUM_ID_MAPPING (0x0, 0xffff, 0x0, ItsNode, 0), + } + } +}; +#pragma pack() +# +VOID * CONST ReferenceAcpiTable =3D &Iort; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc b/Sil= icon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc new file mode 100644 index 0000000000..ef6d94837f --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc @@ -0,0 +1,67 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + + +#define PLATFORM_GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (Core= Id)) + +#define EFI_GICC_STRUCTURE(AcpiCpuUid, Mpidr, GicRBaseOffset) = \ + EFI_ACPI_6_1_GICC_STRUCTURE_INIT(0, AcpiCpuUid, Mpidr, EFI_ACPI_6_1_G= IC_ENABLED, 23, \ + FixedPcdGet64(PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInte= rruptInterfaceBase) + 0x20000, \ + FixedPcdGet64(PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet= 64 (PcdGicRedistributorsBase) + GicRBaseOffset, 0) +#define CORE_NUM 4 +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[CORE= _NUM]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[1]; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +// +// Multiple APIC Description Table +// +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { + { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + EFI_GICC_STRUCTURE (0x00, PLATFORM_GET_MPID (0x00, 0), 0x000000), + EFI_GICC_STRUCTURE (0x01, PLATFORM_GET_MPID (0x00, 1), 0x020000), + EFI_GICC_STRUCTURE (0x02, PLATFORM_GET_MPID (0x01, 0), 0x040000), + EFI_GICC_STRUCTURE (0x03, PLATFORM_GET_MPID (0x01, 1), 0x060000), + }, + + EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT (0, FixedPcdGet32 (PcdGicDistributorBa= se), 0, 0x3), + { + EFI_ACPI_6_1_GIC_ITS_INIT (0, FixedPcdGet64 (PcdGicDistributorBase) + = 0x20000), + } +}; + +VOID * CONST ReferenceAcpiTable =3D &Madt; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc b/Sil= icon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc new file mode 100644 index 0000000000..34eebd6aee --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc @@ -0,0 +1,65 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#define ACPI_6_1_MCFG_VERSION 0x1 + +#pragma pack(1) +typedef struct +{ + UINT64 BaseAddress; + UINT16 SegGroupNum; + UINT8 StartBusNum; + UINT8 EndBusNum; + UINT32 Reserved2; +} EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE; + +typedef struct +{ + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved1; +} EFI_ACPI_6_1_MCFG_TABLE_CONFIG; + +typedef struct +{ + EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[1]; +} EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; +#pragma pack() + +EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=3D +{ + { + { + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDR= ESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_T= ABLE), + ACPI_6_1_MCFG_VERSION, + 0x00, // Checksum will b= e updated at runtime + {EFI_ACPI_PHYTIUM_OEM_ID}, + EFI_ACPI_PHYTIUM_OEM_TABLE_ID, + EFI_ACPI_PHYTIUM_OEM_REVISION, + EFI_ACPI_PHYTIUM_CREATOR_ID, + EFI_ACPI_PHYTIUM_CREATOR_REVISION + }, + 0x0000000000000000, //Reserved + }, + { + { + 0x40000000, //Base Address + 0, //Segment Group Num= ber + 0, //Start Bus Number + 0xff, //End Bus Number + 0x00000000, //Reserved + }, + } +}; + +VOID * CONST ReferenceAcpiTable =3D &Mcfg; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc b/Sil= icon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc new file mode 100644 index 0000000000..ae1a21df23 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc @@ -0,0 +1,219 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; +} PHYTIUM_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; + PHYTIUM_PPTT_CORE Cores[2]; +} PHYTIUM_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; + PHYTIUM_PPTT_CLUSTER Clusters[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_ID ID; +} PHYTIUM_PPTT_PACKAGE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + PHYTIUM_PPTT_PACKAGE Packages[1]; +} PHYTIUM_PPTT_TABLE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (PHYTIUM_PPTT_CORE, DCache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */= \ + }, = \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, = \ + Packages[pid].Clusters[cid]), /* Parent */ = \ + 8 * (pid) + 4 * (cid) + (id), /* AcpiProcessorId */ = \ + 2, /* NumberOfPrivateResource= s */\ + }, { = \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, = \ + Packages[pid].Clusters[cid].Cores[id].DCache), = \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, = \ + Packages[pid].Clusters[cid].Cores[id].ICache), = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_32KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 2, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 0, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_32KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 2, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType = */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + 0, /* WritePolicy */ = \ + }, = \ + 64 /* LineSize */ = \ + } = \ +} + +#define PPTT_CLUSTER(pid, cid) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (PHYTIUM_PPTT_CLUSTER, L2Cache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ = \ + }, = \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid]), /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 1, /* NumberOfPrivateResources = */ \ + }, { = \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache)= , \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_2MB, /* Size */ = \ + 2048, /* NumberOfSets */ = \ + 16, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + PPTT_CORE (pid, cid, 0), = \ + PPTT_CORE (pid, cid, 1), = \ + } = \ +} + +#define PPTT_PANEL(pid) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (PHYTIUM_PPTT_PACKAGE, L3Cache), = \ + {}, = \ + { = \ + 1, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid = */ \ + }, = \ + 0, /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 1, /* NumberOfPrivateResour= ces */ \ + }, { = \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].L3Cache), = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */= \ + 0, /* AllocationTypeValid *= / \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_4MB, /* Size */ = \ + 4096, /* NumberOfSets */ = \ + 16, /* Associativity */ = \ + { = \ + 0, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + PPTT_CLUSTER (pid, 0), = \ + PPTT_CLUSTER (pid, 1), = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_ID, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), = \ + {0}, = \ + 0x54594850, = \ + 0x3, = \ + 0x1, = \ + 0, = \ + 0, = \ + 0, = \ + } = \ +} + + +STATIC PHYTIUM_PPTT_TABLE mPhytiumPpttTable =3D { + { + PHYTIUM_ACPI_HEADER (EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_= STRUCTURE_SIGNATURE, + PHYTIUM_PPTT_TABLE, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISIO= N), + }, + { + PPTT_PANEL (0) + } +}; + +VOID * CONST ReferenceAcpiTable =3D &mPhytiumPpttTable; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc b/Sil= icon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc new file mode 100644 index 0000000000..00ffb7e7a9 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc @@ -0,0 +1,73 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +/// +/// SPCR Flow Control +/// +#define SPCR_FLOW_CONTROL_NONE 0 + + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { + PHYTIUM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_= SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISI= ON), + // UINT8 InterfaceType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_= UART, + // UINT8 Reserved1[3]; + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; + ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)), + // UINT8 InterruptType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + // UINT8 Irq; + 0, // Not used on ARM + // UINT32 GlobalSystemInterrupt; + FixedPcdGet32 (PL011UartInterrupt), + // UINT8 BaudRate; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, + // UINT8 Parity; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + // UINT8 StopBits; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + // UINT8 FlowControl; + SPCR_FLOW_CONTROL_NONE, + // UINT8 TerminalType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + // UINT8 Reserved2; + EFI_ACPI_RESERVED_BYTE, + // UINT16 PciDeviceId; + 0xFFFF, + // UINT16 PciVendorId; + 0xFFFF, + // UINT8 PciBusNumber; + 0x00, + // UINT8 PciDeviceNumber; + 0x00, + // UINT8 PciFunctionNumber; + 0x00, + // UINT32 PciFlags; + 0x00000000, + // UINT8 PciSegment; + 0x00, + // UINT32 Reserved3; + EFI_ACPI_RESERVED_DWORD +}; + +VOID * CONST ReferenceAcpiTable =3D &Spcr; --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72981): https://edk2.groups.io/g/devel/message/72981 Mute This Topic: https://groups.io/mt/81410913/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 10:07:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72982+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72982+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616006562; cv=none; d=zohomail.com; s=zohoarc; b=cGdFnvbdxLKQHN08KyiqxnCYwjYfcLuMPRmfEvgTgs+Rb2A2+o4SZsDQWtb8Oqwqyw27paU+r0B0Jtt/keIq26OUDopc5gZDnC71HVGCmZRuaZ/aKTWcIHDyCkVXvJcklAG4DwJeGkMKvwLSKGyJ2/5YqjL7xwLT51T4H/rStoA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616006562; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7kx5LWG9jlkatLGpp0j86ez2mSeceqbcMYAVf2YiTnU=; b=dwlEmm9iAXdWL8ZOv29ck/kUdTGeGNMGhESVDKe3l9FMGK/1JOMxbUgnGzrNzdVvK4iNfJi8C4571diOuDzOQmnbmejXua3uZIsEt3XkBtcbNLKxsy6T5XJc4KPkAMHJQVYam9zpqkdixFkq7+S89t+6GS7b33mtWZOzHxatv8c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72982+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616006562615611.2997263637362; Wed, 17 Mar 2021 11:42:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZUKaYY1788612xynQ87IYjfJ; Wed, 17 Mar 2021 11:42:42 -0700 X-Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by mx.groups.io with SMTP id smtpd.web08.3267.1615966021521492836 for ; Wed, 17 Mar 2021 00:27:03 -0700 X-Received: from localhost.localdomain (unknown [223.153.147.73]) by c1app7 (Coremail) with SMTP id BwINCgB3HOE4r1FgGIYZAA--.29335S5; Wed, 17 Mar 2021 15:26:58 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [edk2-devel] [PATCH v3 03/10] Silicon/Phytium: Added SMBIOS support to FT2000/4 Date: Wed, 17 Mar 2021 15:26:40 +0800 Message-Id: <20210317072647.77340-4-jialing@phytium.com.cn> In-Reply-To: <20210317072647.77340-1-jialing@phytium.com.cn> References: <20210317072647.77340-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BwINCgB3HOE4r1FgGIYZAA--.29335S5 X-Coremail-Antispam: 1UD129KBjvAXoWfAw13CF45ZrW8Cw1rCFykKrg_yoW5JrWkZo W7Wa1fJayFgrW8Zw47CrZ7Gr48ZF4I9w43tr9FyFyfZF4qv3y3KryUWa45ZrZIk3yjg398 C348J3s5JrW0vFW8n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYu7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r1rM28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK67AK6r4xMxAIw2 8IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4l x2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwIxGrw CI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI 42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z2 80aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjWE_tUUUUU== X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: 2AhBZmiRlsxBFq3vGhCrJnMax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616006562; bh=KQ8iRyA4ziLUP8KHxmYZLSO3fgjWhK19bPg5pa0E80M=; h=Cc:Date:From:Reply-To:Subject:To; b=l09R2rEuCXi0iLRZJO8nqcUM0ylvh3ErGUs0oTDZL/r3gxUelOuyUVR8IEr9m5l3gOW Vj6jk63oijw/joZeAPOQcg2PEsu9CmBjGhWZ0RuuLH02MIqIBPImJP9/mjZTBApSHBxKw /UULpOPjfEyK0jmU+tSmRFIJ2O6QdMJ6T4Y= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This driver installs SMBIOS information for FT2000/4. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Platform/Phytium/DurianPkg/DurianPkg.dsc = | 6 + Platform/Phytium/DurianPkg/DurianPkg.fdf = | 6 + Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.in= f | 47 + Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c = | 943 ++++++++++++++++++++ 4 files changed, 1002 insertions(+) diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index 6f38acb636..28e52e15e3 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -286,6 +286,12 @@ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe= .inf =20 + # + # SMBIOS + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.= inf + # # Bds # diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf index f435f7cb51..3106a43fb7 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -178,6 +178,12 @@ READ_LOCK_STATUS =3D TRUE # INF ShellPkg/Application/Shell/Shell.inf =20 + # + # SMBIOS + # + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatform= Dxe.inf + # # Bds # diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPl= atformDxe.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/Smbio= sPlatformDxe.inf new file mode 100644 index 0000000000..69a021e048 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformD= xe.inf @@ -0,0 +1,47 @@ +#/** @file +# This driver installs SMBIOS information for Phytium. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D SmbiosPlatformDxe + FILE_GUID =3D d64f09f8-40dc-11eb-9be6-f7a038f956ba + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmbiosTablePublishEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D AARCH64 +# +[Sources] + SmbiosPlatformDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + DebugLib + IoLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Guids] + gEfiGlobalVariableGuid + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Guids] + +[Depex] + gEfiSmbiosProtocolGuid diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPl= atformDxe.c b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosP= latformDxe.c new file mode 100644 index 0000000000..4a1f77dfb2 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformD= xe.c @@ -0,0 +1,943 @@ +/** @file + This driver installs SMBIOS information for Phytium Durian platforms. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include +#include +#include +#include +#include + +// SMBIOS tables often reference each other using +// fixed constants, define a list of these constants +// for our hardcoded tables + +#define TYPE0_STRINGS \ + "PHYTIUM LTD\0" /* Vendor */ \ + "V1.0\0" /* BiosVersion */ \ + __DATE__"\0" /* BiosReleaseDate */ + +#define TYPE1_STRINGS \ + "PHYTIUM LTD\0" /* Manufacturer */ \ + "Phytium Durian Development Platform\0" /* Product Name */ \ + "None\0" /* Version */ \ + "Not Set\0" /* SerialNumber */ \ + "Not set\0" /* SKUNumber */ \ + "FT-2000/4\0" /* Family */ \ + +#define TYPE2_STRINGS \ + "PHYTIUM LTD\0" /* Manufacturer */ \ + "Phytium Durian Development Platform\0" /* Product Name */ \ + "None\0" /* Version */ \ + "Not Set\0" /* Serial */ \ + "Not Set\0" /* BaseBoardAssetTag */ \ + "Not Set\0" /* BaseBoardChassisLocation */ + +#define TYPE3_STRINGS \ + "PHYTIUM LTD\0" /* Manufacturer */ \ + "None\0" /* Version */ \ + "Not Set\0" /* Serial */ \ + "Not Set\0" /* AssetTag */ + +#define TYPE4_STRINGS \ + "FT-2000/4\0" /* socket type */ \ + "PHYTIUM LTD\0" /* manufactuer */ \ + "FT-2000/4\0" /* processor version */ \ + "Not Set\0" /* SerialNumber */ \ + "Not Set\0" /* processor 2 description */ \ + "Not Set\0" /* AssetTag */ + + +#define TYPE7_STRINGS \ + "L1 Instruction\0" /* L1I */ \ + "L1 Data\0" /* L1D */ \ + "L2\0" /* L2 */ + +#define TYPE7_L1DATA_STRINGS \ + "L1 Data Cache\0" /* L1 data */ + + +#define TYPE7_L1INS_STRINGS \ + "L1 Instruction Cache\0" /* L1 ins */ + +#define TYPE7_L2_STRINGS \ + "L2 Cache\0" /* L2 */ + +#define TYPE7_L3_STRINGS \ + "L3 Cache\0" /* L3 */ + + +#define TYPE9_STRINGS \ + "PCIE_SLOT0\0" /* Slot0 */ \ + "PCIE_SLOT1\0" /* Slot1 */ \ + "PCIE_SLOT2\0" /* Slot2 */ \ + "PCIE_SLOT3\0" /* Slot3 */ + +#define TYPE9_STRINGS_PCIE0X16 \ + "PCIE0_X16\0" + +#define TYPE9_STRINGS_PCIE0X1 \ + "PCIE0_X1\0" + +#define TYPE9_STRINGS_PCIE1X16 \ + "PCIE1_X16\0" + +#define TYPE9_STRINGS_PCIE1X1 \ + "PCIE1_X1\0" + +#define TYPE13_STRINGS \ + "en|US|iso8859-1\0" \ + "zh|CN|unicode\0" + + +#define TYPE16_STRINGS \ + "\0" /* nothing */ + +#define TYPE17_STRINGS_CHANNEL0 \ + "SOCKET 0 CHANNEL 0 DIMM 0\0" /* location */ \ + "Bank0\0" /* bank description */ \ + "Not Set\0" \ + "Not Set\0" \ + "Not Set\0" \ + "Not Set\0" + +#define TYPE17_STRINGS_CHANNEL1 \ + "SOCKET 0 CHANNEL 1 DIMM 0\0" /* location */ \ + "Bank0\0" \ + "Not Set\0" \ + "Not Set\0" \ + "Not Set\0" \ + "Not Set\0" + + +#define TYPE19_STRINGS \ + "\0" /* nothing */ + +#define TYPE32_STRINGS \ + "\0" /* nothing */ + +#define TYPE39_STRINGS \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ + +#define TYPE38_STRINGS \ + "\0" + +// +// Type definition and contents of the default SMBIOS table. +// This table covers only the minimum structures required by +// the SMBIOS specification (section 6.2, version 3.0) +// +#pragma pack(1) +typedef struct { + SMBIOS_TABLE_TYPE0 Base; + INT8 Strings[sizeof (TYPE0_STRINGS)]; +} ARM_TYPE0; + +typedef struct { + SMBIOS_TABLE_TYPE1 Base; + UINT8 Strings[sizeof (TYPE1_STRINGS)]; +} ARM_TYPE1; + +typedef struct { + SMBIOS_TABLE_TYPE2 Base; + UINT8 Strings[sizeof (TYPE2_STRINGS)]; +} ARM_TYPE2; + +typedef struct { + SMBIOS_TABLE_TYPE3 Base; + UINT8 Strings[sizeof (TYPE3_STRINGS)]; +} ARM_TYPE3; + +typedef struct { + SMBIOS_TABLE_TYPE4 Base; + UINT8 Strings[sizeof (TYPE4_STRINGS)]; +} ARM_TYPE4; + +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[sizeof (TYPE7_L1DATA_STRINGS)]; +} ARM_TYPE7_L1DATA; + +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[sizeof (TYPE7_L1INS_STRINGS)]; +} ARM_TYPE7_L1INS; + +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[sizeof (TYPE7_L2_STRINGS)]; +} ARM_TYPE7_L2; + +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[sizeof (TYPE7_L3_STRINGS)]; +} ARM_TYPE7_L3; + + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof (TYPE9_STRINGS)]; +} ARM_TYPE9; + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE0X16)]; +} ARM_TYPE9_PCIE0X16; + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE0X1)]; +} ARM_TYPE9_PCIE0X1; + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE1X16)]; +} ARM_TYPE9_PCIE1X16; + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE1X1)]; +} ARM_TYPE9_PCIE1X1; + + +typedef struct { + SMBIOS_TABLE_TYPE13 Base; + UINT8 Strings[sizeof (TYPE13_STRINGS)]; +} ARM_TYPE13; + +typedef struct { + SMBIOS_TABLE_TYPE16 Base; + UINT8 Strings[sizeof (TYPE16_STRINGS)]; +} ARM_TYPE16; + +typedef struct { + SMBIOS_TABLE_TYPE17 Base; + UINT8 Strings[sizeof (TYPE17_STRINGS_CHANNEL0)]; +} ARM_TYPE17_CHANNEL0; + +typedef struct { + SMBIOS_TABLE_TYPE17 Base; + UINT8 Strings[sizeof (TYPE17_STRINGS_CHANNEL1)]; +} ARM_TYPE17_CHANNEL1; + +typedef struct { + SMBIOS_TABLE_TYPE19 Base; + UINT8 Strings[sizeof (TYPE19_STRINGS)]; +} ARM_TYPE19; + +typedef struct { + SMBIOS_TABLE_TYPE32 Base; + UINT8 Strings[sizeof (TYPE32_STRINGS)]; +} ARM_TYPE32; + +typedef struct { + SMBIOS_TABLE_TYPE38 Base; + UINT8 Strings[sizeof (TYPE38_STRINGS)]; +} ARM_TYPE38; + +typedef struct { + SMBIOS_TABLE_TYPE39 Base; + UINT8 Strings[sizeof (TYPE39_STRINGS)]; +} ARM_TYPE39; + +enum SMBIOS_REFRENCE_HANDLES { + SMBIOS_HANDLE_L1I =3D 0x1000, + SMBIOS_HANDLE_L1D, + SMBIOS_HANDLE_L2, + SMBIOS_HANDLE_L3, + SMBIOS_HANDLE_MOTHERBOARD, + SMBIOS_HANDLE_CHASSIS, + SMBIOS_HANDLE_CLUSTER, + SMBIOS_HANDLE_MEMORY, + SMBIOS_HANDLE_DIMM_0, + SMBIOS_HANDLE_DIMM_1 +}; + +#define SERIAL_LEN 10 //this must be less than the buffer len allocated i= n the type1 structure + +#pragma pack() + +//BIOS Information (Type 0) +ARM_TYPE0 BiosInfo_Type0 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 1, //Vendor + 2, //BiosVersion + 0x8800, //BiosSegment + 3, //BiosReleaseDate + 0xFF, //BiosSize + { //BiosCharacteristics + 0, // Reserved = :2 + 0, // Unknown = :1 + 0, // BiosCharacteristicsN= otSupported :1 + 0, // IsaIsSupported = :1 + 0, // McaIsSupported = :1 + 0, // EisaIsSupported = :1 + 1, // PciIsSupported = :1 + 0, // PcmciaIsSupported = :1 + 0, // PlugAndPlayIsSupport= ed :1 + 0, // ApmIsSupported = :1 + 1, // BiosIsUpgradable = :1 + 0, // BiosShadowingAllowed= :1 + 0, // VlVesaIsSupported = :1 + 0, // EscdSupportIsAvailab= le :1 + 1, // BootFromCdIsSupporte= d :1 + 1, // SelectableBootIsSupp= orted :1 + 0, // RomBiosIsSocketed = :1 + 0, // BootFromPcmciaIsSupp= orted :1 + 0, // EDDSpecificationIsSu= pported :1 + 0, // JapaneseNecFloppyIsS= upported :1 + 0, // JapaneseToshibaFlopp= yIsSupported :1 + 0, // Floppy525_360IsSuppo= rted :1 + 0, // Floppy525_12IsSuppor= ted :1 + 0, // Floppy35_720IsSuppor= ted :1 + 0, // Floppy35_288IsSuppor= ted :1 + 0, // PrintScreenIsSupport= ed :1 + 0, // Keyboard8042IsSuppor= ted :1 + 0, // SerialIsSupported = :1 + 0, // PrinterIsSupported = :1 + 0, // CgaMonoIsSupported = :1 + 0, // NecPc98 = :1 + 0 // ReservedForVendor = :3 + }, + { + 0x03, //BIOSCharacteristicsEx= tensionBytes[0] + 0x0D //BIOSCharacteristicsEx= tensionBytes[1] + }, + 0xFF, //SystemBiosMajorReleas= e; + 0xFF, //SystemBiosMinorReleas= e; + 0xFF, //EmbeddedControllerFir= mwareMajorRelease; + 0xFF, //EmbeddedControllerFir= mwareMinorRelease; + }, + TYPE0_STRINGS +}; + +//System Information (Type 1). +ARM_TYPE1 SystemInfo_Type1 =3D { + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type, + sizeof (SMBIOS_TABLE_TYPE1), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + 1, // Manufacturer + 2, // ProductName + 3, // Version + 4, // SerialNumber + { // Uuid + 0x12345678, 0x1234, 0x5678, {0x90, 0xab, 0xcd, 0xde, 0xef, 0xaa,= 0xbb, 0xcc} + }, + SystemWakeupTypePowerSwitch, // SystemWakeupType + 5, // SKUNumber, + 6 // Family + }, + TYPE1_STRINGS +}; + +//Base Board (or Module) Information (Type 2) +ARM_TYPE2 BaseboardInfo_Type2 =3D { + { + { // Hdr + EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type, + sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Len= gth + SMBIOS_HANDLE_MOTHERBOARD // Handle + }, + 1, // BaseBoard= Manufacturer + 2, // BaseBoard= ProductName + 3, // BaseBoard= Version + 4, // BaseBoard= SerialNumber + 5, // BaseBoard= AssetTag + { // FeatureFl= ag + 1, // Motherboa= rd :1 + 0, // RequiresD= aughterCard :1 + 0, // Removable= :1 + 1, // Replaceab= le :1 + 0, // HotSwappa= ble :1 + 0 // Reserved = :3 + }, + 6, // BaseBoard= ChassisLocation + 0, // ChassisHa= ndle; + BaseBoardTypeMotherBoard, // BoardType; + 0, // NumberOfC= ontainedObjectHandles; + { + 0 + } // Contained= ObjectHandles[1]; + }, + TYPE2_STRINGS +}; + +//System Enclosure or Chassis (Type 3) +ARM_TYPE3 SystemEnclosure_Type3 =3D { + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE , // Type, + sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Len= gth + SMBIOS_HANDLE_CHASSIS // Handle + }, + 1, // Manufactr= urer + MiscChassisTypeMainServerChassis, // Type + 2, // Version + 3, // SerialNum= ber + 4, // AssetTag + ChassisStateSafe, // BootupSta= te + ChassisStateSafe, // PowerSupp= lyState + ChassisStateSafe, // ThermalSt= ate + ChassisSecurityStatusNone, // SecurityS= tate + { + 0, // OemDefine= d[0] + 0, // OemDefine= d[1] + 0, // OemDefine= d[2] + 0 // OemDefine= d[3] + }, + 2, // Height + 1, // NumberofP= owerCords + 0, // Contained= ElementCount + 0, // Contained= ElementRecordLength + { // Contained= Elements[0] + { + 0, // Contained= ElementType + 0, // Contained= ElementMinimum + 0 // Contained= ElementMaximum + } + } + }, + TYPE3_STRINGS +}; + +//Processor Infomation (Type 4) +ARM_TYPE4 ProcessorInfo_Type4 =3D { + { + { //Header + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, //Type + sizeof (SMBIOS_TABLE_TYPE4), //Length + SMBIOS_HANDLE_CLUSTER //Handle + }, + 1, //Socket + CentralProcessor, //ProcessorType + ProcessorFamilyIndicatorFamily2, //ProcessorFamily + 2, //ProcessorManufacture + { //ProcessorId + { //Signature + 0 + }, + { //FeatureFlags + 0 + } + }, + 3, //ProcessorVersion + { //Voltage + 0, 0, 0, 1, 0, 1 + }, + 1, //ExternalClock + 1, //MaxSpeed + 0, //CurrentSpeed + 0x41, //Status + ProcessorUpgradeUnknown, //ProcessorUpgrade + SMBIOS_HANDLE_L1D, //L1Ins + SMBIOS_HANDLE_L2, //L1Data + SMBIOS_HANDLE_L3, //L2 + 4, //SerialNumber + 5, //AssetTag + 6, //PartNumber + + 4, //CoreCount + 0, //EnabledCoreCount + 0, //ThreadCount + 0x00EC, //ProcessorCharacteristics + + ProcessorFamilyARMv8, //ProcessorFamily2 + + 0, //CoreCount2 + 0, //EnabledCoreCount2 + 0 //ThreadCount2 + }, + TYPE4_STRINGS +}; + +//Cache Information (Type7) L1 DATA +ARM_TYPE7_L1DATA L1Data_Type7 =3D { + { + { //Header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type + sizeof (SMBIOS_TABLE_TYPE7), //Length + SMBIOS_HANDLE_L1D //Handle + }, + 1, //SocketDesignation + 0x0180, //CacheConfiguration + 0, //MaximumCacheSize + 0, //InstalledSize + { //SupportedSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + { //CurrentSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + 0, //CacheSpeed + CacheErrorSingleBit, //ErrorCorrectionType + CacheTypeData, //SystemCacheType + CacheAssociativity8Way, //Associativity + 128, + 128 + }, + TYPE7_L1DATA_STRINGS +}; + +//Cache Information (Type7) L1 INS +ARM_TYPE7_L1INS L1Ins_Type7 =3D { + { + { //Header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type + sizeof (SMBIOS_TABLE_TYPE7), //Length + SMBIOS_HANDLE_L1I //Handle + }, + 1, //SocketDesignation + 0x0180, //CacheConfiguration + 0, //MaximumCacheSize + 0, //InstalledSize + { //SupportedSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + { //CurrentSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + 0, //CacheSpeed + CacheErrorParity, //ErrorCorrectionType + CacheTypeInstruction, //SystemCacheType + CacheAssociativity8Way, //Associativity + 128, + 128 + }, + TYPE7_L1INS_STRINGS +}; + +//Cache Information (Type7) L2 +ARM_TYPE7_L2 L2_Type7 =3D { + { + { //Header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type + sizeof (SMBIOS_TABLE_TYPE7), //Length + SMBIOS_HANDLE_L2 //Handle + }, + 1, //SocketDesignation + 0x0281, //CacheConfiguration + 0, //MaximumCacheSize + 0, //InstalledSize + { //SupportedSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + { //CurrentSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + 0, //CacheSpeed + CacheErrorSingleBit, //ErrorCorrectionType + CacheTypeUnified, //SystemCacheType + CacheAssociativity8Way, //Associativity + 4096, + 4096 + }, + TYPE7_L2_STRINGS +}; + +//Cache Information (Type7) L3 +ARM_TYPE7_L3 L3_Type7 =3D { + { + { //Header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type + sizeof (SMBIOS_TABLE_TYPE7), //Length + SMBIOS_HANDLE_L3 //Handle + }, + 1, //SocketDesignation + 0x0281, //CacheConfiguration + 0, //MaximumCacheSize + 0, //InstalledSize + { //SupportedSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + { //CurrentSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + 0, //CacheSpeed + CacheErrorSingleBit, //ErrorCorrectionType + CacheTypeUnified, //SystemCacheType + CacheAssociativity8Way, //Associativity + 4096, + 4096 + }, + TYPE7_L3_STRINGS +}; + +//PCIE0_X16 (Type 9) +ARM_TYPE9_PCIE0X16 Pcie0X16_Type9 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 1, + SlotTypePciX, + SlotDataBusWidth16X, + SlotUsageInUse, + SlotLengthLong, + 0, + {0, 0, 1, 1, 0, 0, 0, 0}, //unknown + {1, 0, 0, 0, 0}, //PME and SMBUS + 0, + 0, + 0, + }, + TYPE9_STRINGS_PCIE0X16 +}; + +//PCIE0_X1 (Type 9) +ARM_TYPE9_PCIE0X1 Pcie0X1_Type9 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 1, + SlotTypePciX, + SlotDataBusWidth1X, + SlotUsageAvailable, + SlotLengthShort, + 1, + {0, 0, 1, 1, 0, 0, 0, 0}, //unknown + {1, 0, 0, 0, 0}, //PME and SMBUS + 0xFF, + 0xFF, + 0xFF, + }, + TYPE9_STRINGS_PCIE0X1 +}; + +//PCIE1_X16 (Type 9) +ARM_TYPE9_PCIE1X16 Pcie1X16_Type9 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 1, + SlotTypePciX, + SlotDataBusWidth16X, + SlotUsageAvailable, + SlotLengthLong, + 2, + {0, 0, 1, 1, 0, 0, 0, 0}, //unknown + {1, 0, 0, 0, 0}, //PME and SMBUS + 0xFF, + 0xFF, + 0xFF, + }, + TYPE9_STRINGS_PCIE1X16 +}; + +//PCIE1_X1 (Type 9) +ARM_TYPE9_PCIE1X1 Pcie1X1_Type9 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 1, + SlotTypePciX, + SlotDataBusWidth1X, + SlotUsageAvailable, + SlotLengthShort, + 3, + {0, 0, 1, 1, 0, 0, 0, 0}, //unknown + {1, 0, 0, 0, 0}, //PME and SMBUS + 0xFF, + 0xFF, + 0xFF, + }, + TYPE9_STRINGS_PCIE1X1 +}; + +//Bios Language Information (Type13) +ARM_TYPE13 BiosLangInfo_Type13 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE13), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 2, + 0, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 2 + }, + TYPE13_STRINGS +}; + +//Physical Memory Array (Type 16) +ARM_TYPE16 MemArray_Type16 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length + SMBIOS_HANDLE_MEMORY + }, + MemoryArrayLocationSystemBoard, + MemoryArrayUseSystemMemory, + MemoryErrorCorrectionNone, + 0x1000000, //16G + 0xFFFE, + 2 + }, + TYPE16_STRINGS +}; + +//Memory Device (Type17) +ARM_TYPE17_CHANNEL0 MemDev_Type17_0 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length + SMBIOS_HANDLE_DIMM_0 + }, + SMBIOS_HANDLE_MEMORY, //array to which this module belongs + 0xFFFE, //no errors + 64, //single DIMM, no ECC is 64bits (for ecc this wo= uld be 72) + 64, //data width of this device (64-bits) + 0x4000, //16GB + 0x09, //FormFactor + 0, //not part of a set + 1, //right side of board + 2, //bank 0 + MemoryTypeDdr4, //LP DDR4 + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, //unbuffered + 2400, //2400Mhz DDR + 3, //Manufacturer + 4, //serial + 5, //asset tag + 6, //part number + 0, //attrbute + 0x2000, // 8G + 2400, //2400MHz + 1500, //Max V + 1500, //Max V + 1500, //Configure V + }, + TYPE17_STRINGS_CHANNEL0 +}; + +//Memory Device (Type17) +ARM_TYPE17_CHANNEL1 MemDev_Type17_1 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length + SMBIOS_HANDLE_DIMM_1 + }, + SMBIOS_HANDLE_MEMORY, //array to which this module belongs + 0xFFFE, //no errors + 64, //single DIMM, no ECC is 64bits (for ecc this wo= uld be 72) + 64, //data width of this device (64-bits) + 0x2000, //8GB + 0x09, //FormFactor + 0, //not part of a set + 1, //right side of board + 2, //bank 0 + MemoryTypeDdr4, //LP DDR4 + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, //unbuffered + 2400, //2400Mhz DDR + 3, //varies between diffrent production runs + 4, //serial + 5, //asset tag + 6, //part number + 0, //attrbute + 0x4000, // 16G + 2400, //2400MHz + 1500, //Max V + 1500, //Max V + 1500, //Configure V + }, + TYPE17_STRINGS_CHANNEL1 +}; + +//Memory Array Mapped Address (Type 19) +ARM_TYPE19 MemArrayMapAddr_Type19 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 0, + 0x1000000, //16G + SMBIOS_HANDLE_MEMORY, //handle + 2, + 0, //starting addr of first 2GB + 0, //ending addr of first 2GB + }, + TYPE19_STRINGS +}; + +//System Boot Information (Type 32) +ARM_TYPE32 SystemBoot_Type32 =3D { + { + { + EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type, + sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + { // Reserved[6] + 0, + 0, + 0, + 0, + 0, + 0 + }, + BootInformationStatusNoError // BootInformationSta= tus + }, + TYPE32_STRINGS +}; + +VOID *DefaultCommonTables[]=3D +{ + &BiosInfo_Type0, + &SystemInfo_Type1, + &BaseboardInfo_Type2, + &SystemEnclosure_Type3, + &ProcessorInfo_Type4, + &L1Data_Type7, + &L1Ins_Type7, + &L2_Type7, + &L3_Type7, + &Pcie0X16_Type9, + &Pcie0X1_Type9, + &Pcie1X16_Type9, + &Pcie1X1_Type9, + &MemArray_Type16, + &MemDev_Type17_0, + &MemDev_Type17_1, + &MemArrayMapAddr_Type19, + &BiosLangInfo_Type13, + &SystemBoot_Type32, + NULL +}; + + +/** + Installed a whole table worth of structructures. + + @param[in] Smbios The Pointer of Smbios Protocol. + + @retval EFI_SUCCESS Table data successfully installed. + @retval Other Table data was not installed. + +**/ +EFI_STATUS +InstallStructures ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN VOID *DefaultTables[] + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + UINT32 TableEntry; + + Status =3D EFI_SUCCESS; + + for ( TableEntry =3D0; DefaultTables[TableEntry] !=3D NULL; TableEntry++) + { + SmbiosHandle =3D ((EFI_SMBIOS_TABLE_HEADER *)DefaultTables[TableEntry]= )->Handle; + Status =3D Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) DefaultTables[TableEntry] + ); + if (EFI_ERROR (Status)) + break; + } + + return Status; +} + + +/** + Installed All SMBIOS information. + + @param[in] Smbios The Pointer of Smbios Protocol. + + @retval EFI_SUCCESS SMBIOS information successfully installed. + @retval Other SMBIOS information was not installed. + +**/ +STATIC +EFI_STATUS +InstallAllStructures ( + IN EFI_SMBIOS_PROTOCOL *Smbios + ) +{ + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + Status =3D InstallStructures (Smbios, DefaultCommonTables); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + +/** + Find the smbios protocol and installed SMBIOS information + for ARM platforms. + + @param[in] ImageHandle Module's image handle. + @param[in] SystemTable Pointer of EFI_SYSTEM_TABLE. + + @retval EFI_SUCCESS Smbios data successfully installed. + @retval Other Smbios data was not installed. + +**/ +EFI_STATUS +EFIAPI +SmbiosTablePublishEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_PROTOCOL *Smbios; + + // + // Find the SMBIOS protocol + // + Status =3D gBS->LocateProtocol ( + &gEfiSmbiosProtocolGuid, + NULL, + (VOID **)&Smbios + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D InstallAllStructures (Smbios); + + return Status; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72982): https://edk2.groups.io/g/devel/message/72982 Mute This Topic: https://groups.io/mt/81410914/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 10:07:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72983+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72983+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616006564; cv=none; d=zohomail.com; s=zohoarc; b=QxTSei8f/5SdcNOA6dA0eXLeBpEFJ8WzV1XpNAa3QD9SvBb4ALYXGg3RMIx4v+WlLQHLGvTVoSIBUVZKTjhrB6rLUuK6JfFxuBPDUrlk5MwRQBPADQbMJaY4bzVhE/kHgIKqmmU21j/s+uqrfhbCPXBfd4aWumT1YYPBTj/VBlo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616006564; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=SamdGv6/rdqIhm+7hzfzZKBtb7Z5S1XmOE5KVUDV/9M=; b=cROqc1n53Dy5fvdfFS752K12GW/td8KJYmJljqRktKdAHdYGfwkfVoNONh/2nazoIdOx+z7EPN1LAZRsQdmbsZQzPSXFqM4Gz1C4+lXdtIKYwV0qe1RGlNbjotXSvAtZmO+GjnDAAbI+0VCJExvzkxHdHCUuvz0ViKWYW5tOT48= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72983+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161600656438830.33894561654779; Wed, 17 Mar 2021 11:42:44 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id rZ1MYY1788612xFYbX1MSlEU; Wed, 17 Mar 2021 11:42:44 -0700 X-Received: from zg8tmty1ljiyny4xntqumjca.icoremail.net (zg8tmty1ljiyny4xntqumjca.icoremail.net [165.227.154.27]) by mx.groups.io with SMTP id smtpd.web10.3305.1615966021576919457 for ; Wed, 17 Mar 2021 00:27:03 -0700 X-Received: from localhost.localdomain (unknown [223.153.147.73]) by c1app7 (Coremail) with SMTP id BwINCgB3HOE4r1FgGIYZAA--.29335S6; Wed, 17 Mar 2021 15:26:58 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [edk2-devel] [PATCH v3 04/10] Silicon/Phytium: Added PciSegmentLib to FT2000/4 Date: Wed, 17 Mar 2021 15:26:41 +0800 Message-Id: <20210317072647.77340-5-jialing@phytium.com.cn> In-Reply-To: <20210317072647.77340-1-jialing@phytium.com.cn> References: <20210317072647.77340-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BwINCgB3HOE4r1FgGIYZAA--.29335S6 X-Coremail-Antispam: 1UD129KBjvAXoWDJF1UXF17uF1Dtr1kZFy3CFg_yoW7Jr1DAo ZYvFy8Xr1vqw1xKF1xt3sxXw4fWFZ2kr1xArWFqrW5X3WvqFsa9a4Iqa1DJr97G3W7Kryk Xr95Za97JFWrt3Wrn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYN7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW8JVW5JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F 4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK67AK6r4xMx AIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_ Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwI xGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWx JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUUL0ePUUUUU== X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: HTNwENtGccRSyLR0VyOB6mvrx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616006564; bh=OCOD1c75jbVNtwXA+jjRs9K/6+hNHAUeZDV9Dwe1KUY=; h=Cc:Date:From:Reply-To:Subject:To; b=aYnWO5cz1gNfKC46lNEgVELqB3l4IiBqak6jy0sztCxhqqj8xnQtSagNRrtqswBfVhM GARPYn11oLeOzauN5OOlewrA2kSnhPwUuULl4FiWueOJ3WGLZqXkOs3qN0bJ3JafvTuJO 3qxP9/8F0F644lmgeX5jfcn3Ed3T3iuwusw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The PCI Segment Library for Phytium platform. with multiple RCs. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Platform/Phytium/DurianPkg/DurianPkg.dsc | 9= +- Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf | 28= + Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c | 1434= ++++++++++++++++++++ 3 files changed, 1464 insertions(+), 7 deletions(-) diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index 28e52e15e3..093b2cd9db 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -35,7 +35,8 @@ PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf =20 [LibraryClasses.common.DXE_DRIVER] - + # Pci dependencies + PciSegmentLib|Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegme= ntLib.inf =20 ##########################################################################= ###### # @@ -262,12 +263,6 @@ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf =20 - # - # PCI Support - # - ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf - MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic= eDxe.inf - # # The following 2 module perform the same work except one operate variab= le. # Only one of both should be put into fdf. diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLi= b.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf new file mode 100644 index 0000000000..67360016ef --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf @@ -0,0 +1,28 @@ +#/** @file +# PCI Segment Library for Phytium platform with multiple RCs. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D PciSegmentLib + FILE_GUID =3D fa5173d2-40fe-11eb-9b2f-cb20dc669fd3 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciSegmentLib + +[Sources] + PciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLi= b.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c new file mode 100644 index 0000000000..c10b152e0d --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c @@ -0,0 +1,1434 @@ +/** @file + PCI Segment Library for SoC with multiple RCs. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#define PCI_SEG_CONFIG_BASE 0x40000000 +#define PCIE_BIF_MODE 0x29100800 + +typedef enum { + PciCfgWidthUint8 =3D 0, + PciCfgWidthUint16, + PciCfgWidthUint32, + PciCfgWidthMax +} PCI_CFG_WIDTH; + +/** + Assert the validity of a PCI Segment address. + A valid PCI Segment address should not contain 1's in bits 28..31 and 48= ..63 + + @param[in] A The address to validate. + @param[in] M Additional bits to assert to be zero. + +**/ +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \ +ASSERT (((A) & (0xffff0000f0000000ULL | (M))) =3D=3D 0) + + +#define EXTRACT_PCIE_ADDRESS(Address, Bus, Device, Function) \ +{ \ + (Bus) =3D (((Address) >> 20) & 0xff); \ + (Device) =3D (((Address) >> 15) & 0x1f); \ + (Function) =3D (((Address) >> 12) & 0x07); \ +} + + +/** + This function geted the config base of PCI device. + @param[in] Address The address that encodes the PCI Bus, Device, Funct= ion and + Register. + + @return The value of the config base of PCI device. + +**/ +STATIC +UINT64 +PciSegmentLibGetConfigBase ( + IN UINT64 Address + ) +{ + UINT8 Bus; + UINT8 Device; + UINT8 Function; + UINT8 RootPortCount; + UINT8 Peu0RootPortCount; + UINT8 Peu1RootPortCount; + UINT32 BifMode; + UINT32 Peu0BifMode; + UINT32 Peu1BifMode; + + EXTRACT_PCIE_ADDRESS (Address, Bus, Device, Function); + BifMode =3D MmioRead32 (PCIE_BIF_MODE); + Peu0BifMode =3D BifMode & 0x3; + Peu1BifMode =3D (BifMode >> 2) & 0x3; + + if ((Peu0BifMode =3D=3D 1)) { + Peu0RootPortCount =3D 3; + } else { + Peu0RootPortCount =3D 2; + } + + if ((Peu1BifMode =3D=3D 1)) { + Peu1RootPortCount =3D 3; + } else { + Peu1RootPortCount =3D 2; + } + RootPortCount =3D Peu0RootPortCount + Peu1RootPortCount; + //ignore device > 0 or function > 0 on root port + if (RootPortCount =3D=3D 4) { + if ((Bus =3D=3D 1) || (Bus =3D=3D 2) || (Bus =3D=3D 3) || (Bus =3D=3D = 4)) { + if (Device !=3D 0 || Function !=3D 0) { + return 0xFFFFFFFF; + } + return PCI_SEG_CONFIG_BASE; + } + } else if (RootPortCount =3D=3D 5) { + if ((Bus =3D=3D 1) || (Bus =3D=3D 2) || (Bus =3D=3D 3) || (Bus =3D=3D = 4) || (Bus =3D=3D 5)) { + if (Device !=3D 0 || Function !=3D 0) { + return 0xFFFFFFFF; + } + return PCI_SEG_CONFIG_BASE; + } + } else if (RootPortCount =3D=3D 6) { + if ((Bus =3D=3D 1) || (Bus =3D=3D 2) || (Bus =3D=3D 3) || (Bus =3D=3D = 4) || (Bus =3D=3D 5) || (Bus =3D=3D 6)) { + if (Device !=3D 0 || Function !=3D 0) { + return 0xFFFFFFFF; + } + return PCI_SEG_CONFIG_BASE; + } + } + + return PCI_SEG_CONFIG_BASE; +} + +/** + Internal worker function to read a PCI configuration register. + + @param[in] Address The address that encodes the PCI Bus, Device, Functi= on and + Register. + @param[in] Width The width of data to read + + @return The value read from the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibReadWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width + ) +{ + UINT64 Base; + + Base =3D PciSegmentLibGetConfigBase (Address); + if (Base =3D=3D 0xFFFFFFFF) { + return 0xFFFFFFFF; + } + + switch (Width) { + case PciCfgWidthUint8: + return MmioRead8 (Base + (UINT32)Address); + case PciCfgWidthUint16: + return MmioRead16 (Base + (UINT32)Address); + case PciCfgWidthUint32: + return MmioRead32 (Base + (UINT32)Address); + default: + ASSERT (FALSE); + } + + return 0; +} + + +/** + Internal worker function to writes a PCI configuration register. + + @param[in] Address The address that encodes the PCI Bus, Device, Functi= on and + Register. + @param[in] Width The width of data to write + @param[in] Data The value to write. + + @return The value written to the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibWriteWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width, + IN UINT32 Data + ) +{ + UINT64 Base; + + Base =3D PciSegmentLibGetConfigBase (Address); + if (Base =3D=3D 0xFFFFFFFF) { + return 0xFFFFFFFF; + } + + switch (Width) { + case PciCfgWidthUint8: + MmioWrite8 (Base + (UINT32)Address, Data); + break; + case PciCfgWidthUint16: + MmioWrite16 (Base + (UINT32)Address, Data); + break; + case PciCfgWidthUint32: + MmioWrite32 (Base + (UINT32)Address, Data); + break; + default: + ASSERT (FALSE); + } + + return Data; +} + +/** + Register a PCI device so PCI configuration registers may be accessed aft= er + SetVirtualAddressMap(). + + If any reserved bits in Address are set, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, D= evice, Function and + Register. + + @retval RETURN_SUCCESS The PCI device was registered for runti= me access. + @retval RETURN_UNSUPPORTED An attempt was made to call this functi= on + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PC= I device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl= e to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciSegmentRegisterForRuntimeAccess ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return RETURN_UNSUPPORTED; +} + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Addr= ess. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, + and Register. + + @return The 8-bit PCI configuration register specified by Address. + +**/ +UINT8 +EFIAPI +PciSegmentRead8 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8); +} + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with th= e value specified by Value. + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, D= evice, Function, and Register. + @param[in] Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentWrite8 ( + IN UINT64 Address, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Valu= e); +} + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-b= it value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by= OrData, + and writes the result to the 8-bit PCI configuration register specified = by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, and Register. + @param[in] OrData The value to OR with the PCI configuration registe= r. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentOr8 ( + IN UINT64 Address, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | O= rData)); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + and writes the result to the 8-bit PCI configuration register specified = by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + If any reserved bits in Address are set, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, and Register. + @param[in] AndData The value to AND with the PCI configuration regist= er. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAnd8 ( + IN UINT64 Address, + IN UINT8 AndData + ) +{ + return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & A= ndData)); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit value, + followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + performs a bitwise OR between the result of the AND operation and the va= lue specified by OrData, + and writes the result to the 8-bit PCI configuration register specified = by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, and Register. + @param[in] AndData The value to AND with the PCI configuration regis= ter. + @param[in] OrData The value to OR with the PCI configuration registe= r. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAndThenOr8 ( + IN UINT64 Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & = AndData) | OrData)); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address The PCI configuration register to read. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..7. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldRead8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 8-bit register is returned. + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..7. + @param[in] Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldWrite8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Va= lue) + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..7. + @param[in] OrData The value to OR with the PCI configuration registe= r. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrDat= a) + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..7. + @param[in] AndData The value to AND with the PCI configuration regist= er. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAnd8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndD= ata) + ); +} + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..7. + @param[in] AndData The value to AND with the PCI configuration regist= er. + @param[in] OrData The value to OR with the result of the AND operati= on. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAndThenOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit= , AndData, OrData) + ); +} + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, and Register. + + @return The 16-bit PCI configuration register specified by Address. + +**/ +UINT16 +EFIAPI +PciSegmentRead16 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16); +} + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with t= he value specified by Value. + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, D= evice, Function, and Register. + @param[in] Value The value to write. + + @return The parameter of Value. + +**/ +UINT16 +EFIAPI +PciSegmentWrite16 ( + IN UINT64 Address, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Va= lue); +} + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Devic= e, Function and + Register. + @param[in] OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentOr16 ( + IN UINT64 Address, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) = | OrData)); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + and writes the result to the 16-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, and Register. + @param[in] AndData The value to AND with the PCI configuration regist= er. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAnd16 ( + IN UINT64 Address, + IN UINT16 AndData + ) +{ + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) = & AndData)); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit value, + followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + performs a bitwise OR between the result of the AND operation and the va= lue specified by OrData, + and writes the result to the 16-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, and Register. + @param[in] AndData The value to AND with the PCI configuration regist= er. + @param[in] OrData The value to OR with the PCI configuration registe= r. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAndThenOr16 ( + IN UINT64 Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address)= & AndData) | OrData)); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address The PCI configuration register to read. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..15. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldRead16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 16-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..15. + @param[in] Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldWrite16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, = Value) + ); +} + +/** + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by= OrData, + and writes the result to the 16-bit PCI configuration register specified= by Address. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..15. + @param[in] OrData The value to OR with the PCI configuration registe= r. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrD= ata) + ); +} + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, + and writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by= OrData, + and writes the result to the 16-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, and Register. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + The ordinal of the least significant bit in a byte is = bit 0. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + The ordinal of the most significant bit in a byte is b= it 7. + @param[in] AndData The value to AND with the read value from the PCI = configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAnd16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, An= dData) + ); +} + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..15. + @param[in] AndData The value to AND with the PCI configuration regist= er. + @param[in] OrData The value to OR with the result of the AND operati= on. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAndThenOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndB= it, AndData, OrData) + ); +} + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, + and Register. + + @return The 32-bit PCI configuration register specified by Address. + +**/ +UINT32 +EFIAPI +PciSegmentRead32 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); +} + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with t= he value specified by Value. + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, D= evice, + Function, and Register. + @param[in] Value The value to write. + + @return The parameter of Value. + +**/ +UINT32 +EFIAPI +PciSegmentWrite32 ( + IN UINT64 Address, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value); +} + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-b= it value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by= OrData, + and writes the result to the 32-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, and Register. + @param[in] OrData The value to OR with the PCI configuration registe= r. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentOr32 ( + IN UINT64 Address, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + and writes the result to the 32-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, + and Register. + @param[in] AndData The value to AND with the PCI configuration regist= er. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAnd32 ( + IN UINT64 Address, + IN UINT32 AndData + ) +{ + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit value, + followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + performs a bitwise OR between the result of the AND operation and the va= lue specified by OrData, + and writes the result to the 32-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Segment, Bus, Dev= ice, Function, + and Register. + @param[in] AndData The value to AND with the PCI configuration regist= er. + @param[in] OrData The value to OR with the PCI configuration registe= r. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAndThenOr32 ( + IN UINT64 Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData= ) | OrData); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is = returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address The PCI configuration register to read. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..31. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldRead32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 32-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..31. + @param[in] Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldWrite32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, = Value) + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..31. + @param[in] OrData The value to OR with the PCI configuration registe= r. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrD= ata) + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 32-bit register. + + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a bitwise + AND between the read result and the value specified by AndData, and writ= es the result + to the 32-bit PCI configuration register specified by Address. The value= written to + the PCI configuration register is returned. This function must guarante= e that all PCI + read and write operations are serialized. Extra left bits in AndData ar= e stripped. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..31. + @param[in] AndData The value to AND with the PCI configuration regist= er. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAnd32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, An= dData) + ); +} + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bi= t field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit= field. + Range 0..31. + @param[in] AndData The value to AND with the PCI configuration regist= er. + @param[in] OrData The value to OR with the result of the AND operati= on. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAndThenOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndB= it, AndData, OrData) + ); +} + +/** + Reads a range of PCI configuration registers into a caller supplied buff= er. + + Reads the range of PCI configuration registers specified by StartAddress= and + Size into the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to= read + from StartAdress to StartAddress + Size. Due to alignment restrictions, = 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning an= d the + end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param[in] StartAddress The starting address that encodes the PCI Segm= ent, Bus, + Device, Function and Register. + @param[in] Size The size in bytes of the transfer. + @param[in] Buffer The pointer to a buffer receiving the data rea= d. + + @return Size + +**/ +UINTN +EFIAPI +PciSegmentReadBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return Size; + } + + ASSERT (Buffer !=3D NULL); + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // + // Read a byte if StartAddress is byte aligned, + // Volatile ensure that the latest values are read every time. + // + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8 *)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) { + // + // Read a word if StartAddress is word aligned + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16 *)Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Read as many double words as possible + // + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32 *)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Read the last remaining word if exist + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16 *)Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Read the last remaining byte if exist + // + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); + } + + return ReturnValue; +} + + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddres= s and + Size from the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrict= ions, + 8-bit and 16-bit PCI configuration write cycles may be used at the begin= ning + and the end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param[in] StartAddress The starting address that encodes the PCI Segm= ent, Bus, + Device, Function and Register. + @param[in] Size The size in bytes of the transfer. + @param[in] Buffer The pointer to a buffer containing the data to= write. + + @return The parameter of Size. + +**/ +UINTN +EFIAPI +PciSegmentWriteBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return 0; + } + + ASSERT (Buffer !=3D NULL); + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // + // Write a byte if StartAddress is byte aligned + // + PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8 *)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) { + // + // Write a word if StartAddress is word aligned + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16 *)Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Write as many double words as possible + // + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32 *)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Write the last remaining word if exist + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16 *)Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Write the last remaining byte if exist + // + PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer); + } + + return ReturnValue; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72983): https://edk2.groups.io/g/devel/message/72983 Mute This Topic: https://groups.io/mt/81410915/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 10:07:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72985+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72985+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616006560; cv=none; d=zohomail.com; s=zohoarc; b=fPxMU9qOr9cU0bsC3v2YPKlme9RrgOjQoSqyb2VzO/R3A5xas/d0kX4lKg9w2nq4M0S9wKxITigZ2G1PDp1+DhnLm09QhcrgWWbXBewqtr2gHntn2Z9uOZtdjW99kDpMjvUDNg+goj6uH2R9iS7ebLG1DOdiD7iJTowY5oD53dM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616006560; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rDqAJb2RHm72a34tZ0pAgyTz/J7McCNmvmUD3jSnM9Y=; b=P9tXsv+tDDV1qfbf/Wl/+88wjm8vEz13/xs63KOQlH2qy5xdIYKDcD5Sa9kbpv+gtfxgbTEaskJ8x8rTXuT7JeecC8aI7mQ02xoL0eFjxJk+jAZ8r3DEEI/7QZ2xwBFD1j6z8lZKZR03sYfy+KklJaPIMB+rWMw3jmR9rcY2Na8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72985+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616006560797427.9988904073182; Wed, 17 Mar 2021 11:42:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id JjcxYY1788612xZeBGtcSkbn; Wed, 17 Mar 2021 11:42:40 -0700 X-Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by mx.groups.io with SMTP id smtpd.web09.3183.1615966022066663294 for ; Wed, 17 Mar 2021 00:27:03 -0700 X-Received: from localhost.localdomain (unknown [223.153.147.73]) by c1app7 (Coremail) with SMTP id BwINCgB3HOE4r1FgGIYZAA--.29335S7; Wed, 17 Mar 2021 15:26:59 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [edk2-devel] [PATCH v3 05/10] Silicon/Phytium: Added PciHostBridgeLib to FT2000/4 Date: Wed, 17 Mar 2021 15:26:42 +0800 Message-Id: <20210317072647.77340-6-jialing@phytium.com.cn> In-Reply-To: <20210317072647.77340-1-jialing@phytium.com.cn> References: <20210317072647.77340-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BwINCgB3HOE4r1FgGIYZAA--.29335S7 X-Coremail-Antispam: 1UD129KBjvJXoWxtw1rWFWxWr1rGF4UGryUKFg_yoWfCw4xpw 4Utan8X345X3Wjvr48A3s2gF43Aa9Fkw45Jr43Xw17ZFyfXF4kJrsFka45Wa4jq3WDXw4x WF1YqFyfu3ZYgaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr 1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_GF4l42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1Y6r17MIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU1zuWDUUUU X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: mydsUOoE6MEIXrfoIXsFzFQPx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616006560; bh=OSIt+FpFQn7u213zr6PSoBZ6e4chXjGjhN/mtwrI73M=; h=Cc:Date:From:Reply-To:Subject:To; b=U2MeuBrNBGMMGtCusFCFEzJQe+h5pIttRQWLjQ95P5LX2BRBU/+jDn44XLUrsyBOin2 xXYSgBL9rVyqaW2JzWbW1LI2fczEPpLAjLfV1ndGAKJz99ZzoC1Wozc+UIrHvWl+DOa0p 0kK03+DGqIGADNGF2MwfNwSktek4burzuUg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The Pci host bridge library is mainly to get Pci bridge information. v3: Optimize the codes of PciHostBridgeLib.c to conform to specifications. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Platform/Phytium/DurianPkg/DurianPkg.dsc = | 9 + Platform/Phytium/DurianPkg/DurianPkg.fdf = | 6 + Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf = | 47 +++++ Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c = | 181 ++++++++++++++++++++ 4 files changed, 243 insertions(+) diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index 093b2cd9db..3a9bc2289c 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -37,6 +37,7 @@ [LibraryClasses.common.DXE_DRIVER] # Pci dependencies PciSegmentLib|Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegme= ntLib.inf + PciHostBridgeLib|Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/Pc= iHostBridgeLib.inf =20 ##########################################################################= ###### # @@ -263,6 +264,14 @@ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf =20 + # + # PCI Support + # + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic= eDxe.inf + # # The following 2 module perform the same work except one operate variab= le. # Only one of both should be put into fdf. diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf index 3106a43fb7..a443d0f3a4 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -135,6 +135,12 @@ READ_LOCK_STATUS =3D TRUE INF FatPkg/EnhancedFatDxe/Fat.inf INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf =20 + # + # PCI Support + # + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + # # SATA Controller # diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBr= idgeLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostB= ridgeLib.inf new file mode 100644 index 0000000000..0e6f0797b0 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib= .inf @@ -0,0 +1,47 @@ +#/** @file +# PCI Host Bridge Library instance for Phytium SOC. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D PciHostBridgeLib + FILE_GUID =3D f965de0e-40fe-11eb-8290-3f9d1f895a80 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D ARM AARCH64 +# + +[Sources] + PciHostBridgeLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + DebugLib + +[Guids] + +[FixedPcd] + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax + gArmTokenSpaceGuid.PcdPciIoBase + gArmTokenSpaceGuid.PcdPciIoSize + gArmTokenSpaceGuid.PcdPciMmio32Base + gArmTokenSpaceGuid.PcdPciMmio32Size + gArmTokenSpaceGuid.PcdPciMmio64Base + gArmTokenSpaceGuid.PcdPciMmio64Size diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBr= idgeLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBri= dgeLib.c new file mode 100644 index 0000000000..8ed3516749 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib= .c @@ -0,0 +1,181 @@ +/** @file + PCI host bridge library instance for Phytium SOC. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#pragma pack(1) + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; + +#pragma pack () + +#define END_DEVICE_PATH_DEF { END_DEVICE_PATH_TYPE, \ + END_ENTIRE_DEVICE_PATH_SUBTYPE, \ + { END_DEVICE_PATH_LENGTH, 0 } \ + } + +#define ACPI_DEVICE_PATH_DEF(UID) {{ ACPI_DEVICE_PATH, ACPI_DP, \ + { (UINT8) (sizeof (ACPI_HID_DEVICE_PA= TH)), \ + (UINT8) (sizeof (ACPI_HID_DEVICE_PA= TH) >> 8)} \ + }, \ + EISA_PNP_ID (0x0A03), UID \ + } + +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[]= =3D { + { + ACPI_DEVICE_PATH_DEF (0), + END_DEVICE_PATH_DEF + }, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D { + L"Mem", L"I/O", L"Bus" +}; + +STATIC PCI_ROOT_BRIDGE mRootBridge =3D { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, { + // Io + FixedPcdGet64 (PcdPciIoBase), + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPciMmio32Base), + FixedPcdGet32 (PcdPciMmio32Base) + (FixedPcdGet32 (PcdPciMmio32Size) -= 1) + //0x7FFFFFFF + }, { + // MemAbove4G + FixedPcdGet64 (PcdPciMmio64Base), + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath +}; + +/** + Return all the root bridge instances in an array. + + @param[out] Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. + +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + OUT UINTN *Count + ) +{ + *Count =3D 1; + return &mRootBridge; +} + + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges(). + + @param[in] Bridges The root bridge instances array. + @param[in] Count The count of the array. + +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + IN PCI_ROOT_BRIDGE *Bridges, + IN UINTN Count + ) +{ + +} + + +/** + Inform the platform that the resource conflict happens. + + @param[in] HostBridgeHandle Handle of the Host Bridge. + @param[in] Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the reso= urces + for all the root bridges. The resource for each = root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of= the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + SubmitResources(). + +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + IN EFI_HANDLE HostBridgeHandle, + IN VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + BOOLEAN IsPrefetchable; + + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript= or++) { + ASSERT (Descriptor->ResType < + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)); + DEBUG ((DEBUG_INFO, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType= ], + Descriptor->AddrLen, + Descriptor->AddrRangeMax + )); + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + + IsPrefetchable =3D (Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != =3D 0; + + DEBUG ((DEBUG_INFO, " Granularity/SpecificFlag =3D %ld / %02x%= s\n", + Descriptor->AddrSpaceGranularity, + Descriptor->SpecificFlag, + (IsPrefetchable) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the end descriptor for root bridge + // + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72985): https://edk2.groups.io/g/devel/message/72985 Mute This Topic: https://groups.io/mt/81410917/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 10:07:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72979+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72979+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616006563; cv=none; d=zohomail.com; s=zohoarc; b=UDmxdOVVQPFFyFSZfuLXuCmcsA2HkyITL84T5LZWylEoF/YawsAd7dCYcB5rP8D0zKvVYC2MpnD6TNv8hFqRMfCA7yqf3qFh7LKEEa5CoEiZTLbJgmBqjnM9QdRT3iTd3GvTCJmGh44J2sS0VMaz//awKuOu2ajszFBWiRaHVsg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616006563; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Yz2epH6XJgrNaWldFSH3JB3r7Vi3s6ZShtlsKnaB07A=; b=KW5kzqJrbBqOLBj4aLFh/lylw4Jqu+NJ3f5NIh2SjwmpVY8mNjc/tegs0c60HnqRT81N1Hdj+URZUzP2kpz39h0ZXCMtLKniM/G6UJHF21hUwEFsyIXuXPqZ1NERsixyNhb7urxpNdk1DhVjaQHbGAEufe6Umay8bgbm2ps1I5w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72979+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616006563914235.09141649674325; Wed, 17 Mar 2021 11:42:43 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id mFDEYY1788612xnRkqLccskm; Wed, 17 Mar 2021 11:42:43 -0700 X-Received: from zg8tmty1ljiyny4xntqumjca.icoremail.net (zg8tmty1ljiyny4xntqumjca.icoremail.net [165.227.154.27]) by mx.groups.io with SMTP id smtpd.web09.3184.1615966022772472974 for ; Wed, 17 Mar 2021 00:27:03 -0700 X-Received: from localhost.localdomain (unknown [223.153.147.73]) by c1app7 (Coremail) with SMTP id BwINCgB3HOE4r1FgGIYZAA--.29335S8; Wed, 17 Mar 2021 15:26:59 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [edk2-devel] [PATCH v3 06/10] Silicon/Phytium: Added Spi driver support to FT2000/4 Date: Wed, 17 Mar 2021 15:26:43 +0800 Message-Id: <20210317072647.77340-7-jialing@phytium.com.cn> In-Reply-To: <20210317072647.77340-1-jialing@phytium.com.cn> References: <20210317072647.77340-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BwINCgB3HOE4r1FgGIYZAA--.29335S8 X-Coremail-Antispam: 1UD129KBjvJXoW3CF15XrW3GrWUJFy5ArWDArb_yoWDKFWkpF 47trsIgr48Gr4avw4rX340grs5A3s09a4DKrsxWFy5ZFs0gFy8Xa1qyry5Ja4qqr4qyFW8 WFsYqw1Uur1qyw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr 1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_GF4l42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1Y6r17MIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU1zuWDUUUU X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: yakJSfyDp86dOev6IYGqefisx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616006563; bh=qdr+0ogEKh0tU5J8Y3UipbjfUFByhLT6axjH5f/xCmM=; h=Cc:Date:From:Reply-To:Subject:To; b=co8iAhl1Xif0t+IaSKjNk2IxdIw19tSediruTSOphzrHr2t3J2JR5gWKSwLCDsNgLBW 09IJNZ6XQaMfpE3UeYBSlP63aoMhvBtAqsBaRNQRdZjCJLkoZ6FTw1NWTaXHywSBwSbhL 6rqLxn+YNEo4+K/QBQqpDUZnzo22EKqDpIM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The SpiDxe is to provide Spi bus read-write interfaces. v3: Optimized the codes to conform to specifications. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec | 9 + Platform/Phytium/DurianPkg/DurianPkg.dsc | 5 + Platform/Phytium/DurianPkg/DurianPkg.fdf | 2 + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf | 44 +++++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h | 64 ++++= +++ Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h | 51 +++++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c | 198 ++++= ++++++++++++++++ 7 files changed, 373 insertions(+) diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silico= n/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec index 48f430c88d..69842b89e0 100644 --- a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec +++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec @@ -38,4 +38,13 @@ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x0|UINT64|0x00000002 gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x0|UINT64|0x00000003 =20 + # + # SPI Flash Controller Register Base Address and Size + # + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase|0x0|UINT64|0x00000004 + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x0|UINT64|0x00000005 + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x0|UINT64|0x00000006 + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x0|UINT64|0x00000007 + [Protocols] + gSpiMasterProtocolGuid =3D { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0= x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}} diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index 3a9bc2289c..68698d613f 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -244,6 +244,11 @@ # ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf =20 + # + # Spi driver + # + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf + # # Usb Support # diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf index a443d0f3a4..1cf1927484 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -95,6 +95,8 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf =20 + INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf =20 diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf b/Silico= n/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf new file mode 100644 index 0000000000..21d75f268d --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf @@ -0,0 +1,44 @@ +#/** @file +# Phytium Spi Master Drivers. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D SpiDxe + FILE_GUID =3D 2ba95e5c-f7f5-11ea-bf18-67fdc5787495 + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SpiMasterDrvEntryPoint + +[Sources.common] + SpiDxe.c + SpiDxe.h + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Guids] + +[Protocols] + gSpiMasterProtocolGuid + +[FixedPcd] + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase + +[Depex] + TRUE diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h b/Silicon/= Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h new file mode 100644 index 0000000000..fbadd01921 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h @@ -0,0 +1,64 @@ +/** @file + Phytium Spi Drivers Header + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_DXE_H_ +#define SPI_DXE_H_ + +#include +#include +#include +#include +#include +#include + +#define SPI_MASTER_SIGNATURE SIGNATURE_32 ('M', 'S', 'P', 'I') +#define REG_MODE_REG 0x02C + +EFI_STATUS +EFIAPI +SpiMasterGetConfig ( + IN UINT8 CmdId, + OUT UINT32 *Config, + IN UINTN RegAddr + ); + +EFI_STATUS +EFIAPI +SpiMasterSetConfig ( + IN UINT8 CmdId, + IN UINT32 Config, + IN UINTN RegAddr + ); + +EFI_STATUS +EFIAPI +SpiMasterSetMode ( + IN UINT32 Config + ); + +EFI_STATUS +EFIAPI +SpiMasterInit ( + VOID + ); + +typedef struct { + EFI_SPI_DRV_PROTOCOL SpiMasterProtocol; + UINTN Signature; + EFI_HANDLE Handle; +} PHYT_SPI_MASTER; + +EFI_STATUS +EFIAPI +SpiMasterDrvEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +#endif // SPI_DXE_H_ diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.= h b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h new file mode 100644 index 0000000000..3ed64d1a5d --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h @@ -0,0 +1,51 @@ +/** @file + The Header of Protocol For SPI. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_H_ +#define SPI_H_ + +extern EFI_GUID gSpiMasterProtocolGuid; +typedef struct _EFI_SPI_DRV_PROTOCOL EFI_SPI_DRV_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *SPI_DRV_INIT_INTERFACE) ( + VOID + ); + +typedef +EFI_STATUS +(EFIAPI *SPI_DRV_SET_CONFIG_INTERFACE)( + IN UINT8 CmdId, + IN UINT32 Config, + IN UINTN RegAddr + ); + +typedef +EFI_STATUS +(EFIAPI *SPI_DRV_GET_CONFIG_INTERFACE)( + IN UINT8 CmdId, + OUT UINT32 *Config, + IN UINTN RegAddr + ); + +typedef +EFI_STATUS +(EFIAPI *SPI_DRV_CONFIG_MODE_INTERFACE)( + IN UINT32 Config + ); + +struct _EFI_SPI_DRV_PROTOCOL{ + SPI_DRV_INIT_INTERFACE SpiInit; + SPI_DRV_SET_CONFIG_INTERFACE SpiSetConfig; + SPI_DRV_GET_CONFIG_INTERFACE SpiGetConfig; + SPI_DRV_CONFIG_MODE_INTERFACE SpiSetMode; +}; + +#endif // SPI_H_ diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c b/Silicon/= Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c new file mode 100644 index 0000000000..885bbd6361 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c @@ -0,0 +1,198 @@ +/** @file + Phytium Spi Master Drivers. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SpiDxe.h" + +PHYT_SPI_MASTER *pSpiMasterInstance; +static UINTN mSpiControlBase; + +/** + This function inited a spi driver. + + @param None. + + @retval None. + +**/ +EFI_STATUS +EFIAPI +SpiMasterInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + + +/** + This function seted config to spi registers. + + @param[in] CmdId The id of command. + + @param[in] Config The value to be seted. + + @param[in] RegAddr The address of spi registers. + + @retval EFI_SUCCESS SpiMasterSetConfig() is executed successfully. + +**/ +EFI_STATUS +EFIAPI +SpiMasterSetConfig ( + IN UINT8 CmdId, + IN UINT32 Config, + IN UINTN RegAddr + ) +{ + UINTN SpiAddr; + UINT32 Value; + + SpiAddr =3D 0; + Value =3D 0; + + if (CmdId !=3D 0) { + Value =3D (CmdId << 24) | (Config & 0xffffff); + } else { + Value =3D Config; + } + + SpiAddr =3D mSpiControlBase + RegAddr; + MmioWrite32 (SpiAddr, Value); + + return EFI_SUCCESS; +} + + +/** + This function geted config from spi registers. + + @param[in] CmdId The id of command. + + @param[out] Config The pointer of the config. + + @param[in] RegAddr The address of spi registers. + + @retval EFI_SUCCESS SpiMasterGetConfig() is executed successfully. + +**/ +EFI_STATUS +EFIAPI +SpiMasterGetConfig ( + IN UINT8 CmdId, + OUT UINT32 *Config, + IN UINTN RegAddr + ) +{ + UINTN SpiAddr; + UINT32 Value; + + SpiAddr =3D 0; + Value =3D 0; + + SpiAddr =3D mSpiControlBase + RegAddr; + Value =3D MmioRead32 (SpiAddr); + + if (CmdId !=3D 0) { + *Config =3D Value & 0xffffff; + } else { + *Config =3D Value; + } + + return EFI_SUCCESS; +} + + +/** + This function seted spi mode. + + @param[in] Config The value to seted. + + @retval EFI_SUCCESS SpiMasterSetMode() is executed successfully. + +**/ +EFI_STATUS +EFIAPI +SpiMasterSetMode ( + IN UINT32 Config + ) +{ + + SpiMasterSetConfig (0, Config, REG_MODE_REG); + + return EFI_SUCCESS; +} + + +/** + This function inited the spi driver protocol. + + @param[in] SpiMasterProtocol A pointer to the master protocol struct. + + @retval EFI_SUCCESS SpiMasterInitProtocol() is executed succ= essfully. + +**/ +STATIC +EFI_STATUS +EFIAPI +SpiMasterInitProtocol ( + IN EFI_SPI_DRV_PROTOCOL *SpiMasterProtocol + ) +{ + + SpiMasterProtocol->SpiInit =3D SpiMasterInit; + SpiMasterProtocol->SpiSetConfig =3D SpiMasterSetConfig; + SpiMasterProtocol->SpiGetConfig =3D SpiMasterGetConfig; + SpiMasterProtocol->SpiSetMode =3D SpiMasterSetMode; + + return EFI_SUCCESS; +} + + +/** + This function is the entrypoint of the spi driver. + + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. + + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + + @retval other Some error occurs when executing this entry po= int. + +**/ +EFI_STATUS +EFIAPI +SpiMasterDrvEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + pSpiMasterInstance =3D AllocateRuntimeZeroPool (sizeof (PHYT_SPI_MASTER)= ); + if (pSpiMasterInstance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + mSpiControlBase =3D FixedPcdGet64 (PcdSpiControllerBase); + + SpiMasterInitProtocol (&pSpiMasterInstance->SpiMasterProtocol); + + pSpiMasterInstance->Signature =3D SPI_MASTER_SIGNATURE; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &(pSpiMasterInstance->Handle), + &gSpiMasterProtocolGuid, + &(pSpiMasterInstance->SpiMasterProtocol), + NULL + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72979): https://edk2.groups.io/g/devel/message/72979 Mute This Topic: https://groups.io/mt/81410911/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 10:07:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72980+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72980+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616006559; cv=none; d=zohomail.com; s=zohoarc; b=IYTZftuzs+9t316VNW1D4ZBF/2gLXOEwVv4QbbwyZaEh3zjspH9QGkSDqhXq3XgZ76wcaNw2X6bep7omUopNfNvytE7lUNt4CCZP9DfaLXcNStcRhIdUQxwjR7wLMQDkq7fzWTTf0CZi0BtObPdsdq0nIEH6+zeCRwvoYXEk6Cg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616006559; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=gVQJnTj+FTulOi8ru5zYHsVo4eY9Di8dVwh0kHysvqM=; b=OO19qPX2HSYEyfb3dKrhkp5UOdKupj0KuTR7Xg/3t8DxLKuTGyjHA8S0Gd9quYVErMVQ+l/uq8jWFUrOYUR5Pwm9wGGDA4Xp0+FfwBJqAIXhyqhdR7H2VTKa8C9ft5sM3wFT39ExV4jQDk/qqr8TcVFqzyPWsy/8NZOsWKHj4VY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72980+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616006559646155.5064262920465; Wed, 17 Mar 2021 11:42:39 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id UTjbYY1788612xye30KLuFqo; Wed, 17 Mar 2021 11:42:39 -0700 X-Received: from zg8tmty1ljiyny4xntqumjca.icoremail.net (zg8tmty1ljiyny4xntqumjca.icoremail.net [165.227.154.27]) by mx.groups.io with SMTP id smtpd.web12.3229.1615966023147735396 for ; Wed, 17 Mar 2021 00:27:03 -0700 X-Received: from localhost.localdomain (unknown [223.153.147.73]) by c1app7 (Coremail) with SMTP id BwINCgB3HOE4r1FgGIYZAA--.29335S9; Wed, 17 Mar 2021 15:27:00 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [edk2-devel] [PATCH v3 07/10] Silicon/Phytium: Added flash driver support to Phytium Silicon Date: Wed, 17 Mar 2021 15:26:44 +0800 Message-Id: <20210317072647.77340-8-jialing@phytium.com.cn> In-Reply-To: <20210317072647.77340-1-jialing@phytium.com.cn> References: <20210317072647.77340-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BwINCgB3HOE4r1FgGIYZAA--.29335S9 X-Coremail-Antispam: 1UD129KBjvAXoW3CF15XrW5Zw4kWryUWF1xZrb_yoW8CF18to Wxuw4SkrZ7KrWIva1jgr9rCw4xXFnavan3tr40yr9xXan7Xw43WFW2y3WUJrsxtw18K3Zx GryxXas8JF43Ja1kn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYN7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F 4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK67AK6r4xMx AIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_ Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwI xGrwCI42IY6xIIjxv20xvE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWx JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbsYFtUUUUU== X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: QEW9zRutefpEZivneLjbSxdRx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616006559; bh=3gkxMDwzDOWDayEeTbCAhbRtoSFKtL0RROVC9PctdCM=; h=Cc:Date:From:Reply-To:Subject:To; b=NE7cPzDbjp1wF3jLMam98EKOobZhXzGYduhGPmzyCpQ2Qcx75HynrVKB9h/4fLuGDuI XdMD0WJWQRyYuxVLGT4uAzEGNivotiom7IfACTVe5U1IwF/v4XG1YqaL499R4Au6sF/uv RjIY+ewBLIKMH7LY0TLrSykUvCeTLrIdaeA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The SpiNorFlashDxe provided norflash initialization, read-write, erase and other interfaces. v3: Optimized the codes to conform to specifications. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec | = 1 + Platform/Phytium/DurianPkg/DurianPkg.dsc | = 5 + Platform/Phytium/DurianPkg/DurianPkg.fdf | = 1 + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf | = 48 +++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h | = 99 +++++ Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h | = 74 ++++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c | = 424 ++++++++++++++++++++ 7 files changed, 652 insertions(+) diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silico= n/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec index 69842b89e0..2686ba3cc3 100644 --- a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec +++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec @@ -48,3 +48,4 @@ =20 [Protocols] gSpiMasterProtocolGuid =3D { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0= x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}} + gSpiNorFlashProtocolGuid =3D { 0x00b4af42, 0xfbd0, 0x11ea, { 0x80, 0x3a,= 0x27, 0xea, 0x5e, 0x65, 0xe3, 0xf6}} diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index 68698d613f..1c47051441 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -249,6 +249,11 @@ # Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf =20 + # + # NOR Flash driver + # + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf + # # Usb Support # diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf index 1cf1927484..831f7a6828 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -96,6 +96,7 @@ READ_LOCK_STATUS =3D TRUE INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf =20 INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf + INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf =20 INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash= Dxe.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe= .inf new file mode 100644 index 0000000000..2933dc502e --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf @@ -0,0 +1,48 @@ +#/** @file +# Phytium NorFlash Drivers. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D SpiNorFlashDxe + FILE_GUID =3D f37ef706-187c-48fd-9102-ddbf86f551be + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D NorFlashPlatformEntryPoint + +[Sources.common] + SpiNorFlashDxe.c + SpiNorFlashDxe.h + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + UefiLib + UefiBootServicesTableLib + UefiRuntimeLib + UefiDriverEntryPoint + +[FixedPcd] + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase +[Guids] + gEfiEventVirtualAddressChangeGuid + +[Protocols] + gSpiMasterProtocolGuid + gSpiNorFlashProtocolGuid + + [Depex] + TRUE diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash= Dxe.h b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h new file mode 100644 index 0000000000..55f5e8273f --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h @@ -0,0 +1,99 @@ +/** @file + Phytium NorFlash Drivers Header. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_NORFLASH_DXE_H_ +#define SPI_NORFLASH_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Norflash registers +// +#define REG_FLASH_CAP 0x000 +#define REG_RD_CFG 0x004 +#define REG_WR_CFG 0x008 +#define REG_FLUSH_REG 0x00C +#define REG_CMD_PORT 0x010 +#define REG_ADDR_PORT 0x014 +#define REG_HD_PORT 0x018 +#define REG_LD_PORT 0x01C +#define REG_CS_CFG 0x020 +#define REG_WIP_CFG 0x024 +#define REG_WP_REG 0x028 + +#define NORFLASH_SIGNATURE SIGNATURE_32 ('F', 'T', 'S', 'F') + +extern EFI_GUID gSpiMasterProtocolGuid; +extern EFI_GUID gSpiNorFlashProtocolGuid; + +// +// Platform Nor Flash Functions +// +EFI_STATUS +EFIAPI +NorFlashPlatformEraseSingleBlock ( + IN UINTN BlockAddress + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformErase ( + IN UINT64 Offset, + IN UINT64 Length + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformRead ( + IN UINTN Address, + IN VOID *Buffer, + OUT UINT32 Len + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformWrite ( + IN UINTN Address, + IN VOID *Buffer, + IN UINT32 Len + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformGetDevices ( + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformInitialization ( + VOID + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +typedef struct { + EFI_NORFLASH_DRV_PROTOCOL FlashProtocol; + UINTN Signature; + EFI_HANDLE Handle; +} NorFlash_Device; + +#endif // SPI_NORFLASH_DXE_H_ diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashP= rotocol.h b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashPr= otocol.h new file mode 100644 index 0000000000..b3ae26c5d4 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol= .h @@ -0,0 +1,74 @@ +/** @file + The Header of Protocol For NorFlash. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_NORFALSH_H_ +#define SPI_NORFALSH_H_ + +typedef struct _EFI_NORFLASH_DRV_PROTOCOL EFI_NORFLASH_DRV_PROTOCOL; +extern EFI_GUID gSpiNorFlashProtocolGuid; + +typedef struct { + UINTN DeviceBaseAddress; // Start address of the Device Base Ad= dress (DBA) + UINTN RegionBaseAddress; // Start address of one single region + UINTN Size; + UINTN BlockSize; + EFI_GUID Guid; +} NOR_FLASH_DEVICE_DESCRIPTION; + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_ERASE_INTERFACE) ( + IN UINT64 Offset, + IN UINT64 Length + ); + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE) ( + IN UINTN BlockAddress + ); + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_READ_INTERFACE) ( + IN UINTN Address, + IN VOID *Buffer, + OUT UINT32 Len + ); + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_WRITE_INTERFACE) ( + IN UINTN Address, + IN VOID *Buffer, + IN UINT32 Len + ); + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_GETDEVICE_INTERFACE) ( + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices + ); + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_INIT_INTERFACE) ( + VOID + ); + +struct _EFI_NORFLASH_DRV_PROTOCOL{ + NORFLASH_PLATFORM_INIT_INTERFACE Initialization; + NORFLASH_PLATFORM_GETDEVICE_INTERFACE GetDevices; + NORFLASH_PLATFORM_ERASE_INTERFACE Erase; + NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE EraseSingleBlock; + NORFLASH_PLATFORM_READ_INTERFACE Read; + NORFLASH_PLATFORM_WRITE_INTERFACE Write; +}; + +#endif // SPI_NORFALSH_H_ diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash= Dxe.c b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c new file mode 100644 index 0000000000..1c339c4478 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c @@ -0,0 +1,424 @@ +/** @file + Phytium NorFlash Drivers. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SpiNorFlashDxe.h" + +typedef struct { + UINT32 Flash_Index; + UINT32 Flash_Write; + UINT32 Flash_Erase; + UINT32 Flash_Pp; +} FLASH_CMD_INFO; + +STATIC EFI_EVENT mSpiNorFlashVirtualAddrChangeEvent; +STATIC UINTN mNorFlashControlBase; +STATIC UINT8 mCmdWrite; +STATIC UINT8 mCmdEares; +STATIC UINT8 mCmdPp; + +#define SPI_FLASH_BASE FixedPcdGet64 (PcdSpiFlashBase) +#define SPI_FLASH_SIZE FixedPcdGet64 (PcdSpiFlashSize) + +EFI_SPI_DRV_PROTOCOL *mSpiMasterProtocol; +NorFlash_Device *mFlashInstance; + +NOR_FLASH_DEVICE_DESCRIPTION mNorFlashDevices =3D { + SPI_FLASH_BASE, /* Device Base Address */ + SPI_FLASH_BASE, /* Region Base Address */ + SIZE_1MB * 16, /* Size */ + SIZE_64KB, /* Block Size */ + {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5= E, 0x59 } } +}; + + +/** + This function writed up to 256 bytes to flash through spi driver. + + @param[in] Address The address of the flash. + @param[in] Buffer The pointer of buffer to be writed. + @param[in] BufferSizeInBytes The bytes to be writed. + + @retval EFI_SUCCESS NorFlashWrite256() is executed successfull= y. + +**/ +STATIC +EFI_STATUS +NorFlashWrite256 ( + IN UINTN Address, + IN VOID *Buffer, + IN UINT32 BufferSizeInBytes + ) +{ + UINT32 Index; + UINT8 CmdId; + UINT32 *TempBuffer; + UINT8 WriteSize; + + TempBuffer =3D Buffer; + WriteSize =3D sizeof (UINT32); + + if (BufferSizeInBytes > 256) { + DEBUG ((DEBUG_ERROR, "The max length is 256 bytes.\n")); + return EFI_INVALID_PARAMETER; + } + + if ((BufferSizeInBytes % WriteSize) !=3D 0) { + DEBUG ((DEBUG_ERROR, "The length must four bytes aligned.\n")); + return EFI_INVALID_PARAMETER; + } + + if ((Address % WriteSize) !=3D 0) { + DEBUG ((DEBUG_ERROR, "The address must four bytes aligned.\n")); + return EFI_INVALID_PARAMETER; + } + + CmdId =3D mCmdPp; + mSpiMasterProtocol->SpiSetConfig (CmdId, 0x400000, REG_CMD_PORT); + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT); + + CmdId =3D mCmdWrite; + mSpiMasterProtocol->SpiSetConfig (CmdId, 0x000208, REG_WR_CFG); + + for (Index =3D 0; Index < (BufferSizeInBytes / WriteSize); Index++) { + MmioWrite32 ((Address + (Index * WriteSize)), TempBuffer[Index]); + } + + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_FLUSH_REG); + + mSpiMasterProtocol->SpiSetConfig (0, 0x0, REG_WR_CFG); + + return EFI_SUCCESS; +} + +/** + This function erased a sector of flash through spi driver. + + @param[in] BlockAddress The sector address to be erased. + + @retval None. + +**/ +STATIC +inline void +NorFlashPlatformEraseSector ( + IN UINTN BlockAddress + ) +{ + UINT8 CmdId; + + CmdId =3D mCmdPp; + mSpiMasterProtocol->SpiSetConfig (CmdId, 0x400000, REG_CMD_PORT); + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT); + + CmdId =3D mCmdEares; + mSpiMasterProtocol->SpiSetConfig (CmdId, 0x408000, REG_CMD_PORT); + mSpiMasterProtocol->SpiSetConfig (0, BlockAddress, REG_ADDR_PORT); + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT); + +} + + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed. + + @param[in] Context Event Context. + + @retval None. + +**/ +VOID +EFIAPI +PlatformNorFlashVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EfiConvertPointer (0x0, (VOID **)&mNorFlashControlBase); + EfiConvertPointer (0x0, (VOID **)&mSpiMasterProtocol->SpiGetConfig); + EfiConvertPointer (0x0, (VOID **)&mSpiMasterProtocol->SpiSetConfig); + EfiConvertPointer (0x0, (VOID **)&mSpiMasterProtocol); +} + + +/** + This function inited the flash platform. + + @param None. + + @retval EFI_SUCCESS NorFlashPlatformInitialization() is execut= ed successfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformInitialization ( + VOID + ) +{ + + mCmdWrite =3D 0x2; + mCmdEares =3D 0xD8; + mCmdPp =3D 0x6; + + mNorFlashControlBase =3D FixedPcdGet64 (PcdSpiControllerBase); + + return EFI_SUCCESS; +} + + +/** + This function geted the flash device information. + + @param[out] NorFlashDevices the pointer to store flash device informa= tion. + @param[out] Count the number of the flash device. + + @retval EFI_SUCCESS NorFlashPlatformGetDevices() is executed s= uccessfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformGetDevices ( + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices + ) +{ + + *NorFlashDevices =3D mNorFlashDevices; + + return EFI_SUCCESS; +} + + +/** + This function readed flash content form the specified area of flash. + + @param[in] Address The address of the flash. + @param[in] Buffer The pointer of the Buffer to be stored. + @param[out] Len The bytes readed form flash. + + @retval EFI_SUCCESS NorFlashPlatformRead() is executed succes= sfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformRead ( + IN UINTN Address, + IN VOID *Buffer, + OUT UINT32 Len + ) +{ + + DEBUG ((DEBUG_BLKIO, + "NorFlashPlatformRead: Address: 0x%lx Buffer:0x%p Len:0x%x\n", + Address, Buffer, Len + )); + + CopyMem ((VOID *)Buffer, (VOID *)Address, Len); + + return EFI_SUCCESS; +} + + +/** + This function erased one block flash content. + + @param[in] BlockAddress the BlockAddress to be erased. + + @retval EFI_SUCCESS NorFlashPlatformEraseSingleBlock() is exe= cuted successfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformEraseSingleBlock ( + IN UINTN BlockAddress + ) +{ + + NorFlashPlatformEraseSector (BlockAddress); + + return EFI_SUCCESS; +} + + +/** + This function erased the flash content of the specified area. + + @param[in] Offset the offset of the flash. + @param[in] Length length to be erased. + + @retval EFI_SUCCESS NorFlashPlatformErase() is executed succe= ssfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformErase ( + IN UINT64 Offset, + IN UINT64 Length + ) +{ + EFI_STATUS Status; + UINT64 Index; + UINT64 Count; + + Status =3D EFI_SUCCESS; + if ((Length % SIZE_64KB) =3D=3D 0) { + Count =3D Length / SIZE_64KB; + for (Index =3D 0; Index < Count; Index++) { + NorFlashPlatformEraseSingleBlock (Offset); + Offset +=3D SIZE_64KB; + } + } else { + Status =3D EFI_INVALID_PARAMETER; + } + + return Status; +} + + +/** + This function writed data to flash. + + @param[in] Address the address of the flash. + + @param[in] Buffer the pointer of the Buffer to be writed. + + @param[in] BufferSizeInBytes the bytes of the Buffer. + + @retval EFI_SUCCESS NorFlashPlatformWrite() is executed succe= ssfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformWrite ( + IN UINTN Address, + IN VOID *Buffer, + IN UINT32 BufferSizeInBytes + ) +{ + UINT32 Index; + UINT32 Remainder; + UINT32 Quotient; + EFI_STATUS Status; + UINTN TmpAddress; + + TmpAddress =3D Address; + Remainder =3D BufferSizeInBytes % 256; + Quotient =3D BufferSizeInBytes / 256; + + if (BufferSizeInBytes <=3D 256) { + Status =3D NorFlashWrite256 (TmpAddress, Buffer, BufferSizeInBytes); + } else { + for (Index =3D 0; Index < Quotient; Index++) { + Status =3D NorFlashWrite256 (TmpAddress, Buffer, 256); + TmpAddress +=3D 256; + Buffer +=3D 256; + } + + if (Remainder !=3D 0) { + Status =3D NorFlashWrite256 (TmpAddress, Buffer, Remainder); + } + } + + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + } + + return EFI_SUCCESS; + +} + + +/** + This function inited the flash driver protocol. + + @param[in] NorFlashProtocol A pointer to the norflash protocol struct. + + @retval EFI_SUCCESS NorFlashPlatformInitProtocol() is executed suc= cessfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformInitProtocol ( + IN EFI_NORFLASH_DRV_PROTOCOL *NorFlashProtocol + ) +{ + NorFlashProtocol->Initialization =3D NorFlashPlatformInitialization; + NorFlashProtocol->GetDevices =3D NorFlashPlatformGetDevices; + NorFlashProtocol->Erase =3D NorFlashPlatformErase; + NorFlashProtocol->EraseSingleBlock =3D NorFlashPlatformEraseSingleBlock; + NorFlashProtocol->Read =3D NorFlashPlatformRead; + NorFlashProtocol->Write =3D NorFlashPlatformWrite; + + return EFI_SUCCESS; +} + + +/** + This function is the entrypoint of the norflash driver. + + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. + + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + + @retval other Some error occurs when executing this entry po= int. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status =3D gBS->LocateProtocol ( + &gSpiMasterProtocolGuid, + NULL, + (VOID **)&mSpiMasterProtocol + ); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + mFlashInstance =3D AllocateRuntimeZeroPool (sizeof (NorFlash_Device)); + if (mFlashInstance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + NorFlashPlatformInitProtocol (&mFlashInstance->FlashProtocol); + + mFlashInstance->Signature =3D NORFLASH_SIGNATURE; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &(mFlashInstance->Handle), + &gSpiNorFlashProtocolGuid, + &(mFlashInstance->FlashProtocol), + NULL + ); + ASSERT_EFI_ERROR (Status); + + //Register for the virtual address change event + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + PlatformNorFlashVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mSpiNorFlashVirtualAddrChangeEvent + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72980): https://edk2.groups.io/g/devel/message/72980 Mute This Topic: https://groups.io/mt/81410912/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 10:07:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72986+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72986+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616006561; cv=none; d=zohomail.com; s=zohoarc; b=FDcInMcM5XsVqhNX3BYodldYE6SWGkB8w1ZTtmYpgtHrBXT7OspN6hi8bj2nHKhp+PP5FwulZVEDcMwh1SgJrxYxToJ696ImYhLwOS8lCWvihXDz4uJ9rF6hlddeIbpzHH9aASQ8M9+dA9sNJHD0LkzFYEuGQQve8ylbm1EXkTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616006561; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=FNRQT71E0yjI4bKfgpEkjTVa/WUtmewIgg3K62q8URc=; b=k46QCsdtv4r3tdCb0i9n9zsgHsya4+WAvaSK76OjrCRI8eg123K4IY4TZG2qSAtyvHhR3vZh8dqHHueJJbIHF4ZIWdJHpVuyd3IyQyaY7y26QcStldA6+TPkbIjjYdrwRuE/sPosqq9y/9MkCgDVoVnFA8OWv+XSUo7STpO4MgE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72986+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616006561370104.72598242284494; Wed, 17 Mar 2021 11:42:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id b9PpYY1788612xtOlFYptCx5; Wed, 17 Mar 2021 11:42:40 -0700 X-Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by mx.groups.io with SMTP id smtpd.web09.3185.1615966023546591780 for ; Wed, 17 Mar 2021 00:27:04 -0700 X-Received: from localhost.localdomain (unknown [223.153.147.73]) by c1app7 (Coremail) with SMTP id BwINCgB3HOE4r1FgGIYZAA--.29335S10; Wed, 17 Mar 2021 15:27:00 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [edk2-devel] [PATCH v3 08/10] Silicon/Phytium: Added fvb driver for norflash Date: Wed, 17 Mar 2021 15:26:45 +0800 Message-Id: <20210317072647.77340-9-jialing@phytium.com.cn> In-Reply-To: <20210317072647.77340-1-jialing@phytium.com.cn> References: <20210317072647.77340-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BwINCgB3HOE4r1FgGIYZAA--.29335S10 X-Coremail-Antispam: 1UD129KBjvAXoWDJw4UXrW3KF15Kr4DKr13twb_yoWrCry3Ao WxZr4fXw18trWSgFs8KrWjk3yxJFnaqanxtrs5Zry2q3Z5Jw1a9FWIy3WUWw4ft34jkrnx KryfX3s5JFW3trykn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYM7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r 4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl 6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6x IIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_ Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFwVW8Cw CF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j 6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64 vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_ Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0x vEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUvg4hUUUUU= X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: 8lfFCsLKct3TdToCqSpjdycWx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616006560; bh=Lk1oggHi+GnsrahYBORVSG8Xc6mzNK4vxqvOCNLM31c=; h=Cc:Date:From:Reply-To:Subject:To; b=hZtWfI/wj4FFh7/FBtCQvBk/B+BWnkshk9pGNWc7rq0OMVN9o3RxLIH7+MzpVbdJMTA i9sLOaof+3yrxhG9dyRhrp5x1HGK0zUgdMScGswN44AuEHbE9VKsYHdB6UFiU5y6K179O BOWJoaPCAD23JCpsfnuJDdCzXAYirqU2afk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The FlashFvbDxe provided the fvb protocol, which requested by the flash operators. v3: Optimized the codes to conform to specifications. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Platform/Phytium/DurianPkg/DurianPkg.dsc | = 1 + Platform/Phytium/DurianPkg/DurianPkg.fdf | = 1 + Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf | 6= 1 + Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h | 10= 4 ++ Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c | 130= 4 ++++++++++++++++++++ 5 files changed, 1471 insertions(+) diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index 1c47051441..99034365d3 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -253,6 +253,7 @@ # NOR Flash driver # Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf + Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf =20 # # Usb Support diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf index 831f7a6828..67458458dd 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -103,6 +103,7 @@ READ_LOCK_STATUS =3D TRUE =20 INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf =20 diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbD= xe.inf b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.i= nf new file mode 100644 index 0000000000..ff23721d6e --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf @@ -0,0 +1,61 @@ +#/** @file +# Phytium NorFlash Fvb Drivers. +# +# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D FlashFvbDxe + FILE_GUID =3D b8923820-3e7c-11eb-b12c-17525e90ecc8 + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 0.1 + ENTRY_POINT =3D FvbEntryPoint + +[Sources] + FlashFvbDxe.c + FlashFvbDxe.h + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + DxeServicesTableLib + HobLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiRuntimeLib + UefiDriverEntryPoint + +[Guids] + gEfiAuthenticatedVariableGuid + gEfiEventVirtualAddressChangeGuid + gEfiSystemNvDataFvGuid + gEfiVariableGuid + +[Protocols] + gEfiDevicePathProtocolGuid + gEfiFirmwareVolumeBlockProtocolGuid + gSpiNorFlashProtocolGuid + +[Pcd.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize + +[Depex] + gSpiNorFlashProtocolGuid diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbD= xe.h b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h new file mode 100644 index 0000000000..e63ff9f220 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h @@ -0,0 +1,104 @@ +/** @file + Phytium NorFlash Fvb Drivers Header. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef FVB_FLASH_DXE_H_ +#define FVB_FLASH_DXE_H_ + +#include +#include +#include + +#define GET_DATA_OFFSET(BaseAddr, Lba, LbaSize) ((BaseAddr) + (UINTN)((Lba= ) * (LbaSize))) +#define FVB_FLASH_SIGNATURE SIGNATURE_32('S', 'N', '= O', 'R') +#define INSTANCE_FROM_FVB_THIS(a) CR(a, FT_FVB_DEVICE, Fvb= Protocol, FVB_FLASH_SIGNATURE) + +typedef struct _FT_FVB_DEVICE FT_FVB_DEVICE; + +#define NOR_FLASH_ERASE_RETRY 10 + +typedef struct { + VENDOR_DEVICE_PATH Vendor; + EFI_DEVICE_PATH_PROTOCOL End; + } FT_FVB_DEVICE_PATH; + +struct _FT_FVB_DEVICE { + UINT32 Signature; + EFI_HANDLE Handle; + + UINTN DeviceBaseAddress; + UINTN RegionBaseAddress; + UINTN Size; + EFI_LBA StartLba; + EFI_BLOCK_IO_MEDIA Media; + + EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol; + + FT_FVB_DEVICE_PATH DevicePath; + EFI_NORFLASH_DRV_PROTOCOL *SpiFlashProtocol; + VOID *ShadowBuffer; + UINTN FvbSize; + }; + +EFI_STATUS +EFIAPI +FvbGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This, + OUT EFI_FVB_ATTRIBUTES_2 * Attributes + ); + +EFI_STATUS +EFIAPI +FvbSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This, + IN OUT EFI_FVB_ATTRIBUTES_2 * Attributes + ); + +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This, + OUT EFI_PHYSICAL_ADDRESS * Address + ); + +EFI_STATUS +EFIAPI +FvbGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This, + IN EFI_LBA Lba, + OUT UINTN * BlockSize, + OUT UINTN * NumberOfBlocks + ); + +EFI_STATUS +EFIAPI +FvbRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN * NumBytes, + IN OUT UINT8 * Buffer + ); + +EFI_STATUS +EFIAPI +FvbWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN * NumBytes, + IN UINT8 * Buffer + ); + +EFI_STATUS +EFIAPI +FvbEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This, + ... + ); + +#endif // FVB_FLASH_DXE_H_ diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbD= xe.c b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c new file mode 100644 index 0000000000..794db68987 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c @@ -0,0 +1,1304 @@ +/** @file + Phytium NorFlash Fvb Drivers. + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "FlashFvbDxe.h" + +STATIC EFI_EVENT FvbVirtualAddrChangeEvent; +STATIC FT_FVB_DEVICE *FvbDevice; +STATIC UINTN mFlashNvStorageVariableBase; +STATIC UINTN mFlashNvStorageFtwWorkingBase; +STATIC UINTN mFlashNvStorageFtwSpareBase; +STATIC UINT32 mFlashNvStorageVariableSize; +STATIC UINT32 mFlashNvStorageFtwWorkingSize; +STATIC UINT32 mFlashNvStorageFtwSpareSize; + +STATIC FT_FVB_DEVICE FvbFlashInstanceTemplate =3D { + FVB_FLASH_SIGNATURE, // Signature + NULL, // Handle ... NEED TO BE FILLED + 0, // DeviceBaseAddress ... NEED TO BE FILLED + 0, // RegionBaseAddress ... NEED TO BE FILLED + 0, // Size ... NEED TO BE FILLED + 0, // StartLba + { + 0, // MediaId ... NEED TO BE FILLED + FALSE, // RemovableMedia + TRUE, // MediaPresent + FALSE, // LogicalPartition + FALSE, // ReadOnly + FALSE, // WriteCaching; + 0, // BlockSize ... NEED TO BE FILLED + 4, // IoAlign + 0, // LastBlock ... NEED TO BE FILLED + 0, // LowestAlignedLba + 1, // LogicalBlocksPerPhysicalBlock + }, //Media; + { + FvbGetAttributes, // GetAttributes + FvbSetAttributes, // SetAttributes + FvbGetPhysicalAddress, // GetPhysicalAddress + FvbGetBlockSize, // GetBlockSize + FvbRead, // Read + FvbWrite, // Write + FvbEraseBlocks, // EraseBlocks + NULL, // ParentHandle + }, // FvbProtoccol; + + { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8) sizeof (VENDOR_DEVICE_PATH), + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + { + 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + }, // GUID ... NEED TO BE FILLED + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + sizeof (EFI_DEVICE_PATH_PROTOCOL), + 0 + } + } + }, // DevicePath + + NULL, // SpiFlashProtocol ... NEED TO BE FILLED + NULL, // ShadowBuffer ... NEED TO BE FILLED + 0 // Fvb Size +}; + + +/** + Erases a single block of flash. + + @param[in] FlashInstance The poiter of the fvb device sturct. + + @param[in] BlockAddress Physical address of Lba to be erased. + + @retval EFI_SUCCESS The erase single block request successfull= y completed. + +**/ +STATIC +EFI_STATUS +FvbFlashEraseSingleBlock ( + IN FT_FVB_DEVICE *FlashInstance, + IN UINTN BlockAddress + ) +{ + EFI_STATUS Status; + UINTN Index; + EFI_TPL OriginalTPL; + + if ( ! EfiAtRuntime ()) { + OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + } else { + OriginalTPL =3D TPL_HIGH_LEVEL; + } + + Index =3D 0; + + do { + Status =3D FlashInstance->SpiFlashProtocol->EraseSingleBlock (BlockAdd= ress); + Index++; + } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status =3D=3D EFI_WRITE_PRO= TECTED)); + + if (Index =3D=3D NOR_FLASH_ERASE_RETRY) { + DEBUG (( + DEBUG_ERROR, + "EraseSingleBlock(BlockAddress=3D0x%08x: BlockLocked Error (try to e= rase % d times)\n", + BlockAddress, + Index + )); + } + + if ( ! EfiAtRuntime ()) { + gBS->RestoreTPL (OriginalTPL); + } + + return Status; +} + + +/** + Readed the specified number of bytes from the form the block to output b= uffer. + + @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance. + + @param[in] Lba The starting logical block index to wri= te to. + + @param[in] Offset Offset into the block at which to begin= writing. + + @param[in] BufferSizeInBytes The number of bytes to be writed. + + @param[out] Buffer The pointer to a caller-allocated buffe= r that + contains the source for the write. + + @retval EFI_SUCCESS FvbFlashRead() is executed successfully. + +**/ +STATIC +EFI_STATUS +FvbFlashRead ( + IN FT_FVB_DEVICE *FlashInstance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN BufferSizeInBytes, + OUT VOID *Buffer + ) +{ + UINTN Address; + + Address =3D GET_DATA_OFFSET ( + FlashInstance->RegionBaseAddress, + Lba, + FlashInstance->Media.BlockSize + ) + Offset; + + if (BufferSizeInBytes =3D=3D 0) { + return EFI_SUCCESS; + } + + // The buffer must be valid + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + return FlashInstance->SpiFlashProtocol->Read (Address, Buffer, BufferSiz= eInBytes); +} + + +/** + Write a full or portion of a block. It must not span block boundaries; t= hat is, + Offset + *NumBytes <=3D FlashInstance->Media.BlockSize. + + @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance. + + @param[in] Lba The starting logical block index to wri= te to. + + @param[in] Offset Offset into the block at which to begin= writing. + + @param[in] BufferSizeInBytes The number of bytes to be writed. + + @param[out] Buffer The pointer to a caller-allocated buffe= r that + contains the source for the write. + + @retval EFI_SUCCESS FvbWriteBlock() is executed successfull= y. + + @retval EFI_BAD_BUFFER_SIZE The write spaned block boundaries. + +**/ +STATIC +EFI_STATUS +FvbWriteBlock ( + IN FT_FVB_DEVICE *FlashInstance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN BufferSizeInBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN BlockSize; + UINTN BlockAddress; + + // Detect WriteDisabled state + if (FlashInstance->Media.ReadOnly =3D=3D TRUE) { + DEBUG (( + DEBUG_ERROR, + "FvbWriteBlock: ERROR - Can not write:Device is in WriteDisabled sta= te.\n" + )); + // It is in WriteDisabled state, return an error right away + return EFI_ACCESS_DENIED; + } + + // Cache the block size to avoid de-referencing pointers all the time + BlockSize =3D FlashInstance->Media.BlockSize; + + // The write must not span block boundaries. + // We need to check each variable individually because adding two large = values together overflows. + if ((Offset >=3D BlockSize) || + (BufferSizeInBytes > BlockSize) || + ((Offset + BufferSizeInBytes) > BlockSize)) + { + DEBUG (( + DEBUG_ERROR, + "FvbWriteBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset =3D0x %x + NumB= ytes =3D0x%x) > BlockSize =3D0x%x\n", + Offset, + BufferSizeInBytes, + BlockSize + )); + return EFI_BAD_BUFFER_SIZE; + } + + // We must have some bytes to write + if (BufferSizeInBytes =3D=3D 0) { + DEBUG (( + DEBUG_ERROR, + "FvbWriteBlock: ERROR - EFI_BAD_BUFFER_SIZE: NumBytes =3D=3D 0\n" + )); + return EFI_BAD_BUFFER_SIZE; + } + + // Check we did get some memory. Buffer is BlockSize. + if (FlashInstance->ShadowBuffer =3D=3D NULL) { + DEBUG (( + DEBUG_ERROR, + "FvbWriteBlock: ERROR - ShadowBuffer is NULL!\n" + )); + return EFI_DEVICE_ERROR; + } + + // + // Write the word to NOR. + // + BlockAddress =3D GET_DATA_OFFSET ( + FlashInstance->RegionBaseAddress, + Lba, + FlashInstance->Media.BlockSize + ); + + // Read NOR Flash data into shadow buffer + Status =3D FlashInstance->SpiFlashProtocol->Read ( + BlockAddress, + FlashInstance->ShadowBuffer, + BlockSize + ); + if (EFI_ERROR (Status)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + + // Put the data at the appropriate location inside the buffer area + CopyMem ( + (VOID *) ((UINTN)FlashInstance->ShadowBuffer + Offset), + Buffer, + BufferSizeInBytes + ); + + Status =3D FlashInstance->SpiFlashProtocol->EraseSingleBlock (BlockAddre= ss); + if (EFI_ERROR (Status)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + + // Write the modified buffer back to the NorFlash + Status =3D FlashInstance->SpiFlashProtocol->Write (BlockAddress, + FlashInstance->ShadowBuffer, + BlockSize + ); + if (EFI_ERROR (Status)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + + +/** + Writes the specified number of bytes from the input buffer to the block. + + @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance. + + @param[in] Lba The starting logical block index to writ= e to. + + @param[in] Offset Offset into the block at which to begin = writing. + + @param[in] BufferSizeInBytes The number of bytes to be writed. + + @param[in] Buffer The pointer to a caller-allocated buffer= that + contains the source for the write. + + @retval EFI_SUCCESS FvbFlashWrite() is executed successfully. + + @retval EFI_WRITE_PROTECTED Flash state is in the WriteDisabled stat= e. + + @retval EFI_INVALID_PARAMETER The pointer of Buffer is NULL. + +**/ +STATIC +EFI_STATUS +FvbFlashWrite ( + IN FT_FVB_DEVICE *FlashInstance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN BufferSizeInBytes, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT32 BlockSize; + UINT32 BlockOffset; + UINTN RemainingBytes; + UINTN WriteSize; + + if (FlashInstance->Media.ReadOnly =3D=3D TRUE) { + return EFI_WRITE_PROTECTED; + } + + if (BufferSizeInBytes =3D=3D 0) { + return EFI_SUCCESS; + } + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Status =3D EFI_SUCCESS; + BlockSize =3D FlashInstance->Media.BlockSize; + BlockOffset =3D Offset; + RemainingBytes =3D BufferSizeInBytes; + + // The write must not span block boundaries. + // We need to check each variable individually because adding + // two large values together overflows. + if (Offset >=3D BlockSize) { + DEBUG (( + DEBUG_ERROR, + "FvbFlashWrite: ERROR - EFI_BAD_BUFFER_SIZE: Offset =3D0x%x > BlockS= ize =3D0x%x\n", + Offset, + BlockSize + )); + return EFI_BAD_BUFFER_SIZE; + } + + // We must have some bytes to read + // Write either all the remaining bytes, or the number of bytes that bri= ng + // us up to a block boundary, whichever is less. + // (DiskOffset | (BlockSize - 1)) + 1) rounds DiskOffset up to the next + // block boundary (even if it is already on one). + WriteSize =3D MIN (RemainingBytes, BlockSize - BlockOffset); + + do { + Status =3D FvbWriteBlock ( + FlashInstance, + Lba, + BlockOffset, + WriteSize, + Buffer + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // Now continue writing either all the remaining bytes or single block= s. + RemainingBytes -=3D WriteSize; + Buffer =3D (UINT8 *) Buffer + WriteSize; + Lba++; + BlockOffset =3D 0; + WriteSize =3D MIN (RemainingBytes, BlockSize); + } while (RemainingBytes); + + return Status; +} + + +/** + Initialises the FV Header and Variable Store Header + to support variable operations. + + @param[in] Ptr Location to initialise the headers. + + @retval EFI_SUCCESS FvbInitFvAndVariableStoreHeaders() + is executed successfully. + +**/ +STATIC +EFI_STATUS +FvbInitFvAndVariableStoreHeaders ( + IN FT_FVB_DEVICE *FlashInstance + ) +{ + EFI_STATUS Status; + VOID * Headers; + UINTN HeadersLength; + UINT32 TempAttributes; + EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + + HeadersLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADER) + + sizeof (EFI_FV_BLOCK_MAP_ENTRY) + + sizeof (VARIABLE_STORE_HEADER); + + Headers =3D AllocateZeroPool (HeadersLength); + + // FirmwareVolumeHeader->FvLength is declared to have the Variable area + // AND the FTW working area AND the FTW Spare contiguous. + ASSERT (mFlashNvStorageVariableBase + mFlashNvStorageVariableSize =3D=3D= mFlashNvStorageFtwWorkingBase); + ASSERT (mFlashNvStorageFtwWorkingBase + mFlashNvStorageFtwWorkingSize = =3D=3D mFlashNvStorageFtwSpareBase); + + // Check if the size of the area is at least one block size + ASSERT ((mFlashNvStorageVariableSize > 0) && (mFlashNvStorageVariableSiz= e / FlashInstance->Media.BlockSize > 0)); + ASSERT ((mFlashNvStorageFtwWorkingSize > 0) && (mFlashNvStorageFtwWorkin= gSize / FlashInstance->Media.BlockSize > 0)); + ASSERT ((mFlashNvStorageFtwSpareSize > 0) && (mFlashNvStorageFtwSpareSiz= e / FlashInstance->Media.BlockSize > 0)); + + // Ensure the Variable area Base Addresses are aligned on a block size b= oundaries + ASSERT (mFlashNvStorageVariableBase % FlashInstance->Media.BlockSize =3D= =3D 0); + ASSERT (mFlashNvStorageFtwWorkingBase % FlashInstance->Media.BlockSize = =3D=3D 0); + ASSERT (mFlashNvStorageFtwSpareBase % FlashInstance->Media.BlockSize =3D= =3D 0); + + // + // EFI_FIRMWARE_VOLUME_HEADER + // + FirmwareVolumeHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)Headers; + CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid= ); + FirmwareVolumeHeader->FvLength =3D FlashInstance->FvbSize; + + TempAttributes =3D ( + EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled + EFI_FVB2_READ_STATUS | // Reads are currently = enabled + EFI_FVB2_STICKY_WRITE | // A block erase is req= uired to + EFI_FVB2_MEMORY_MAPPED | // It is memory mapped + EFI_FVB2_ERASE_POLARITY | // After erasure all bi= ts take this value + EFI_FVB2_WRITE_STATUS | // Writes are currently= enabled + EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enabled + ); + + FirmwareVolumeHeader->Signature =3D EFI_FVH_SIGNATURE; + FirmwareVolumeHeader->Attributes =3D (EFI_FVB_ATTRIBUTES_2) TempAttribut= es; + + FirmwareVolumeHeader->HeaderLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADE= R) + sizeof (EFI_FV_BLOCK_MAP_ENTRY); + FirmwareVolumeHeader->Revision =3D EFI_FVH_REVISION; + FirmwareVolumeHeader->BlockMap[0].NumBlocks =3D FlashInstance->Media.Las= tBlock + 1; + FirmwareVolumeHeader->BlockMap[0].Length =3D FlashInstance->Media.Blo= ckSize; + FirmwareVolumeHeader->BlockMap[1].NumBlocks =3D 0; + FirmwareVolumeHeader->BlockMap[1].Length =3D 0; + FirmwareVolumeHeader->Checksum =3D CalculateCheckSum16 ( + (UINT16 *)FirmwareVolumeHeader, + FirmwareVolumeHeader->HeaderLength + ); + + // + // VARIABLE_STORE_HEADER + // + VariableStoreHeader =3D (VARIABLE_STORE_HEADER *) ((UINTN)Headers + Firm= wareVolumeHeader->HeaderLength); + CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGui= d); + VariableStoreHeader->Size =3D mFlashNvStorageVariableSize - FirmwareVo= lumeHeader->HeaderLength; + VariableStoreHeader->Format =3D VARIABLE_STORE_FORMATTED; + VariableStoreHeader->State =3D VARIABLE_STORE_HEALTHY; + + // Install the combined super-header in the NorFlash + Status =3D FvbWrite (&FlashInstance->FvbProtocol, 0, 0, &HeadersLength, = Headers); + + FreePool (Headers); + + return Status; +} + + +/** + Check the integrity of firmware volume header. + + @param[in] FwVolHeader A pointer to a firmware volume header + + @retval EFI_SUCCESS The firmware volume is consistent + + @retval EFI_NOT_FOUND The firmware volume has been corrupted. + +**/ +STATIC +EFI_STATUS +FvbValidateFvHeader ( + IN FT_FVB_DEVICE *FlashInstance + ) +{ + UINT16 Checksum; + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + UINTN VariableStoreLength; + UINTN FvLength; + + FwVolHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)GET_DATA_OFFSET (FlashInst= ance->RegionBaseAddress, + FlashInstance->StartLba, + FlashInstance->Media.Block= Size + ); + FvLength =3D FlashInstance->FvbSize; + + + if ((FwVolHeader->Revision !=3D EFI_FVH_REVISION) || + (FwVolHeader->Signature !=3D EFI_FVH_SIGNATURE) || + (FwVolHeader->FvLength !=3D FvLength)) + { + DEBUG (( + DEBUG_ERROR, + "ValidateFvHeader: No Firmware Volume header present\n" + )); + return EFI_NOT_FOUND; + } + + // Check the Firmware Volume Guid + if ( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid)= =3D=3D FALSE ) { + DEBUG (( + DEBUG_ERROR, + "ValidateFvHeader: Firmware Volume Guid non-compatible\n" + )); + return EFI_NOT_FOUND; + } + + // Verify the header checksum + Checksum =3D CalculateSum16 ((UINT16 *)FwVolHeader, FwVolHeader->HeaderL= ength); + if (Checksum !=3D 0) { + DEBUG (( + DEBUG_ERROR, + "ValidateFvHeader: FV checksum is invalid (Checksum:0x%X)\n", + Checksum)); + return EFI_NOT_FOUND; + } + + VariableStoreHeader =3D (VARIABLE_STORE_HEADER *) ((UINTN)FwVolHeader + = FwVolHeader->HeaderLength); + + // Check the Variable Store Guid + if ( ! CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) = && + ! CompareGuid (&VariableStoreHeader->Signature, + &gEfiAuthenticatedVariableGuid)) + { + DEBUG (( + DEBUG_ERROR, + "%a: Variable Store Guid non-compatible\n" + )); + return EFI_NOT_FOUND; + } + + VariableStoreLength =3D mFlashNvStorageVariableSize - FwVolHeader->Heade= rLength; + if (VariableStoreHeader->Size !=3D VariableStoreLength) { + DEBUG (( + DEBUG_ERROR, + "ValidateFvHeader: Variable Store Length does not match\n" + )); + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + + +/** + The FvbGetAttributes() function retrieves the attributes and + current settings of the block. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL in= stance. + + @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attribu= tes and + current settings are returned. + Type EFI_FVB_ATTRIBUTES_2 is defined in + EFI_FIRMWARE_VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were returned. + +**/ +EFI_STATUS +EFIAPI +FvbGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; + CONST FT_FVB_DEVICE *FlashInstance; + + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + + FlashFvbAttributes =3D (EFI_FVB_ATTRIBUTES_2) ( + EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled + EFI_FVB2_READ_STATUS | // Reads are currently enabled + EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bit= s into EFI_FVB2_ERASE_POLARITY + EFI_FVB2_MEMORY_MAPPED | // It is memory mapped + EFI_FVB2_ERASE_POLARITY // After erasure all bits take this valu= e (i.e. '1') + ); + + // Check if it is write protected + if (FlashInstance->Media.ReadOnly !=3D TRUE) { + FlashFvbAttributes =3D FlashFvbAttributes | + EFI_FVB2_WRITE_STATUS | // Writes are curren= tly enabled + EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be ena= bled + } + + *Attributes =3D FlashFvbAttributes; + + return EFI_SUCCESS; +} + + +/** + The FvbSetAttributes() function sets configurable firmware volume attrib= utes + and returns the new settings of the firmware volume. + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL inst= ance. + + @param Attributes On input, Attributes is a pointer to + EFI_FVB_ATTRIBUTES_2 that contains the d= esired + firmware volume settings. + On successful return, it contains the new + settings of the firmware volume. + + @retval EFI_SUCCESS The firmware volume attributes were retu= rned. + + @retval EFI_INVALID_PARAMETER The attributes requested are in conflict= with + the capabilities as declared in the firm= ware + volume header. + +**/ +EFI_STATUS +EFIAPI +FvbSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + The FvbGetPhysicalAddress() function retrieves the base address of + a memory-mapped firmware volume. This function should be called + only for memory-mapped firmware volumes. + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Address Pointer to a caller-allocated + EFI_PHYSICAL_ADDRESS that, on successful + return from GetPhysicalAddress(), contains the + base address of the firmware volume. + + @retval EFI_SUCCESS The firmware volume base address was returned. + + @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped. + +**/ +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ) +{ + ASSERT (Address !=3D NULL); + + *Address =3D mFlashNvStorageVariableBase; + + return EFI_SUCCESS; +} + + +/** + The FvbGetBlockSize() function retrieves the size of the requested + block. It also returns the number of additional blocks with + the identical size. The FvbGetBlockSize() function is used to + retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER). + + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL inst= ance. + + @param Lba Indicates the block whose size to return. + + @param BlockSize Pointer to a caller-allocated UINTN in w= hich + the size of the block is returned. + + @param NumberOfBlocks Pointer to a caller-allocated UINTN in + which the number of consecutive blocks, + starting with Lba, is returned. All + blocks in this range have a size of + BlockSize. + + + @retval EFI_SUCCESS The firmware volume base address was ret= urned. + + @retval EFI_INVALID_PARAMETER The requested LBA is out of range. + +**/ +EFI_STATUS +EFIAPI +FvbGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks + ) +{ + EFI_STATUS Status; + FT_FVB_DEVICE *FlashInstance; + + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + + if (Lba > FlashInstance->Media.LastBlock) { + Status =3D EFI_INVALID_PARAMETER; + } else { + // This is easy because in this platform each NorFlash device has equa= l sized blocks. + *BlockSize =3D (UINTN) FlashInstance->Media.BlockSize; + *NumberOfBlocks =3D (UINTN) (FlashInstance->Media.LastBlock - Lba + 1); + Status =3D EFI_SUCCESS; + } + + return Status; +} + + +/** + Reads the specified number of bytes into a buffer from the specified blo= ck. + + The FvbRead() function reads the requested number of bytes from the + requested block and stores them in the provided buffer. + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Lba The starting logical block index from which = to read. + + @param Offset Offset into the block at which to begin read= ing. + + @param NumBytes Pointer to a UINTN. + At entry, *NumBytes contains the total size = of the + buffer. + At exit, *NumBytes contains the total number= of + bytes read. + + @param Buffer Pointer to a caller-allocated buffer that wi= ll be + used to hold the data that is read. + + @retval EFI_SUCCESS The firmware volume was read successfully, a= nd + contents are in Buffer. + + @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary. + On output, NumBytes contains the total numbe= r of + bytes returned in Buffer. + + @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled s= tate. + + @retval EFI_DEVICE_ERROR The block device is not functioning correctl= y and + could not be read. +**/ +EFI_STATUS +EFIAPI +FvbRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer + ) +{ + UINTN BlockSize; + FT_FVB_DEVICE *FlashInstance; + EFI_STATUS Status; + + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + + // Cache the block size to avoid de-referencing pointers all the time + BlockSize =3D FlashInstance->Media.BlockSize; + + // The read must not span block boundaries. + // We need to check each variable individually because adding two large = values together overflows. + if ((Offset >=3D BlockSize) || + (*NumBytes > BlockSize) || + ((Offset + *NumBytes) > BlockSize)) { + return EFI_BAD_BUFFER_SIZE; + } + + // We must have some bytes to read + if (*NumBytes =3D=3D 0) { + return EFI_BAD_BUFFER_SIZE; + } + + Status =3D FvbFlashRead ( + FlashInstance, + FlashInstance->StartLba + Lba, + Offset, + *NumBytes, + Buffer + ); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + + +/** + Writes the specified number of bytes from the input buffer to the block. + + The FvbWrite() function writes the specified number of bytes from + the provided buffer to the specified block and offset. + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Lba The starting logical block index to write to. + + @param Offset Offset into the block at which to begin writ= ing. + + @param NumBytes The pointer to a UINTN. + At entry, *NumBytes contains the total size = of the + buffer. + At exit, *NumBytes contains the total number= of + bytes actually written. + + @param Buffer The pointer to a caller-allocated buffer that + contains the source for the write. + + @retval EFI_SUCCESS The firmware volume was written successfully. + + @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA bounda= ry. + On output, NumBytes contains the total numbe= r of + bytes actually written. + + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled = state. + + @retval EFI_DEVICE_ERROR The block device is malfunctioning and could= not be + written. + +**/ +EFI_STATUS +EFIAPI +FvbWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + FT_FVB_DEVICE *FlashInstance; + + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + + return FvbFlashWrite (FlashInstance, + FlashInstance->StartLba + Lba, + Offset, + *NumBytes, + Buffer + ); +} + + +/** + Erases and initialises a firmware volume block. + + The FvbEraseBlocks() function erases one or more blocks as denoted + by the variable argument list. + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL + instance. + + @param ... The variable argument list is a list of = tuples. + Each tuple describes a range of LBAs to = erase + and consists of the following: + An EFI_LBA that indicates the starting L= BA + A UINTN that indicates the number of blo= cks + to erase. + + The list is terminated with an + EFI_LBA_LIST_TERMINATOR. + + @retval EFI_SUCCESS The erase request successfully completed. + + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisab= led + state. + + @retval EFI_DEVICE_ERROR The block device is not functioning corr= ectly + and could not be written. + The firmware device may have been partia= lly + erased. + + @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the va= riable + argument list do not exist in the firmwa= re + volume. + +**/ +EFI_STATUS +EFIAPI +FvbEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... + ) +{ + EFI_STATUS Status; + VA_LIST Args; + UINTN BlockAddress; // Physical address of Lba to erase + EFI_LBA StartingLba; // Lba from which we start erasing + UINTN NumOfLba; // Number of Lba blocks to erase + FT_FVB_DEVICE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + Status =3D EFI_SUCCESS; + + // Detect WriteDisabled state + if (Instance->Media.ReadOnly =3D=3D TRUE) { + // Firmware volume is in WriteDisabled state + DEBUG (( + DEBUG_ERROR, + "FvbEraseBlocks: ERROR - Device is in WriteDisabled state.\n" + )); + return EFI_ACCESS_DENIED; + } + + // Before erasing, check the entire list of parameters to ensure all spe= cified blocks are valid + + VA_START (Args, This); + do { + // Get the Lba from which we start erasing + StartingLba =3D VA_ARG (Args, EFI_LBA); + + // Have we reached the end of the list? + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + //Exit the while loop + break; + } + + // How many Lba blocks are we requested to erase? + NumOfLba =3D VA_ARG (Args, UINT32); + + // All blocks must be within range + if ((NumOfLba =3D=3D 0) || ((Instance->StartLba + StartingLba + NumOfL= ba - 1) > Instance->Media.LastBlock)) { + VA_END (Args); + DEBUG (( + DEBUG_ERROR, + "FvbEraseBlocks: ERROR - Lba range goes past the last Lba.\n" + )); + Status =3D EFI_INVALID_PARAMETER; + goto EXIT; + } + } while (TRUE); + + VA_END (Args); + + // + // To get here, all must be ok, so start erasing + // + VA_START (Args, This); + do { + // Get the Lba from which we start erasing + StartingLba =3D VA_ARG (Args, EFI_LBA); + + // Have we reached the end of the list? + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + // Exit the while loop + break; + } + + // How many Lba blocks are we requested to erase? + NumOfLba =3D VA_ARG (Args, UINT32); + + // Go through each one and erase it + while (NumOfLba > 0) { + // Get the physical address of Lba to erase + BlockAddress =3D GET_DATA_OFFSET ( + Instance->RegionBaseAddress, + Instance->StartLba + StartingLba, + Instance->Media.BlockSize + ); + + // Erase it + Status =3D FvbFlashEraseSingleBlock (Instance, BlockAddress); + if (EFI_ERROR (Status)) { + VA_END (Args); + Status =3D EFI_DEVICE_ERROR; + goto EXIT; + } + + // Move to the next Lba + StartingLba++; + NumOfLba--; + } + } while (TRUE); + + VA_END (Args); + +EXIT: + return Status; +} + + +/** + This function inited the NorFlash instance. + + @param[in][out] FlashInstance The pointer of FT_FVB_DEVICE instance. + + @retval EFI_SUCCESS PhytNorFlashFvbInitialize() is executed = successfully. + +**/ +STATIC +EFI_STATUS +PhytNorFlashFvbInitialize ( + IN OUT FT_FVB_DEVICE *FlashInstance + ) +{ + EFI_STATUS Status; + UINT32 FvbNumLba; + EFI_BOOT_MODE BootMode; + UINTN TotalFvbSize; + + // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + mFlashNvStorageVariableBase, + FlashInstance->FvbSize, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gDS->SetMemorySpaceAttributes ( + mFlashNvStorageVariableBase, + FlashInstance->FvbSize, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME + ); + ASSERT_EFI_ERROR (Status); + + TotalFvbSize =3D FlashInstance->FvbSize; + + // Set the index of the first LBA for the FVB + FlashInstance->StartLba =3D (mFlashNvStorageVariableBase - FlashInstance= ->RegionBaseAddress) / FlashInstance->Media.BlockSize; + + BootMode =3D GetBootModeHob (); + if (BootMode =3D=3D BOOT_WITH_DEFAULT_SETTINGS) { + Status =3D EFI_INVALID_PARAMETER; + } else { + // Determine if there is a valid header at the beginning of the NorFla= sh + Status =3D FvbValidateFvHeader (FlashInstance); + } + + // Install the Default FVB header if required + if (EFI_ERROR (Status)) { + // There is no valid header, so time to install one. + DEBUG (( + DEBUG_ERROR, + "NorFlashFvbInitialize: ERROR - The FVB Header is invalid. Installin= g a correct one for this volume.\n" + )); + + // Erase all the NorFlash that is reserved for variable storage + FvbNumLba =3D TotalFvbSize / FlashInstance->Media.BlockSize; + + Status =3D FvbEraseBlocks ( + &FlashInstance->FvbProtocol, + (EFI_LBA)0, + FvbNumLba, + EFI_LBA_LIST_TERMINATOR + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // Install all appropriate headers + Status =3D FvbInitFvAndVariableStoreHeaders (FlashInstance); + if (EFI_ERROR (Status)) { + return Status; + } + } + + return Status; +} + + +/** + The CreateInstance() function Create Fvb Instance. + + @retval EFI_SUCCESS Create Instance successfully. + + @retval other Create Instance failed. + +**/ +STATIC +EFI_STATUS +CreateInstance ( + VOID + ) +{ + EFI_STATUS Status; + NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevice; + + // Locate flash protocols + Status =3D gBS->LocateProtocol (&gSpiNorFlashProtocolGuid, + NULL, + (VOID **)&FvbDevice->SpiFlashProtocol); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Cannot locate NorFlash protocol.\n" + )); + return Status; + } + + NorFlashDevice =3D AllocateRuntimePool (sizeof (NOR_FLASH_DEVICE_DESCRIP= TION)); + if (NorFlashDevice =3D=3D NULL) { + DEBUG (( + DEBUG_ERROR, + "Cannot Allocate NorFlashDevice Pool.\n" + )); + return Status; + } + + Status =3D FvbDevice->SpiFlashProtocol->GetDevices (NorFlashDevice); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D FvbDevice->SpiFlashProtocol->Initialization (); + if (EFI_ERROR (Status)) { + return Status; + } + + FvbDevice->DeviceBaseAddress =3D NorFlashDevice->DeviceBaseAddress; + FvbDevice->RegionBaseAddress =3D NorFlashDevice->RegionBaseAddress; + FvbDevice->Size =3D NorFlashDevice->Size; + + FvbDevice->Media.MediaId =3D 0; + FvbDevice->Media.BlockSize =3D NorFlashDevice->BlockSize; + FvbDevice->Media.LastBlock =3D (FvbDevice->Size / FvbDevice->Media.Block= Size) - 1; + FvbDevice->FvbSize =3D mFlashNvStorageVariableSize + + mFlashNvStorageFtwWorkingSize + + mFlashNvStorageFtwSpareSize; + + CopyGuid (&FvbDevice->DevicePath.Vendor.Guid, &NorFlashDevice->Guid); + + FvbDevice->ShadowBuffer =3D AllocateRuntimePool (FvbDevice->Media.BlockS= ize); + if (FvbDevice->ShadowBuffer =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &FvbDevice->Handle, + &gEfiDevicePathProtocolGuid, + &FvbDevice->DevicePath, + &gEfiFirmwareVolumeBlockProtocolGuid, + &FvbDevice->FvbProtocol, + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (FvbDevice); + return Status; + } + + Status =3D PhytNorFlashFvbInitialize (FvbDevice); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "PhytNorFlashFvbInitialize: Fail to init NorFlash devices\n" + )); + return Status; + } + + FreePool (NorFlashDevice); + + return Status; +} + + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers + in lib to virtual mode. + + @param[in] Event The Event that is being processed. + + @param[in] Context Event Context. + + @retval None. + +**/ +STATIC +VOID +EFIAPI +FvbVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // Convert SpiFlashProtocol + EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Erase); + EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Write); + EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Read); + EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->GetDevice= s); + EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Initializ= ation); + EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->EraseSing= leBlock); + EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol); + + EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageVariableBase); + EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageFtwWorkingBase); + EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageFtwSpareBase); + EfiConvertPointer (0x0, (VOID **)&FvbDevice); + + return; +} + + +/** + This function is the entrypoint of the fvb driver. + + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. + + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + + @retval other Some error occurs when executing this entry po= int. + +**/ +EFI_STATUS +EFIAPI +FvbEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + FvbDevice =3D AllocateRuntimeCopyPool ( + sizeof (FvbFlashInstanceTemplate), + &FvbFlashInstanceTemplate + ); + if (FvbDevice =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + mFlashNvStorageVariableBase =3D FixedPcdGet64 (PcdFlashNvStorageVariab= leBase64); + mFlashNvStorageFtwWorkingBase =3D FixedPcdGet64 (PcdFlashNvStorageFtwWor= kingBase64); + mFlashNvStorageFtwSpareBase =3D FixedPcdGet64 (PcdFlashNvStorageFtwSpa= reBase64); + mFlashNvStorageVariableSize =3D FixedPcdGet32 (PcdFlashNvStorageVariab= leSize); + mFlashNvStorageFtwWorkingSize =3D FixedPcdGet32 (PcdFlashNvStorageFtwWor= kingSize); + mFlashNvStorageFtwSpareSize =3D FixedPcdGet32 (PcdFlashNvStorageFtwSpa= reSize); + + Status =3D CreateInstance (); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "CreateInstance: Fail to create instance for NorFlash\n" + )); + } + +// +// Register for the virtual address change event +// + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + FvbVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &FvbVirtualAddrChangeEvent + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72986): https://edk2.groups.io/g/devel/message/72986 Mute This Topic: https://groups.io/mt/81410918/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 10:07:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72988+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72988+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1616006562; cv=none; d=zohomail.com; s=zohoarc; b=SKTXjv7fPP2YyNTuaxlo/GsbLT5Q/y+X7vDAAbn5hvLBSl/3pB+KZsvDw9L7ugz2xwRZYBIrvDxXJqVPBKabrzoA1KcicrI3Svfa3PsWRRLAjAqEy2H1ahC1R2NGNyMV6I0Vw764eUPDdavYLbaSpzjZY6U2QcTtqSgEpNw2brs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616006562; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=eWTHafk+YtC7Qx/cxFleZZRsQ3BT4olxNbpJF5ZgHWI=; b=FxHyFV/Cc1h+2YoRfifJYTGREamIv5+ezDhYIsOB32zYnoPhZm7JpCdOi79McS7MP7oo5WFXVbqoM/gVjUsYgRcUh0O20DlVLMIER1cKDLFfSr0DoW+mUS63CMDxfFyaxDKAU4cf/rRutf2TmhdHeUNTBx4k89ENEKnz2ZG1qSU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72988+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1616006561814111.14781242798597; Wed, 17 Mar 2021 11:42:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id esH9YY1788612xN2Oed672B1; Wed, 17 Mar 2021 11:42:41 -0700 X-Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by mx.groups.io with SMTP id smtpd.web09.3187.1615966025468148033 for ; Wed, 17 Mar 2021 00:27:05 -0700 X-Received: from localhost.localdomain (unknown [223.153.147.73]) by c1app7 (Coremail) with SMTP id BwINCgB3HOE4r1FgGIYZAA--.29335S11; Wed, 17 Mar 2021 15:27:01 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [edk2-devel] [PATCH v3 09/10] Silicon/Phytium: Added Rtc driver to FT2000/4 Date: Wed, 17 Mar 2021 15:26:46 +0800 Message-Id: <20210317072647.77340-10-jialing@phytium.com.cn> In-Reply-To: <20210317072647.77340-1-jialing@phytium.com.cn> References: <20210317072647.77340-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BwINCgB3HOE4r1FgGIYZAA--.29335S11 X-Coremail-Antispam: 1UD129KBjvAXoWfGF1UuFy3XFWkZF4xZw4UXFb_yoW8AF45Xo WfGrWIq3y8Jr1rua4Syw1kAFW2grZagan0qr4jvFZ7K3ZrZr1ayFyUt3W2qry3tr9rAw43 KrWfJ3s7AFWaqFs7n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYM7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r 4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl 6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6x IIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_ Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFwVW8Cw CF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j 6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64 vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_ Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0x vEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUvg4hUUUUU= X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: tiEfLJUte8JeSztibmsXRd7tx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616006561; bh=ol1p4Mio8wcK6vQ+T/dKnuQ+vt6F7yBlIe5jHLWMemE=; h=Cc:Date:From:Reply-To:Subject:To; b=vgBc+BidjiUcZcvuS/dmUICCky674fX5E3nuamcCR8WJVEDTlW2FYH1BdrkSW4jU6o5 jajM6V9xN18sFtBLpGgGfM/FbHIrI9xDDUuHfjRTbt+KVO2jZUePmS9QDcexpcnx8c0x/ Hu/45dXSaSX0aqNe2NQ/W8tz8nHEdtSy1fA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The RealTimeClockLib implemented EFI RealTimeClock runtime services via RTC Lib. v3: Optimized the codes to conform to specifications. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec = | 1 + Platform/Phytium/DurianPkg/DurianPkg.dsc = | 6 + Platform/Phytium/DurianPkg/DurianPkg.fdf = | 2 + Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.inf = | 39 ++ Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.h = | 24 + Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.c = | 462 ++++++++++++++++++++ 6 files changed, 534 insertions(+) diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silico= n/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec index 2686ba3cc3..4c6c5c5f11 100644 --- a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec +++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec @@ -45,6 +45,7 @@ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x0|UINT64|0x00000005 gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x0|UINT64|0x00000006 gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x0|UINT64|0x00000007 + gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT32|0x00000008 =20 [Protocols] gSpiMasterProtocolGuid =3D { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0= x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}} diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index 99034365d3..9579f8e9b7 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -29,6 +29,10 @@ # Phytium Platform library ArmPlatformLib|Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformL= ib.inf =20 + #FT2000-4Pkg RTC Driver + RealTimeClockLib|Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/Re= alTimeClockLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + # PL011 UART Driver and Dependency Libraries SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortL= ib.inf PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartCloc= kLib.inf @@ -168,6 +172,8 @@ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf } MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf =20 # # Common Arm Timer and Gic Components diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf index 67458458dd..242f647ca1 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -93,6 +93,8 @@ READ_LOCK_STATUS =3D TRUE # INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf =20 INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeC= lockLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTime= ClockLib.inf new file mode 100644 index 0000000000..09a06d53ae --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib= .inf @@ -0,0 +1,39 @@ +#/** @file +# Phytium RealTime Clock Library file. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RealTimeClockLib + FILE_GUID =3D fb320c94-40fe-11eb-b990-171865af292c + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RealTimeClockLib + +[Sources.common] + RealTimeClockLib.c + RealTimeClockLib.h + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + DebugLib + DxeServicesTableLib + IoLib + TimeBaseLib + UefiRuntimeLib + +[Guids] + gEfiEventVirtualAddressChangeGuid + +[Pcd] + gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeC= lockLib.h b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeCl= ockLib.h new file mode 100644 index 0000000000..41ce002dc3 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib= .h @@ -0,0 +1,24 @@ +/** @file + Phytium RealTime Clock Header. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef REAL_TIME_CLOCK_H_ +#define REAL_TIME_CLOCK_H_ + +#define RTC_CMR 0x4 +#define RTC_AES_SEL 0x8 +#define RTC_CCR 0xC +#define RTC_STAT 0x10 +#define RTC_RSTAT 0x14 +#define RTC_EOI 0x18 +#define RTC_CDR_LOW 0x20 +#define RTC_CCVR 0x24 +#define RTC_CLR_LOW 0x28 +#define RTC_CLR 0x2C + +#endif // REAL_TIME_CLOCK_H_ diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeC= lockLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeCl= ockLib.c new file mode 100644 index 0000000000..bf3047fb67 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib= .c @@ -0,0 +1,462 @@ +/** @file + Implement EFI RealTimeClock runtime services via RTC Lib. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include "RealTimeClockLib.h" + +STATIC EFI_EVENT mRtcVirtualAddrChangeEvent; +STATIC UINTN mRtcBase; +STATIC CONST CHAR16 mTimeZoneVariableName[] =3D L"RtcTimeZone"; +STATIC CONST CHAR16 mDaylightVariableName[] =3D L"RtcDaylight"; + +/** + Returns the current time and date information, and the time-keeping capa= bilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapsho= t of the current time. + @param Capabilities An optional pointer to a buffer to receiv= e the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to ha= rdware error. + @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an= authentication failure. + +**/ +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + UINT32 EpochSeconds; + INT16 TimeZone; + UINT8 Daylight; + UINTN Size; + EFI_STATUS Status; + + // Ensure Time is a valid pointer + if (Time =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + MmioWrite32 (mRtcBase + RTC_AES_SEL, 0x100); + // + //read cdr high 32bit + // + EpochSeconds =3D MmioRead32 (mRtcBase + RTC_CCVR); + MmioRead32 (mRtcBase + RTC_CDR_LOW); + // + // Get the current time zone information from non-volatile storage + // + Size =3D sizeof (TimeZone); + Status =3D EfiGetVariable ( + (CHAR16 *)mTimeZoneVariableName, + &gEfiCallerIdGuid, + NULL, + &Size, + (VOID *)&TimeZone + ); + + if (EFI_ERROR (Status)) { + ASSERT (Status !=3D EFI_INVALID_PARAMETER); + ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL); + // + // The time zone variable does not exist in non-volatile storage, so c= reate it. + //UTC+8:00 + // + Time->TimeZone =3D -480; + // + // Store it + // + Status =3D EfiSetVariable ( + (CHAR16 *)mTimeZoneVariableName, + &gEfiCallerIdGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_= VARIABLE_RUNTIME_ACCESS, + Size, + (VOID *)&(Time->TimeZone) + ); + if (EFI_ERROR (Status)) { + return Status; + } + } else { + // + // Got the time zone + // + Time->TimeZone =3D TimeZone; + // + // Check TimeZone bounds: -1440 to 1440 or 2047 + // + if (((Time->TimeZone < -1440) || (Time->TimeZone > 1440)) + && (Time->TimeZone !=3D EFI_UNSPECIFIED_TIMEZONE)) { + Time->TimeZone =3D EFI_UNSPECIFIED_TIMEZONE; + } + // + // Adjust for the correct time zone + // + if (Time->TimeZone !=3D EFI_UNSPECIFIED_TIMEZONE) { + EpochSeconds -=3D Time->TimeZone * SEC_PER_MIN; + } + } + // + // Get the current daylight information from non-volatile storage + // + Size =3D sizeof (Daylight); + Status =3D EfiGetVariable ( + (CHAR16 *)mDaylightVariableName, + &gEfiCallerIdGuid, + NULL, + &Size, + (VOID *)&Daylight + ); + + if (EFI_ERROR (Status)) { + ASSERT (Status !=3D EFI_INVALID_PARAMETER); + ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL); + // + // The daylight variable does not exist in non-volatile storage, so cr= eate it. + // + Time->Daylight =3D 0; + // + // Store it + // + Status =3D EfiSetVariable ( + (CHAR16 *)mDaylightVariableName, + &gEfiCallerIdGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_= VARIABLE_RUNTIME_ACCESS, + Size, + (VOID *)&(Time->Daylight) + ); + + if (EFI_ERROR (Status)) { + return Status; + } + } else { + // + // Got the daylight information + // + Time->Daylight =3D Daylight; + // + // Adjust for the correct period + // + if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) =3D=3D EFI_TIME_IN_DAYLIGH= T) { + // + // Convert to adjusted time, i.e. spring forwards one hour + // + EpochSeconds +=3D SEC_PER_HOUR; + } + } + + // + // Convert from internal 32-bit time to UEFI time + // + EpochToEfiTime (EpochSeconds, Time); + + return EFI_SUCCESS; +} + + +/** + Sets the current local time and date information. + + @param[in] Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardw= are error. + +**/ +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ) +{ + UINTN EpochSeconds; + EFI_STATUS Status; + // + // the maximum time span is just over 136 years. + // Time is stored in Unix Epoch format, so it starts in 1970, + // Therefore it can not exceed the year 2106. + // + if ((Time->Year < 1970) || (Time->Year >=3D 2106)) { + return EFI_UNSUPPORTED; + } + EpochSeconds =3D EfiTimeToEpoch (Time); + // + // Adjust for the correct time zone, i.e. convert to UTC time zone + // + if (Time->TimeZone !=3D EFI_UNSPECIFIED_TIMEZONE) { + EpochSeconds +=3D Time->TimeZone * SEC_PER_MIN; + } + // + // Adjust for the correct period + // + if (((Time->Daylight & EFI_TIME_IN_DAYLIGHT) =3D=3D EFI_TIME_IN_DAYLIGHT) + && (EpochSeconds > SEC_PER_HOUR)) { + // + // Convert to un-adjusted time, i.e. fall back one hour + // + EpochSeconds -=3D SEC_PER_HOUR; + } + // + // Set the Rtc + // + MmioWrite32 (mRtcBase + RTC_AES_SEL, 0x100); + MmioWrite32 (mRtcBase + RTC_CLR_LOW, 0x0); + MmioWrite32 (mRtcBase + RTC_CLR, (UINT32)EpochSeconds); + // + // Save the current time zone information into non-volatile storage + // + Status =3D EfiSetVariable ( + (CHAR16 *)mTimeZoneVariableName, + &gEfiCallerIdGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA= RIABLE_RUNTIME_ACCESS, + sizeof (Time->TimeZone), + (VOID *)&(Time->TimeZone) + ); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Save the current daylight information into non-volatile storage + // + Status =3D EfiSetVariable ( + (CHAR16 *)mDaylightVariableName, + &gEfiCallerIdGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA= RIABLE_RUNTIME_ACCESS, + sizeof (Time->Daylight), + (VOID *)&(Time->Daylight) + ); + if (EFI_ERROR (Status)) { + return Status; + } + return EFI_SUCCESS; +} + + +/** + Returns the current wakeup alarm clock setting. + + @param[out] Enabled Indicates if the alarm is currently e= nabled or disabled. + @param[out] Pending Indicates if the alarm signal is pend= ing and requires acknowledgement. + @param[out] Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieve= d due to a hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + // Not a required feature + return EFI_UNSUPPORTED; +} + + +/** + Sets the system wakeup alarm clock time. + + @param[in] Enabled Enable or disable the wakeup alarm. + @param[out] Time If Enable is TRUE, the time to set th= e wakeup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup al= arm was enabled. If + Enable is FALSE, then the wakeup alar= m was disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due = to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on th= is platform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + // Not a required feature + return EFI_UNSUPPORTED; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context + +**/ +VOID +EFIAPI +LibRtcVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // + // Only needed if you are going to support the OS calling RTC functions = in virtual mode. + // You will need to call EfiConvertPointer (). To convert any stored phy= sical addresses + // to virtual address. After the OS transitions to calling in virtual mo= de, all future + // runtime calls will be made in virtual mode. + // + EfiConvertPointer (0x0, (VOID **)&mRtcBase); + + return; +} + +/** + This is the declaration of an EFI image entry point. This can be the ent= ry point to an application + written to this specification, an EFI boot service driver, or an EFI run= time driver. + + @param[in] ImageHandle Handle that identifies the loaded imag= e. + @param[in] SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + INT16 TimeZone; + UINTN Size; + EFI_TIME Time; + UINT8 Daylight; + // + // Initialize RTC Base Address + // + mRtcBase =3D PcdGet32 (PcdRtcBaseAddress); + // + // Declare the controller as EFI_MEMORY_RUNTIME + // + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + mRtcBase, + SIZE_4KB, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME + ); + if (EFI_ERROR (Status)) { + return Status; + } + // + //init timezone + // + Size =3D sizeof (TimeZone); + Status =3D EfiGetVariable ( + (CHAR16 *)mTimeZoneVariableName, + &gEfiCallerIdGuid, + NULL, + &Size, + (VOID *)&TimeZone + ); + if (EFI_ERROR (Status)) { + ASSERT (Status !=3D EFI_INVALID_PARAMETER); + ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL); + // + // The time zone variable does not exist in non-volatile storage, so c= reate it. + //UTC 8:00 + // + Time.TimeZone =3D -480; + // + // Store it + // + Status =3D EfiSetVariable ( + (CHAR16 *)mTimeZoneVariableName, + &gEfiCallerIdGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA= RIABLE_RUNTIME_ACCESS, + Size, + (VOID *)&(Time.TimeZone) + ); + if (EFI_ERROR (Status)) { + return Status; + } + } + // + //daylight init + // + Size =3D sizeof (Daylight); + Status =3D EfiGetVariable ( + (CHAR16 *)mDaylightVariableName, + &gEfiCallerIdGuid, + NULL, + &Size, + (VOID *)&Daylight + ); + if (EFI_ERROR (Status)) { + ASSERT (Status !=3D EFI_INVALID_PARAMETER); + ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL); + // + // The daylight variable does not exist in non-volatile storage, so cr= eate it. + // + Time.Daylight =3D 0; + // + // Store it + // + Status =3D EfiSetVariable ( + (CHAR16 *)mDaylightVariableName, + &gEfiCallerIdGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA= RIABLE_RUNTIME_ACCESS, + Size, + (VOID *)&(Time.Daylight) + ); + if (EFI_ERROR (Status)) { + return Status; + } + } + + Status =3D gDS->SetMemorySpaceAttributes (mRtcBase, SIZE_4KB, EFI_MEMORY= _UC | EFI_MEMORY_RUNTIME); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Install the protocol + // + Handle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiRealTimeClockArchProtocolGuid, + NULL, + NULL + ); + ASSERT_EFI_ERROR (Status); + // + // Register for the virtual address change event + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + LibRtcVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mRtcVirtualAddrChangeEvent + ); + ASSERT_EFI_ERROR (Status); + return Status; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Wed, 17 Mar 2021 00:27:04 -0700 X-Received: from localhost.localdomain (unknown [223.153.147.73]) by c1app7 (Coremail) with SMTP id BwINCgB3HOE4r1FgGIYZAA--.29335S12; Wed, 17 Mar 2021 15:27:01 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [edk2-devel] [PATCH v3 10/10] Maintainers.txt: Added maintainers and reviewers for the DurianPkg Date: Wed, 17 Mar 2021 15:26:47 +0800 Message-Id: <20210317072647.77340-11-jialing@phytium.com.cn> In-Reply-To: <20210317072647.77340-1-jialing@phytium.com.cn> References: <20210317072647.77340-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BwINCgB3HOE4r1FgGIYZAA--.29335S12 X-Coremail-Antispam: 1UD129KBjvdXoW7Gr1xAryDWw1UAw13tryfCrg_yoW3GrX_GF 45tasY9r1YvF12kw4IqFnxWryfJrW0qw18JF10y345Xa4DAw1jgFnrtF97A3W5GF17C3y8 t3s3XrW5KrZxCjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbhAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAVCq3wA2048vs2 IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28E F7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr 1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_GF4l42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1Y6r17MIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUY3kuDUUUU X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: Nsu13GLEWBAsO3AXf1Z03ucUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1616006561; bh=OXxO/nELoGgb6Qnj++SRMXi5d2DAUXzhxzWb4tb3Avw=; h=Cc:Date:From:Reply-To:Subject:To; b=uQ7x/m1YyYAaKcrOWfDZlSmUPC7yC9n5P/OYPo+0cY5RB5fCaQJPGFaU9V7PFf1k8DE k+1dbgQAslaSw+52pXRWYp8QquvsjBPpjo8iaTu4cOnUV519agp6PpLI9PSCRK8GFg9aN 34DlP4y1MqQvACVFM4po2U0KDrzyceJfudo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Maintainers.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index afbd2cff0e..b6cfe74e09 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -321,3 +321,11 @@ F: Silicon/SiFive/ M: Abner Chang M: Gilbert Chen R: Daniel Schaefer + +Phytium platforms and silicon +F: Platform/Phytium/ +F: Silicon/silicon/ +M: Leif Lindholm +R: Peng Xie +R: Ling Jia +R: Yiqi Shu --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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