From nobody Mon Feb 9 07:23:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72782+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72782+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1615780821; cv=none; d=zohomail.com; s=zohoarc; b=fi++7XwWnNA/5Hlods6lQ58qoKAAM0JfBoYdpb9bYL1oLmoQv158tZ4eeo/lF4j8FoZ/Psc8L3Z/bZ3tDv3l6w6fAbZxzzXGkqaxwxMoWG8Rynqc2YB8Ao1LaV/G4vrYVKMJ30IwYrNFQuaYBBDYV5FoyHHxU09YHAtmW+YIJHI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615780821; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=gV2HxGour4QtIJO+ovWyVQQsuMk3a23IZ2gZA+x2wxA=; b=d4WJd0/5yI7g/fa8C51IwQk1kfruv2+fGEN/yNxYSlZNuDtaV2uYCu9lOYd4Cx74dXsd9LRlUi5JwH0At+0dPAwcjFrPNEhgnx2AjJtPKYAdbEP8SB5EpUMb0tEqUN4uS17KU2SdV989M/NkqDrlTJ4LH6zDOEm00d9XjWp94jg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72782+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161578082125352.14086844583778; Sun, 14 Mar 2021 21:00:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id neORYY1788612xbILJpRlFTi; Sun, 14 Mar 2021 21:00:20 -0700 X-Received: from mga01.intel.com (mga01.intel.com []) by mx.groups.io with SMTP id smtpd.web11.4353.1615780814589881695 for ; Sun, 14 Mar 2021 21:00:15 -0700 IronPort-SDR: f859f8tV44eVawXPfW77eUkNiVYe54ri3VNa+nbxI1kza7ICQnevT5QxROIhppwFw5J7/82dzA Yglpi/8WGkkw== X-IronPort-AV: E=McAfee;i="6000,8403,9923"; a="208926864" X-IronPort-AV: E=Sophos;i="5.81,249,1610438400"; d="scan'208";a="208926864" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2021 20:59:57 -0700 IronPort-SDR: I6t9Layk13JqVScqbbl1xfYMnOFPZmZ5CusM4iFyWQyu47PN+dTh1082jdUD/v3qR4ipx+LCKJ gxkjGZ8hphYA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,249,1610438400"; d="scan'208";a="373298226" X-Received: from shwdeopenpsi114.ccr.corp.intel.com ([10.239.154.141]) by orsmga006.jf.intel.com with ESMTP; 14 Mar 2021 20:59:56 -0700 From: "Dandan Bi" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [edk2-devel] [patch 28/28] MdePkg/Baseib: Filter/trace MSR access for IA32/X64 Date: Mon, 15 Mar 2021 11:58:44 +0800 Message-Id: <20210315035844.32756-29-dandan.bi@intel.com> In-Reply-To: <20210315035844.32756-1-dandan.bi@intel.com> References: <20210315035844.32756-1-dandan.bi@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dandan.bi@intel.com X-Gm-Message-State: SsdT2BKOe8NlBIeZ4dzNneHwx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1615780820; bh=Wzw0ukcY+/xFX05bBxlruJB/4/5JmoXq+zQg6vuRMmQ=; h=Cc:Date:From:Reply-To:Subject:To; b=voHThuxDPJ4Z3SBG5/8yjk+k/4YopKihfSE+K+QKcRCP/Pdu6FZOZ1aKDjHIksQQ3Cv DN1UtiJNpmt36BG3RTxsR/RvFThoorG41YEe/spZEMNub+0wgDOPuyeIKH4L2CzLyIACN WEuGzuUFjqDeTKgxveMtGMMlcOsKo1HesRQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3246 Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Dandan Bi --- MdePkg/Library/BaseLib/BaseLib.inf | 5 ++- MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c | 36 ++++++++++++------ MdePkg/Library/BaseLib/Ia32/ReadMsr64.c | 38 +++++++++++++++++-- MdePkg/Library/BaseLib/Ia32/WriteMsr64.c | 22 +++++++---- MdePkg/Library/BaseLib/X64/GccInlinePriv.c | 41 ++++++++++++++------- MdePkg/Library/BaseLib/X64/ReadMsr64.c | 15 +++++++- MdePkg/Library/BaseLib/X64/WriteMsr64.c | 13 ++++++- 7 files changed, 128 insertions(+), 42 deletions(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 3b85c56c3c..58e29cc7af 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -1,9 +1,9 @@ ## @file # Base Library implementation. # -# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -409,10 +409,13 @@ [LibraryClasses] PcdLib DebugLib BaseMemoryLib =20 +[LibraryClasses.X64, LibraryClasses.IA32] + RegisterFilterLib + [Pcd] gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength ## SOMETIMES_CO= NSUMES gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## SOMETIMES_CO= NSUMES gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength ## SOMETIMES_CO= NSUMES gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask ## SOME= TIMES_CONSUMES diff --git a/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c b/MdePkg/Library/B= aseLib/Ia32/GccInlinePriv.c index 30aa63243b..7e9cd82c94 100644 --- a/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c +++ b/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c @@ -8,10 +8,11 @@ =20 **/ =20 =20 #include "BaseLibInternals.h" +#include =20 /** Enables CPU interrupts. =20 Enables CPU interrupts. @@ -61,16 +62,21 @@ EFIAPI AsmReadMsr64 ( IN UINT32 Index ) { UINT64 Data; - - __asm__ __volatile__ ( - "rdmsr" - : "=3DA" (Data) // %0 - : "c" (Index) // %1 - ); + BOOLEAN Flag; + + Flag =3D FilterBeforeMsrRead (Index, &Data); + if (Flag) { + __asm__ __volatile__ ( + "rdmsr" + : "=3DA" (Data) // %0 + : "c" (Index) // %1 + ); + } + FilterAfterMsrRead (Index, &Data); =20 return Data; } =20 /** @@ -95,16 +101,22 @@ EFIAPI AsmWriteMsr64 ( IN UINT32 Index, IN UINT64 Value ) { - __asm__ __volatile__ ( - "wrmsr" - : - : "c" (Index), - "A" (Value) - ); + BOOLEAN Flag; + + Flag =3D FilterBeforeMsrWrite (Index, &Value); + if (Flag) { + __asm__ __volatile__ ( + "wrmsr" + : + : "c" (Index), + "A" (Value) + ); + } + FilterAfterMsrWrite (Index, &Value); =20 return Value; } =20 /** diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c b/MdePkg/Library/BaseL= ib/Ia32/ReadMsr64.c index 6d2394b1a3..afe3aa5bdc 100644 --- a/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c +++ b/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c @@ -1,15 +1,15 @@ /** @file AsmReadMsr64 function =20 - Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 =20 - +#include =20 /** Returns a 64-bit Machine Specific Register(MSR). =20 Reads and returns the 64-bit MSR specified by Index. No parameter checki= ng is @@ -22,16 +22,46 @@ =20 @return The value of the MSR identified by Index. =20 **/ UINT64 -EFIAPI -AsmReadMsr64 ( +AsmReadMsr64Internal ( IN UINT32 Index ) { _asm { mov ecx, Index rdmsr } } =20 +/** + Returns a 64-bit Machine Specific Register(MSR). + + Reads and returns the 64-bit MSR specified by Index. No parameter checki= ng is + performed on Index, and some Index values may cause CPU exceptions. The + caller must either guarantee that Index is valid, or the caller must set= up + exception handlers to catch the exceptions. This function is only availa= ble + on IA-32 and x64. + + @param Index The 32-bit MSR index to read. + + @return The value of the MSR identified by Index. + +**/ +UINT64 +EFIAPI +AsmReadMsr64 ( + IN UINT32 Index + ) +{ + UINT64 Value; + BOOLEAN Flag; + + Flag =3D FilterBeforeMsrRead (Index, &Value); + if (Flag) { + Value =3D AsmReadMsr64Internal (Index); + } + FilterAfterMsrRead (Index, &Value); + + return Value; +} diff --git a/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c b/MdePkg/Library/Base= Lib/Ia32/WriteMsr64.c index badf1d8e58..ba0cf3f74c 100644 --- a/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c +++ b/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c @@ -1,15 +1,15 @@ /** @file AsmWriteMsr64 function =20 - Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 =20 - +#include =20 /** Writes a 64-bit value to a Machine Specific Register(MSR), and returns t= he value. =20 @@ -31,13 +31,21 @@ EFIAPI AsmWriteMsr64 ( IN UINT32 Index, IN UINT64 Value ) { - _asm { - mov edx, dword ptr [Value + 4] - mov eax, dword ptr [Value + 0] - mov ecx, Index - wrmsr + BOOLEAN Flag; + + Flag =3D FilterBeforeMsrWrite (Index, &Value); + if (Flag) { + _asm { + mov edx, dword ptr [Value + 4] + mov eax, dword ptr [Value + 0] + mov ecx, Index + wrmsr + } } + FilterAfterMsrWrite (Index, &Value); + + return Value; } =20 diff --git a/MdePkg/Library/BaseLib/X64/GccInlinePriv.c b/MdePkg/Library/Ba= seLib/X64/GccInlinePriv.c index 98be19b3c7..7f92da6a0c 100644 --- a/MdePkg/Library/BaseLib/X64/GccInlinePriv.c +++ b/MdePkg/Library/BaseLib/X64/GccInlinePriv.c @@ -8,10 +8,11 @@ =20 **/ =20 =20 #include "BaseLibInternals.h" +#include =20 /** Enables CPU interrupts. =20 Enables CPU interrupts. @@ -62,17 +63,24 @@ AsmReadMsr64 ( IN UINT32 Index ) { UINT32 LowData; UINT32 HighData; - - __asm__ __volatile__ ( - "rdmsr" - : "=3Da" (LowData), // %0 - "=3Dd" (HighData) // %1 - : "c" (Index) // %2 - ); + UINT64 Value; + BOOLEAN Flag; + + Flag =3D FilterBeforeMsrRead (Index, &Value); + if (Flag) { + __asm__ __volatile__ ( + "rdmsr" + : "=3Da" (LowData), // %0 + "=3Dd" (HighData) // %1 + : "c" (Index) // %2 + ); + Value =3D (((UINT64)HighData) << 32) | LowData; + } + FilterAfterMsrRead (Index, &Value); =20 return (((UINT64)HighData) << 32) | LowData; } =20 /** @@ -99,21 +107,26 @@ AsmWriteMsr64 ( IN UINT64 Value ) { UINT32 LowData; UINT32 HighData; + BOOLEAN Flag; =20 LowData =3D (UINT32)(Value); HighData =3D (UINT32)(Value >> 32); =20 - __asm__ __volatile__ ( - "wrmsr" - : - : "c" (Index), - "a" (LowData), - "d" (HighData) - ); + Flag =3D FilterBeforeMsrWrite (Index, &Value); + if (Flag) { + __asm__ __volatile__ ( + "wrmsr" + : + : "c" (Index), + "a" (LowData), + "d" (HighData) + ); + } + FilterAfterMsrWrite (Index, &Value); =20 return Value; } =20 /** diff --git a/MdePkg/Library/BaseLib/X64/ReadMsr64.c b/MdePkg/Library/BaseLi= b/X64/ReadMsr64.c index 5ee7ca53f3..36a349432c 100644 --- a/MdePkg/Library/BaseLib/X64/ReadMsr64.c +++ b/MdePkg/Library/BaseLib/X64/ReadMsr64.c @@ -1,17 +1,19 @@ /** @file CpuBreakpoint function. =20 - Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 /** Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics. **/ =20 +#include + unsigned __int64 __readmsr (int register); =20 #pragma intrinsic(__readmsr) =20 /** @@ -26,8 +28,17 @@ UINT64 EFIAPI AsmReadMsr64 ( IN UINT32 Index ) { - return __readmsr (Index); + UINT64 Value; + BOOLEAN Flag; + + Flag =3D FilterBeforeMsrRead (Index, &Value); + if (Flag) { + Value =3D __readmsr (Index); + } + FilterAfterMsrRead (Index, &Value); + + return Value; } =20 diff --git a/MdePkg/Library/BaseLib/X64/WriteMsr64.c b/MdePkg/Library/BaseL= ib/X64/WriteMsr64.c index 98c5458d8a..bb030832c4 100644 --- a/MdePkg/Library/BaseLib/X64/WriteMsr64.c +++ b/MdePkg/Library/BaseLib/X64/WriteMsr64.c @@ -1,17 +1,19 @@ /** @file CpuBreakpoint function. =20 - Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 /** Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics. **/ =20 +#include + void __writemsr (unsigned long Register, unsigned __int64 Value); =20 #pragma intrinsic(__writemsr) =20 /** @@ -28,9 +30,16 @@ EFIAPI AsmWriteMsr64 ( IN UINT32 Index, IN UINT64 Value ) { - __writemsr (Index, Value); + BOOLEAN Flag; + + Flag =3D FilterBeforeMsrWrite (Index, &Value); + if (Flag) { + __writemsr (Index, Value); + } + FilterAfterMsrWrite (Index, &Value); + return Value; } =20 --=20 2.18.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72782): https://edk2.groups.io/g/devel/message/72782 Mute This Topic: https://groups.io/mt/81342002/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-