From nobody Tue Feb 10 01:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72818+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72818+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1615842076; cv=none; d=zohomail.com; s=zohoarc; b=FlqDFKqnk4SG7DBglSGW8u2AAXpqj/VhZ+pWsEzEJpC66cLg7XnhBQ6+VukAcxFMM0xV2EByGtsENNC4HqV+Ia1woiuqfVrYNgZbb3txEY0bXUPTTKdtX3O9AS5Thr6wZKy49sv7NqwCQb1CBriTwpqRx6hw75SOG9yD5h4RLnE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615842076; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=AGzpJQ09vaConso3VLuOLFq7x4QSarKaQLMNkx4eFt0=; b=GQ7EZvJ+MTJOBVXdR6fjWBG3xPQ6WHqjyKWL0SJteF4xSWl9C1xSwBjf72RJ+WyTB5jjpYep3qjgvL8p96meRYE1BVHyq2pPStOjrq4TiyTmJzNd0sFWHH7Wqt6YX+CRTkTti2wvDlhwDG7fMucNawNbtfXNlZjLDyycmTdv9fQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72818+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1615842076926203.63063666233927; Mon, 15 Mar 2021 14:01:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id XVeOYY1788612xsR7krbnhC1; Mon, 15 Mar 2021 14:01:16 -0700 X-Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by mx.groups.io with SMTP id smtpd.web10.6607.1615546925977606473 for ; Fri, 12 Mar 2021 03:02:06 -0800 X-Received: from localhost.localdomain (unknown [223.104.131.160]) by c1app4 (Coremail) with SMTP id BAINCgC3mwEVSktgMY01BQ--.34795S10; Fri, 12 Mar 2021 19:02:03 +0800 (CST) From: Ling Jia To: devel@edk2.groups.io Cc: Leif Lindholm , Peng Xie , Yiqi Shu , Ling Jia Subject: [edk2-devel] [PATCH v3 20/46] Silicon/Phytium: Added flash driver support to Phytium Silicon Date: Fri, 12 Mar 2021 19:01:28 +0800 Message-Id: <20210312110141.75749-9-jialing@phytium.com.cn> In-Reply-To: <20210312110141.75749-1-jialing@phytium.com.cn> References: <20210312110141.75749-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BAINCgC3mwEVSktgMY01BQ--.34795S10 X-Coremail-Antispam: 1UD129KBjvAXoW3CF15XrW5Zw4kWryUWF1xZrb_yoW8CF1DJo Wxuw4SkrZ7KrWIvayjgr9rCw4xXFnavan3tr40yr9xXan7Xw43WFWIy3WUJrsxtw18K3Zx GryxXas8JF43Xa1kn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUY_7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r 4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl 6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6x IIjxv20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_ Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFwVW8Kw CF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j 6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64 vIr41lIxAIcVC0I7IYx2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_ Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42 IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUOsjjDUUUU X-Originating-IP: [223.104.131.160] X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: 8FqY2SlU5CvMwCQJELzOjML0x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1615842076; bh=WSdAZ+VxxCnPrpxNw9KTfsv2WoWoAElhVOMVCaDXGS4=; h=Cc:Date:From:Reply-To:Subject:To; b=oS3vaAgmkyvSGlVszXiiD3qYIM5w2wnC+KXoNZ/SdNAL95rhZn5frrEmmBplbe3h2yu SjN+ChoBD2k0HvZx3BcOxH4POD0y7Lpmv0ZioXXY4FzrZFkjQkH8MKtnKpWRSiVRHD6LO m+8E04u3/g1vBOYkf6pazzMh8cp9hZm1SNk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The SpiNorFlashDxe provided norflash initialization, read-write, erase and other interfaces. v3: Optimized the codes to conform to specifications. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec | = 1 + Platform/Phytium/DurianPkg/DurianPkg.dsc | = 5 + Platform/Phytium/DurianPkg/DurianPkg.fdf | = 1 + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf | = 48 +++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h | = 99 +++++ Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h | = 74 ++++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c | = 424 ++++++++++++++++++++ 7 files changed, 652 insertions(+) diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silico= n/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec index 69842b89e021..2686ba3cc3a2 100644 --- a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec +++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec @@ -48,3 +48,4 @@ [PcdsFixedAtBuild.common] =20 [Protocols] gSpiMasterProtocolGuid =3D { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0= x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}} + gSpiNorFlashProtocolGuid =3D { 0x00b4af42, 0xfbd0, 0x11ea, { 0x80, 0x3a,= 0x27, 0xea, 0x5e, 0x65, 0xe3, 0xf6}} diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index 68698d613f96..1c4705144151 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -249,6 +249,11 @@ [Components.common] # Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf =20 + # + # NOR Flash driver + # + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf + # # Usb Support # diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf index 1cf1927484db..831f7a682837 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -96,6 +96,7 @@ [FV.FvMain] INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf =20 INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf + INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf =20 INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash= Dxe.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe= .inf new file mode 100644 index 000000000000..2933dc502eed --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf @@ -0,0 +1,48 @@ +#/** @file +# Phytium NorFlash Drivers. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D SpiNorFlashDxe + FILE_GUID =3D f37ef706-187c-48fd-9102-ddbf86f551be + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D NorFlashPlatformEntryPoint + +[Sources.common] + SpiNorFlashDxe.c + SpiNorFlashDxe.h + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + UefiLib + UefiBootServicesTableLib + UefiRuntimeLib + UefiDriverEntryPoint + +[FixedPcd] + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase +[Guids] + gEfiEventVirtualAddressChangeGuid + +[Protocols] + gSpiMasterProtocolGuid + gSpiNorFlashProtocolGuid + + [Depex] + TRUE diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash= Dxe.h b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h new file mode 100644 index 000000000000..55f5e8273f7f --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h @@ -0,0 +1,99 @@ +/** @file + Phytium NorFlash Drivers Header. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_NORFLASH_DXE_H_ +#define SPI_NORFLASH_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Norflash registers +// +#define REG_FLASH_CAP 0x000 +#define REG_RD_CFG 0x004 +#define REG_WR_CFG 0x008 +#define REG_FLUSH_REG 0x00C +#define REG_CMD_PORT 0x010 +#define REG_ADDR_PORT 0x014 +#define REG_HD_PORT 0x018 +#define REG_LD_PORT 0x01C +#define REG_CS_CFG 0x020 +#define REG_WIP_CFG 0x024 +#define REG_WP_REG 0x028 + +#define NORFLASH_SIGNATURE SIGNATURE_32 ('F', 'T', 'S', 'F') + +extern EFI_GUID gSpiMasterProtocolGuid; +extern EFI_GUID gSpiNorFlashProtocolGuid; + +// +// Platform Nor Flash Functions +// +EFI_STATUS +EFIAPI +NorFlashPlatformEraseSingleBlock ( + IN UINTN BlockAddress + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformErase ( + IN UINT64 Offset, + IN UINT64 Length + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformRead ( + IN UINTN Address, + IN VOID *Buffer, + OUT UINT32 Len + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformWrite ( + IN UINTN Address, + IN VOID *Buffer, + IN UINT32 Len + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformGetDevices ( + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformInitialization ( + VOID + ); + +EFI_STATUS +EFIAPI +NorFlashPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +typedef struct { + EFI_NORFLASH_DRV_PROTOCOL FlashProtocol; + UINTN Signature; + EFI_HANDLE Handle; +} NorFlash_Device; + +#endif // SPI_NORFLASH_DXE_H_ diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashP= rotocol.h b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashPr= otocol.h new file mode 100644 index 000000000000..b3ae26c5d44f --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol= .h @@ -0,0 +1,74 @@ +/** @file + The Header of Protocol For NorFlash. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_NORFALSH_H_ +#define SPI_NORFALSH_H_ + +typedef struct _EFI_NORFLASH_DRV_PROTOCOL EFI_NORFLASH_DRV_PROTOCOL; +extern EFI_GUID gSpiNorFlashProtocolGuid; + +typedef struct { + UINTN DeviceBaseAddress; // Start address of the Device Base Ad= dress (DBA) + UINTN RegionBaseAddress; // Start address of one single region + UINTN Size; + UINTN BlockSize; + EFI_GUID Guid; +} NOR_FLASH_DEVICE_DESCRIPTION; + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_ERASE_INTERFACE) ( + IN UINT64 Offset, + IN UINT64 Length + ); + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE) ( + IN UINTN BlockAddress + ); + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_READ_INTERFACE) ( + IN UINTN Address, + IN VOID *Buffer, + OUT UINT32 Len + ); + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_WRITE_INTERFACE) ( + IN UINTN Address, + IN VOID *Buffer, + IN UINT32 Len + ); + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_GETDEVICE_INTERFACE) ( + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices + ); + +typedef +EFI_STATUS +(EFIAPI *NORFLASH_PLATFORM_INIT_INTERFACE) ( + VOID + ); + +struct _EFI_NORFLASH_DRV_PROTOCOL{ + NORFLASH_PLATFORM_INIT_INTERFACE Initialization; + NORFLASH_PLATFORM_GETDEVICE_INTERFACE GetDevices; + NORFLASH_PLATFORM_ERASE_INTERFACE Erase; + NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE EraseSingleBlock; + NORFLASH_PLATFORM_READ_INTERFACE Read; + NORFLASH_PLATFORM_WRITE_INTERFACE Write; +}; + +#endif // SPI_NORFALSH_H_ diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash= Dxe.c b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c new file mode 100644 index 000000000000..1c339c447858 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c @@ -0,0 +1,424 @@ +/** @file + Phytium NorFlash Drivers. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SpiNorFlashDxe.h" + +typedef struct { + UINT32 Flash_Index; + UINT32 Flash_Write; + UINT32 Flash_Erase; + UINT32 Flash_Pp; +} FLASH_CMD_INFO; + +STATIC EFI_EVENT mSpiNorFlashVirtualAddrChangeEvent; +STATIC UINTN mNorFlashControlBase; +STATIC UINT8 mCmdWrite; +STATIC UINT8 mCmdEares; +STATIC UINT8 mCmdPp; + +#define SPI_FLASH_BASE FixedPcdGet64 (PcdSpiFlashBase) +#define SPI_FLASH_SIZE FixedPcdGet64 (PcdSpiFlashSize) + +EFI_SPI_DRV_PROTOCOL *mSpiMasterProtocol; +NorFlash_Device *mFlashInstance; + +NOR_FLASH_DEVICE_DESCRIPTION mNorFlashDevices =3D { + SPI_FLASH_BASE, /* Device Base Address */ + SPI_FLASH_BASE, /* Region Base Address */ + SIZE_1MB * 16, /* Size */ + SIZE_64KB, /* Block Size */ + {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5= E, 0x59 } } +}; + + +/** + This function writed up to 256 bytes to flash through spi driver. + + @param[in] Address The address of the flash. + @param[in] Buffer The pointer of buffer to be writed. + @param[in] BufferSizeInBytes The bytes to be writed. + + @retval EFI_SUCCESS NorFlashWrite256() is executed successfull= y. + +**/ +STATIC +EFI_STATUS +NorFlashWrite256 ( + IN UINTN Address, + IN VOID *Buffer, + IN UINT32 BufferSizeInBytes + ) +{ + UINT32 Index; + UINT8 CmdId; + UINT32 *TempBuffer; + UINT8 WriteSize; + + TempBuffer =3D Buffer; + WriteSize =3D sizeof (UINT32); + + if (BufferSizeInBytes > 256) { + DEBUG ((DEBUG_ERROR, "The max length is 256 bytes.\n")); + return EFI_INVALID_PARAMETER; + } + + if ((BufferSizeInBytes % WriteSize) !=3D 0) { + DEBUG ((DEBUG_ERROR, "The length must four bytes aligned.\n")); + return EFI_INVALID_PARAMETER; + } + + if ((Address % WriteSize) !=3D 0) { + DEBUG ((DEBUG_ERROR, "The address must four bytes aligned.\n")); + return EFI_INVALID_PARAMETER; + } + + CmdId =3D mCmdPp; + mSpiMasterProtocol->SpiSetConfig (CmdId, 0x400000, REG_CMD_PORT); + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT); + + CmdId =3D mCmdWrite; + mSpiMasterProtocol->SpiSetConfig (CmdId, 0x000208, REG_WR_CFG); + + for (Index =3D 0; Index < (BufferSizeInBytes / WriteSize); Index++) { + MmioWrite32 ((Address + (Index * WriteSize)), TempBuffer[Index]); + } + + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_FLUSH_REG); + + mSpiMasterProtocol->SpiSetConfig (0, 0x0, REG_WR_CFG); + + return EFI_SUCCESS; +} + +/** + This function erased a sector of flash through spi driver. + + @param[in] BlockAddress The sector address to be erased. + + @retval None. + +**/ +STATIC +inline void +NorFlashPlatformEraseSector ( + IN UINTN BlockAddress + ) +{ + UINT8 CmdId; + + CmdId =3D mCmdPp; + mSpiMasterProtocol->SpiSetConfig (CmdId, 0x400000, REG_CMD_PORT); + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT); + + CmdId =3D mCmdEares; + mSpiMasterProtocol->SpiSetConfig (CmdId, 0x408000, REG_CMD_PORT); + mSpiMasterProtocol->SpiSetConfig (0, BlockAddress, REG_ADDR_PORT); + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT); + +} + + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed. + + @param[in] Context Event Context. + + @retval None. + +**/ +VOID +EFIAPI +PlatformNorFlashVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EfiConvertPointer (0x0, (VOID **)&mNorFlashControlBase); + EfiConvertPointer (0x0, (VOID **)&mSpiMasterProtocol->SpiGetConfig); + EfiConvertPointer (0x0, (VOID **)&mSpiMasterProtocol->SpiSetConfig); + EfiConvertPointer (0x0, (VOID **)&mSpiMasterProtocol); +} + + +/** + This function inited the flash platform. + + @param None. + + @retval EFI_SUCCESS NorFlashPlatformInitialization() is execut= ed successfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformInitialization ( + VOID + ) +{ + + mCmdWrite =3D 0x2; + mCmdEares =3D 0xD8; + mCmdPp =3D 0x6; + + mNorFlashControlBase =3D FixedPcdGet64 (PcdSpiControllerBase); + + return EFI_SUCCESS; +} + + +/** + This function geted the flash device information. + + @param[out] NorFlashDevices the pointer to store flash device informa= tion. + @param[out] Count the number of the flash device. + + @retval EFI_SUCCESS NorFlashPlatformGetDevices() is executed s= uccessfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformGetDevices ( + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices + ) +{ + + *NorFlashDevices =3D mNorFlashDevices; + + return EFI_SUCCESS; +} + + +/** + This function readed flash content form the specified area of flash. + + @param[in] Address The address of the flash. + @param[in] Buffer The pointer of the Buffer to be stored. + @param[out] Len The bytes readed form flash. + + @retval EFI_SUCCESS NorFlashPlatformRead() is executed succes= sfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformRead ( + IN UINTN Address, + IN VOID *Buffer, + OUT UINT32 Len + ) +{ + + DEBUG ((DEBUG_BLKIO, + "NorFlashPlatformRead: Address: 0x%lx Buffer:0x%p Len:0x%x\n", + Address, Buffer, Len + )); + + CopyMem ((VOID *)Buffer, (VOID *)Address, Len); + + return EFI_SUCCESS; +} + + +/** + This function erased one block flash content. + + @param[in] BlockAddress the BlockAddress to be erased. + + @retval EFI_SUCCESS NorFlashPlatformEraseSingleBlock() is exe= cuted successfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformEraseSingleBlock ( + IN UINTN BlockAddress + ) +{ + + NorFlashPlatformEraseSector (BlockAddress); + + return EFI_SUCCESS; +} + + +/** + This function erased the flash content of the specified area. + + @param[in] Offset the offset of the flash. + @param[in] Length length to be erased. + + @retval EFI_SUCCESS NorFlashPlatformErase() is executed succe= ssfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformErase ( + IN UINT64 Offset, + IN UINT64 Length + ) +{ + EFI_STATUS Status; + UINT64 Index; + UINT64 Count; + + Status =3D EFI_SUCCESS; + if ((Length % SIZE_64KB) =3D=3D 0) { + Count =3D Length / SIZE_64KB; + for (Index =3D 0; Index < Count; Index++) { + NorFlashPlatformEraseSingleBlock (Offset); + Offset +=3D SIZE_64KB; + } + } else { + Status =3D EFI_INVALID_PARAMETER; + } + + return Status; +} + + +/** + This function writed data to flash. + + @param[in] Address the address of the flash. + + @param[in] Buffer the pointer of the Buffer to be writed. + + @param[in] BufferSizeInBytes the bytes of the Buffer. + + @retval EFI_SUCCESS NorFlashPlatformWrite() is executed succe= ssfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformWrite ( + IN UINTN Address, + IN VOID *Buffer, + IN UINT32 BufferSizeInBytes + ) +{ + UINT32 Index; + UINT32 Remainder; + UINT32 Quotient; + EFI_STATUS Status; + UINTN TmpAddress; + + TmpAddress =3D Address; + Remainder =3D BufferSizeInBytes % 256; + Quotient =3D BufferSizeInBytes / 256; + + if (BufferSizeInBytes <=3D 256) { + Status =3D NorFlashWrite256 (TmpAddress, Buffer, BufferSizeInBytes); + } else { + for (Index =3D 0; Index < Quotient; Index++) { + Status =3D NorFlashWrite256 (TmpAddress, Buffer, 256); + TmpAddress +=3D 256; + Buffer +=3D 256; + } + + if (Remainder !=3D 0) { + Status =3D NorFlashWrite256 (TmpAddress, Buffer, Remainder); + } + } + + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + } + + return EFI_SUCCESS; + +} + + +/** + This function inited the flash driver protocol. + + @param[in] NorFlashProtocol A pointer to the norflash protocol struct. + + @retval EFI_SUCCESS NorFlashPlatformInitProtocol() is executed suc= cessfully. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformInitProtocol ( + IN EFI_NORFLASH_DRV_PROTOCOL *NorFlashProtocol + ) +{ + NorFlashProtocol->Initialization =3D NorFlashPlatformInitialization; + NorFlashProtocol->GetDevices =3D NorFlashPlatformGetDevices; + NorFlashProtocol->Erase =3D NorFlashPlatformErase; + NorFlashProtocol->EraseSingleBlock =3D NorFlashPlatformEraseSingleBlock; + NorFlashProtocol->Read =3D NorFlashPlatformRead; + NorFlashProtocol->Write =3D NorFlashPlatformWrite; + + return EFI_SUCCESS; +} + + +/** + This function is the entrypoint of the norflash driver. + + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. + + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + + @retval other Some error occurs when executing this entry po= int. + +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status =3D gBS->LocateProtocol ( + &gSpiMasterProtocolGuid, + NULL, + (VOID **)&mSpiMasterProtocol + ); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + mFlashInstance =3D AllocateRuntimeZeroPool (sizeof (NorFlash_Device)); + if (mFlashInstance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + NorFlashPlatformInitProtocol (&mFlashInstance->FlashProtocol); + + mFlashInstance->Signature =3D NORFLASH_SIGNATURE; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &(mFlashInstance->Handle), + &gSpiNorFlashProtocolGuid, + &(mFlashInstance->FlashProtocol), + NULL + ); + ASSERT_EFI_ERROR (Status); + + //Register for the virtual address change event + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + PlatformNorFlashVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mSpiNorFlashVirtualAddrChangeEvent + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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