From nobody Sun May 5 02:27:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72530+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72530+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1615180554; cv=none; d=zohomail.com; s=zohoarc; b=ZrISJZaOcCf/2lRLDHEBKYeXZB3XCaUu9wRbba74QZpaW0sRmb3jjeuKZcjRawus3ULmI41jufkEN4m8i7cjh6F4bfMFYkGvdQ73Ml0UsZWm172c1znggyrsZl2PBdnO1ZnHjPKDMbRCbQM7UZBa/vBaxV0Qf0dl2WqHE+e7+Gg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615180554; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=rAJYCdrVkG2dt79DL7YMY8Krnk0dxIWW0tF1jhJbvcI=; b=J4uuRHCz8Br+C0WZQ8LtEs2uKTJ7MDLdwQ4hNXSUcd54cCdP21iNAoEGm44bcvNXvwaGVKX2cfvx45e9icMA9ihoxiqbr7/snwvkFhM4hq242UxiUAGchUvG1pcjTkiF4Fus/d21GQ5FrOPxqdajClsI9XQMP7EeaXMLXFV3Jv8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72530+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1615180554704204.38871417963344; Sun, 7 Mar 2021 21:15:54 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id upDoYY1788612xjtEpTHSPc0; Sun, 07 Mar 2021 21:15:54 -0800 X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web08.32206.1615180553627465522 for ; Sun, 07 Mar 2021 21:15:53 -0800 IronPort-SDR: T0X8RIWVeFnOWHNMwhtl8VfVR4xpxYOoJsbGZs4d3PSr9M4QkNL2qURHmy2sNIINLzNtb7NAMY WXkpcOT3A3vA== X-IronPort-AV: E=McAfee;i="6000,8403,9916"; a="175583438" X-IronPort-AV: E=Sophos;i="5.81,231,1610438400"; d="scan'208";a="175583438" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2021 21:15:51 -0800 IronPort-SDR: qK0FyxyMlJdVXqr+9dWrEKaifq6omB7dddaFPo7XrrA0GK2FYOU6vbn6r2wKnsOXk23tUitvyw lxM5/x1Sl+IA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,231,1610438400"; d="scan'208";a="519818918" X-Received: from unknown (HELO shwdeOpenPSI114.ccr.corp.intel.com) ([10.239.154.141]) by orsmga004.jf.intel.com with ESMTP; 07 Mar 2021 21:15:49 -0800 From: "Dandan Bi" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [edk2-devel] [RFC][patch] Add a new library class RegisterFilterLib in edk2 to filter/trace port IO/MMIO/MSR access Date: Mon, 8 Mar 2021 13:15:32 +0800 Message-Id: <20210308051532.13872-1-dandan.bi@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dandan.bi@intel.com X-Gm-Message-State: RkSbaCXAqMG0JeJHrTRLbRwWx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1615180554; bh=MDkSE9h7nnPzABPZNPFZ3p3uKKu0XwAsTLarkyYj4Uo=; h=Cc:Date:From:Reply-To:Subject:To; b=qsQPJoZq6+oLjTC8vkyWTUwC9k2MQ6az4zyWe5t8TC6BmBD6IPUPx+DGnn5BX3HahdI es3Ihiuy+QzdMT9Yfv7Hn+5dTl2BFdVDRBZSvICRevQUJzXzfX+bzmKvfeC8hpyPjjUmz XoB7Kv2T+GaxqJ0o4WjkovOidg5SOgwyArI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3246 1.Purpose: Skip port IO/MMIO/MSR access in some emulatoion env. Trace port IO/MMIO/MSR access. 2.Plan to do in Edk2: Filter and trace in low level APIs in BaseIoLibIntrinsic and BaseLib. Add a new library class (RegisterFilterLib) for the filter and trace func= tionality. 3.Plan to filter and trace scope in Edk2 : a. Port IO R/W: IA32 X64 (Only filter/trace for IA32 X64) b. MMIO R/W: IA32 X64 EBC ARM AARCH64 RISCV64 (Filter/trace for the Arche= s supported in BaseIoLibIntrinsic.inf) c. MSR R/W: IA32 X64 (Only filter/trace for IA32 X64, if other ARCH has s= imilar use case can add new APIs per needs) 4.RegisterFilterLib Library Class: a. Add RegisterFilterLib library class for the filter and trace operation. b. Add RegisterFilterLib.h in MdePkg/Include/Library. c. 12 APIs will be added to filter and trace port IO, MMIO and MSR access. d. Add a NULL instance RegisterFilterLibNull in MdePkg/Library.(Verified = that null instance will not impact binary size.) e. Platform can implement its own RegisterFilterLib instance. 12 APIs can be divided into 2 categories: 6 [Before] APIs use to check whether need to execute port IO/MMIO/MSR acc= ess or do some tracing before access. 6 [After] APIs use to trace after port IO/MMIO/MSR access. The detailed API definitions are included in this patch. For port IO access: FilterBeforeIoRead=20 FilterAfterIoRead FilterBeforeIoWrite=20 FilterAfterIoWrite For MMIO access: FilterBeforeMmIoRead FilterAfterMmIoRead FilterBeforeMmIoWrite FilterAfterMmIoWrite For MSR access: FilterBeforeMsrRead=20 FilterAfterMsrRead FilterBeforeMsrWrite FilterAfterMsrWrite 5.Change and Impact a. Add the RegisterFilterLib libary class and RegisterFilterLibNull insta= nce firstly. b. Update the dsc in edk2 and edk2-platform repo to consume the RegisterF= ilterLibNull instance. c. Update the BaseLib and IoLib to consume RegisterFilterLib. =20 This is an incompatible change. No code change in BaseLib and IoLib consumers, only need to change dsc to= consume new FilterLib instance. Update BaseIoLibIntrinsic.inf and BaseIoLibIntrinsicSev.inf to consume Re= gisterFilterLib for all supported Arch Update BaseLib.inf to consume RegisterFilterLib only for IA32 and X64 This topic has been reviewed in Tiano Design meeting of 2021/0305 RegisterFilterLib header file and desgin foil can be found in: https://edk2.groups.io/g/devel/files/Designs/2021/0305 Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Dandan Bi --- MdePkg/Include/Library/RegisterFilterLib.h | 224 +++++++++++++++++++++ 1 file changed, 224 insertions(+) create mode 100644 MdePkg/Include/Library/RegisterFilterLib.h diff --git a/MdePkg/Include/Library/RegisterFilterLib.h b/MdePkg/Include/Li= brary/RegisterFilterLib.h new file mode 100644 index 0000000000..be111304ba --- /dev/null +++ b/MdePkg/Include/Library/RegisterFilterLib.h @@ -0,0 +1,224 @@ +/** @file + Public include file for the Port IO/MMIO/MSR filter Library + +Copyright (c) 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __REGISTER_FILTER_LIB_H__ +#define __REGISTER_FILTER_LIB_H__ + +typedef enum { + FilterWidth8, + FilterWidth16, + FilterWidth32, + FilterWidth64 +} FILTER_IO_WIDTH; + +/** + Filter IO read operation before read IO port. + It is used to filter IO read operation. + + It will return the flag to decide whether require read real IO port. + It can be used for emulation environment. + + @param[in] Width Signifies the width of the I/O operation. + @param[in] Address The base address of the I/O operation. + @param[in] Buffer The destination buffer to store the results. + +**/ +BOOLEAN +EFIAPI +FilterBeforeIoRead ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN OUT VOID *Buffer + ); + +/** + Trace IO read operation after read IO port. + It is used to trace IO operation. + + @param[in] Width Signifies the width of the I/O operation. + @param[in] Address The base address of the I/O operation. + @param[in] Buffer The destination buffer to store the results. + +**/ +VOID +EFIAPI +FilterAfterIoRead ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); +/** + Filter IO Write operation before wirte IO port. + It is used to filter IO operation. + + It will return the flag to decide whether require read write IO port. + It can be used for emulation environment. + + @param[in] Width Signifies the width of the I/O operation. + @param[in] Address The base address of the I/O operation. + @param[in] Buffer The source buffer from which to BeforeWrite da= ta. + +**/ +BOOLEAN +EFIAPI +FilterBeforeIoWrite ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); + + /** + Trace IO Write operation after wirte IO port. + It is used to trace IO operation. + + @param[in] Width Signifies the width of the I/O operation. + @param[in] Address The base address of the I/O operation. + @param[in] Buffer The source buffer from which to BeforeWrite da= ta. + +**/ +VOID +EFIAPI +FilterAfterIoWrite ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); + +/** + Filter memory IO before Read operation. + + It will return the flag to decide whether require read real MMIO. + It can be used for emulation environment. + + @param[in] Width Signifies the width of the memory I/O operatio= n. + @param[in] Address The base address of the memory I/O operation. + @param[in] Buffer The destination buffer to store the results. + +**/ +BOOLEAN +EFIAPI +FilterBeforeMmIoRead ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN OUT VOID *Buffer + ); + +/** + Tracer memory IO after read operation + + @param[in] Width Signifies the width of the memory I/O operatio= n. + @param[in] Address The base address of the memory I/O operation. + @param[in] Buffer The destination buffer to store the results. + +**/ +VOID +EFIAPI +FilterAfterMmIoRead ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); + +/** + Filter memory IO before write operation + + It will return the flag to decide whether require wirte real MMIO. + It can be used for emulation environment. + + @param[in] Width Signifies the width of the memory I/O operatio= n. + @param[in] Address The base address of the memory I/O operation. + @param[in] Buffer The source buffer from which to BeforeWrite da= ta. + +**/ +BOOLEAN +EFIAPI +FilterBeforeMmIoWrite ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); + +/** + Tracer memory IO after write operation + + @param[in] Width Signifies the width of the memory I/O operatio= n. + @param[in] Address The base address of the memory I/O operation. + @param[in] Buffer The source buffer from which to BeforeWrite da= ta. + +**/ +VOID +EFIAPI +FilterAfterMmIoWrite ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); + +/** + Filter MSR before read operation. + + It will return the flag to decide whether require read real MSR. + It can be used for emulation environment. + + @param Index The 8-bit Machine Specific Register in= dex to BeforeWrite. + @param Value The 64-bit value to BeforeRead from th= e Machine Specific Register. + +**/ +BOOLEAN +EFIAPI +FilterBeforeMsrRead ( + IN UINT32 Index, + IN OUT UINT64 *Value + ); + +/** + Trace MSR after read operation + + @param Index The 8-bit Machine Specific Register in= dex to BeforeWrite. + @param Value The 64-bit value to BeforeRead from th= e Machine Specific Register. + +**/ +VOID +EFIAPI +FilterAfterMsrRead ( + IN UINT32 Index, + IN UINT64 *Value + ); + +/** + Filter MSR before write operation + + It will return the flag to decide whether require write real MSR. + It can be used for emulation environment. + + @param Index The 8-bit Machine Specific Register in= dex to BeforeWrite. + @param Value The 64-bit value to BeforeWrite to the= Machine Specific Register. + +**/ +BOOLEAN +EFIAPI +FilterBeforeMsrWrite ( + IN UINT32 Index, + IN UINT64 *Value + ); + +/** + Trace MSR after write operation + + @param Index The 8-bit Machine Specific Register in= dex to BeforeWrite. + @param Value The 64-bit value to BeforeWrite to the= Machine Specific Register. + +**/ +VOID +EFIAPI +FilterAfterMsrWrite ( + IN UINT32 Index, + IN UINT64 *Value + ); + +#endif // __REGISTER_FILTER_LIB_H__ --=20 2.18.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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