From nobody Sat May 4 03:20:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72156+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72156+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1614196161; cv=none; d=zohomail.com; s=zohoarc; b=O9qsdMkufHpjbYawJbiN1D9DnlhR6jq50uoLV9tAWGsqaXUPAHiiRIchaSoZzezP+JuLh5IaQuSfBi3zE80v0yaSNjdLnvJ/4f2PCwqRRt89A4pAbNGhr2xrZsev2bpDwfPgaaU0LGZCoIbY2Q18HtymHQbfwaBkkL4f5HmTwq4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614196161; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=RyNjfTiYwHrViVDTmsOxKDS65zoM7vP2V2KHqGMo+5A=; b=a9CbCH9tmkSENyEvUb1KB7p7IqD86WSyHuNgOJzzoVt0KkwPzZmIOAtjVQRy42vh1XVZ+V/ROQJUsc+EZk9VObUnIrun3MBBSaOc0ECqc/uXmY8ODu8vvGdN8fjIBBDawpR7/h3xIpaYO+ZhZ9HPPeLDF2+RTxs4yuKNFn+z9Aw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72156+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1614196161506283.5328342189123; Wed, 24 Feb 2021 11:49:21 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id A2gbYY1788612xE4Spcq5ATo; Wed, 24 Feb 2021 11:49:20 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.6623.1614172355420694373 for ; Wed, 24 Feb 2021 05:12:35 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 07CA91FB; Wed, 24 Feb 2021 05:12:35 -0800 (PST) X-Received: from usa.arm.com (a074744.blr.arm.com [10.162.17.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 523AF3F70D; Wed, 24 Feb 2021 05:12:33 -0800 (PST) From: Chandni Cherukuri To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation Date: Wed, 24 Feb 2021 18:42:20 +0530 Message-Id: <20210224131224.11481-2-chandni.cherukuri@arm.com> In-Reply-To: <20210224131224.11481-1-chandni.cherukuri@arm.com> References: <20210224131224.11481-1-chandni.cherukuri@arm.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chandni.cherukuri@arm.com X-Gm-Message-State: ABTwcQggQcKEEhwwaf77MvlTx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1614196160; bh=5vj95WZlfByRLnMK50iBuztG6KFvttJDUzmRcONMKi4=; h=Cc:Date:From:Reply-To:Subject:To; b=WsouISAw4QeLzQTxbxZaUolW4SSl2Xzkf1M5wyQIQu+7Ex5b4rpG9PYgL1fSmRgn7J5 NmVQYGS9EZV49Z7wbdkAh5ChUYyUkZuI1Jts7LMq/q6oFMNYp5TLn6SvnI5hZLj/1PnfD 8PJC/SWFtrMIJgTOBPlXWwSxA+32WMGZg3M= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Anurag Koul This patch adds initial Morello Platform Library support. It includes virtual memory map and helper functions for platform initialization. Co-authored-by: Chandni Cherukuri Signed-off-by: Chandni Cherukuri --- Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf | 52 ++++++ Platform/ARM/Morello/Include/MorelloPlatform.h | 67 +++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c | 66 +++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c | 194 ++++++++++= ++++++++++ Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S | 83 +++++++++ 5 files changed, 462 insertions(+) diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf b/Pla= tform/ARM/Morello/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 000000000000..2066d1f3a3f8 --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,52 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D ArmMorelloLib + FILE_GUID =3D 36853D86-7200-47B4-9408-E962A00963FD + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[Sources.common] + PlatformLibMem.c + PlatformLib.c + +[Sources.AARCH64] + AArch64/Helper.S | GCC + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base + + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress + gArmMorelloTokenSpaceGuid.PcdPciIoSize + +[Guids] + gEfiHobListGuid ## CONSUMES ## SystemTable + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/Morello/Include/MorelloPlatform.h b/Platform/ARM/= Morello/Include/MorelloPlatform.h new file mode 100644 index 000000000000..f61cfe7f9ee8 --- /dev/null +++ b/Platform/ARM/Morello/Include/MorelloPlatform.h @@ -0,0 +1,67 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef MORELLO_PLATFORM_H__ +#define MORELLO_PLATFORM_H__ + +#define MORELLO_DRAM_BLOCK1_SIZE SIZE_2GB + +// ***********************************************************************= ***** +// Platform Memory Map +// ***********************************************************************= ***** + +// SubSystem Peripherals - UART0 +#define MORELLO_UART0_BASE 0x2A400000 +#define MORELLO_UART0_SZ SIZE_64KB + +// SubSystem Peripherals - UART1 +#define MORELLO_UART1_BASE 0x2A410000 +#define MORELLO_UART1_SZ SIZE_64KB + +// SubSystem Peripherals - Generic Watchdog +#define MORELLO_GENERIC_WDOG_BASE 0x2A440000 +#define MORELLO_GENERIC_WDOG_SZ SIZE_128KB + +// SubSystem Peripherals - GIC(600) +#define MORELLO_GIC_BASE 0x30000000 +#define MORELLO_GICR_BASE 0x300C0000 +#define MORELLO_GIC_SZ SIZE_256KB +#define MORELLO_GICR_SZ SIZE_1MB + +// SubSystem non-secure SRAM +#define MORELLO_NON_SECURE_SRAM_BASE 0x06000000 +#define MORELLO_NON_SECURE_SRAM_SZ SIZE_64KB + +// AXI Expansion peripherals +#define MORELLO_EXP_PERIPH_BASE 0x1C000000 +#define MORELLO_EXP_PERIPH_BASE_SZ 0x1300000 + +// Platform information structure base address +#define MORELLO_PLAT_INFO_STRUCT_BASE MORELLO_NON_SECURE_SRAM_BASE + +/* + * Platform information structure stored in Non-secure SRAM. Platform + * information are passed from the trusted firmware with the below structu= re + * format. The elements of MORELLO_PLAT_INFO should be always in sync with + * the lower level firmware. + */ +#pragma pack(1) + +typedef struct { + /*! Local DDR memory size in Bytes */ + UINT64 LocalDdrSize; + /*! Remote DDR memory size in Bytes */ + UINT64 RemoteDdrSize; + /*! Slave count in C2C mode */ + UINT8 SlaveCount; + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ + UINT8 Mode; +} MORELLO_PLAT_INFO; + +#pragma pack() + +#endif diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c b/Platf= orm/ARM/Morello/Library/PlatformLib/PlatformLib.c new file mode 100644 index 000000000000..cd06ca5ce53f --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,66 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +STATIC ARM_CORE_INFO mCoreInfoTable[] =3D { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 + { 0x1, 0x0 }, // Cluster 1, Core 0 + { 0x1, 0x1 } // Cluster 1, Core 1 +}; + +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); + *ArmCoreTable =3D mCoreInfoTable; + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { + PrePeiCoreGetMpCoreInfo +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c b/Pl= atform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 000000000000..140a6ec79bd3 --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,194 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +// The total number of descriptors, including the final "end-of-table" des= criptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 + +#if !defined(MDEPKG_NDEBUG) +STATIC CONST CHAR8 *tblAttrDesc[] =3D { + "UNCACHED_UNBUFFERED ", + "NONSECURE_UNCACHED_UNBUFFERED", + "WRITE_BACK ", + "NONSECURE_WRITE_BACK ", + "WB_NONSHAREABLE ", + "NONSECURE_WB_NONSHAREABLE ", + "WRITE_THROUGH ", + "NONSECURE_WRITE_THROUGH ", + "DEVICE ", + "NONSECURE_DEVICE " +}; +#endif + +#define LOG_MEM(desc) DEBUG (( \ + EFI_D_ERROR, \ + desc, \ + VirtualMemoryTable[Index].PhysicalBase, \ + (VirtualMemoryTable[Index].PhysicalBase + \ + VirtualMemoryTable[Index].Length - 1), \ + VirtualMemoryTable[Index].Length, \ + tblAttrDesc[VirtualMemoryTable[Index].Attributes] \ + )); + +/** + Returns the Virtual Memory Map of the platform. + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing + a Physical-to-Virtual Memory mapping. This = array + must be ended by a zero-filled entry. +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + UINTN Index =3D 0; + ARM_MEMORY_REGION_DESCRIPTOR * VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + MORELLO_PLAT_INFO * PlatInfo; + UINT64 DramBlock2Size =3D 0; + + PlatInfo =3D (MORELLO_PLAT_INFO *)MORELLO_PLAT_INFO_STRUCT_BASE; + if (PlatInfo->LocalDdrSize > MORELLO_DRAM_BLOCK1_SIZE) + DramBlock2Size =3D PlatInfo->LocalDdrSize - MORELLO_DRAM_BLOCK1_SIZE; + + if (DramBlock2Size !=3D 0) { + ResourceAttributes =3D + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdDramBlock2Base), + DramBlock2Size); + } + + ASSERT (VirtualMemoryMap !=3D NULL); + Index =3D 0; + + VirtualMemoryTable =3D AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTO= R) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + DEBUG (( + EFI_D_ERROR, + " Memory Map\n--------------------------------------------------------= --\n" + )); + DEBUG (( + EFI_D_ERROR, + "Description : START - END = " \ + "[ SIZE ] { ATTR }\n" + )); + + // SubSystem Peripherals - Generic Watchdog + VirtualMemoryTable[Index].PhysicalBase =3D MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_GENERIC_WDOG_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("Generic Watchdog : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem Peripherals - GIC-600 + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_GIC_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_GIC_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_GIC_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("GIC-600 : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem Peripherals - GICR-600 + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_GICR_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_GICR_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_GICR_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("GICR-600 : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_NON_SECURE_SRAM_BA= SE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_NON_SECURE_SRAM_BA= SE; + VirtualMemoryTable[Index].Length =3D MORELLO_NON_SECURE_SRAM_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_UNCACHED_UNBUFFERED; + LOG_MEM ("non-secure SRAM : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // SubSystem Pheripherals - UART0 + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_UART0_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_UART0_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_UART0_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("UART0 : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // DDR Primary + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemoryS= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_WRITE_BACK; + LOG_MEM ("DDR Primary : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // DDR Secondary + if (DramBlock2Size !=3D 0) { + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdDramBlock2B= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdDramBlock2B= ase); + VirtualMemoryTable[Index].Length =3D DramBlock2Size; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_WRITE_BACK; + LOG_MEM ("DDR Secondary : 0x%016lx - 0x%016lx [ 0x%0= 16lx ] { %a }\n"); + } + + // Expansion Peripherals + VirtualMemoryTable[++Index].PhysicalBase =3D MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase =3D MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].Length =3D MORELLO_EXP_PERIPH_BASE_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("Expansion Peripherals : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // PCI Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciExpressBas= eAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciExpressBas= eAddress); + VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdPciBusM= ax) - + FixedPcdGet32 (PcdPciBusMin= ) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("PCI Configuration Space : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // PCI MMIO32/IO Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdPciMmio32Base= ); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdPciMmio32Base= ); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdPciMmio32Size= ) + + PcdGet32 (PcdPciIoSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("PCI MMIO32 & IO Region : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // PCI MMIO64 Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciMmio64Base= ); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciMmio64Base= ); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdPciMmio64Size= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + LOG_MEM ("PCI MMIO64 Region : 0x%016lx - 0x%016lx [ 0x%016= lx ] { %a }\n"); + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBU= TES)0; + + ASSERT ((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S b/Pl= atform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S new file mode 100644 index 000000000000..f6cc087a132c --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S @@ -0,0 +1,83 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + ret + +// +// Return the core position from the value of its MpId register +// +// This function returns core position from the position 0 in the processo= r. +// This function might be called from assembler before any stack is set. +// +// @return Return the core position +// +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +// +// Return the MpId of the primary core +// +// This function returns the MpId of the primary core. +// This function might be called from assembler before any stack is set. +// +// @return Return the MpId of the primary core +// +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +// +// Return a non-zero value if the callee is the primary core +// +// This function returns a non-zero value if the callee is the primary cor= e. +// Primary core is the core responsible to initialize hardware and run UEF= I. +// This function might be called from assembler before any stack is set. +// +// @return Return a non-zero value if the callee is the primary core. +// +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72156): https://edk2.groups.io/g/devel/message/72156 Mute This Topic: https://groups.io/mt/80885826/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 03:20:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72157+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72157+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1614196168; cv=none; d=zohomail.com; s=zohoarc; b=BvJw3JhjWsXK/69vTdweAybnOnM5eVJavGLkB28GKrt5uWkzB0peMoy3TcdAMTgCdE0E0VqchyH5LnZDpSSr8Vaa6furFIFuBPXLMZ7UIUjVkBzTUKyABX5fHy+i4cPV4Zi3ypoxh/5/TiGMeejXg+2Yi7j/QX3bWeXxC9DkP3Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614196168; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=z7E5AK89CJ+ml3N+nk9brPAeM7M8DLKA2SI5lgRhRjw=; b=Ir0Up9GJt72aMpgNO0P2slaNyIMolgsLteKJocPkaSrMswtoSgUEK3Dzzo4MeIa6L2qJsY8lC32e0q/uJPpI/7W+hn0SmtskGBpLmRtss39PrML1amsAsrURmNz1KtUCnfdOsA8Bp8ICIt/Qd2hKbzEv8qbQXJOVfO/KG2ztC4M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72157+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161419616899356.880499101438545; Wed, 24 Feb 2021 11:49:28 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id iN5aYY1788612xwMdbPxjJ1d; Wed, 24 Feb 2021 11:49:27 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.6495.1614172357295767756 for ; Wed, 24 Feb 2021 05:12:37 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EB0E31FB; Wed, 24 Feb 2021 05:12:36 -0800 (PST) X-Received: from usa.arm.com (a074744.blr.arm.com [10.162.17.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7B3613F70D; Wed, 24 Feb 2021 05:12:35 -0800 (PST) From: Chandni Cherukuri To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 2/5] Platform/ARM/Morello: Add support for PciHostBridgeLib Date: Wed, 24 Feb 2021 18:42:21 +0530 Message-Id: <20210224131224.11481-3-chandni.cherukuri@arm.com> In-Reply-To: <20210224131224.11481-1-chandni.cherukuri@arm.com> References: <20210224131224.11481-1-chandni.cherukuri@arm.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chandni.cherukuri@arm.com X-Gm-Message-State: flTUbhpz2fRmbJYzva94QbT9x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1614196167; bh=YyNbpaPnbwtUA1qtkwsi/qSIAnj+ZxXvCLxIElpr1z8=; h=Cc:Date:From:Reply-To:Subject:To; b=CmYd6D3VRqtjnbTeQVkuj87V1Sy5/ZYQ71vjTwI0GklYfssq8Pk5ftZSbRv0MWhgJ86 Ag8DF0oQLFJ3wL1Bvvy61E4spGn+kJv7cv98lhYxjFa0spjBGnuxUBRniSH0nRFZCqzn/ Vf7Qu8d5nnCbGYsuWhpkXlJ4D/HhM8fwZPg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Morello FVP platform supports a PCIe root complex. This patch implements PciHostBridgeLib to support PCIe. Signed-off-by: Chandni Cherukuri --- Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf | 4= 8 ++++++ Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c | 18= 2 ++++++++++++++++++++ 2 files changed, 230 insertions(+) diff --git a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLib= Fvp.inf b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp= .inf new file mode 100644 index 000000000000..3220704b2984 --- /dev/null +++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf @@ -0,0 +1,48 @@ +## @file +# PCI Host Bridge Library instance for ARM Morello FVP platform. +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PciHostBridgeLib + FILE_GUID =3D 6879CEAD-DC94-42EB-895C-096D36B8083C + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D AARCH64 +# + +[Sources] + PciHostBridgeLibFvp.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[FixedPcd] + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciIoBase + gArmMorelloTokenSpaceGuid.PcdPciIoSize + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + +[Protocols] + gEfiCpuIo2ProtocolGuid ## CONSUMES + +[Depex] + gEfiCpuIo2ProtocolGuid diff --git a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLib= Fvp.c b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c new file mode 100644 index 000000000000..a88da8950362 --- /dev/null +++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c @@ -0,0 +1,182 @@ +/** @file + PCI Host Bridge Library instance for ARM Morello FVP platform. + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include + +#define ROOT_COMPLEX_NUM 1 + +GLOBAL_REMOVE_IF_UNREFERENCED +STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D= { + L"Mem", L"I/O", L"Bus" +}; + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_CO= MPLEX_NUM] =3D { + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID(0x0A08), + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, +}; + +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] =3D { + { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpa= ce + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, { + // Io + FixedPcdGet64 (PcdPciIoBase), + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPciMmio32Base), + FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) = - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPciMmio64Base), + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) = - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] + }, +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + *Count =3D ARRAY_SIZE (mPciRootBridge); + return mPciRootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the reso= urces + for all the root bridges. The resource for each = root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of= the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex =3D 0; + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript= or++) { + ASSERT (Descriptor->ResType < + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]) + ) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType= ], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag =3D %ld / %02x= %s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETC= HABLE + ) !=3D 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72157): https://edk2.groups.io/g/devel/message/72157 Mute This Topic: https://groups.io/mt/80885827/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 03:20:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72158+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72158+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1614196166; cv=none; d=zohomail.com; s=zohoarc; b=g/dgLsEBLsGDoDL/WBaMKC4GNSYk0lnsFaMOMQMhjuIFYcOu2xTnHYhgVW/cB7V45BS03ihqiMmRK4R0fpOJ6P25PHLriQG2boLH2L49hu72sppz6r3wWtSx5RYuqN7o2GhgpZ7vjMD9xLf7gQRLXJ9iyH/3jXhCNBFRhAQu4XI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614196166; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=5FsmKjI77ghHTWosXxvmgpe+xjVB3YYF0Dj/M6Vl9zA=; b=jWo+ht9ekJmw1dWEMyYHYRuDhGcP2QUvj4dq/4bO8/d83OfJqdU72ki1nXlz/Hmp7wQb191lnahL71lI+Xk+mxXZt5qu4zrN/gWVhSVI5/v5IZ5gvFjSC1ddgrscxwMbgoqRqbEfy7/jzJBgmyyEobSanLS7XQArKGYkjwgOTmo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72158+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1614196166642630.8863452021467; Wed, 24 Feb 2021 11:49:26 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id RiG7YY1788612xou82l3fi4B; Wed, 24 Feb 2021 11:49:26 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.6496.1614172359280038901 for ; Wed, 24 Feb 2021 05:12:39 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DA936101E; Wed, 24 Feb 2021 05:12:38 -0800 (PST) X-Received: from usa.arm.com (a074744.blr.arm.com [10.162.17.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6A35F3F70D; Wed, 24 Feb 2021 05:12:37 -0800 (PST) From: Chandni Cherukuri To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 3/5] Platform/ARM/Morello: Add PlatformDxe driver for Morello Date: Wed, 24 Feb 2021 18:42:22 +0530 Message-Id: <20210224131224.11481-4-chandni.cherukuri@arm.com> In-Reply-To: <20210224131224.11481-1-chandni.cherukuri@arm.com> References: <20210224131224.11481-1-chandni.cherukuri@arm.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chandni.cherukuri@arm.com X-Gm-Message-State: xITaTqMYItoyPxBXyCMFyhngx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1614196166; bh=HHNtG67Q/XtKTReYdKZqcXJFkmPCJmGbpiTKA1eky/Y=; h=Cc:Date:From:Reply-To:Subject:To; b=t2IbQQSnHfx0tEN3xZTabrAKDO9mpn0wZjKzDbMWqOM8Y3HNEbVgPPTODhu7rGK++w0 DPkIJaS3tnYF2LFISvg29byr3Oo+LlRicTSNG7DvX2t0BhDAedP6MSsRntnHos5RBcO9p l6kl7sPmSCM/51BRJJCoW9anQ2ty/TJAdhY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Anurag Koul This patch adds the PlatformDxe Driver for Morello platform. It includes the registration of the ramdisk device. Co-authored-by: Chandni Cherukuri Signed-off-by: Chandni Cherukuri --- Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf | 43 +++++= ++++ Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h | 14 +++ Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c | 58 +++++= ++++++++ Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c | 91 +++++= +++++++++++++++ 4 files changed, 206 insertions(+) diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf b/= Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf new file mode 100644 index 000000000000..69df9019cde3 --- /dev/null +++ b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf @@ -0,0 +1,43 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformDxe + FILE_GUID =3D 11FC8B5A-377D-47A8-AEE9-0093D3D3407F + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ArmMorelloEntryPoint + +[Sources.common] + PlatformDxeFvp.c + VirtioDevices.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[LibraryClasses] + UefiDriverEntryPoint + VirtioMmioDeviceLib + +[Protocols] + gEfiRamDiskProtocolGuid + +[FeaturePcd] + gArmMorelloTokenSpaceGuid.PcdRamDiskSupported + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported + +[FixedPcd] + gArmMorelloTokenSpaceGuid.PcdRamDiskBase + gArmMorelloTokenSpaceGuid.PcdRamDiskSize + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress + +[Depex] + gEfiRamDiskProtocolGuid diff --git a/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.= h b/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h new file mode 100644 index 000000000000..27ae61bb1cf5 --- /dev/null +++ b/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h @@ -0,0 +1,14 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef MORELLO_VIRTIO_DEVICES_FORMSET_H__ +#define MORELLO_VIRTIO_DEVICES_FORMSET_H__ + +#define MORELLO_VIRTIO_BLOCK_GUID \ + { 0x2B6E62D0, 0x9346, 0x4E1A, { 0xAA, 0x1E, 0xCB, 0x01, 0xC3, 0x23, 0x4A= , 0x00 } } + +#endif diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c b/Pl= atform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c new file mode 100644 index 000000000000..ff99c16b2c9a --- /dev/null +++ b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c @@ -0,0 +1,58 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +VOID +InitVirtioDevices ( + VOID + ); + +EFI_STATUS +EFIAPI +ArmMorelloEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_RAM_DISK_PROTOCOL *RamDisk; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + Status =3D EFI_SUCCESS; + + InitVirtioDevices (); + + if (FeaturePcdGet (PcdRamDiskSupported)) { + Status =3D gBS->LocateProtocol ( + &gEfiRamDiskProtocolGuid, + NULL, + (VOID**)&RamDisk + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Couldn't find the RAM Disk protocol %r\n", + __FUNCTION__, Status)); + return Status; + } + + Status =3D RamDisk->Register ( + (UINTN)PcdGet32 (PcdRamDiskBase), + (UINTN)PcdGet32 (PcdRamDiskSize), + &gEfiVirtualCdGuid, + NULL, + &DevicePath + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to register RAM Disk - %r\n", + __FUNCTION__, Status)); + } + } + + return Status; +} diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c b/Pla= tform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c new file mode 100644 index 000000000000..a83a4e71a47e --- /dev/null +++ b/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c @@ -0,0 +1,91 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH VendorDevicePath; + EFI_DEVICE_PATH_PROTOCOL End; +} VIRTIO_DEVICE_PATH; +#pragma pack () + +STATIC VIRTIO_DEVICE_PATH mVirtioBlockDevicePath =3D +{ + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)(sizeof (VENDOR_DEVICE_PATH)), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + MORELLO_VIRTIO_BLOCK_GUID, + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + sizeof (EFI_DEVICE_PATH_PROTOCOL), + 0 + } + } +}; + +// +// Initialize platform Virtio devices. +// +// @return None. +// +VOID +InitVirtioDevices ( + VOID + ) +{ + EFI_STATUS Status; + STATIC EFI_HANDLE mVirtIoBlkController =3D NULL; + + Status =3D EFI_SUCCESS; + + // Install protocol interface for storage device + if (FeaturePcdGet (PcdVirtioBlkSupported)) { + + Status =3D gBS->InstallProtocolInterface ( + &mVirtIoBlkController, + &gEfiDevicePathProtocolGuid, + EFI_NATIVE_INTERFACE, + &mVirtioBlockDevicePath + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to install EFI_DEVICE_PATH protocol= " + "for Virtio Block device (Status =3D %r)\n", + __FUNCTION__, Status)); + } else { + // Declare the Virtio BlockIo device + Status =3D VirtioMmioInstallDevice ( + FixedPcdGet32 (PcdVirtioBlkBaseAddress), + mVirtIoBlkController + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to find Virtio Block MMIO device " + "(Status =3D=3D %r)\n", __FUNCTION__, Status)); + gBS->UninstallProtocolInterface ( + mVirtIoBlkController, + &gEfiDevicePathProtocolGuid, + &mVirtioBlockDevicePath + ); + } else { + DEBUG ((DEBUG_INIT, "%a: Installed Virtio Block device\n", + __FUNCTION__)); + } + } + } +} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72158): https://edk2.groups.io/g/devel/message/72158 Mute This Topic: https://groups.io/mt/80885829/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 03:20:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72159+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72159+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1614196171; cv=none; d=zohomail.com; s=zohoarc; b=i7/b517vdqht8PqoX1rtwhvquBiE/I4KTzcizqd5bkG57o2py9jO01omrmw0VgRHxVHqieLJoq61PQOnX6GgY0f3jIWF5CRP4ygA+/mXiunsW4LzHfoDN7NhjJLCdZkphD0V9Wg4AH1EvXuTkJ9sp+pxDr/LbKIHyou0WoYiGYs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614196171; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=h3WdJwnRilzMDIt/PfSJ9bX8T9mLRQhijnOC1sbt5ac=; b=MpdHiI6tton2riAjOZGhLYzoR1U7KERIz/vwehF3rqoe5k+aIdUQCh3BplxCY+hzZlUFtr3Zln5tOMhmaLAxkYZ8xaV8kxYOqslOrGnQp096tMUucLNwnRnpvSHQP9E48wADR4HLefxUh2TonzUc5uZCafrtNn+sj57OOgIPA/0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72159+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1614196171201621.0020136942995; Wed, 24 Feb 2021 11:49:31 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ySMTYY1788612xz1MpwiBAt9; Wed, 24 Feb 2021 11:49:30 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.6498.1614172361654057623 for ; Wed, 24 Feb 2021 05:12:41 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D0731FB; Wed, 24 Feb 2021 05:12:41 -0800 (PST) X-Received: from usa.arm.com (a074744.blr.arm.com [10.162.17.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 584F43F70D; Wed, 24 Feb 2021 05:12:39 -0800 (PST) From: Chandni Cherukuri To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 4/5] Platform/ARM/Morello: Add Configuration Manager for Morello Date: Wed, 24 Feb 2021 18:42:23 +0530 Message-Id: <20210224131224.11481-5-chandni.cherukuri@arm.com> In-Reply-To: <20210224131224.11481-1-chandni.cherukuri@arm.com> References: <20210224131224.11481-1-chandni.cherukuri@arm.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chandni.cherukuri@arm.com X-Gm-Message-State: AGSZWPMEhnND3HVJBh4v8CZqx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1614196170; bh=i756AqxVxGKTpZRTaKy6gvfwhGwvj+8LLrIA/03C/XU=; h=Cc:Date:From:Reply-To:Subject:To; b=m4UsV1OW8WUf/SGN+a1y7DIxuA1t/cKUma+d1/cX92pxjo06Cv488gMeFcVxlZ2kPNX r2RZynddEFQ9DkzBFSGzGi1PHRmpJua5QFY5mj2bSwEbDtgxY6jLqO+6XgjGB2AMG9YSQ Ly6b9gGYrf7ysrphjwSVRodGdn3mGQBJMy8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch implements the configuration manager for Morello platform. It enables support for generating the following ACPI tables for Morello FVP Platform: 1. FADT 2. DSDT 3. GTDT 4. MADT 5. SPCR 6. DBG2 7. PPTT 8. IORT 9. MCFG 10. SSDT Structures have been created to add Common Platform information and FVP/Testchip platform specific information so that the same Dxe is usable for all variants of the platform. Co-authored-by: Jessica Clarke Signed-off-by: Chandni Cherukuri --- Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc = | 16 + Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Configur= ationManagerDxeFvp.inf | 94 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Configur= ationManager.h | 304 ++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Configur= ationManagerFvp.h | 81 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform= .h | 91 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Configur= ationManager.c | 1005 ++++++++++++++++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Configur= ationManagerFvp.c | 531 +++++++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTable= s/DsdtFvp.asl | 114 +++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTable= s/SsdtPciFvp.asl | 130 +++ 9 files changed, 2366 insertions(+) diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManager= Fvp.dsc.inc b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManage= rFvp.dsc.inc new file mode 100644 index 000000000000..71916783c24c --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc= .inc @@ -0,0 +1,16 @@ +## @file +# dsc include file for Configuration Manager +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + +[BuildOptions] + +[Components.common] + # Configuration Manager + Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Config= urationManagerDxeFvp.inf diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManager= Dxe/ConfigurationManagerDxeFvp.inf b/Platform/ARM/Morello/ConfigurationMana= ger/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf new file mode 100644 index 000000000000..9137de2dd118 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Con= figurationManagerDxeFvp.inf @@ -0,0 +1,94 @@ +## @file +# Configuration Manager Dxe +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D ConfigurationManagerDxe + FILE_GUID =3D 6F9C3B47-6F7D-44B6-87E5-4B7F44A60147 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ConfigurationManagerDxeInitialize + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D AARCH64 +# + +[Sources] + AslTables/DsdtFvp.asl + AslTables/SsdtPciFvp.asl + ConfigurationManagerFvp.c + ConfigurationManager.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + DynamicTablesPkg/DynamicTablesPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + +[Protocols] + gEdkiiConfigurationManagerProtocolGuid + +[FixedPcd] + ## PL011 Serial Debug UART + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz + + gArmPlatformTokenSpaceGuid.PL011UartClkInHz + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + # SBSA Generic Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt + + # PCI + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciBusCount + gArmMorelloTokenSpaceGuid.PcdPciIoBase + gArmMorelloTokenSpaceGuid.PcdPciIoSize + gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase + gArmMorelloTokenSpaceGuid.PcdPciIoTranslation + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase + gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase + gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress +[Pcd] + +[Depex] + TRUE diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManager= Dxe/ConfigurationManager.h b/Platform/ARM/Morello/ConfigurationManager/Conf= igurationManagerDxe/ConfigurationManager.h new file mode 100644 index 000000000000..b44270639001 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Con= figurationManager.h @@ -0,0 +1,304 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#ifndef CONFIGURATION_MANAGER_H__ +#define CONFIGURATION_MANAGER_H__ + +/** The configuration manager version. +*/ +#define CONFIGURATION_MANAGER_REVISION CREATE_REVISION (1, 0) + +/** The OEM ID +*/ +#define CFG_MGR_OEM_ID { 'A', 'R', 'M', 'L', 'T', 'D' } +#define CFG_MGR_OEM_REVISION 0x20181101 + +/** A helper macro for mapping a reference token +*/ +#define REFERENCE_TOKEN(Field) \ + (CM_OBJECT_TOKEN)((UINT8*)&CommonPlatformInfo + \ + OFFSET_OF (EDKII_COMMON_PLATFORM_REPOSITORY_INFO, Field)) + +/** A helper macro that constructs the MPID based on the + Aff0, Aff1, Aff2, Aff3 values +*/ +#define GET_MPID3(Aff3, Aff2, Aff1, Aff0) \ + (((Aff3##ULL) << 32) | ((Aff2) << 16) | ((Aff1) << 8) | (Aff0)) + +/** A helper macro for populating the GIC CPU information +*/ +#define GICC_ENTRY( \ + CPUInterfaceNumber, \ + Mpidr, \ + PmuIrq, \ + VGicIrq, \ + GicRedistBase, \ + EnergyEfficiency, \ + SpeIrq, \ + ProximityDomain, \ + ClockDomain \ + ) { \ + CPUInterfaceNumber, /* UINT32 CPUInterfaceNumber */ \ + CPUInterfaceNumber, /* UINT32 AcpiProcessorUid */ \ + EFI_ACPI_6_2_GIC_ENABLED, /* UINT32 Flags */ \ + 0, /* UINT32 ParkingProtocolVersion */ \ + PmuIrq, /* UINT32 PerformanceInterruptGsiv */ \ + 0, /* UINT64 ParkedAddress */ \ + FixedPcdGet64 ( \ + PcdGicInterruptInterfaceBase \ + ), /* UINT64 PhysicalBaseAddress */ \ + 0, /* UINT64 GICV */ \ + 0, /* UINT64 GICH */ \ + VGicIrq, /* UINT32 VGICMaintenanceInterrupt */ \ + GicRedistBase, /* UINT64 GICRBaseAddress */ \ + Mpidr, /* UINT64 MPIDR */ \ + EnergyEfficiency, /* UINT8 ProcessorPowerEfficiencyClass*/ \ + SpeIrq, /* UINT16 SpeOverflowInterrupt */ \ + ProximityDomain, /* UINT32 ProximityDomain */ \ + ClockDomain, /* UINT32 ClockDomain */ \ + EFI_ACPI_6_3_GICC_ENABLED,/* UINT32 Flags */ \ + } + +/** A helper macro for populating the Processor Hierarchy Node flags +*/ +#define PROC_NODE_FLAGS( \ + PhysicalPackage, \ + AcpiProcessorIdValid, \ + ProcessorIsThread, \ + NodeIsLeaf, \ + IdenticalImplementation \ + ) \ + ( \ + PhysicalPackage | \ + (AcpiProcessorIdValid << 1) | \ + (ProcessorIsThread << 2) | \ + (NodeIsLeaf << 3) | \ + (IdenticalImplementation << 4) \ + ) + +/** A helper macro for populating the Cache Type Structure's attributes +*/ +#define CACHE_ATTRIBUTES( \ + AllocationType, \ + CacheType, \ + WritePolicy \ + ) \ + ( \ + AllocationType | \ + (CacheType << 2) | \ + (WritePolicy << 4) \ + ) + +/** A helper macro for returning configuration manager objects +*/ +#define HANDLE_CM_OBJECT(ObjId, CmObjectId, Object, ObjectCount) \ + case ObjId: { \ + CmObject->ObjectId =3D CmObjectId; \ + CmObject->Size =3D sizeof (Object); \ + CmObject->Data =3D (VOID*)&Object; \ + CmObject->Count =3D ObjectCount; \ + DEBUG (( \ + DEBUG_INFO, \ + #CmObjectId ": Ptr =3D 0x%p, Size =3D %d, Count =3D %d\n", = \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + break; \ + } + +/** A helper macro for returning configuration manager objects + referenced by token +*/ +#define HANDLE_CM_OBJECT_REF_BY_TOKEN( = \ + ObjId, = \ + CmObjectId, = \ + Object, = \ + ObjectCount, = \ + Token, = \ + HandlerProc = \ + ) = \ + case ObjId: { = \ + CmObject->ObjectId =3D CmObjectId; = \ + if (Token =3D=3D CM_NULL_TOKEN) { = \ + CmObject->Size =3D sizeof (Object); = \ + CmObject->Data =3D (VOID*)&Object; = \ + CmObject->Count =3D ObjectCount; = \ + DEBUG (( = \ + DEBUG_INFO, = \ + #CmObjectId ": Ptr =3D 0x%p, Size =3D %d, Count =3D %d\n", = \ + CmObject->Data, = \ + CmObject->Size, = \ + CmObject->Count = \ + )); = \ + } else { = \ + Status =3D HandlerProc (This, CmObjectId, Token, CmObject); = \ + DEBUG (( = \ + DEBUG_INFO, = \ + #CmObjectId ": Token =3D 0x%p, Ptr =3D 0x%p, Size =3D %d, Count = =3D %d\n", \ + (VOID*)Token, = \ + CmObject->Data, = \ + CmObject->Size, = \ + CmObject->Count = \ + )); = \ + } = \ + break; = \ + } + +/** A helper macro for returning configuration manager objects referenced + by token when the entire platform repository is in scope and the + CM_NULL_TOKEN value is not allowed. +*/ +#define HANDLE_CM_OBJECT_SEARCH_PLAT_REPO( = \ + ObjId, = \ + CmObjectId, = \ + Token, = \ + HandlerProc = \ + ) = \ + case ObjId: { = \ + CmObject->ObjectId =3D CmObjectId; = \ + if (Token =3D=3D CM_NULL_TOKEN) { = \ + Status =3D EFI_INVALID_PARAMETER; = \ + DEBUG (( = \ + DEBUG_ERROR, = \ + #ObjId ": CM_NULL_TOKEN value is not allowed when searching" = \ + " the entire platform repository.\n" = \ + )); = \ + } else { = \ + Status =3D HandlerProc (This, CmObjectId, Token, CmObject); = \ + DEBUG (( = \ + DEBUG_INFO, = \ + #ObjId ": Token =3D 0x%p, Ptr =3D 0x%p, Size =3D %d, Count =3D %d\= n", \ + (VOID*)Token, = \ + CmObject->Data, = \ + CmObject->Size, = \ + CmObject->Count = \ + )); = \ + } = \ + break; = \ + } + +/** The number of CPUs +*/ +#define PLAT_CPU_COUNT 4 + +/** The number of platform generic timer blocks +*/ +#define PLAT_GTBLOCK_COUNT 1 + +/** The number of timer frames per generic timer block +*/ +#define PLAT_GTFRAME_COUNT 2 + +/** The number of Processor Hierarchy Nodes + - one package node + - two cluster nodes + - two cores in cluster 0 + - two cores in cluster 1 +*/ +#define PLAT_PROC_HIERARCHY_NODE_COUNT 7 + +/** The number of unique cache structures: + - cluster L3 unified cache + - core L1 instruction cache + - core L1 data cache + - core L2 cache + - slc unified cache +*/ +#define PLAT_CACHE_COUNT 5 + +/** The number of resources private to the cluster + - L3 cache +*/ +#define CLUSTER_RESOURCE_COUNT 1 + +/** The number of resources private to 'core instance + - L1 data cache + - L1 instruction cache + - L2 cache +*/ +#define CORE_RESOURCE_COUNT 3 + +/** The number of resources private to SoC + - slc cache + - Proc Node Id Info +*/ +#define SOC_RESOURCE_COUNT 2 + +/** A structure describing the platform configuration + manager repository information +*/ +typedef struct CommonPlatformRepositoryInfo { + /// Configuration Manager Information + CM_STD_OBJ_CONFIGURATION_MANAGER_INFO CmInfo; + + /// Boot architecture information + CM_ARM_BOOT_ARCH_INFO BootArchInfo; + +#ifdef HEADLESS_PLATFORM + /// Fixed feature flag information + CM_ARM_FIXED_FEATURE_FLAGS FixedFeatureFlags; +#endif + + /// Power management profile information + CM_ARM_POWER_MANAGEMENT_PROFILE_INFO PmProfileInfo; + + /// GIC CPU interface information + CM_ARM_GICC_INFO GicCInfo[PLAT_CPU_COUNT]; + + /// GIC distributor information + CM_ARM_GICD_INFO GicDInfo; + + /// GIC Redistributor information + CM_ARM_GIC_REDIST_INFO GicRedistInfo; + + /// Generic timer information + CM_ARM_GENERIC_TIMER_INFO GenericTimerInfo; + + /// Generic timer block information + CM_ARM_GTBLOCK_INFO GTBlockInfo[PLAT_GTBLOCK_COUNT]; + + /// Generic timer frame information + CM_ARM_GTBLOCK_TIMER_FRAME_INFO GTBlock0TimerInfo[PLAT_GTFRAME_COU= NT]; + + /// Watchdog information + CM_ARM_GENERIC_WATCHDOG_INFO Watchdog; + + /** Serial port information for the + serial port console redirection port + */ + CM_ARM_SERIAL_PORT_INFO SpcrSerialPort; + + /// Serial port information for the DBG2 UART port + CM_ARM_SERIAL_PORT_INFO DbgSerialPort; + + // Processor topology information + CM_ARM_PROC_HIERARCHY_INFO ProcHierarchyInfo[PLAT_PROC_HIERAR= CHY_NODE_COUNT]; + + // Processor Node Id Info + CM_ARM_PROC_NODE_ID_INFO ProcNodeIdInfo; + + + // Cache information + CM_ARM_CACHE_INFO CacheInfo[PLAT_CACHE_COUNT]; + + // Cluster private resources + CM_ARM_OBJ_REF ClusterResources[CLUSTER_RESOURCE_= COUNT]; + + // Core private resources + CM_ARM_OBJ_REF CoreResources[CORE_RESOURCE_COUNT]; + + // SoC Resources + CM_ARM_OBJ_REF SocResources[SOC_RESOURCE_COUNT]; + +} EDKII_COMMON_PLATFORM_REPOSITORY_INFO; + +#endif // CONFIGURATION_MANAGER_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManager= Dxe/ConfigurationManagerFvp.h b/Platform/ARM/Morello/ConfigurationManager/C= onfigurationManagerDxe/ConfigurationManagerFvp.h new file mode 100644 index 000000000000..be0f02fab1ce --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Con= figurationManagerFvp.h @@ -0,0 +1,81 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#ifndef FVP_CONFIGURATION_MANAGER_H__ +#define FVP_CONFIGURATION_MANAGER_H__ + +#include "ConfigurationManager.h" + +/** The number of ACPI tables to install +*/ +#define PLAT_ACPI_TABLE_COUNT 10 + +/** A helper macro for mapping a reference token +*/ +#define REFERENCE_TOKEN_FVP(Field) \ + (CM_OBJECT_TOKEN)((UINT8*)&MorelloFvpRepositoryInfo + \ + OFFSET_OF (EDKII_FVP_PLATFORM_REPOSITORY_INFO, Field)) + +/** C array containing the compiled AML template. + These symbols are defined in the auto generated C file + containing the AML bytecode array. +*/ +extern CHAR8 dsdtfvp_aml_code[]; +extern CHAR8 ssdtpcifvp_aml_code[]; + +//Add FVP Platform specific information +typedef struct FvpPlatformRepositoryInfo { + /// List of ACPI tables + CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[PLAT_ACPI_TABLE_CO= UNT]; + + /// GIC ITS information + CM_ARM_GIC_ITS_INFO GicItsInfo[2]; + + /// ITS Group node + CM_ARM_ITS_GROUP_NODE ItsGroupInfo[2]; + + /// ITS Identifier array + CM_ARM_ITS_IDENTIFIER ItsIdentifierArray[2]; + + /// SMMUv3 node + CM_ARM_SMMUV3_NODE SmmuV3Info[1]; + + /// PCI Root complex node + CM_ARM_ROOT_COMPLEX_NODE RootComplexInfo[1]; + + /// Array of DeviceID mapping + CM_ARM_ID_MAPPING DeviceIdMapping[2][2]; + + /// PCI configuration space information + CM_ARM_PCI_CONFIG_SPACE_INFO PciConfigInfo[1]; + +} EDKII_FVP_PLATFORM_REPOSITORY_INFO; + +typedef struct PlatformRepositoryInfo { + + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * CommonPlatRepoInfo; + + EDKII_FVP_PLATFORM_REPOSITORY_INFO * FvpPlatRepoInfo; + +} EDKII_PLATFORM_REPOSITORY_INFO; + +extern EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo; + +EFI_STATUS +EFIAPI +GetArmNameSpaceObjectPlat ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ); + +#endif // FVP_CONFIGURATION_MANAGER_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManager= Dxe/Platform.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationMan= agerDxe/Platform.h new file mode 100644 index 000000000000..2e5286e892df --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Pla= tform.h @@ -0,0 +1,91 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef PLATFORM_H__ +#define PLATFORM_H__ + +#define ENABLE_MEM_MAPPED_TIMER + +#ifdef ENABLE_MEM_MAPPED_TIMER +// REFCLK CNTControl +#define MORELLO_SYSTEM_TIMER_BASE_ADDRESS 0x2A430000 +// REFCLK CNTRead +#define MORELLO_CNT_READ_BASE_ADDRESS 0x2A800000 +#else +#define MORELLO_SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#define MORELLO_CNT_READ_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +// GT Block Timer +// AP_REFCLK CNTCTL +#define MORELLO_GT_BLOCK_CTL_BASE 0x2A810000 +#define MORELLO_TIMER_FRAMES_COUNT 2 + +// GT Block Timer Frames +// AP_REFCLK_NS CNTBase0 +#define MORELLO_GT_BLOCK_FRAME0_CTL_BASE 0x2A830000 +#define MORELLO_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define MORELLO_GT_BLOCK_FRAME0_GSIV 92 + +// AP_REFCLK_S CNTBase1 +#define MORELLO_GT_BLOCK_FRAME1_CTL_BASE 0x2A820000 +#define MORELLO_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define MORELLO_GT_BLOCK_FRAME1_GSIV 91 + +#define GTDT_TIMER_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_SAVE_CONTEXT \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY +#define GTDT_TIMER_LOSE_CONTEXT 0 + +#define MORELLO_GTDT_GTIMER_FLAGS (GTDT_TIMER_LOSE_CONTEXT | \ + GTDT_TIMER_ACTIVE_LOW | \ + GTDT_TIMER_LEVEL_TRIGGERED) + +// GT Block Timer Flags +#define GTX_TIMER_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTX_TIMER_LEVEL_TRIGGERED 0 +#define GTX_TIMER_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTX_TIMER_ACTIVE_HIGH 0 + +#define MORELLO_GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | \ + GTX_TIMER_LEVEL_TRIGGERED) + +#define GTX_TIMER_SECURE \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER +#define GTX_TIMER_NON_SECURE 0 +#define GTX_TIMER_SAVE_CONTEXT \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY +#define GTX_TIMER_LOSE_CONTEXT 0 + +#define MORELLO_GTX_COMMON_FLAGS_S (GTX_TIMER_SAVE_CONTEXT | \ + GTX_TIMER_SECURE) +#define MORELLO_GTX_COMMON_FLAGS_NS (GTX_TIMER_SAVE_CONTEXT | \ + GTX_TIMER_NON_SECURE) + +// Watchdog +#define SBSA_WATCHDOG_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE +#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0 +#define SBSA_WATCHDOG_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POL= ARITY +#define SBSA_WATCHDOG_ACTIVE_HIGH 0 +#define SBSA_WATCHDOG_SECURE \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER +#define SBSA_WATCHDOG_NON_SECURE 0 + +#define MORELLO_SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE = | \ + SBSA_WATCHDOG_ACTIVE_HIGH |= \ + SBSA_WATCHDOG_LEVEL_TRIGGERED) + +#endif // PLATFORM_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManager= Dxe/ConfigurationManager.c b/Platform/ARM/Morello/ConfigurationManager/Conf= igurationManagerDxe/ConfigurationManager.c new file mode 100644 index 000000000000..e324cc50853f --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Con= figurationManager.c @@ -0,0 +1,1005 @@ +/** @file + Configuration Manager Dxe + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#include +#include +#include +#include +#include + +#include "ConfigurationManagerFvp.h" +#include "ConfigurationManager.h" +#include "Platform.h" + +extern EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo; + +// The platform configuration repository information. +EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo =3D { + // Configuration Manager information + { CONFIGURATION_MANAGER_REVISION, CFG_MGR_OEM_ID }, + + // Boot architecture information + { EFI_ACPI_6_3_ARM_PSCI_COMPLIANT }, // BootArchFlags + +#ifdef HEADLESS_PLATFORM + // Fixed feature flag information + { EFI_ACPI_6_3_HEADLESS }, // Fixed feature flags +#endif + + // Power management profile information + { EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Pro= file + + /* GIC CPU Interface information + GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, GicRedistBase, + EnergyEfficiency, SpeIrq, ProximityDomain, ClockDomain) + */ + { + GICC_ENTRY (0, GET_MPID3 (0x0, 0x0, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (1, GET_MPID3 (0x0, 0x0, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (2, GET_MPID3 (0x0, 0x1, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (3, GET_MPID3 (0x0, 0x1, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0), + }, + + // GIC Distributor Info + { + FixedPcdGet64 (PcdGicDistributorBase), // UINT64 PhysicalBaseAddress + 0, // UINT32 SystemVectorBase + 3 // UINT8 GicVersion + }, + + // GIC Re-Distributor Info + { + // UINT64 DiscoveryRangeBaseAddress + FixedPcdGet64 (PcdGicRedistributorsBase), + // UINT32 DiscoveryRangeLength + SIZE_1MB + }, + + // Generic Timer Info + { + // The physical base address for the counter control frame + MORELLO_SYSTEM_TIMER_BASE_ADDRESS, + // The physical base address for the counter read frame + MORELLO_CNT_READ_BASE_ADDRESS, + // The secure PL1 timer interrupt + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), + // The secure PL1 timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The non-secure PL1 timer interrupt + FixedPcdGet32 (PcdArmArchTimerIntrNum), + // The non-secure PL1 timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The virtual timer interrupt + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), + // The virtual timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The non-secure PL2 timer interrupt + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), + // The non-secure PL2 timer flags + MORELLO_GTDT_GTIMER_FLAGS + }, + + // Generic Timer Block Information + { + { + // The physical base address for the GT Block Timer structure + MORELLO_GT_BLOCK_CTL_BASE, + // The number of timer frames implemented in the GT Block + MORELLO_TIMER_FRAMES_COUNT, + // Reference token for the GT Block timer frame list + REFERENCE_TOKEN (GTBlock0TimerInfo) + } + }, + + // GT Block Timer Frames + { + // Frame 0 + { + 0, // UINT8 FrameNumber + MORELLO_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 PhysicalAddressCntB= ase + MORELLO_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 PhysicalAddressCntE= L0Base + MORELLO_GT_BLOCK_FRAME0_GSIV, // UINT32 PhysicalTimerGSIV + MORELLO_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags + 0, // UINT32 VirtualTimerGSIV + 0, // UINT32 VirtualTimerFlags + MORELLO_GTX_COMMON_FLAGS_NS // UINT32 CommonFlags + }, + // Frame 1 + { + 1, // UINT8 FrameNumber + MORELLO_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 PhysicalAddressCntB= ase + MORELLO_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 PhysicalAddressCntE= L0Base + MORELLO_GT_BLOCK_FRAME1_GSIV, // UINT32 PhysicalTimerGSIV + MORELLO_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags + 0, // UINT32 VirtualTimerGSIV + 0, // UINT32 VirtualTimerFlags + MORELLO_GTX_COMMON_FLAGS_S // UINT32 CommonFlags + }, + }, + + // Watchdog Info + { + // The physical base address of the SBSA Watchdog control frame + FixedPcdGet64 (PcdGenericWatchdogControlBase), + // The physical base address of the SBSA Watchdog refresh frame + FixedPcdGet64 (PcdGenericWatchdogRefreshBase), + // The watchdog interrupt + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), + // The watchdog flags + MORELLO_SBSA_WATCHDOG_FLAGS + }, + + // SPCR Serial Port + { + FixedPcdGet64 (PcdSerialRegisterBase), // BaseAddress + FixedPcdGet32 (PL011UartInterrupt), // Interrupt + FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate + FixedPcdGet32 (PL011UartClkInHz), // Clock + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART // Port subtype + }, + + // Debug Serial Port + { + FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress + 0, // Interrupt -= unused + FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate + FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART // Port subtype + }, + + // Processor Hierarchy Nodes + { + // Package + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[0]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + CM_NULL_TOKEN, + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + SOC_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (SocResources) + }, + + // Cluster0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[1]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + CLUSTER_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (ClusterResources) + }, + // Cluster1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[2]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + CLUSTER_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (ClusterResources) + }, + // Cluster0 - Cpu0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[3]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[0]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + // Cluster0 - Cpu1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[4]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[1]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + // Cluster1 - Cpu0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[3]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[2]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + + // Cluster1 - Cpu1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[4]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[3]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + }, + + // Processor Node Id Info + { + // A unique token used to identify this object + REFERENCE_TOKEN (ProcNodeIdInfo), + // Vendor ID (as described in ACPI ID registry) + SIGNATURE_32('A', 'R', 'M', 'H'), + // First level unique node ID + 0, + // Second level unique node ID + 0, + // Major revision of the node + 0, + // Minor revision of the node + 0, + // Spin revision of the node + 0 + }, + + // Cache information + { + // 'cluster's L3 cache + { + REFERENCE_TOKEN (CacheInfo[0]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCach= eToken + SIZE_1MB, // UINT32 Size + 2048, // UINT32 NumberOfSets + 8, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // 'core's L1 instruction cache + { + REFERENCE_TOKEN (CacheInfo[1]), // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCach= eToken + SIZE_64KB, // UINT32 Size + 256, // UINT32 NumberOfSets + 4, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // 'core's L1 data cache + { + REFERENCE_TOKEN (CacheInfo[2]), // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCach= eToken + SIZE_64KB, // UINT32 Size + 256, // UINT32 NumberOfSets + 4, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // cores's L2 cache + { + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCach= eToken + SIZE_1MB, // UINT32 Size + 2048, // UINT32 NumberOfSets + 8, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // slc cache + { + REFERENCE_TOKEN (CacheInfo[4]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCach= eToken + SIZE_8MB, // UINT32 Size + 4096, // UINT32 NumberOfSets + 16, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + }, + // Resources private to the 'cluster (shared among cores) in Cluster + { + { REFERENCE_TOKEN (CacheInfo[0]) } // -> 'cluster's L3 cache in Clust= er + }, + // Resources private to each individual 'core instance in Cluster + { + { REFERENCE_TOKEN (CacheInfo[1]) }, // -> 'core's L1 I-cache in Cluster + { REFERENCE_TOKEN (CacheInfo[2]) }, // -> 'core's L1 D-cache in Cluster + { REFERENCE_TOKEN (CacheInfo[3]) } // -> 'core's L2 cache in Cluster + }, + + // Resources private to the SoC + { + { REFERENCE_TOKEN (CacheInfo[4]) }, // -> slc for SoC + { REFERENCE_TOKEN (ProcNodeIdInfo) }, // -> ProcNodeIdInfo for SoC + }, +}; + +/** Initialize the Platform Configuration Repository. + + @param [in] This Pointer to the Platform Configuration Repositor= y. + + @retval + EFI_SUCCESS Success +**/ +STATIC +EFI_STATUS +EFIAPI +InitializePlatformRepository ( + IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatformRepo + ) +{ + return EFI_SUCCESS; +} + +/** Return a GT Block timer frame info list. + + @param [in] This Pointer to the Configuration Manager Protoc= ol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not fou= nd. +**/ +EFI_STATUS +EFIAPI +GetGTBlockTimerFrameInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo =3D This->PlatRepoInfo->CommonPlatRepoInfo; + + if (Token !=3D (CM_OBJECT_TOKEN)&PlatformRepo->GTBlock0TimerInfo) { + return EFI_NOT_FOUND; + } + + CmObject->ObjectId =3D CmObjectId; + CmObject->Size =3D sizeof (PlatformRepo->GTBlock0TimerInfo); + CmObject->Data =3D (VOID*)&PlatformRepo->GTBlock0TimerInfo; + CmObject->Count =3D sizeof (PlatformRepo->GTBlock0TimerInfo) / + sizeof (PlatformRepo->GTBlock0TimerInfo[0]); + return EFI_SUCCESS; +} + +/** Return GIC CPU Interface Info. + + @param [in] This Pointer to the Configuration Manager Pro= tocol. + @param [in] CmObjectId The Object ID of the CM object requested + @param [in] SearchToken A unique token for identifying the reque= sted + CM_ARM_GICC_INFO object. + @param [in, out] CmObject Pointer to the Configuration Manager Obj= ect + descriptor describing the requested Obje= ct. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not f= ound. +**/ +EFI_STATUS +EFIAPI +GetGicCInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN SearchToken, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINT32 TotalObjCount; + UINT32 ObjIndex; + + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo =3D This->PlatRepoInfo->CommonPlatRepoInfo; + TotalObjCount =3D PLAT_CPU_COUNT; + + for (ObjIndex =3D 0; ObjIndex < TotalObjCount; ObjIndex++) { + if (SearchToken =3D=3D (CM_OBJECT_TOKEN)&PlatformRepo->GicCInfo[ObjInd= ex]) { + CmObject->ObjectId =3D CmObjectId; + CmObject->Size =3D sizeof (PlatformRepo->GicCInfo[ObjIndex]); + CmObject->Data =3D (VOID*)&PlatformRepo->GicCInfo[ObjIndex]; + CmObject->Count =3D 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return a list of Configuration Manager object references pointed to by= the + given input token. + + @param [in] This Pointer to the Configuration Manager Pro= tocol. + @param [in] CmObjectId The Object ID of the CM object requested + @param [in] SearchToken A unique token for identifying the reque= sted + CM_ARM_OBJ_REF list. + @param [in, out] CmObject Pointer to the Configuration Manager Obj= ect + descriptor describing the requested Obje= ct. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not f= ound. +**/ +EFI_STATUS +EFIAPI +GetCmObjRefs ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN SearchToken, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo =3D This->PlatRepoInfo; + + if (SearchToken =3D=3D (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInf= o->ClusterResources) { + CmObject->Size =3D sizeof (PlatformRepo->CommonPlatRepoInfo->ClusterRe= sources); + CmObject->Data =3D (VOID*)&PlatformRepo->CommonPlatRepoInfo->ClusterRe= sources; + CmObject->Count =3D ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->Clus= terResources); + return EFI_SUCCESS; + } + if (SearchToken =3D=3D (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInf= o->CoreResources) { + CmObject->Size =3D sizeof (PlatformRepo->CommonPlatRepoInfo->CoreResou= rces); + CmObject->Data =3D (VOID*)&PlatformRepo->CommonPlatRepoInfo->CoreResou= rces; + CmObject->Count =3D ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->Core= Resources); + return EFI_SUCCESS; + } + if (SearchToken =3D=3D (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInf= o->SocResources) { + CmObject->Size =3D sizeof (PlatformRepo->CommonPlatRepoInfo->SocResour= ces); + CmObject->Data =3D (VOID*)&PlatformRepo->CommonPlatRepoInfo->SocResour= ces; + CmObject->Count =3D ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->SocR= esources); + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +/** Return a standard namespace object. + + @param [in] This Pointer to the Configuration Manager Protoc= ol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not fou= nd. +**/ +EFI_STATUS +EFIAPI +GetStandardNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + Status =3D EFI_SUCCESS; + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo =3D This->PlatRepoInfo; + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EStdObjCfgMgrInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->CmInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EStdObjAcpiTableList, + CmObjectId, + PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList, + (sizeof (PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList) / + sizeof (PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList[0])) + ); + default: { + Status =3D EFI_NOT_FOUND; + DEBUG (( + DEBUG_ERROR, + "ERROR: Object 0x%x. Status =3D %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** Return an ARM namespace object. + + @param [in] This Pointer to the Configuration Manager Protoc= ol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not fou= nd. +**/ +EFI_STATUS +EFIAPI +GetArmNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINT32 GicRedistCount; + UINT32 GicCpuCount; + UINT32 ProcHierarchyInfoCount; + + Status =3D EFI_SUCCESS; + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo =3D This->PlatRepoInfo; + + GicRedistCount =3D 1; + GicCpuCount =3D PLAT_CPU_COUNT; + ProcHierarchyInfoCount =3D PLAT_PROC_HIERARCHY_NODE_COUNT; + + Status =3D GetArmNameSpaceObjectPlat (This, CmObjectId, Token, CmObject); + + if (Status =3D=3D EFI_NOT_FOUND) { + + Status =3D EFI_SUCCESS; + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EArmObjBootArchInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->BootArchInfo, + 1 + ); + +#ifdef HEADLESS_PLATFORM + HANDLE_CM_OBJECT ( + EArmObjFixedFeatureFlags, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->FixedFeatureFlags, + 1 + ); +#endif + HANDLE_CM_OBJECT ( + EArmObjPowerManagementProfileInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->PmProfileInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjGenericTimerInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GenericTimerInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjPlatformGenericWatchdogInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->Watchdog, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjPlatformGTBlockInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GTBlockInfo, + (sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlockInfo) / + sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlockInfo[0])) + ); + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGTBlockTimerFrameInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo, + (sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo) / + sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo[0])= ), + Token, + GetGTBlockTimerFrameInfo + ); + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGicCInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicCInfo, + GicCpuCount, + Token, + GetGicCInfo + ); + HANDLE_CM_OBJECT ( + EArmObjGicDInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicDInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjGicRedistributorInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicRedistInfo, + GicRedistCount + ); + HANDLE_CM_OBJECT ( + EArmObjSerialConsolePortInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->SpcrSerialPort, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjSerialDebugPortInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->DbgSerialPort, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjProcHierarchyInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->ProcHierarchyInfo, + ProcHierarchyInfoCount + ); + HANDLE_CM_OBJECT ( + EArmObjProcNodeIdInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->ProcNodeIdInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjCacheInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->CacheInfo, + ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->CacheInfo) + ); + HANDLE_CM_OBJECT_SEARCH_PLAT_REPO ( + EArmObjCmRef, + CmObjectId, + Token, + GetCmObjRefs + ); + default: { + Status =3D EFI_NOT_FOUND; + DEBUG (( + DEBUG_INFO, + "INFO: Object 0x%x. Status =3D %r\n", + CmObjectId, + Status + )); + break; + } + }//switch + } + return Status; +} + +/** Return an OEM namespace object. + + @param [in] This Pointer to the Configuration Manager Protoc= ol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not fou= nd. +**/ +EFI_STATUS +EFIAPI +GetOemNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + default: { + Status =3D EFI_NOT_FOUND; + DEBUG (( + DEBUG_ERROR, + "ERROR: Object 0x%x. Status =3D %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** The GetObject function defines the interface implemented by the + Configuration Manager Protocol for returning the Configuration + Manager Objects. + + @param [in] This Pointer to the Configuration Manager Protoc= ol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not fou= nd. +**/ +EFI_STATUS +EFIAPI +MorelloPlatformGetObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + switch (GET_CM_NAMESPACE_ID (CmObjectId)) { + case EObjNameSpaceStandard: + Status =3D GetStandardNameSpaceObject (This, CmObjectId, Token, CmOb= ject); + break; + case EObjNameSpaceArm: + Status =3D GetArmNameSpaceObject (This, CmObjectId, Token, CmObject); + break; + case EObjNameSpaceOem: + Status =3D GetOemNameSpaceObject (This, CmObjectId, Token, CmObject); + break; + default: { + Status =3D EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "ERROR: Unknown Namespace Object =3D 0x%x. Status =3D %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** The SetObject function defines the interface implemented by the + Configuration Manager Protocol for updating the Configuration + Manager Objects. + + @param [in] This Pointer to the Configuration Manager Protoc= ol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in] CmObject Pointer to the Configuration Manager Object + descriptor describing the Object. + + @retval EFI_UNSUPPORTED This operation is not supported. +**/ +EFI_STATUS +EFIAPI +MorelloPlatformSetObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + return EFI_UNSUPPORTED; +} + +/** A structure describing the configuration manager protocol interface. +*/ +STATIC +CONST +EDKII_CONFIGURATION_MANAGER_PROTOCOL MorelloPlatformConfigManagerProtocol = =3D { + CREATE_REVISION(1,0), + MorelloPlatformGetObject, + MorelloPlatformSetObject, + &MorelloRepositoryInfo +}; + +/** + Entrypoint of Configuration Manager Dxe. + + @param ImageHandle + @param SystemTable + + @return EFI_SUCCESS + @return EFI_LOAD_ERROR + @return EFI_OUT_OF_RESOURCES + +**/ +EFI_STATUS +EFIAPI +ConfigurationManagerDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE * SystemTable + ) +{ + EFI_STATUS Status; + + // Initialize the Platform Configuration Repository before installing the + // Configuration Manager Protocol + Status =3D InitializePlatformRepository ( + MorelloPlatformConfigManagerProtocol.PlatRepoInfo + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "ERROR: Failed to initialize the Platform Configuration Repository."= \ + " Status =3D %r\n", + Status + )); + } + + Status =3D gBS->InstallProtocolInterface ( + &ImageHandle, + &gEdkiiConfigurationManagerProtocolGuid, + EFI_NATIVE_INTERFACE, + (VOID*)&MorelloPlatformConfigManagerProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "ERROR: Failed to get Install Configuration Manager Protocol." \ + " Status =3D %r\n", + Status + )); + goto error_handler; + } + +error_handler: + return Status; +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManager= Dxe/ConfigurationManagerFvp.c b/Platform/ARM/Morello/ConfigurationManager/C= onfigurationManagerDxe/ConfigurationManagerFvp.c new file mode 100644 index 000000000000..b50a9db220a2 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Con= figurationManagerFvp.c @@ -0,0 +1,531 @@ +/** @file + Configuration Manager Dxe + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "ConfigurationManagerFvp.h" +#include "Platform.h" + +EDKII_FVP_PLATFORM_REPOSITORY_INFO MorelloFvpRepositoryInfo =3D { + // ACPI Table List + { + // FADT Table + { + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt), + NULL + }, + // GTDT Table + { + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdGtdt), + NULL + }, + // MADT Table + { + EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt), + NULL + }, + // SPCR Table + { + EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSpcr), + NULL + }, + // DSDT Table + { + EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + 0, // Unused + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDsdt), + (EFI_ACPI_DESCRIPTION_HEADER*)dsdtfvp_aml_code + }, + // DBG2 Table + { + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2), + NULL + }, + // PPTT Table + { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt), + NULL + }, + // IORT Table + { + EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort), + NULL + }, + // PCI MCFG Table + { + EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDR= ESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg), + NULL, + }, + // SSDT table describing the PCI root complex + { + EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + 0, // Unused + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt), + (EFI_ACPI_DESCRIPTION_HEADER*)ssdtpcifvp_aml_code + }, + }, + + // GIC ITS + { + // GIC ITS - PCIe TCU + { + // The GIC ITS ID. + 0, + // The physical address for the Interrupt Translation Service + 0x30060000, + //Proximity Domain + 0 + }, + // GIC ITS - PCIe RC + { + // The GIC ITS ID. + 1, + // The physical address for the Interrupt Translation Service + 0x300A0000, + //Proximity Domain + 0 + }, + }, + + // ITS group node + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (ItsGroupInfo[0]), + // The number of ITS identifiers in the ITS node. + 1, + // Reference token for the ITS identifier array + REFERENCE_TOKEN_FVP (ItsIdentifierArray[0]) + }, + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (ItsGroupInfo[1]), + // The number of ITS identifiers in the ITS node. + 1, + // Reference token for the ITS identifier array + REFERENCE_TOKEN_FVP (ItsIdentifierArray[1]) + }, + }, + + // ITS identifier array + { + { + // The ITS Identifier + 0 + }, + { + // The ITS Identifier + 1 + }, + }, + + // SMMUv3 Node + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (SmmuV3Info[0]), + // Number of ID mappings + 2, + // Reference token for the ID mapping array + REFERENCE_TOKEN_FVP (DeviceIdMapping[0][0]), + // SMMU Base Address + 0x4F400000, + // SMMU flags + EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE, + // VATOS address + 0, + // Model + EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, + // GSIV of the Event interrupt if SPI based + 0x10B, + // PRI Interrupt if SPI based + 0, + // GERR interrupt if GSIV based + 0x10D, + // Sync interrupt if GSIV based + 0x10C, + // Proximity domain flag, ignored in this case + 0, + // Index into the array of ID mapping, ignored as SMMU + // control interrupts are GSIV based + 1 + }, + }, + + // Root Complex node info + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (RootComplexInfo[0]), + // Number of ID mappings + 1, + // Reference token for the ID mapping array + REFERENCE_TOKEN_FVP (DeviceIdMapping[1][0]), + + // Memory access properties : Cache coherent attributes + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + // Memory access properties : Allocation hints + 0, + // Memory access properties : Memory access flags + 0, + // ATS attributes + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED, + // PCI segment number + 0, + // Memory address size limit + 42 + }, + }, + + // Array of Device ID mappings + { + // DeviceIdMapping[0][0] - [0][1] + { + /* Mapping SMMUv3 -> ITS Group + */ + + // SMMUv3 device ID mapping + { + // Input base + 0x0, + // Number of input IDs + 0x0000FFFF, + // Output Base + 0x0, + // Output reference + REFERENCE_TOKEN_FVP (ItsGroupInfo[1]), + // Flags + 0 + }, + // SMMUv3 device ID mapping + { + // Input base + 0x0, + // Number of input IDs + 0x00000001, + // Output Base + 0x0, + // Output reference token for the IORT node + REFERENCE_TOKEN_FVP (ItsGroupInfo[0]), + // Flags + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE + } + }, + // DeviceIdMapping[1][0] + { + // Mapping for RootComplex -> SMMUv3 + + // Device ID mapping for Root complex node + { + // Input base + 0x0, + // Number of input IDs + 0x0000FFFF, + // Output Base + 0x0, + // Output reference + REFERENCE_TOKEN_FVP (SmmuV3Info[0]), + // Flags + 0 + }, + }, + }, + // PCI Configuration Space Info + { + // PCIe ECAM + { + FixedPcdGet64 (PcdPciExpressBaseAddress), // Base Address + 0x0, // Segment Group Number + FixedPcdGet32 (PcdPciBusMin), // Start Bus Number + FixedPcdGet32 (PcdPciBusMax) // End Bus Number + }, + }, +}; + +EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo =3D { + &CommonPlatformInfo, + &MorelloFvpRepositoryInfo +}; + +/** Return a device Id mapping array. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not fou= nd. +*/ +EFI_STATUS +EFIAPI +GetDeviceIdMappingArray ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo =3D This->PlatRepoInfo->FvpPlatRepoInfo; + + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Token =3D %p\n")); + + if (Token =3D=3D (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[0][0]) { + Count =3D 2; + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[0][0]\n")= ); + } else if (Token =3D=3D + (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[1][0]) { + Count =3D 1; + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[1][0]\n")= ); + } else { + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Not Found\n")); + return EFI_NOT_FOUND; + } + + CmObject->Data =3D (VOID*)Token; + CmObject->ObjectId =3D CmObjectId; + CmObject->Count =3D Count; + CmObject->Size =3D Count * sizeof (CM_ARM_ID_MAPPING); + + return EFI_SUCCESS; +} + +/** Return an ITS identifier array. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not fou= nd. +*/ +EFI_STATUS +EFIAPI +GetItsIdentifierArray ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + UINTN Index; + + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo =3D This->PlatRepoInfo->FvpPlatRepoInfo; + + Count =3D sizeof (PlatformRepo->ItsIdentifierArray) / + sizeof (PlatformRepo->ItsIdentifierArray[0]); + + for (Index =3D 0; Index < Count; Index++) { + if (Token =3D=3D (CM_OBJECT_TOKEN)&PlatformRepo->ItsIdentifierArray[In= dex]) { + CmObject->ObjectId =3D CmObjectId; + CmObject->Size =3D sizeof (PlatformRepo->ItsIdentifierArray[0]); + CmObject->Data =3D (VOID*)&PlatformRepo->ItsIdentifierArray[Index]; + CmObject->Count =3D 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return an ITS group info. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not fou= nd. +*/ +EFI_STATUS +EFIAPI +GetItsGroupInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + UINTN Index; + + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo =3D This->PlatRepoInfo->FvpPlatRepoInfo; + + Count =3D sizeof (PlatformRepo->ItsGroupInfo) / + sizeof (PlatformRepo->ItsGroupInfo[0]); + + for (Index =3D 0; Index < Count; Index++) { + if (Token =3D=3D (CM_OBJECT_TOKEN)&PlatformRepo->ItsGroupInfo[Index]) { + CmObject->ObjectId =3D CmObjectId; + CmObject->Size =3D sizeof (PlatformRepo->ItsGroupInfo[0]); + CmObject->Data =3D (VOID*)&PlatformRepo->ItsGroupInfo[Index]; + CmObject->Count =3D 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return an ARM namespace object. + + @param [in] This Pointer to the Configuration Manager Protoc= ol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not fou= nd. +**/ +EFI_STATUS +EFIAPI +GetArmNameSpaceObjectPlat ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + Status =3D EFI_SUCCESS; + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo =3D This->PlatRepoInfo->FvpPlatRepoInfo; + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EArmObjGicItsInfo, + CmObjectId, + PlatformRepo->GicItsInfo, + (sizeof (PlatformRepo->GicItsInfo) / + sizeof (PlatformRepo->GicItsInfo[0])) + ); + + HANDLE_CM_OBJECT ( + EArmObjSmmuV3, + CmObjectId, + PlatformRepo->SmmuV3Info[0], + 1 + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjItsGroup, + CmObjectId, + PlatformRepo->ItsGroupInfo, + (sizeof (PlatformRepo->ItsGroupInfo) / + sizeof (PlatformRepo->ItsGroupInfo[0])), + Token, + GetItsGroupInfo + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGicItsIdentifierArray, + CmObjectId, + PlatformRepo->ItsIdentifierArray, + (sizeof (PlatformRepo->ItsIdentifierArray) / + sizeof (PlatformRepo->ItsIdentifierArray[0])), + Token, + GetItsIdentifierArray + ); + + HANDLE_CM_OBJECT ( + EArmObjRootComplex, + CmObjectId, + PlatformRepo->RootComplexInfo[0], + 1 + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjIdMappingArray, + CmObjectId, + PlatformRepo->DeviceIdMapping, + (sizeof (PlatformRepo->DeviceIdMapping) / + sizeof (PlatformRepo->DeviceIdMapping[0][0])), + Token, + GetDeviceIdMappingArray + ); + + HANDLE_CM_OBJECT ( + EArmObjPciConfigSpaceInfo, + CmObjectId, + PlatformRepo->PciConfigInfo[0], + 1 + ); + default: { + Status =3D EFI_NOT_FOUND; + break; + } + }//switch + return Status; +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManager= Dxe/AslTables/DsdtFvp.asl b/Platform/ARM/Morello/ConfigurationManager/Confi= gurationManagerDxe/AslTables/DsdtFvp.asl new file mode 100644 index 000000000000..f048f81d0646 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Asl= Tables/DsdtFvp.asl @@ -0,0 +1,114 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2021, ARM Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "ConfigurationManager.h" + +DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "MORELLO", CFG_MGR_OEM_RE= VISION) { + Scope(_SB) { + Device(CP00) { // Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + Name(_STA, 0xF) + } + + Device(CP01) { // Cluster 0, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 1) + Name(_STA, 0xF) + } + + Device(CP02) { // Cluster 1, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 2) + Name(_STA, 0xF) + } + + Device(CP03) { // Cluster 1, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 3) + Name(_STA, 0xF) + } + + // UART PL011 + Device(COM0) { + Name(_HID, "ARMH0011") + Name(_CID, "ARMH0011") + Name(_UID, 0) + + Method(_STA) { + Return(0xF) + } + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x2A400000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 } + }) + } + + // VIRTIO DISK + Device(VR00) { + Name(_HID, "LNRO0005") + Name(_UID, 0) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed( + ReadWrite, + FixedPcdGet32(PcdVirtioBlkBaseAddress), + FixedPcdGet32(PcdVirtioBlkSize) + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { + FixedPcdGet32(PcdVirtioBlkInterrupt) + } + }) + } + + // VIRTIO NET + Device(VR01) { + Name(_HID, "LNRO0005") + Name(_UID, 1) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C180000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 134 } + }) + } + + // VIRTIO RANDOM + Device(VR02) { + Name(_HID, "LNRO0005") + Name(_UID, 2) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C190000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 133 } + }) + } + + // VIRTIO P9 Device + Device(VR03) { + Name(_HID, "LNRO0005") + Name(_UID, 3) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C1A0000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 135 } + }) + } + + // SMC91X + Device(NET0) { + Name(_HID, "LNRO0003") + Name(_UID, 0) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1D100000, 0x00001000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 130 } + }) + } + } // Scope(_SB) +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManager= Dxe/AslTables/SsdtPciFvp.asl b/Platform/ARM/Morello/ConfigurationManager/Co= nfigurationManagerDxe/AslTables/SsdtPciFvp.asl new file mode 100644 index 000000000000..bdf2f06aed69 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Asl= Tables/SsdtPciFvp.asl @@ -0,0 +1,130 @@ +/** @file + Secondary System Description Table (SSDT) + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "ConfigurationManager.h" + +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \ + Device(Link_Name) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, Unique_Id) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \ + }) \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ +} + +#define PRT_ENTRY(Address, Pin, Link) = \ + Package (4) { = \ + Address, /* uses the same format as _ADR */ = \ + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC,= 3-INTD) */ \ + Link, /* Interrupt allocated via Link device */ = \ + Zero /* global system interrupt number (no used) */ = \ +} + +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) // D= evice 0 for Bridge. + +DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "MORELLO", + CFG_MGR_OEM_REVISION) +{ + Scope (_SB) { + // + // PCI Root Complex + // + LNK_DEVICE(1, LNKA, 201) + LNK_DEVICE(2, LNKB, 202) + LNK_DEVICE(3, LNKC, 203) + LNK_DEVICE(4, LNKD, 204) + + // PCI Root Complex + Device(PCI0) { + Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_CCA, 1) // Cache Coherency Attribute + + // Root Complex 0 + Device (RP0) { + Name(_ADR, 0xF0000000) // Dev 0, Func 0 + } + + // PCI Routing Table + Name(_PRT, Package() { + ROOT_PRT_ENTRY(0, LNKA), // INTA + ROOT_PRT_ENTRY(1, LNKB), // INTB + ROOT_PRT_ENTRY(2, LNKC), // INTC + ROOT_PRT_ENTRY(3, LNKD), // INTD + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assig= ned to this root + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + 0, // AddressGranularity + FixedPcdGet32 (PcdPciBusMin), // AddressMinimum - = Minimum Bus Number + FixedPcdGet32 (PcdPciBusMax), // AddressMaximum - = Maximum Bus Number + 0, // AddressTranslatio= n - Set to 0 + FixedPcdGet32 (PcdPciBusCount) // RangeLength - Num= ber of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + FixedPcdGet32 (PcdPciMmio32Base), // Min Base Address + FixedPcdGet32 (PcdPciMmio32MaxBase), // Max Base Address + FixedPcdGet32 (PcdPciMmio32Translation), // Translate + FixedPcdGet32 (PcdPciMmio32Size) // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + FixedPcdGet64 (PcdPciMmio64Base), // Min Base Address + FixedPcdGet64 (PcdPciMmio64MaxBase), // Max Base Address + FixedPcdGet64 (PcdPciMmio64Translation), // Translate + FixedPcdGet64 (PcdPciMmio64Size) // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + FixedPcdGet32 (PcdPciIoBase), // Min Base Address + FixedPcdGet32 (PcdPciIoMaxBase), // Max Base Address + FixedPcdGet32 (PcdPciIoTranslation), // Translate + FixedPcdGet32 (PcdPciIoSize), // Length + , + , + , + TypeTranslation + ) + }) // Name(RBUF) + Return (RBUF) + } // Method (_CRS) + } // Device (PCI0) + } // _SB +} // DB --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72159): https://edk2.groups.io/g/devel/message/72159 Mute This Topic: https://groups.io/mt/80885830/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 03:20:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72160+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72160+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1614196168; cv=none; d=zohomail.com; s=zohoarc; b=jTcA+Uv0fhuxmOTipWB/fT4EpmHKbONIJXFaOTDty8yb3p7aW4JXRRRXZZwa8tc0GCSs0dCKnTmE6NnyhditLT+u3ZO/jjaMC4x1j1JnyRFZRDFNeKdR5xSQIVK6WX2zqIMus7eeHQ1cwwh6Hu+S+C3u2jHCIt22HWdC/07ethQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614196168; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=NRgc/hxn4p7dmvzt/R7lAO8jVJkKhwkmF99Q30mvCk4=; b=bgoea9rqdTd2Q8CataSrxRxcB+GI/XfySnZ+gnlCSGO9GAXlGuDjU0zj5apS/sRcRUKalK5Frk63CLeBSF1huG9YrhEYPDUPT1GvIN9tKP44oiXMhxv6r2U7fwQxgff6YEo/pfkMNAv1h0Z0pp35TmSZPKMadQE9EnS0zOC/rO8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72160+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1614196168471330.42127569339675; Wed, 24 Feb 2021 11:49:28 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id kNq3YY1788612x0f0u4z9SkM; Wed, 24 Feb 2021 11:49:27 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.6573.1614172363537515648 for ; Wed, 24 Feb 2021 05:12:43 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3A3171FB; Wed, 24 Feb 2021 05:12:43 -0800 (PST) X-Received: from usa.arm.com (a074744.blr.arm.com [10.162.17.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BEA863F70D; Wed, 24 Feb 2021 05:12:41 -0800 (PST) From: Chandni Cherukuri To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 5/5] Platform/ARM/Morello: Add initial support for Morello Platform Date: Wed, 24 Feb 2021 18:42:24 +0530 Message-Id: <20210224131224.11481-6-chandni.cherukuri@arm.com> In-Reply-To: <20210224131224.11481-1-chandni.cherukuri@arm.com> References: <20210224131224.11481-1-chandni.cherukuri@arm.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chandni.cherukuri@arm.com X-Gm-Message-State: Y4PD1WXppot4ZhX2WjEEmxE0x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1614196167; bh=yR9hJ8TL2lvcuEsjmNMP6BuxJu+hlkSfo5YNujp81QY=; h=Cc:Date:From:Reply-To:Subject:To; b=ZgJKJqQj5iWG+pwAaNzgpxaNf5/u1xPJNXLbzqCf1RGSAW7A16XhGHFBjtiCcTDDIDT 8EKQ3NHAGivM2xf7TqkDNTFI3JyyQq5zA5yesz0dCbwO3HE3JGjYMIQjgcQB+lidYgGBm W7ecoFrESP+VjG2YxbDyd18VfHMRurxugZQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Anurag Koul This patch adds the initial support for Morello FVP platform. Co-authored-by: Chandni Cherukuri Signed-off-by: Chandni Cherukuri --- Platform/ARM/Morello/MorelloPlatform.dec | 59 ++++ Platform/ARM/Morello/MorelloPlatform.dsc.inc | 235 +++++++++++++++ Platform/ARM/Morello/MorelloPlatformFvp.dsc | 60 ++++ Platform/ARM/Morello/MorelloPlatformFvp.fdf | 302 ++++++++++++++++++++ 4 files changed, 656 insertions(+) diff --git a/Platform/ARM/Morello/MorelloPlatform.dec b/Platform/ARM/Morell= o/MorelloPlatform.dec new file mode 100644 index 000000000000..5bf9f5f12005 --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatform.dec @@ -0,0 +1,59 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + PACKAGE_NAME =3D Morello + PACKAGE_GUID =3D F09A2C11-7864-4B1D-869E-03EE2AD79288 + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package + +[Guids.common] + gArmMorelloTokenSpaceGuid =3D { 0x0A8C3A78, 0xA56F, 0x4788, { 0x83, 0xB= 4, 0xCD, 0x29, 0x62, 0x96, 0x77, 0x51 } } + +[PcdsFixedAtBuild] + # Ramdisk + gArmMorelloTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 + gArmMorelloTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 + + # Secondary DDR memory + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000003 + + # Virtio Block device + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x00000000|UINT32|0x00= 000004 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize|0x00000000|UINT32|0x00000005 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt|0x00000000|UINT32|0x0000= 0006 + + # PCIe + gArmMorelloTokenSpaceGuid.PcdPciBusMin|0|UINT32|0x00000009 + gArmMorelloTokenSpaceGuid.PcdPciBusMax|15|UINT32|0x0000000A + gArmMorelloTokenSpaceGuid.PcdPciBusCount|16|UINT32|0x0000000B + gArmMorelloTokenSpaceGuid.PcdPciIoBase|0x0|UINT32|0x0000000C + gArmMorelloTokenSpaceGuid.PcdPciIoSize|0x00800000|UINT32|0x0000000D + gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase|0x007FFFFF|UINT32|0x0000000E + gArmMorelloTokenSpaceGuid.PcdPciIoTranslation|0x67800000|UINT32|0x000000= 0F + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base|0x60000000|UINT32|0x00000010 + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size|0x07800000|UINT32|0x00000011 + gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase|0x677FFFFF|UINT32|0x000000= 12 + gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT32|0x00000013 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base|0x900000000|UINT64|0x00000014 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size|0x2000000000|UINT64|0x00000015 + gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase|0x28FFFFFFFF|UINT64|0x0000= 0016 + gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000017 + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000|UINT64|0x0= 0000018 + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|FALSE|BOOLEAN|0x00000007 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000008 diff --git a/Platform/ARM/Morello/MorelloPlatform.dsc.inc b/Platform/ARM/Mo= rello/MorelloPlatform.dsc.inc new file mode 100644 index 000000000000..0715d5e24a6b --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatform.dsc.inc @@ -0,0 +1,235 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmPlatformLib|Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf + BasePathLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + # Ramdisk Support + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + +[LibraryClasses.common.SEC] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + +[LibraryClasses.common.PEI_CORE, LibraryClasses.common.PEIM] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf + +[LibraryClasses.common.PEI_CORE] + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + +[LibraryClasses.common.PEIM] + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[LibraryClasses.common.DXE_CORE] + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +[LibraryClasses.common.DXE_DRIVER] + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf +!if $(TARGET) !=3D RELEASE + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibS= erialPort.inf +!endif + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION= , LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVE= R] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0 + + # System Memory (2GB - 16MB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 + + # Secondary DDR memory + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base|0x8080000000 + + # GIC Base Addresses + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000 + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 + + # PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2A400000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|50000000 + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95 + + # PL011 Serial Debug UART (DBG2) + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|gEfiMdeModulePkgToke= nSpaceGuid.PcdSerialRegisterBase + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|gEfiMdePkgTokenSpace= Guid.PcdUartDefaultBaudRate + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000 + + # SBSA Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93 + + # PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C100000 + + # ARM Architectural Timer Frequency + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000 + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1000 + + # ARM Cores and Clusters + gArmPlatformTokenSpaceGuid.PcdCoreCount|2 + gArmPlatformTokenSpaceGuid.PcdClusterCount|2 + + # ACPI Table Version + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + + # Runtime Variable storage + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + + # RAM Disk + gArmMorelloTokenSpaceGuid.PcdRamDiskBase|0x88000000 + gArmMorelloTokenSpaceGuid.PcdRamDiskSize|0x18000000 + + # PCIe + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000 + +[PcdsDynamicHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|0 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # PEI Phase modules + ArmPkg/Drivers/CpuPei/CpuPei.inf + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } + + # DXE + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + } + + # Architectural Protocols + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + + # ACPI Support + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # FAT filesystem + GPT/MBR partitioning + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # Bds + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + + # RAM Disk + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # Required by PCI + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # PCI Support + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F + } + + # AHCI Support + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # SATA Controller + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.dsc b/Platform/ARM/Mor= ello/MorelloPlatformFvp.dsc new file mode 100644 index 000000000000..04a966c33f8d --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatformFvp.dsc @@ -0,0 +1,60 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D morellofvp + PLATFORM_GUID =3D CB995FFD-EAEF-4d5E-8A4B-3213B39CD14A + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001B +!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY =3D $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) +!endif + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D NOOPT|DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/ARM/Morello/MorelloPlatformF= vp.fdf + BUILD_NUMBER =3D 1 + + # Network definition + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + +!include Platform/ARM/Morello/MorelloPlatform.dsc.inc +!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc +!include DynamicTablesPkg/DynamicTables.dsc.inc +!include Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp= .dsc.inc + +[LibraryClasses.common] + # Virtio Support + VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf + VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDevice= Lib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + +[LibraryClasses.common.DXE_DRIVER] + PciHostBridgeLib|Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBr= idgeLibFvp.inf + +[PcdsFeatureFlag.common] + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|TRUE + +[PcdsFixedAtBuild.common] + # Virtio Disk + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x1C170000 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize|0x200 + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt|128 + +[Components.common] + OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + + # Platform driver + Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.fdf b/Platform/ARM/Mor= ello/MorelloPlatformFvp.fdf new file mode 100644 index 000000000000..29e7e099cc7b --- /dev/null +++ b/Platform/ARM/Morello/MorelloPlatformFvp.fdf @@ -0,0 +1,302 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.BL33_AP_UEFI] +BaseAddress =3D 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The ba= se address of the Firmware in NOR Flash. +Size =3D 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The si= ze in bytes of the FLASH Device +ErasePolarity =3D 1 + +# This one is tricky, it must be: BlockSize * NumBlocks =3D Size +BlockSize =3D 0x00001000 +NumBlocks =3D 0x200 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of +# different images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) +# followed by the pipe "|" character, followed by the size of the region, = also +# in hex with the leading "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### + +0x00000000|0x00200000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a +# flash device file. This section also defines order the components and mo= dules +# are positioned within the image. The [FV] section consists of define +# statements, set statements and module statements. +# +##########################################################################= ###### + +[FV.FvMain] +BlockSize =3D 0x40 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 8 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # PI DXE Drivers producing Architectural Protocols (EFI Services) + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + # ACPI Support + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # Configuration Manager + INF Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Co= nfigurationManagerDxeFvp.inf + + # Dynamic Table fdf + !include DynamicTablesPkg/DynamicTables.fdf.inc + + # Multiple Console IO support + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # Virtio Block Device support + INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + + # FAT filesystem + GPT/MBR partitioning + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + + # FV FileSystem + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.i= nf + INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # UEFI applications + INF ShellPkg/Application/Shell/Shell.inf + + # Platform driver + INF Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf + + # Bds + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + # Required by PCI + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # PCI Support + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # AHCI Support + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # SATA Controller + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 8 +BlockSize =3D 0x1000 +NumBlocks =3D 0x200 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } + + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + + +##########################################################################= ## +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section = # +##########################################################################= ## +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER =3D $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING=3D"$(MODULE_NAME)" Optional +# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N= UMBER) +# } +# } +# } +# +##########################################################################= ## + +# +# These SEC rules are used for ArmPlatformPkg/PrePeiCore module. +# ArmPlatformPkg/PrePeiCore is declared as a SEC module to make GenFv patch +# the UEFI Firmware to jump to ArmPlatformPkg/PrePeiCore entrypoint +# + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR= UE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + UI STRING =3D"$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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