From nobody Mon Apr 29 07:32:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72083+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72083+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1614090405; cv=none; d=zohomail.com; s=zohoarc; b=hAxzerIjXfyQiz5/lEudoUW3NEryuKK50n+Bvi+NRR/5J3wU2odOtHbieJJ0YC+NPbt/1hQMP6XpaN3vrWS1GqCA8E0/eEFZnZwB9kFj6vVsfIqO22PCFOyE8MZ49zA2DTesW+Zo/kc2LfvJbrCC6TEVw0800CWWB9ofOwXicIw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614090405; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=+WilQX7CCot+zuTSo2HIXG9rYnErIIArxiB3dRVnHtg=; b=OPEvUmDI+rBTQsyPWGVuGcSiGzkQFIesStAqoxpGeTfARC/HfCYFf1iV089Q9Y2sNrA5h5/bzDxtxfgBowCMnjUwCHKcmD+NrdoJ9JqzjzCV43DHyaM+hWxlI0n2tWHU05dLGETpjxFQO5Gxmpr9wAUqsdxcG0FtnODMXGMnL14= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72083+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161409040459297.31010013091986; Tue, 23 Feb 2021 06:26:44 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id gt14YY1788612xc9NppeVxHB; Tue, 23 Feb 2021 06:26:44 -0800 X-Received: from mail-il1-f178.google.com (mail-il1-f178.google.com [209.85.166.178]) by mx.groups.io with SMTP id smtpd.web08.10312.1614090403760667718 for ; Tue, 23 Feb 2021 06:26:43 -0800 X-Received: by mail-il1-f178.google.com with SMTP id q9so14238528ilo.1 for ; Tue, 23 Feb 2021 06:26:43 -0800 (PST) X-Gm-Message-State: y2nqY90XjpLBfetGGXpvY0q4x1787277AA= X-Google-Smtp-Source: ABdhPJzEseMvXsyZYUlX3uNGK81QCvwWCqQSokLRcI44K1m3fCSdtxAcqCHjRseWJocqEvxPfpWDhQ== X-Received: by 2002:a92:d447:: with SMTP id r7mr19651675ilm.272.1614090402808; Tue, 23 Feb 2021 06:26:42 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id b9sm15391541ilo.41.2021.02.23.06.26.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 06:26:42 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Radoslaw Biernacki Subject: [edk2-devel] [edk2-platforms PATCH v4 1/4] SbsaQemu: Add FdtHelperLib Date: Tue, 23 Feb 2021 07:26:32 -0700 Message-Id: <20210223142635.8807-2-rebecca@nuviainc.com> In-Reply-To: <20210223142635.8807-1-rebecca@nuviainc.com> References: <20210223142635.8807-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1614090404; bh=omyUBo9rB1M37fkowVOPotQsknCHBdnIAIwcoE55oDM=; h=Cc:Date:From:Reply-To:Subject:To; b=d+Xw4s6HhD9nCF534evvqk1dZ8LYnTaPZb9b4FvXZt83Z81RwTqj3r4yzM7CKWWvbsx Qx2DbnH6najq3v45XB4dQG4q8kCxLot7MdTwY3kj89rG2wZjYRxaVcet/anoQPZeYu0Gf aMQySTxH178ypKjj7bdSdylhVATcCRRWI5E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The CountCpusFromFdt function is now used in two places. Create FdtHelperLib for this and similar functions. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 + Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 5 +- Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h | 24 +++++= +++ Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c | 62 +++++= +++++++++++++++ Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf | 28 +++++= ++++ 5 files changed, 120 insertions(+), 1 deletion(-) diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/S= bsaQemu.dsc index f6af3f9111ee..8faad3eda217 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -121,6 +121,8 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE # ARM PL011 UART Driver PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf =20 + FdtHelperLib|Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf + # Debug Support PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index fb7c1835c3d7..7bf60cd2ded1 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -487,9 +487,12 @@ InitializeSbsaQemuAcpiDxe ( { EFI_STATUS Status; EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + UINT32 NumCores; =20 // Parse the device tree and get the number of CPUs - CountCpusFromFdt (); + NumCores =3D FdtHelperCountCpus (); + Status =3D PcdSet32S (PcdCoreCount, NumCores); + ASSERT_RETURN_ERROR (Status); =20 // Check if ACPI Table Protocol has been installed Status =3D gBS->LocateProtocol ( diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h b/Silicon= /Qemu/SbsaQemu/Include/Library/FdtHelperLib.h new file mode 100644 index 000000000000..e9e7281c1342 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h @@ -0,0 +1,24 @@ +/** @file +* FdtHelperLib.h +* +* Copyright (c) 2021, NUVIA Inc. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef FDT_HELPER_LIB_ +#define FDT_HELPER_LIB_ + +/** Walks through the Device Tree created by Qemu and counts the number + of CPUs present in it. + + @return The number of CPUs present. +**/ +EFIAPI +UINT32 +FdtHelperCountCpus ( + VOID + ); + +#endif /* FDT_HELPER_LIB_ */ diff --git a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c b/Si= licon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c new file mode 100644 index 000000000000..411f035ee7d8 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c @@ -0,0 +1,62 @@ +/** @file +* FdtHelperLib.c +* +* Copyright (c) 2021, NUVIA Inc. All rights reserved. +* Copyright (c) 2020, Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include + +/** Walks through the Device Tree created by Qemu and counts the number + of CPUs present in it. + + @return The number of CPUs present. +**/ +EFIAPI +UINT32 +FdtHelperCountCpus ( + VOID + ) +{ + VOID *DeviceTreeBase; + INT32 Node; + INT32 Prev; + INT32 CpuNode; + UINT32 CpuCount; + + DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); + ASSERT (DeviceTreeBase !=3D NULL); + + // Make sure we have a valid device tree blob + ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); + + CpuNode =3D fdt_path_offset (DeviceTreeBase, "/cpus"); + if (CpuNode <=3D 0) { + DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in device tree\n")); + return 0; + } + + CpuCount =3D 0; + + // Walk through /cpus node and count the number of subnodes. + // The count of these subnodes corresponds to the number of + // CPUs created by Qemu. + Prev =3D fdt_first_subnode (DeviceTreeBase, CpuNode); + while (1) { + CpuCount++; + Node =3D fdt_next_subnode (DeviceTreeBase, Prev); + if (Node < 0) { + break; + } + Prev =3D Node; + } + + return CpuCount; +} diff --git a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf b/= Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf new file mode 100644 index 000000000000..d84c16f888d1 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf @@ -0,0 +1,28 @@ +#/** @file +# +# Component description file for FdtHelperLib module +# +# Copyright (c) 2021, NUVIA Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D FdtHelperLib + FILE_GUID =3D 34e4396f-c2fc-4f9e-ad58-0f98e99e3875 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FdtHelperLib + +[Sources.common] + FdtHelperLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/Qemu/SbsaQemu/SbsaQemu.dec + +[FixedPcd] + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id b9sm15391541ilo.41.2021.02.23.06.26.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 06:26:43 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Radoslaw Biernacki Subject: [edk2-devel] [edk2-platforms PATCH v4 2/4] SbsaQemu: Update SbsaQemuAcpiDxe to use FdtHelperLib Date: Tue, 23 Feb 2021 07:26:33 -0700 Message-Id: <20210223142635.8807-3-rebecca@nuviainc.com> In-Reply-To: <20210223142635.8807-1-rebecca@nuviainc.com> References: <20210223142635.8807-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1614090405; bh=i3voMzzmTc4fL5WNPPZ8i3/JU0dGQtAmJSTmJulXs3w=; h=Cc:Date:From:Reply-To:Subject:To; b=kn3ewSKD9PggN2A2RMcXwBtxuPxof86nQ2x1OrjWfBc94Jh+V4UfWJF7jLWBIVjwY/B p0nUsBeIeimz5guVC8BDWLr7k/mAeZQ9Xeb+SVgqbN7ZFYgfVihVjWs9/s1Uz0JNQzuIw eZF0woIfDG5bf7WeSXQBtoHjYJFIoT44Unc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Use FdtHelperCountCpus from FdtHelperLib. Signed-off-by: Rebecca Cran --- Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 50 +--= ----------------- Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 1 + 2 files changed, 2 insertions(+), 49 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 7bf60cd2ded1..037c7cff4c18 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -25,55 +26,6 @@ STATIC INT32 FdtFirstCpuOffset; STATIC INT32 FdtCpuNodeSize; =20 -/* - * A function that walks through the Device Tree created - * by Qemu and counts the number of CPUs present in it. - */ -STATIC -VOID -CountCpusFromFdt ( - VOID -) -{ - VOID *DeviceTreeBase; - INT32 Node, Prev; - RETURN_STATUS PcdStatus; - INT32 CpuNode; - INT32 CpuCount; - - DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); - ASSERT (DeviceTreeBase !=3D NULL); - - // Make sure we have a valid device tree blob - ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); - - CpuNode =3D fdt_path_offset (DeviceTreeBase, "/cpus"); - if (CpuNode <=3D 0) { - DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in device tree\n")); - return; - } - - CpuCount =3D 0; - - // Walk through /cpus node and count the number of subnodes. - // The count of these subnodes corresponds to the number of - // CPUs created by Qemu. - Prev =3D fdt_first_subnode (DeviceTreeBase, CpuNode); - FdtFirstCpuOffset =3D Prev; - while (1) { - CpuCount++; - Node =3D fdt_next_subnode (DeviceTreeBase, Prev); - if (Node < 0) { - break; - } - FdtCpuNodeSize =3D Node - Prev; - Prev =3D Node; - } - - PcdStatus =3D PcdSet32S (PcdCoreCount, CpuCount); - ASSERT_RETURN_ERROR (PcdStatus); -} - /* * Get MPIDR from device tree passed by Qemu */ diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf index 127eef029f3c..a58ebfaf76d5 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf @@ -34,6 +34,7 @@ BaseLib DebugLib DxeServicesLib + FdtHelperLib FdtLib PcdLib PrintLib --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id b9sm15391541ilo.41.2021.02.23.06.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 06:26:44 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Radoslaw Biernacki Subject: [edk2-devel] [edk2-platforms PATCH v4 3/4] Platform/Qemu/SbsaQemu: Add SMBIOS tables Date: Tue, 23 Feb 2021 07:26:34 -0700 Message-Id: <20210223142635.8807-4-rebecca@nuviainc.com> In-Reply-To: <20210223142635.8807-1-rebecca@nuviainc.com> References: <20210223142635.8807-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1614090406; bh=h457g/94KdEZe0MUZkgTqcJ/J//+DCt41B5sp8Vt4V0=; h=Cc:Date:From:Reply-To:Subject:To; b=Vz1Dl6hiuExdh6e5J7UOLcJTSYY/GHFpYDK/S3yvZGCx40nZAAF6+x4Nm35az79FtVx 5g+c6+GSoCnKkZm9fy0k5t1yNxhqSWRMKEKao6i/8Wbgap0V+vGC51S9C3wS7pndBDg/J c/Dr6RR7dKSYhaD+t7yKB7H/juobgV8ztHY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" o Add SMBIOS 3.4.0 tables using ArmPkg/Universal/Smbios. o Bump the PcdSmbiosVersion PCD from 0x300 to 0x304 to indicate support for SMBIOS 3.4.0, as is required by SBBR. o Add an implementation of OemMiscLib that provides the system information. The serial numbers, asset tags etc. are currently all fixed strings, to allow fwts to pass without errors. o Add SMBIOS PCDs to identify the platform. The processor serial number, asset tag and part number are populated because otherwise fwts reports errors. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm --- Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 242 ++++++++++++++++++++ Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 53 +++++ Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 48 +++- Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 7 + Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 18 ++ 5 files changed, 367 insertions(+), 1 deletion(-) diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c b/Platform/Qemu= /SbsaQemu/OemMiscLib/OemMiscLib.c new file mode 100644 index 000000000000..11340788aadf --- /dev/null +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c @@ -0,0 +1,242 @@ +/** @file +* OemMiscLib.c +* +* Copyright (c) 2021, NUVIA Inc. All rights reserved. +* Copyright (c) 2020, Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** Returns whether the specified processor is present or not. + + @param ProcessorIndex The processor index to check. + + @return TRUE if the processor is present, FALSE otherwise. +**/ +BOOLEAN +EFIAPI +OemIsProcessorPresent ( + UINTN ProcessorIndex + ) +{ + if (ProcessorIndex < FdtHelperCountCpus ()) { + return TRUE; + } + + return FALSE; +} + +/** Gets the CPU frequency of the specified processor. + + @param ProcessorIndex Index of the processor to get the frequency for. + + @return CPU frequency in Hz +**/ +UINTN +EFIAPI +OemGetCpuFreq ( + UINT8 ProcessorIndex + ) +{ + return 2000000000; // 2 GHz +} + +/** Gets information about the specified processor and stores it in + the structures provided. + + @param ProcessorIndex Index of the processor to get the information for. + @param ProcessorStatus Processor status. + @param ProcessorCharacteristics Processor characteritics. + @param MiscProcessorData Miscellaneous processor information. + + @return TRUE on success, FALSE on failure. +**/ +BOOLEAN +EFIAPI +OemGetProcessorInformation ( + IN UINTN ProcessorIndex, + IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus, + IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics, + IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData + ) +{ + UINT16 ProcessorCount; + + ProcessorCount =3D FdtHelperCountCpus (); + + if (ProcessorIndex < ProcessorCount) { + ProcessorStatus->Bits.CpuStatus =3D 1; // CPU enabled + ProcessorStatus->Bits.Reserved1 =3D 0; + ProcessorStatus->Bits.SocketPopulated =3D 1; + ProcessorStatus->Bits.Reserved2 =3D 0; + } else { + ProcessorStatus->Bits.CpuStatus =3D 0; // CPU disabled + ProcessorStatus->Bits.Reserved1 =3D 0; + ProcessorStatus->Bits.SocketPopulated =3D 0; + ProcessorStatus->Bits.Reserved2 =3D 0; + } + + ProcessorCharacteristics->ProcessorReserved1 =3D 0; + ProcessorCharacteristics->ProcessorUnknown =3D 0; + ProcessorCharacteristics->Processor64BitCapable =3D 1; + ProcessorCharacteristics->ProcessorMultiCore =3D 0; + ProcessorCharacteristics->ProcessorHardwareThread =3D 0; + ProcessorCharacteristics->ProcessorExecuteProtection =3D 1; + ProcessorCharacteristics->ProcessorEnhancedVirtualization =3D 0; + ProcessorCharacteristics->ProcessorPowerPerformanceCtrl =3D 0; + ProcessorCharacteristics->Processor128BitCapable =3D 0; + ProcessorCharacteristics->ProcessorArm64SocId =3D 1; + ProcessorCharacteristics->ProcessorReserved2 =3D 0; + + MiscProcessorData->CurrentSpeed =3D 2000; + MiscProcessorData->MaxSpeed =3D 2000; + MiscProcessorData->CoreCount =3D 1; + MiscProcessorData->CoresEnabled =3D 1; + MiscProcessorData->ThreadCount =3D 1; + + return TRUE; +} + +/** Gets the maximum number of processors supported by the platform. + + @return The maximum number of processors. +**/ +UINT8 +EFIAPI +OemGetMaxProcessors ( + VOID + ) +{ + return FdtHelperCountCpus (); +} + +/** Gets information about the cache at the specified cache level. + + @param ProcessorIndex The processor to get information for. + @param CacheLevel The cache level to get information for. + @param DataCache Whether the cache is a data cache. + @param UnifiedCache Whether the cache is a unified cache. + @param SmbiosCacheTable The SMBIOS Type7 cache information structure. + + @return TRUE on success, FALSE on failure. +**/ +BOOLEAN +EFIAPI +OemGetCacheInformation ( + IN UINT8 ProcessorIndex, + IN UINT8 CacheLevel, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache, + IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable + ) +{ + SmbiosCacheTable->CacheConfiguration =3D CacheLevel - 1; + + if (CacheLevel =3D=3D 1 && !DataCache && !UnifiedCache) { + // Unknown operational mode + SmbiosCacheTable->CacheConfiguration |=3D (3 << 8); + } else { + // Write back operational mode + SmbiosCacheTable->CacheConfiguration |=3D (1 << 8); + } + + return TRUE; +} + +/** Gets the type of chassis for the system. + + @retval The type of the chassis. +**/ +MISC_CHASSIS_TYPE +EFIAPI +OemGetChassisType ( + VOID + ) +{ + return MiscChassisTypeMainServerChassis; +} + +/** Updates the HII string for the specified field. + + @param HiiHandle The HII handle. + @param TokenToUpdate The string to update. + @param Field The field to get information about. +**/ +VOID +EFIAPI +OemUpdateSmbiosInfo ( + IN EFI_HII_HANDLE HiiHandle, + IN EFI_STRING_ID TokenToUpdate, + IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field + ) +{ + CHAR16 *String; + + // These values are fixed for now, but should be configurable via + // something like an emulated SCP. + switch (Field) { + case SystemManufacturerType01: + String =3D (CHAR16*)PcdGetPtr (PcdSystemManufacturer); + break; + case SerialNumType01: + String =3D (CHAR16*)PcdGetPtr (PcdSystemSerialNumber); + break; + case SkuNumberType01: + String =3D (CHAR16*)PcdGetPtr (PcdSystemSKU); + break; + case FamilyType01: + String =3D (CHAR16*)PcdGetPtr (PcdSystemFamily); + break; + case AssertTagType02: + String =3D (CHAR16*)PcdGetPtr (PcdBaseBoardAssetTag); + break; + case SerialNumberType02: + String =3D (CHAR16*)PcdGetPtr (PcdBaseBoardSerialNumber); + break; + case BoardManufacturerType02: + String =3D (CHAR16*)PcdGetPtr (PcdBaseBoardManufacturer); + break; + case SkuNumberType02: + String =3D (CHAR16*)PcdGetPtr (PcdBaseBoardSKU); + break; + case ChassisLocationType02: + String =3D (CHAR16*)PcdGetPtr (PcdBaseBoardLocation); + break; + case SerialNumberType03: + String =3D (CHAR16*)PcdGetPtr (PcdChassisSerialNumber); + break; + case VersionType03: + String =3D (CHAR16*)PcdGetPtr (PcdChassisVersion); + break; + case ManufacturerType03: + String =3D (CHAR16*)PcdGetPtr (PcdChassisManufacturer); + break; + case AssetTagType03: + String =3D (CHAR16*)PcdGetPtr (PcdChassisAssetTag); + break; + case SkuNumberType03: + String =3D (CHAR16*)PcdGetPtr (PcdChassisSKU); + break; + default: + String =3D NULL; + break; + } + + if (String !=3D NULL) { + HiiSetString (HiiHandle, TokenToUpdate, String, NULL); + } +} + diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf b/Platform/Qe= mu/SbsaQemu/OemMiscLib/OemMiscLib.inf new file mode 100644 index 000000000000..04a07a55cee9 --- /dev/null +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf @@ -0,0 +1,53 @@ +#/** @file +# OemMiscLib.inf +# +# Copyright (c) 2021, NUVIA Inc. All rights reserved. +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D OemMiscLib + FILE_GUID =3D 958caf90-9e55-4e2a-86e0-71da21485e2c + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D OemMiscLib + +[Sources.common] + OemMiscLib.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Qemu/SbsaQemu/SbsaQemu.dec + +[LibraryClasses] + BaseMemoryLib + FdtLib + FdtHelperLib + IoLib + PcdLib + +[Pcd] + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemManufacturer + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSerialNumber + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSKU + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemFamily + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardAssetTag + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardSerialNumber + gArmTokenSpaceGuid.PcdBaseBoardManufacturer + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardSKU + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardLocation + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSerialNumber + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisVersion + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisManufacturer + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisAssetTag + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSKU diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/S= bsaQemu.dsc index 8faad3eda217..c1f8a4696560 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -1,4 +1,5 @@ # +# Copyright (c) 2021, NUVIA Inc. All rights reserved. # Copyright (c) 2019, Linaro Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -122,6 +123,7 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf =20 FdtHelperLib|Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf + OemMiscLib|Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf =20 # Debug Support PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf @@ -486,6 +488,23 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE # enumeration to complete before installing ACPI tables. gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE =20 + gArmTokenSpaceGuid.PcdSystemProductName|L"QEMU SBSA-REF Machine" + gArmTokenSpaceGuid.PcdSystemVersion|L"1.0" + gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L"QEMU" + gArmTokenSpaceGuid.PcdBaseBoardProductName|L"SBSA-REF" + gArmTokenSpaceGuid.PcdBaseBoardVersion|L"1.0" + + # These values are fixed for now, but should be configurable via + # something like an emulated SCP. + gArmTokenSpaceGuid.PcdProcessorManufacturer|L"QEMU" + gArmTokenSpaceGuid.PcdProcessorVersion|L"arm-virt" + gArmTokenSpaceGuid.PcdProcessorSerialNumber|L"SN0000" + gArmTokenSpaceGuid.PcdProcessorAssetTag|L"AT0000" + gArmTokenSpaceGuid.PcdProcessorPartNumber|L"PN0000" + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"EFI Development Kit I= I / SbsaQemu" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"1.0" + [PcdsDynamicDefault.common] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3 =20 @@ -510,9 +529,28 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE # # SMBIOS entry point version # - gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0304 gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 =20 + gArmTokenSpaceGuid.PcdSystemBiosRelease|0x0100 + gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0x0100 + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemManufacturer|L"QEMU" + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSerialNumber|L"SN0000" + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSKU|L"SK0000" + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemFamily|L"ArmVirt" + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardAssetTag|L"AT0000" + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardSerialNumber|L"SN0000" + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardSKU|L"SK000" + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardLocation|L"Internal" + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSerialNumber|L"SN0000" + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisVersion|L"1.0" + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisManufacturer|L"QEMU" + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisAssetTag|L"AT0000" + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSKU|L"SK0000" + ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform @@ -670,6 +708,14 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf =20 + # + # SMBIOS support + # + ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + EmbeddedPkg/Library/FdtLib/FdtLib.inf + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + # # PCI support # diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/S= bsaQemu.fdf index 3bcf0bf0040a..c35e3ed44054 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf @@ -236,6 +236,13 @@ READ_LOCK_STATUS =3D TRUE INF RuleOverride =3D ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTabl= es.inf INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphic= sResourceTableDxe.inf =20 + # + # SMBIOS support + # + INF ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + INF ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + # # PCI support # diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/Sbs= aQemu.dec index 476dc82f98f3..3abc9b64e49e 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -50,3 +50,21 @@ [PcdsDynamic.common] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000100 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x0000= 0101 + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemManufacturer|L""|VOID*|0= x00000110 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSerialNumber|L""|VOID*|0= x00000111 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSKU|L""|VOID*|0x00000112 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemFamily|L""|VOID*|0x00000= 113 + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardAssetTag|L""|VOID*|0x= 00000114 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardSerialNumber|L""|VOID= *|0x00000115 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID= *|0x00000116 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardSKU|L""|VOID*|0x00000= 117 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdBaseBoardLocation|L""|VOID*|0x= 00000118 + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSerialNumber|L""|VOID*|= 0x00000119 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisVersion|L""|VOID*|0x000= 0011A + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisManufacturer|L""|VOID*|= 0x0000011B + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisAssetTag|L""|VOID*|0x00= 00011C + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSKU|L""|VOID*|0x0000011D + --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72085): https://edk2.groups.io/g/devel/message/72085 Mute This Topic: https://groups.io/mt/80851705/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 07:32:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72086+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72086+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1614090412; cv=none; d=zohomail.com; s=zohoarc; b=bIrpxTTJqoHK2mBKhHwWlXEwUpSTEPh/6tLAjcZIpdxkkh4+fgu0tBpiuy6zmbfRHPHhzYKa8PW1OU8JqiewFR54k0ggxHvsruYwa9NMVpq1CR1P9zCTrZJwFs1P1MUn5YcDLHTFt13rCrT9deMnSG7zCJX2Cpzc6wrXR1prx28= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614090412; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Aqvfv+Zyel8hgHij5RVT1zTQZA9sCa4KcbiqZmG/rTA=; b=FsnPFAw9kDOC2yvcUq/9BRqZxrQ+pAUTAtdw4OYsWa6kC73fSPeM53lnYCA2Z+UzD9XU8Nl1xGh95IeLnvDWl7i4HvNGDhpRJPhF9kC6UvUTEybkvGBIgrTu7iyo3IELXa9hbAATEm7oTkhtPUB0FLkjjBMxsQ/ny36suQ4YZ3o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72086+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1614090412526122.81366428369768; Tue, 23 Feb 2021 06:26:52 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9AsVYY1788612xw4Vz9wRwS8; Tue, 23 Feb 2021 06:26:52 -0800 X-Received: from mail-il1-f180.google.com (mail-il1-f180.google.com [209.85.166.180]) by mx.groups.io with SMTP id smtpd.web11.10438.1614090406744729921 for ; Tue, 23 Feb 2021 06:26:46 -0800 X-Received: by mail-il1-f180.google.com with SMTP id g9so14232077ilc.3 for ; Tue, 23 Feb 2021 06:26:46 -0800 (PST) X-Gm-Message-State: 7SqqTK68ExAwHVYCVATkaa2Mx1787277AA= X-Google-Smtp-Source: ABdhPJzNpKYnULUbAXmf6agfHfBDiaNtKlZK+lQSEQmULyftuZaBvwSnbR4i8BAeg1Ot1xLDMbjbHQ== X-Received: by 2002:a05:6e02:1bcb:: with SMTP id x11mr18789277ilv.226.1614090405865; Tue, 23 Feb 2021 06:26:45 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id b9sm15391541ilo.41.2021.02.23.06.26.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 06:26:45 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Radoslaw Biernacki Subject: [edk2-devel] [edk2-platforms PATCH v4 4/4] Silicon/Qemu: Don't re-use NumCores as loop index in AddMadtTable Date: Tue, 23 Feb 2021 07:26:35 -0700 Message-Id: <20210223142635.8807-5-rebecca@nuviainc.com> In-Reply-To: <20210223142635.8807-1-rebecca@nuviainc.com> References: <20210223142635.8807-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1614090412; bh=ECpExtYGsjDcGz85C8qw/a1WBgny6eq6t30rmLfRus4=; h=Cc:Date:From:Reply-To:Subject:To; b=iocho/BVGpZpyDZ0tCCf27iynIuxB6i9eT9vYqMuRewZR57J8fScip//3jEiMBbOQGa nUOVd6b69T1eN8+/hl72MtpjsDzQOg+CHFD+19c7Yoouv+wrlliKs8l+z4S2vgoYBpN2U PmEtlmybxRvM4o/W7ovpEW/9QB9wM/ksj0A= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Avoid re-using the NumCores variable as a loop index, in AddMadtTable: add a new CoreIndex variable for that purpose. Signed-off-by: Rebecca Cran --- Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 037c7cff4c18..84120f1c1b51 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -88,6 +88,7 @@ AddMadtTable ( EFI_PHYSICAL_ADDRESS PageAddress; UINT8 *New; UINT32 NumCores; + UINT32 CoreIndex; =20 // Initialize MADT ACPI Header EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header =3D { @@ -152,13 +153,13 @@ AddMadtTable ( New +=3D sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); =20 // Add new GICC structures for the Cores - for (NumCores =3D 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) { + for (CoreIndex =3D 0; CoreIndex < PcdGet32 (PcdCoreCount); CoreIndex++) { EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr; =20 CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); GiccPtr =3D (EFI_ACPI_6_0_GIC_STRUCTURE *) New; - GiccPtr->AcpiProcessorUid =3D NumCores; - GiccPtr->MPIDR =3D GetMpidr (NumCores); + GiccPtr->AcpiProcessorUid =3D CoreIndex; + GiccPtr->MPIDR =3D GetMpidr (CoreIndex); New +=3D sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); } =20 --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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