From nobody Tue Feb 10 04:16:25 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+72072+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72072+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1614086090; cv=none; d=zohomail.com; s=zohoarc; b=XeLP0PRrQtEUa9+iOjU146oC+x1ptiPJxkwSN14vw3XTz+anXaak8z6g18ozVzdUN4tCot51umwJUO7lSWTldiJ9YQo70Ce2TtocodwamBhkfgejNKawSte+wwVJPOm4fImW6ir9C+mbHpwobozaPknpIiQk/1oJfCZck6CnieU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614086090; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=rIsutcrZJ5AlQZGEo6p+Tgo9ff5Nt8qpyTK3jPqz54Q=; b=JmWLLNfYIE2JFMPJJpo92CrpCOfGf5rkCNfF4pDAy1wCfIiM4XCqPHAwDAaAqxFSlw8w3fdVI0lP0K5ew0LKUAf1AE0DIeDK8qfrVOBOztm+Budk2FhonYsg66KoX1F+jlv0bz+Bq9nyMeewjBi8SGBoe4MlFj/fQJzaj05o5s0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+72072+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161408609052278.94776114018839; Tue, 23 Feb 2021 05:14:50 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id njcOYY1788612xLttBKOt1JQ; Tue, 23 Feb 2021 05:14:50 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.9507.1614086084692074317 for ; Tue, 23 Feb 2021 05:14:44 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 57F1C31B; Tue, 23 Feb 2021 05:14:44 -0800 (PST) X-Received: from e120189.arm.com (unknown [10.57.9.161]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0D1883F70D; Tue, 23 Feb 2021 05:14:42 -0800 (PST) From: "PierreGondois" To: devel@edk2.groups.io, ardb+tianocore@kernel.org, leif@nuviainc.com, sami.mujawar@arm.com Subject: [edk2-devel] [PATCH v3 18/26] ArmPkg: Fix Ecc error 8005/8007 in ArmDisassemblerLib Date: Tue, 23 Feb 2021 13:13:58 +0000 Message-Id: <20210223131406.3484-19-Pierre.Gondois@arm.com> In-Reply-To: <20210223131406.3484-1-Pierre.Gondois@arm.com> References: <20210223131406.3484-1-Pierre.Gondois@arm.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pierre.gondois@arm.com X-Gm-Message-State: SiX36IxfwDkMh4YgLR0bVNdTx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1614086090; bh=BG2v6Jtn39A+c7JaJj7MTQkX3dqG9PHUHldX6mG5KSc=; h=Date:From:Reply-To:Subject:To; b=UWTw4vOR0UXDgqGn3XyETjFZ+xMp4W69nv+PPctXtk7s70wU5ob0zCxpmsbVi0dMPq7 qK3hE8sExzLFkfR92aKfDL1TnTrfutlGTRrEV4rAPOmhmigvDNFS2Ml+gOSO3ZDdv+fWK iuQJhjQQT7vunRKrzhvloo1ettnDHXqjVi4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pierre Gondois This patch fixes the following Ecc reported error: 8005: Variable name does not follow the rules: 1. First character should be upper case 2. Must contain lower case characters 3. No white space characters 4. Global variable name must start with a 'g' 8007: There should be no use of short (single character) variable names Signed-off-by: Pierre Gondois Reviewed-by: Sami Mujawar --- The changes can be seen at: https://github.com/PierreARM/edk2/tree/1552_Ecc= _ArmPkg_BIS_v3 .../ArmDisassemblerLib/ArmDisassembler.c | 159 +++++++++--------- .../ArmDisassemblerLib/ThumbDisassembler.c | 158 ++++++++--------- 2 files changed, 163 insertions(+), 154 deletions(-) diff --git a/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c b/ArmPkg/L= ibrary/ArmDisassemblerLib/ArmDisassembler.c index e67e13a50ace..03a9f1fbe2e5 100644 --- a/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c +++ b/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c @@ -71,7 +71,7 @@ CHAR8 *gLdmStack[] =3D { =20 =20 #define SIGN(_U) ((_U) ? "" : "-") -#define WRITE(_W) ((_W) ? "!" : "") +#define WRITE(_Write) ((_Write) ? "!" : "") #define BYTE(_B) ((_B) ? "B":"") #define USER(_B) ((_B) ? "^" : "") =20 @@ -159,23 +159,24 @@ DisassembleArmInstruction ( ) { UINT32 OpCode; - CHAR8 *Type, *Root; - BOOLEAN I, P, U, B, W, L, S, H; + CHAR8 *Type; + CHAR8 *Root; + BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half; UINT32 Rn, Rd, Rm; - UINT32 imode, offset_8, offset_12; + UINT32 IMod, Offset8, Offset12; UINT32 Index; - UINT32 shift_imm, shift; + UINT32 ShiftImm, Shift; =20 OpCode =3D **OpCodePtr; =20 - I =3D (OpCode & BIT25) =3D=3D BIT25; - P =3D (OpCode & BIT24) =3D=3D BIT24; - U =3D (OpCode & BIT23) =3D=3D BIT23; - B =3D (OpCode & BIT22) =3D=3D BIT22; // Also called S - W =3D (OpCode & BIT21) =3D=3D BIT21; - L =3D (OpCode & BIT20) =3D=3D BIT20; - S =3D (OpCode & BIT6) =3D=3D BIT6; - H =3D (OpCode & BIT5) =3D=3D BIT5; + Imm =3D (OpCode & BIT25) =3D=3D BIT25; // I + Pre =3D (OpCode & BIT24) =3D=3D BIT24; // P + Up =3D (OpCode & BIT23) =3D=3D BIT23; // U + WriteBack =3D (OpCode & BIT22) =3D=3D BIT22; // B, also called S + Write =3D (OpCode & BIT21) =3D=3D BIT21; // W + Load =3D (OpCode & BIT20) =3D=3D BIT20; // L + Sign =3D (OpCode & BIT6) =3D=3D BIT6; // S + Half =3D (OpCode & BIT5) =3D=3D BIT5; // H Rn =3D (OpCode >> 16) & 0xf; Rd =3D (OpCode >> 12) & 0xf; Rm =3D (OpCode & 0xf); @@ -189,7 +190,7 @@ DisassembleArmInstruction ( =20 // LDREX, STREX if ((OpCode & 0x0fe000f0) =3D=3D 0x01800090) { - if (L) { + if (Load) { // A4.1.27 LDREX{} , [] AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd],= gReg[Rn]); } else { @@ -201,89 +202,89 @@ DisassembleArmInstruction ( =20 // LDM/STM if ((OpCode & 0x0e000000) =3D=3D 0x08000000) { - if (L) { + if (Load) { // A4.1.20 LDM{} {!}, // A4.1.21 LDM{} , ^ // A4.1.22 LDM{} {!}, ^ - AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT = (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B)); + AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT = (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER = (WriteBack)); } else { // A4.1.97 STM{} {!}, // A4.1.98 STM{} , ^ - AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT = (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B)); + AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT = (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER = (WriteBack)); } return; } =20 // LDR/STR Address Mode 2 if ( ((OpCode & 0x0c000000) =3D=3D 0x04000000) || ((OpCode & 0xfd70f000= ) =3D=3D 0xf550f000) ) { - offset_12 =3D OpCode & 0xfff; + Offset12 =3D OpCode & 0xfff; if ((OpCode & 0xfd70f000 ) =3D=3D 0xf550f000) { Index =3D AsciiSPrint (Buf, Size, "PLD"); } else { - Index =3D AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR"= , COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]); + Index =3D AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "S= TR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]); } - if (P) { - if (!I) { + if (Pre) { + if (!Imm) { // A5.2.2 [, #+/-] // A5.2.5 [, #+/-] - AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn= ], SIGN (U), offset_12, WRITE (W)); + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn= ], SIGN (Up), Offset12, WRITE (Write)); } else if ((OpCode & 0x03000ff0) =3D=3D 0x03000000) { // A5.2.3 [, +/-] // A5.2.6 [, +/-]! - AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn],= SIGN (U), WRITE (W)); + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn],= SIGN (Up), WRITE (Write)); } else { // A5.2.4 [, +/-, LSL #] // A5.2.7 [, +/-, LSL #]! - shift_imm =3D (OpCode >> 7) & 0x1f; - shift =3D (OpCode >> 5) & 0x3; - if (shift =3D=3D 0x0) { + ShiftImm =3D (OpCode >> 7) & 0x1f; + Shift =3D (OpCode >> 5) & 0x3; + if (Shift =3D=3D 0x0) { Type =3D "LSL"; - } else if (shift =3D=3D 0x1) { + } else if (Shift =3D=3D 0x1) { Type =3D "LSR"; - if (shift_imm =3D=3D 0) { - shift_imm =3D 32; + if (ShiftImm =3D=3D 0) { + ShiftImm =3D 32; } - } else if (shift =3D=3D 0x2) { + } else if (Shift =3D=3D 0x2) { Type =3D "ASR"; - } else if (shift_imm =3D=3D 0) { - AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a"= , gReg[Rn], SIGN (U), gReg[Rm], WRITE (W)); + } else if (ShiftImm =3D=3D 0) { + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a"= , gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write)); return; } else { Type =3D "ROR"; } =20 - AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", = gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W)); + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", = gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write)); } - } else { // !P - if (!I) { + } else { // !Pre + if (!Imm) { // A5.2.8 [], #+/- - AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn],= SIGN (U), offset_12); + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn],= SIGN (Up), Offset12); } else if ((OpCode & 0x03000ff0) =3D=3D 0x03000000) { // A5.2.9 [], +/- - AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], S= IGN (U), gReg[Rm]); + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], S= IGN (Up), gReg[Rm]); } else { // A5.2.10 [], +/-, LSL # - shift_imm =3D (OpCode >> 7) & 0x1f; - shift =3D (OpCode >> 5) & 0x3; + ShiftImm =3D (OpCode >> 7) & 0x1f; + Shift =3D (OpCode >> 5) & 0x3; =20 - if (shift =3D=3D 0x0) { + if (Shift =3D=3D 0x0) { Type =3D "LSL"; - } else if (shift =3D=3D 0x1) { + } else if (Shift =3D=3D 0x1) { Type =3D "LSR"; - if (shift_imm =3D=3D 0) { - shift_imm =3D 32; + if (ShiftImm =3D=3D 0) { + ShiftImm =3D 32; } - } else if (shift =3D=3D 0x2) { + } else if (Shift =3D=3D 0x2) { Type =3D "ASR"; - } else if (shift_imm =3D=3D 0) { - AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", = gReg[Rn], SIGN (U), gReg[Rm]); + } else if (ShiftImm =3D=3D 0) { + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", = gReg[Rn], SIGN (Up), gReg[Rm]); // FIx me return; } else { Type =3D "ROR"; } =20 - AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gR= eg[Rn], SIGN (U), gReg[Rm], Type, shift_imm); + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gR= eg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm); } } return; @@ -292,18 +293,18 @@ DisassembleArmInstruction ( if ((OpCode & 0x0e000000) =3D=3D 0x00000000) { // LDR/STR address mode 3 // LDR|STR{}H|SH|SB|D , - if (L) { - if (!S) { + if (Load) { + if (!Sign) { Root =3D "LDR%aH %a, "; - } else if (!H) { + } else if (!Half) { Root =3D "LDR%aSB %a, "; } else { Root =3D "LDR%aSH %a, "; } } else { - if (!S) { + if (!Sign) { Root =3D "STR%aH %a "; - } else if (!H) { + } else if (!Half) { Root =3D "LDR%aD %a "; } else { Root =3D "STR%aD %a "; @@ -312,28 +313,28 @@ DisassembleArmInstruction ( =20 Index =3D AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]); =20 - S =3D (OpCode & BIT6) =3D=3D BIT6; - H =3D (OpCode & BIT5) =3D=3D BIT5; - offset_8 =3D ((OpCode >> 4) | (OpCode * 0xf)) & 0xff; - if (P & !W) { + Sign =3D (OpCode & BIT6) =3D=3D BIT6; + Half =3D (OpCode & BIT5) =3D=3D BIT5; + Offset8 =3D ((OpCode >> 4) | (OpCode * 0xf)) & 0xff; + if (Pre & !Write) { // Immediate offset/index - if (B) { + if (WriteBack) { // A5.3.2 [, #+/-] // A5.3.4 [, #+/-]! - AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn]= , SIGN (U), offset_8, WRITE (W)); + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn]= , SIGN (Up), Offset8, WRITE (Write)); } else { // A5.3.3 [, +/-] // A5.3.5 [, +/-]! - AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], = SIGN (U), gReg[Rm], WRITE (W)); + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], = SIGN (Up), gReg[Rm], WRITE (Write)); } } else { // Register offset/index - if (B) { + if (WriteBack) { // A5.3.6 [], #+/- - AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], = SIGN (U), offset_8); + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], = SIGN (Up), Offset8); } else { // A5.3.7 [], +/- - AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], = SIGN (U), gReg[Rm]); + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], = SIGN (Up), gReg[Rm]); } } return; @@ -342,19 +343,19 @@ DisassembleArmInstruction ( if ((OpCode & 0x0fb000f0) =3D=3D 0x01000050) { // A4.1.108 SWP SWP{}B , , [] // A4.1.109 SWPB SWP{}B , , [] - AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B= ), gReg[Rd], gReg[Rm], gReg[Rn]); + AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (W= riteBack), gReg[Rd], gReg[Rm], gReg[Rn]); return; } =20 if ((OpCode & 0xfe5f0f00) =3D=3D 0xf84d0500) { // A4.1.90 SRS SRS #{!} - AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3]= , OpCode & 0x1f, WRITE (W)); + AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3]= , OpCode & 0x1f, WRITE (Write)); return; } =20 if ((OpCode & 0xfe500f00) =3D=3D 0xf8100500) { // A4.1.59 RFE {!} - AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gRe= g[Rn], WRITE (W)); + AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gRe= g[Rn], WRITE (Write)); return; } =20 @@ -369,9 +370,9 @@ DisassembleArmInstruction ( if (((OpCode >> 6) & 0x7) =3D=3D 0) { AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f)); } else { - imode =3D (OpCode >> 18) & 0x3; + IMod =3D (OpCode >> 18) & 0x3; Index =3D AsciiSPrint (Buf, Size, "CPS%a %a%a%a", - (imode =3D=3D 3) ? "ID":"IE", + (IMod =3D=3D 3) ? "ID":"IE", ((OpCode & BIT8) !=3D 0) ? "A":"", ((OpCode & BIT7) !=3D 0) ? "I":"", ((OpCode & BIT6) !=3D 0) ? "F":""); @@ -390,19 +391,19 @@ DisassembleArmInstruction ( =20 if ((OpCode & 0x0fb00000) =3D=3D 0x01000000) { // A4.1.38 MRS{} , CPSR MRS{} , SPSR - AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "= SPSR" : "CPSR"); + AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], Write= Back ? "SPSR" : "CPSR"); return; } =20 =20 if ((OpCode & 0x0db00000) =3D=3D 0x01200000) { // A4.1.38 MSR{} CPSR_, # MSR{} CPSR_, - if (I) { + if (Imm) { // MSR{} CPSR_, # - AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), B ? "S= PSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf,= ((OpCode >> 8) & 0xf) *2)); + AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteB= ack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCod= e & 0xf, ((OpCode >> 8) & 0xf) *2)); } else { // MSR{} CPSR_, - AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR"= : "CPSR", gReg[Rd]); + AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack = ? "SPSR" : "CPSR", gReg[Rd]); } return; } @@ -416,35 +417,35 @@ DisassembleArmInstruction ( if ((OpCode & 0x0e000000) =3D=3D 0x0c000000) { // A4.1.19 LDC and A4.1.96 SDC if ((OpCode & 0xf0000000) =3D=3D 0xf0000000) { - Index =3D AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", L ? "LDC":"SDC= ", (OpCode >> 8) & 0xf, Rd); + Index =3D AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"= SDC", (OpCode >> 8) & 0xf, Rd); } else { - Index =3D AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", L ? "LDC":"S= DC", COND (OpCode), (OpCode >> 8) & 0xf, Rd); + Index =3D AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC"= :"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd); } =20 - if (!P) { - if (!W) { + if (!Pre) { + if (!Write) { // A5.5.5.5 [],