From nobody Thu May 2 15:13:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+71865+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+71865+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1613790940; cv=none; d=zohomail.com; s=zohoarc; b=WO5ubCjI0hniCDkJfPNsKGmisueD7NA/Wwp9K91+uCyqk7U+6DHaIJ7ytS5sAAhk/HYgbQIYaGDjG6dA7tjtm8sK+lSUL8sHNBZ5Lues8RemmibmP8o88EodcDNhCzy5Ql9vZGMyC8bDQOxsV9D/YHdOPFF0nArwj13NgXXbfX8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613790940; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=G0flsgAjGrRBqdPLpcvInG+SJyPFJRl4C5gSQll8+Mw=; b=Ha7xjwx3zG8/BRl8OsGHZySTFF+gDn4JuyqquKjMIIvhJeD78+7lrD2i9R/srCwpy23ZnQ9nnUBiWRfLU45+9GkmN+12SAWKEAN702YC7fvB+L0T/7YnehxIfIkGeLJkpQWBGsF9hb4KjT/iDHzW5PlWlmZ5ba3hntlSdSAZ5sI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+71865+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161379094060986.79948892480013; Fri, 19 Feb 2021 19:15:40 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id D2xcYY1788612xgMw6dqskwR; Fri, 19 Feb 2021 19:15:40 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.2539.1613790934463072726 for ; Fri, 19 Feb 2021 19:15:34 -0800 IronPort-SDR: FqCxlhL/KPod+w1VW7p39uqd5MNEBkXgWeFXOLZRxgQzXbHbcQc29cJVz88MPKxoo6YIHkK01b B+e9rN6fDL0g== X-IronPort-AV: E=McAfee;i="6000,8403,9900"; a="184082925" X-IronPort-AV: E=Sophos;i="5.81,192,1610438400"; d="scan'208";a="184082925" X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2021 19:15:34 -0800 IronPort-SDR: /C2healfzFvx5vzB82+dSVldSy3TmC5mzyHQiWDSGN7NTC1Aby3+xIFYJubXasI9EuzLA9NqJr IDK8a0YKhNtQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,192,1610438400"; d="scan'208";a="440520725" X-Received: from unknown (HELO shwdeSSSDDPDWEI.ccr.corp.intel.com) ([10.239.157.35]) by orsmga001.jf.intel.com with ESMTP; 19 Feb 2021 19:15:32 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Jiewen Yao Subject: [edk2-devel] [PATCH v5 1/2] MdePkg/Include: Add CET instructions to Nasm.inc Date: Sat, 20 Feb 2021 11:15:00 +0800 Message-Id: <20210220031501.24284-2-w.sheng@intel.com> In-Reply-To: <20210220031501.24284-1-w.sheng@intel.com> References: <20210220031501.24284-1-w.sheng@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: byaHSpkUiaVbokZQSQb4lTyBx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1613790940; bh=X3U2U9T26N8MYzKCLsYqCKgv+AtyewftckEBw3QeMTg=; h=Cc:Date:From:Reply-To:Subject:To; b=g0EOZozWBQjfVCYEOaGcaW7jmHaqdiQECe2XL9zfOjjckzQuBz0LrKRxP5N711KeQQc G8NFy3SD9rRzUe8IG6cJXa+KashgY+IDwlKqk+O/Ixm5bWfe7QLWH6Yx5RugY/N3BVFxb djlIbhjeASZgpJuUyAqCaoPpkKS7YaCbK0s= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is to add instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP_RAX in Nasm. The open CI is using NASM 2.14.02. CET instructions are supported since NASM 2.15.01. DB-encoded CET instructions need to be removed after open CI update to NASM 2.15.01. The BZ ticket is https://bugzilla.tianocore.org/show_bug.cgi?id=3D3227 . REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3192 Signed-off-by: Sheng Wei Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Jiewen Yao Reviewed-by: Jiewen Yao Reviewed-by: Liming Gao --- MdePkg/Include/Ia32/Nasm.inc | 12 ++++++++++++ MdePkg/Include/X64/Nasm.inc | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/MdePkg/Include/Ia32/Nasm.inc b/MdePkg/Include/Ia32/Nasm.inc index 31ce861f1e..fa42f9d3e9 100644 --- a/MdePkg/Include/Ia32/Nasm.inc +++ b/MdePkg/Include/Ia32/Nasm.inc @@ -9,6 +9,18 @@ ; ;-------------------------------------------------------------------------= ----- =20 +%macro SAVEPREVSSP 0 + DB 0xF3, 0x0F, 0x01, 0xEA +%endmacro + +%macro CLRSSBSY_EAX 0 + DB 0x67, 0xF3, 0x0F, 0xAE, 0x30 +%endmacro + +%macro RSTORSSP_EAX 0 + DB 0x67, 0xF3, 0x0F, 0x01, 0x28 +%endmacro + %macro SETSSBSY 0 DB 0xF3, 0x0F, 0x01, 0xE8 %endmacro diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc index 42412735ea..e57a803c81 100644 --- a/MdePkg/Include/X64/Nasm.inc +++ b/MdePkg/Include/X64/Nasm.inc @@ -9,6 +9,18 @@ ; ;-------------------------------------------------------------------------= ----- =20 +%macro SAVEPREVSSP 0 + DB 0xF3, 0x0F, 0x01, 0xEA +%endmacro + +%macro CLRSSBSY_RAX 0 + DB 0xF3, 0x0F, 0xAE, 0x30 +%endmacro + +%macro RSTORSSP_RAX 0 + DB 0xF3, 0x0F, 0x01, 0x28 +%endmacro + %macro SETSSBSY 0 DB 0xF3, 0x0F, 0x01, 0xE8 %endmacro --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#71865): https://edk2.groups.io/g/devel/message/71865 Mute This Topic: https://groups.io/mt/80772530/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 15:13:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+71866+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+71866+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1613790938; cv=none; d=zohomail.com; s=zohoarc; b=kw2wJfZrueCx4Y5DdcfN6cMPJ0HK5nY/tFqvdLv3VXBLv+uZj4/VEjKe/S7z2vMrCzkpwWEshlyGzWYB/SDM0ZtYe0KbmI6dwuEY16tZxo05OxS8GyXfvsD5FlmQn072pgioDlCE202xY3tHm2zhFCKtD3TiDjVAQ7y5OAyb51s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613790938; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=ODnVMdTgvAfCJSi+KHyrlsofqONLvCRWBNch4UKTj/I=; b=OJpxIJkpOqK3x7yRlPE4eoTg393eaXNhnkd3YL+XPHeNM5e30jsQ7oTYHDxDEkxsOqnKyV5yf3eTmYyczs2jmWKBL9NT/jrik/ykPoJh3/FJ0Y/OarsHyOOgiCWOfJYTuUujzfpEiJDLoOBoVbFGaYGUVZhHrSefXXjaq7EEBTo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+71866+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1613790937674350.9951716622335; Fri, 19 Feb 2021 19:15:37 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id GLoEYY1788612xaoV5oEw9pi; Fri, 19 Feb 2021 19:15:37 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.2541.1613790936874003376 for ; Fri, 19 Feb 2021 19:15:36 -0800 IronPort-SDR: eh6gNwYLJhUt1lXvQQ4sT01Kg2RsnRzcNA8b2h6hlHtXYsQPonKt7TZ3PzQXwTNs9ngY1pYZVA UIionwjknLTQ== X-IronPort-AV: E=McAfee;i="6000,8403,9900"; a="184082950" X-IronPort-AV: E=Sophos;i="5.81,192,1610438400"; d="scan'208";a="184082950" X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2021 19:15:36 -0800 IronPort-SDR: E+BP9Ta4p005oBcy0Y9rd1483/+JkYRZIMUhK3mTv56qrSSByQGIDggu2/Muv55bmM23ef4bgm JswI4D/SI+qQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,192,1610438400"; d="scan'208";a="440520733" X-Received: from unknown (HELO shwdeSSSDDPDWEI.ccr.corp.intel.com) ([10.239.157.35]) by orsmga001.jf.intel.com with ESMTP; 19 Feb 2021 19:15:34 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar , Jiewen Yao , Roger Feng Subject: [edk2-devel] [PATCH v5 2/2] UefiCpuPkg/CpuExceptionHandlerLib: Clear CET shadow stack token busy bit Date: Sat, 20 Feb 2021 11:15:01 +0800 Message-Id: <20210220031501.24284-3-w.sheng@intel.com> In-Reply-To: <20210220031501.24284-1-w.sheng@intel.com> References: <20210220031501.24284-1-w.sheng@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: OK61TRrtRRgn82OX1kyxCY8lx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1613790937; bh=ZQQPHYYLHKp9X35WnqgBy/Sv8wQ1BAT+CbIatQ5Uq/Q=; h=Cc:Date:From:Reply-To:Subject:To; b=cjR0Cf5tElnoUOa9HIbIsUGwEvKjjNOJK4Jz80TZHII9JXfS2a1iri8WSaI6y2qiBKV vztwbTBMYs8YS3pjAhO1h0Sa5H278sQgb+HirMda3O5JgiK6+tAoSLOqzo2ozcvlMtakL +t6+/r6ppNMke3TI8Qmxyo0K4cRqKxV6G+M= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If CET shadows stack feature enabled in SMM and stack switch is enabled. When code execute from SMM handler to SMM exception, CPU will check SMM exception shadow stack token busy bit if it is cleared or not. If it is set, it will trigger #DF exception. If it is not set, CPU will set the busy bit when enter SMM exception. So, the busy bit should be cleared when return back form SMM exception to SMM handler. Otherwise, keeping busy bit 1 will cause to trigger #DF exception when enter SMM exception next time. So, we use instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP to clear the shadow stack token busy bit before RETF instruction in SMM exception. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3192 Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Jiewen Yao Cc: Roger Feng Reviewed-by: Jiewen Yao --- .../DxeCpuExceptionHandlerLib.inf | 3 ++ .../PeiCpuExceptionHandlerLib.inf | 3 ++ .../SecPeiCpuExceptionHandlerLib.inf | 4 ++ .../SmmCpuExceptionHandlerLib.inf | 3 ++ .../X64/Xcode5ExceptionHandlerAsm.nasm | 46 ++++++++++++++++++= +++- .../Xcode5SecPeiCpuExceptionHandlerLib.inf | 4 ++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 15 ++++++- 7 files changed, 75 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index 07b34c92a8..e7a81bebdb 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -43,6 +43,9 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize =20 +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES + [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandle= rLib.inf index feae7b3e06..cf5bfe4083 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf @@ -57,3 +57,6 @@ [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard # CONSUMES =20 +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES + diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHa= ndlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException= HandlerLib.inf index 967cb61ba6..8ae4feae62 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf @@ -49,3 +49,7 @@ LocalApicLib PeCoffGetEntryPointLib VmgExitLib + +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES + diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandle= rLib.inf index ea5b10b5c8..c9f20da058 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf @@ -53,3 +53,6 @@ DebugLib VmgExitLib =20 +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES + diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionH= andlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5Except= ionHandlerAsm.nasm index 26cae56cc5..ebe0eec874 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm @@ -13,6 +13,7 @@ ; Notes: ; ;-------------------------------------------------------------------------= ----- +%include "Nasm.inc" =20 ; ; CommonExceptionHandler() @@ -23,6 +24,7 @@ extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag extern ASM_PFX(CommonExceptionHandler) +extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) =20 SECTION .data =20 @@ -371,8 +373,48 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location mov rax, [rax] ; restore rax popfq ; restore EFLAGS - DB 0x48 ; prefix to composite "retq" with next "ret= f" - retf ; far return + + ; The follow algorithm is used for clear shadow stack token busy bit. + ; The comment is based on the sample shadow stack. + ; The sample shadow stack layout : + ; Address | Context + ; +-------------------------+ + ; 0xFD0 | FREE | it is 0xFD8|0x02|(LMA & CS.L), a= fter SAVEPREVSSP. + ; +-------------------------+ + ; 0xFD8 | Prev SSP | + ; +-------------------------+ + ; 0xFE0 | RIP | + ; +-------------------------+ + ; 0xFE8 | CS | + ; +-------------------------+ + ; 0xFF0 | 0xFF0 | BUSY | BUSY flag cleared after CLRSSBSY + ; +-------------------------+ + ; 0xFF8 | 0xFD8|0x02|(LMA & CS.L) | + ; +-------------------------+ + ; Instructions for Intel Control Flow Enforcement Technology (CET) are= supported since NASM version 2.15.01. + push rax ; SSP should be 0xFD8 at this point + cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0 + jz CetDone + mov rax, cr4 + and rax, 0x800000 ; check if CET is enabled + jz CetDone + mov rax, 0x04 ; advance past cs:lip:prevssp;supervisor s= hadow stack token + INCSSP_RAX ; After this SSP should be 0xFF8 + SAVEPREVSSP ; now the shadow stack restore token will = be created at 0xFD0 + READSSP_RAX ; Read new SSP, SSP should be 0x1000 + push rax + sub rax, 0x10 + CLRSSBSY_RAX ; Clear token at 0xFF0, SSP should be 0 af= ter this + sub rax, 0x20 + RSTORSSP_RAX ; Restore to token at 0xFD0, new SSP will = be 0xFD0 + pop rax + mov rax, 0x01 ; Pop off the new save token created + INCSSP_RAX ; SSP should be 0xFD8 now +CetDone: + pop rax ; restore rax + + DB 0x48 ; prefix to composite "retq" with next "re= tf" + retf ; far return DoIret: iretq =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExcep= tionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPei= CpuExceptionHandlerLib.inf index 743c2aa766..a15f125d5b 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf @@ -54,3 +54,7 @@ LocalApicLib PeCoffGetEntryPointLib VmgExitLib + +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES + diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSm= mCpuDxeSmm/X64/SmmFuncsArch.c index 28f8e8e133..7ef3b1d488 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c @@ -173,6 +173,7 @@ InitShadowStack ( { UINTN SmmShadowStackSize; UINT64 *InterruptSspTable; + UINT32 InterruptSsp; =20 if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) !=3D 0) && mCetSup= ported) { SmmShadowStackSize =3D EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 = (PcdCpuSmmShadowStackSize))); @@ -191,7 +192,19 @@ InitShadowStack ( ASSERT (mSmmInterruptSspTables !=3D 0); DEBUG ((DEBUG_INFO, "mSmmInterruptSspTables - 0x%x\n", mSmmInterru= ptSspTables)); } - mCetInterruptSsp =3D (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE= (1) - sizeof(UINT64)); + + // + // The highest address on the stack (0xFF8) is a save-previous-ssp t= oken pointing to a location that is 40 bytes away - 0xFD0. + // The supervisor shadow stack token is just above it at address 0xF= F0. This is where the interrupt SSP table points. + // So when an interrupt of exception occurs, we can use SAVESSP/REST= ORESSP/CLEARSSBUSY for the supervisor shadow stack, + // due to the reason the RETF in SMM exception handler cannot clear = the BUSY flag with same CPL. + // (only IRET or RETF with different CPL can clear BUSY flag) + // Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for= the full stack frame at runtime. + // + InterruptSsp =3D (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) = - sizeof(UINT64)); + *(UINT32 *)(UINTN)InterruptSsp =3D (InterruptSsp - sizeof(UINT64) * = 4) | 0x2; + mCetInterruptSsp =3D InterruptSsp - sizeof(UINT64); + mCetInterruptSspTable =3D (UINT32)(UINTN)(mSmmInterruptSspTables + s= izeof(UINT64) * 8 * CpuIndex); InterruptSspTable =3D (UINT64 *)(UINTN)mCetInterruptSspTable; InterruptSspTable[1] =3D mCetInterruptSsp; --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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