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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:32 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [edk2-devel] [PATCH v7 08/21] ArmPkg: Add definition of the maximum cache level in ARMv8-A Date: Sun, 31 Jan 2021 16:24:58 -0700 Message-Id: <20210131232511.18340-9-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135539; bh=9MaaWkeBIAdzRPRZi72ZnvITex8p40Nw4zXyxNXkQOE=; h=Cc:Date:From:Reply-To:Subject:To; b=cHXkasqqlKBosKYuitLXhnyHmlyRFsgP6Tcaia7Bl9q/g36NtDNRa0AMAf34uWlwENJ iAhz8jdjtLAfouPVJVw38kmYt77TbefxUpHpy8MwaDtZC9wClmtszGKpeFTt70KUYGrE2 IWNR+9h6Z+t/+MQ078F+i7+YZ6GMWJ0G4xU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The ARM Architecture Reference Manual for ARMv8-A defines up to seven levels of cache, L1 through L7. Define MAX_ARM_CACHE_LEVEL to be 7. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/Library/ArmLib.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index 26cb05def0a2..fd4f06d24274 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -109,6 +109,10 @@ typedef enum { #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK) =20 +// The ARM Architecture Reference Manual for ARMv8-A defines up +// to 7 levels of cache, L1 through L7. +#define MAX_ARM_CACHE_LEVEL 7 + UINTN EFIAPI ArmDataCacheLineLength ( --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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