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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:22 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [edk2-devel] [PATCH v7 03/21] ArmPkg: Add register encoding definition for MMFR2 Date: Sun, 31 Jan 2021 16:24:53 -0700 Message-Id: <20210131232511.18340-4-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135529; bh=RW2ZxrmPofKyqYAtrXnt/rpwuY63aW/36NRRC3nNjRI=; h=Cc:Date:From:Reply-To:Subject:To; b=EYH4cUHRozn2eYzYlY2f4AOBpkh96Cfn3OkD7nnJiuLbwe26zJaPoS9OF6dWLWblD5y wiT208xUkAza6K7oyHMRFbQV3YBQSOZcZ0AM/ioub/O0OmRHMS1sdug105sP7DUeklPtx iPlcV0QWH1/6KFml37O/dewsqH+Jl6uqJm4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add register encoding definition for Memory Model Feature Register 2. We need to define it here because we build for ARMv8.0, which doesn't have it. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/Chipset/AArch64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArc= h64.h index 0ade5cce91c3..7c2b592f92ee 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -112,6 +112,10 @@ #define ARM_VECTOR_LOW_A32_FIQ 0x700 #define ARM_VECTOR_LOW_A32_SERR 0x780 =20 +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we +// build for ARMv8.0, we need to define the register here. +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + #define VECTOR_BASE(tbl) \ .section .text.##tbl##,"ax"; \ .align 11; \ --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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