From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70927+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70927+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135520; cv=none; d=zohomail.com; s=zohoarc; b=USYjhdalqXXvLGzYJ/g+lwVdxwA6SUqDyfQkFyxdRP5SUHCdzvhdZuOEtz6xWOIHAjZedHXQ0xjK6qc+7DCGnEAwPhtAwRxjN1AlUlcqkILEIICROoOAIyeMFScLqqzCr0BSoBm5GReFhbVNv2XGX3tFPc0+G9Gk2Yk7ehjpfrA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135520; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=HAbGtaqTyG+90xRAq5FgLWSjSI0HH4jaYAX/ipiUaiA=; b=BXIcKDvG/H7x8cOEkOTyIlK81TTM4+JVjNy2DSB4XqG2e76rogQLiHtHf7onPk/NUBxOdJo+eZvtumJTEqw2iE1egP8rMqNC25mKrzbn+54ImpLMUXWwivMOnx35/H186+zdKdrE/LAmINEwFNcoPpxHDIZsU3lBk0xb3fDFGlU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70927+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1612135520612372.7657477980671; Sun, 31 Jan 2021 15:25:20 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id WAoCYY1788612xYiN1ZELT3F; Sun, 31 Jan 2021 15:25:20 -0800 X-Received: from mail-qt1-f181.google.com (mail-qt1-f181.google.com [209.85.160.181]) by mx.groups.io with SMTP id smtpd.web11.26307.1612135519766814870 for ; Sun, 31 Jan 2021 15:25:19 -0800 X-Received: by mail-qt1-f181.google.com with SMTP id e15so11018912qte.9 for ; Sun, 31 Jan 2021 15:25:19 -0800 (PST) X-Gm-Message-State: pjKKpdhNFfnzfCKRm1XCWKzPx1787277AA= X-Google-Smtp-Source: ABdhPJy40MbwMka1m66FM4XMAoW35oNj7zT/k57x3W/9qoQR0VilVuG50K7f4nR3yRR/9TFb2eIElg== X-Received: by 2002:ac8:5e12:: with SMTP id h18mr13092094qtx.335.1612135518621; Sun, 31 Jan 2021 15:25:18 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:18 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [edk2-devel] [PATCH v7 01/21] ArmPkg: Add ARM SMC Architecture functions to ArmStdSmc.h Date: Sun, 31 Jan 2021 16:24:51 -0700 Message-Id: <20210131232511.18340-2-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135520; bh=TjwHOZNQi9YcKHxKE+fTlDeEMolB+mizIyGXPURot2g=; h=Cc:Date:From:Reply-To:Subject:To; b=kql3bkTUCLzMQHZh3iG4e2COylrMmFVW7GJ3K81ZfMj+GozMhqqDhFZLEmf2qgCXmCZ HhbOjWQT994fWdCboj/roE9fXdP77Esb+SDittLCQpcaCg/5//0Gzkrjf9ZWgYUvRvmCS /RpAuPYr5dzoKRGjzI+eWUyK1lGyBJ0nc6o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The ARM SMC Architecture functions were missing from ArmStdSmc.h. Add them, based on the SMC Calling Convention version 1.2 specification. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h b/ArmPkg/Include/I= ndustryStandard/ArmStdSmc.h index 3509eb680f18..9e0a3a3960d5 100644 --- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h +++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h @@ -1,9 +1,13 @@ /** @file * +* Copyright (c) 2020, NUVIA Inc. All rights reserved.
* Copyright (c) 2012-2017, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * +* @par Revision Reference: +* - SMC Calling Convention version 1.2 +* (https://developer.arm.com/documentation/den0028/c/?lang=3Den) **/ =20 #ifndef __ARM_STD_SMC_H__ @@ -52,6 +56,18 @@ #define ARM_SMC_MM_RET_DENIED -3 #define ARM_SMC_MM_RET_NO_MEMORY -4 =20 +// ARM Architecture Calls +#define SMCCC_VERSION 0x80000000 +#define SMCCC_ARCH_FEATURES 0x80000001 +#define SMCCC_ARCH_SOC_ID 0x80000002 +#define SMCCC_ARCH_WORKAROUND_1 0x80008000 +#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF + +#define SMC_ARCH_CALL_SUCCESS 0 +#define SMC_ARCH_CALL_NOT_SUPPORTED -1 +#define SMC_ARCH_CALL_NOT_REQUIRED -2 +#define SMC_ARCH_CALL_INVALID_PARAMETER -3 + /* * Power State Coordination Interface (PSCI) calls cover a subset of the * Standard Service Call range. --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70927): https://edk2.groups.io/g/devel/message/70927 Mute This Topic: https://groups.io/mt/80271113/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70928+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70928+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135522; cv=none; d=zohomail.com; s=zohoarc; b=VL4GjuedbgGZNqz8REvCVT8CWgw0ddHFraGYTKdDHaHblOaLoJM7OxKZTcpRE6OjOqlLrxYqsEWV5+jeGlcAPkfEAOlll1JDpahyIOVIZfSk0EayQyccIRPOtd/ryWsKvHTGpMiot23m3nU/VEg5qaDC37zUqxwFR2VKp2dqZPs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135522; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Gh9bWj0FXL8flE82mxj1er6GlmlMnWI3aOU58HQE2yI=; b=UlcvGjhpADzzQUb2E9IoR/yPGvxL19u+JuETrDtybC0NX4YW0q7ToJBxNR7PYfzFlXOndyeeX1xbx3deDYIsnoWKxENMkTQRmdFGbrGPooDBevZQsql3ZwKvCIAbbEJK9JLU6YdikNyQrGknyR4B8ZSSDL8/DYHtHDWgt0fnj30= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70928+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161213552259932.18197275795467; Sun, 31 Jan 2021 15:25:22 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id KXzKYY1788612x3Cvcx9ZnSb; Sun, 31 Jan 2021 15:25:22 -0800 X-Received: from mail-qt1-f173.google.com (mail-qt1-f173.google.com [209.85.160.173]) by mx.groups.io with SMTP id smtpd.web08.26161.1612135521664137599 for ; Sun, 31 Jan 2021 15:25:21 -0800 X-Received: by mail-qt1-f173.google.com with SMTP id l23so11018343qtq.13 for ; Sun, 31 Jan 2021 15:25:21 -0800 (PST) X-Gm-Message-State: YZwnPiP6mDol7pSZN7IF35Smx1787277AA= X-Google-Smtp-Source: ABdhPJxqiNHbnnNGVeNKf9mFn2f5h+3HXJGQxOyGysm/aMCn6ywsA9VMhHzxkMYMK1wOs9PTHtfOoQ== X-Received: by 2002:ac8:5315:: with SMTP id t21mr5792229qtn.345.1612135520633; Sun, 31 Jan 2021 15:25:20 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:20 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [edk2-devel] [PATCH v7 02/21] MdePkg: Update IndustryStandard/SmBios.h with processor status data Date: Sun, 31 Jan 2021 16:24:52 -0700 Message-Id: <20210131232511.18340-3-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135522; bh=qpNB9+BROVb0fJU8oVW/A9ZcJFMJSG8kk3qzFp3Vigo=; h=Cc:Date:From:Reply-To:Subject:To; b=iomzZoxPm3aHaCmdecbx+A8g98kSZZTMtUF0isreffmXmJbjTHH5hSDWkLq8WZIN0Jd hMo3lbKcY/kC+orRQQt1uO1fNEbDvzHu0+GTbBQC7rWGi5XkT787vuLAZh9lnEdliKUXU ApkNDygzdIhs4VQPALzO4bVy1HJZxESxmB4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add a bitfield that describes the structure of the byte in the Status field of the SMBIOS Type 4 Processor Information table. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Acked-by: Sami Mujawar --- MdePkg/Include/IndustryStandard/SmBios.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/Indu= stryStandard/SmBios.h index 3bc8732eef99..cc023b73692a 100644 --- a/MdePkg/Include/IndustryStandard/SmBios.h +++ b/MdePkg/Include/IndustryStandard/SmBios.h @@ -875,6 +875,19 @@ typedef struct { UINT16 ProcessorReserved2 :6; } PROCESSOR_CHARACTERISTIC_FLAGS; =20 +/// +/// Processor Information - Status +/// +typedef union { + struct { + UINT8 CpuStatus :3; ///< Indicates the status of the processor. + UINT8 Reserved1 :3; ///< Reserved for future use. Must be set to= zero. + UINT8 SocketPopulated :1; ///< Indicates if the processor socket is po= pulated or not. + UINT8 Reserved2 :1; ///< Reserved for future use. Must be set to= zero. + } Bits; + UINT8 Data; +} PROCESSOR_STATUS_DATA; + typedef struct { PROCESSOR_SIGNATURE Signature; PROCESSOR_FEATURE_FLAGS FeatureFlags; --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70928): https://edk2.groups.io/g/devel/message/70928 Mute This Topic: https://groups.io/mt/80271114/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70929+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70929+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135529; cv=none; d=zohomail.com; s=zohoarc; b=m/9XHfFhFQzvXXCwK2c6QXj2sSAQUz0WZZDDETmyfLU426sfKCXpV78nL6nKliaRczXt6vZNxxczL+3Fc7LOFMvT+aaXjKlftqx4/Gr0T+kFlpsyd/llMVqAEU4eYB9olQxklD/o/REq5T/OThSj/4AaT3J22Wvid91rnj/6IYY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135529; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=eog4yjLiKBCFrEZ9kExFuwW9JAbFdVnm75M5Gn2JSvs=; b=Lumloeak/csDlluaTHTIRu9cqphwq4gfLBUvveGm8Clz0/WrAU2Nr7DOlh4zJghZ8g3PNaD3x4Q//ccOmWs82oSRKtgo3kSEEccCd1HnR30Tk62U0PXO3snyTdof0923HWmB2eSBZFgNE5CbZ1DuOsDzuZGY+cPuQY2tzEgPQ0M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70929+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1612135529653582.0966769319837; Sun, 31 Jan 2021 15:25:29 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id i9ZoYY1788612xoxRMhQDoLn; Sun, 31 Jan 2021 15:25:29 -0800 X-Received: from mail-qv1-f46.google.com (mail-qv1-f46.google.com [209.85.219.46]) by mx.groups.io with SMTP id smtpd.web09.26062.1612135523620719279 for ; Sun, 31 Jan 2021 15:25:23 -0800 X-Received: by mail-qv1-f46.google.com with SMTP id r13so2957273qvm.11 for ; Sun, 31 Jan 2021 15:25:23 -0800 (PST) X-Gm-Message-State: lvomlESZ6SRmwqoqiNtzaQ0Vx1787277AA= X-Google-Smtp-Source: ABdhPJyJVvRvvgV8HrlmGnxuK3FFgf3IXo9/Bz/US+BsP8fSH1ymRlOfRChzl8Ra2azOD89v+iYzxw== X-Received: by 2002:a0c:f008:: with SMTP id z8mr10928821qvk.21.1612135522606; Sun, 31 Jan 2021 15:25:22 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:22 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [edk2-devel] [PATCH v7 03/21] ArmPkg: Add register encoding definition for MMFR2 Date: Sun, 31 Jan 2021 16:24:53 -0700 Message-Id: <20210131232511.18340-4-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135529; bh=RW2ZxrmPofKyqYAtrXnt/rpwuY63aW/36NRRC3nNjRI=; h=Cc:Date:From:Reply-To:Subject:To; b=EYH4cUHRozn2eYzYlY2f4AOBpkh96Cfn3OkD7nnJiuLbwe26zJaPoS9OF6dWLWblD5y wiT208xUkAza6K7oyHMRFbQV3YBQSOZcZ0AM/ioub/O0OmRHMS1sdug105sP7DUeklPtx iPlcV0QWH1/6KFml37O/dewsqH+Jl6uqJm4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add register encoding definition for Memory Model Feature Register 2. We need to define it here because we build for ARMv8.0, which doesn't have it. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/Chipset/AArch64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArc= h64.h index 0ade5cce91c3..7c2b592f92ee 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -112,6 +112,10 @@ #define ARM_VECTOR_LOW_A32_FIQ 0x700 #define ARM_VECTOR_LOW_A32_SERR 0x780 =20 +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we +// build for ARMv8.0, we need to define the register here. +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + #define VECTOR_BASE(tbl) \ .section .text.##tbl##,"ax"; \ .align 11; \ --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:24 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [edk2-devel] [PATCH v7 04/21] ArmPkg: Add helper to read the Memory Model Features Register 2 Date: Sun, 31 Jan 2021 16:24:54 -0700 Message-Id: <20210131232511.18340-5-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135527; bh=VjlFQLX6gFlRfOu6C0WRiwx+v8yig7tkWgnJVxnu1qk=; h=Cc:Date:From:Reply-To:Subject:To; b=BPolKfCFWmoDWyyYX65LTRIcAWCp/QIkhZuzHeOBDhA4ja75XY5gSnwklS7EXci4Tzm XG/xDVPmdc6QcwvqVd/h2VNMf1A1Hhe0AloWD7M+2XH8RPdMLfV6x41Fgi8/80sL+aMaW gcS4UUdl/p9s3cHJ871h0a6zsI4XSXdYriI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add helper function to read the MMFR2 register. We will need this to determine CCIDX support. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h | 11 +++++++++++ ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 3 +++ 2 files changed, 14 insertions(+) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h b/ArmPkg/Library/Ar= mLib/AArch64/AArch64Lib.h index 85bcecda730f..cfc0c878a415 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h @@ -41,5 +41,16 @@ EFIAPI ArmReadIdAA64Pfr0 ( VOID ); + +/** Reads the ID_AA64MMFR2_EL1 register. + + @return The contents of the ID_AA64MMFR2_EL1 register. +**/ +UINTN +EFIAPI +ArmReadIdAA64Mmfr2 ( + VOID + ); + #endif // __AARCH64_LIB_H__ =20 diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Librar= y/ArmLib/AArch64/AArch64Support.S index 129205d2ac27..d3cc1e86716b 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -425,6 +425,9 @@ ASM_FUNC(ArmCallWFI) wfi ret =20 +ASM_FUNC(ArmReadIdAA64Mmfr2) + mrs x0, ID_AA64MMFR2_EL1 // read EL1 MMFR2 + ret =20 ASM_FUNC(ArmReadMpidr) mrs x0, mpidr_el1 // read EL1 MPIDR --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70930): https://edk2.groups.io/g/devel/message/70930 Mute This Topic: https://groups.io/mt/80271121/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70931+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70931+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135531; cv=none; d=zohomail.com; s=zohoarc; b=gdwAfyrtxnYqe7l89CyOEfPTAltTxpBrmU4UXx4nGRlBg1r8Kld1HmPyctzMheRIT8cgwf46U+sYmE/FsLSUlGWMmuOaJ16J24d8QslT+emDTlcEDnoOu3sOlxMsQcUvGcT3+lqYDBkAql7mExzw+c1BDUCoPqrH+GbokUalyiQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135531; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=aQOAHa92hUrxCJoGdjIiknSrXnT1S2bu8Tol9HC2lcs=; b=FvsZShU9EQlVJj/IPw8CZWbFcBW0jUcofBOOfq7y682C7In5+SxqKSUVhxPMIyS3J8d4K2z8/J1wj9KKoVTwov7Fi65mcGgQenWcWj/gFstdqRIPbbwzrsTamRngTsZkEfegzxKrk6x2t0cq83tds4Gn+5IBQ3F/X00houNodxc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70931+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1612135531630772.23793788994; Sun, 31 Jan 2021 15:25:31 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id QviCYY1788612xGagnKvEwUD; Sun, 31 Jan 2021 15:25:31 -0800 X-Received: from mail-qk1-f172.google.com (mail-qk1-f172.google.com [209.85.222.172]) by mx.groups.io with SMTP id smtpd.web09.26064.1612135527641438486 for ; Sun, 31 Jan 2021 15:25:27 -0800 X-Received: by mail-qk1-f172.google.com with SMTP id x81so14632655qkb.0 for ; Sun, 31 Jan 2021 15:25:27 -0800 (PST) X-Gm-Message-State: vAu9cWPnzZTXxFyEKVvJ4Mplx1787277AA= X-Google-Smtp-Source: ABdhPJzhSXoWNblQXwImqP3ejRfvyMAiKoiI3OF4kEJLcnkuVCgK4cMZwD6gHzUs+yx8/bFwSQ0yWQ== X-Received: by 2002:a37:bcc2:: with SMTP id m185mr11915339qkf.62.1612135526571; Sun, 31 Jan 2021 15:25:26 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:26 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [edk2-devel] [PATCH v7 05/21] ArmPkg: Add helper function to read the Memory Model Feature Register 4 Date: Sun, 31 Jan 2021 16:24:55 -0700 Message-Id: <20210131232511.18340-6-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135531; bh=fa4l8vlAL1+DD/rH3YPoChGyg/URXdXWEu6xk9UsAgg=; h=Cc:Date:From:Reply-To:Subject:To; b=tqVctpYNtMgc/gDtFsUR6tWtszz+g8kPeLBR50rSz4w/vIAcWVIoWW+3TpAMmjfxrDB Kir2YLLA4NDzkbvOr+Z62qdFSisIG8lwgVP4GsiqEDZrhbj+ce0K+bdMGZBHESrvTqlDH eLaUXgqVyWMaCeI5UtrtszHZOJpgtBokGUQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" In AARCH32, CCIDX support is indicated in the MMFR4 register - unlike under AARCH64 where it's in MMFR2. Add a helper function to read it. Signed-off-by: Rebecca Cran Reviewed-by: Sami Mujawar Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h | 8 ++++++-- ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S | 4 ++++ ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm | 4 ++++ 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h b/ArmPkg/Library/ArmLib/A= rm/ArmV7Lib.h index bb7bda0a3aeb..dcf6723b803b 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h @@ -48,9 +48,13 @@ ArmCleanInvalidateDataCacheEntryBySetWay ( IN UINTN SetWayFormat ); =20 -UINTN +/** Reads the ID_MMFR4 register. + + @return The contents of the ID_MMFR4 register. +**/ +UINT32 EFIAPI -ArmReadIdPfr0 ( +ArmReadIdMmfr4 ( VOID ); =20 diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S b/ArmPkg/Library/A= rmLib/Arm/ArmLibSupportV7.S index 01c91b10fcb7..a60a2f634132 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S @@ -60,6 +60,10 @@ ASM_FUNC(ArmDisableInterrupts) isb bx LR =20 +ASM_FUNC(ArmReadIdMmfr4) + mrc p15,0,r0,c0,c2,6 @ Read ID_MMFR4 Register + bx lr + // UINT32 // ReadCCSIDR ( // IN UINT32 CSSELR diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm b/ArmPkg/Library= /ArmLib/Arm/ArmLibSupportV7.asm index 26ffa331b929..1679b09b797a 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm @@ -64,6 +64,10 @@ isb bx LR =20 + RVCT_ASM_EXPORT ArmReadIdMmfr4 + mrc p15,0,r0,c0,c2,6 ; Read ID_MMFR4 Register + bx LR + // UINT32 // ReadCCSIDR ( // IN UINT32 CSSELR --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:28 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [edk2-devel] [PATCH v7 06/21] ArmPkg: Fix the return type of the ReadCCSIDR function Date: Sun, 31 Jan 2021 16:24:56 -0700 Message-Id: <20210131232511.18340-7-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135535; bh=xfAA+n/IHpIiZrYF8UtDDLxvV5+CbbvBrBR3If9En5g=; h=Cc:Date:From:Reply-To:Subject:To; b=ggn/8ceoYYjmZ2WB9Dxmxl+9A0pJ2j+ennYKk482YhexXcX6SoAr7DJbS/mMcFdTrP3 1IJ+aP0aIkqHQz2p1HaateN3cmHWYPSjTZ4zyMwfmqW1+ysBJ2OsIPHkUBy4nlDL29LUb CK//b81iBZdj56QA34gh484wwuWeuRzRiDA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" When CCIDX is supported, the Current Cache Size ID Register contains data above 32 bits: namely the number of sets. Avoid truncating this by returning a UINTN instead of UINT32. On AARCH32, the expanded number of sets data can be read via the CCSIDR2 register. Also, add Doxygen comments for the function. Signed-off-by: Rebecca Cran Reviewed-by: Sami Mujawar Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 9 ++++++++- ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S | 2 +- ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S | 2 +- ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm | 2 +- 4 files changed, 11 insertions(+), 4 deletions(-) diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/= ArmLibPrivate.h index 2e90739eb858..8959bdd9d73c 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -61,7 +61,14 @@ CPSRRead ( VOID ); =20 -UINT32 +/** Reads the CCSIDR register for the specified cache. + + @param CSSELR The CSSELR cache selection register value. + + @return The contents of the CCSIDR_EL1 register for the specified cache,= when in AARCH64 mode. + Returns the contents of the CCSIDR register in AARCH32 mode. +**/ +UINTN ReadCCSIDR ( IN UINT32 CSSELR ); diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S b/ArmPkg/Libra= ry/ArmLib/AArch64/ArmLibSupportV8.S index 0e8d21e2264f..0ae75e4cb9f9 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S @@ -84,7 +84,7 @@ ASM_FUNC(ArmDisableAllExceptions) ret =20 =20 -// UINT32 +// UINTN // ReadCCSIDR ( // IN UINT32 CSSELR // ) diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S b/ArmPkg/Library/A= rmLib/Arm/ArmLibSupportV7.S index a60a2f634132..af61dbee5261 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S @@ -64,7 +64,7 @@ ASM_FUNC(ArmReadIdMmfr4) mrc p15,0,r0,c0,c2,6 @ Read ID_MMFR4 Register bx lr =20 -// UINT32 +// UINTN // ReadCCSIDR ( // IN UINT32 CSSELR // ) diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm b/ArmPkg/Library= /ArmLib/Arm/ArmLibSupportV7.asm index 1679b09b797a..81f3cb79994c 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm @@ -68,7 +68,7 @@ mrc p15,0,r0,c0,c2,6 ; Read ID_MMFR4 Register bx LR =20 -// UINT32 +// UINTN // ReadCCSIDR ( // IN UINT32 CSSELR // ) --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:30 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [edk2-devel] [PATCH v7 07/21] ArmPkg: Update ArmLibPrivate.h with cache register definitions Date: Sun, 31 Jan 2021 16:24:57 -0700 Message-Id: <20210131232511.18340-8-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135532; bh=lKQqtt9U6+n3fHXos9/rI2sPqHILnZlExIfYmTjV+wU=; h=Cc:Date:From:Reply-To:Subject:To; b=g3/8EzURajAOUQ9rO1gft+fQ2aubABGXoxRWXVACB/TkV8OYoBWD6tDoRr/W4RSmuLV 43YBrcYfm5Y1CXqjJwwhAC0nRQ8taxf0CasRUjCSIiOgo+cj6JG3k+0Nx8KWue0Nj6qVl XIQ7En/lITJ9+IaRXIX7N7TF99N7FfwizMs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Update the cache definitions in ArmLibPrivate.h based on current ARMv8 documentation. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 97 ++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/= ArmLibPrivate.h index 8959bdd9d73c..a354ede0da51 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -1,5 +1,7 @@ /** @file + ArmLibPrivate.h =20 + Copyright (c) 2020, NUVIA Inc. All rights reserved.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -50,6 +52,101 @@ #define CACHE_ARCHITECTURE_UNIFIED (0UL) #define CACHE_ARCHITECTURE_SEPARATE (1UL) =20 + +/// Defines the structure of the CSSELR (Cache Size Selection) register +typedef union { + struct { + UINT32 InD :1; ///< Instruction not Data bit + UINT32 Level :3; ///< Cache level (zero based) + UINT32 TnD :1; ///< Allocation not Data bit + UINT32 Reserved :27; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSELR_DATA; + +/// The cache type values for the InD field of the CSSELR register +typedef enum +{ + /// Select the data or unified cache + CsselrCacheTypeDataOrUnified =3D 0, + /// Select the instruction cache + CsselrCacheTypeInstruction, + CsselrCacheTypeMax +} CSSELR_CACHE_TYPE; + +/// Defines the structure of the CCSIDR (Current Cache Size ID) register +typedef union { + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in ca= che) - 4) + UINT64 Associativity :10; ///< Associativity - 1 + UINT64 NumSets :15; ///< Number of sets in the cache -1 + UINT64 Unknown :4; ///< Reserved, UNKNOWN + UINT64 Reserved :32; ///< Reserved, RES0 + } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX= is not supported. + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in ca= che) - 4) + UINT64 Associativity :21; ///< Associativity - 1 + UINT64 Reserved1 :8; ///< Reserved, RES0 + UINT64 NumSets :24; ///< Number of sets in the cache -1 + UINT64 Reserved2 :8; ///< Reserved, RES0 + } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX = is supported. + struct { + UINT64 LineSize : 3; + UINT64 Associativity : 21; + UINT64 Reserved : 8; + UINT64 Unallocated : 32; + } BitsCcidxAA32; + UINT64 Data; ///< The entire 64-bit value +} CCSIDR_DATA; + +/// Defines the structure of the AARCH32 CCSIDR2 register. +typedef union { + struct { + UINT32 NumSets :24; ///< Number of sets in the cache - 1 + UINT32 Reserved :8; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CCSIDR2_DATA; + +/** Defines the structure of the CLIDR (Cache Level ID) register. + * + * The lower 32 bits are the same for both AARCH32 and AARCH64 + * so we can use the same structure for both. +**/ +typedef union { + struct { + UINT32 Ctype1 : 3; ///< Level 1 cache type + UINT32 Ctype2 : 3; ///< Level 2 cache type + UINT32 Ctype3 : 3; ///< Level 3 cache type + UINT32 Ctype4 : 3; ///< Level 4 cache type + UINT32 Ctype5 : 3; ///< Level 5 cache type + UINT32 Ctype6 : 3; ///< Level 6 cache type + UINT32 Ctype7 : 3; ///< Level 7 cache type + UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable + UINT32 LoC : 3; ///< Level of Coherency + UINT32 LoUU : 3; ///< Level of Unification Uniprocessor + UINT32 Icb : 3; ///< Inner Cache Boundary + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CLIDR_DATA; + +/// The cache types reported in the CLIDR register. +typedef enum { + /// No cache is present + ClidrCacheTypeNone =3D 0, + /// There is only an instruction cache + ClidrCacheTypeInstructionOnly, + /// There is only a data cache + ClidrCacheTypeDataOnly, + /// There are separate data and instruction caches + ClidrCacheTypeSeparate, + /// There is a unified cache + ClidrCacheTypeUnified, + ClidrCacheTypeMax +} CLIDR_CACHE_TYPE; + +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * level)) & 0b111) + VOID CPSRMaskInsert ( IN UINT32 Mask, --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:32 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [edk2-devel] [PATCH v7 08/21] ArmPkg: Add definition of the maximum cache level in ARMv8-A Date: Sun, 31 Jan 2021 16:24:58 -0700 Message-Id: <20210131232511.18340-9-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135539; bh=9MaaWkeBIAdzRPRZi72ZnvITex8p40Nw4zXyxNXkQOE=; h=Cc:Date:From:Reply-To:Subject:To; b=cHXkasqqlKBosKYuitLXhnyHmlyRFsgP6Tcaia7Bl9q/g36NtDNRa0AMAf34uWlwENJ iAhz8jdjtLAfouPVJVw38kmYt77TbefxUpHpy8MwaDtZC9wClmtszGKpeFTt70KUYGrE2 IWNR+9h6Z+t/+MQ078F+i7+YZ6GMWJ0G4xU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The ARM Architecture Reference Manual for ARMv8-A defines up to seven levels of cache, L1 through L7. Define MAX_ARM_CACHE_LEVEL to be 7. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/Library/ArmLib.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index 26cb05def0a2..fd4f06d24274 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -109,6 +109,10 @@ typedef enum { #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK) =20 +// The ARM Architecture Reference Manual for ARMv8-A defines up +// to 7 levels of cache, L1 through L7. +#define MAX_ARM_CACHE_LEVEL 7 + UINTN EFIAPI ArmDataCacheLineLength ( --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70934): https://edk2.groups.io/g/devel/message/70934 Mute This Topic: https://groups.io/mt/80271127/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70935+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70935+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135537; cv=none; d=zohomail.com; s=zohoarc; b=E+repuyhftz87Qbv6kACl/bl6qU86y7BrxWHIgvdvaxvO8gCKHFZ+1i2qGWQmQktTTYLJbktsKxHKe/c9XjwWnaHwv4oIQ/7QCLsoP1e9QhPQCqKmU4/lHiwDGfK5ZMmRxqmkdR4mmDuppNkCT38OGYeKhDW4lOsJfnyleEHKWM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135537; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xIrfTeda4sqiDcTPLHh67z95Db4UrhYDAY6DtkUj4P0=; b=cUfRhS8AGbCHp3RKu3D7CCmg0S0+UqM3QIeWSt+WzDllXfM0531YKagRIGzBFlaP/x0UTFh0JcgSl5T+fVq54zmP2jntf/AQs6GSZUoGSHBoOWd4KCb+r5S32jHLpQcxks2UnvxRk8ZI/odOcYT7M36ErI04uOWCfp081Zn4xeU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70935+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161213553712396.63867615255435; Sun, 31 Jan 2021 15:25:37 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id pxf6YY1788612xckrb8T0iR2; Sun, 31 Jan 2021 15:25:36 -0800 X-Received: from mail-qk1-f180.google.com (mail-qk1-f180.google.com [209.85.222.180]) by mx.groups.io with SMTP id smtpd.web11.26312.1612135536112669390 for ; Sun, 31 Jan 2021 15:25:36 -0800 X-Received: by mail-qk1-f180.google.com with SMTP id t63so14633889qkc.1 for ; Sun, 31 Jan 2021 15:25:36 -0800 (PST) X-Gm-Message-State: oNNA3j1IxAPohWskON1GeQ4Ex1787277AA= X-Google-Smtp-Source: ABdhPJxUsEsilfz3211AjLyLmlhMXn98Crql4rfUfbN90NyXBm39A6R0eIZabS3bVEMj5L/e/XOFMw== X-Received: by 2002:a37:9581:: with SMTP id x123mr13512478qkd.439.1612135534964; Sun, 31 Jan 2021 15:25:34 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:34 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [edk2-devel] [PATCH v7 09/21] ArmPkg: Add helper to read CCIDX status Date: Sun, 31 Jan 2021 16:24:59 -0700 Message-Id: <20210131232511.18340-10-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135536; bh=UrT34WUw784QUkukD3y7Asoig/j9jYCa1C6797b45Vc=; h=Cc:Date:From:Reply-To:Subject:To; b=TChyYHlkmmH0fhMUEvAli7zGt8iL5dkJMxjl04KwhzIZzKlPj1W8pycbqsMbfez5OO/ COi2f67QxM+b2D644DL9FT0+2OlUDIoIkZOskVXbJTpDCMWQhzZfiXaA8O8saCjIKdaZx CEzb5wYJ777gIyl4xa5sElzb1GM/c/esxxA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add a helper function to determine CCIDX support. Signed-off-by: Rebecca Cran Reviewed-by: Sami Mujawar Reviewed-by: Leif Lindholm --- ArmPkg/Include/Library/ArmLib.h | 11 +++++++++++ ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 19 ++++++++++++++++++- ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c | 19 ++++++++++++++++++- 3 files changed, 47 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index fd4f06d24274..70b9d816b74c 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -725,6 +725,17 @@ ArmHasGicSystemRegisters ( VOID ); =20 +/** Checks if CCIDX is implemented. + + @retval TRUE CCIDX is implemented. + @retval FALSE CCIDX is not implemented. +**/ +BOOLEAN +EFIAPI +ArmHasCcidx ( + VOID + ); + #ifdef MDE_CPU_ARM /// /// AArch32-only ID Register Helper functions diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/Ar= mLib/AArch64/AArch64Lib.c index 53e593bc994b..191a5fea31a1 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c @@ -2,7 +2,7 @@ =20 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2020, NUVIA Inc. All rights reserved.
+ Copyright (c) 2021, NUVIA Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -87,3 +87,20 @@ ArmHasGicSystemRegisters ( { return ((ArmReadIdAA64Pfr0 () & AARCH64_PFR0_GIC) !=3D 0); } + +/** Checks if CCIDX is implemented. + + @retval TRUE CCIDX is implemented. + @retval FALSE CCIDX is not implemented. +**/ +BOOLEAN +EFIAPI +ArmHasCcidx ( + VOID + ) +{ + UINTN Mmfr2; + + Mmfr2 =3D ArmReadIdAA64Mmfr2 (); + return (((Mmfr2 >> 20) & 0xF) =3D=3D 1) ? TRUE : FALSE; +} diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c b/ArmPkg/Library/ArmLib/A= rm/ArmV7Lib.c index 9f81a7223732..c5dd3f8b2f1c 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c @@ -2,7 +2,7 @@ =20 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. - Copyright (c) 2020, NUVIA Inc. All rights reserved.
+ Copyright (c) 2021, NUVIA Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -102,3 +102,20 @@ ArmHasSecurityExtensions ( { return ((ArmReadIdPfr1 () & ARM_PFR1_SEC) !=3D 0); } + +/** Checks if CCIDX is implemented. + + @retval TRUE CCIDX is implemented. + @retval FALSE CCIDX is not implemented. +**/ +BOOLEAN +EFIAPI +ArmHasCcidx ( + VOID + ) +{ + UINTN Mmfr4; + + Mmfr4 =3D ArmReadIdMmfr4 (); + return (((Mmfr4 >> 24) & 0xF) =3D=3D 1) ? TRUE : FALSE; +} --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:36 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 10/21] ArmPkg: Add helper to read the CCSIDR2 register Date: Sun, 31 Jan 2021 16:25:00 -0700 Message-Id: <20210131232511.18340-11-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135538; bh=t9CBvIhbXlg4I9fobKSzNROXuEs+NkJJMgNAJbQpWbE=; h=Cc:Date:From:Reply-To:Subject:To; b=q1Qr7tNIbGpqH3NDP4LBB8jxcKx2lHDDJcJxcO69NVPwrBb3RFLf63e/BMgD2puqPHn vDrib//gj3FcPybZPt8PXXvQ1fQXPVik52dRoSu1p0swNoxawNVI1xpUTqPAQVUZwcxEm v2rnYvX/DXvC+pvAp8SV74Tn7z4cehjT6wE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add helper function to read the CCSIDR2 register. This is used when CCIDX is supported in AARCH32 mode. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 11 +++++++++++ ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S | 10 ++++++++++ ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm | 10 ++++++++++ 3 files changed, 31 insertions(+) diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/= ArmLibPrivate.h index a354ede0da51..7c99121843f6 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -170,6 +170,17 @@ ReadCCSIDR ( IN UINT32 CSSELR ); =20 +/** Reads the CCSIDR2 for the specified cache. + + @param CSSELR The CSSELR cache selection register value + + @return The contents of the CCSIDR2 register for the specified cache. +**/ +UINT32 +ReadCCSIDR2 ( + IN UINT32 CSSELR + ); + UINT32 ReadCLIDR ( VOID diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S b/ArmPkg/Library/A= rmLib/Arm/ArmLibSupportV7.S index af61dbee5261..d843f91dfca8 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S @@ -74,6 +74,16 @@ ASM_FUNC(ReadCCSIDR) mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSID= R) bx lr =20 +// UINT32 +// ReadCCSIDR2 ( +// IN UINT32 CSSELR +// ) +ASM_FUNC(ReadCCSIDR2) + mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR) + isb + mrc p15,1,r0,c0,c0,2 @ Read current CP15 Cache Size ID Register (CCSID= R2) + bx lr + // UINT32 // ReadCLIDR ( // IN UINT32 CSSELR diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm b/ArmPkg/Library= /ArmLib/Arm/ArmLibSupportV7.asm index 81f3cb79994c..e14f1566258c 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm @@ -78,6 +78,16 @@ mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR) bx lr =20 +// UINT32 +// ReadCCSIDR2 ( +// IN UINT32 CSSELR +// ) + RVCT_ASM_EXPORT ReadCCSIDR2 + mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR) + isb + mrc p15,1,r0,c0,c0,2 ; Read current CP15 Cache Size ID Register (CCSIDR2) + bx lr + // UINT32 // ReadCLIDR ( // IN UINT32 CSSELR --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:38 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 11/21] ArmPkg: Add Library/OemMiscLib.h Date: Sun, 31 Jan 2021 16:25:01 -0700 Message-Id: <20210131232511.18340-12-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135545; bh=YzFbgcN2mVw3yd2iDYtJfl5ZohU2uOmLbDUwOBAOEJM=; h=Cc:Date:From:Reply-To:Subject:To; b=Ka7ladNWjuDGrwIgmoGHVbG18BYKslhWMTXQZXXQoYwOzTAsr/JLFrg++AekrYeKeOE LhkJQjT0uPWOlwnOBD3u9XFkV2xHadjzcXl5H+eNESNeu+ESFALA7UnuP8qin6woQL7l1 +aV2lew848yspuvcEtGpz4zBj/W0c3JXD9E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" OemMiscLib.h provides the interface which platforms should implement to interact with the SmbiosMiscDxe and ProcessorSubClassDxe drivers to update SMBIOS tables. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm --- ArmPkg/Include/Library/OemMiscLib.h | 166 ++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/ArmPkg/Include/Library/OemMiscLib.h b/ArmPkg/Include/Library/O= emMiscLib.h new file mode 100644 index 000000000000..a14eb36a60e3 --- /dev/null +++ b/ArmPkg/Include/Library/OemMiscLib.h @@ -0,0 +1,166 @@ +/** @file +* +* Copyright (c) 2021, NUVIA Inc. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + + +#ifndef OEM_MISC_LIB_H_ +#define OEM_MISC_LIB_H_ + +#include +#include + +typedef enum +{ + CpuCacheL1 =3D 0, + CpuCacheL2, + CpuCacheL3, + CpuCacheL4, + CpuCacheL5, + CpuCacheL6, + CpuCacheL7, + CpuCacheLevelMax +} OEM_MISC_CPU_CACHE_LEVEL; + +typedef struct +{ + UINT8 Voltage; ///< Processor voltage + UINT16 CurrentSpeed; ///< Current clock speed in MHz + UINT16 MaxSpeed; ///< Maximum clock speed in MHz + UINT16 ExternalClock; ///< External clock speed in MHz + UINT16 CoreCount; ///< Number of cores available + UINT16 CoresEnabled; ///< Number of cores enabled + UINT16 ThreadCount; ///< Number of threads per processor +} OEM_MISC_PROCESSOR_DATA; + +typedef enum +{ + ProductNameType01, + SerialNumType01, + UuidType01, + SystemManufacturerType01, + SkuNumberType01, + FamilyType01, + AssertTagType02, + SerialNumberType02, + BoardManufacturerType02, + SkuNumberType02, + ChassisLocationType02, + AssetTagType03, + SerialNumberType03, + VersionType03, + ChassisTypeType03, + ManufacturerType03, + SkuNumberType03, + SmbiosHiiStringFieldMax +} OEM_MISC_SMBIOS_HII_STRING_FIELD; + +/* + * The following are functions that the each platform needs to + * implement in its OemMiscLib library. + */ + +/** Gets the CPU frequency of the specified processor. + + @param ProcessorIndex Index of the processor to get the frequency for. + + @return CPU frequency in Hz +**/ +EFIAPI +UINTN +OemGetCpuFreq ( + IN UINT8 ProcessorIndex + ); + +/** Gets information about the specified processor and stores it in + the structures provided. + + @param ProcessorIndex Index of the processor to get the information for. + @param ProcessorStatus Processor status. + @param ProcessorCharacteristics Processor characteritics. + @param MiscProcessorData Miscellaneous processor information. + + @return TRUE on success, FALSE on failure. +**/ +EFIAPI +BOOLEAN +OemGetProcessorInformation ( + IN UINTN ProcessorIndex, + IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus, + IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics, + IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData + ); + +/** Gets information about the cache at the specified cache level. + + @param ProcessorIndex The processor to get information for. + @param CacheLevel The cache level to get information for. + @param InstructionOrUnifiedCache Whether the cache is instruction or + unified, not data. + @param SmbiosCacheTable The SMBIOS Type7 cache information structure. + + @return TRUE on success, FALSE on failure. +**/ +EFIAPI +BOOLEAN +OemGetCacheInformation ( + IN UINT8 ProcessorIndex, + IN UINT8 CacheLevel, + IN BOOLEAN InstructionOrUnifiedCache, + IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable + ); + +/** Gets the maximum number of sockets supported by the platform. + + @return The maximum number of sockets. +**/ +EFIAPI +UINT8 +OemGetProcessorMaxSockets ( + VOID + ); + +/** Gets the type of chassis for the system. + + @param ChassisType The type of the chassis. + + @retval EFI_SUCCESS The chassis type was fetched successfully. +**/ +EFIAPI +EFI_STATUS +OemGetChassisType ( + OUT UINT8 *ChassisType + ); + +/** Returns whether the specified processor is present or not. + + @param ProcessIndex The processor index to check. + + @return TRUE is the processor is present, FALSE otherwise. +**/ +EFIAPI +BOOLEAN +OemIsSocketPresent ( + IN UINTN ProcessorIndex + ); + +/** Updates the HII string for the specified field. + + @param mHiiHandle The HII handle. + @param TokenToUpdate The string to update. + @param Offset The field to get information about. +**/ +EFIAPI +VOID +OemUpdateSmbiosInfo ( + IN EFI_HII_HANDLE HiiHandle, + IN EFI_STRING_ID TokenToUpdate, + IN OEM_MISC_SMBIOS_HII_STRING_FIELD Offset + ); + +#endif // OEM_MISC_LIB_H_ --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:40 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 12/21] ArmPkg: Add Universal/Smbios/OemMiscLibNull Date: Sun, 31 Jan 2021 16:25:02 -0700 Message-Id: <20210131232511.18340-13-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135542; bh=yhi9EmOce0fOv78bdWfip55/3fkF5uR1PIQiPWgzAog=; h=Cc:Date:From:Reply-To:Subject:To; b=kGZ0mbg4c54bcuM9WzF2cP1DAO3XCpPYc1wRZmC5xaToJNPnoRI9a6waTUV5ZTdP+g8 PFHEUeCH30JZMKNw1DQ2hBy9eIuXRS7L1Ey15zb1M529KkjTfMW19H3BYdUQdRGbBlBW2 fbjPE8YQcX/qtLphJeW/NoeFQjymJJTTLX0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add a Null implementation of OemMiscLib. OemMiscLib provides functions that platforms implement to fill in SMBIOS information for the SmbiosMiscDxe and ProcessSubClassDxe drivers. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm --- ArmPkg/ArmPkg.dsc | 2 + ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf | 31 +++++ ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c | 143 ++++++++++= ++++++++++ 3 files changed, 176 insertions(+) diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc index 48059cf38ed3..0f77a6da4483 100644 --- a/ArmPkg/ArmPkg.dsc +++ b/ArmPkg/ArmPkg.dsc @@ -84,6 +84,8 @@ [LibraryClasses.common] =20 ArmMtlLib|ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.inf =20 + OemMiscLib|ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf + [LibraryClasses.common.PEIM] HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf diff --git a/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf b/Ar= mPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf new file mode 100644 index 000000000000..b21eeade64b5 --- /dev/null +++ b/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf @@ -0,0 +1,31 @@ +#/** @file +# OemMiscLib.inf +# +# Copyright (c) 2021, NUVIA Inc. All rights reserved. +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D OemMiscLibNull + FILE_GUID =3D e80b8e6b-fffb-4c39-b433-41de67c9d7b8 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D OemMiscLib + +[Sources.common] + OemMiscLib.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseMemoryLib + diff --git a/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c b/ArmPkg/U= niversal/Smbios/OemMiscLibNull/OemMiscLib.c new file mode 100644 index 000000000000..8233904647e5 --- /dev/null +++ b/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c @@ -0,0 +1,143 @@ +/** @file +* OemMiscLib.c +* +* Copyright (c) 2021, NUVIA Inc. All rights reserved. +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include + +#include + + +/** Gets the CPU frequency of the specified processor. + + @param ProcessorIndex Index of the processor to get the frequency for. + + @return CPU frequency in Hz +**/ +EFIAPI +UINTN +OemGetCpuFreq ( + IN UINT8 ProcessorIndex + ) +{ + ASSERT (FALSE); + return 0; +} + +/** Gets information about the specified processor and stores it in + the structures provided. + + @param ProcessorIndex Index of the processor to get the information for. + @param ProcessorStatus Processor status. + @param ProcessorCharacteristics Processor characteritics. + @param MiscProcessorData Miscellaneous processor information. + + @return TRUE on success, FALSE on failure. +**/ +EFIAPI +BOOLEAN +OemGetProcessorInformation ( + IN UINTN ProcessorIndex, + IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus, + IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics, + IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData + ) +{ + ASSERT (FALSE); + return TRUE; +} + +/** Gets information about the cache at the specified cache level. + + @param ProcessorIndex The processor to get information for. + @param CacheLevel The cache level to get information for. + @param InstructionOrUnifiedCache Whether the cache is instruction or + unified, not data. + @param SmbiosCacheTable The SMBIOS Type7 cache information structure. + + @return TRUE on success, FALSE on failure. +**/ +EFIAPI +BOOLEAN +OemGetCacheInformation ( + IN UINT8 ProcessorIndex, + IN UINT8 CacheLevel, + IN BOOLEAN InstructionOrUnifiedCache, + IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable + ) +{ + ASSERT (FALSE); + return TRUE; +} + +/** Gets the maximum number of sockets supported by the platform. + + @return The maximum number of sockets. +**/ +EFIAPI +UINT8 +OemGetProcessorMaxSockets ( + VOID + ) +{ + ASSERT (FALSE); + return 1; +} + +/** Gets the type of chassis for the system. + + @param ChassisType The type of the chassis. + + @retval EFI_SUCCESS The chassis type was fetched successfully. +**/ +EFI_STATUS +EFIAPI +OemGetChassisType ( + UINT8 *ChassisType + ) +{ + ASSERT (FALSE); + *ChassisType =3D MiscChassisTypeUnknown; + return EFI_SUCCESS; +} + +/** Returns whether the specified processor is present or not. + + @param ProcessIndex The processor index to check. + + @return TRUE is the processor is present, FALSE otherwise. +**/ +EFIAPI +BOOLEAN +OemIsSocketPresent ( + IN UINTN ProcessorIndex + ) +{ + ASSERT (FALSE); + return FALSE; +} + +/** Updates the HII string for the specified field. + + @param mHiiHandle The HII handle. + @param TokenToUpdate The string to update. + @param Offset The field to get information about. +**/ +EFIAPI +VOID +OemUpdateSmbiosInfo ( + IN EFI_HII_HANDLE mHiiHandle, + IN EFI_STRING_ID TokenToUpdate, + IN OEM_MISC_SMBIOS_HII_STRING_FIELD Offset + ) +{ + ASSERT (FALSE); +} --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:42 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 13/21] ArmPkg: Add Universal/Smbios/ProcessorSubClassDxe Date: Sun, 31 Jan 2021 16:25:03 -0700 Message-Id: <20210131232511.18340-14-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135545; bh=po2rf7mZ8JlEVqVjlD//OIHKSKmhJh1QS5zVViq1cFQ=; h=Cc:Date:From:Reply-To:Subject:To; b=GGFPa4lYlwzZkYesfcbE6ueqsKVfvUQvHlRD4qFMRzQzHawfrZCsQeHOi3vhcfmHx4b R2LxiZSFhVsVm9Beeb+LEvAqjVq5LeIdYECyV+3uiHOiWgurpX6KNNbOZqlU1qjjHQ6VK Mt8ul8kZg54++H+QBZIan1bxySKFTx/at9k= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" ProcessorSubClassDxe provides SMBIOS CPU information using generic methods combined with calls into OemMiscLib. Signed-off-by: Rebecca Cran Reviewed-by: Samer El-Haj-Mahmoud --- ArmPkg/ArmPkg.dsc = | 2 + ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf = | 65 ++ ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessor.h = | 106 +++ ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c = | 766 ++++++++++++++++++++ ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c = | 97 +++ ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c = | 103 +++ ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c = | 250 +++++++ ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings.uni = | 24 + 8 files changed, 1413 insertions(+) diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc index 0f77a6da4483..fce86cb6d710 100644 --- a/ArmPkg/ArmPkg.dsc +++ b/ArmPkg/ArmPkg.dsc @@ -148,6 +148,8 @@ [Components.common] ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf =20 + ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + [Components.AARCH64] ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass= Dxe.inf b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe= .inf new file mode 100644 index 000000000000..d74e365375b3 --- /dev/null +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf @@ -0,0 +1,65 @@ +#/** @file +# ProcessorSubClassDxe.inf +# +# Copyright (c) 2021, NUVIA Inc. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D ProcessorSubClass + FILE_GUID =3D f3fe0e33-ea38-4069-9fb5-be23407207c7 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ProcessorSubClassEntryPoint + +[Sources] + SmbiosProcessorArmCommon.c + ProcessorSubClass.c + ProcessorSubClassStrings.uni + +[Sources.AARCH64] + SmbiosProcessorAArch64.c + +[Sources.ARM] + SmbiosProcessorArm.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + ArmSmcLib + BaseLib + BaseMemoryLib + DebugLib + HiiLib + IoLib + MemoryAllocationLib + OemMiscLib + PcdLib + PrintLib + UefiDriverEntryPoint + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Pcd] + gArmTokenSpaceGuid.PcdProcessorManufacturer + gArmTokenSpaceGuid.PcdProcessorVersion + gArmTokenSpaceGuid.PcdProcessorSerialNumber + gArmTokenSpaceGuid.PcdProcessorAssetTag + gArmTokenSpaceGuid.PcdProcessorPartNumber + +[Guids] + + +[Depex] + gEfiSmbiosProtocolGuid diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessor.h= b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessor.h new file mode 100644 index 000000000000..002fd6cc142b --- /dev/null +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessor.h @@ -0,0 +1,106 @@ +/** @file + SMBIOS Processor Related Functions. + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMBIOS_PROCESSOR_H_ +#define SMBIOS_PROCESSOR_H_ + +#include +#include + +/** Returns the maximum cache level implemented by the current CPU. + + @return The maximum cache level implemented. +**/ +UINT8 +SmbiosProcessorGetMaxCacheLevel ( + VOID + ); + +/** Returns whether or not the specified cache level has separate I/D cach= es. + + @param CacheLevel The cache level (L1, L2 etc.). Zero based. + + @return TRUE if the cache level has separate I/D caches, FALSE otherwi= se. +**/ +BOOLEAN +SmbiosProcessorHasSeparateCaches ( + UINT8 CacheLevel + ); + +/** Gets the size of the specified cache. + + @param CacheLevel The cache level (L1, L2 etc.). Zero based. + @param InstructionCache Whether the cache is a dedicated instruction c= ache. + @param DataCache Whether the cache is a dedicated data cache. + @param UnifiedCache Whether the cache is a unified cache. + + @return The cache size. +**/ +UINT64 +SmbiosProcessorGetCacheSize ( + IN UINT8 CacheLevel, + IN BOOLEAN InstructionCache, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache + ); + +/** Gets the associativity of the specified cache. + + @param CacheLevel The cache level (L1, L2 etc.). Zero based. + @param InstructionCache Whether the cache is a dedicated instruction c= ache. + @param DataCache Whether the cache is a dedicated data cache. + @param UnifiedCache Whether the cache is a unified cache. + + @return The cache associativity. +**/ +UINT32 +SmbiosProcessorGetCacheAssociativity ( + IN UINT8 CacheLevel, + IN BOOLEAN InstructionCache, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache + ); + +/** Returns a value for the Processor ID field that conforms to SMBIOS + requirements. + + @return Processor ID. +**/ +UINT64 +SmbiosGetProcessorId (VOID); + +/** Returns the external clock frequency. + + @return The external CPU clock frequency. +**/ +UINTN +SmbiosGetExternalClockFrequency (VOID); + +/** Returns the SMBIOS ProcessorFamily field value. + + @return The value for the ProcessorFamily field. +**/ +UINT8 +SmbiosGetProcessorFamily (VOID); + +/** Returns the ProcessorFamily2 field value. + + @return The value for the ProcessorFamily2 field. +**/ +UINT16 +SmbiosGetProcessorFamily2 (VOID); + +/** Returns the SMBIOS Processor Characteristics. + + @return Processor Characteristics bitfield. +**/ +PROCESSOR_CHARACTERISTIC_FLAGS +SmbiosGetProcessorCharacteristics (VOID); + +#endif // SMBIOS_PROCESSOR_H_ diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass= .c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c new file mode 100644 index 000000000000..ca55bc019f96 --- /dev/null +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -0,0 +1,766 @@ +/** @file + ProcessorSubClass.c + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved. + Copyright (c) 2015, Linaro Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SmbiosProcessor.h" + +extern UINT8 ProcessorSubClassStrings[]; + +#define CACHE_SOCKETED_SHIFT 3 +#define CACHE_LOCATION_SHIFT 5 +#define CACHE_ENABLED_SHIFT 7 +#define CACHE_OPERATION_MODE_SHIFT 8 + +typedef enum { + CacheModeWriteThrough =3D 0, ///< Cache is write-through + CacheModeWriteBack, ///< Cache is write-back + CacheModeVariesWithAddress, ///< Cache mode varies by address + CacheModeUnknown, ///< Cache mode is unknown + CacheModeMax +} CACHE_OPERATION_MODE; + +typedef enum { + CacheLocationInternal =3D 0, ///< Cache is internal to the processor + CacheLocationExternal, ///< Cache is external to the processor + CacheLocationReserved, ///< Reserved + CacheLocationUnknown, ///< Cache location is unknown + CacheLocationMax +} CACHE_LOCATION; + +EFI_HII_HANDLE mHiiHandle; + +EFI_SMBIOS_PROTOCOL *mSmbios; + +SMBIOS_TABLE_TYPE4 mSmbiosProcessorTableTemplate =3D { + { // Hdr + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE4), // Length + 0 // Handle + }, + 1, // Socket + CentralProcessor, // ProcessorType + ProcessorFamilyIndicatorFamily2, // ProcessorFamily + 2, // ProcessorManufacture + { // ProcessorId + { // Signature + 0 + }, + { // FeatureFlags + 0 + } + }, + 3, // ProcessorVersion + { // Voltage + 0 + }, + 0, // ExternalClock + 0, // MaxSpeed + 0, // CurrentSpeed + 0, // Status + ProcessorUpgradeUnknown, // ProcessorUpgrade + 0xFFFF, // L1CacheHandle + 0xFFFF, // L2CacheHandle + 0xFFFF, // L3CacheHandle + 4, // SerialNumber + 5, // AssetTag + 6, // PartNumber + 0, // CoreCount + 0, //EnabledCoreCount + 0, // ThreadCount + 0, // ProcessorCharacteristics + ProcessorFamilyARM, // ProcessorFamily2 + 0, // CoreCount2 + 0, // EnabledCoreCount2 + 0 // ThreadCount2 +}; + +/** Sets the HII variable `StringId` is `Pcd` isn't empty. + + @param Pcd The FixedAtBuild PCD that contains the string to fetc= h. + @param StringId The string identifier to set. +**/ +#define SET_HII_STRING_IF_PCD_NOT_EMPTY(Pcd, StringId) \ + do { \ + CHAR16 *Str; \ + Str =3D (CHAR16*)PcdGetPtr (Pcd); \ + if (StrLen (Str) > 0) { \ + HiiSetString (mHiiHandle, StringId, Str, NULL); \ + } \ + } while (0) + +/** Fetches the specified processor's frequency in Hz. + + @param ProcessorNumber The processor number + + @return The clock frequency in MHz + +**/ +UINT16 +GetCpuFrequency ( + IN UINT8 ProcessorNumber + ) +{ + return (UINT16)(OemGetCpuFreq (ProcessorNumber) / 1000 / 1000); +} + +/** Gets a description of the specified cache. + + @param[in] CacheLevel Zero-based cache level (e.g. L1 cache is 0). + @param[in] InstructionCache Cache is an instruction cache. + @param[in] DataCache Cache is a data cache. + @param[in] UnifiedCache Cache is a unified cache. + @param[out] CacheSocketStr The description of the specified cache + + @return The number of Unicode characters in CacheSocketStr not including= the + terminating NUL. +**/ +UINTN +GetCacheSocketStr ( + IN UINT8 CacheLevel, + IN BOOLEAN InstructionCache, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache, + OUT CHAR16 *CacheSocketStr + ) +{ + UINTN CacheSocketStrLen; + + if (CacheLevel =3D=3D CpuCacheL1 && InstructionCache) { + CacheSocketStrLen =3D UnicodeSPrint ( + CacheSocketStr, + SMBIOS_STRING_MAX_LENGTH - 1, + L"L%x Instruction Cache", + CacheLevel + 1); + } else if (CacheLevel =3D=3D CpuCacheL1 && DataCache) { + CacheSocketStrLen =3D UnicodeSPrint (CacheSocketStr, + SMBIOS_STRING_MAX_LENGTH - 1, + L"L%x Data Cache", + CacheLevel + 1); + } else { + CacheSocketStrLen =3D UnicodeSPrint (CacheSocketStr, + SMBIOS_STRING_MAX_LENGTH - 1, + L"L%x Cache", + CacheLevel + 1); + } + + return CacheSocketStrLen; +} + +/** Fills in the Type 7 record with the cache architecture information + read from the CPU registers. + + @param[in] CacheLevel Cache level (e.g. L1, L2). + @param[in] InstructionCache Cache is an instruction cache. + @param[in] DataCache Cache is a data cache. + @param[in] UnifiedCache Cache is a unified cache. + @param[out] Type7Record The Type 7 record to fill in. + +**/ +VOID +ConfigureCacheArchitectureInformation ( + IN UINT8 CacheLevel, + IN BOOLEAN InstructionCache, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache, + OUT SMBIOS_TABLE_TYPE7 *Type7Record + ) +{ + UINT8 Associativity; + UINT32 CacheSize32; + UINT16 CacheSize16; + UINT64 CacheSize64; + + ASSERT (InstructionCache || DataCache || UnifiedCache); + + if (InstructionCache) { + Type7Record->SystemCacheType =3D CacheTypeInstruction; + } else if (DataCache) { + Type7Record->SystemCacheType =3D CacheTypeData; + } else if (UnifiedCache) { + Type7Record->SystemCacheType =3D CacheTypeUnified; + } else { + ASSERT(FALSE); + } + + CacheSize64 =3D SmbiosProcessorGetCacheSize (CacheLevel, + InstructionCache, + DataCache, + UnifiedCache + ); + + Associativity =3D SmbiosProcessorGetCacheAssociativity (CacheLevel, + InstructionCache, + DataCache, + UnifiedCache + ); + + CacheSize64 /=3D 1024; // Minimum granularity is 1K + + // Encode the cache size into the format SMBIOS wants + if (CacheSize64 < MAX_INT16) { + CacheSize16 =3D CacheSize64; + CacheSize32 =3D CacheSize16; + } else if ((CacheSize64 / 64) < MAX_INT16) { + CacheSize16 =3D (1 << 15) | (CacheSize64 / 64); + CacheSize32 =3D CacheSize16; + } else { + if ((CacheSize64 / 1024) <=3D 2047) { + CacheSize32 =3D CacheSize64; + } else { + CacheSize32 =3D (1 << 31) | (CacheSize64 / 64); + } + + CacheSize16 =3D -1; + } + + Type7Record->Associativity =3D Associativity + 1; + Type7Record->MaximumCacheSize =3D CacheSize16; + Type7Record->InstalledSize =3D CacheSize16; + Type7Record->MaximumCacheSize2 =3D CacheSize32; + Type7Record->InstalledSize2 =3D CacheSize32; + + switch (Associativity + 1) { + case 2: + Type7Record->Associativity =3D CacheAssociativity2Way; + break; + case 4: + Type7Record->Associativity =3D CacheAssociativity4Way; + break; + case 8: + Type7Record->Associativity =3D CacheAssociativity8Way; + break; + case 16: + Type7Record->Associativity =3D CacheAssociativity16Way; + break; + case 12: + Type7Record->Associativity =3D CacheAssociativity12Way; + break; + case 24: + Type7Record->Associativity =3D CacheAssociativity24Way; + break; + case 32: + Type7Record->Associativity =3D CacheAssociativity32Way; + break; + case 48: + Type7Record->Associativity =3D CacheAssociativity48Way; + break; + case 64: + Type7Record->Associativity =3D CacheAssociativity64Way; + break; + case 20: + Type7Record->Associativity =3D CacheAssociativity20Way; + break; + default: + Type7Record->Associativity =3D CacheAssociativityOther; + break; + } + + Type7Record->CacheConfiguration =3D (CacheModeUnknown << CACHE_OPERATION= _MODE_SHIFT) | + (1 << CACHE_ENABLED_SHIFT) | + (CacheLocationUnknown << CACHE_LOCATIO= N_SHIFT) | + (0 << CACHE_SOCKETED_SHIFT) | + CacheLevel; +} + + +/** Allocates and initializes an SMBIOS_TABLE_TYPE7 structure. + + @param[in] CacheLevel The cache level (L1-L7). + @param[in] InstructionCache Cache is an instruction cache. + @param[in] DataCache Cache is a data cache. + @param[in] UnifiedCache Cache is a unified cache. + + @return A pointer to the Type 7 structure. Returns NULL on failure. +**/ +SMBIOS_TABLE_TYPE7 * +AllocateAndInitCacheInformation ( + IN UINT8 CacheLevel, + IN BOOLEAN InstructionCache, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache + ) +{ + SMBIOS_TABLE_TYPE7 *Type7Record; + EFI_STRING CacheSocketStr; + UINTN CacheSocketStrLen; + UINTN StringBufferSize; + CHAR8 *OptionalStrStart; + UINTN TableSize; + + // Allocate and fetch the cache description + StringBufferSize =3D sizeof (CHAR16) * SMBIOS_STRING_MAX_LENGTH; + CacheSocketStr =3D AllocateZeroPool (StringBufferSize); + if (CacheSocketStr =3D=3D NULL) { + return NULL; + } + + CacheSocketStrLen =3D GetCacheSocketStr (CacheLevel, + InstructionCache, + DataCache, + UnifiedCache, + CacheSocketStr); + + TableSize =3D sizeof (SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1; + Type7Record =3D AllocateZeroPool (TableSize); + if (Type7Record =3D=3D NULL) { + FreePool(CacheSocketStr); + return NULL; + } + + Type7Record->Hdr.Type =3D EFI_SMBIOS_TYPE_CACHE_INFORMATION; + Type7Record->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE7); + Type7Record->Hdr.Handle =3D SMBIOS_HANDLE_PI_RESERVED; + + Type7Record->SocketDesignation =3D 1; + + Type7Record->SupportedSRAMType.Unknown =3D 1; + Type7Record->CurrentSRAMType.Unknown =3D 1; + Type7Record->CacheSpeed =3D 0; + Type7Record->ErrorCorrectionType =3D CacheErrorUnknown; + + OptionalStrStart =3D (CHAR8 *)(Type7Record + 1); + UnicodeStrToAsciiStrS (CacheSocketStr, OptionalStrStart, CacheSocketStrL= en + 1); + FreePool (CacheSocketStr); + + return Type7Record; +} + +/** + Add Type 7 SMBIOS Record for Cache Information. + + @param[in] ProcessorIndex Processor number of specified processo= r. + @param[out] L1CacheHandle Pointer to the handle of the L1 Cache = SMBIOS record. + @param[out] L2CacheHandle Pointer to the handle of the L2 Cache = SMBIOS record. + @param[out] L3CacheHandle Pointer to the handle of the L3 Cache = SMBIOS record. + +**/ +VOID +AddSmbiosCacheTypeTable ( + IN UINTN ProcessorIndex, + OUT EFI_SMBIOS_HANDLE *L1CacheHandle, + OUT EFI_SMBIOS_HANDLE *L2CacheHandle, + OUT EFI_SMBIOS_HANDLE *L3CacheHandle + ) +{ + EFI_STATUS Status; + SMBIOS_TABLE_TYPE7 *Type7Record; + EFI_SMBIOS_HANDLE SmbiosHandle; + UINT8 CacheLevel; + UINT8 MaxCacheLevel; + BOOLEAN DataCacheType; + BOOLEAN SeparateCaches; + + Status =3D EFI_SUCCESS; + + MaxCacheLevel =3D 0; + + // See if there's an L1 cache present. + MaxCacheLevel =3D SmbiosProcessorGetMaxCacheLevel (); + + if (MaxCacheLevel < 1) { + return; + } + + for (CacheLevel =3D 0; CacheLevel < MaxCacheLevel; CacheLevel++) { + Type7Record =3D NULL; + + SeparateCaches =3D SmbiosProcessorHasSeparateCaches (CacheLevel); + + // At each level of cache, we can have a single type (unified, instruc= tion or data), + // or two types - separate data and instruction caches. If we have sep= arate + // instruction and data caches, then on the first iteration (CacheSubL= evel =3D 0) + // process the instruction cache. + for (DataCacheType =3D 0; DataCacheType <=3D 1; DataCacheType++) { + // If there's no separate data/instruction cache, skip the second it= eration + if (DataCacheType > 0 && !SeparateCaches) { + continue; + } + + Type7Record =3D AllocateAndInitCacheInformation (CacheLevel, + DataCacheType =3D=3D = 0 && SeparateCaches, + DataCacheType =3D=3D = 1, + DataCacheType =3D=3D = 0 && !SeparateCaches + ); + if (Type7Record =3D=3D NULL) { + continue; + } + + ConfigureCacheArchitectureInformation(CacheLevel, + (DataCacheType =3D=3D 0) && Se= parateCaches, + DataCacheType =3D=3D 1, + (DataCacheType =3D=3D 0) && !S= eparateCaches, + Type7Record + ); + + // Allow the platform to fill in other information such as speed, SR= AM type etc. + if (!OemGetCacheInformation (ProcessorIndex, CacheLevel, + DataCacheType =3D=3D 0, Type7Record)) { + continue; + } + + SmbiosHandle =3D SMBIOS_HANDLE_PI_RESERVED; + // Finally, install the table + Status =3D mSmbios->Add (mSmbios, NULL, &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *)Type7Record); + if (EFI_ERROR (Status)) { + continue; + } + + // Config L1/L2/L3 Cache Handle + switch (CacheLevel) { + case CpuCacheL1: + *L1CacheHandle =3D SmbiosHandle; + break; + case CpuCacheL2: + *L2CacheHandle =3D SmbiosHandle; + break; + case CpuCacheL3: + *L3CacheHandle =3D SmbiosHandle; + break; + default: + break; + } + } + } +} + +/** Allocates a Type 4 Processor Information structure and sets the + strings following the data fields. + + @param[out] Type4Record The Type 4 structure to allocate and initiali= ze + @param[in] ProcessorIndex The index of the processor socket + @param[in] Populated Whether the specified processor socket is + populated. + + @retval EFI_SUCCESS The Type 4 structure was successfully + allocated and the strings initialized. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory needed. +**/ +EFI_STATUS +AllocateType4AndSetProcessorInformationStrings ( + SMBIOS_TABLE_TYPE4 **Type4Record, + UINT8 ProcessorIndex, + BOOLEAN Populated + ) +{ + EFI_STATUS Status; + EFI_STRING_ID ProcessorManu; + EFI_STRING_ID ProcessorVersion; + EFI_STRING_ID SerialNumber; + EFI_STRING_ID AssetTag; + EFI_STRING_ID PartNumber; + EFI_STRING ProcessorSocketStr; + EFI_STRING ProcessorManuStr; + EFI_STRING ProcessorVersionStr; + EFI_STRING SerialNumberStr; + EFI_STRING AssetTagStr; + EFI_STRING PartNumberStr; + CHAR8 *OptionalStrStart; + CHAR8 *StrStart; + UINTN ProcessorSocketStrLen; + UINTN ProcessorManuStrLen; + UINTN ProcessorVersionStrLen; + UINTN SerialNumberStrLen; + UINTN AssetTagStrLen; + UINTN PartNumberStrLen; + UINTN TotalSize; + UINTN StringBufferSize; + + Status =3D EFI_SUCCESS; + + ProcessorManuStr =3D NULL; + ProcessorVersionStr =3D NULL; + SerialNumberStr =3D NULL; + AssetTagStr =3D NULL; + PartNumberStr =3D NULL; + + ProcessorManu =3D STRING_TOKEN (STR_PROCESSOR_MANUFACTURE); + ProcessorVersion =3D STRING_TOKEN (STR_PROCESSOR_VERSION); + SerialNumber =3D STRING_TOKEN (STR_PROCESSOR_SERIAL_NUMBER); + AssetTag =3D STRING_TOKEN (STR_PROCESSOR_ASSET_TAG); + PartNumber =3D STRING_TOKEN (STR_PROCESSOR_PART_NUMBER); + + SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorManufacturer, ProcessorManu= ); + SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorVersion, ProcessorVersion); + SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorSerialNumber, SerialNumber); + SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorAssetTag, AssetTag); + SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorPartNumber, PartNumber); + + // Processor Socket Designation + StringBufferSize =3D sizeof (CHAR16) * SMBIOS_STRING_MAX_LENGTH; + ProcessorSocketStr =3D AllocateZeroPool (StringBufferSize); + if (ProcessorSocketStr =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ProcessorSocketStrLen =3D UnicodeSPrint (ProcessorSocketStr, StringBuffe= rSize, + L"CPU%02d", ProcessorIndex + 1); + + // Processor Manufacture + ProcessorManuStr =3D HiiGetPackageString (&gEfiCallerIdGuid, ProcessorMa= nu, NULL); + ProcessorManuStrLen =3D StrLen (ProcessorManuStr); + + // Processor Version + ProcessorVersionStr =3D HiiGetPackageString (&gEfiCallerIdGuid, Processo= rVersion, NULL); + ProcessorVersionStrLen =3D StrLen (ProcessorVersionStr); + + // Serial Number + SerialNumberStr =3D HiiGetPackageString (&gEfiCallerIdGuid, SerialNumber= , NULL); + SerialNumberStrLen =3D StrLen (SerialNumberStr); + + // Asset Tag + AssetTagStr =3D HiiGetPackageString (&gEfiCallerIdGuid, AssetTag, NULL); + AssetTagStrLen =3D StrLen (AssetTagStr); + + // Part Number + PartNumberStr =3D HiiGetPackageString (&gEfiCallerIdGuid, PartNumber, NU= LL); + PartNumberStrLen =3D StrLen (PartNumberStr); + + TotalSize =3D sizeof (SMBIOS_TABLE_TYPE4) + + ProcessorSocketStrLen + 1 + + ProcessorManuStrLen + 1 + + ProcessorVersionStrLen + 1 + + SerialNumberStrLen + 1 + + AssetTagStrLen + 1 + + PartNumberStrLen + 1 + 1; + + *Type4Record =3D AllocateZeroPool (TotalSize); + if (*Type4Record =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto Exit; + } + + CopyMem (*Type4Record, &mSmbiosProcessorTableTemplate, sizeof (SMBIOS_TA= BLE_TYPE4)); + + OptionalStrStart =3D (CHAR8 *)(*Type4Record + 1); + UnicodeStrToAsciiStrS ( + ProcessorSocketStr, + OptionalStrStart, + ProcessorSocketStrLen + 1 + ); + + StrStart =3D OptionalStrStart + ProcessorSocketStrLen + 1; + UnicodeStrToAsciiStrS ( + ProcessorManuStr, + StrStart, + ProcessorManuStrLen + 1 + ); + + StrStart +=3D ProcessorManuStrLen + 1; + UnicodeStrToAsciiStrS ( + ProcessorVersionStr, + StrStart, + ProcessorVersionStrLen + 1 + ); + + StrStart +=3D ProcessorVersionStrLen + 1; + UnicodeStrToAsciiStrS ( + SerialNumberStr, + StrStart, + SerialNumberStrLen + 1 + ); + + StrStart +=3D SerialNumberStrLen + 1; + UnicodeStrToAsciiStrS ( + AssetTagStr, + StrStart, + AssetTagStrLen + 1 + ); + + StrStart +=3D AssetTagStrLen + 1; + UnicodeStrToAsciiStrS ( + PartNumberStr, + StrStart, + PartNumberStrLen + 1 + ); + +Exit: + FreePool (ProcessorSocketStr); + FreePool (ProcessorManuStr); + FreePool (ProcessorVersionStr); + FreePool (SerialNumberStr); + FreePool (AssetTagStr); + FreePool (PartNumberStr); + + return Status; +} + +/** + Add Type 4 SMBIOS Record for Processor Information. + + @param[in] ProcessorIndex Processor index of specified processor. + +**/ +EFI_STATUS +AddSmbiosProcessorTypeTable ( + IN UINTN ProcessorIndex + ) +{ + EFI_STATUS Status; + SMBIOS_TABLE_TYPE4 *Type4Record; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_SMBIOS_HANDLE L1CacheHandle; + EFI_SMBIOS_HANDLE L2CacheHandle; + EFI_SMBIOS_HANDLE L3CacheHandle; + UINT8 *LegacyVoltage; + PROCESSOR_STATUS_DATA ProcessorStatus; + UINT64 *ProcessorId; + PROCESSOR_CHARACTERISTIC_FLAGS ProcessorCharacteristics; + OEM_MISC_PROCESSOR_DATA MiscProcessorData; + BOOLEAN SocketPopulated; + + Type4Record =3D NULL; + + MiscProcessorData.Voltage =3D 0; + MiscProcessorData.CurrentSpeed =3D 0; + MiscProcessorData.CoreCount =3D 0; + MiscProcessorData.CoresEnabled =3D 0; + MiscProcessorData.ThreadCount =3D 0; + MiscProcessorData.MaxSpeed =3D 0; + L1CacheHandle =3D 0xFFFF; + L2CacheHandle =3D 0xFFFF; + L3CacheHandle =3D 0xFFFF; + + SocketPopulated =3D OemIsSocketPresent(ProcessorIndex); + + Status =3D AllocateType4AndSetProcessorInformationStrings ( + &Type4Record, + ProcessorIndex, + SocketPopulated + ); + if (EFI_ERROR (Status)) { + return Status; + } + + OemGetProcessorInformation (ProcessorIndex, + &ProcessorStatus, + (PROCESSOR_CHARACTERISTIC_FLAGS*) + &Type4Record->ProcessorCharacteristics, + &MiscProcessorData); + + if (SocketPopulated) { + AddSmbiosCacheTypeTable (ProcessorIndex, &L1CacheHandle, + &L2CacheHandle, &L3CacheHandle); + } + + LegacyVoltage =3D (UINT8*)&Type4Record->Voltage; + + *LegacyVoltage =3D MiscProcessorData.Voltage; + Type4Record->CurrentSpeed =3D MiscProcessorData.CurrentSpeed; + Type4Record->MaxSpeed =3D MiscProcessorData.MaxSpeed; + Type4Record->Status =3D ProcessorStatus.Data; + Type4Record->L1CacheHandle =3D L1CacheHandle; + Type4Record->L2CacheHandle =3D L2CacheHandle; + Type4Record->L3CacheHandle =3D L3CacheHandle; + Type4Record->CoreCount =3D MiscProcessorData.CoreCount; + Type4Record->CoreCount2 =3D MiscProcessorData.CoreCount; + Type4Record->EnabledCoreCount =3D MiscProcessorData.CoresEnabled; + Type4Record->EnabledCoreCount2 =3D MiscProcessorData.CoresEnabled; + Type4Record->ThreadCount =3D MiscProcessorData.ThreadCount; + Type4Record->ThreadCount2 =3D MiscProcessorData.ThreadCount; + + Type4Record->CurrentSpeed =3D GetCpuFrequency (ProcessorIndex); + Type4Record->ExternalClock =3D + (UINT16)(SmbiosGetExternalClockFrequency () / 1000 / 1000); + + ProcessorId =3D (UINT64*)&Type4Record->ProcessorId; + *ProcessorId =3D SmbiosGetProcessorId (); + + ProcessorCharacteristics =3D SmbiosGetProcessorCharacteristics (); + Type4Record->ProcessorCharacteristics |=3D *((UINT64*)&ProcessorCharacte= ristics); + + Type4Record->ProcessorFamily =3D SmbiosGetProcessorFamily (); + Type4Record->ProcessorFamily2 =3D SmbiosGetProcessorFamily2 (); + + SmbiosHandle =3D SMBIOS_HANDLE_PI_RESERVED; + Status =3D mSmbios->Add (mSmbios, NULL, &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *)Type4Record); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type04 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + FreePool (Type4Record); + + return Status; +} + +/** + Standard EFI driver point. + + @param ImageHandle Handle for the image of this driver + @param SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS The data was successfully stored. + +**/ +EFI_STATUS +EFIAPI +ProcessorSubClassEntryPoint( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT32 SocketIndex; + + // + // Locate dependent protocols + // + Status =3D gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID**)&= mSmbios); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", Status= )); + return Status; + } + + // + // Add our default strings to the HII database. They will be modified la= ter. + // + mHiiHandle =3D HiiAddPackages (&gEfiCallerIdGuid, + NULL, + ProcessorSubClassStrings, + NULL, + NULL + ); + if (mHiiHandle =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Add SMBIOS tables for populated sockets. + // + for (SocketIndex =3D 0; SocketIndex < OemGetProcessorMaxSockets(); Socke= tIndex++) { + Status =3D AddSmbiosProcessorTypeTable (SocketIndex); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Add Processor Type Table Failed! %r.\n", Stat= us)); + return Status; + } + } + + return Status; +} diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAA= rch64.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch= 64.c new file mode 100644 index 000000000000..96f739b2abea --- /dev/null +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c @@ -0,0 +1,97 @@ +/** @file + Functions for AARCH64 processor information + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include "SmbiosProcessor.h" + +/** Gets the size of the specified cache. + + @param CacheLevel The cache level (L1, L2 etc.). Zero based. + @param InstructionCache Whether the cache is a dedicated instruction c= ache. + @param DataCache Whether the cache is a dedicated data cache. + @param UnifiedCache Whether the cache is a unified cache. + + @return The cache size. +**/ +UINT64 +SmbiosProcessorGetCacheSize ( + IN UINT8 CacheLevel, + IN BOOLEAN InstructionCache, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache +) +{ + CCSIDR_DATA Ccsidr; + CSSELR_DATA Csselr; + BOOLEAN CcidxSupported; + UINT64 CacheSize; + + Csselr.Data =3D 0; + Csselr.Bits.Level =3D CacheLevel; + Csselr.Bits.InD =3D InstructionCache; + + Ccsidr.Data =3D ReadCCSIDR (Csselr.Data); + + CcidxSupported =3D ArmHasCcidx (); + + if (CcidxSupported) { + CacheSize =3D (UINT64)(1 << (Ccsidr.BitsCcidxAA64.LineSize + 4)) * + (Ccsidr.BitsCcidxAA64.Associativity + 1) * + (Ccsidr.BitsCcidxAA64.NumSets + 1); + } else { + CacheSize =3D (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) * + (Ccsidr.BitsNonCcidx.Associativity + 1) * + (Ccsidr.BitsNonCcidx.NumSets + 1); + } + + return CacheSize; +} + +/** Gets the associativity of the specified cache. + + @param CacheLevel The cache level (L1, L2 etc.). Zero based. + @param InstructionCache Whether the cache is a dedicated instruction c= ache. + @param DataCache Whether the cache is a dedicated data cache. + @param UnifiedCache Whether the cache is a unified cache. + + @return The cache associativity. +**/ +UINT32 +SmbiosProcessorGetCacheAssociativity ( + IN UINT8 CacheLevel, + IN BOOLEAN InstructionCache, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache + ) +{ + CCSIDR_DATA Ccsidr; + CSSELR_DATA Csselr; + BOOLEAN CcidxSupported; + UINT32 Associativity; + + Csselr.Data =3D 0; + Csselr.Bits.Level =3D CacheLevel; + Csselr.Bits.InD =3D (InstructionCache | UnifiedCache); + + Ccsidr.Data =3D ReadCCSIDR (Csselr.Data); + + CcidxSupported =3D ArmHasCcidx (); + + if (CcidxSupported) { + Associativity =3D Ccsidr.BitsCcidxAA64.Associativity; + } else { + Associativity =3D Ccsidr.BitsNonCcidx.Associativity; + } + + return Associativity; +} + diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAr= m.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c new file mode 100644 index 000000000000..5222b71f9f68 --- /dev/null +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c @@ -0,0 +1,103 @@ +/** @file + Functions for ARM processor information + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include "SmbiosProcessor.h" + +/** Gets the size of the specified cache. + + @param CacheLevel The cache level (L1, L2 etc.). Zero based. + @param InstructionCache Whether the cache is a dedicated instruction c= ache. + @param DataCache Whether the cache is a dedicated data cache. + @param UnifiedCache Whether the cache is a unified cache. + + @return The cache size. +**/ +UINT64 +ArmGetCacheSize ( + IN UINT8 CacheLevel, + IN BOOLEAN InstructionCache, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache + ) +{ + CCSIDR_DATA Ccsidr; + CCSIDR2_DATA Ccsidr2; + CSSELR_DATA Csselr; + BOOLEAN CcidxSupported; + UINT64 CacheSize; + + // Read the CCSIDR register to get the cache architecture + Csselr.Data =3D 0; + Csselr.Bits.Level =3D CacheLevel; + Csselr.Bits.InD =3D (InstructionCache | UnifiedCache); + + Ccsidr.Data =3D ReadCCSIDR (Csselr.Data); + + CcidxSupported =3D ArmHasCcidx (); + + if (CcidxSupported) { + Ccsidr2.Data =3D ReadCCSIDR2 (Csselr.Data); + CacheSize =3D (UINT64)(1 << (Ccsidr.BitsCcidxAA32.LineSize + 4)) * + (Ccsidr.BitsCcidxAA32.Associativity + 1) * + (Ccsidr2.Bits.NumSets + 1); + } else { + CacheSize =3D (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) * + (Ccsidr.BitsNonCcidx.Associativity + 1) * + (Ccsidr.BitsNonCcidx.NumSets + 1); + } + + return CacheSize; +} + +/** Gets the associativity of the specified cache. + + @param CacheLevel The cache level (L1, L2 etc.). Zero based. + @param InstructionCache Whether the cache is a dedicated instruction c= ache. + @param DataCache Whether the cache is a dedicated data cache. + @param UnifiedCache Whether the cache is a unified cache. + + @return The cache associativity. +**/ +UINT32 +ArmGetCacheAssociativity ( + IN UINT8 CacheLevel, + IN BOOLEAN InstructionCache, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache + ) +{ + CCSIDR_DATA Ccsidr; + CCSIDR2_DATA Ccsidr2; + CSSELR_DATA Csselr; + BOOLEAN CcidxSupported; + UINT32 Associativity; + + // Read the CCSIDR register to get the cache architecture + Csselr.Data =3D 0; + Csselr.Bits.Level =3D CacheLevel; + Csselr.Bits.InD =3D (InstructionCache | UnifiedCache); + + Ccsidr.Data =3D ReadCCSIDR (Csselr.Data); + + CcidxSupported =3D ArmHasCcidx (); + + if (CcidxSupported) { + Ccsidr2.Data =3D ReadCCSIDR2 (Csselr.Data); + Associativity =3D Ccsidr.BitsCcidxAA32.Associativity; + } else { + Associativity =3D Ccsidr.BitsNonCcidx.Associativity; + } + + return Associativity; +} + diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAr= mCommon.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm= Common.c new file mode 100644 index 000000000000..ed6583c19383 --- /dev/null +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon= .c @@ -0,0 +1,250 @@ +/** @file + Functions for processor information common to ARM and AARCH64. + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "SmbiosProcessor.h" + +/** Returns the maximum cache level implemented by the current CPU. + + @return The maximum cache level implemented. +**/ +UINT8 +SmbiosProcessorGetMaxCacheLevel ( + VOID + ) +{ + CLIDR_DATA Clidr; + UINT8 CacheLevel; + UINT8 MaxCacheLevel; + + MaxCacheLevel =3D 0; + + // Read the CLIDR register to find out what caches are present. + Clidr.Data =3D ReadCLIDR (); + + // Get the cache type for the L1 cache. If it's 0, there are no caches. + if (CLIDR_GET_CACHE_TYPE (Clidr.Data, 0) =3D=3D ClidrCacheTypeNone) { + return 0; + } + + for (CacheLevel =3D 1; CacheLevel < MAX_ARM_CACHE_LEVEL; CacheLevel++) { + if (CLIDR_GET_CACHE_TYPE (Clidr.Data, CacheLevel) =3D=3D ClidrCacheTyp= eNone) { + MaxCacheLevel =3D CacheLevel; + break; + } + } + + return MaxCacheLevel; +} + +/** Returns whether or not the specified cache level has separate I/D cach= es. + + @param CacheLevel The cache level (L1, L2 etc.). Zero based. + + @return TRUE if the cache level has separate I/D caches, FALSE otherwi= se. +**/ +BOOLEAN +SmbiosProcessorHasSeparateCaches ( + UINT8 CacheLevel + ) +{ + CLIDR_CACHE_TYPE CacheType; + CLIDR_DATA Clidr; + BOOLEAN SeparateCaches; + + SeparateCaches =3D FALSE; + + Clidr.Data =3D ReadCLIDR (); + + CacheType =3D CLIDR_GET_CACHE_TYPE (Clidr.Data, CacheLevel); + + if (CacheType =3D=3D ClidrCacheTypeSeparate) + { + SeparateCaches =3D TRUE; + } + + return SeparateCaches; +} + +/** Checks if ther ARM64 SoC ID SMC call is supported + + @return Whether the ARM64 SoC ID call is supported. +**/ +BOOLEAN +HasSmcArm64SocId ( + VOID + ) +{ + ARM_SMC_ARGS Args; + INT32 SmcCallStatus; + BOOLEAN Arm64SocIdSupported; + + Arm64SocIdSupported =3D FALSE; + + Args.Arg0 =3D SMCCC_VERSION; + ArmCallSmc (&Args); + SmcCallStatus =3D (INT32)Args.Arg0; + + if (SmcCallStatus < 0 || (SmcCallStatus >> 16) >=3D 1) { + Args.Arg0 =3D SMCCC_ARCH_FEATURES; + Args.Arg1 =3D SMCCC_ARCH_SOC_ID; + ArmCallSmc (&Args); + + if (Args.Arg0 >=3D 0) { + Arm64SocIdSupported =3D TRUE; + } + } + + return Arm64SocIdSupported; +} + +/** Fetches the JEP106 code and SoC Revision. + + @param Jep106Code JEP 106 code. + @param SocRevision SoC revision. + + @retval EFI_SUCCESS Succeeded. + @retval EFI_UNSUPPORTED Failed. +**/ +EFI_STATUS +SmbiosGetSmcArm64SocId ( + OUT INT32 *Jep106Code, + OUT INT32 *SocRevision + ) +{ + ARM_SMC_ARGS Args; + INT32 SmcCallStatus; + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + Args.Arg0 =3D SMCCC_ARCH_SOC_ID; + Args.Arg1 =3D 0; + ArmCallSmc (&Args); + SmcCallStatus =3D (INT32)Args.Arg0; + + if (SmcCallStatus >=3D 0) { + *Jep106Code =3D (INT32)Args.Arg0; + } else { + Status =3D EFI_UNSUPPORTED; + } + + Args.Arg0 =3D SMCCC_ARCH_SOC_ID; + Args.Arg1 =3D 1; + ArmCallSmc (&Args); + SmcCallStatus =3D (INT32)Args.Arg0; + + if (SmcCallStatus >=3D 0) { + *SocRevision =3D (INT32)Args.Arg0; + } else { + Status =3D EFI_UNSUPPORTED; + } + + return Status; +} + +/** Returns a value for the Processor ID field that conforms to SMBIOS + requirements. + + @return Processor ID. +**/ +UINT64 +SmbiosGetProcessorId ( + VOID + ) +{ + INT32 Jep106Code; + INT32 SocRevision; + UINT64 ProcessorId; + + if (HasSmcArm64SocId ()) { + SmbiosGetSmcArm64SocId (&Jep106Code, &SocRevision); + ProcessorId =3D ((UINT64)Jep106Code << 32) | SocRevision; + } else { + ProcessorId =3D ArmReadMidr (); + } + + return ProcessorId; +} + +/** Returns the external clock frequency. + + @return The external clock frequency. +**/ +UINTN +SmbiosGetExternalClockFrequency ( + VOID + ) +{ + return ArmReadCntFrq (); +} + +/** Returns the SMBIOS ProcessorFamily field value. + + @return The value for the ProcessorFamily field. +**/ +UINT8 +SmbiosGetProcessorFamily ( + VOID + ) +{ + return ProcessorFamilyIndicatorFamily2; +} + +/** Returns the ProcessorFamily2 field value. + + @return The value for the ProcessorFamily2 field. +**/ +UINT16 +SmbiosGetProcessorFamily2 ( + VOID + ) +{ + UINTN MainIdRegister; + UINT16 ProcessorFamily2; + + MainIdRegister =3D ArmReadMidr (); + + if (((MainIdRegister >> 16) & 0xF) < 8) { + ProcessorFamily2 =3D ProcessorFamilyARM; + } else { + if (sizeof (VOID*) =3D=3D 4) { + ProcessorFamily2 =3D ProcessorFamilyARMv7; + } else { + ProcessorFamily2 =3D ProcessorFamilyARMv8; + } + } + + return ProcessorFamily2; +} + +/** Returns the SMBIOS Processor Characteristics. + + @return Processor Characteristics bitfield. +**/ +PROCESSOR_CHARACTERISTIC_FLAGS +SmbiosGetProcessorCharacteristics ( + VOID + ) +{ + PROCESSOR_CHARACTERISTIC_FLAGS Characteristics; + + ZeroMem (&Characteristics, sizeof (Characteristics)); + + Characteristics.ProcessorArm64SocId =3D HasSmcArm64SocId (); + + return Characteristics; +} diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass= Strings.uni b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClas= sStrings.uni new file mode 100644 index 000000000000..22b3c64d9fe2 --- /dev/null +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings= .uni @@ -0,0 +1,24 @@ +/** @file + SMBIOS Type 4 strings + + Copyright (c) 2021, NUVIA Inc. All rights reserved. + Copyright (c) 2015, Hisilicon Limited. All rights reserved. + Copyright (c) 2015, Linaro Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +#langdef en-US "English" + +// +// Processor Information +// +#string STR_PROCESSOR_SOCKET_DESIGNATION #language en-US "Not Specifie= d" +#string STR_PROCESSOR_MANUFACTURE #language en-US "Not Specifie= d" +#string STR_PROCESSOR_VERSION #language en-US "Not Specifie= d" +#string STR_PROCESSOR_SERIAL_NUMBER #language en-US "Not Specifie= d" +#string STR_PROCESSOR_ASSET_TAG #language en-US "Not Specifie= d" +#string STR_PROCESSOR_PART_NUMBER #language en-US "Not Specifie= d" +#string STR_PROCESSOR_UNKNOWN #language en-US "Unknown" --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70939): https://edk2.groups.io/g/devel/message/70939 Mute This Topic: https://groups.io/mt/80271141/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70940+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70940+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135547; cv=none; d=zohomail.com; s=zohoarc; b=LZEABpDT8eEsdHVsSC9Mw1sNK/xZ8W9xmh8vzkQSyK49I1sLfT7DsJy3ygFp0EIizWKc9p1LtEngC+IKH06UamD5zzaOkLIXmvjT4VGhScvB6+u0tTghdFo5GPPeu601YOvy89oK4IF4eZJS69A5XpsUYl2rMumhYGys0ZDByqs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135547; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=a6A8wNZbyC47+lidPPoR4S34KO+5XOYo2FNKKy8TKko=; b=R3U+N1ZXcQjmblwyhnuJKblmgjeS343C8ubluJoyzr0EeSewVVf/wvu7kvV+CO9xP45hmBxnf2br0PPO7zfe8bVJiAJ/LdwysgxtZduzscypfR64dHvvGezuVhhMW9TFPkqQiR/3H9pQSGGyZ9/4zCezzrS5chz1sOS3Onu43A8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70940+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1612135547244871.4383102035741; Sun, 31 Jan 2021 15:25:47 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id x6r7YY1788612xOTO6eTXi3d; Sun, 31 Jan 2021 15:25:46 -0800 X-Received: from mail-qk1-f171.google.com (mail-qk1-f171.google.com [209.85.222.171]) by mx.groups.io with SMTP id smtpd.web09.26077.1612135546353044136 for ; Sun, 31 Jan 2021 15:25:46 -0800 X-Received: by mail-qk1-f171.google.com with SMTP id t63so14634133qkc.1 for ; Sun, 31 Jan 2021 15:25:46 -0800 (PST) X-Gm-Message-State: 7dmwMHESLi1rXXGgIoPV2lxbx1787277AA= X-Google-Smtp-Source: ABdhPJy7UyyCdMBF7vaRSt6g3/ygYpcdcnvb9HMaVNiizDZ80aimLykKPse9Pc3bXmNaaK6OgUCjpA== X-Received: by 2002:a37:a095:: with SMTP id j143mr14037679qke.445.1612135545012; Sun, 31 Jan 2021 15:25:45 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:44 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 14/21] ArmPkg: Add Universal/Smbios/SmbiosMiscDxe/Type00 Date: Sun, 31 Jan 2021 16:25:04 -0700 Message-Id: <20210131232511.18340-15-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135546; bh=T5MVDeDoNMiSuHxk9+i3QvMYQmOrg5x8XCVQqNCdTqQ=; h=Cc:Date:From:Reply-To:Subject:To; b=ZA0T17eKoHb6l5xHyRYlfJJQCKSFt046qVnuIGVcy8NHUscAK/rYbkkdECYcMCTPij4 8MNkoUULzD7qNLlOiw4MYhcLleaVl2Hfss7WzgVt/WM292geA8khPaZ1Aj/CGndJ0W1mD 5QeJA7BHbPR+eBxikzbD3DaV7dc+E0tW38Y= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This code provides information for the SMBIOS Type 0 table. Signed-off-by: Rebecca Cran Reviewed-by: Samer El-Haj-Mahmoud Reviewed-by: Leif Lindholm --- ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c | 9= 3 ++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c | 29= 6 ++++++++++++++++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni | 1= 8 ++ 3 files changed, 407 insertions(+) diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorDat= a.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c new file mode 100644 index 000000000000..edf0186aeae8 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c @@ -0,0 +1,93 @@ +/** @file + This file provides Smbios Type0 Data + + Based on the files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) Bios Vendor data. +// +SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE0, MiscBiosVendor) =3D { + { // Hdr + EFI_SMBIOS_TYPE_BIOS_INFORMATION, // Type, + 0, // Length, + 0 // Handle + }, + 1, // Vendor + 2, // BiosVersion + 0xE000, // BiosSegment + 3, // BiosReleaseDate + 0, // BiosSize + { // BiosCharacteristics + 0, // Reserved = :2 + 0, // Unknown = :1 + 0, // BiosCharacteristicsNotSu= pported :1 + 0, // IsaIsSupported = :1 + 0, // McaIsSupported = :1 + 0, // EisaIsSupported = :1 + 1, // PciIsSupported = :1 + 0, // PcmciaIsSupported = :1 + 1, // PlugAndPlayIsSupported = :1 + 0, // ApmIsSupported = :1 + 1, // BiosIsUpgradable = :1 + 1, // BiosShadowingAllowed = :1 + 0, // VlVesaIsSupported = :1 + 0, // EscdSupportIsAvailable = :1 + 1, // BootFromCdIsSupported = :1 + 1, // SelectableBootIsSupporte= d :1 + 0, // RomBiosIsSocketed = :1 + 0, // BootFromPcmciaIsSupporte= d :1 + 0, // EDDSpecificationIsSuppor= ted :1 + 0, // JapaneseNecFloppyIsSuppo= rted :1 + 0, // JapaneseToshibaFloppyIsS= upported :1 + 0, // Floppy525_360IsSupported= :1 + 0, // Floppy525_12IsSupported = :1 + 0, // Floppy35_720IsSupported = :1 + 0, // Floppy35_288IsSupported = :1 + 0, // PrintScreenIsSupported = :1 + 0, // Keyboard8042IsSupported = :1 + 0, // SerialIsSupported = :1 + 0, // PrinterIsSupported = :1 + 0, // CgaMonoIsSupported = :1 + 0, // NecPc98 = :1 + 0 // ReservedForVendor = :32 + }, + + { + 0x01, // BIOSCharacteristicsExt= ensionBytes[0] + // { // BiosReserved + // 1, // AcpiIsSupported = :1 + // 0, // UsbLegacyIsSupport= ed :1 + // 0, // AgpIsSupported = :1 + // 0, // I20BootIsSupported= :1 + // 0, // Ls120BootIsSupport= ed :1 + // 0, // AtapiZipDriveBootI= sSupported :1 + // 0, // Boot1394IsSupporte= d :1 + // 0 // SmartBatteryIsSupp= orted :1 + // }, + 0x0C //BIOSCharacteristicsExte= nsionBytes[1] + // { //SystemReserved + // 0, //BiosBootSpecIsSuppo= rted :1 + // 0, //FunctionKeyNetworkB= ootIsSupported :1 + // 1, //TargetContentDistri= butionEnabled :1 + // 1, //UefiSpecificationSu= pported :1 + // 0, //VirtualMachineSuppo= rted :1 + // 0 //ExtensionByte2Reser= ved :3 + // }, + }, + 0xFF, // SystemBiosMajorRelease; + 0xFF, // SystemBiosMinorRelease; + 0xFF, // EmbeddedControllerFirmwareM= ajorRelease; + 0xFF // EmbeddedControllerFirmwareM= inorRelease; +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFun= ction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFuncti= on.c new file mode 100644 index 000000000000..5aea32521bd3 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c @@ -0,0 +1,296 @@ +/** @file + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "SmbiosMisc.h" + + +typedef struct { + CONST CHAR8* MonthStr; + UINT32 MonthInt; +} MONTH_DESCRIPTION; + +STATIC CONST +MONTH_DESCRIPTION mMonthDescription[] =3D { + { "Jan", 1 }, + { "Feb", 2 }, + { "Mar", 3 }, + { "Apr", 4 }, + { "May", 5 }, + { "Jun", 6 }, + { "Jul", 7 }, + { "Aug", 8 }, + { "Sep", 9 }, + { "Oct", 10 }, + { "Nov", 11 }, + { "Dec", 12 }, + { "???", 1 }, // Use 1 as default month +}; + +/** + Field Filling Function. Transform an EFI_EXP_BASE2_DATA to a byte, with = '64k' + as the unit. + + @param Value Pointer to Base2_Data + + @retval + +**/ +UINT8 +Base2ToByteWith64KUnit ( + IN UINTN Value + ) +{ + UINT8 Size; + + Size =3D ((Value + (SIZE_64KB - 1)) >> 16); + + return Size; +} + +/** + Returns the date and time this file (and firmware) was built. + + @param[out] *Time Pointer to the EFI_TIME structure to fill in. +**/ +VOID +GetReleaseTime ( + OUT EFI_TIME *Time + ) +{ + CONST CHAR8 *ReleaseDate =3D __DATE__; + CONST CHAR8 *ReleaseTime =3D __TIME__; + UINTN i; + + for (i =3D 0; i < 12; i++) { + if (AsciiStrnCmp (ReleaseDate, mMonthDescription[i].MonthStr, 3) =3D= =3D 0) { + break; + } + } + + Time->Month =3D mMonthDescription[i].MonthInt; + Time->Day =3D AsciiStrDecimalToUintn (ReleaseDate + 4); + Time->Year =3D AsciiStrDecimalToUintn (ReleaseDate + 7); + Time->Hour =3D AsciiStrDecimalToUintn (ReleaseTime); + Time->Minute =3D AsciiStrDecimalToUintn (ReleaseTime + 3); + Time->Second =3D AsciiStrDecimalToUintn (ReleaseTime + 6); +} + +/** + Fetches the firmware ('BIOS') release date from the + FirmwareVersionInfo HOB. + + @return The release date as a UTF-16 string +**/ +CHAR16 * +GetBiosReleaseDate ( + VOID + ) +{ + CHAR16 *ReleaseDate; + EFI_TIME BuildTime; + + ReleaseDate =3D AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_= LENGTH); + if (ReleaseDate =3D=3D NULL) { + return NULL; + } + + GetReleaseTime (&BuildTime); + + (VOID)UnicodeSPrintAsciiFormat (ReleaseDate, + (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LE= NGTH, + "%02d/%02d/%4d", + BuildTime.Month, + BuildTime.Day, + BuildTime.Year + ); + + return ReleaseDate; +} + +/** + Fetches the firmware ('BIOS') version from the + FirmwareVersionInfo HOB. + + @return The version as a UTF-16 string +**/ +CHAR16 * +GetBiosVersion ( + VOID + ) +{ + CHAR16 *ReleaseString; + + ReleaseString =3D (CHAR16 *)FixedPcdGetPtr (PcdFirmwareVersionString); + + return ReleaseString; +} + + +/** + This function makes boot time changes to the contents of the + MiscBiosVendor (Type 0) record. + + @param RecordData Pointer to SMBIOS table with default = values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS table was successfully add= ed. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory. + +**/ +SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor) +{ + CHAR8 *OptionalStrStart; + CHAR8 *StrStart; + UINTN VendorStrLen; + UINTN VerStrLen; + UINTN DateStrLen; + UINTN BiosPhysicalSize; + CHAR16 *Vendor; + CHAR16 *Version; + CHAR16 *ReleaseDate; + CHAR16 *Char16String; + EFI_STATUS Status; + EFI_STRING_ID TokenToUpdate; + EFI_STRING_ID TokenToGet; + SMBIOS_TABLE_TYPE0 *SmbiosRecord; + SMBIOS_TABLE_TYPE0 *InputData; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE0 *)RecordData; + + Vendor =3D (CHAR16 *) PcdGetPtr (PcdFirmwareVendor); + + if (StrLen (Vendor) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BIOS_VENDOR); + HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Vendor, NULL); + } + + Version =3D GetBiosVersion(); + + if (StrLen (Version) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BIOS_VERSION); + HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Version, NULL); + } else { + Version =3D (CHAR16 *) PcdGetPtr (PcdFirmwareVersionString); + if (StrLen (Version) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BIOS_VERSION); + HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Version, NULL); + } + } + + Char16String =3D GetBiosReleaseDate (); + if (StrLen(Char16String) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE); + HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Char16String, NULL); + } + + TokenToGet =3D STRING_TOKEN (STR_MISC_BIOS_VENDOR); + Vendor =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + VendorStrLen =3D StrLen (Vendor); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BIOS_VERSION); + Version =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen =3D StrLen (Version); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE); + ReleaseDate =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL= ); + DateStrLen =3D StrLen (ReleaseDate); + + // + // Now update the BiosPhysicalSize + // + BiosPhysicalSize =3D FixedPcdGet32 (PcdFdSize); + + // + // Two zeros following the last string. + // + SmbiosRecord =3D AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE0) + VendorS= trLen + 1 + + VerStrLen + 1 + + DateStrLen + 1 + 1); + if (SmbiosRecord =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto Exit; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE0)); + + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE0); + SmbiosRecord->BiosSegment =3D (UINT16)(FixedPcdGet32 (PcdFdBaseAddress) = / SIZE_64KB); + if (BiosPhysicalSize < SIZE_16MB) { + SmbiosRecord->BiosSize =3D Base2ToByteWith64KUnit (BiosPhysicalSize) -= 1; + SmbiosRecord->ExtendedBiosSize.Size =3D BiosPhysicalSize / SIZE_1MB; + SmbiosRecord->ExtendedBiosSize.Unit =3D 0; // Size is in MB + } else { + SmbiosRecord->BiosSize =3D 0xFF; + if (BiosPhysicalSize > 0x3FFF) { + SmbiosRecord->ExtendedBiosSize.Size =3D BiosPhysicalSize / SIZE_1GB; + SmbiosRecord->ExtendedBiosSize.Unit =3D 1; // Size is in GB + } + } + + SmbiosRecord->SystemBiosMajorRelease =3D (UINT8) (PcdGet16 (PcdSystemBio= sRelease) >> 8); + SmbiosRecord->SystemBiosMinorRelease =3D (UINT8) (PcdGet16 (PcdSystemBio= sRelease) & 0xFF); + + SmbiosRecord->EmbeddedControllerFirmwareMajorRelease =3D (UINT16) + (PcdGet16 (PcdEmbeddedControllerFirmwareRelease) >> 8); + SmbiosRecord->EmbeddedControllerFirmwareMinorRelease =3D (UINT16) + (PcdGet16 (PcdEmbeddedControllerFirmwareRelease) & 0xFF); + + OptionalStrStart =3D (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStrS (Vendor, OptionalStrStart, VendorStrLen + 1); + StrStart =3D OptionalStrStart + VendorStrLen + 1; + UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1); + StrStart +=3D VerStrLen + 1; + UnicodeStrToAsciiStrS (ReleaseDate, StrStart, DateStrLen + 1); + // + // Now we have got the full smbios record, call smbios protocol to add t= his record. + // + Status =3D SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type00 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + +Exit: + if (Vendor !=3D NULL) { + FreePool (Vendor); + } + + if (Version !=3D NULL) { + FreePool (Version); + } + + if (ReleaseDate !=3D NULL) { + FreePool (ReleaseDate); + } + + if (Char16String !=3D NULL) { + FreePool (Char16String); + } + + return Status; +} diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.un= i b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni new file mode 100644 index 000000000000..a3f068cdcca2 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni @@ -0,0 +1,18 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +#string STR_MISC_BIOS_VENDOR #language en-US "Not Specified" +#string STR_MISC_BIOS_VERSION #language en-US "Not Specified" +#string STR_MISC_BIOS_RELEASE_DATE #language en-US "Not Specified" +#string STR_MISC_BIOS_VENDOR #language en-US "Not Specified" +#string STR_MISC_BIOS_RELEASE_DATE #language en-US "12/02/2020" --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:46 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 15/21] ArmPkg: Add Universal/Smbios/SmbiosMiscDxe/Type01 Date: Sun, 31 Jan 2021 16:25:05 -0700 Message-Id: <20210131232511.18340-16-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135548; bh=zvLa5nLF6dOrUuRa3+ObY0rNHBrlhvVPnt4sqiGbdu0=; h=Cc:Date:From:Reply-To:Subject:To; b=WlbtSkkTGwcHdNworwNjN4vV2nfeH6ZQYk/hzE0H2QNwZSMJJ1ZrZ2270/gu0HZnnbS mb8y3SyUgHNPV2wL80jm2GSQSLKwEotkV3V4S++6TkT1NJA3dYIVbL7dbrKGW4VsGHSlr SI5WPZWu//Fioa1QXeSFwTiZGSY+CXGvCEs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This code provides information for the SMBIOS Type 1 table. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Samer El-Haj-Mahmoud --- ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c = | 36 ++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunctio= n.c | 196 ++++++++++++++++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.uni = | 20 ++ 3 files changed, 252 insertions(+) diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufac= turerData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufa= cturerData.c new file mode 100644 index 000000000000..c03b133690ce --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerDa= ta.c @@ -0,0 +1,36 @@ +/** @file + This file provides Smbios Type1 Data + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) System Manufacturer data. +// +SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE1, MiscSystemManufacturer) =3D { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type, + 0, // Length, + 0 // Handle + }, + 1, // Manufacturer + 2, // ProductName + 3, // Version + 4, // SerialNumber + { // Uuid + 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,= 0x00} + }, + SystemWakeupTypePowerSwitch, // SystemWakeupType + 5, // SKUNumber, + 6 // Family +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufac= turerFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemMa= nufacturerFunction.c new file mode 100644 index 000000000000..2c69c2593f5d --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFu= nction.c @@ -0,0 +1,196 @@ +/** @file + This driver parses the mMiscSubclassDataTable structure and reports + any generated data to smbios. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SmbiosMisc.h" + +/** + This function makes boot time changes to the contents of the + MiscSystemManufacturer (Type 1) record. + + @param RecordData Pointer to SMBIOS table with default = values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS table was successfully add= ed. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory. + +**/ +SMBIOS_MISC_TABLE_FUNCTION(MiscSystemManufacturer) +{ + CHAR8 *OptionalStrStart; + CHAR8 *StrStart; + UINTN ManuStrLen; + UINTN VerStrLen; + UINTN PdNameStrLen; + UINTN SerialNumStrLen; + UINTN SKUNumStrLen; + UINTN FamilyStrLen; + UINTN RecordLength; + EFI_STRING Manufacturer; + EFI_STRING ProductName; + EFI_STRING Version; + EFI_STRING SerialNumber; + EFI_STRING SKUNumber; + EFI_STRING Family; + EFI_STRING_ID TokenToGet; + SMBIOS_TABLE_TYPE1 *SmbiosRecord; + SMBIOS_TABLE_TYPE1 *InputData; + EFI_STATUS Status; + EFI_STRING_ID TokenToUpdate; + CHAR16 *Product; + CHAR16 *pVersion; + + Status =3D EFI_SUCCESS; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE1 *)RecordData; + + Product =3D (CHAR16 *) PcdGetPtr (PcdSystemProductName); + if (StrLen (Product) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME); + HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Product, NULL); + } + + pVersion =3D (CHAR16 *) PcdGetPtr (PcdSystemVersion); + if (StrLen (pVersion) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_SYSTEM_VERSION); + HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, pVersion, NULL); + } + + OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER), + SerialNumType01); + OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER), + SystemManufacturerType01); + OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER), + SkuNumberType01); + OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_SYSTEM_FAMILY), + FamilyType01); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER); + Manufacturer =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + ManuStrLen =3D StrLen (Manufacturer); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME); + ProductName =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + PdNameStrLen =3D StrLen (ProductName); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_VERSION); + Version =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen =3D StrLen (Version); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER); + SerialNumber =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, = NULL); + SerialNumStrLen =3D StrLen (SerialNumber); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER); + SKUNumber =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + SKUNumStrLen =3D StrLen (SKUNumber); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_FAMILY); + Family =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + FamilyStrLen =3D StrLen (Family); + + // + // Two zeros following the last string. + // + RecordLength =3D sizeof (SMBIOS_TABLE_TYPE1) + + ManuStrLen + 1 + + PdNameStrLen + 1 + + VerStrLen + 1 + + SerialNumStrLen + 1 + + SKUNumStrLen + 1 + + FamilyStrLen + 1 + 1; + SmbiosRecord =3D AllocateZeroPool (RecordLength); + + if (SmbiosRecord =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto Exit; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE1)); + + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE1); + + CopyGuid(&SmbiosRecord->Uuid, &InputData->Uuid); + + OptionalStrStart =3D (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStrS (Manufacturer, OptionalStrStart, ManuStrLen + 1); + StrStart =3D OptionalStrStart + ManuStrLen + 1; + UnicodeStrToAsciiStrS (ProductName, StrStart, PdNameStrLen + 1); + StrStart +=3D PdNameStrLen + 1; + UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1); + StrStart +=3D VerStrLen + 1; + UnicodeStrToAsciiStrS (SerialNumber, StrStart, SerialNumStrLen + 1); + StrStart +=3D SerialNumStrLen + 1; + UnicodeStrToAsciiStrS (SKUNumber, StrStart, SKUNumStrLen + 1); + StrStart +=3D SKUNumStrLen + 1; + UnicodeStrToAsciiStrS (Family, StrStart, FamilyStrLen + 1); + + // + // Now we have got the full smbios record, call smbios protocol to add t= his record. + // + Status =3D SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type01 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + +Exit: + if (Manufacturer !=3D NULL) { + FreePool (Manufacturer); + } + + if (ProductName !=3D NULL) { + FreePool (ProductName); + } + + if (Version !=3D NULL) { + FreePool (Version); + } + + if (SerialNumber !=3D NULL) { + FreePool (SerialNumber); + } + + if (SKUNumber !=3D NULL) { + FreePool (SKUNumber); + } + + if (Family !=3D NULL) { + FreePool (Family); + } + + return Status; +} diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufac= turer.uni b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufact= urer.uni new file mode 100644 index 000000000000..8038f0e4b0bf --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.u= ni @@ -0,0 +1,20 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +#string STR_MISC_SYSTEM_MANUFACTURER #language en-US "Not Specified" +#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "Not Specified" +#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "Not Specified" +#string STR_MISC_SYSTEM_VERSION #language en-US "Not Specified" +#string STR_MISC_SYSTEM_SERIAL_NUMBER #language en-US "Not Specified" +#string STR_MISC_SYSTEM_SKU_NUMBER #language en-US "Not Specified" +#string STR_MISC_SYSTEM_FAMILY #language en-US "Not Specified" --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70941): https://edk2.groups.io/g/devel/message/70941 Mute This Topic: https://groups.io/mt/80271144/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70942+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70942+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135557; cv=none; d=zohomail.com; s=zohoarc; b=Ypz3KdV6dao/myTlqdqPIgyncFBedvawgaO1czTBzX02cSTZ57SWJKArt5G1MuSH2AF7fvdYooLh0AVnTh2ipektPT15Iz7uvYcGFIoKgtgLA/j10oXkqIbT/egdFnSMZt1tWNIdsZbR0hSOHk3XIiFyB/UyKBtaIH4F0l6nNvY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135557; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=befjYf96jH//zn13QoUJOJjpuyHE6FBE8rgpuazZqGI=; b=eJm5VcMvov8XzwQfAdU7o3od3Jvwt83pgyPQcr7rC108kVN/knGjrcxcFlRsqNno4SN7hkjIdkXwJK5C6iP6T//GQbjazKtB6rk5n2c30aNNSlQLmPWDwRc2HZS6hz8gRzYIt2ahOOtTH6VrS7i1fVSij7/Bg542rqu+ggtulT0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70942+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1612135557855101.38516971308036; Sun, 31 Jan 2021 15:25:57 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8ahYYY1788612xKwQpwQpxkg; Sun, 31 Jan 2021 15:25:57 -0800 X-Received: from mail-qk1-f172.google.com (mail-qk1-f172.google.com [209.85.222.172]) by mx.groups.io with SMTP id smtpd.web09.26078.1612135550265161290 for ; Sun, 31 Jan 2021 15:25:50 -0800 X-Received: by mail-qk1-f172.google.com with SMTP id a12so14597139qkh.10 for ; Sun, 31 Jan 2021 15:25:50 -0800 (PST) X-Gm-Message-State: WwNoor9Rx2cQBB6fSbBVz66px1787277AA= X-Google-Smtp-Source: ABdhPJwBmX5J7q3IjSwEr9EI10XoN8gXypI6z9h1n/puWkVNa/TlOdrGNIgXZurlFMsJXVU8I0vOYw== X-Received: by 2002:a37:e217:: with SMTP id g23mr13644430qki.283.1612135549025; Sun, 31 Jan 2021 15:25:49 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:48 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 16/21] ArmPkg: Add Universal/Smbios/SmbiosMiscDxe/Type02 Date: Sun, 31 Jan 2021 16:25:06 -0700 Message-Id: <20210131232511.18340-17-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135557; bh=Q525v484wtsXjIOuDG6v8KN/LvApYq7xBuOfL9dIOWU=; h=Cc:Date:From:Reply-To:Subject:To; b=M2hZxBvfr6UY5uR3QunvIWj+7jzz0PGdtZ9JszhH1rX7YHJThS3Y6mkF+Q6RQZvhe3Y OSfMLmbi7zRIrZ5NebT1FcWrQZioRQGOPtkrG7EzR89hAzhpbTNNF9vU6MVPdstvrrD7Y 8ig7TofhAhwTcM+fm9R5v1eY9aTn0VgO0is= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This code provides information for the SMBIOS Type 2 table. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Samer El-Haj-Mahmoud --- ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData= .c | 46 ++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunc= tion.c | 230 ++++++++++++++++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturer.uni= | 20 ++ 3 files changed, 296 insertions(+) diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManu= facturerData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoard= ManufacturerData.c new file mode 100644 index 000000000000..dfe1f2d45b92 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacture= rData.c @@ -0,0 +1,46 @@ +/** @file + + This file provide OEM to define Smbios Type2 Data + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + +// +// Static (possibly build generated) Chassis Manufacturer data. +// +SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE2, MiscBaseBoardManufacturer) =3D { + { // Hdr + EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type, + 0, // Length, + 0 // Handle + }, + 1, // BaseBoardManu= facturer + 2, // BaseBoardProd= uctName + 3, // BaseBoardVers= ion + 4, // BaseBoardSeri= alNumber + 5, // BaseBoardAsse= tTag + { // FeatureFlag + 1, // Motherboard = :1 + 0, // RequiresDaugh= terCard :1 + 0, // Removable = :1 + 1, // Replaceable = :1 + 0, // HotSwappable = :1 + 0 // Reserved = :3 + }, + 6, // BaseBoardChas= sisLocation + 0, // ChassisHandle; + BaseBoardTypeMotherBoard, // BoardType; + 0, // NumberOfConta= inedObjectHandles; + { + 0 + } // ContainedObje= ctHandles[1]; +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManu= facturerFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseB= oardManufacturerFunction.c new file mode 100644 index 000000000000..097777a23904 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacture= rFunction.c @@ -0,0 +1,230 @@ +/** @file + This driver parses the mSmbiosMiscDataTable structure and reports + any generated data using SMBIOS protocol. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SmbiosMisc.h" + + +/** + This function makes boot time changes to the contents of the + MiscBaseBoardManufacturer (Type 2) record. + + @param RecordData Pointer to SMBIOS table with default = values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS table was successfully add= ed. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory. + +**/ +SMBIOS_MISC_TABLE_FUNCTION(MiscBaseBoardManufacturer) +{ + CHAR8 *OptionalStrStart; + CHAR8 *StrStart; + UINTN RecordLength; + UINTN ManuStrLen; + UINTN ProductNameStrLen; + UINTN VerStrLen; + UINTN SerialNumStrLen; + UINTN AssetTagStrLen; + UINTN ChassisLocaStrLen; + UINTN HandleCount; + UINT16 *HandleArray; + CHAR16 *BaseBoardManufacturer; + CHAR16 *BaseBoardProductName; + CHAR16 *Version; + EFI_STRING SerialNumber; + EFI_STRING AssetTag; + EFI_STRING ChassisLocation; + EFI_STRING_ID TokenToGet; + SMBIOS_TABLE_TYPE2 *SmbiosRecord; + SMBIOS_TABLE_TYPE2 *InputData; + EFI_STATUS Status; + + EFI_STRING_ID TokenToUpdate; + + HandleCount =3D 0; + HandleArray =3D NULL; + InputData =3D NULL; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE2*)RecordData; + + BaseBoardManufacturer =3D (CHAR16 *) PcdGetPtr (PcdBaseBoardManufacturer= ); + if (StrLen (BaseBoardManufacturer) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER); + HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, BaseBoardManufactur= er, NULL); + } + + BaseBoardProductName =3D (CHAR16 *) PcdGetPtr (PcdBaseBoardProductName); + if (StrLen (BaseBoardProductName) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME); + HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, BaseBoardProductNam= e, NULL); + } + + Version =3D (CHAR16 *) PcdGetPtr (PcdBaseBoardVersion); + if (StrLen (Version) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION); + HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Version, NULL); + } + + OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG), + AssertTagType02 + ); + OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER), + SerialNumberType02 + ); + OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER), + BoardManufacturerType02 + ); + OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER), + SerialNumberType02 + ); + OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_BASE_BOARD_SKU_NUMBER), + SerialNumberType02 + ); + OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION), + ChassisLocationType02 + ); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER); + BaseBoardManufacturer =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenT= oGet, NULL); + ManuStrLen =3D StrLen (BaseBoardManufacturer); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME); + BaseBoardProductName =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenTo= Get, NULL); + ProductNameStrLen =3D StrLen (BaseBoardProductName); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION); + Version =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen =3D StrLen (Version); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER); + SerialNumber =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + SerialNumStrLen =3D StrLen (SerialNumber); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG); + AssetTag =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + AssetTagStrLen =3D StrLen (AssetTag); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION); + ChassisLocation =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, = NULL); + ChassisLocaStrLen =3D StrLen (ChassisLocation); + + // + // Two zeros following the last string. + // + RecordLength =3D sizeof (SMBIOS_TABLE_TYPE2) + + ManuStrLen + 1 + + ProductNameStrLen + 1 + + VerStrLen + 1 + + SerialNumStrLen + 1 + + AssetTagStrLen + 1 + + ChassisLocaStrLen + 1 + 1; + SmbiosRecord =3D AllocateZeroPool (RecordLength); + if (SmbiosRecord =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto Exit; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE2)); + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE2); + + // + // Update Contained objects Handle + // + SmbiosRecord->NumberOfContainedObjectHandles =3D 0; + SmbiosMiscGetLinkTypeHandle (EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, &HandleAr= ray, + &HandleCount); + // It's assumed there's at most a single chassis + ASSERT (HandleCount < 2); + if (HandleCount > 0) { + SmbiosRecord->ChassisHandle =3D HandleArray[0]; + } + + FreePool (HandleArray); + + OptionalStrStart =3D (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStrS (BaseBoardManufacturer, OptionalStrStart, ManuStrL= en + 1); + + StrStart =3D OptionalStrStart + ManuStrLen + 1; + UnicodeStrToAsciiStrS (BaseBoardProductName, StrStart, ProductNameStrLen= + 1); + + StrStart +=3D ProductNameStrLen + 1; + UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1); + + StrStart +=3D VerStrLen + 1; + UnicodeStrToAsciiStrS (SerialNumber, StrStart, SerialNumStrLen + 1); + + StrStart +=3D SerialNumStrLen + 1; + UnicodeStrToAsciiStrS (AssetTag, StrStart, AssetTagStrLen + 1); + + StrStart +=3D AssetTagStrLen + 1; + UnicodeStrToAsciiStrS (ChassisLocation, StrStart, ChassisLocaStrLen + 1); + + Status =3D SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type02 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + +Exit: + if (BaseBoardManufacturer !=3D NULL) { + FreePool (BaseBoardManufacturer); + } + + if (BaseBoardProductName !=3D NULL) { + FreePool (BaseBoardProductName); + } + + if (Version !=3D NULL) { + FreePool (Version); + } + + if (SerialNumber !=3D NULL) { + FreePool (SerialNumber); + } + + if (AssetTag !=3D NULL) { + FreePool (AssetTag); + } + + if (ChassisLocation !=3D NULL) { + FreePool (ChassisLocation); + } + + return 0; +} diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManu= facturer.uni b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardMa= nufacturer.uni new file mode 100644 index 000000000000..0f0fb1f93bbb --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacture= r.uni @@ -0,0 +1,20 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +#string STR_MISC_BASE_BOARD_MANUFACTURER #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_PRODUCT_NAME #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_VERSION #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_SERIAL_NUMBER #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_ASSET_TAG #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_CHASSIS_LOCATION #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_SKU_NUMBER #language en-US "Not Specifi= ed" --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70942): https://edk2.groups.io/g/devel/message/70942 Mute This Topic: https://groups.io/mt/80271145/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70943+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70943+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135553; cv=none; d=zohomail.com; s=zohoarc; b=jfOH0A5anSmOOdCe6hipxpVSN3jD3fR2Izpgo21UdeqPea9RFKkjIQIGcsiuCI94jmyAphLDZquQK4FkdrQ9BSqbQR4pyyBH8y/GA9aNft6VUyJqdjO+K049QlW+jA5bdk3tusiGvIyhXZIqJ+TMEHMVbjq6zAUSlx7WvMrsdj4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135553; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Yfri3ueIuFSeKrVXOWGkic6OWE1eCnfvoNc5865uDLY=; b=HnnlUyfQMbI/jPIu4HCDsLFpApxKt8RjTIMLfzcMJI4qpVPcKw9FMM/JkrtyAQDDHwaY92SfKdLe/W8QVfM/h2vTmzmT0CDoofgPblWSfDT2t8mHEoPrLeMydUiNwx5Kcf3BwJ6+dSZFQ/UdBCdwXlW+EOQWh+dV22o7A8rV6yo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70943+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161213555311678.88922380847669; Sun, 31 Jan 2021 15:25:53 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id k9SWYY1788612xSNlZYRVOzO; Sun, 31 Jan 2021 15:25:52 -0800 X-Received: from mail-qt1-f178.google.com (mail-qt1-f178.google.com [209.85.160.178]) by mx.groups.io with SMTP id smtpd.web09.26080.1612135552202181240 for ; Sun, 31 Jan 2021 15:25:52 -0800 X-Received: by mail-qt1-f178.google.com with SMTP id r20so7483069qtm.3 for ; Sun, 31 Jan 2021 15:25:52 -0800 (PST) X-Gm-Message-State: 33RHBsmR7SggzTYVsXXC2PQmx1787277AA= X-Google-Smtp-Source: ABdhPJw7XEg8sXrT4lFVTgJ7QD7zA5iaGMO8PTfXEWh8o21bmpcVku9ll6f3a88eFRaL0Bng8hb5Rg== X-Received: by 2002:ac8:6b8a:: with SMTP id z10mr13733574qts.384.1612135550986; Sun, 31 Jan 2021 15:25:50 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:50 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 17/21] ArmPkg: Add Universal/Smbios/SmbiosMiscDxe/Type03 Date: Sun, 31 Jan 2021 16:25:07 -0700 Message-Id: <20210131232511.18340-18-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135552; bh=wJK5/mIJuDByeYP6XOFeTfV+O7YB9BGt8CNfytnbMns=; h=Cc:Date:From:Reply-To:Subject:To; b=vK+IT5KQwIhN/wZXMck2auWZJIXQ+KXD3kzT3P8LnLwnAIJF8NdpBeuo41a4WmXRrRU pLwmXhT22cYZdvlkR4A8OnDZUW81tYsF0GPwMFQoqo3SOVdoHd3KrhUdMhFaD9F/oObDu 0VvnQJ7GdDio+pVUxESeL5Y8Zmsw+D8s+Aw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This code provides information for the SMBIOS Type 3 table. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Samer El-Haj-Mahmoud --- ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c= | 52 +++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFuncti= on.c | 224 ++++++++++++++++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.uni = | 18 ++ 3 files changed, 294 insertions(+) diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufa= cturerData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManu= facturerData.c new file mode 100644 index 000000000000..137bd941d0b1 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerD= ata.c @@ -0,0 +1,52 @@ +/** @file + This file provides Smbios Type3 Data + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) Chassis Manufacturer data. +// +SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) =3D { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // Type, + 0, // Length, + 0 // Handle + }, + 1, // Manufactrurer + MiscChassisTypeMainServerChassis, // Type + 2, // Version + 3, // SerialNumber + 4, // AssetTag + ChassisStateSafe, // BootupState + ChassisStateSafe, // PowerSupplySt= ate + ChassisStateSafe, // ThermalState + ChassisSecurityStatusNone, // SecurityState + { + 0, // OemDefined[0] + 0, // OemDefined[1] + 0, // OemDefined[2] + 0 // OemDefined[3] + }, + 2, // Height + 1, // NumberofPower= Cords + 0, // ContainedElem= entCount + 0, // ContainedElem= entRecordLength + { // ContainedElem= ents[0] + { + 0, // ContainedEl= ementType + 0, // ContainedEl= ementMinimum + 0 // ContainedEl= ementMaximum + } + } +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufa= cturerFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassis= ManufacturerFunction.c new file mode 100644 index 000000000000..e6adbceba2d5 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerF= unction.c @@ -0,0 +1,224 @@ +/** @file + This driver parses the mMiscSubclassDataTable structure and reports + any generated data to smbios. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SmbiosMisc.h" + +/** + * Returns the chassis type in SMBIOS format. + * + * @return Chassis type +**/ +UINT8 +GetChassisType ( + VOID + ) +{ + EFI_STATUS Status; + UINT8 ChassisType; + + Status =3D OemGetChassisType (&ChassisType); + if (EFI_ERROR (Status)) { + return 0; + } + + return ChassisType; +} + +/** + This function makes boot time changes to the contents of the + MiscChassisManufacturer (Type 3) record. + + @param RecordData Pointer to SMBIOS table with default = values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS table was successfully add= ed. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory. + +**/ +SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer) +{ + CHAR8 *OptionalStrStart; + CHAR8 *StrStart; + UINTN RecordLength; + UINTN ManuStrLen; + UINTN VerStrLen; + UINTN AssertTagStrLen; + UINTN SerialNumStrLen; + UINTN ChaNumStrLen; + EFI_STRING Manufacturer; + EFI_STRING Version; + EFI_STRING SerialNumber; + EFI_STRING AssertTag; + EFI_STRING ChassisSkuNumber; + EFI_STRING_ID TokenToGet; + SMBIOS_TABLE_TYPE3 *SmbiosRecord; + SMBIOS_TABLE_TYPE3 *InputData; + EFI_STATUS Status; + + UINT8 ContainedElementCount; + CONTAINED_ELEMENT ContainedElements; + UINT8 ExtendLength; + + UINT8 ChassisType; + + ExtendLength =3D 0; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE3 *)RecordData; + + OemUpdateSmbiosInfo ( + mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG), + AssetTagType03 + ); + OemUpdateSmbiosInfo ( + mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER), + SerialNumberType03 + ); + OemUpdateSmbiosInfo ( + mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_CHASSIS_VERSION), + VersionType03 + ); + OemUpdateSmbiosInfo ( + mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER), + ManufacturerType03 + ); + OemUpdateSmbiosInfo ( + mSmbiosMiscHiiHandle, + STRING_TOKEN (STR_MISC_CHASSIS_SKU_NUMBER), + SkuNumberType03 + ); + + TokenToGet =3D STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER); + Manufacturer =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + ManuStrLen =3D StrLen (Manufacturer); + + TokenToGet =3D STRING_TOKEN (STR_MISC_CHASSIS_VERSION); + Version =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen =3D StrLen (Version); + + TokenToGet =3D STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER); + SerialNumber =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + SerialNumStrLen =3D StrLen (SerialNumber); + + TokenToGet =3D STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG); + AssertTag =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + AssertTagStrLen =3D StrLen (AssertTag); + + TokenToGet =3D STRING_TOKEN (STR_MISC_CHASSIS_SKU_NUMBER); + ChassisSkuNumber =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet,= NULL); + ChaNumStrLen =3D StrLen (ChassisSkuNumber); + + ContainedElementCount =3D InputData->ContainedElementCount; + + if (ContainedElementCount > 1) { + ExtendLength =3D (ContainedElementCount - 1) * sizeof (CONTAINED_ELEME= NT); + } + + // + // Two zeros following the last string. + // + RecordLength =3D sizeof (SMBIOS_TABLE_TYPE3) + + ExtendLength + 1 + + ManuStrLen + 1 + + VerStrLen + 1 + + SerialNumStrLen + 1 + + AssertTagStrLen + 1 + + ChaNumStrLen + 1 + 1; + SmbiosRecord =3D AllocateZeroPool (RecordLength); + if (SmbiosRecord =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto Exit; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE3)); + + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength = + 1; + + ChassisType =3D GetChassisType (); + if (ChassisType !=3D 0) { + SmbiosRecord->Type =3D ChassisType; + } + + //ContainedElements + ASSERT (ContainedElementCount < 2); + (VOID)CopyMem (SmbiosRecord + 1, &ContainedElements, ExtendLength); + + //ChassisSkuNumber + *((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength) = =3D 5; + + OptionalStrStart =3D (CHAR8 *)((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TA= BLE_TYPE3) + + ExtendLength + 1); + UnicodeStrToAsciiStrS (Manufacturer, OptionalStrStart, ManuStrLen + 1); + StrStart =3D OptionalStrStart + ManuStrLen + 1; + UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1); + StrStart +=3D VerStrLen + 1; + UnicodeStrToAsciiStrS (SerialNumber, StrStart, SerialNumStrLen + 1); + StrStart +=3D SerialNumStrLen + 1; + UnicodeStrToAsciiStrS (AssertTag, StrStart, AssertTagStrLen + 1); + StrStart +=3D AssertTagStrLen + 1; + UnicodeStrToAsciiStrS (ChassisSkuNumber, StrStart, ChaNumStrLen + 1); + // + // Now we have got the full smbios record, call smbios protocol to add t= his record. + // + Status =3D SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type03 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + +Exit: + if (Manufacturer !=3D NULL) { + FreePool (Manufacturer); + } + + if (Version !=3D NULL) { + FreePool (Version); + } + + if (SerialNumber !=3D NULL) { + FreePool (SerialNumber); + } + + if (AssertTag !=3D NULL) { + FreePool (AssertTag); + } + + if (ChassisSkuNumber !=3D NULL) { + FreePool (ChassisSkuNumber); + } + + return 0; +} diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufa= cturer.uni b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufa= cturer.uni new file mode 100644 index 000000000000..9512b354fe9a --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.= uni @@ -0,0 +1,18 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +#string STR_MISC_CHASSIS_MANUFACTURER #language en-US "Not Specified" +#string STR_MISC_CHASSIS_VERSION #language en-US "Not Specified" +#string STR_MISC_CHASSIS_SERIAL_NUMBER #language en-US "Not Specified" +#string STR_MISC_CHASSIS_ASSET_TAG #language en-US "Not Specified" +#string STR_MISC_CHASSIS_SKU_NUMBER #language en-US "Not Specified" --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70943): https://edk2.groups.io/g/devel/message/70943 Mute This Topic: https://groups.io/mt/80271146/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70944+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70944+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135557; cv=none; d=zohomail.com; s=zohoarc; b=ih8eOqB1N6FNiyJ8TGLz4On0LI9YPS0hYHY9tNNg4BgddZD7PL+WSf88QBX4fumK0nSGoJ8cKEl789tB6U604CzJxAZ6GR8pxhxPNaqT4LRlCwxnJo1aEJJXna9TvZGV/eYJnVc0/gmudDm9PuHRcDJ3tepAJbz6aK9Ggfg9S/I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135557; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=IUctxfn+UlLFNDmQQIc1hfFCEUvV5tWzoQc7cKG4VGs=; b=LugYGVp+NbmYgFHSv//nZTRJja21QdGs9syP/82Tz4zJLRgGcT11p0KZlobV6wblfhlKhguKcoloWMmnfTbun3MHSxRGSD2pCg2NaSPJNOoSYURjOfyFEwJ+WW/rrvea/qh/TVWrjjm533/ebOIvTDwF7zYdtOop79+7JI/jsb0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70944+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161213555736118.167767122782493; Sun, 31 Jan 2021 15:25:57 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8Zo5YY1788612xgP4glzuRxX; Sun, 31 Jan 2021 15:25:54 -0800 X-Received: from mail-qt1-f171.google.com (mail-qt1-f171.google.com [209.85.160.171]) by mx.groups.io with SMTP id smtpd.web12.26150.1612135554429262283 for ; Sun, 31 Jan 2021 15:25:54 -0800 X-Received: by mail-qt1-f171.google.com with SMTP id c1so11071466qtc.1 for ; Sun, 31 Jan 2021 15:25:54 -0800 (PST) X-Gm-Message-State: R1sAr4KcJN9MfKLBhuReUbLex1787277AA= X-Google-Smtp-Source: ABdhPJx8zB75vAGilMMZXp5TQ9OORYJiCoDURJp8HJLYYWeC7uAa2C1Fmn60c4EhcgMpAbnmbW5ZSQ== X-Received: by 2002:ac8:4d93:: with SMTP id a19mr12870372qtw.356.1612135552992; Sun, 31 Jan 2021 15:25:52 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:52 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 18/21] ArmPkg: Add Universal/Smbios/SmbiosMiscDxe/Type13 Date: Sun, 31 Jan 2021 16:25:08 -0700 Message-Id: <20210131232511.18340-19-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135554; bh=f6FoOmTdLVh975ImfO9XWMW/Cef69ZJzpkK+b7A/cyM=; h=Cc:Date:From:Reply-To:Subject:To; b=ucSUfLpZqpFZy1nqogZM2mVwvXTMyZJcsFPL2JukLQ4S+iLccvjCDkhOPqvzett8bpA oLEd2L/wtxdMJBjQYV7dDAbgX29N/mahbHaC/xScg4Tkks8djMBZay4+D8ZZILWfjkBql jwHDqfPsocX5mqBWn4ktB+d3brdLcLZRy/Y= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This code provides information for the SMBIOS Type 13 table. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm --- ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLangua= gesData.c | 33 ++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLangua= gesFunction.c | 166 ++++++++++++++++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLangua= ges.uni | 43 +++++ 3 files changed, 242 insertions(+) diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInsta= llableLanguagesData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNu= mberOfInstallableLanguagesData.c new file mode 100644 index 000000000000..97d7303d1a33 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableL= anguagesData.c @@ -0,0 +1,33 @@ +/** @file + This file provides Smbios Type13 Data + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + +// +// Static (possibly build generated) Bios Vendor data. +// + +SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguag= es) =3D +{ + { // Hdr + EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // Type, + 0, // Length, + 0 // Handle + }, + 0, // InstallableLang= uages + 0, // Flags + { + 0 // Reserved[15] + }, + 1 // CurrentLanguage +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInsta= llableLanguagesFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/Mi= scNumberOfInstallableLanguagesFunction.c new file mode 100644 index 000000000000..19b60ed71f8c --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableL= anguagesFunction.c @@ -0,0 +1,166 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SmbiosMisc.h" + +/** + Get next language from language code list (with separator ';'). + + @param LangCode Input: point to first language in the list. On + Otput: point to next language in the list, or + NULL if no more language in the list. + @param Lang The first language in the list. + +**/ +VOID +EFIAPI +GetNextLanguage ( + IN OUT CHAR8 **LangCode, + OUT CHAR8 *Lang + ) +{ + UINTN Index; + CHAR8 *StringPtr; + + if (LangCode =3D=3D NULL || *LangCode =3D=3D NULL || Lang =3D=3D NULL) { + return; + } + + Index =3D 0; + StringPtr =3D *LangCode; + while (StringPtr[Index] !=3D 0 && StringPtr[Index] !=3D ';') { + Index++; + } + + (VOID)CopyMem (Lang, StringPtr, Index); + Lang[Index] =3D 0; + + if (StringPtr[Index] =3D=3D ';') { + Index++; + } + *LangCode =3D StringPtr + Index; +} + +/** + This function returns the number of supported languages on HiiHandle. + + @param HiiHandle The HII package list handle. + + @retval The number of supported languages. + +**/ +UINT16 +EFIAPI +GetSupportedLanguageNumber ( + IN EFI_HII_HANDLE HiiHandle + ) +{ + CHAR8 *Lang; + CHAR8 *Languages; + CHAR8 *LanguageString; + UINT16 LangNumber; + + Languages =3D HiiGetSupportedLanguages (HiiHandle); + if (Languages =3D=3D NULL) { + return 0; + } + + LangNumber =3D 0; + Lang =3D AllocatePool (AsciiStrSize (Languages)); + if (Lang !=3D NULL) { + LanguageString =3D Languages; + while (*LanguageString !=3D 0) { + GetNextLanguage (&LanguageString, Lang); + LangNumber++; + } + FreePool (Lang); + } + FreePool (Languages); + return LangNumber; +} + + +/** + This function makes boot time changes to the contents of the + MiscNumberOfInstallableLanguages (Type 13) record. + + @param RecordData Pointer to SMBIOS table with default = values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS table was successfully add= ed. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory. + +**/ +SMBIOS_MISC_TABLE_FUNCTION(MiscNumberOfInstallableLanguages) +{ + UINTN LangStrLen; + CHAR8 CurrentLang[SMBIOS_STRING_MAX_= LENGTH + 1]; + CHAR8 *OptionalStrStart; + EFI_STATUS Status; + SMBIOS_TABLE_TYPE13 *SmbiosRecord; + SMBIOS_TABLE_TYPE13 *InputData; + + InputData =3D NULL; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE13 *)RecordData; + + InputData->InstallableLanguages =3D GetSupportedLanguageNumber (mSmbiosM= iscHiiHandle); + + // + // Try to check if current langcode matches with the langcodes in instal= led languages + // + ZeroMem (CurrentLang, SMBIOS_STRING_MAX_LENGTH - 1); + (VOID)AsciiStrCpyS (CurrentLang, SMBIOS_STRING_MAX_LENGTH - 1, "en|US|is= o8859-1"); + LangStrLen =3D AsciiStrLen (CurrentLang); + + // + // Two zeros following the last string. + // + SmbiosRecord =3D AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE13) + LangSt= rLen + 1 + 1); + if (SmbiosRecord =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE13)); + + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE13); + + OptionalStrStart =3D (CHAR8 *)(SmbiosRecord + 1); + (VOID)AsciiStrCpyS (OptionalStrStart, SMBIOS_STRING_MAX_LENGTH - 1, Curr= entLang); + // + // Now we have got the full smbios record, call smbios protocol to add t= his record. + // + Status =3D SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type13 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + return Status; +} diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInsta= llableLanguages.uni b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumb= erOfInstallableLanguages.uni new file mode 100644 index 000000000000..3af7a01653d8 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableL= anguages.uni @@ -0,0 +1,43 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +/=3D# +// +// Language String (Long Format) +// +#string STR_MISC_BIOS_LANGUAGES_ENG_LONG #language en-US "en|US|is= o8859-1" +#string STR_MISC_BIOS_LANGUAGES_FRA_LONG #language en-US "fr|CA|is= o8859-1" +#string STR_MISC_BIOS_LANGUAGES_CHN_LONG #language en-US "zh|TW|un= icode" +#string STR_MISC_BIOS_LANGUAGES_JPN_LONG #language en-US "ja|JP|un= icode" +#string STR_MISC_BIOS_LANGUAGES_ITA_LONG #language en-US "it|IT|is= o8859-1" +#string STR_MISC_BIOS_LANGUAGES_SPA_LONG #language en-US "es|ES|is= o8859-1" +#string STR_MISC_BIOS_LANGUAGES_GER_LONG #language en-US "de|DE|is= o8859-1" +#string STR_MISC_BIOS_LANGUAGES_POR_LONG #language en-US "pt|PT|is= o8859-1" + + +// +// Language String (Abbreviated Format) +// +#string STR_MISC_BIOS_LANGUAGES_ENG_ABBREVIATE #language en-US "enUS" +#string STR_MISC_BIOS_LANGUAGES_FRA_ABBREVIATE #language en-US "frCA" +#string STR_MISC_BIOS_LANGUAGES_CHN_ABBREVIATE #language en-US "zhTW" +#string STR_MISC_BIOS_LANGUAGES_JPN_ABBREVIATE #language en-US "jaJP" +#string STR_MISC_BIOS_LANGUAGES_ITA_ABBREVIATE #language en-US "itIT" +#string STR_MISC_BIOS_LANGUAGES_SPA_ABBREVIATE #language en-US "esES" +#string STR_MISC_BIOS_LANGUAGES_GER_ABBREVIATE #language en-US "deDE" +#string STR_MISC_BIOS_LANGUAGES_POR_ABBREVIATE #language en-US "ptPT" + +#string STR_MISC_BIOS_LANGUAGES_SIMPLECH_ABBREVIATE #language en-US "zhC= N" +#string STR_MISC_BIOS_LANGUAGES_SIMPLECH_LONG #language en-US "zh|= CN|unicode" + + --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70944): https://edk2.groups.io/g/devel/message/70944 Mute This Topic: https://groups.io/mt/80271147/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70945+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70945+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135558; cv=none; d=zohomail.com; s=zohoarc; b=gdfRF6g4XEWFCCqAHmRFy/mwhtnOuG1LHqcpZ54mwyoCWrZw9OSoGkjWHonNjNnuSKNkINgTfodmauDboKL4kqavlQayhmkh1NK8+n9w5ZEPAxQd1G+aPe3bXmu07m/jXw46JbhVJ60vHR0vXFME4RUD01aUvlaL0FNb0vrw98s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135558; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=JtbV6B89rbFaOAIWZnZwVjHROilNlXAsQazgtyE1fUo=; b=ZC8+79mRU6cUdyB5cbIUlLtvfaAJQ6kR/7nnlLuvpfJqXY5jqXq81fSf0hrOGP5cfZSyx2tIzIFcdRjsnoQazPqSN9p1PFf1p2/TqU09lzscrtQKzK1nsmQdDLjr21NQxTf0gzhEdlfDR37kYEyh3VIdYIIe8HZLnMIcMQYaACA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70945+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1612135558295215.61005688355954; Sun, 31 Jan 2021 15:25:58 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id kojrYY1788612xK2UiOpV8QN; Sun, 31 Jan 2021 15:25:58 -0800 X-Received: from mail-qv1-f54.google.com (mail-qv1-f54.google.com [209.85.219.54]) by mx.groups.io with SMTP id smtpd.web09.26082.1612135557040401856 for ; Sun, 31 Jan 2021 15:25:57 -0800 X-Received: by mail-qv1-f54.google.com with SMTP id u20so3320711qvx.7 for ; Sun, 31 Jan 2021 15:25:56 -0800 (PST) X-Gm-Message-State: BipTbMkfdrO41wMJqSc1fQOix1787277AA= X-Google-Smtp-Source: ABdhPJxXiTiD9JmbamEegVJM+tu1wXl/QmIVksSHnRlFZWxZdgUdOsaopdzDSXx+i135kKQwCmeieg== X-Received: by 2002:a05:6214:410:: with SMTP id z16mr13411120qvx.39.1612135555720; Sun, 31 Jan 2021 15:25:55 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:54 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 19/21] ArmPkg: Add Universal/Smbios/SmbiosMiscDxe/Type32 Date: Sun, 31 Jan 2021 16:25:09 -0700 Message-Id: <20210131232511.18340-20-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135558; bh=TErGjAJ8b3g25wmH2MfQetSHC5RHRat8RIWoz3Q6t/s=; h=Cc:Date:From:Reply-To:Subject:To; b=c8gljUPTgFl2qHvmr9zytV03A7AK9+6HMYd32yXoHv9XJBS3sWIvNyTPoxV36rkIisb ot2aa0Y/+gYgfkFKCFQHeyiwIcgj61CMRGqhm5KAyqk4IxGdAKabp9+xQStzXPXPUFsyT n7FYjO7wliO7AGNQPtf0NiL0zArrhbgIEyo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This code provides information for the SMBIOS Type 32 table. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Samer El-Haj-Mahmoud --- ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c = | 32 +++++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c= | 73 ++++++++++++++++++++ 2 files changed, 105 insertions(+) diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformati= onData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformation= Data.c new file mode 100644 index 000000000000..ebe4ad941c5f --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c @@ -0,0 +1,32 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE32, MiscBootInformation) =3D { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type, + 0, // Length, + 0 // Handle + }, + { // Reserved[6] + 0, + 0, + 0, + 0, + 0, + 0 + }, + BootInformationStatusNoError // BootInformation= Status +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformati= onFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInforma= tionFunction.c new file mode 100644 index 000000000000..733615bbcf1a --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunct= ion.c @@ -0,0 +1,73 @@ +/** @file + boot information boot time changes. + SMBIOS type 32. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include "SmbiosMisc.h" + +/** + This function makes boot time changes to the contents of the + MiscBootInformation (Type 32) record. + + @param RecordData Pointer to SMBIOS table with default = values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS table was successfully add= ed. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory. + +**/ +SMBIOS_MISC_TABLE_FUNCTION(MiscBootInformation) +{ + EFI_STATUS Status; + SMBIOS_TABLE_TYPE32 *SmbiosRecord; + SMBIOS_TABLE_TYPE32 *InputData; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE32 *)RecordData; + + // + // Two zeros following the last string. + // + SmbiosRecord =3D AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1); + if (SmbiosRecord =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE32)); + + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE32); + + // + // Now we have got the full smbios record, call smbios protocol to add t= his record. + // + Status =3D SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type32 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + return Status; +} --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70945): https://edk2.groups.io/g/devel/message/70945 Mute This Topic: https://groups.io/mt/80271149/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70946+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70946+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135561; cv=none; d=zohomail.com; s=zohoarc; b=nyClV2r+DLXw+BtAcgZHWzsYsvkPa1jDTT/65Via47ciDNr8Z1IbfD4D75RHuWQZqj5j8c6s9un+46RrwVprrzNhKIcwT+cM8NoVFW3KRu8G6OMwxNdF3S3vcg2YAnGLP1q8+cI661Z9q7RI+PttBcVg0EhpWwmknUssYBZWuhU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135561; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=9HOxi7OPD/6ID3Zyg+8N2fKrwSB9VFQyyogmWrMVqlg=; b=GKGDqxZGhTZBYmWpyp+EG51VjzoaogKN6HvYA7Pe8tzsw/aYzE7B1myNJExnnjqJzKVgVGZP8CaH0KqsZHvmG/CjtovuN+Mi4CcDefkyBcfzzTfUQ4Uco+KHAfEu2iyS0p/jsAVF298eXElKyjvwKIY1UWaVewLy9JVA+J74+iM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70946+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 161213556184861.13680351180176; Sun, 31 Jan 2021 15:26:01 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id FtreYY1788612xUkgA8iThgM; Sun, 31 Jan 2021 15:26:01 -0800 X-Received: from mail-qk1-f180.google.com (mail-qk1-f180.google.com [209.85.222.180]) by mx.groups.io with SMTP id smtpd.web10.26297.1612135559341564184 for ; Sun, 31 Jan 2021 15:25:59 -0800 X-Received: by mail-qk1-f180.google.com with SMTP id x81so14633448qkb.0 for ; Sun, 31 Jan 2021 15:25:59 -0800 (PST) X-Gm-Message-State: hBpJixb7R0rUWhMSc6fs0jTNx1787277AA= X-Google-Smtp-Source: ABdhPJwApOMoDSxKJRRQ7xQ07xqHaDDK0HqxDPOIQ4KOTmhNAhGEbqbxljHn7X6o+wxhvPYZd1MFyw== X-Received: by 2002:a37:4d45:: with SMTP id a66mr13843646qkb.12.1612135558136; Sun, 31 Jan 2021 15:25:58 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:57 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 20/21] ArmPkg: Add SMBIOS PCDs to ArmPkg.dec Date: Sun, 31 Jan 2021 16:25:10 -0700 Message-Id: <20210131232511.18340-21-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135561; bh=El5II934RKnB7iRb5xCxd79pJKA4slZIAuRP8momZwU=; h=Cc:Date:From:Reply-To:Subject:To; b=pYW0wuBCcfkB2hjCReOwN9M/DvjIeI2Fm3fHrQ7QVYc5OCIAVOfOV9bdlVEOQQVHXII ipjYnUD/zERmYLVsDyHGRcTpr9dS7yxkz6TLajQYnQRblQKUM6qoFad46Vco4NUIROghf MMvuxofK0Re6mHLYLYPmGeIl9pNlFpZR4uc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Platforms are expected to override these PCDs to provide relevant information to SMBIOS. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm --- ArmPkg/ArmPkg.dec | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index eaf1072d9ef3..f0b136a57af0 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -115,6 +115,20 @@ [PcdsFixedAtBuild.common] # The Primary Core is ClusterId[0] & CoreId[0] gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037 =20 + # + # SMBIOS PCDs + # + gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053 + gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054 + gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055 + gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056 + gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057 + gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071 + gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072 + gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073 + gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074 + gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075 + # # ARM L2x0 PCDs # @@ -215,6 +229,9 @@ [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatch= ableInModule.common] gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045 gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046 =20 + gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058 + gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x= 30000059 + [PcdsFixedAtBuild.common, PcdsDynamic.common] # # ARM Architectural Timer --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70946): https://edk2.groups.io/g/devel/message/70946 Mute This Topic: https://groups.io/mt/80271150/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 16:36:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70947+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70947+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1612135562; cv=none; d=zohomail.com; s=zohoarc; b=OGYE9+c4ZupqIluMOYlYDDRsBwJw/8byPvarpPK5IkAAsbPLNNGdJbT4/A87aFk/8jxwMWw8g6+mxemR4M4hLffhANuiwER3yPMFEGT+c0ZbWyhM9LBePyfBOiR0ArHNTZ+qV8FfCR+d2eHzi+cXq7P2rIbAJkHeobRwknOOSKA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612135562; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=yNepsOIYXMF2RV3PnyUWuMz+WtSuLQDzNtspRMFq3UA=; b=L59Nxo8Jcwj49f7kzaNKSNpwyuRJI/tHi1vIdMhR9qOVRqjaO3vRwArrFejnudEmv9rYvGXhZmBycnADrZeS0CasM8InPcDB3lujh2TmfI0Jn4Iu9lkRnYZIRBmClE7tUh4cgXwkQCkt0pilOKKLuON1cGzuYPzBNqmf9oKB/cU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70947+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1612135562801663.0338214365112; Sun, 31 Jan 2021 15:26:02 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1gqyYY1788612xf8B7LDoHoE; Sun, 31 Jan 2021 15:26:02 -0800 X-Received: from mail-qv1-f53.google.com (mail-qv1-f53.google.com [209.85.219.53]) by mx.groups.io with SMTP id smtpd.web08.26175.1612135561785836036 for ; Sun, 31 Jan 2021 15:26:02 -0800 X-Received: by mail-qv1-f53.google.com with SMTP id w11so7337218qvz.12 for ; Sun, 31 Jan 2021 15:26:01 -0800 (PST) X-Gm-Message-State: VCRpp92e5jqeO8849DE8rklpx1787277AA= X-Google-Smtp-Source: ABdhPJzWE076bu+4qoD7gfsE5BwXV3tgbHX7U+2pn3ysqOhwwszqK7NI6/gABo4OVCyTg28EOpiOFA== X-Received: by 2002:ad4:4e8a:: with SMTP id dy10mr13242561qvb.36.1612135560175; Sun, 31 Jan 2021 15:26:00 -0800 (PST) X-Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:59 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [edk2-devel] [PATCH v7 21/21] ArmPkg: Add Universal/Smbios/SmbiosMiscDxe Date: Sun, 31 Jan 2021 16:25:11 -0700 Message-Id: <20210131232511.18340-22-rebecca@nuviainc.com> In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1612135562; bh=MiDgz5DUyOhVy9VzCPLfifPyMhE7GSKnIwDmFeixM8w=; h=Cc:Date:From:Reply-To:Subject:To; b=u/GEIiGpFhAqvyrkvjTB4noytj4cDeFjNNCZ0aBlo2lbnR93WLMyAQGube4jTFDAt/U 7I/LKQKrh7WWSV6RqPCtPnAKnmNRgW1I39jnPj+TCY0PcHIoPnLp9xHPlywD7OxlcjmRV bEgNyN/9IZUH7ivUMrJWVGEifLGKSPIbIsI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" SmbiosMiscDxe provides SMBIOS tables 0, 1, 2, 3, 13, and 32. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Samer El-Haj-Mahmoud --- ArmPkg/ArmPkg.dsc | 1 + ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 89 +++++= +++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMisc.h | 134 +++++= +++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c | 62 ++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c | 223 +++++= +++++++++++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxeStrings.uni | 22 ++ 6 files changed, 531 insertions(+) diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc index fce86cb6d710..7194eb2d3c44 100644 --- a/ArmPkg/ArmPkg.dsc +++ b/ArmPkg/ArmPkg.dsc @@ -149,6 +149,7 @@ [Components.common] ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf =20 ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf =20 [Components.AARCH64] ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/ArmP= kg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf new file mode 100644 index 000000000000..60d8fe31c219 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf @@ -0,0 +1,89 @@ +#/** @file +# Component description file for SmbiosMisc instance. +# +# Parses the MiscSubclassDataTable and reports any generated data to the D= ataHub. +# All .uni file who tagged with "ToolCode=3D"DUMMY"" in following file li= st is included by +# MiscSubclassDriver.uni file, the StrGather tool will expand MiscSubclas= sDriver.uni file +# and parse all .uni file. +# +# Copyright (c) 2021, NUVIA Inc. All rights reserved.
+# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +# Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ +#**/ + + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D SmbiosMiscDxe + FILE_GUID =3D 7e5e26d4-0be9-401f-b5e1-1c2bda7ca777 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmbiosMiscEntryPoint + +[Sources] + SmbiosMisc.h + SmbiosMiscDataTable.c + SmbiosMiscEntryPoint.c + SmbiosMiscDxeStrings.uni + Type00/MiscBiosVendorData.c + Type00/MiscBiosVendorFunction.c + Type01/MiscSystemManufacturerData.c + Type01/MiscSystemManufacturerFunction.c + Type02/MiscBaseBoardManufacturerData.c + Type02/MiscBaseBoardManufacturerFunction.c + Type03/MiscChassisManufacturerData.c + Type03/MiscChassisManufacturerFunction.c + Type13/MiscNumberOfInstallableLanguagesData.c + Type13/MiscNumberOfInstallableLanguagesFunction.c + Type32/MiscBootInformationData.c + Type32/MiscBootInformationFunction.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + PcdLib + HiiLib + HobLib + MemoryAllocationLib + OemMiscLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Pcd] + gArmTokenSpaceGuid.PcdFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + gArmTokenSpaceGuid.PcdSystemBiosRelease + gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease + gArmTokenSpaceGuid.PcdSystemProductName + gArmTokenSpaceGuid.PcdSystemVersion + gArmTokenSpaceGuid.PcdBaseBoardManufacturer + gArmTokenSpaceGuid.PcdBaseBoardProductName + gArmTokenSpaceGuid.PcdBaseBoardVersion + gArmTokenSpaceGuid.PcdFdBaseAddress + +[Guids] + gEfiGenericVariableGuid + +[Depex] + gEfiSmbiosProtocolGuid + + diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMisc.h b/ArmPkg/Un= iversal/Smbios/SmbiosMiscDxe/SmbiosMisc.h new file mode 100644 index 000000000000..4fd37c4cdc0b --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMisc.h @@ -0,0 +1,134 @@ +/** @file + Header file for the SmbiosMisc Driver. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMBIOS_MISC_H_ +#define SMBIOS_MISC_H_ + +#include +#include + +// +// Data table entry update function. +// +typedef EFI_STATUS (EFIAPI SMBIOS_MISC_DATA_FUNCTION) ( + IN VOID *RecordData, + IN EFI_SMBIOS_PROTOCOL *Smbios + ); + + +// +// Data table entry definition. +// +typedef struct { + // + // intermediate input data for SMBIOS record + // + VOID *RecordData; + SMBIOS_MISC_DATA_FUNCTION *Function; +} SMBIOS_MISC_DATA_TABLE; + + +// +// SMBIOS table extern definitions +// +#define SMBIOS_MISC_TABLE_EXTERNS(NAME1, NAME2, NAME3) \ +extern NAME1 NAME2 ## Data; \ +extern SMBIOS_MISC_DATA_FUNCTION NAME3 ## Function; + + +// +// SMBIOS data table entries +// +// This is used to define a pair of table structure pointer and functions +// in order to iterate through the list of tables, populate them and add +// them into the system. +#define SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION(NAME1, NAME2) \ +{ \ + & NAME1 ## Data, \ + NAME2 ## Function \ +} + +// +// Global definition macros. +// +#define SMBIOS_MISC_TABLE_DATA(NAME1, NAME2) \ + NAME1 NAME2 ## Data + +#define SMBIOS_MISC_TABLE_FUNCTION(NAME2) \ + EFI_STATUS EFIAPI NAME2 ## Function( \ + IN VOID *RecordData, \ + IN EFI_SMBIOS_PROTOCOL *Smbios \ + ) + +// +// Data Table Array Entries +// +extern EFI_HII_HANDLE mSmbiosMiscHiiHandle; + +typedef struct _SMBIOS_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING{ + UINT8 *LanguageSignature; + EFI_STRING_ID InstallableLanguageLongString; + EFI_STRING_ID InstallableLanguageAbbreviateString; +} SMBIOS_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING; + + +/** + Adds an SMBIOS record. + + @param Buffer The data for the SMBIOS record. + The format of the record is determined by + EFI_SMBIOS_TABLE_HEADER.Type. The size of the + formatted area is defined by EFI_SMBIOS_TABLE_HEAD= ER.Length + and either followed by a double-null (0x0000) or a= set + of null terminated strings and a null. + @param SmbiosHandle A unique handle will be assigned to the SMBIOS rec= ord + if not NULL. + + @retval EFI_SUCCESS Record was added. + @retval EFI_OUT_OF_RESOURCES Record was not added due to lack of system= resources. + @retval EFI_ALREADY_STARTED The SmbiosHandle passed in was already in = use. + +**/ +EFI_STATUS +SmbiosMiscAddRecord ( + IN UINT8 *Buffer, + IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle OPTIONAL + ); + +/** + Get Link Type Handle. + + @param [in] SmbiosType Get this Type from SMBIOS table + @param [out] HandleArray Pointer to handle array which will be freed = by caller + @param [out] HandleCount Pointer to handle count + +**/ +VOID +SmbiosMiscGetLinkTypeHandle( + IN UINT8 SmbiosType, + OUT UINT16 **HandleArray, + OUT UINTN *HandleCount + ); + +// +// Data Table Array +// +extern SMBIOS_MISC_DATA_TABLE mSmbiosMiscDataTable[]; + +// +// Data Table Array Entries +// +extern UINTN mSmbiosMiscDataTableEntries; +extern UINT8 mSmbiosMiscDxeStrings[]; + +#endif // SMBIOS_MISC_H_ diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c b/= ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c new file mode 100644 index 000000000000..ac16c3a2688e --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c @@ -0,0 +1,62 @@ +/** @file + This file provides SMBIOS Misc Type. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent\ + +**/ + +#include "SmbiosMisc.h" + +SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE0, + MiscBiosVendor, + MiscBiosVendor) +SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE1, + MiscSystemManufacturer, + MiscSystemManufacturer) +SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE3, + MiscChassisManufacturer, + MiscChassisManufacturer) +SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE2, + MiscBaseBoardManufacturer, + MiscBaseBoardManufacturer) +SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE13, + MiscNumberOfInstallableLanguages, + MiscNumberOfInstallableLanguages) +SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE32, + MiscBootInformation, + MiscBootInformation) + + +SMBIOS_MISC_DATA_TABLE mSmbiosMiscDataTable[] =3D { + // Type0 + SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBiosVendor, + MiscBiosVendor), + // Type1 + SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscSystemManufacturer, + MiscSystemManufacturer), + // Type3 + SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscChassisManufacturer, + MiscChassisManufacturer), + // Type2 + SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBaseBoardManufacturer, + MiscBaseBoardManufacturer), + // Type13 + SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscNumberOfInstallableLangua= ges, + MiscNumberOfInstallableLangua= ges), + // Type32 + SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBootInformation, + MiscBootInformation), +}; + + +// +// Number of Data Table entries. +// +UINTN mSmbiosMiscDataTableEntries =3D + (sizeof (mSmbiosMiscDataTable)) / sizeof (SMBIOS_MISC_DATA_TABLE); diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c b= /ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c new file mode 100644 index 000000000000..eb7f4cb4c16d --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c @@ -0,0 +1,223 @@ +/** @file + This driver parses the mSmbiosMiscDataTable structure and reports + any generated data using SMBIOS protocol. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +#include "SmbiosMisc.h" + + +STATIC EFI_HANDLE mSmbiosMiscImageHandle; +STATIC EFI_SMBIOS_PROTOCOL *mSmbiosMiscSmbios =3D NULL; + +EFI_HII_HANDLE mSmbiosMiscHiiHandle; + +/** + Standard EFI driver point. This driver parses the mSmbiosMiscDataTable + structure and reports any generated data using SMBIOS protocol. + + @param ImageHandle Handle for the image of this driver + @param SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS The data was successfully stored. + +**/ +EFI_STATUS +EFIAPI +SmbiosMiscEntryPoint( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINTN Index; + EFI_STATUS EfiStatus; + + mSmbiosMiscImageHandle =3D ImageHandle; + + EfiStatus =3D gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, + (VOID**)&mSmbiosMiscSmbios); + if (EFI_ERROR (EfiStatus)) { + DEBUG ((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", EfiSta= tus)); + return EfiStatus; + } + + mSmbiosMiscHiiHandle =3D HiiAddPackages (&gEfiCallerIdGuid, + mSmbiosMiscImageHandle, + SmbiosMiscDxeStrings, + NULL + ); + if (mSmbiosMiscHiiHandle =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < mSmbiosMiscDataTableEntries; ++Index) { + // + // If the entry have a function pointer, just log the data. + // + if (mSmbiosMiscDataTable[Index].Function !=3D NULL) { + EfiStatus =3D (*mSmbiosMiscDataTable[Index].Function)(mSmbiosMiscDat= aTable[Index].RecordData, + mSmbiosMiscSmbios + ); + + if (EFI_ERROR(EfiStatus)) { + DEBUG ((DEBUG_ERROR, "Misc smbios store error. Index=3D%d," + "ReturnStatus=3D%r\n", Index, EfiStatus)); + return EfiStatus; + } + } + } + + return EfiStatus; +} + + +/** + Adds an SMBIOS record. + + @param Buffer The data for the SMBIOS record. + The format of the record is determined by + EFI_SMBIOS_TABLE_HEADER.Type. The size of the + formatted area is defined by EFI_SMBIOS_TABLE_HEAD= ER.Length + and either followed by a double-null (0x0000) or a= set + of null terminated strings and a null. + @param SmbiosHandle A unique handle will be assigned to the SMBIOS rec= ord + if not NULL. + + @retval EFI_SUCCESS Record was added. + @retval EFI_OUT_OF_RESOURCES Record was not added due to lack of system= resources. + @retval EFI_ALREADY_STARTED The SmbiosHandle passed in was already in = use. + +**/ +EFI_STATUS +SmbiosMiscAddRecord ( + IN UINT8 *Buffer, + IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle OPTIONAL + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE Handle; + + Handle =3D SMBIOS_HANDLE_PI_RESERVED; + + if (SmbiosHandle !=3D NULL) { + Handle =3D *SmbiosHandle; + } + + Status =3D mSmbiosMiscSmbios->Add ( + mSmbiosMiscSmbios, + NULL, + &Handle, + (EFI_SMBIOS_TABLE_HEADER *)Buffer + ); + + if (SmbiosHandle !=3D NULL) { + *SmbiosHandle =3D Handle; + } + + return Status; +} + + +/** Fetches the number of handles of the specified SMBIOS type. + * + * @param SmbiosType The type of SMBIOS record to look for. + * + * @return The number of handles + * +**/ +STATIC +UINTN +GetHandleCount ( + IN UINT8 SmbiosType + ) +{ + UINTN HandleCount; + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_SMBIOS_TABLE_HEADER *Record; + + HandleCount =3D 0; + + // Iterate through entries to get the number + do { + Status =3D mSmbiosMiscSmbios->GetNext (mSmbiosMiscSmbios, + &SmbiosHandle, + &SmbiosType, + &Record, + NULL + ); + + if (Status =3D=3D EFI_SUCCESS) { + HandleCount++; + } + } while (!EFI_ERROR (Status)); + + return HandleCount; +} + +/** + Fetches a list of the specified SMBIOS table types. + + @param[in] SmbiosType The type of table to fetch + @param[out] **HandleArray The array of handles + @param[out] *HandleCount Number of handles in the array +**/ +VOID +SmbiosMiscGetLinkTypeHandle( + IN UINT8 SmbiosType, + OUT SMBIOS_HANDLE **HandleArray, + OUT UINTN *HandleCount + ) +{ + UINTN Index; + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_SMBIOS_TABLE_HEADER *Record; + + if (mSmbiosMiscSmbios =3D=3D NULL) { + return; + } + + SmbiosHandle =3D SMBIOS_HANDLE_PI_RESERVED; + *HandleCount =3D GetHandleCount (SmbiosType); + + *HandleArray =3D AllocateZeroPool (sizeof (SMBIOS_HANDLE) * (*HandleCoun= t)); + if (*HandleArray =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "HandleArray allocate memory resource failed.\n")= ); + *HandleCount =3D 0; + return; + } + + SmbiosHandle =3D SMBIOS_HANDLE_PI_RESERVED; + + for (Index =3D 0; Index < (*HandleCount); Index++) { + Status =3D mSmbiosMiscSmbios->GetNext (mSmbiosMiscSmbios, + &SmbiosHandle, + &SmbiosType, + &Record, + NULL + ); + + if (!EFI_ERROR (Status)) { + (*HandleArray)[Index] =3D Record->Handle; + } else { + break; + } + } +} + diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxeStrings.uni= b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxeStrings.uni new file mode 100644 index 000000000000..6f877e706922 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxeStrings.uni @@ -0,0 +1,22 @@ +/** @file + * Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + * + * Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ * Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ * Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ * Copyright (c) 2015, Linaro Limited. All rights reserved.
+ * SPDX-License-Identifier: BSD-2-Clause-Patent + * + * +**/ + + +/=3D# + +#langdef en-US "English" + +#include "Type00/MiscBiosVendor.uni" +#include "Type01/MiscSystemManufacturer.uni" +#include "Type02/MiscBaseBoardManufacturer.uni" +#include "Type03/MiscChassisManufacturer.uni" +#include "Type13/MiscNumberOfInstallableLanguages.uni" --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70947): https://edk2.groups.io/g/devel/message/70947 Mute This Topic: https://groups.io/mt/80271152/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-