From nobody Tue Feb 10 06:25:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70623+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70623+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1611222709; cv=none; d=zohomail.com; s=zohoarc; b=ameA2iMmEQ+RAQzjiN3wuDxdjxlKsSYyPoXzemfPxwHZiL/wuCtUqGfmki56jbzNQF5OxoHxiz7a6Aze8ebB/SQMFvjW0vFhtm0KqhGSlwbFw3co/+o3GFvCBZQSMdoLDKsrdWoSpRhSgydMBrZSfxercloLKG5ajEa464tuWxE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611222709; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=7VKj3DyZvOBRY62cDTF7gklblKJNyIQQQ3MrU6oSFGo=; b=B362j0NM7mU2SwgbukZh7wlYp8Y7Ax4x/3qZ52R9LMZdaBTcp0X89z0iDYkdybD8rqMdNfcbtne3SrMqfJ0t8/h1kjK25VhqbZzuKTTjfNnxOveW6X4DC7NbqOZoP4seWKDofAl49Xr50tj3PQyQn1oMVe0Lsw4h5YLOUQlq0Es= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70623+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1611222709371922.216419708058; Thu, 21 Jan 2021 01:51:49 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id IZlmYY1788612x6dXohhMvf6; Thu, 21 Jan 2021 01:51:48 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.4986.1611222708318398151 for ; Thu, 21 Jan 2021 01:51:48 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 37EEC1509; Thu, 21 Jan 2021 01:51:38 -0800 (PST) X-Received: from e120189.arm.com (unknown [10.57.40.199]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1F3403F719; Thu, 21 Jan 2021 01:51:36 -0800 (PST) From: "PierreGondois" To: devel@edk2.groups.io, ardb+tianocore@kernel.org, leif@nuviainc.com Cc: sami.mujawar@arm.com Subject: [edk2-devel] [PATCH v1 01/27] ArmPkg: Fix Ecc error 8001 in Chipset Date: Thu, 21 Jan 2021 09:50:53 +0000 Message-Id: <20210121095119.22143-2-Pierre.Gondois@arm.com> In-Reply-To: <20210121095119.22143-1-Pierre.Gondois@arm.com> References: <20210121095119.22143-1-Pierre.Gondois@arm.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pierre.gondois@arm.com X-Gm-Message-State: 5YFXS3G2lrpaPj2Y78XtrUKrx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1611222708; bh=+xhkM9LiM0Bs8BgcOlq8u4VMhVxZDl2WUivDQ2Pbgzk=; h=Cc:Date:From:Reply-To:Subject:To; b=OmMNAXg7jxzg7/0FzSzU5VLIUTqCvi4eOaJb+7i+zE1RE0uTLihGi5RxOqrdfd4sngs htjZHhefR2myKdpzSeP3Abp/fct6BUNRKhETVNQDSzGkDV1NJDXHKIesXrWVPHXb1DhAW TD2uwEDTQssUB99nWMtyfsLAr9UQbDV5y08= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pierre Gondois This patch fixes the following Ecc reported error: Only capital letters are allowed to be used for #define declarations Edk2 coding standard stating that: "Names starting with one or two underscores, such as _MACRO_GUARD_FILE_NAME_H_, must not be used." the include guard of ArmCortexA5x.h is also updated. Ref: https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/ 5_source_files/53_include_files# 5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard Signed-off-by: Pierre Gondois Reviewed-by: Sami Mujawar --- The changes can be seen at: https://github.com/PierreARM/edk2/tree/1552_Ecc= _ArmPkg_BIS_v1 ArmPkg/Include/Chipset/AArch64.h | 12 ++++++------ ArmPkg/Include/Chipset/ArmCortexA5x.h | 6 +++--- ArmPkg/Include/Chipset/ArmV7.h | 4 ++-- .../ArmExceptionLib/AArch64/ExceptionSupport.S | 10 +++++----- ArmPlatformPkg/PrePeiCore/AArch64/Exception.S | 10 +++++----- 5 files changed, 21 insertions(+), 21 deletions(-) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArc= h64.h index 0ade5cce91c3..d49f4d60b15d 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -1,7 +1,7 @@ /** @file Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.
+ Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -39,7 +39,7 @@ // MIDR - Main ID Register definitions #define ARM_CPU_TYPE_SHIFT 4 #define ARM_CPU_TYPE_MASK 0xFFF -#define ARM_CPU_TYPE_AEMv8 0xD0F +#define ARM_CPU_TYPE_AEMV8 0xD0F #define ARM_CPU_TYPE_A53 0xD03 #define ARM_CPU_TYPE_A57 0xD07 #define ARM_CPU_TYPE_A72 0xD08 @@ -97,10 +97,10 @@ #define ARM_VECTOR_CUR_SP0_FIQ 0x100 #define ARM_VECTOR_CUR_SP0_SERR 0x180 -#define ARM_VECTOR_CUR_SPx_SYNC 0x200 -#define ARM_VECTOR_CUR_SPx_IRQ 0x280 -#define ARM_VECTOR_CUR_SPx_FIQ 0x300 -#define ARM_VECTOR_CUR_SPx_SERR 0x380 +#define ARM_VECTOR_CUR_SPX_SYNC 0x200 +#define ARM_VECTOR_CUR_SPX_IRQ 0x280 +#define ARM_VECTOR_CUR_SPX_FIQ 0x300 +#define ARM_VECTOR_CUR_SPX_SERR 0x380 #define ARM_VECTOR_LOW_A64_SYNC 0x400 #define ARM_VECTOR_LOW_A64_IRQ 0x480 diff --git a/ArmPkg/Include/Chipset/ArmCortexA5x.h b/ArmPkg/Include/Chipset= /ArmCortexA5x.h index 847a6e00430b..2661ed8c0182 100644 --- a/ArmPkg/Include/Chipset/ArmCortexA5x.h +++ b/ArmPkg/Include/Chipset/ArmCortexA5x.h @@ -6,8 +6,8 @@ **/ -#ifndef __ARM_CORTEX_A5x_H__ -#define __ARM_CORTEX_A5x_H__ +#ifndef ARM_CORTEX_A5X_H__ +#define ARM_CORTEX_A5X_H__ // // Cortex A5x feature bit definitions @@ -41,4 +41,4 @@ ArmUnsetCpuExCrBit ( IN UINT64 Bits ); -#endif +#endif // ARM_CORTEX_A5X_H__ diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h index fe91031ef33d..025f87a56d16 100644 --- a/ArmPkg/Include/Chipset/ArmV7.h +++ b/ArmPkg/Include/Chipset/ArmV7.h @@ -1,7 +1,7 @@ /** @file Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -70,7 +70,7 @@ // MIDR - Main ID Register definitions #define ARM_CPU_TYPE_SHIFT 4 #define ARM_CPU_TYPE_MASK 0xFFF -#define ARM_CPU_TYPE_AEMv8 0xD0F +#define ARM_CPU_TYPE_AEMV8 0xD0F #define ARM_CPU_TYPE_A53 0xD03 #define ARM_CPU_TYPE_A57 0xD07 #define ARM_CPU_TYPE_A15 0xC0F diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/Ar= mPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S index 5b10a1339ac1..9202952ee9c0 100644 --- a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S +++ b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S @@ -1,5 +1,5 @@ // -// Copyright (c) 2011 - 2014 ARM LTD. All rights reserved.
+// Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
// Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<= BR> // Copyright (c) 2016 HP Development Company, L.P. // @@ -200,19 +200,19 @@ ASM_PFX(SErrorSP0): // // Current EL with SPx: 0x200 - 0x380 // -VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC) +VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SYNC) ASM_PFX(SynchronousExceptionSPx): ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, SP0 -VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ) +VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_IRQ) ASM_PFX(IrqSPx): ExceptionEntry EXCEPT_AARCH64_IRQ -VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ) +VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_FIQ) ASM_PFX(FiqSPx): ExceptionEntry EXCEPT_AARCH64_FIQ -VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR) +VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SERR) ASM_PFX(SErrorSPx): ExceptionEntry EXCEPT_AARCH64_SERROR diff --git a/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S b/ArmPlatformPkg= /PrePeiCore/AArch64/Exception.S index 59a3da2721e7..43e40f97c3ee 100644 --- a/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S +++ b/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S @@ -1,5 +1,5 @@ # -# Copyright (c) 2011-2014, ARM Limited. All rights reserved. +# Copyright (c) 2011-2021, Arm Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -51,22 +51,22 @@ _DefaultSError_t: mov x0, #EXCEPT_AARCH64_SERROR TO_HANDLER -VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC) +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_SYNC) _DefaultSyncExceptHandler_h: mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS TO_HANDLER -VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ) +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_IRQ) _DefaultIrq_h: mov x0, #EXCEPT_AARCH64_IRQ TO_HANDLER -VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ) +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_FIQ) _DefaultFiq_h: mov x0, #EXCEPT_AARCH64_FIQ TO_HANDLER -VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR) +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_SERR) _DefaultSError_h: mov x0, #EXCEPT_AARCH64_SERROR TO_HANDLER -- 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70623): https://edk2.groups.io/g/devel/message/70623 Mute This Topic: https://groups.io/mt/80000379/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-