From nobody Tue Feb 10 12:59:26 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70303+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70303+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1610642212; cv=none; d=zohomail.com; s=zohoarc; b=inCQVE0elgmOycXwaJJQxJnKparQc6rvJWxB45UBdTrsJDIp2OtBOHw7pC0sNCzg74sqWCBDMNqEJFfVaKDkQqdMr8cRKpW898+BgS2Mn47vHwNqdc+EVL7vju7fKx/iV/SNZBYw2dvtRnT83ZTLgQ42rJIV6TcZJVdwa7hvW5I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610642212; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cdtmu6FCcMXem789lASVpZfcT6Tn5F861CVmFjMA3d8=; b=Ygdjr+KSqsKPecFZISBAggx4lECBCCnMt1chIBPRwwE2VbDa4aCJoryD8ECZcyJY7hllkyxZOHYXW2M2ZccEUHGST8fjWeKOGS21wL/QLMCoIeBe5a1V4wD9IaDccJODEzgvrkwPTBz12Kq0SakJReYp65EyGV2o5Ym9+g7dC58= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70303+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1610642212969489.1216595396528; Thu, 14 Jan 2021 08:36:52 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id E764YY1788612xyvagkGgj6F; Thu, 14 Jan 2021 08:36:52 -0800 X-Received: from mail-io1-f52.google.com (mail-io1-f52.google.com [209.85.166.52]) by mx.groups.io with SMTP id smtpd.web09.4095.1610642206514332856 for ; Thu, 14 Jan 2021 08:36:46 -0800 X-Received: by mail-io1-f52.google.com with SMTP id y19so12418026iov.2 for ; Thu, 14 Jan 2021 08:36:46 -0800 (PST) X-Gm-Message-State: JvufQG3MLTQhSKkD2n7JwfK9x1787277AA= X-Google-Smtp-Source: ABdhPJxEkIacTvdmelIvahxQ9PBhvL+xMnQ8QafeH/fJPhnzJ4hUZYHp8SMAotc2QxBP3svKua7Fzw== X-Received: by 2002:a05:6638:2686:: with SMTP id o6mr7137358jat.68.1610642205627; Thu, 14 Jan 2021 08:36:45 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id y5sm3711920ilj.35.2021.01.14.08.36.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 08:36:44 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Leif Lindholm , Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Sami Mujawar Subject: [edk2-devel] [PATCH v6 08/22] ArmPkg: Update ArmLibPrivate.h with cache register definitions Date: Thu, 14 Jan 2021 09:36:14 -0700 Message-Id: <20210114163628.31952-9-rebecca@nuviainc.com> In-Reply-To: <20210114163628.31952-1-rebecca@nuviainc.com> References: <20210114163628.31952-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1610642212; bh=ymh4xDXy/2J4tR40uD2WaisQCpzqZ2DcBu2h46wGKSQ=; h=Cc:Date:From:Reply-To:Subject:To; b=pi3kTxaeNhPWNb64I1pe6awAXZQVgRL0DOkxISvYlgSoUwtpn2lxfPHlTTxe/tjc4i9 mA2/VzqaRVXFU1fRuCE2t/UGERFHyq5eJg50QeUy7L3ikTiSXJ57F83/k0l48yo0+649S J2b4knEp//jDXR7r+tckzzn7KUQxLOAhu/8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Update the cache definitions in ArmLibPrivate.h based on current ARMv8 documentation. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 97 ++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/= ArmLibPrivate.h index 8959bdd9d73c..77e592a99def 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -1,5 +1,7 @@ /** @file + ArmLibPrivate.h =20 + Copyright (c) 2020, NUVIA Inc. All rights reserved.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -50,6 +52,101 @@ #define CACHE_ARCHITECTURE_UNIFIED (0UL) #define CACHE_ARCHITECTURE_SEPARATE (1UL) =20 + +/// Defines the structure of the CSSELR (Cache Size Selection) register +typedef union { + struct { + UINT32 InD :1; ///< Instruction not Data bit + UINT32 Level :3; ///< Cache level (zero based) + UINT32 TnD :1; ///< Allocation not Data bit + UINT32 Reserved :27; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSELR_DATA; + +/// The cache type values for the InD field of the CSSELR register +typedef enum +{ + /// Select the data or unified cache + CsselrCacheTypeDataOrUnified =3D 0, + /// Select the instruction cache + CsselrCacheTypeInstruction, + CsselrCacheTypeMax +} CSSELR_CACHE_TYPE; + +/// Defines the structure of the CCSIDR (Current Cache Size ID) register +typedef union { + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in ca= che) - 4) + UINT64 Associativity :10; ///< Associativity - 1 + UINT64 NumSets :15; ///< Number of sets in the cache -1 + UINT64 Unknown :4; ///< Reserved, UNKNOWN + UINT64 Reserved :32; ///< Reserved, RES0 + } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX= is not supported. + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in ca= che) - 4) + UINT64 Associativity :21; ///< Associativity - 1 + UINT64 Reserved1 :8; ///< Reserved, RES0 + UINT64 NumSets :24; ///< Number of sets in the cache -1 + UINT64 Reserved2 :8; ///< Reserved, RES0 + } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX = is supported. + struct { + UINT64 LineSize : 3; + UINT64 Associativity : 21; + UINT64 Reserved : 8; + UINT64 Unallocated : 32; + } BitsCcidxAA32; + UINT64 Data; ///< The entire 64-bit value +} CCSIDR_DATA; + +/// Defines the structure of the AARCH32 CCSIDR2 register. +typedef union { + struct { + UINT32 NumSets :24; ///< Number of sets in the cache - 1 + UINT32 Reserved :8; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSIDR2_DATA; + +/** Defines the structure of the CLIDR (Cache Level ID) register. + * + * The lower 32 bits are the same for both AARCH32 and AARCH64 + * so we can use the same structure for both. +**/ +typedef union { + struct { + UINT32 Ctype1 : 3; ///< Level 1 cache type + UINT32 Ctype2 : 3; ///< Level 2 cache type + UINT32 Ctype3 : 3; ///< Level 3 cache type + UINT32 Ctype4 : 3; ///< Level 4 cache type + UINT32 Ctype5 : 3; ///< Level 5 cache type + UINT32 Ctype6 : 3; ///< Level 6 cache type + UINT32 Ctype7 : 3; ///< Level 7 cache type + UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable + UINT32 LoC : 3; ///< Level of Coherency + UINT32 LoUU : 3; ///< Level of Unification Uniprocessor + UINT32 Icb : 3; ///< Inner Cache Boundary + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CLIDR_DATA; + +/// The cache types reported in the CLIDR register. +typedef enum { + /// No cache is present + ClidrCacheTypeNone =3D 0, + /// There is only an instruction cache + ClidrCacheTypeInstructionOnly, + /// There is only a data cache + ClidrCacheTypeDataOnly, + /// There are separate data and instruction caches + ClidrCacheTypeSeparate, + /// There is a unified cache + ClidrCacheTypeUnified, + ClidrCacheTypeMax +} CLIDR_CACHE_TYPE; + +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * level)) & 0b111) + VOID CPSRMaskInsert ( IN UINT32 Mask, --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70303): https://edk2.groups.io/g/devel/message/70303 Mute This Topic: https://groups.io/mt/79679245/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-