From nobody Tue Apr 23 23:41:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70172+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70172+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1610490434; cv=none; d=zohomail.com; s=zohoarc; b=eMp7r0T5g9NJzua3TL5tN4ftBw7PohQD7aHUWW0VPnBbw+qhzH3ZCUMZz8Br/5Hn/24mj5zPItjNHwqUJisnl064zOQAsAcaQxzve47JjAWz4qF/UkPARNaIxh+YED9O7l5hc6J+10ATXa6b0lUj/CGl8jMKEKKOBhXdtiRZT/g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610490434; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jcyQgA9tUQhd1oKdvQkZ/V7Sxm5/RnN2D2orulWhYbA=; b=JkQB3bl2gGTPyGNxUMBP+EThqodGSm4VUKKV1lC0j4YiEA5oPYZHtDZzodGkq+ABgb7FYCWA2oaEKE8SFq3TM1gMsiGtpJT264Kt+zjZxVKMUKgb6JRGCT471b9UTVJXojttpHQaxc/QwTrCxHk8yg0/bwYEx0sWHM5v5593jIE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70172+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1610490434851425.6493083307838; Tue, 12 Jan 2021 14:27:14 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id KEskYY1788612xW3dTzqCtTd; Tue, 12 Jan 2021 14:27:14 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.17557.1610490433938903119 for ; Tue, 12 Jan 2021 14:27:14 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4FF1C1063; Tue, 12 Jan 2021 14:27:12 -0800 (PST) X-Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.28.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 47F873F719; Tue, 12 Jan 2021 14:27:12 -0800 (PST) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, awarkentin@vmware.com, samer.el-haj-mahmoud@arm.com, leif@nuviainc.com, ard.biesheuvel@arm.com, Jeremy Linton Subject: [edk2-devel] [RFC 1/3] rpi4: Add XHCI/PCI selection menu Date: Tue, 12 Jan 2021 16:27:06 -0600 Message-Id: <20210112222708.1757044-2-jeremy.linton@arm.com> In-Reply-To: <20210112222708.1757044-1-jeremy.linton@arm.com> References: <20210112222708.1757044-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: L42FDpPgyVJeMS3PqQ9Ei8o3x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1610490434; bh=2LfN4wbnQUex2U0Wp8Li3LhpsFG/h8G5Tfh7JBqT/e0=; h=Cc:Date:From:Reply-To:Subject:To; b=Ja5Om9Vk1Et7OAXf/+LriOlFYF/I8ugPhpsnCuoBEGoTp42KRyBPVvLwo+VmZJufxqL VJuj++Os3J2Le9PKASC3/gxifORpJ5yQeON2EgG797huw+52aDjTWXLoApCI2g6JxRjlt F2eqQthQGqMnEj1vaA41ol2mZ8UYLroHdpw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" ARM has standardized a SMC PCI conduit that can be used to access the PCI config space in a standardized way. This functionality doesn't yet exist in many OS/Distro's. Lets add another advanced config item that allows the user to toggle between presenting the XHCI on the base rpi4 as a platform device, or presenting this newer PCIe conduit. Signed-off-by: Jeremy Linton Reviewed-by: Andrei Warkentin --- Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 32 ++++++++++++++++++= ++++ .../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 3 ++ .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 ++++ .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 13 +++++++++ Platform/RaspberryPi/Include/ConfigVars.h | 4 +++ Platform/RaspberryPi/RPi3/RPi3.dsc | 9 ++++++ Platform/RaspberryPi/RPi4/RPi4.dsc | 11 ++++++++ Platform/RaspberryPi/RaspberryPi.dec | 3 ++ 8 files changed, 80 insertions(+) diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c index 6fcbdcdd17..7a3b8e9068 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c @@ -266,6 +266,38 @@ SetupVariables ( ASSERT_EFI_ERROR (Status); } =20 + if (mModelFamily >=3D 4) { + Size =3D sizeof (UINT32); + Status =3D gRT->GetVariable (L"XhciPci", + &gConfigDxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status) || (Var32 !=3D 2)) { + // enable Xhci by default + Status =3D PcdSet32S (PcdXhciPci, 1); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet32S (PcdXhci, 1); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet32S (PcdPci, 0); + ASSERT_EFI_ERROR (Status); + } else { + // enable PCIe + Status =3D PcdSet32S (PcdXhciPci, 2); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet32S (PcdXhci, 0); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet32S (PcdPci, 1); + ASSERT_EFI_ERROR (Status); + } + } else { + // disable pcie and xhci + Status =3D PcdSet32S (PcdXhciPci, 0); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet32S (PcdXhci, 0); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet32S (PcdPci, 0); + ASSERT_EFI_ERROR (Status); + } + Size =3D sizeof (AssetTagVar); Status =3D gRT->GetVariable (L"AssetTag", &gConfigDxeFormSetGuid, diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf b/Platfor= m/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf index 544e3b3e10..aa0fbc7e25 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf @@ -92,6 +92,9 @@ gRaspberryPiTokenSpaceGuid.PcdRamLimitTo3GB gRaspberryPiTokenSpaceGuid.PcdFanOnGpio gRaspberryPiTokenSpaceGuid.PcdFanTemp + gRaspberryPiTokenSpaceGuid.PcdXhciPci + gRaspberryPiTokenSpaceGuid.PcdXhci + gRaspberryPiTokenSpaceGuid.PcdPci =20 [Depex] gPcdProtocolGuid AND gRaspberryPiFirmwareProtocolGuid diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni b/Plat= form/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni index 2afe8f32ae..34efb82f57 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni @@ -57,6 +57,11 @@ #string STR_ADVANCED_FANTEMP_PROMPT #language en-US "ACPI fan temperatur= e" #string STR_ADVANCED_FANTEMP_HELP #language en-US "Cycle a fan at C" =20 +#string STR_ADVANCED_XHCIPCI_PROMPT #language en-US "ACPI XHCI/PCIe" +#string STR_ADVANCED_XHCIPCI_HELP #language en-US "OS sees XHCI USB pl= atform device or PCIe bridge" +#string STR_ADVANCED_XHCIPCI_XHCI #language en-US "XHCI" +#string STR_ADVANCED_XHCIPCI_PCIE #language en-US "PCIe" + #string STR_ADVANCED_ASSET_TAG_PROMPT #language en-US "Asset Tag" #string STR_ADVANCED_ASSET_TAG_HELP #language en-US "Set the system Asse= t Tag" =20 diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr b/Plat= form/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr index de5e43471a..4d5876eb24 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr @@ -56,6 +56,11 @@ formset name =3D FanTemp, guid =3D CONFIGDXE_FORM_SET_GUID; =20 + efivarstore ADVANCED_XHCIPCI_VARSTORE_DATA, + attribute =3D EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME= _ACCESS | EFI_VARIABLE_NON_VOLATILE, + name =3D XhciPci, + guid =3D CONFIGDXE_FORM_SET_GUID; + efivarstore SYSTEM_TABLE_MODE_VARSTORE_DATA, attribute =3D EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME= _ACCESS | EFI_VARIABLE_NON_VOLATILE, name =3D SystemTableMode, @@ -207,6 +212,14 @@ formset default =3D 60, endnumeric; endif; + + oneof varid =3D XhciPci.Value, + prompt =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_PROMPT), + help =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_HELP), + flags =3D NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + option text =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_XHCI), value= =3D 1, flags =3D DEFAULT; + option text =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_PCIE), value= =3D 2, flags =3D 0; + endoneof; #endif string varid =3D AssetTag.AssetTag, prompt =3D STRING_TOKEN(STR_ADVANCED_ASSET_TAG_PROMPT), diff --git a/Platform/RaspberryPi/Include/ConfigVars.h b/Platform/Raspberry= Pi/Include/ConfigVars.h index c185bfe28b..eb08ad8987 100644 --- a/Platform/RaspberryPi/Include/ConfigVars.h +++ b/Platform/RaspberryPi/Include/ConfigVars.h @@ -77,6 +77,10 @@ typedef struct { } ADVANCED_FANTEMP_VARSTORE_DATA; =20 typedef struct { + UINT32 Value; +} ADVANCED_XHCIPCI_VARSTORE_DATA; + +typedef struct { #define SYSTEM_TABLE_MODE_ACPI 0 #define SYSTEM_TABLE_MODE_BOTH 1 #define SYSTEM_TABLE_MODE_DT 2 diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc b/Platform/RaspberryPi/RPi3= /RPi3.dsc index 530b42796a..0aeb27d69d 100644 --- a/Platform/RaspberryPi/RPi3/RPi3.dsc +++ b/Platform/RaspberryPi/RPi3/RPi3.dsc @@ -514,6 +514,15 @@ =20 gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberr= yPiTokenSpaceGuid|0x0|0 =20 + # Select XHCI/PCIe mode (not valid on rpi3) + # + # 0 - DISABLED + # + gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0= x0|0 + # SSDT selectors + gRaspberryPiTokenSpaceGuid.PcdXhci|L"Xhci"|gConfigDxeFormSetGuid|0x0|0 + gRaspberryPiTokenSpaceGuid.PcdPci|L"Pci"|gConfigDxeFormSetGuid|0x0|0 + # # Common UEFI ones. # diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4= /RPi4.dsc index 0cd1014095..d5952288cc 100644 --- a/Platform/RaspberryPi/RPi4/RPi4.dsc +++ b/Platform/RaspberryPi/RPi4/RPi4.dsc @@ -528,6 +528,17 @@ =20 gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberr= yPiTokenSpaceGuid|0x0|0 =20 + # Select XHCI/PCIe mode + # + # 0 - DISABLED (not valid for rpi4) + # 1 - Xhci Enabled (default) + # 2 - Pcie Enabled + # + gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0= x0|1 + # SSDT selectors + gRaspberryPiTokenSpaceGuid.PcdXhci|L"Xhci"|gConfigDxeFormSetGuid|0x0|1 + gRaspberryPiTokenSpaceGuid.PcdPci|L"Pci"|gConfigDxeFormSetGuid|0x0|0 + # # Common UEFI ones. # diff --git a/Platform/RaspberryPi/RaspberryPi.dec b/Platform/RaspberryPi/Ra= spberryPi.dec index 10723036aa..6c7d4e5116 100644 --- a/Platform/RaspberryPi/RaspberryPi.dec +++ b/Platform/RaspberryPi/RaspberryPi.dec @@ -69,3 +69,6 @@ gRaspberryPiTokenSpaceGuid.PcdFanOnGpio|0|UINT32|0x0000001C gRaspberryPiTokenSpaceGuid.PcdFanTemp|0|UINT32|0x0000001D gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|0|UINT32|0x0000001E + gRaspberryPiTokenSpaceGuid.PcdXhci|0|UINT32|0x0000001F + gRaspberryPiTokenSpaceGuid.PcdPci|0|UINT32|0x00000020 + gRaspberryPiTokenSpaceGuid.PcdXhciPci|0|UINT32|0x00000021 --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70172): https://edk2.groups.io/g/devel/message/70172 Mute This Topic: https://groups.io/mt/79637124/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 23:41:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70171+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70171+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1610490439; cv=none; d=zohomail.com; s=zohoarc; b=IhtMuYSy7/Py6XZnJkqFoYHiATSNI0YydUPXOCKseTVXLEuKiESCIfJnr6ehqel36tCv/hgPk0/jztDsvCwO5+HIaZv68Ojbsq+B7xSuYTpQn5+EU9KNnCfoblHGcysqf5id3gCPmZ6BubcUXQvzX7aIQ6hSb0qAS7ebbkOz/L8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610490439; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=dFu4L4aglRkkrqNc5lcBxbZRnH2qe2Eh9lBiBMTg+Xw=; b=FrdV03BYtslLIMqPq/8vu1T+o/YKMrh2F37oXyq8qh2bF08xe1G76eUyU2HhGIDbxFTDuGP1iySaLr3Qp5VKxsyq99wwb79XcTgQWWiWm3G7ThaE/9nSrdNrYOVA0fTFoXLSGE6b6eRsreeA6q9VRtHCPs6VXHhjCEot+IfCsRY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70171+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1610490439633413.318516291563; Tue, 12 Jan 2021 14:27:19 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id X4swYY1788612xAzoMTgivxL; Tue, 12 Jan 2021 14:27:19 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.17355.1610490433518303311 for ; Tue, 12 Jan 2021 14:27:13 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 37CFE11D4; Tue, 12 Jan 2021 14:27:13 -0800 (PST) X-Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.28.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2F3983F719; Tue, 12 Jan 2021 14:27:13 -0800 (PST) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, awarkentin@vmware.com, samer.el-haj-mahmoud@arm.com, leif@nuviainc.com, ard.biesheuvel@arm.com, Jeremy Linton Subject: [edk2-devel] [RFC 2/3] rpi4/acpi/dsdt: break XHCI into its own SSDT Date: Tue, 12 Jan 2021 16:27:07 -0600 Message-Id: <20210112222708.1757044-3-jeremy.linton@arm.com> In-Reply-To: <20210112222708.1757044-1-jeremy.linton@arm.com> References: <20210112222708.1757044-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: KsrnScgy2HEVQJWv57OeYG9Jx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1610490439; bh=xpO5SxFzCkfrZ1ghPPAnRmgfggcAJk5rYug7VhTnl5g=; h=Cc:Date:From:Reply-To:Subject:To; b=ems2IHb05OLBmxOOMj14wcjXmZnqp3P2b0MfIqvf065PKqHZ0lQJHg89rLhR3I7a7LH UNe/tLKX0ntrtAEoC4VVdVtElSnAudP4OPlvxqxaD/yilYnSnVmNCEJ6LvnzXc6okhxdv p+/ARLpNo40XO47Xu/IUFxlp/Kpiqpkdg4k= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Lets prepare to switch between XHCI and PCI by moving the XHCI definition into its own SSDT. That way we can select it based on the menu settings. Signed-off-by: Jeremy Linton --- Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 + Platform/RaspberryPi/AcpiTables/Dsdt.asl | 4 +-- Platform/RaspberryPi/AcpiTables/Xhci.asl | 33 ++++++++++++++----= ---- Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 5 ++++ 4 files changed, 28 insertions(+), 15 deletions(-) diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Rasp= berryPi/AcpiTables/AcpiTables.inf index 2867c83b71..17dee581a0 100644 --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf @@ -36,6 +36,7 @@ Pptt.aslc Pcct.aslc SsdtThermal.asl + Xhci.asl =20 [Packages] ArmPkg/ArmPkg.dec diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/RaspberryP= i/AcpiTables/Dsdt.asl index ae3bd129d6..5a665d7dd1 100644 --- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl +++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl @@ -63,9 +63,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 5, "RPIFDN", "RPI", = 2) Scope (\_SB_) { include ("Pep.asl") -#if (RPI_MODEL =3D=3D 4) - include ("Xhci.asl") -#endif + Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities CreateDWordField (Arg3, 0x00, STS0) CreateDWordField (Arg3, 0x04, CAP0) diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl b/Platform/RaspberryP= i/AcpiTables/Xhci.asl index bc3fea60f9..6d18adf590 100644 --- a/Platform/RaspberryPi/AcpiTables/Xhci.asl +++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl @@ -9,6 +9,8 @@ =20 #include =20 +#include "AcpiTables.h" + /* * The following can be used to remove parenthesis from * defined macros that the compiler complains about. @@ -24,12 +26,17 @@ */ #define XHCI_REG_LENGTH 0x1000 =20 -Device (SCB0) { - Name (_HID, "ACPI0004") - Name (_UID, 0x0) - Name (_CCA, 0x0) +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2) +{ + Scope (\_SB_) + { + + Device (SCB0) { + Name (_HID, "ACPI0004") + Name (_UID, 0x0) + Name (_CCA, 0x0) =20 - Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings + Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings /* * Container devices with _DMA must have _CRS, meaning SCB0 * to provide all resources that XHC0 consumes (except @@ -57,9 +64,9 @@ Device (SCB0) { Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) Return (RBUF) - } + } =20 - Name (_DMA, ResourceTemplate() { + Name (_DMA, ResourceTemplate() { /* * XHC0 is limited to DMA to first 3GB. Note this * only applies to PCIe, not GENET or other devices @@ -79,10 +86,10 @@ Device (SCB0) { , , ) - }) + }) =20 - Device (XHC0) - { + Device (XHC0) + { Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x0) // _UID: Unique ID Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute @@ -131,5 +138,7 @@ Device (SCB0) { Debug =3D "xHCI enable" Store (0x6, CMND) } - } -} + } // end XHC0 + } //end SCB0 + } //end scope sb +} //end definition block diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c index 7a3b8e9068..f13abd67c0 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c @@ -755,6 +755,11 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D { SsdtNameOpReplace }, { + SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'), + PcdToken(PcdXhci), + NULL + }, + { SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0), 0, NULL --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70171): https://edk2.groups.io/g/devel/message/70171 Mute This Topic: https://groups.io/mt/79637123/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 23:41:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+70173+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70173+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1610490435; cv=none; d=zohomail.com; s=zohoarc; b=b9CZ5numdg5ITsnCf1Mgo2/Rp5308dwDORa7M8sUs7HhWmO/2fO67rGRI+8oBg5P8Bn2WdBWSzkJYdR0RnjlrAsAFAT1vTQykRPYPWoTjXfTyIfnjbye8Ysf1I4ThMC3HpKaSWv8tYPhwnNP69QyETTStLMaCvoTxQnxoDnAVtQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610490435; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=OfCBbwguilGPjMW8kI3F0LTKMn1WxI3u699589Tm7OY=; b=jOAehK3Ze6lEohAb74OCv7B95I1QZg0yDbyPYNrw7HUxTMJt25wp1TC6joMhggk7xCRb194QNuqwfs93VTp4MeKdmlZOyYbkZM0gcSBcutLe53PA3djQjDPgL0Zh/l3wNlQvDUzNiZR2OQGYj8bVtACyCLwGBXBfyua8RjVWK3g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+70173+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1610490435272293.9524711077572; Tue, 12 Jan 2021 14:27:15 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id xwF7YY1788612x2m2ZRuOJuD; Tue, 12 Jan 2021 14:27:14 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.17558.1610490434201211830 for ; Tue, 12 Jan 2021 14:27:14 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E772C11FB; Tue, 12 Jan 2021 14:27:13 -0800 (PST) X-Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.28.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DEA083F719; Tue, 12 Jan 2021 14:27:13 -0800 (PST) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, awarkentin@vmware.com, samer.el-haj-mahmoud@arm.com, leif@nuviainc.com, ard.biesheuvel@arm.com, Jeremy Linton Subject: [edk2-devel] [RFC 3/3] rpi4/acpi: Add PCIe SSDT Date: Tue, 12 Jan 2021 16:27:08 -0600 Message-Id: <20210112222708.1757044-4-jeremy.linton@arm.com> In-Reply-To: <20210112222708.1757044-1-jeremy.linton@arm.com> References: <20210112222708.1757044-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: Yge5QZPPYydYCyDo7fIuXmPmx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1610490434; bh=yE3Q22Uu3sY9rPNlZwnOLCrGpE/+YNX/A8LGT5TJkkY=; h=Cc:Date:From:Reply-To:Subject:To; b=V1nh/d+oTMcbxffKmCpuDYoNBucee0aA+UZoWHy3LLEgLwPRk9mwdko2s0inZIoK71b 113b33vTe/DciT+85FlgAGPwPotscobmaEihHUBxGtCU5WwQBWVo1YG+tKoaoI9P2bcQG 2rdzw4MMH7n0/x512KFzKHFq84MgFJSVcXM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Since we plan on toggling between XHCI and PCI the PCI root needs to be in its own SSDT. This is all thats needed of UEFI. The SMC conduit is provided directly to the running OS. When the OS detects this PCIe port, on a machine without a MADT it attempts to connect to the SMC conduit. This definition doesn't have any power mgmt, and only provides a description of the root port. Signed-off-by: Jeremy Linton --- Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 + Platform/RaspberryPi/AcpiTables/Pci.asl | 239 +++++++++++++++++= ++++ Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 5 + 3 files changed, 247 insertions(+) create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Rasp= berryPi/AcpiTables/AcpiTables.inf index 17dee581a0..d261861e59 100644 --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf @@ -37,6 +37,7 @@ Pcct.aslc SsdtThermal.asl Xhci.asl + Pci.asl =20 [Packages] ArmPkg/ArmPkg.dec @@ -57,6 +58,8 @@ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicDistributorBase gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi= /AcpiTables/Pci.asl new file mode 100644 index 0000000000..71b90d6958 --- /dev/null +++ b/Platform/RaspberryPi/AcpiTables/Pci.asl @@ -0,0 +1,239 @@ +/** @file + * + * Copyright (c) 2019 Linaro, Limited. All rights reserved. + * Copyright (c) 2021 Arm + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#include "AcpiTables.h" + +/* + * The following can be used to remove parenthesis from + * defined macros that the compiler complains about. + */ +#define ISOLATE_ARGS(...) __VA_ARGS__ +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x + +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_W= INDOW) // 600000000 +#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMI= O_LEN) // 03ffffff +#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM= _WIN) // f8000000 + +/* + * According to UEFI boot log for the VLI device on Pi 4. + */ +#define XHCI_REG_LENGTH 0x1000 + +// copy paste job from juno +#define LNK_DEVICE(Unique_Id, Link_Name, irq) = \ + Device(Link_Name) { = \ + Name(_HID, EISAID("PNP0C0F")) = \ + Name(_UID, Unique_Id) = \ + Name(_PRS, ResourceTemplate() { = \ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq = } \ + }) = \ + Method (_CRS, 0) { Return (_PRS) } = \ + Method (_SRS, 1) { } = \ + Method (_DIS) { } = \ + } + +#define PRT_ENTRY(Address, Pin, Link) = \ + Package (4) { = \ + Address, /* uses the same format as _ADR */ = \ + Pin, /* The PCI pin number of the device (0-INTA, 1-INT= B, 2-INTC, 3-INTD). */ \ + Link, /* Interrupt allocated via Link device. */ = \ + Zero /* global system interrupt number (no used) */ = \ + } +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) + +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2) +{ + Scope (\_SB_) + { + + Device (SCB0) { + Name (_HID, "ACPI0004") + Name (_UID, 0x0) + Name (_CCA, 0x0) + + Method (_CRS, 0, Serialized) { + // Container devices with _DMA must have _CRS,=20 + // meaning SCB0 to provide all resources that + // PCI0 consumes (except interrupts). + Name (RBUF, ResourceTemplate () { + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX + 0x0, + 0x1, // LEN + , + , + MMIO + ) + }) + CreateQwordField (RBUF, MMIO._MAX, MMBE) + CreateQwordField (RBUF, MMIO._LEN, MMLE) + Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) + Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) + Return (RBUF) + } + + Name (_DMA, ResourceTemplate() { + // PCIe is limited to DMA to first 3GB. Note this + // only applies to PCIe, not GENET or other devices + QWordMemory (ResourceConsumer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + // + // PCI Root Complex + // + LNK_DEVICE(1, LNKA, 175) + LNK_DEVICE(2, LNKB, 176) //todo check int b,c,d values + LNK_DEVICE(3, LNKC, 177) + LNK_DEVICE(4, LNKD, 178) + + Device(PCI0) + { + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name(_SEG, Zero) // PCI Segment Group number + Name(_BBN, Zero) // PCI Base Bus Number + Name(_CCA, 0) // mark the PCI noncoherent + + // Root Complex 0 + Device (RP0) { + Name(_ADR, 0xF0000000) // Dev 0, Func 0 + } + + Name (_DMA, ResourceTemplate() { + QWordMemory (ResourceConsumer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + // PCI Routing Table + Name(_PRT, Package() { + ROOT_PRT_ENTRY(0, LNKA), // INTA + ROOT_PRT_ENTRY(1, LNKB), // INTB + ROOT_PRT_ENTRY(2, LNKC), // INTC + ROOT_PRT_ENTRY(3, LNKD), // INTD + }) + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + QWordMemory ( // 32-bit BAR Windows in 64-bit addr + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + NonCacheable, ReadWrite, //cacheable? is that right? + 0x00000000, // Granularity + 0, // SANITIZED_PCIE_PCI_MMIO_B= EGIN + 1, // SANITIZED_PCIE_MMIO_LEN += SANITIZED_PCIE_PCI_MMIO_BEGIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_B= EGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW + 2 // SANITIZED_PCIE_MMIO_LEN += 1 + ,,,MMI1,,TypeTranslation + ) + }) // Name(RBUF) + + // Work around ASL's inability to add in a resource definition + // or for that matter compute the min,max,len properly + CreateQwordField (RBUF, MMI1._MIN, MMIB) + CreateQwordField (RBUF, MMI1._MAX, MMIE) + CreateQwordField (RBUF, MMI1._TRA, MMIT) + CreateQwordField (RBUF, MMI1._LEN, MMIL) + Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB) + Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMI= E) + Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT) + Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL) + + Return (RBUF) + } // Method(_CRS) + // + // OS Control Handoff + // + Name(SUPP, Zero) // PCI _OSC Support Field value + Name(CTRL, Zero) // PCI _OSC Control Field value + + // See [1] 6.2.10, [2] 4.5 + Method(_OSC,4) { + // Note, This code is very similar to the code in the PCIe firmw= are + // specification which can be used as a reference + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // Mask out Native HotPlug + And(CTRL,0x1E,CTRL) + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + + If(LNotEqual(Arg1,One)) { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Return(Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + } // PCI0 + } //end SCB0 + } //end scope sb +} //end definition block diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c index f13abd67c0..87ad0fc816 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c @@ -760,6 +760,11 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D { NULL }, { + SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'), + PcdToken(PcdPci), + NULL + }, + { SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0), 0, NULL --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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