From nobody Thu Apr 25 09:01:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+69645+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+69645+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1609801136; cv=none; d=zohomail.com; s=zohoarc; b=Meg/nhRbo3uC22fmqn6bzyUjTJKIg/YcWTCLC/YukZ1JGdP4y2ooNc46n+lKL7YLRJn+qVf0caQ20JZ6nARMXsdifPNE3QTyKyXaykOB5ACT+FHncdDjXpOfV9Tihudh03VvGB60lCXAigX8rIGvR+gv6C1/jRD2V5D01XO3LNA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609801136; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=mXl0+QV6Gi+3QkO9Kc1YgBPwgxEYUpOBE6Cv5D3DWzY=; b=kOxD1wcfpqeje6/7f8U/zRNItrPxeM4Uz7gz0ICSpoBMzE99R4RvUbdPoACzFpn+q9KeQZ3CG4FEF9lXD/eeov1PAKbmZUfdf5wa2I9O6R+X6ls4O7vdr5bWEXqYnZqvPIcuJivG4dTJFo20sn89yRDZn5syZL7fBDTTf5uV+RU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+69645+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1609801136866346.4178702360871; Mon, 4 Jan 2021 14:58:56 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id I7IwYY1788612xfp1RXBkqF4; Mon, 04 Jan 2021 14:58:56 -0800 X-Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) by mx.groups.io with SMTP id smtpd.web10.66.1609801131067894705 for ; Mon, 04 Jan 2021 14:58:51 -0800 X-Received: by mail-pj1-f46.google.com with SMTP id m5so525490pjv.5 for ; Mon, 04 Jan 2021 14:58:51 -0800 (PST) X-Gm-Message-State: W0zPOBwLXA2IeXa3m5nKQiPqx1787277AA= X-Google-Smtp-Source: ABdhPJyHWVAW69se7VJPReV8qtkiG0DwbipeXO8xC0vHnR6LolEdO+OWkdmbv4cylm6y6DKuXf1B9g== X-Received: by 2002:a17:90a:430f:: with SMTP id q15mr1090406pjg.218.1609801130122; Mon, 04 Jan 2021 14:58:50 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id x143sm64185289pgx.66.2021.01.04.14.58.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:58:49 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Leif Lindholm , Ard Biesheuvel , "nd @ arm . com . Sami Mujawar" , Liming Gao , Michael D Kinney , Zhiguang Liu Subject: [edk2-devel] [PATCH v5 07/23] ArmPkg: Update ArmLibPrivate.h with cache register definitions Date: Mon, 4 Jan 2021 15:58:14 -0700 Message-Id: <20210104225830.12606-8-rebecca@nuviainc.com> In-Reply-To: <20210104225830.12606-1-rebecca@nuviainc.com> References: <20210104225830.12606-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1609801136; bh=+1c2oNkAdhxcSWhOJ1jheIJ6jW9OD1zXoQu5yeimmYc=; h=Cc:Date:From:Reply-To:Subject:To; b=ZPiKlYuggLcNKUzuIjINhOG+FRrwP8LiQEJ9FcP9Pikq4bXVShMn2cHn2TvyubIT4Aw QvAVhIhQ+K/Lzms4nqPSCq0phMZf5rwKi43K4wHj7DRazFa1ai9rYPd/36Hghjh4qzuBB +ghFJDTJPOcsjlpVGVH+kEr99CDCt4/bMjw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Update the cache definitions in ArmLibPrivate.h based on current ARMv8 documentation. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 97 ++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/= ArmLibPrivate.h index 8959bdd9d73c..5d0224080f3f 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -1,5 +1,7 @@ /** @file + ArmLibPrivate.h =20 + Copyright (c) 2020, NUVIA Inc. All rights reserved.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -50,6 +52,101 @@ #define CACHE_ARCHITECTURE_UNIFIED (0UL) #define CACHE_ARCHITECTURE_SEPARATE (1UL) =20 + +/// Defines the structure of the CSSELR (Cache Size Selection) register +typedef union { + struct { + UINT32 InD :1; ///< Instruction not Data bit + UINT32 Level :3; ///< Cache level (zero based) + UINT32 TnD :1; ///< Allocation not Data bit + UINT32 Reserved :27; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSELR_DATA; + +/// The cache type values for the InD field of the CSSELR register +typedef enum +{ + /// Select the data or unified cache + CsselrCacheTypeDataOrUnified =3D 0, + /// Select the instruction cache + CsselrCacheTypeInstruction, + CsselrCacheTypeMax +} CSSELR_CACHE_TYPE; + +/// Defines the structure of the CCSIDR (Current Cache Size ID) register +typedef union { + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in ca= che) - 4) + UINT64 Associativity :10; ///< Associativity - 1 + UINT64 NumSets :15; ///< Number of sets in the cache -1 + UINT64 Unknown :4; ///< Reserved, UNKNOWN + UINT64 Reserved :32; ///< Reserved, RES0 + } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX= is not supported. + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in ca= che) - 4) + UINT64 Associativity :21; ///< Associativity - 1 + UINT64 Reserved1 :8; ///< Reserved, RES0 + UINT64 NumSets :24; ///< Number of sets in the cache -1 + UINT64 Reserved2 :8; ///< Reserved, RES0 + } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX = is supported. + struct { + UINT64 LineSize : 3; + UINT64 Associativity : 21; + UINT64 Reserved : 9; + UINT64 Unallocated : 32; + } BitsCcidxAA32; + UINT64 Data; ///< The entire 64-bit value +} CCSIDR_DATA; + +/// Defines the structure of the AARCH32 CCSIDR2 register. +typedef union { + struct { + UINT32 NumSets :24; ///< Number of sets in the cache - 1 + UINT32 Reserved :8; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSIDR2_DATA; + +/** Defines the structure of the CLIDR (Cache Level ID) register. + * + * The lower 32 bits are the same for both AARCH32 and AARCH64 + * so we can use the same structure for both. +**/ +typedef union { + struct { + UINT32 Ctype1 : 3; ///< Level 1 cache type + UINT32 Ctype2 : 3; ///< Level 2 cache type + UINT32 Ctype3 : 3; ///< Level 3 cache type + UINT32 Ctype4 : 3; ///< Level 4 cache type + UINT32 Ctype5 : 3; ///< Level 5 cache type + UINT32 Ctype6 : 3; ///< Level 6 cache type + UINT32 Ctype7 : 3; ///< Level 7 cache type + UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable + UINT32 LoC : 3; ///< Level of Coherency + UINT32 LoUU : 3; ///< Level of Unification Uniprocessor + UINT32 Icb : 3; ///< Inner Cache Boundary + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CLIDR_DATA; + +/// The cache types reported in the CLIDR register. +typedef enum { + /// No cache is present + ClidrCacheTypeNone =3D 0, + /// There is only an instruction cache + ClidrCacheTypeInstructionOnly, + /// There is only a data cache + ClidrCacheTypeDataOnly, + /// There are separate data and instruction caches + ClidrCacheTypeSeparate, + /// There is a unified cache + ClidrCacheTypeUnified, + ClidrCacheTypeMax +} CLIDR_CACHE_TYPE; + +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * level)) & 0b111) + VOID CPSRMaskInsert ( IN UINT32 Mask, --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#69645): https://edk2.groups.io/g/devel/message/69645 Mute This Topic: https://groups.io/mt/79438409/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-