From nobody Thu Apr 25 08:48:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+69641+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+69641+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1609801124; cv=none; d=zohomail.com; s=zohoarc; b=J1wS+ZX1LeC0PdHpW+gTO4M/4J/89zHpHfrWmaXvtagv1PNIXkyP45kYH0khQb7sggjT3gRhy0oAgDISAY5T/KrMvpwjcMy3c6+AMnz6QqaVfxwnqClqQzkefNbGbX8GsypGj+SwJfZKzUGY+B4ZtO5ckrJ0aKS0Atb/0dH3f9M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609801124; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=um7Eiueh1EuUlQVaVAcsdU9JQwYOKnfphjSpCzDyYRE=; b=lBQxH2MBP3q3xFgxQbPZTBSMan2sKFquBK6rCN7LkTB7t6ih4ReyNhCFsiWtpPpd+EvkZsRx4JvoC14Vg9Hld9wvrMnNPaDrGyB5XpzFXVfntKiTza71WRDzwSfAatH3ypIAVwZHtvEG3H161t875oZKlWBwEqpT7GQ99jMzM8A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+69641+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 160980112483553.465122207041986; Mon, 4 Jan 2021 14:58:44 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id KNzaYY1788612x2VBfQ0ItLd; Mon, 04 Jan 2021 14:58:44 -0800 X-Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) by mx.groups.io with SMTP id smtpd.web10.65.1609801123970806012 for ; Mon, 04 Jan 2021 14:58:44 -0800 X-Received: by mail-pj1-f53.google.com with SMTP id l23so538560pjg.1 for ; Mon, 04 Jan 2021 14:58:43 -0800 (PST) X-Gm-Message-State: Mb52bfigh6N7ukxzb3HQswx2x1787277AA= X-Google-Smtp-Source: ABdhPJyBf1/gE+r6mv7M0r+ltSeUB4qJvc9JHVeONYXjs3N8DgYOUFqULk/94eGJxyQh3A1Sbavuzg== X-Received: by 2002:a17:90b:4a10:: with SMTP id kk16mr1103792pjb.30.1609801123180; Mon, 04 Jan 2021 14:58:43 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id x143sm64185289pgx.66.2021.01.04.14.58.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:58:42 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Leif Lindholm , Ard Biesheuvel , "nd @ arm . com . Sami Mujawar" , Liming Gao , Michael D Kinney , Zhiguang Liu Subject: [edk2-devel] [PATCH v5 03/23] ArmPkg: Add register encoding definition for MMFR2 Date: Mon, 4 Jan 2021 15:58:10 -0700 Message-Id: <20210104225830.12606-4-rebecca@nuviainc.com> In-Reply-To: <20210104225830.12606-1-rebecca@nuviainc.com> References: <20210104225830.12606-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1609801124; bh=OaNTj3gYhXZgM4WdMFVtmExqjjpqErNCrdLh/S+SYd0=; h=Cc:Date:From:Reply-To:Subject:To; b=xOTySF1yCJEU1n/aMFgF1wxT87bMzk3D9V6WXwicI4aKkrQONW3gF6xf2NLx8987nlH pC5WvB6W1kttqlJOpdS/BT1CP6Ui7hYS6ixJSNcUmxyBYXf/QwP44hGKaexOTt14aJlhW 7MvPrLYWx7FS8mSXEJGChjw5/7m9g/63dAM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add register encoding definition for Memory Model Feature Register 2. We need to define it here because we build for ARMv8.0, which doesn't have it. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/Chipset/AArch64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArc= h64.h index 0ade5cce91c3..7c2b592f92ee 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -112,6 +112,10 @@ #define ARM_VECTOR_LOW_A32_FIQ 0x700 #define ARM_VECTOR_LOW_A32_SERR 0x780 =20 +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we +// build for ARMv8.0, we need to define the register here. +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + #define VECTOR_BASE(tbl) \ .section .text.##tbl##,"ax"; \ .align 11; \ --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#69641): https://edk2.groups.io/g/devel/message/69641 Mute This Topic: https://groups.io/mt/79438405/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-