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[82.27.183.148]) by smtp.gmail.com with ESMTPSA id b12sm18558569wmj.2.2020.12.18.06.16.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Dec 2020 06:16:19 -0800 (PST) From: "Leif Lindholm" To: devel@edk2.groups.io Cc: Ard Biesheuvel Subject: [edk2-devel] [PATCH 2/9] ArmPkg: use ID register helper for ArmGicArch(Sec)Lib Date: Fri, 18 Dec 2020 14:16:10 +0000 Message-Id: <20201218141617.26947-3-leif@nuviainc.com> In-Reply-To: <20201218141617.26947-1-leif@nuviainc.com> References: <20201218141617.26947-1-leif@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,leif@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1608301004; bh=CR+Yht+taKpQaBlY6A73ckAeK6zGPOl+nGT00q1tnTk=; h=Cc:Date:From:Reply-To:Subject:To; b=fNQbUXmKkqV1iXG9Fl/zyL6NFg93Y03fM8kedxSPjCRiMAfhsZ7G3+voiollsKZy49t fUn5gaw3armxqind8ixrQph9azyCkLvtaT2fea8X/AlSuMP5Ab1P7F9s5G8fbdPEsyLhV hTHSbS2aExDKomxYZtrJRE9WulQwijVb77I= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Use ArmHasGicSystemRegisters () instead of direct ID register tests. Cc: Ard Biesheuvel Signed-off-by: Leif Lindholm --- ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c | 2 +- ArmPkg/Library/ArmGicArchLib/Arm/ArmGicArchLib.c | 2 +- ArmPkg/Library/ArmGicArchSecLib/AArch64/ArmGicArchLib.c | 2 +- ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c b/ArmPkg/= Library/ArmGicArchLib/AArch64/ArmGicArchLib.c index 4086a294dafd..6fd69658e0e5 100644 --- a/ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c +++ b/ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c @@ -25,7 +25,7 @@ ArmGicArchLibInitialize ( // feature is implemented on the CPU. This is also convenient as our GIC= v3 // driver requires SRE. If only Memory mapped access is available we try= to // drive the GIC as a v2. - if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) { + if (ArmHasGicSystemRegisters ()) { // Make sure System Register access is enabled (SRE). This depends on = the // higher privilege level giving us permission, otherwise we will eith= er // cause an exception here, or the write doesn't stick in which case w= e need diff --git a/ArmPkg/Library/ArmGicArchLib/Arm/ArmGicArchLib.c b/ArmPkg/Libr= ary/ArmGicArchLib/Arm/ArmGicArchLib.c index 222d8059825d..7e7e46e69faa 100644 --- a/ArmPkg/Library/ArmGicArchLib/Arm/ArmGicArchLib.c +++ b/ArmPkg/Library/ArmGicArchLib/Arm/ArmGicArchLib.c @@ -25,7 +25,7 @@ ArmGicArchLibInitialize ( // feature is implemented on the CPU. This is also convenient as our GIC= v3 // driver requires SRE. If only Memory mapped access is available we try= to // drive the GIC as a v2. - if (ArmReadIdPfr1 () & ARM_PFR1_GIC) { + if (ArmHasGicSystemRegisters ()) { // Make sure System Register access is enabled (SRE). This depends on = the // higher privilege level giving us permission, otherwise we will eith= er // cause an exception here, or the write doesn't stick in which case w= e need diff --git a/ArmPkg/Library/ArmGicArchSecLib/AArch64/ArmGicArchLib.c b/ArmP= kg/Library/ArmGicArchSecLib/AArch64/ArmGicArchLib.c index 4f2479e70c74..ca81951b2b2b 100644 --- a/ArmPkg/Library/ArmGicArchSecLib/AArch64/ArmGicArchLib.c +++ b/ArmPkg/Library/ArmGicArchSecLib/AArch64/ArmGicArchLib.c @@ -23,7 +23,7 @@ ArmGicGetSupportedArchRevision ( // feature is implemented on the CPU. This is also convenient as our GIC= v3 // driver requires SRE. If only Memory mapped access is available we try= to // drive the GIC as a v2. - if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) { + if (ArmHasGicSystemRegisters ()) { // Make sure System Register access is enabled (SRE). This depends on = the // higher privilege level giving us permission, otherwise we will eith= er // cause an exception here, or the write doesn't stick in which case w= e need diff --git a/ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c b/ArmPkg/L= ibrary/ArmGicArchSecLib/Arm/ArmGicArchLib.c index 8e1baeee201a..2373ca409a17 100644 --- a/ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c +++ b/ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c @@ -23,7 +23,7 @@ ArmGicGetSupportedArchRevision ( // feature is implemented on the CPU. This is also convenient as our GIC= v3 // driver requires SRE. If only Memory mapped access is available we try= to // drive the GIC as a v2. - if (ArmReadIdPfr1 () & ARM_PFR1_GIC) { + if (ArmHasGicSystemRegisters ()) { // Make sure System Register access is enabled (SRE). This depends on = the // higher privilege level giving us permission, otherwise we will eith= er // cause an exception here, or the write doesn't stick in which case w= e need --=20 2.20.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#69198): https://edk2.groups.io/g/devel/message/69198 Mute This Topic: https://groups.io/mt/79061634/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-