From nobody Tue Feb 10 11:14:37 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+68394+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68394+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1607363694; cv=none; d=zohomail.com; s=zohoarc; b=Adkax7IhFUjdTTZ6j4hhLIzm4ATyPA1WJrVoU3LYo96ZmvUaz4we+ycK5F1lJ0Pn1zXYdRvlginzs6nKrNA4CTKZff5kVgslQNXHkCVLLO3/XwNAVGqVPS+4EGODwjgOutz/DwKiz4jyvnGZbrVTsjdodoHnx4Q/IxwK4kXKP5E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607363694; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=PeRd6utWQKUD8aXJdim4uMcDGhYq/vycILi9DUJCzCM=; b=CU+fthK6MwTrYi6dq1b+dlmCcvfcx8HPpNtbityBYLSxeSe68Yrkl1dds4fL+Tx07fr/NrQO/9vTWAzRssx9xz+cCwElNjLr3lqsi82mY/rG8CfcxeB6W4LASilGllfjPJ7fB2zOCbtmVHKgRfCm9UJnRCk8kANHYJLyHOIxq/I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68394+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1607363694675366.4337203316893; Mon, 7 Dec 2020 09:54:54 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id LxWeYY1788612xxdVlULXdbN; Mon, 07 Dec 2020 09:54:54 -0800 X-Received: from mail-pj1-f66.google.com (mail-pj1-f66.google.com [209.85.216.66]) by mx.groups.io with SMTP id smtpd.web11.156.1607363690831130989 for ; Mon, 07 Dec 2020 09:54:50 -0800 X-Received: by mail-pj1-f66.google.com with SMTP id e5so48333pjt.0 for ; Mon, 07 Dec 2020 09:54:50 -0800 (PST) X-Gm-Message-State: S6v3SebjDtravyeZYHQDtrxlx1787277AA= X-Google-Smtp-Source: ABdhPJwMlRmdAnnfPtgO8178E08nqrKjAcjPnVQxKOL0qqJLG2wylgdGd/3TaXg6rqKKfc6Y9VAHeA== X-Received: by 2002:a17:90a:1b29:: with SMTP id q38mr17355211pjq.223.1607363689988; Mon, 07 Dec 2020 09:54:49 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:49 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 08/10] ArmPkg: Update ArmLibPrivate.h with cache register definitions Date: Mon, 7 Dec 2020 10:54:25 -0700 Message-Id: <20201207175427.28712-9-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363694; bh=N4+NpYpQ4UuubDhnci+U7o24WGZaRDK5/OY51H2ubqo=; h=Cc:Date:From:Reply-To:Subject:To; b=ew71tEcUqx4wuVUddkH+6NadoJfo8+d8b8DZ3BevAahEZ0oyFNn9fr0mA3jz8abcD/L iBeKamwNHJ9rrhpq4TjSa/bJVey9UotGtzrvu7Sr5tvk85PZKki2kw+DQwYhkiOHqBWm8 9rW8VFt4KIDtFg7wSF+LbGl6jXTh2C0T6ms= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Update the cache definitions in ArmLibPrivate.h based on current ARMv8 documentation. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 91 ++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/= ArmLibPrivate.h index 5eecbc0e1c43..fb1e2cc6b2ac 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -1,5 +1,7 @@ /** @file + ArmLibPrivate.h =20 + Copyright (c) 2020, NUVIA Inc. All rights reserved.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -50,6 +52,95 @@ #define CACHE_ARCHITECTURE_UNIFIED (0UL) #define CACHE_ARCHITECTURE_SEPARATE (1UL) =20 + +/// Defines the structure of the CSSELR (Cache Size Selection) register +typedef union { + struct { + UINT32 InD :1; ///< Instruction not Data bit + UINT32 Level :3; ///< Cache level (zero based) + UINT32 TnD :1; ///< Allocation not Data bit + UINT32 Reserved :27; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSELR_DATA; + +/// The cache type values for the InD field of the CSSELR register +typedef enum +{ + /// Select the data or unified cache + CsselrCacheTypeDataOrUnified =3D 0, + /// Select the instruction cache + CsselrCacheTypeInstruction, + CsselrCacheTypeMax +} CSSELR_CACHE_TYPE; + +/// Defines the structure of the CCSIDR (Current Cache Size ID) register +typedef union { + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in ca= che) - 4) + UINT64 Associativity :10; ///< Associativity - 1 + UINT64 NumSets :15; ///< Number of sets in the cache -1 + UINT64 Unknown :4; ///< Reserved, UNKNOWN + UINT64 Reserved :32; ///< Reserved, RES0 + } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX= is not supported. + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in ca= che) - 4) + UINT64 Associativity :21; ///< Associativity - 1 + UINT64 Reserved1 :8; ///< Reserved, RES0 + UINT64 NumSets :24; ///< Number of sets in the cache -1 + UINT64 Reserved2 :8; ///< Reserved, RES0 + } BitsCcidx; ///< Bitfield definition of the register when FEAT_IDX is s= upported. + UINT64 Data; ///< The entire 64-bit value +} CCSIDR_DATA; + +/// Defines the structure of the AARCH32 CCSIDR2 register. +typedef union { + struct { + UINT32 NumSets :24; ///< Number of sets in the cache - 1 + UINT32 Reserved :8; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSIDR2_DATA; + +/** Defines the structure of the CLIDR (Cache Level ID) register. + * + * The lower 32 bits are the same for both AARCH32 and AARCH64 + * so we can use the same structure for both. +**/ +typedef union { + struct { + UINT32 Ctype1 : 3; ///< Level 1 cache type + UINT32 Ctype2 : 3; ///< Level 2 cache type + UINT32 Ctype3 : 3; ///< Level 3 cache type + UINT32 Ctype4 : 3; ///< Level 4 cache type + UINT32 Ctype5 : 3; ///< Level 5 cache type + UINT32 Ctype6 : 3; ///< Level 6 cache type + UINT32 Ctype7 : 3; ///< Level 7 cache type + UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable + UINT32 LoC : 3; ///< Level of Coherency + UINT32 LoUU : 3; ///< Level of Unification Uniprocessor + UINT32 Icb : 3; ///< Inner Cache Boundary + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CLIDR_DATA; + +/// The cache types reported in the CLIDR register. +typedef enum { + /// No cache is present + ClidrCacheTypeNone =3D 0, + /// There is only an instruction cache + ClidrCacheTypeInstructionOnly, + /// There is only a data cache + ClidrCacheTypeDataOnly, + /// There are separate data and instruction caches + ClidrCacheTypeSeparate, + /// There is a unified cache + ClidrCacheTypeUnified, + ClidrCacheTypeMax +} CLIDR_CACHE_TYPE; + +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * level)) & 0b111) + VOID CPSRMaskInsert ( IN UINT32 Mask, --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#68394): https://edk2.groups.io/g/devel/message/68394 Mute This Topic: https://groups.io/mt/78784071/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-