From nobody Wed Feb 11 00:59:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+68389+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68389+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1607363692; cv=none; d=zohomail.com; s=zohoarc; b=FLT7zhLZko/ZGgMJEo5vc9jRgVOU15D+7tElDyOH/o2R2zHurdejAbP4pnETPUtvbau2Sjq8Q1Y9XIXDvONokHJtafGKT5pFS4gAT6uMo0EOREvwc0OmXiRFMYA3Eh8lrn/STF5w6lBjFR0q0dUfSFu283W+lLtUyUNILbEzt7I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607363692; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=pHiYPPAGBsZQp3OaE0+ClHWrFH9wt8ZyGpMTNHedHIM=; b=dhYKGRhKkzQ0bsz9vgDcFgDUfIzde2oOhcxCPquiziTGnlPKxYKy1KD+rJevzGkq0vvHaC9EDI0vzLks90R/Iip2BqytqmcdwcB7cgET906JQu6D0u2CdQgguiJ0rbRCm8AVynxB7MMm8TW3lKvoBu5OAYCedCkebf0PoLll8dA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68389+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1607363692806751.0502144429385; Mon, 7 Dec 2020 09:54:52 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id pTYqYY1788612x7dD4ArN08T; Mon, 07 Dec 2020 09:54:52 -0800 X-Received: from mail-pj1-f68.google.com (mail-pj1-f68.google.com [209.85.216.68]) by mx.groups.io with SMTP id smtpd.web11.152.1607363683875576735 for ; Mon, 07 Dec 2020 09:54:43 -0800 X-Received: by mail-pj1-f68.google.com with SMTP id p21so280350pjv.0 for ; Mon, 07 Dec 2020 09:54:43 -0800 (PST) X-Gm-Message-State: Ty07mtM1uzaEDJTX9oEW0OVpx1787277AA= X-Google-Smtp-Source: ABdhPJz8Cc9quc8a7bv+lfDY9hum4w3LCP6gbGyxbpg4D4iE5ktyrXn2iMobDgq6eN7CXB4Pg8fjMw== X-Received: by 2002:a17:90a:c484:: with SMTP id j4mr17705896pjt.69.1607363682895; Mon, 07 Dec 2020 09:54:42 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:42 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 03/10] ArmPkg: Add register encoding definition for MMFR2 Date: Mon, 7 Dec 2020 10:54:20 -0700 Message-Id: <20201207175427.28712-4-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363692; bh=gkoPfvuKl50ksax9I/FdY7MM/9E1QMnvFkMzIGT5zm8=; h=Cc:Date:From:Reply-To:Subject:To; b=e/708XIgfa64NAyvFvPsmoADVbryUsOgjDiWQGVEINakZeIllHOLS8I4PPQBQTO5i31 wPAUeL2SCMXgve5w6Kw9msCTIiW/OpAhT4a/ec+QeveXzBK1c4yZq8Js/3FKNghn2A38K aW2I2XFlh2p+yV22aCGFZgpdW0UQlXq7fOE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add register encoding definition for Memory Model Feature Register 2. We need to define it here because we build for ARMv8.0, which doesn't have it. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/Chipset/AArch64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArc= h64.h index 0ade5cce91c3..7c2b592f92ee 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -112,6 +112,10 @@ #define ARM_VECTOR_LOW_A32_FIQ 0x700 #define ARM_VECTOR_LOW_A32_SERR 0x780 =20 +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we +// build for ARMv8.0, we need to define the register here. +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + #define VECTOR_BASE(tbl) \ .section .text.##tbl##,"ax"; \ .align 11; \ --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#68389): https://edk2.groups.io/g/devel/message/68389 Mute This Topic: https://groups.io/mt/78784064/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-