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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:50 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 09/10] ArmPkg: Add definition of the maximum cache level in ARMv8-A Date: Mon, 7 Dec 2020 10:54:26 -0700 Message-Id: <20201207175427.28712-10-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363694; bh=axCShmMtQg0mP2IpeZf7GQVYDOr317ddLjNrGQyMT3U=; h=Cc:Date:From:Reply-To:Subject:To; b=EzEod7N5flC0UKUsqoelYNP4m3pUR2XDPAtcSGr1DFNtc9LYu59Pe+rB7NWH6TF9gH6 Lipw9KvHbjf4lTHvJRDT10tQtvblJMniDWFO5TExBi0UyxJ+/CpYvkQv3ZO/ULWsoe1zv eGb+g1qcA/FVCxj3Z2hKEYbDjfK1Ns2vOuY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The ARM Architecture Reference Manual for ARMv8-A defines up to seven levels of cache, L1 through L7. Define MAX_ARM_CACHE_LEVEL to be 7. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/Library/ArmLib.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index 87c3a6f1ecac..4e26991727cb 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -108,6 +108,10 @@ typedef enum { #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK) =20 +// The ARM Architecture Reference Manual for ARMv8-A defines up +// to 7 levels of cache, L1 through L7. +#define MAX_ARM_CACHE_LEVEL 7 + UINTN EFIAPI ArmDataCacheLineLength ( --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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