From nobody Tue Apr 30 20:51:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+68387+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68387+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1607363681; cv=none; d=zohomail.com; s=zohoarc; b=FUCVNJwf7xaurBh/2ZLiG/H3/HZZ8pDzPsHD3AUnj0ejf5CNlyqbkgRJDifTwjwo9NsdGlA8kGaKpjF8fmENdHkLv7ye4uhLiJU1v4FWPZyqWtMCIc2HmbE9US1pJJBv2Jp6o1H33RkUahFcN8l+q/r/efZCMGpWBLYl/wZ4kN4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607363681; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=FXugJ+qS8MSQG6k0dyXZEdRd0taCQfzbv9TlSrNYjm4=; b=g3UoAhR4Hzg/hFO0dFeItx9tlAMZSwivsmxNWuG8buZf4SMKkG0uxeqrqVqzny7F8tZcBKka+B2U2MukKcwsbXWFyl6/LWBuEe5Hoi6/Rw5QRHRSaAHZITsSL6/ZZPZXejtOoQyf4INJk/f9V8jDEvNrCtmZgFlzkGwf+ko0IDI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68387+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1607363681800840.2648684491055; Mon, 7 Dec 2020 09:54:41 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id CCqtYY1788612x2TuARkKtHH; Mon, 07 Dec 2020 09:54:41 -0800 X-Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by mx.groups.io with SMTP id smtpd.web09.151.1607363680895662375 for ; Mon, 07 Dec 2020 09:54:40 -0800 X-Received: by mail-pg1-f193.google.com with SMTP id n7so9543082pgg.2 for ; Mon, 07 Dec 2020 09:54:40 -0800 (PST) X-Gm-Message-State: bAAKSuarC8FrHvyXL61BUqDEx1787277AA= X-Google-Smtp-Source: ABdhPJwqQXQBPHFgVmv7k0lpds4XnSt0za4LpAtn0G0aXlCkY9AC6Pohn1HAF3fPE0D9kJyi9adMFg== X-Received: by 2002:a63:f348:: with SMTP id t8mr19391376pgj.425.1607363680180; Mon, 07 Dec 2020 09:54:40 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:39 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 01/10] ArmPkg: Add ARM SMC Architecture functions to ArmStdSmc.h Date: Mon, 7 Dec 2020 10:54:18 -0700 Message-Id: <20201207175427.28712-2-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363681; bh=DXorDHDu0s8J4MifijcWmH+hOSo2yhnqW62Yz+LxbV0=; h=Cc:Date:From:Reply-To:Subject:To; b=rbCprI7aeQhkThcDRU8pgaa/l875xQaP8QXzIeqGzyqk3T3HNpTsaifdY5J+XbOkmim Y1C9pyWQIUVrRyLjrTiRo/oujXWeXsmO9ccvvoufoH1g2IkpgpcjMIEyFTKXQvjKAtSnx YdfCRlpNUCjfme3qxxHkLP6I4y3hUs5B+G8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The ARM SMC Architecture functions were missing from ArmStdSmc.h. Add them, based on the SMC Calling Convention version 1.2 specification. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h b/ArmPkg/Include/I= ndustryStandard/ArmStdSmc.h index 3509eb680f18..13f2245f37f5 100644 --- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h +++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h @@ -1,5 +1,6 @@ /** @file * +* Copyright (c) 2020, NUVIA Inc. All rights reserved.
* Copyright (c) 2012-2017, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent @@ -52,6 +53,18 @@ #define ARM_SMC_MM_RET_DENIED -3 #define ARM_SMC_MM_RET_NO_MEMORY -4 =20 +// ARM Architecture Calls +#define SMCCC_VERSION 0x80000000 +#define SMCCC_ARCH_FEATURES 0x80000001 +#define SMCCC_ARCH_SOC_ID 0x80000002 +#define SMCCC_ARCH_WORKAROUND_1 0x80008000 +#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF + +#define SMC_ARCH_CALL_SUCCESS 0 +#define SMC_ARCH_CALL_NOT_SUPPORTED -1 +#define SMC_ARCH_CALL_NOT_REQUIRED -2 +#define SMC_ARCH_CALL_INVALID_PARAMETER -3 + /* * Power State Coordination Interface (PSCI) calls cover a subset of the * Standard Service Call range. --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#68387): https://edk2.groups.io/g/devel/message/68387 Mute This Topic: https://groups.io/mt/78784060/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 30 20:51:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+68388+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68388+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1607363691; cv=none; d=zohomail.com; s=zohoarc; b=SIaud8Hi8j8Ap10eeFVHriRW0Xn+9TQDSyFFDJk5smz3GWOt8KXE/CEq+VHVLucQRj/BGthCIBP3CEBU97482evK/Y8dpCYz5f6p5aMKFYGWEV+koHNuWuYr6X2JD8eKYEHJXM04NixrX7s+e8v5xfpK0cqp0sD8u5Cm4dfpkWA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607363691; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rS1gAUM5xd5SToce6FvDxpX3jXQSsjO5ZX8vngHkpig=; b=b1Y0YwAHRpUX/NdnLKG2orNeZQg28hmYBry/oBsy1IsZeQEC3oxkfMMmQ0O1uisT0pBKHueS0zySD0ckextsT5x0sLV3P017hpuL3aqnhSa/OP+Sr3s7onbbsyd4/2EGlnh2fXfPX0JruYlnbz0B1E11NutpHMYrayrEfc9xALM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68388+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1607363691696694.728800151885; Mon, 7 Dec 2020 09:54:51 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id vKXkYY1788612xkdQRVsWdWG; Mon, 07 Dec 2020 09:54:51 -0800 X-Received: from mail-pj1-f65.google.com (mail-pj1-f65.google.com [209.85.216.65]) by mx.groups.io with SMTP id smtpd.web09.152.1607363682473219598 for ; Mon, 07 Dec 2020 09:54:42 -0800 X-Received: by mail-pj1-f65.google.com with SMTP id hk16so31709pjb.4 for ; Mon, 07 Dec 2020 09:54:42 -0800 (PST) X-Gm-Message-State: wzpDogBwrvx0MqFmuHltT4I0x1787277AA= X-Google-Smtp-Source: ABdhPJxPtJan9mZE9JJnB81YGh9vJAyYkCB46zYtGjHYYGvlAPdse8Qb1IVsrqOJ6iSfQivvkMQnOA== X-Received: by 2002:a17:90a:8589:: with SMTP id m9mr17290399pjn.190.1607363681572; Mon, 07 Dec 2020 09:54:41 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:41 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [PATCH v4 02/10] MdePkg: Update IndustryStandard/SmBios.h with processor status data Date: Mon, 7 Dec 2020 10:54:19 -0700 Message-Id: <20201207175427.28712-3-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363691; bh=kMKXfMcD463GyeeJVkGwIeVN9Qz+FjdKcOgnLbv+nsQ=; h=Cc:Date:From:Reply-To:Subject:To; b=fKaqettkoSv0RI4cKumgKVt2XqgCIgc9qU6+aGSklDJ06YUaH0pfdXRtS7UNJFLTsr3 ofUy0BZP7nVNl/XEMmel7AKtDMHoj2nIm0elLl96JUJnzihnSKeLAR0Y5qM0pUkUKdkro c1s/rp+laKA+aY8huUuqBy6cXDgVb9OwL/Y= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add a bitfield that describes the structure of the byte in the Status field of the SMBIOS Type 4 Processor Information table. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Acked-by: Sami Mujawar Reviewed-by: Liming Gao --- MdePkg/Include/IndustryStandard/SmBios.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/Indu= stryStandard/SmBios.h index 3bc8732eef99..cc023b73692a 100644 --- a/MdePkg/Include/IndustryStandard/SmBios.h +++ b/MdePkg/Include/IndustryStandard/SmBios.h @@ -875,6 +875,19 @@ typedef struct { UINT16 ProcessorReserved2 :6; } PROCESSOR_CHARACTERISTIC_FLAGS; =20 +/// +/// Processor Information - Status +/// +typedef union { + struct { + UINT8 CpuStatus :3; ///< Indicates the status of the processor. + UINT8 Reserved1 :3; ///< Reserved for future use. Must be set to= zero. + UINT8 SocketPopulated :1; ///< Indicates if the processor socket is po= pulated or not. + UINT8 Reserved2 :1; ///< Reserved for future use. Must be set to= zero. + } Bits; + UINT8 Data; +} PROCESSOR_STATUS_DATA; + typedef struct { PROCESSOR_SIGNATURE Signature; PROCESSOR_FEATURE_FLAGS FeatureFlags; --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#68388): https://edk2.groups.io/g/devel/message/68388 Mute This Topic: https://groups.io/mt/78784062/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 30 20:51:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+68389+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68389+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1607363692; cv=none; d=zohomail.com; s=zohoarc; b=FLT7zhLZko/ZGgMJEo5vc9jRgVOU15D+7tElDyOH/o2R2zHurdejAbP4pnETPUtvbau2Sjq8Q1Y9XIXDvONokHJtafGKT5pFS4gAT6uMo0EOREvwc0OmXiRFMYA3Eh8lrn/STF5w6lBjFR0q0dUfSFu283W+lLtUyUNILbEzt7I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607363692; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=pHiYPPAGBsZQp3OaE0+ClHWrFH9wt8ZyGpMTNHedHIM=; b=dhYKGRhKkzQ0bsz9vgDcFgDUfIzde2oOhcxCPquiziTGnlPKxYKy1KD+rJevzGkq0vvHaC9EDI0vzLks90R/Iip2BqytqmcdwcB7cgET906JQu6D0u2CdQgguiJ0rbRCm8AVynxB7MMm8TW3lKvoBu5OAYCedCkebf0PoLll8dA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68389+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1607363692806751.0502144429385; Mon, 7 Dec 2020 09:54:52 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id pTYqYY1788612x7dD4ArN08T; Mon, 07 Dec 2020 09:54:52 -0800 X-Received: from mail-pj1-f68.google.com (mail-pj1-f68.google.com [209.85.216.68]) by mx.groups.io with SMTP id smtpd.web11.152.1607363683875576735 for ; Mon, 07 Dec 2020 09:54:43 -0800 X-Received: by mail-pj1-f68.google.com with SMTP id p21so280350pjv.0 for ; Mon, 07 Dec 2020 09:54:43 -0800 (PST) X-Gm-Message-State: Ty07mtM1uzaEDJTX9oEW0OVpx1787277AA= X-Google-Smtp-Source: ABdhPJz8Cc9quc8a7bv+lfDY9hum4w3LCP6gbGyxbpg4D4iE5ktyrXn2iMobDgq6eN7CXB4Pg8fjMw== X-Received: by 2002:a17:90a:c484:: with SMTP id j4mr17705896pjt.69.1607363682895; Mon, 07 Dec 2020 09:54:42 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:42 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 03/10] ArmPkg: Add register encoding definition for MMFR2 Date: Mon, 7 Dec 2020 10:54:20 -0700 Message-Id: <20201207175427.28712-4-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363692; bh=gkoPfvuKl50ksax9I/FdY7MM/9E1QMnvFkMzIGT5zm8=; h=Cc:Date:From:Reply-To:Subject:To; b=e/708XIgfa64NAyvFvPsmoADVbryUsOgjDiWQGVEINakZeIllHOLS8I4PPQBQTO5i31 wPAUeL2SCMXgve5w6Kw9msCTIiW/OpAhT4a/ec+QeveXzBK1c4yZq8Js/3FKNghn2A38K aW2I2XFlh2p+yV22aCGFZgpdW0UQlXq7fOE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add register encoding definition for Memory Model Feature Register 2. We need to define it here because we build for ARMv8.0, which doesn't have it. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/Chipset/AArch64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArc= h64.h index 0ade5cce91c3..7c2b592f92ee 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -112,6 +112,10 @@ #define ARM_VECTOR_LOW_A32_FIQ 0x700 #define ARM_VECTOR_LOW_A32_SERR 0x780 =20 +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we +// build for ARMv8.0, we need to define the register here. +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + #define VECTOR_BASE(tbl) \ .section .text.##tbl##,"ax"; \ .align 11; \ --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:43 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 04/10] ArmPkg: Add helper to read the Memory Model Features Register 2 Date: Mon, 7 Dec 2020 10:54:21 -0700 Message-Id: <20201207175427.28712-5-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363693; bh=UwOTLutFhkDfuvik3p5rmtyFk3cN2yk4zwQIoDC3vWQ=; h=Cc:Date:From:Reply-To:Subject:To; b=nnUkLhHQwAtMeFMouM1X6ZDQl8lCV7Vp+LC6M5qi7IihEhKa0vS3R/j65eFpIkHVBq/ OmDMH2TctAnWtj9GCn+IqWXUT5WvaUs5x3oXY1xP1ouEL6mb6S1VgIAmFvcGJRSYIzI0/ hzjHDxhegL64cDZQ6mOihmWUiTU8REaKOWg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add helper function to read the MMFR2 register. We will need this to determine CCIDX support. Signed-off-by: Rebecca Cran --- ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h | 6 ++++++ ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 3 +++ 2 files changed, 9 insertions(+) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h b/ArmPkg/Library/Ar= mLib/AArch64/AArch64Lib.h index b2c8a8ea0b84..d6bcfc3b82ae 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h @@ -35,5 +35,11 @@ ArmCleanInvalidateDataCacheEntryBySetWay ( IN UINTN SetWayFormat ); =20 +UINTN +EFIAPI +ArmReadIdMmfr2 ( + VOID + ); + #endif // __AARCH64_LIB_H__ =20 diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Librar= y/ArmLib/AArch64/AArch64Support.S index 199374ff59e3..874bc2866ac3 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -424,6 +424,9 @@ ASM_FUNC(ArmCallWFI) wfi ret =20 +ASM_FUNC(ArmReadIdMmfr2) + mrs x0, ID_AA64MMFR2_EL1 // read EL1 MMFR2 + ret =20 ASM_FUNC(ArmReadMpidr) mrs x0, mpidr_el1 // read EL1 MPIDR --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#68390): https://edk2.groups.io/g/devel/message/68390 Mute This Topic: https://groups.io/mt/78784065/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 30 20:51:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+68391+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68391+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1607363691; cv=none; d=zohomail.com; s=zohoarc; b=cYAzAwyrD8whrc2ybzNqhK/f4J/iQAlRgUnjWqDbBo8s7L7rjVxQwrFJ2EfNOA2DLt3i/1ZNxLkNxVqo1J/68kdjn0ocL2oY6vILLnQUQJixxMbXvZlJpAv45Ry9XJDKgf/ixPEkhJigN8Z5MjUdV33kRF1oASP9gzqdZUtjXWc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607363691; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Oil9+w5O3FN1yVthNmgCEO8xfjyW0Cl/VHjgha13/Xk=; b=I34I7aRGWT76o7JnpbcpsJRmvq9WiRbGtQFIbYwk+AHObhVp1vP7JKm7iTw09A3ea7ZFf6kiMWiJNK66QYK78tfeGnWoQAWIERaz1fIlv3y4jZ3w+FoXgZSh/Y//JWc/sTjAUZdQy/KQdzJSGAbrmWFx6yfSEuuOjUNrmJrQUb8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68391+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1607363691146524.3347830655387; Mon, 7 Dec 2020 09:54:51 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id jAFqYY1788612xScdGNFvnLu; Mon, 07 Dec 2020 09:54:50 -0800 X-Received: from mail-pg1-f178.google.com (mail-pg1-f178.google.com [209.85.215.178]) by mx.groups.io with SMTP id smtpd.web09.154.1607363686619027673 for ; Mon, 07 Dec 2020 09:54:46 -0800 X-Received: by mail-pg1-f178.google.com with SMTP id g18so9554095pgk.1 for ; Mon, 07 Dec 2020 09:54:46 -0800 (PST) X-Gm-Message-State: XqHZ3kb3uanoquTCBYnkh56px1787277AA= X-Google-Smtp-Source: ABdhPJw7KLa8g9IrORVq42ShqLV8d2Fhke2C5oK5/Z6mZ2Gx2igF8Lr3MLVhHBnEHe3f8Ib7/fvzFw== X-Received: by 2002:a17:902:8a87:b029:d7:cf56:ce1f with SMTP id p7-20020a1709028a87b02900d7cf56ce1fmr17446172plo.22.1607363685841; Mon, 07 Dec 2020 09:54:45 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:45 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 05/10] ArmPkg: Add helper function to read the Memory Model Feature Register 4 Date: Mon, 7 Dec 2020 10:54:22 -0700 Message-Id: <20201207175427.28712-6-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363690; bh=mD1s3hksUMr9Ffs/X8XaSxtdCa109qBjquFVQplXESs=; h=Cc:Date:From:Reply-To:Subject:To; b=p+a2M7DS8xYyFf7cY+9bfjin+b33d3QAK5kgVgRzNT/3pIzVI/bcG+HuzdIUEfQTU92 HTreXA94axHetGHcmqKUKq6/6bVtXY0yPvw4rHQqy/vlsGx9tKwgmKARhhijd8sCnFxR5 pW1aa5Z71OQsUagLsg5t8Uz/M86b3d39oto= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" In AARCH32, CCIDX support is indicated in the MMFR4 register - unlike under AARCH64 where it's in MMFR2. Add a helper function to read it. Signed-off-by: Rebecca Cran Reviewed-by: Sami Mujawar --- ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h | 6 ++++++ ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S | 4 ++++ ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm | 4 ++++ 3 files changed, 14 insertions(+) diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h b/ArmPkg/Library/ArmLib/A= rm/ArmV7Lib.h index 93183e67230e..3b331a3b2088 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h @@ -48,5 +48,11 @@ ArmCleanInvalidateDataCacheEntryBySetWay ( IN UINTN SetWayFormat ); =20 +UINT32 +EFIAPI +ArmReadIdMmfr4 ( + VOID + ); + #endif // __ARM_V7_LIB_H__ =20 diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S b/ArmPkg/Library/A= rmLib/Arm/ArmLibSupportV7.S index 01c91b10fcb7..a60a2f634132 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S @@ -60,6 +60,10 @@ ASM_FUNC(ArmDisableInterrupts) isb bx LR =20 +ASM_FUNC(ArmReadIdMmfr4) + mrc p15,0,r0,c0,c2,6 @ Read ID_MMFR4 Register + bx lr + // UINT32 // ReadCCSIDR ( // IN UINT32 CSSELR diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm b/ArmPkg/Library= /ArmLib/Arm/ArmLibSupportV7.asm index 26ffa331b929..1679b09b797a 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm @@ -64,6 +64,10 @@ isb bx LR =20 + RVCT_ASM_EXPORT ArmReadIdMmfr4 + mrc p15,0,r0,c0,c2,6 ; Read ID_MMFR4 Register + bx LR + // UINT32 // ReadCCSIDR ( // IN UINT32 CSSELR --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:46 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 06/10] ArmPkg: Add helper to read CCIDX status Date: Mon, 7 Dec 2020 10:54:23 -0700 Message-Id: <20201207175427.28712-7-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363691; bh=41f3iC0U6IETI0YiK5BceAm1hIBl1kRr1523Z/FgfYk=; h=Cc:Date:From:Reply-To:Subject:To; b=clhThvQC410KEPxrD9cw1rXTgfi2o3cDcSshbIJ/pn0sWlJW2amadMBW71xyM7o3txN lgcFlCimiFJHDSwOT2iFXzrSvqa1xbpvxLWR3hALld7OlkUsiSo5biHyhppgqqXG81xbh h0lI+btkJPWQwee+2QOdGnaIHiMasHKhmV8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add a helper function to determine CCIDX support. Signed-off-by: Rebecca Cran Reviewed-by: Sami Mujawar --- ArmPkg/Include/Library/ArmLib.h | 6 ++++++ ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 12 ++++++++++++ ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c | 12 ++++++++++++ 3 files changed, 30 insertions(+) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index 5a27b7c2fc27..87c3a6f1ecac 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -132,6 +132,12 @@ ArmIsArchTimerImplemented ( VOID ); =20 +BOOLEAN +EFIAPI +ArmIsCcidxImplemented ( + VOID + ); + UINTN EFIAPI ArmReadIdPfr0 ( diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/Ar= mLib/AArch64/AArch64Lib.c index 3fbd591192e2..915c2cacdd99 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c @@ -71,3 +71,15 @@ ArmCleanDataCache ( ArmDataSynchronizationBarrier (); AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay); } + +BOOLEAN +EFIAPI +ArmIsCcidxImplemented ( + VOID + ) +{ + UINTN Mmfr2; + + Mmfr2 =3D ArmReadIdMmfr2 (); + return (((Mmfr2 >> 20) & 0xF) =3D=3D 1) ? TRUE : FALSE; +} diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c b/ArmPkg/Library/ArmLib/A= rm/ArmV7Lib.c index 2c4a23e1a1b2..7331b1c678f3 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c @@ -71,3 +71,15 @@ ArmCleanDataCache ( ArmDataSynchronizationBarrier (); ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay); } + +BOOLEAN +EFIAPI +ArmIsCcidxImplemented ( + VOID + ) +{ + UINTN Mmfr4; + + Mmfr4 =3D ArmReadIdMmfr4 (); + return (((Mmfr4 >> 24) & 0xF) =3D=3D 1) ? TRUE : FALSE; +} --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#68392): https://edk2.groups.io/g/devel/message/68392 Mute This Topic: https://groups.io/mt/78784068/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 30 20:51:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+68393+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68393+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1607363693; cv=none; d=zohomail.com; s=zohoarc; b=ddHGzvse5ljihUSg7WfsShy0RRXQk7gkXMk67mUbMtot3giEkodCis6Mw4Rm5uOV+5Wi2jnokxw+Vmj8+ldRUcawpHVgehY4uuR7mWt273IzOtOAZaRIF1yTn/tvldNfRAm4UxWDt9SlPwLt+4M1xb4BNULO73P7r0no0S8BcSg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607363693; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=yO3aQT8X/OIxBy4OL3KbyAyjI6275E4FaJpO4DlwtfI=; b=jFUKe9cuwbcyzzl06mpCjslIVTncJJiOma0Ax4V4tBjEppZUu0YYVk4+E2HiG9u12dye2kMMhecKrEtxOuFtXQyP/n1CCOPB2tAWSz4ujQL0b8SijnUbge+CmYhNc7VzdVLigNXL57KgpjGG6So5qo4R8aJDEJ2AjyOID2zh6QQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68393+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1607363693290662.6318381607643; Mon, 7 Dec 2020 09:54:53 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id IBdlYY1788612xmI6x0FJxQg; Mon, 07 Dec 2020 09:54:52 -0800 X-Received: from mail-pj1-f65.google.com (mail-pj1-f65.google.com [209.85.216.65]) by mx.groups.io with SMTP id smtpd.web11.155.1607363689437649703 for ; Mon, 07 Dec 2020 09:54:49 -0800 X-Received: by mail-pj1-f65.google.com with SMTP id l23so44044pjg.1 for ; Mon, 07 Dec 2020 09:54:49 -0800 (PST) X-Gm-Message-State: YmXKcBfixak1Gm7zmD6bcancx1787277AA= X-Google-Smtp-Source: ABdhPJx4O//OBp3H7qHFl0yADir79zPS01SHsUw4jlh0VM0zXezhtt91L4fpDCoEFbVwrJXrpPFI6w== X-Received: by 2002:a17:90a:73c2:: with SMTP id n2mr3757764pjk.37.1607363688642; Mon, 07 Dec 2020 09:54:48 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:48 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 07/10] ArmPkg: Fix the return type of the ReadCCSIDR function Date: Mon, 7 Dec 2020 10:54:24 -0700 Message-Id: <20201207175427.28712-8-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363692; bh=3/W/wr5su63uveMbai6Sj998/XXsC/QfhMrzS1A/WrA=; h=Cc:Date:From:Reply-To:Subject:To; b=mGlSdNx2jhM+UR44s0CtgipAhcs7EGzfLeMJ3faQMmxUAuFlIOwHzVd3QLYbYu46irj WJwd9aMwFrQ8JXMeO9gU0vQR4DEQ4oofmtUv8FJsfhm8KCZyStWkpV5qmkvAkUOBdsjwh sSkdlMbe4tvSbzIZPjdQJ9KllXxIj+rxBt0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" When CCIDX is supported, the Current Cache Size ID Register contains data above 32 bits: namely the number of sets. Avoid truncating this by returning a UINTN instead of UINT32. On AARCH32, the expanded number of sets data can be read via the CCSIDR2 register. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 2 +- ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S | 2 +- ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/= ArmLibPrivate.h index 2e90739eb858..5eecbc0e1c43 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -61,7 +61,7 @@ CPSRRead ( VOID ); =20 -UINT32 +UINTN ReadCCSIDR ( IN UINT32 CSSELR ); diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S b/ArmPkg/Libra= ry/ArmLib/AArch64/ArmLibSupportV8.S index 0e8d21e2264f..0ae75e4cb9f9 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S @@ -84,7 +84,7 @@ ASM_FUNC(ArmDisableAllExceptions) ret =20 =20 -// UINT32 +// UINTN // ReadCCSIDR ( // IN UINT32 CSSELR // ) diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm b/ArmPkg/Library= /ArmLib/Arm/ArmLibSupportV7.asm index 1679b09b797a..81f3cb79994c 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm @@ -68,7 +68,7 @@ mrc p15,0,r0,c0,c2,6 ; Read ID_MMFR4 Register bx LR =20 -// UINT32 +// UINTN // ReadCCSIDR ( // IN UINT32 CSSELR // ) --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:49 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 08/10] ArmPkg: Update ArmLibPrivate.h with cache register definitions Date: Mon, 7 Dec 2020 10:54:25 -0700 Message-Id: <20201207175427.28712-9-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363694; bh=N4+NpYpQ4UuubDhnci+U7o24WGZaRDK5/OY51H2ubqo=; h=Cc:Date:From:Reply-To:Subject:To; b=ew71tEcUqx4wuVUddkH+6NadoJfo8+d8b8DZ3BevAahEZ0oyFNn9fr0mA3jz8abcD/L iBeKamwNHJ9rrhpq4TjSa/bJVey9UotGtzrvu7Sr5tvk85PZKki2kw+DQwYhkiOHqBWm8 9rW8VFt4KIDtFg7wSF+LbGl6jXTh2C0T6ms= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Update the cache definitions in ArmLibPrivate.h based on current ARMv8 documentation. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 91 ++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/= ArmLibPrivate.h index 5eecbc0e1c43..fb1e2cc6b2ac 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -1,5 +1,7 @@ /** @file + ArmLibPrivate.h =20 + Copyright (c) 2020, NUVIA Inc. All rights reserved.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -50,6 +52,95 @@ #define CACHE_ARCHITECTURE_UNIFIED (0UL) #define CACHE_ARCHITECTURE_SEPARATE (1UL) =20 + +/// Defines the structure of the CSSELR (Cache Size Selection) register +typedef union { + struct { + UINT32 InD :1; ///< Instruction not Data bit + UINT32 Level :3; ///< Cache level (zero based) + UINT32 TnD :1; ///< Allocation not Data bit + UINT32 Reserved :27; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSELR_DATA; + +/// The cache type values for the InD field of the CSSELR register +typedef enum +{ + /// Select the data or unified cache + CsselrCacheTypeDataOrUnified =3D 0, + /// Select the instruction cache + CsselrCacheTypeInstruction, + CsselrCacheTypeMax +} CSSELR_CACHE_TYPE; + +/// Defines the structure of the CCSIDR (Current Cache Size ID) register +typedef union { + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in ca= che) - 4) + UINT64 Associativity :10; ///< Associativity - 1 + UINT64 NumSets :15; ///< Number of sets in the cache -1 + UINT64 Unknown :4; ///< Reserved, UNKNOWN + UINT64 Reserved :32; ///< Reserved, RES0 + } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX= is not supported. + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in ca= che) - 4) + UINT64 Associativity :21; ///< Associativity - 1 + UINT64 Reserved1 :8; ///< Reserved, RES0 + UINT64 NumSets :24; ///< Number of sets in the cache -1 + UINT64 Reserved2 :8; ///< Reserved, RES0 + } BitsCcidx; ///< Bitfield definition of the register when FEAT_IDX is s= upported. + UINT64 Data; ///< The entire 64-bit value +} CCSIDR_DATA; + +/// Defines the structure of the AARCH32 CCSIDR2 register. +typedef union { + struct { + UINT32 NumSets :24; ///< Number of sets in the cache - 1 + UINT32 Reserved :8; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSIDR2_DATA; + +/** Defines the structure of the CLIDR (Cache Level ID) register. + * + * The lower 32 bits are the same for both AARCH32 and AARCH64 + * so we can use the same structure for both. +**/ +typedef union { + struct { + UINT32 Ctype1 : 3; ///< Level 1 cache type + UINT32 Ctype2 : 3; ///< Level 2 cache type + UINT32 Ctype3 : 3; ///< Level 3 cache type + UINT32 Ctype4 : 3; ///< Level 4 cache type + UINT32 Ctype5 : 3; ///< Level 5 cache type + UINT32 Ctype6 : 3; ///< Level 6 cache type + UINT32 Ctype7 : 3; ///< Level 7 cache type + UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable + UINT32 LoC : 3; ///< Level of Coherency + UINT32 LoUU : 3; ///< Level of Unification Uniprocessor + UINT32 Icb : 3; ///< Inner Cache Boundary + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CLIDR_DATA; + +/// The cache types reported in the CLIDR register. +typedef enum { + /// No cache is present + ClidrCacheTypeNone =3D 0, + /// There is only an instruction cache + ClidrCacheTypeInstructionOnly, + /// There is only a data cache + ClidrCacheTypeDataOnly, + /// There are separate data and instruction caches + ClidrCacheTypeSeparate, + /// There is a unified cache + ClidrCacheTypeUnified, + ClidrCacheTypeMax +} CLIDR_CACHE_TYPE; + +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * level)) & 0b111) + VOID CPSRMaskInsert ( IN UINT32 Mask, --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#68394): https://edk2.groups.io/g/devel/message/68394 Mute This Topic: https://groups.io/mt/78784071/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 30 20:51:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+68395+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68395+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1607363695; cv=none; d=zohomail.com; s=zohoarc; b=P2f7LYE/kyAllxCoMmRceyWmHeUev9NzvNo6ZPsff7S7HTLZahLrxLIJYHUInJZpBuXXU3syKMs9tS1MHdEjKzP5Os+m2nb48RCFF5SRN5NTUBybFHCeNwDK+e6WTqMs/whwHzfx9p8teqD1hdbClAzi5Wc9yF0+AhbxeYGMpkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607363695; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Gm+fyAzURlk2KtCruZ1LhtlPoThPMxinplODNf42GeU=; b=lhJF1KkJ/VLNcan6zeeQJF4d4aPrC2o52XZZe117FyVVvs0E+63mX5adGnTQCRZxGNlvB1U3HBV11h7VUZWxk7Te6wRqPRmZEoXekTDm8mBbPMdK+HE6a/mNaZVXRe2JiCPOcRgk3HxK+J6PmOriDB0T5eXGiDDGS/ezAcs1Xk0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68395+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16073636957831003.0799719592543; Mon, 7 Dec 2020 09:54:55 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id QsjtYY1788612xaoPUKgzeJT; Mon, 07 Dec 2020 09:54:54 -0800 X-Received: from mail-pf1-f193.google.com (mail-pf1-f193.google.com [209.85.210.193]) by mx.groups.io with SMTP id smtpd.web10.133.1607363692010217607 for ; Mon, 07 Dec 2020 09:54:52 -0800 X-Received: by mail-pf1-f193.google.com with SMTP id 131so10778280pfb.9 for ; Mon, 07 Dec 2020 09:54:51 -0800 (PST) X-Gm-Message-State: A9qRNgZPamU1rV3GKIXi0trAx1787277AA= X-Google-Smtp-Source: ABdhPJwuW2lt/38Kyj8XaJnF5rNLXChBqdvXuCI/bksYl5pUJhbkPyVwQJit4jMoKPN1WIeTCZn8Xg== X-Received: by 2002:a62:b607:0:b029:197:7177:df6e with SMTP id j7-20020a62b6070000b02901977177df6emr17348216pff.4.1607363691243; Mon, 07 Dec 2020 09:54:51 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:50 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 09/10] ArmPkg: Add definition of the maximum cache level in ARMv8-A Date: Mon, 7 Dec 2020 10:54:26 -0700 Message-Id: <20201207175427.28712-10-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363694; bh=axCShmMtQg0mP2IpeZf7GQVYDOr317ddLjNrGQyMT3U=; h=Cc:Date:From:Reply-To:Subject:To; b=EzEod7N5flC0UKUsqoelYNP4m3pUR2XDPAtcSGr1DFNtc9LYu59Pe+rB7NWH6TF9gH6 Lipw9KvHbjf4lTHvJRDT10tQtvblJMniDWFO5TExBi0UyxJ+/CpYvkQv3ZO/ULWsoe1zv eGb+g1qcA/FVCxj3Z2hKEYbDjfK1Ns2vOuY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The ARM Architecture Reference Manual for ARMv8-A defines up to seven levels of cache, L1 through L7. Define MAX_ARM_CACHE_LEVEL to be 7. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/Library/ArmLib.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index 87c3a6f1ecac..4e26991727cb 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -108,6 +108,10 @@ typedef enum { #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK) =20 +// The ARM Architecture Reference Manual for ARMv8-A defines up +// to 7 levels of cache, L1 through L7. +#define MAX_ARM_CACHE_LEVEL 7 + UINTN EFIAPI ArmDataCacheLineLength ( --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#68395): https://edk2.groups.io/g/devel/message/68395 Mute This Topic: https://groups.io/mt/78784073/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 30 20:51:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+68396+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68396+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1607363697; cv=none; d=zohomail.com; s=zohoarc; b=kBT4ePkN/99bNJfYlb5eXn6ZdU1B9pGYPhO66PnDNC3efBi4cGa9h/qmbDv01rMztHT4FHyga8bDqHl/SNF/lS4fi+QUALfdeqY0pFRcth7Nitwua+VDV3rql/5wSO4kLg5UzkuZEgCyh6PCCmtniUokeJb4Jfqg+FZXfuokmWI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607363697; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=tMxghvE3L0fv3rP0XKS7orQFFJ2XwC7+TzDRaBhqx+g=; b=mBAgV+eNBk5Wfs1yBH2E2J6c/nxMNZvPko8B//LN7oaaSOUrf2TQZvmpZiIeq4DXZ0tQB5igLtZ8DZOCmz6G1fz1PACu7LNTg1ZwVtcRrXYjRt4c4Y2AYkFRLAjeqO5iK5nJi/3C4kNYbqR5Si+Gt91Kr8GFX6rcRIPlWJMY4Lo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68396+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1607363697336819.7764480404852; Mon, 7 Dec 2020 09:54:57 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id kw7EYY1788612xOZuFeXFc0E; Mon, 07 Dec 2020 09:54:56 -0800 X-Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) by mx.groups.io with SMTP id smtpd.web09.159.1607363696268900859 for ; Mon, 07 Dec 2020 09:54:56 -0800 X-Received: by mail-pj1-f44.google.com with SMTP id e5so48447pjt.0 for ; Mon, 07 Dec 2020 09:54:56 -0800 (PST) X-Gm-Message-State: kQ62DwNiPUEF5eOLDFKNWkIPx1787277AA= X-Google-Smtp-Source: ABdhPJxfh1fyFLmMDO+wttWQwdM6FkRhzzIT7swjf4+nx7WSxjppW6dtax7ut0lgBE+IFIyDwaxxsg== X-Received: by 2002:a17:90a:ea02:: with SMTP id w2mr2089581pjy.99.1607363693235; Mon, 07 Dec 2020 09:54:53 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:52 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [edk2-devel] [PATCH v4 10/10] ArmPkg: Add Universal/Smbios, a generic SMBIOS library for ARM Date: Mon, 7 Dec 2020 10:54:27 -0700 Message-Id: <20201207175427.28712-11-rebecca@nuviainc.com> In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1607363696; bh=9V9OLcnGcUNXiry7kOJ1+3TeIfEGDGSO3oSob11avv0=; h=Cc:Date:From:Reply-To:Subject:To; b=uD5tn/m5m2LSBEgPjW009PyEraYHPAiAGaAiyWWAHxM+jdZXhoNWtoqC3QGhEBrM1ba q8l6BaUMsItV4JOv8frdYOSCO46SlRevUooGIoQWPJ7AaWD6+P8ha4w12MT1cu782ptWo 0TR5E1ZSGxmGuJsA+QGoXJDwb0Vgy0U8JqY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Much of the data for the SMBIOS tables is generic, and need not be duplicated for each platform. This patch series introduces ArmPkg/Universal/Smbios, which is largely copied from edk2-platforms/Silicon/HiSilicon/Drivers/Smbios and generates SMBIOS tables 0,1,2,3,4,713,32 and uses a combination of PCDs and calls into a new OemMiscLib to get information which varies between platforms. Signed-off-by: Rebecca Cran --- ArmPkg/ArmPkg.dec = | 14 + ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf = | 56 ++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf = | 86 ++ ArmPkg/Include/Library/OemMiscLib.h = | 95 +++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMisc.h = | 136 ++++ ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c = | 835 ++++++++++++++++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c = | 61 ++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c = | 178 +++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c = | 92 +++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c = | 263 ++++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c = | 35 + ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunctio= n.c | 173 ++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData= .c | 45 ++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunc= tion.c | 201 +++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c= | 51 ++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFuncti= on.c | 200 +++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLangua= gesData.c | 32 + ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLangua= gesFunction.c | 154 ++++ ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c = | 34 + ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c= | 67 ++ ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings.uni = | 23 + ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscLibStrings.uni = | 21 + ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni = | 17 + ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.uni = | 20 + ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturer.uni= | 20 + ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.uni = | 17 + ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLangua= ges.uni | 42 + 27 files changed, 2968 insertions(+) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index eaf1072d9ef3..62683146ed40 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -115,6 +115,20 @@ [PcdsFixedAtBuild.common] # The Primary Core is ClusterId[0] & CoreId[0] gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037 =20 + # + # SMBIOS PCDs + # + gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053 + gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054 + gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055 + gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056 + gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057 + gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071 + gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072 + gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073 + gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074 + gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075 + # # ARM L2x0 PCDs # diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass= Dxe.inf b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe= .inf new file mode 100644 index 000000000000..35e8e830b797 --- /dev/null +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf @@ -0,0 +1,56 @@ +#/** @file +# +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D ProcessorSubClass + FILE_GUID =3D f3fe0e33-ea38-4069-9fb5-be23407207c7 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ProcessorSubClassEntryPoint + +[Sources] + ProcessorSubClass.c + ProcessorSubClassStrings.uni + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + ArmSmcLib + BaseLib + BaseMemoryLib + DebugLib + HiiLib + IoLib + MemoryAllocationLib + OemMiscLib + PcdLib + PrintLib + UefiDriverEntryPoint + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Pcd] + gArmTokenSpaceGuid.PcdProcessorManufacturer + gArmTokenSpaceGuid.PcdProcessorVersion + gArmTokenSpaceGuid.PcdProcessorSerialNumber + gArmTokenSpaceGuid.PcdProcessorAssetTag + gArmTokenSpaceGuid.PcdProcessorPartNumber + +[Guids] + + +[Depex] + gEfiSmbiosProtocolGuid diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/ArmP= kg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf new file mode 100644 index 000000000000..2b31317451cd --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf @@ -0,0 +1,86 @@ +## @file +# Component description file for SmbiosMisc instance. +# +# Parses the MiscSubclassDataTable and reports any generated data to the D= ataHub. +# All .uni file who tagged with "ToolCode=3D"DUMMY"" in following file li= st is included by +# MiscSubclassDriver.uni file, the StrGather tool will expand MiscSubclas= sDriver.uni file +# and parse all .uni file. +# +# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +# Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ +## + + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D SmbiosMiscDxe + FILE_GUID =3D 7e5e26d4-0be9-401f-b5e1-1c2bda7ca777 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmbiosMiscEntryPoint + +[Sources] + SmbiosMisc.h + SmbiosMiscDataTable.c + SmbiosMiscEntryPoint.c + SmbiosMiscLibStrings.uni + Type00/MiscBiosVendorData.c + Type00/MiscBiosVendorFunction.c + Type01/MiscSystemManufacturerData.c + Type01/MiscSystemManufacturerFunction.c + Type02/MiscBaseBoardManufacturerData.c + Type02/MiscBaseBoardManufacturerFunction.c + Type03/MiscChassisManufacturerData.c + Type03/MiscChassisManufacturerFunction.c + Type13/MiscNumberOfInstallableLanguagesData.c + Type13/MiscNumberOfInstallableLanguagesFunction.c + Type32/MiscBootInformationData.c + Type32/MiscBootInformationFunction.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + PcdLib + HiiLib + HobLib + MemoryAllocationLib + OemMiscLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Pcd] + gArmTokenSpaceGuid.PcdFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + gArmTokenSpaceGuid.PcdSystemProductName + gArmTokenSpaceGuid.PcdSystemVersion + gArmTokenSpaceGuid.PcdBaseBoardManufacturer + gArmTokenSpaceGuid.PcdBaseBoardProductName + gArmTokenSpaceGuid.PcdBaseBoardVersion + gArmTokenSpaceGuid.PcdFdBaseAddress + +[Guids] + gEfiGenericVariableGuid + +[Depex] + gEfiSmbiosProtocolGuid + + diff --git a/ArmPkg/Include/Library/OemMiscLib.h b/ArmPkg/Include/Library/O= emMiscLib.h new file mode 100644 index 000000000000..4b70fb539e09 --- /dev/null +++ b/ArmPkg/Include/Library/OemMiscLib.h @@ -0,0 +1,95 @@ +/** @file +* +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + + +#ifndef OEM_MISC_LIB_H_ +#define OEM_MISC_LIB_H_ + +#include +#include + +typedef enum +{ + CpuCacheL1 =3D 0, + CpuCacheL2, + CpuCacheL3, + CpuCacheL4, + CpuCacheL5, + CpuCacheL6, + CpuCacheL7, + CpuCacheLevelMax +} CPU_CACHE_LEVEL; + +typedef struct +{ + UINT8 Voltage; ///< Processor voltage + UINT16 CurrentSpeed; ///< Current clock speed in MHz + UINT16 MaxSpeed; ///< Maximum clock speed in MHz + UINT16 ExternalClock; ///< External clock speed in MHz + UINT16 CoreCount; ///< Number of cores available + UINT16 CoresEnabled; ///< Number of cores enabled + UINT16 ThreadCount; ///< Number of threads per processor +} MISC_PROCESSOR_DATA; + +typedef enum { + ProductNameType01, + SerialNumType01, + UuidType01, + SystemManufacturerType01, + AssertTagType02, + SerialNumberType02, + BoardManufacturerType02, + AssetTagType03, + SerialNumberType03, + VersionType03, + ChassisTypeType03, + ManufacturerType03, + SmbiosHiiStringFieldMax +} SMBIOS_HII_STRING_FIELD; + +/* + * The following are functions that the each platform needs to + * implement in its OemMiscLib library. + */ + +UINTN OemGetCpuFreq ( + IN UINT8 ProcessorIndex + ); + +BOOLEAN +OemGetProcessorInformation ( + IN UINTN ProcessorNumber, + IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus, + IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics, + IN OUT MISC_PROCESSOR_DATA *MiscProcessorData + ); + +BOOLEAN OemGetCacheInformation ( + IN UINT8 CacheLevel, + IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable + ); + +UINT8 OemGetProcessorMaxSockets (VOID); + +EFI_STATUS OemGetChassisType ( + OUT UINT8 *ChassisType + ); + +BOOLEAN OemIsSocketPresent ( + IN UINTN ProcessorIndex + ); + +VOID +UpdateSmbiosInfo ( + IN EFI_HII_HANDLE mHiiHandle, + IN EFI_STRING_ID TokenToUpdate, + IN SMBIOS_HII_STRING_FIELD Offset + ); + +#endif // OEM_MISC_LIB_H_ diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMisc.h b/ArmPkg/Un= iversal/Smbios/SmbiosMiscDxe/SmbiosMisc.h new file mode 100644 index 000000000000..20840f40d04b --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMisc.h @@ -0,0 +1,136 @@ +/** @file + Header file for the SmbiosMisc Driver. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMBIOS_MISC_H_ +#define SMBIOS_MISC_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +// +// Data table entry update function. +// +typedef EFI_STATUS (EFIAPI EFI_MISC_SMBIOS_DATA_FUNCTION) ( + IN VOID *RecordData, + IN EFI_SMBIOS_PROTOCOL *Smbios + ); + + +// +// Data table entry definition. +// +typedef struct { + // + // intermediate input data for SMBIOS record + // + VOID *RecordData; + EFI_MISC_SMBIOS_DATA_FUNCTION *Function; +} EFI_MISC_SMBIOS_DATA_TABLE; + + +// +// SMBIOS table extern definitions +// +#define MISC_SMBIOS_TABLE_EXTERNS(NAME1, NAME2, NAME3) \ +extern NAME1 NAME2 ## Data; \ +extern EFI_MISC_SMBIOS_DATA_FUNCTION NAME3 ## Function; + + +// +// SMBIOS data table entries +// +// This is used to define a pair of table structure pointer and functions +// in order to iterate through the list of tables, populate them and add +// them into the system. +#define MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(NAME1, NAME2) \ +{ \ + & NAME1 ## Data, \ + NAME2 ## Function \ +} + +// +// Global definition macros. +// +#define MISC_SMBIOS_TABLE_DATA(NAME1, NAME2) \ + NAME1 NAME2 ## Data + +#define MISC_SMBIOS_TABLE_FUNCTION(NAME2) \ + EFI_STATUS EFIAPI NAME2 ## Function( \ + IN VOID *RecordData, \ + IN EFI_SMBIOS_PROTOCOL *Smbios \ + ) + +// +// Data Table Array Entries +// +extern EFI_HII_HANDLE mHiiHandle; + +typedef struct _EFI_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING{ + UINT8 *LanguageSignature; + EFI_STRING_ID InstallableLanguageLongString; + EFI_STRING_ID InstallableLanguageAbbreviateString; +} EFI_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING; + + +/** + Logs SMBIOS record. + + @param [in] Buffer Pointer to the data buffer. + @param [in] SmbiosHandle Pointer for retrieve handle. + +**/ +EFI_STATUS +LogSmbiosData ( + IN UINT8 *Buffer, + IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle + ); + +/** + Get Link Type Handle. + + @param [in] SmbiosType Get this Type from SMBIOS table + @param [out] HandleArray Pointer to handle array which will be freed = by caller + @param [out] HandleCount Pointer to handle count + +**/ +VOID +GetLinkTypeHandle( + IN UINT8 SmbiosType, + OUT UINT16 **HandleArray, + OUT UINTN *HandleCount + ); + +// +// Data Table Array +// +extern EFI_MISC_SMBIOS_DATA_TABLE mSmbiosMiscDataTable[]; + +// +// Data Table Array Entries +// +extern UINTN mSmbiosMiscDataTableEntries; +extern UINT8 SmbiosMiscDxeStrings[]; + +#endif // SMBIOS_MISC_H_ diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass= .c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c new file mode 100644 index 000000000000..bd91451b6382 --- /dev/null +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -0,0 +1,835 @@ +/** @file +* ProcessorSubClass.c +* +* Copyright (c) 2020, NUVIA Inc. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern UINT8 ProcessorSubClassStrings[]; + +#define CACHE_SOCKETED_SHIFT 3 +#define CACHE_LOCATION_SHIFT 5 +#define CACHE_ENABLED_SHIFT 7 +#define CACHE_OPERATION_MODE_SHIFT 8 + +// Sets the HII variable `x` if `pcd` isn't empty +#define SET_HII_STRING_IF_PCD_NOT_EMPTY(pcd, x) \ + x##Str =3D (CHAR16 *)PcdGetPtr (pcd); \ + if (StrLen (x##Str) > 0) { \ + HiiSetString (mHiiHandle, x, x##Str, NULL); \ + } \ + +typedef enum { + CacheModeWriteThrough =3D 0, ///< Cache is write-through + CacheModeWriteBack, ///< Cache is write-back + CacheModeVariesWithAddress, ///< Cache mode varies by address + CacheModeUnknown, ///< Cache mode is unknown + CacheModeMax +} CACHE_OPERATION_MODE; + +typedef enum { + CacheLocationInternal =3D 0, ///< Cache is internal to the processor + CacheLocationExternal, ///< Cache is external to the processor + CacheLocationReserved, ///< Reserved + CacheLocationUnknown, ///< Cache location is unknown + CacheLocationMax +} CACHE_LOCATION; + +EFI_HII_HANDLE mHiiHandle; + +EFI_SMBIOS_PROTOCOL *mSmbios; + +SMBIOS_TABLE_TYPE4 mSmbiosProcessorTableTemplate =3D { + { // Hdr + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE4), // Length + 0 // Handle + }, + 1, // Socket + CentralProcessor, // ProcessorType + ProcessorFamilyIndicatorFamily2, // ProcessorFamily + 2, // ProcessorManufacture + { // ProcessorId + { // Signature + 0 + }, + { // FeatureFlags + 0 + } + }, + 3, // ProcessorVersion + { // Voltage + 0 + }, + 0, // ExternalClock + 0, // MaxSpeed + 0, // CurrentSpeed + 0, // Status + ProcessorUpgradeUnknown, // ProcessorUpgrade + 0xFFFF, // L1CacheHandle + 0xFFFF, // L2CacheHandle + 0xFFFF, // L3CacheHandle + 4, // SerialNumber + 5, // AssetTag + 6, // PartNumber + 0, // CoreCount + 0, //EnabledCoreCount + 0, // ThreadCount + 0, // ProcessorCharacteristics + ProcessorFamilyARM, // ProcessorFamily2 + 0, // CoreCount2 + 0, // EnabledCoreCount2 + 0 // ThreadCount2 +}; + + +/** Fetches the specified processor's frequency in Hz + * + * @param ProcessorNumber The processor number + * + * @return The clock frequency in MHz + * +**/ +UINT16 +GetCpuFrequency ( + IN UINT8 ProcessorNumber + ) +{ + return (UINT16)(OemGetCpuFreq (ProcessorNumber) / 1000 / 1000); +} + +/** Gets a description of the specified cache + * + * @param[in] CacheLevel Zero-based cache level (e.g. L1 cache is 0) + * @param[in] CacheSubLevel Where the cache level has separate data and + * instruction caches, 0 is instruction and 1 i= s data + * @param[out] CacheSocketStr The description of the specified cache + * + * @return The number of Unicode characters in CacheSocketStr not includin= g the + * terminating NUL +**/ +UINTN +GetCacheSocketStr ( + IN UINT8 CacheLevel, + IN UINT8 CacheSubLevel, + OUT CHAR16 *CacheSocketStr + ) +{ + UINTN CacheSocketStrLen; + + if (CacheLevel =3D=3D CpuCacheL1 + && CacheSubLevel =3D=3D 0) { + CacheSocketStrLen =3D UnicodeSPrint ( + CacheSocketStr, + SMBIOS_STRING_MAX_LENGTH - 1, + L"L%x Instruction Cache", + CacheLevel + 1); + } else if (CacheLevel =3D=3D CpuCacheL1 && CacheSubLevel =3D=3D 1) { + CacheSocketStrLen =3D UnicodeSPrint (CacheSocketStr, + SMBIOS_STRING_MAX_LENGTH - 1, + L"L%x Data Cache", + CacheLevel + 1); + } else { + CacheSocketStrLen =3D UnicodeSPrint (CacheSocketStr, + SMBIOS_STRING_MAX_LENGTH - 1, + L"L%x Cache", + CacheLevel + 1); + } + + return CacheSocketStrLen; +} + +/** Fills in the Type 7 record with the cache architecture information + * read from the CPU registers. + * + * @param[in] CacheLevel Cache level (e.g. L1) + * @param[in] CacheSubLevel Type of cache (e.g. instruction) + * @param[in] CcidxSupported Whether CCIDX is supported + * @param[in] CacheType The type of cache supported at this cache= level + * @param[out] Type7Record The Type 7 record to fill in + * +**/ +VOID +SetCacheArchitectureInformation ( + IN UINT8 CacheLevel, + IN UINT8 CacheSubLevel, + IN BOOLEAN CcidxSupported, + IN CLIDR_CACHE_TYPE CacheType, + OUT SMBIOS_TABLE_TYPE7 *Type7Record + ) +{ + CSSELR_DATA Csselr; + CCSIDR_DATA Ccsidr; + UINT8 Associativity; + UINT32 CacheSize32; + UINT16 CacheSize16; + UINT64 CacheSize64; + + Csselr.Data =3D 0; + Csselr.Bits.Level =3D CacheLevel; + + if (CacheSubLevel =3D=3D 0) { + if (CacheType =3D=3D ClidrCacheTypeInstructionOnly || + CacheType =3D=3D ClidrCacheTypeSeparate) { + Csselr.Bits.InD =3D CsselrCacheTypeInstruction; + Type7Record->SystemCacheType =3D CacheTypeInstruction; + } else { + Csselr.Bits.InD =3D CsselrCacheTypeDataOrUnified; + if (CacheType =3D=3D ClidrCacheTypeDataOnly) { + Type7Record->SystemCacheType =3D CacheTypeData; + } else { + Type7Record->SystemCacheType =3D CacheTypeUnified; + } + } + } else { + Type7Record->SystemCacheType =3D CacheTypeData; + Csselr.Bits.InD =3D CsselrCacheTypeDataOrUnified; + } + + // Read the CCSIDR register to get the cache architecture + Ccsidr.Data =3D ReadCCSIDR (Csselr.Data); + + if (CcidxSupported) { + CacheSize64 =3D (UINT64)(1 << (Ccsidr.BitsCcidx.LineSize + 4)) * + (Ccsidr.BitsCcidx.Associativity + 1) * + (Ccsidr.BitsCcidx.NumSets + 1); + Associativity =3D Ccsidr.BitsCcidx.Associativity; + } else { + CacheSize64 =3D (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) * + (Ccsidr.BitsNonCcidx.Associativity + 1) * + (Ccsidr.BitsNonCcidx.NumSets + 1); + Associativity =3D Ccsidr.BitsNonCcidx.Associativity; + } + + CacheSize64 /=3D 1024; // Minimum granularity is 1K + + // Encode the cache size into the format SMBIOS wants + if (CacheSize64 < MAX_INT16) { + CacheSize16 =3D CacheSize64; + CacheSize32 =3D CacheSize16; + } else if ((CacheSize64 / 64) < MAX_INT16) { + CacheSize16 =3D (1 << 15) | (CacheSize64 / 64); + CacheSize32 =3D CacheSize16; + } else { + if ((CacheSize64 / 1024) <=3D 2047) { + CacheSize32 =3D CacheSize64; + } else { + CacheSize32 =3D (1 << 31) | (CacheSize64 / 64); + } + + CacheSize16 =3D -1; + } + + Type7Record->Associativity =3D Associativity + 1; + Type7Record->MaximumCacheSize =3D CacheSize16; + Type7Record->InstalledSize =3D CacheSize16; + Type7Record->MaximumCacheSize2 =3D CacheSize32; + Type7Record->InstalledSize2 =3D CacheSize32; + + switch (Associativity + 1) { + case 2: + Type7Record->Associativity =3D CacheAssociativity2Way; + break; + case 4: + Type7Record->Associativity =3D CacheAssociativity4Way; + break; + case 8: + Type7Record->Associativity =3D CacheAssociativity8Way; + break; + case 16: + Type7Record->Associativity =3D CacheAssociativity16Way; + break; + case 12: + Type7Record->Associativity =3D CacheAssociativity12Way; + break; + case 24: + Type7Record->Associativity =3D CacheAssociativity24Way; + break; + case 32: + Type7Record->Associativity =3D CacheAssociativity32Way; + break; + case 48: + Type7Record->Associativity =3D CacheAssociativity48Way; + break; + case 64: + Type7Record->Associativity =3D CacheAssociativity64Way; + break; + case 20: + Type7Record->Associativity =3D CacheAssociativity20Way; + break; + default: + Type7Record->Associativity =3D CacheAssociativityOther; + break; + } + + Type7Record->CacheConfiguration =3D (CacheModeUnknown << CACHE_OPERATION= _MODE_SHIFT) | + (1 << CACHE_ENABLED_SHIFT) | + (CacheLocationUnknown << CACHE_LOCATIO= N_SHIFT) | + (0 << CACHE_SOCKETED_SHIFT) | + CacheLevel; +} + + +/** Allocates and initializes an SMBIOS_TABLE_TYPE7 structure + * + * @param[in] CacheLevel The cache level (L1-L7) + * @param[in] CacheSubLevel The type of cache + * + * @return A pointer to the Type 7 structure. Returns NULL on failure. + * +**/ +SMBIOS_TABLE_TYPE7 * +AllocateAndInitCacheInformation ( + IN UINT8 CacheLevel, + IN UINT8 CacheSubLevel + ) +{ + SMBIOS_TABLE_TYPE7 *Type7Record; + EFI_STRING CacheSocketStr; + UINTN CacheSocketStrLen; + UINTN StringBufferSize; + CHAR8 *OptionalStrStart; + UINTN TableSize; + + // Allocate and fetch the cache description + StringBufferSize =3D sizeof (CHAR16) * SMBIOS_STRING_MAX_LENGTH; + CacheSocketStr =3D AllocateZeroPool (StringBufferSize); + if (CacheSocketStr =3D=3D NULL) { + return NULL; + } + + CacheSocketStrLen =3D GetCacheSocketStr (CacheLevel, CacheSubLevel, Cach= eSocketStr); + + TableSize =3D sizeof (SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1; + Type7Record =3D AllocateZeroPool (TableSize); + if (Type7Record =3D=3D NULL) { + FreePool(CacheSocketStr); + return NULL; + } + + Type7Record->Hdr.Type =3D EFI_SMBIOS_TYPE_CACHE_INFORMATION; + Type7Record->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE7); + Type7Record->Hdr.Handle =3D SMBIOS_HANDLE_PI_RESERVED; + + Type7Record->SocketDesignation =3D 1; + + Type7Record->SupportedSRAMType.Unknown =3D 1; + Type7Record->CurrentSRAMType.Unknown =3D 1; + Type7Record->CacheSpeed =3D 0; + Type7Record->ErrorCorrectionType =3D CacheErrorUnknown; + + OptionalStrStart =3D (CHAR8 *)(Type7Record + 1); + UnicodeStrToAsciiStrS (CacheSocketStr, OptionalStrStart, CacheSocketStrL= en + 1); + FreePool (CacheSocketStr); + + return Type7Record; +} + + +/** + * Add Type 7 SMBIOS Record for Cache Information. + * + * @param[in] ProcessorNumber Processor number of specified process= or. + * @param[out] L1CacheHandle Pointer to the handle of the L1 Cache= SMBIOS record. + * @param[out] L2CacheHandle Pointer to the handle of the L2 Cache= SMBIOS record. + * @param[out] L3CacheHandle Pointer to the handle of the L3 Cache= SMBIOS record. + * +**/ +VOID +AddSmbiosCacheTypeTable ( + IN UINTN ProcessorIndex, + OUT EFI_SMBIOS_HANDLE *L1CacheHandle, + OUT EFI_SMBIOS_HANDLE *L2CacheHandle, + OUT EFI_SMBIOS_HANDLE *L3CacheHandle + ) +{ + EFI_STATUS Status; + SMBIOS_TABLE_TYPE7 *Type7Record; + EFI_SMBIOS_HANDLE SmbiosHandle; + UINT8 CacheLevel; + UINT8 CacheSubLevel; + CLIDR_DATA Clidr; + BOOLEAN CcidxSupported; + UINT8 MaxCacheLevel; + + Status =3D EFI_SUCCESS; + + MaxCacheLevel =3D 0; + + // Read the CLIDR register to find out what caches are present. + Clidr.Data =3D ReadCLIDR (); + + // Get the cache type for the L1 cache. If it's 0, there are no caches. + if (CLIDR_GET_CACHE_TYPE (Clidr.Data, 0) =3D=3D ClidrCacheTypeNone) { + return; + } + + for (CacheLevel =3D 1; CacheLevel < MAX_ARM_CACHE_LEVEL; CacheLevel++) { + if (CLIDR_GET_CACHE_TYPE (Clidr.Data, CacheLevel) =3D=3D ClidrCacheTyp= eNone) { + MaxCacheLevel =3D CacheLevel; + break; + } + } + + CcidxSupported =3D ArmIsCcidxImplemented (); + + for (CacheLevel =3D 0; CacheLevel < MaxCacheLevel; CacheLevel++) { + Type7Record =3D NULL; + + CLIDR_CACHE_TYPE CacheType =3D CLIDR_GET_CACHE_TYPE (Clidr.Data, Cache= Level); + + // At each level of cache, we can have a single type (unified, instruc= tion or data), + // or two types - separate data and instruction caches. If we have sep= arate + // instruction and data caches, then on the first iteration (CacheSubL= evel =3D 0) + // process the instruction cache. + for (CacheSubLevel =3D 0; CacheSubLevel <=3D 1; CacheSubLevel++) { + // If there's no separate data/instruction cache, skip the second it= eration + if (CacheSubLevel > 0 && CacheType !=3D ClidrCacheTypeSeparate) { + continue; + } + + Type7Record =3D AllocateAndInitCacheInformation (CacheLevel, CacheSu= bLevel); + if (Type7Record =3D=3D NULL) { + continue; + } + + SetCacheArchitectureInformation(CacheLevel, CacheSubLevel, CcidxSupp= orted, + CacheType, Type7Record); + + // Allow the platform to fill in other information such as speed, SR= AM type etc. + if (!OemGetCacheInformation (CacheLevel, Type7Record)) { + continue; + } + + SmbiosHandle =3D SMBIOS_HANDLE_PI_RESERVED; + // Finally, install the table + Status =3D mSmbios->Add (mSmbios, NULL, &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *)Type7Record); + if (EFI_ERROR (Status)) { + continue; + } + + // Config L1/L2/L3 Cache Handle + switch (CacheLevel) { + case CpuCacheL1: + *L1CacheHandle =3D SmbiosHandle; + break; + case CpuCacheL2: + *L2CacheHandle =3D SmbiosHandle; + break; + case CpuCacheL3: + *L3CacheHandle =3D SmbiosHandle; + break; + default: + break; + } + } + } +} + +/** Fills in the Type 4 CPU processor ID field + * + * @param[out] Type4Record The SMBIOS Type 4 record to fill in + * +**/ +VOID +SetProcessorIdField ( + OUT SMBIOS_TABLE_TYPE4 *Type4Record +) +{ + ARM_SMC_ARGS Args; + INT32 SmcCallStatus; + INT32 Jep106Code; + INT32 SocRevision; + BOOLEAN Arm64SocIdSupported =3D FALSE; + UINT64 *ProcessorId; + + Args.Arg0 =3D SMCCC_VERSION; + ArmCallSmc (&Args); + SmcCallStatus =3D (INT32)Args.Arg0; + + if (SmcCallStatus < 0 || (SmcCallStatus >> 16) >=3D 1) { + Args.Arg0 =3D SMCCC_ARCH_FEATURES; + Args.Arg1 =3D SMCCC_ARCH_SOC_ID; + ArmCallSmc (&Args); + + if (Args.Arg0 >=3D 0) { + PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristicFlags =3D + (PROCESSOR_CHARACTERISTIC_FLAGS*)&Type4Record->ProcessorCharacteri= stics; + Args.Arg0 =3D SMCCC_ARCH_SOC_ID; + Args.Arg1 =3D 0; + ArmCallSmc (&Args); + SmcCallStatus =3D (int)Args.Arg0; + + if (SmcCallStatus >=3D 0) { + Arm64SocIdSupported =3D TRUE; + ProcessorCharacteristicFlags->ProcessorArm64SocId =3D 1; + Jep106Code =3D (int)Args.Arg0; + } else { + ProcessorCharacteristicFlags->ProcessorArm64SocId =3D 0; + } + Args.Arg0 =3D SMCCC_ARCH_SOC_ID; + Args.Arg1 =3D 1; + ArmCallSmc (&Args); + SmcCallStatus =3D (int)Args.Arg0; + + if (SmcCallStatus >=3D 0) { + SocRevision =3D (int)Args.Arg0; + } + } + } + + ProcessorId =3D (UINT64 *)&Type4Record->ProcessorId; + + if (Arm64SocIdSupported) { + *ProcessorId =3D ((UINT64)Jep106Code << 32) | SocRevision; + } else { + *ProcessorId =3D ArmReadMidr (); + } +} + + +/** Allocates a Type 4 Processor Information structure and sets the + * strings following the data fields. + * + * @param[out] Type4Record The Type 4 structure to allocate and initial= ize + * @param[in] ProcessorIndex The index of the processor socket + * @param[in] Populated Whether the specified processor socket is + * populated. + * + * @retval EFI_SUCCESS The Type 4 structure was successfully + * allocated and the strings initialized. +**/ +EFI_STATUS +AllocateType4AndSetProcessorInformationStrings ( + SMBIOS_TABLE_TYPE4 **Type4Record, + UINT8 ProcessorIndex, + BOOLEAN Populated + ) +{ + EFI_STATUS Status; + EFI_STRING_ID ProcessorManu; + EFI_STRING_ID ProcessorVersion; + EFI_STRING_ID SerialNumber; + EFI_STRING_ID AssetTag; + EFI_STRING_ID PartNumber; + EFI_STRING ProcessorSocketStr; + EFI_STRING ProcessorManuStr; + EFI_STRING ProcessorVersionStr; + EFI_STRING SerialNumberStr; + EFI_STRING AssetTagStr; + EFI_STRING PartNumberStr; + CHAR8 *OptionalStrStart; + CHAR8 *StrStart; + UINTN ProcessorSocketStrLen; + UINTN ProcessorManuStrLen; + UINTN ProcessorVersionStrLen; + UINTN SerialNumberStrLen; + UINTN AssetTagStrLen; + UINTN PartNumberStrLen; + UINTN TotalSize; + UINTN StringBufferSize; + + Status =3D EFI_SUCCESS; + + ProcessorManuStr =3D NULL; + ProcessorVersionStr =3D NULL; + SerialNumberStr =3D NULL; + AssetTagStr =3D NULL; + PartNumberStr =3D NULL; + + ProcessorManu =3D STRING_TOKEN (STR_PROCESSOR_UNKNOWN); + ProcessorVersion =3D STRING_TOKEN (STR_PROCESSOR_UNKNOWN); + SerialNumber =3D STRING_TOKEN (STR_PROCESSOR_UNKNOWN); + AssetTag =3D STRING_TOKEN (STR_PROCESSOR_UNKNOWN); + PartNumber =3D STRING_TOKEN (STR_PROCESSOR_UNKNOWN); + + if (Populated) { + ProcessorManu =3D STRING_TOKEN (STR_PROCESSOR_MANUFACTURE); + ProcessorVersion =3D STRING_TOKEN (STR_PROCESSOR_VERSION); + SerialNumber =3D STRING_TOKEN (STR_PROCESSOR_SERIAL_NUMBER); + AssetTag =3D STRING_TOKEN (STR_PROCESSOR_ASSET_TAG); + PartNumber =3D STRING_TOKEN (STR_PROCESSOR_PART_NUMBER); + + SET_HII_STRING_IF_PCD_NOT_EMPTY(PcdProcessorManufacturer, ProcessorMan= u); + SET_HII_STRING_IF_PCD_NOT_EMPTY(PcdProcessorVersion, ProcessorVersion); + SET_HII_STRING_IF_PCD_NOT_EMPTY(PcdProcessorSerialNumber, SerialNumber= ); + SET_HII_STRING_IF_PCD_NOT_EMPTY(PcdProcessorAssetTag, AssetTag); + SET_HII_STRING_IF_PCD_NOT_EMPTY(PcdProcessorPartNumber, PartNumber); + } + + // Processor Socket Designation + StringBufferSize =3D sizeof (CHAR16) * SMBIOS_STRING_MAX_LENGTH; + ProcessorSocketStr =3D AllocateZeroPool (StringBufferSize); + if (ProcessorSocketStr =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ProcessorSocketStrLen =3D UnicodeSPrint (ProcessorSocketStr, StringBuffe= rSize, + L"CPU%02d", ProcessorIndex + 1); + + // Processor Manufacture + ProcessorManuStr =3D HiiGetPackageString (&gEfiCallerIdGuid, ProcessorMa= nu, NULL); + ProcessorManuStrLen =3D StrLen (ProcessorManuStr); + + // Processor Version + ProcessorVersionStr =3D HiiGetPackageString (&gEfiCallerIdGuid, Processo= rVersion, NULL); + ProcessorVersionStrLen =3D StrLen (ProcessorVersionStr); + + // Serial Number + SerialNumberStr =3D HiiGetPackageString (&gEfiCallerIdGuid, SerialNumber= , NULL); + SerialNumberStrLen =3D StrLen (SerialNumberStr); + + // Asset Tag + AssetTagStr =3D HiiGetPackageString (&gEfiCallerIdGuid, AssetTag, NULL); + AssetTagStrLen =3D StrLen (AssetTagStr); + + // Part Number + PartNumberStr =3D HiiGetPackageString (&gEfiCallerIdGuid, PartNumber, NU= LL); + PartNumberStrLen =3D StrLen (PartNumberStr); + + TotalSize =3D sizeof (SMBIOS_TABLE_TYPE4) + + ProcessorSocketStrLen + 1 + + ProcessorManuStrLen + 1 + + ProcessorVersionStrLen + 1 + + SerialNumberStrLen + 1 + + AssetTagStrLen + 1 + + PartNumberStrLen + 1 + 1; + + *Type4Record =3D AllocateZeroPool (TotalSize); + if (*Type4Record =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto Exit; + } + + CopyMem (*Type4Record, &mSmbiosProcessorTableTemplate, sizeof (SMBIOS_TA= BLE_TYPE4)); + + OptionalStrStart =3D (CHAR8 *)(*Type4Record + 1); + UnicodeStrToAsciiStrS ( + ProcessorSocketStr, + OptionalStrStart, + ProcessorSocketStrLen + 1 + ); + + StrStart =3D OptionalStrStart + ProcessorSocketStrLen + 1; + UnicodeStrToAsciiStrS ( + ProcessorManuStr, + StrStart, + ProcessorManuStrLen + 1 + ); + + StrStart +=3D ProcessorManuStrLen + 1; + UnicodeStrToAsciiStrS ( + ProcessorVersionStr, + StrStart, + ProcessorVersionStrLen + 1 + ); + + StrStart +=3D ProcessorVersionStrLen + 1; + UnicodeStrToAsciiStrS ( + SerialNumberStr, + StrStart, + SerialNumberStrLen + 1 + ); + + StrStart +=3D SerialNumberStrLen + 1; + UnicodeStrToAsciiStrS ( + AssetTagStr, + StrStart, + AssetTagStrLen + 1 + ); + + StrStart +=3D AssetTagStrLen + 1; + UnicodeStrToAsciiStrS ( + PartNumberStr, + StrStart, + PartNumberStrLen + 1 + ); + +Exit: + FreePool (ProcessorSocketStr); + FreePool (ProcessorManuStr); + FreePool (ProcessorVersionStr); + FreePool (SerialNumberStr); + FreePool (AssetTagStr); + FreePool (PartNumberStr); + + return Status; +} + +/** + * Add Type 4 SMBIOS Record for Processor Information. + * + * @param[in] ProcessorNumber Processor number of specified process= or. + * +**/ +EFI_STATUS +AddSmbiosProcessorTypeTable ( + IN UINTN ProcessorIndex + ) +{ + EFI_STATUS Status; + SMBIOS_TABLE_TYPE4 *Type4Record; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_SMBIOS_HANDLE L1CacheHandle; + EFI_SMBIOS_HANDLE L2CacheHandle; + EFI_SMBIOS_HANDLE L3CacheHandle; + UINT8 *LegacyVoltage; + PROCESSOR_STATUS_DATA ProcessorStatus =3D {{0}}; + MISC_PROCESSOR_DATA MiscProcessorData; + BOOLEAN SocketPopulated; + + Type4Record =3D NULL; + + MiscProcessorData.Voltage =3D 0; + MiscProcessorData.CurrentSpeed =3D 0; + MiscProcessorData.CoreCount =3D 0; + MiscProcessorData.CoresEnabled =3D 0; + MiscProcessorData.ThreadCount =3D 0; + L1CacheHandle =3D 0xFFFF; + L2CacheHandle =3D 0xFFFF; + L3CacheHandle =3D 0xFFFF; + + SocketPopulated =3D OemIsSocketPresent(ProcessorIndex); + + Status =3D AllocateType4AndSetProcessorInformationStrings ( + &Type4Record, + ProcessorIndex, + SocketPopulated + ); + if (EFI_ERROR (Status)) { + return Status; + } + + OemGetProcessorInformation (ProcessorIndex, + &ProcessorStatus, + (PROCESSOR_CHARACTERISTIC_FLAGS*) + &Type4Record->ProcessorCharacteristics, + &MiscProcessorData); + + if (SocketPopulated) { + AddSmbiosCacheTypeTable (ProcessorIndex, &L1CacheHandle, + &L2CacheHandle, &L3CacheHandle); + } + + LegacyVoltage =3D (UINT8*)&Type4Record->Voltage; + + *LegacyVoltage =3D MiscProcessorData.Voltage; + Type4Record->CurrentSpeed =3D MiscProcessorData.CurrentSpeed; + Type4Record->MaxSpeed =3D MiscProcessorData.MaxSpeed; + Type4Record->Status =3D ProcessorStatus.Data; + Type4Record->L1CacheHandle =3D L1CacheHandle; + Type4Record->L2CacheHandle =3D L2CacheHandle; + Type4Record->L3CacheHandle =3D L3CacheHandle; + Type4Record->CoreCount =3D MiscProcessorData.CoreCount; + Type4Record->CoreCount2 =3D MiscProcessorData.CoreCount; + Type4Record->EnabledCoreCount =3D MiscProcessorData.CoresEnabled; + Type4Record->EnabledCoreCount2 =3D MiscProcessorData.CoresEnabled; + Type4Record->ThreadCount =3D MiscProcessorData.ThreadCount; + Type4Record->ThreadCount2 =3D MiscProcessorData.ThreadCount; + + Type4Record->CurrentSpeed =3D GetCpuFrequency (ProcessorIndex); + Type4Record->ExternalClock =3D (UINT16)(ArmReadCntFrq () / 1000 /= 1000); + + SetProcessorIdField (Type4Record); + + UINTN MainIdRegister =3D ArmReadMidr (); + if (((MainIdRegister >> 16) & 0xF) < 8) { + Type4Record->ProcessorFamily2 =3D ProcessorFamilyARM; + } else { + if (sizeof (VOID*) =3D=3D 4) { + Type4Record->ProcessorFamily2 =3D ProcessorFamilyARMv7; + } else { + Type4Record->ProcessorFamily2 =3D ProcessorFamilyARMv8; + } + } + + SmbiosHandle =3D SMBIOS_HANDLE_PI_RESERVED; + Status =3D mSmbios->Add (mSmbios, NULL, &SmbiosHandle, (EFI_SMBIOS_TABLE= _HEADER *)Type4Record); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type04 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + FreePool (Type4Record); + + return Status; +} + +/** + * Standard EFI driver point. This driver locates the ProcessorConfigurat= ionData Variable, + * if it exists, add the related SMBIOS tables by PI SMBIOS protocol. + * + * @param ImageHandle Handle for the image of this driver + * @param SystemTable Pointer to the EFI System Table + * + * @retval EFI_SUCCESS The data was successfully stored. + * +**/ +EFI_STATUS +EFIAPI +ProcessorSubClassEntryPoint( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT32 SocketIndex; + + // + // Locate dependent protocols + // + Status =3D gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID**)&= mSmbios); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", Status= )); + return Status; + } + + // + // Add our default strings to the HII database. They will be modified la= ter. + // + mHiiHandle =3D HiiAddPackages (&gEfiCallerIdGuid, + NULL, + ProcessorSubClassStrings, + NULL, + NULL + ); + if (mHiiHandle =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Add SMBIOS tables for populated sockets. + // + for (SocketIndex =3D 0; SocketIndex < OemGetProcessorMaxSockets(); Socke= tIndex++) { + Status =3D AddSmbiosProcessorTypeTable (SocketIndex); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Add Processor Type Table Failed! %r.\n", Stat= us)); + return Status; + } + } + + return Status; +} diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c b/= ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c new file mode 100644 index 000000000000..c9f460f1d5a8 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c @@ -0,0 +1,61 @@ +/** @file + This file provides SMBIOS Misc Type. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent\ + +**/ + +#include "SmbiosMisc.h" + +MISC_SMBIOS_TABLE_EXTERNS (SMBIOS_TABLE_TYPE0, + MiscBiosVendor, + MiscBiosVendor) +MISC_SMBIOS_TABLE_EXTERNS (SMBIOS_TABLE_TYPE1, + MiscSystemManufacturer, + MiscSystemManufacturer) +MISC_SMBIOS_TABLE_EXTERNS (SMBIOS_TABLE_TYPE3, + MiscChassisManufacturer, + MiscChassisManufacturer) +MISC_SMBIOS_TABLE_EXTERNS (SMBIOS_TABLE_TYPE2, + MiscBaseBoardManufacturer, + MiscBaseBoardManufacturer) +MISC_SMBIOS_TABLE_EXTERNS (SMBIOS_TABLE_TYPE13, + MiscNumberOfInstallableLanguages, + MiscNumberOfInstallableLanguages) +MISC_SMBIOS_TABLE_EXTERNS (SMBIOS_TABLE_TYPE32, + MiscBootInformation, + MiscBootInformation) + + +EFI_MISC_SMBIOS_DATA_TABLE mSmbiosMiscDataTable[] =3D { + // Type0 + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBiosVendor, + MiscBiosVendor), + // Type1 + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION (MiscSystemManufacturer, + MiscSystemManufacturer), + // Type3 + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION (MiscChassisManufacturer, + MiscChassisManufacturer), + // Type2 + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBaseBoardManufacturer, + MiscBaseBoardManufacturer), + // Type13 + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION (MiscNumberOfInstallableLangua= ges, + MiscNumberOfInstallableLangua= ges), + // Type32 + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBootInformation, + MiscBootInformation), +}; + + +// +// Number of Data Table entries. +// +UINTN mSmbiosMiscDataTableEntries =3D + (sizeof (mSmbiosMiscDataTable)) / sizeof (EFI_MISC_SMBIOS_DATA_TABLE); diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c b= /ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c new file mode 100644 index 000000000000..d61744fcd8e8 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c @@ -0,0 +1,178 @@ +/** @file + This driver parses the mSmbiosMiscDataTable structure and reports + any generated data using SMBIOS protocol. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + + +EFI_HANDLE mImageHandle; +EFI_HII_HANDLE mHiiHandle; +EFI_SMBIOS_PROTOCOL *mSmbios =3D NULL; + +/** + Standard EFI driver point. This driver parses the mSmbiosMiscDataTable + structure and reports any generated data using SMBIOS protocol. + + @param ImageHandle Handle for the image of this driver + @param SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS The data was successfully stored. + +**/ +EFI_STATUS +EFIAPI +SmbiosMiscEntryPoint( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINTN Index; + EFI_STATUS EfiStatus; + EFI_SMBIOS_PROTOCOL *Smbios; + + mImageHandle =3D ImageHandle; + + EfiStatus =3D gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID*= *)&Smbios); + if (EFI_ERROR (EfiStatus)) { + DEBUG ((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", EfiSta= tus)); + return EfiStatus; + } + + mSmbios =3D Smbios; + + mHiiHandle =3D HiiAddPackages ( + &gEfiCallerIdGuid, + mImageHandle, + SmbiosMiscDxeStrings, + NULL + ); + if (mHiiHandle =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < mSmbiosMiscDataTableEntries; ++Index) { + // + // If the entry have a function pointer, just log the data. + // + if (mSmbiosMiscDataTable[Index].Function !=3D NULL) { + EfiStatus =3D (*mSmbiosMiscDataTable[Index].Function)( + mSmbiosMiscDataTable[Index].RecordData, + Smbios + ); + + if (EFI_ERROR(EfiStatus)) { + DEBUG ((DEBUG_ERROR, "Misc smbios store error. Index=3D%d, Return= Status=3D%r\n", Index, EfiStatus)); + return EfiStatus; + } + } + } + + return EfiStatus; +} + + +/** + Logs SMBIOS record. + + @param Buffer The data for the fixed portion of the SMBI= OS record. The format of the record is + determined by EFI_SMBIOS_TABLE_HEADER.Type= . The size of the formatted area is defined + by EFI_SMBIOS_TABLE_HEADER.Length and eith= er followed by a double-null (0x0000) or + a set of null terminated strings and a nul= l. + @param SmbiosHandle A unique handle will be assigned to the SM= BIOS record. + + @retval EFI_SUCCESS Record was added. + @retval EFI_OUT_OF_RESOURCES Record was not added due to lack of system= resources. + +**/ +EFI_STATUS +LogSmbiosData ( + IN UINT8 *Buffer, + IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle + ) +{ + EFI_STATUS Status; + + *SmbiosHandle =3D SMBIOS_HANDLE_PI_RESERVED; + + Status =3D mSmbios->Add ( + mSmbios, + NULL, + SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *)Buffer + ); + + return Status; +} + + +VOID +GetLinkTypeHandle( + IN UINT8 SmbiosType, + OUT SMBIOS_HANDLE **HandleArray, + OUT UINTN *HandleCount + ) +{ + UINTN Index; + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_SMBIOS_TABLE_HEADER *Record; + + if (mSmbios =3D=3D NULL) { + return; + } + + SmbiosHandle =3D SMBIOS_HANDLE_PI_RESERVED; + *HandleCount =3D 0; + + // Iterate through entries to get the number + while (TRUE) { + Status =3D mSmbios->GetNext ( + mSmbios, + &SmbiosHandle, + &SmbiosType, + &Record, + NULL + ); + + if (!EFI_ERROR (Status)) { + (*HandleCount)++; + } else { + break; + } + } + + *HandleArray =3D AllocateZeroPool (sizeof (SMBIOS_HANDLE) * (*HandleCoun= t)); + if (*HandleArray =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "HandleArray allocate memory resource failed.\n")= ); + *HandleCount =3D 0; + return; + } + + SmbiosHandle =3D SMBIOS_HANDLE_PI_RESERVED; + + for (Index =3D 0; Index < (*HandleCount); Index++) { + Status =3D mSmbios->GetNext ( + mSmbios, + &SmbiosHandle, + &SmbiosType, + &Record, + NULL + ); + + if (!EFI_ERROR (Status)) { + (*HandleArray)[Index] =3D Record->Handle; + } else { + break; + } + } +} + diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorDat= a.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c new file mode 100644 index 000000000000..3b0d907c3996 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c @@ -0,0 +1,92 @@ +/** @file + This file provides Smbios Type0 Data + + Based on the files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE0, MiscBiosVendor) =3D { + { // Hdr + EFI_SMBIOS_TYPE_BIOS_INFORMATION, // Type, + 0, // Length, + 0 // Handle + }, + 1, // Vendor + 2, // BiosVersion + 0xE000, // BiosSegment + 3, // BiosReleaseDate + 0, // BiosSize + { // BiosCharacteristics + 0, // Reserved = :2 + 0, // Unknown = :1 + 0, // BiosCharacteristicsNotSu= pported :1 + 0, // IsaIsSupported = :1 + 0, // McaIsSupported = :1 + 0, // EisaIsSupported = :1 + 1, // PciIsSupported = :1 + 0, // PcmciaIsSupported = :1 + 1, // PlugAndPlayIsSupported = :1 + 0, // ApmIsSupported = :1 + 1, // BiosIsUpgradable = :1 + 1, // BiosShadowingAllowed = :1 + 0, // VlVesaIsSupported = :1 + 0, // EscdSupportIsAvailable = :1 + 1, // BootFromCdIsSupported = :1 + 1, // SelectableBootIsSupporte= d :1 + 0, // RomBiosIsSocketed = :1 + 0, // BootFromPcmciaIsSupporte= d :1 + 1, // EDDSpecificationIsSuppor= ted :1 + 0, // JapaneseNecFloppyIsSuppo= rted :1 + 0, // JapaneseToshibaFloppyIsS= upported :1 + 0, // Floppy525_360IsSupported= :1 + 0, // Floppy525_12IsSupported = :1 + 0, // Floppy35_720IsSupported = :1 + 0, // Floppy35_288IsSupported = :1 + 0, // PrintScreenIsSupported = :1 + 0, // Keyboard8042IsSupported = :1 + 0, // SerialIsSupported = :1 + 0, // PrinterIsSupported = :1 + 0, // CgaMonoIsSupported = :1 + 0, // NecPc98 = :1 + 0 // ReservedForVendor = :32 + }, + + { + 0x03, // BIOSCharacteristicsExt= ensionBytes[0] + // { // BiosReserved + // 1, // AcpiIsSupported = :1 + // 1, // UsbLegacyIsSupport= ed :1 + // 0, // AgpIsSupported = :1 + // 0, // I20BootIsSupported= :1 + // 0, // Ls120BootIsSupport= ed :1 + // 0, // AtapiZipDriveBootI= sSupported :1 + // 0, // Boot1394IsSupporte= d :1 + // 0 // SmartBatteryIsSupp= orted :1 + // }, + 0x0D //BIOSCharacteristicsExte= nsionBytes[1] + // { //SystemReserved + // 1, //BiosBootSpecIsSuppo= rted :1 + // 0, //FunctionKeyNetworkB= ootIsSupported :1 + // 1, //TargetContentDistri= butionEnabled :1 + // 1, //UefiSpecificationSu= pported :1 + // 0, //VirtualMachineSuppo= rted :1 + // 0 //ExtensionByte2Reser= ved :3 + // }, + }, + 0xFF, // SystemBiosMajorRelease; + 0xFF, // SystemBiosMinorRelease; + 0xFF, // EmbeddedControllerFirmwareM= ajorRelease; + 0xFF // EmbeddedControllerFirmwareM= inorRelease; +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFun= ction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFuncti= on.c new file mode 100644 index 000000000000..a502c06e4b46 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c @@ -0,0 +1,263 @@ +/** @file + This driver parses the mMiscSubclassDataTable structure and reports + any generated data to the DataHub. + + Copyright (c) 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" +typedef struct { + CONST CHAR8* MonthStr; + UINT32 MonthInt; +} MONTH_DESCRIPTION; + +MONTH_DESCRIPTION mMonthDescription[] =3D { + { "Jan", 1 }, + { "Feb", 2 }, + { "Mar", 3 }, + { "Apr", 4 }, + { "May", 5 }, + { "Jun", 6 }, + { "Jul", 7 }, + { "Aug", 8 }, + { "Sep", 9 }, + { "Oct", 10 }, + { "Nov", 11 }, + { "Dec", 12 }, + { "???", 1 }, // Use 1 as default month +}; + +/** + * Field Filling Function. Transform an EFI_EXP_BASE2_DATA to a byte, with= '64k' + * as the unit. + * + * @param Value Pointer to Base2_Data + * + * @retval + * +**/ +UINT8 +Base2ToByteWith64KUnit ( + IN UINTN Value + ) +{ + UINT8 Size; + + Size =3D Value / SIZE_64KB + (Value % SIZE_64KB + SIZE_64KB - 1) / SIZE_= 64KB; + + return Size; +} + + +VOID +GetReleaseTime ( + OUT EFI_TIME *Time + ) +{ + CONST CHAR8 *ReleaseDate =3D __DATE__; + CONST CHAR8 *ReleaseTime =3D __TIME__; + UINTN i; + + for (i =3D 0; i < 12; i++) { + if (AsciiStrnCmp (ReleaseDate, mMonthDescription[i].MonthStr, 3) =3D= =3D 0) { + break; + } + } + + Time->Month =3D mMonthDescription[i].MonthInt; + Time->Day =3D AsciiStrDecimalToUintn (ReleaseDate + 4); + Time->Year =3D AsciiStrDecimalToUintn (ReleaseDate + 7); + Time->Hour =3D AsciiStrDecimalToUintn (ReleaseTime); + Time->Minute =3D AsciiStrDecimalToUintn (ReleaseTime + 3); + Time->Second =3D AsciiStrDecimalToUintn (ReleaseTime + 6); +} + +/** + * Fetches the firmware ('BIOS') release date from the + * FirmwareVersionInfo HOB. + * + * @return The release date as a UTF-16 string +**/ +CHAR16 * +GetBiosReleaseDate ( + VOID + ) +{ + CHAR16 *ReleaseDate =3D NULL; + EFI_TIME BuildTime; + + ReleaseDate =3D AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_= LENGTH); + if (ReleaseDate =3D=3D NULL) { + return NULL; + } + + GetReleaseTime (&BuildTime); + + (VOID)UnicodeSPrintAsciiFormat (ReleaseDate, + (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH, + "%02d/%02d/%4d", + BuildTime.Month, + BuildTime.Day, + BuildTime.Year + ); + + return ReleaseDate; +} + +/** + * Fetches the firmware ('BIOS') version from the + * FirmwareVersionInfo HOB. + * + * @return The version as a UTF-16 string +**/ +CHAR16 * +GetBiosVersion ( + VOID + ) +{ + CHAR16 *ReleaseString =3D + (CHAR16 *)FixedPcdGetPtr (PcdFirmwareVersionString); + + return ReleaseString; +} + + +/** + * This function makes boot time changes to the contents of the + * MiscBiosVendor (Type 0). + * + * @param RecordData Pointer to copy of RecordData from t= he Data Table. + * + * @retval EFI_SUCCESS All parameters were valid. + * @retval EFI_UNSUPPORTED Unexpected RecordType value. + * @retval EFI_INVALID_PARAMETER Invalid parameter was found. + * +**/ +MISC_SMBIOS_TABLE_FUNCTION (MiscBiosVendor) +{ + CHAR8 *OptionalStrStart; + CHAR8 *StrStart; + UINTN VendorStrLen; + UINTN VerStrLen; + UINTN DateStrLen; + UINTN BiosPhysicalSizeHexValue; + CHAR16 *Vendor; + CHAR16 *Version; + CHAR16 *ReleaseDate; + CHAR16 *Char16String; + EFI_STATUS Status; + EFI_STRING_ID TokenToUpdate; + EFI_STRING_ID TokenToGet; + SMBIOS_TABLE_TYPE0 *SmbiosRecord; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE0 *InputData; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE0 *)RecordData; + + Vendor =3D (CHAR16 *) PcdGetPtr (PcdFirmwareVendor); + + if (StrLen (Vendor) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BIOS_VENDOR); + HiiSetString (mHiiHandle, TokenToUpdate, Vendor, NULL); + } + + Version =3D GetBiosVersion(); + + if (StrLen (Version) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BIOS_VERSION); + HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); + } else { + Version =3D (CHAR16 *) PcdGetPtr (PcdFirmwareVersionString); + if (StrLen (Version) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BIOS_VERSION); + HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); + } + } + + Char16String =3D GetBiosReleaseDate (); + if (StrLen(Char16String) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE); + HiiSetString (mHiiHandle, TokenToUpdate, Char16String, NULL); + } + + TokenToGet =3D STRING_TOKEN (STR_MISC_BIOS_VENDOR); + Vendor =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + VendorStrLen =3D StrLen (Vendor); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BIOS_VERSION); + Version =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen =3D StrLen (Version); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE); + ReleaseDate =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL= ); + DateStrLen =3D StrLen (ReleaseDate); + + // + // Now update the BiosPhysicalSize + // + BiosPhysicalSizeHexValue =3D FixedPcdGet32 (PcdFdSize); + + // + // Two zeros following the last string. + // + SmbiosRecord =3D AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE0) + VendorS= trLen + 1 + + VerStrLen + 1 + + DateStrLen + 1 + 1); + if (SmbiosRecord =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto Exit; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE0)); + + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE0); + SmbiosRecord->BiosSegment =3D (UINT16)(FixedPcdGet32 (PcdFdBaseAddress) = / SIZE_64KB); + SmbiosRecord->BiosSize =3D Base2ToByteWith64KUnit (BiosPhysicalSizeHexVa= lue) - 1; + + OptionalStrStart =3D (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStrS (Vendor, OptionalStrStart, VendorStrLen + 1); + StrStart =3D OptionalStrStart + VendorStrLen + 1; + UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1); + StrStart +=3D VerStrLen + 1; + UnicodeStrToAsciiStrS (ReleaseDate, StrStart, DateStrLen + 1); + // + // Now we have got the full smbios record, call smbios protocol to add t= his record. + // + Status =3D LogSmbiosData ((UINT8*)SmbiosRecord, &SmbiosHandle); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type00 Table Log Failed! %r = \n", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + +Exit: + if (Vendor !=3D NULL) { + FreePool (Vendor); + } + + if (Version !=3D NULL) { + FreePool (Version); + } + + if (ReleaseDate !=3D NULL) { + FreePool (ReleaseDate); + } + + if (Char16String !=3D NULL) { + FreePool (Char16String); + } + + return Status; +} diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufac= turerData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufa= cturerData.c new file mode 100644 index 000000000000..908ab9164b63 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerDa= ta.c @@ -0,0 +1,35 @@ +/** @file + This file provides Smbios Type1 Data + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) System Manufacturer data. +// +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE1, MiscSystemManufacturer) =3D { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type, + 0, // Length, + 0 // Handle + }, + 1, // Manufacturer + 2, // ProductName + 3, // Version + 4, // SerialNumber + { // Uuid + 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,= 0x00} + }, + SystemWakeupTypePowerSwitch, // SystemWakeupType + 5, // SKUNumber, + 6 // Family +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufac= turerFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemMa= nufacturerFunction.c new file mode 100644 index 000000000000..ee2d5929555f --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFu= nction.c @@ -0,0 +1,173 @@ +/** @file + This driver parses the mMiscSubclassDataTable structure and reports + any generated data to smbios. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + +/** + This function makes boot time changes to the contents of the + MiscSystemManufacturer (Type 1). + + @param RecordData Pointer to copy of RecordData from th= e Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) +{ + CHAR8 *OptionalStrStart; + CHAR8 *StrStart; + UINTN ManuStrLen; + UINTN VerStrLen; + UINTN PdNameStrLen; + UINTN SerialNumStrLen; + UINTN SKUNumStrLen; + UINTN FamilyStrLen; + UINTN RecordLength; + EFI_STRING Manufacturer; + EFI_STRING ProductName; + EFI_STRING Version; + EFI_STRING SerialNumber; + EFI_STRING SKUNumber; + EFI_STRING Family; + EFI_STRING_ID TokenToGet; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE1 *SmbiosRecord; + SMBIOS_TABLE_TYPE1 *InputData; + EFI_STATUS Status; + EFI_STRING_ID TokenToUpdate; + CHAR16 *Product; + CHAR16 *pVersion; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE1 *)RecordData; + + Product =3D (CHAR16 *) PcdGetPtr (PcdSystemProductName); + if (StrLen (Product) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME); + HiiSetString (mHiiHandle, TokenToUpdate, Product, NULL); + } + + pVersion =3D (CHAR16 *) PcdGetPtr (PcdSystemVersion); + if (StrLen (pVersion) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_SYSTEM_VERSION); + HiiSetString (mHiiHandle, TokenToUpdate, pVersion, NULL); + } + UpdateSmbiosInfo (mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBE= R), SerialNumType01); + UpdateSmbiosInfo (mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER= ), SystemManufacturerType01); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER); + Manufacturer =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + ManuStrLen =3D StrLen (Manufacturer); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME); + ProductName =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + PdNameStrLen =3D StrLen (ProductName); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_VERSION); + Version =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen =3D StrLen (Version); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER); + SerialNumber =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, = NULL); + SerialNumStrLen =3D StrLen (SerialNumber); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER); + SKUNumber =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + SKUNumStrLen =3D StrLen (SKUNumber); + + TokenToGet =3D STRING_TOKEN (STR_MISC_SYSTEM_FAMILY); + Family =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + FamilyStrLen =3D StrLen (Family); + + // + // Two zeros following the last string. + // + RecordLength =3D sizeof (SMBIOS_TABLE_TYPE1) + + ManuStrLen + 1 + + PdNameStrLen + 1 + + VerStrLen + 1 + + SerialNumStrLen + 1 + + SKUNumStrLen + 1 + + FamilyStrLen + 1 + 1; + SmbiosRecord =3D AllocateZeroPool (RecordLength); + + if (SmbiosRecord =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto Exit; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE1)); + + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE1); + + SmbiosRecord->Uuid =3D InputData->Uuid; + + OptionalStrStart =3D (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStrS (Manufacturer, OptionalStrStart, ManuStrLen + 1); + StrStart =3D OptionalStrStart + ManuStrLen + 1; + UnicodeStrToAsciiStrS (ProductName, StrStart, PdNameStrLen + 1); + StrStart +=3D PdNameStrLen + 1; + UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1); + StrStart +=3D VerStrLen + 1; + UnicodeStrToAsciiStrS (SerialNumber, StrStart, SerialNumStrLen + 1); + StrStart +=3D SerialNumStrLen + 1; + UnicodeStrToAsciiStrS (SKUNumber, StrStart, SKUNumStrLen + 1); + StrStart +=3D SKUNumStrLen + 1; + UnicodeStrToAsciiStrS (Family, StrStart, FamilyStrLen + 1); + + // + // Now we have got the full smbios record, call smbios protocol to add t= his record. + // + Status =3D LogSmbiosData ((UINT8*)SmbiosRecord, &SmbiosHandle); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type01 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + +Exit: + if (Manufacturer !=3D NULL) { + FreePool (Manufacturer); + } + + if (ProductName !=3D NULL) { + FreePool (ProductName); + } + + if (Version !=3D NULL) { + FreePool (Version); + } + + if (SerialNumber !=3D NULL) { + FreePool (SerialNumber); + } + + if (SKUNumber !=3D NULL) { + FreePool (SKUNumber); + } + + if (Family !=3D NULL) { + FreePool (Family); + } + + return 0; +} diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManu= facturerData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoard= ManufacturerData.c new file mode 100644 index 000000000000..f9122d5d8963 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacture= rData.c @@ -0,0 +1,45 @@ +/** @file + + This file provide OEM to define Smbios Type2 Data + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + +// +// Static (possibly build generated) Chassis Manufacturer data. +// +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE2, MiscBaseBoardManufacturer) =3D { + { // Hdr + EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type, + 0, // Length, + 0 // Handle + }, + 1, // BaseBoardManu= facturer + 2, // BaseBoardProd= uctName + 3, // BaseBoardVers= ion + 4, // BaseBoardSeri= alNumber + 5, // BaseBoardAsse= tTag + { // FeatureFlag + 1, // Motherboard = :1 + 0, // RequiresDaugh= terCard :1 + 0, // Removable = :1 + 1, // Replaceable = :1 + 0, // HotSwappable = :1 + 0 // Reserved = :3 + }, + 6, // BaseBoardChas= sisLocation + 0, // ChassisHandle; + BaseBoardTypeMotherBoard, // BoardType; + 0, // NumberOfConta= inedObjectHandles; + { + 0 + } // ContainedObje= ctHandles[1]; +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManu= facturerFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseB= oardManufacturerFunction.c new file mode 100644 index 000000000000..ce56017281aa --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacture= rFunction.c @@ -0,0 +1,201 @@ +/** @file + This driver parses the mSmbiosMiscDataTable structure and reports + any generated data using SMBIOS protocol. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + + +/** + This function makes basic board manufacturer to the contents of the + Misc Base Board Manufacturer (Type 2). + + @param RecordData Pointer to copy of RecordData from th= e Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscBaseBoardManufacturer) +{ + CHAR8 *OptionalStrStart; + CHAR8 *StrStart; + UINTN RecordLength; + UINTN ManuStrLen; + UINTN ProductNameStrLen; + UINTN VerStrLen; + UINTN SerialNumStrLen; + UINTN AssetTagStrLen; + UINTN ChassisLocaStrLen; + UINTN HandleCount =3D 0; + UINT16 *HandleArray =3D NULL; + CHAR16 *BaseBoardManufacturer; + CHAR16 *BaseBoardProductName; + CHAR16 *Version; + EFI_STRING SerialNumber; + EFI_STRING AssetTag; + EFI_STRING ChassisLocation; + EFI_STRING_ID TokenToGet; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE2 *SmbiosRecord; + SMBIOS_TABLE_TYPE2 *InputData =3D NULL; + EFI_STATUS Status; + + EFI_STRING_ID TokenToUpdate; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE2*)RecordData; + + BaseBoardManufacturer =3D (CHAR16 *) PcdGetPtr (PcdBaseBoardManufacturer= ); + if (StrLen (BaseBoardManufacturer) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER); + HiiSetString (mHiiHandle, TokenToUpdate, BaseBoardManufacturer, NULL); + } + + BaseBoardProductName =3D (CHAR16 *) PcdGetPtr (PcdBaseBoardProductName); + if (StrLen (BaseBoardProductName) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME); + HiiSetString (mHiiHandle, TokenToUpdate, BaseBoardProductName, NULL); + } + + Version =3D (CHAR16 *) PcdGetPtr (PcdBaseBoardVersion); + if (StrLen (Version) > 0) { + TokenToUpdate =3D STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION); + HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); + } + + UpdateSmbiosInfo (mHiiHandle, + STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG), + AssertTagType02 + ); + UpdateSmbiosInfo (mHiiHandle, + STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER), + SerialNumberType02 + ); + UpdateSmbiosInfo (mHiiHandle, + STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER), + BoardManufacturerType02 + ); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER); + BaseBoardManufacturer =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenT= oGet, NULL); + ManuStrLen =3D StrLen (BaseBoardManufacturer); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME); + BaseBoardProductName =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenTo= Get, NULL); + ProductNameStrLen =3D StrLen (BaseBoardProductName); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION); + Version =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen =3D StrLen (Version); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER); + SerialNumber =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + SerialNumStrLen =3D StrLen (SerialNumber); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG); + AssetTag =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + AssetTagStrLen =3D StrLen (AssetTag); + + TokenToGet =3D STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION); + ChassisLocation =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, = NULL); + ChassisLocaStrLen =3D StrLen (ChassisLocation); + + // + // Two zeros following the last string. + // + RecordLength =3D sizeof (SMBIOS_TABLE_TYPE2) + + ManuStrLen + 1 + + ProductNameStrLen + 1 + + VerStrLen + 1 + + SerialNumStrLen + 1 + + AssetTagStrLen + 1 + + ChassisLocaStrLen + 1 + 1; + SmbiosRecord =3D AllocateZeroPool (RecordLength); + if (SmbiosRecord =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto Exit; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE2)); + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE2); + + // + // Update Contained objects Handle + // + SmbiosRecord->NumberOfContainedObjectHandles =3D 0; + GetLinkTypeHandle (EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, &HandleArray, &Hand= leCount); + if (HandleCount > 0) { + SmbiosRecord->ChassisHandle =3D HandleArray[0]; + } + + FreePool (HandleArray); + + OptionalStrStart =3D (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStrS (BaseBoardManufacturer, OptionalStrStart, ManuStrL= en + 1); + + StrStart =3D OptionalStrStart + ManuStrLen + 1; + UnicodeStrToAsciiStrS (BaseBoardProductName, StrStart, ProductNameStrLen= + 1); + + StrStart +=3D ProductNameStrLen + 1; + UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1); + + StrStart +=3D VerStrLen + 1; + UnicodeStrToAsciiStrS (SerialNumber, StrStart, SerialNumStrLen + 1); + + StrStart +=3D SerialNumStrLen + 1; + UnicodeStrToAsciiStrS (AssetTag, StrStart, AssetTagStrLen + 1); + + StrStart +=3D AssetTagStrLen + 1; + UnicodeStrToAsciiStrS (ChassisLocation, StrStart, ChassisLocaStrLen + 1); + + Status =3D LogSmbiosData ((UINT8 *)SmbiosRecord, &SmbiosHandle); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type02 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + +Exit: + if (BaseBoardManufacturer !=3D NULL) { + FreePool (BaseBoardManufacturer); + } + + if (BaseBoardProductName !=3D NULL) { + FreePool (BaseBoardProductName); + } + + if (Version !=3D NULL) { + FreePool (Version); + } + + if (SerialNumber !=3D NULL) { + FreePool (SerialNumber); + } + + if (AssetTag !=3D NULL) { + FreePool (AssetTag); + } + + if (ChassisLocation !=3D NULL) { + FreePool (ChassisLocation); + } + + return 0; +} diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufa= cturerData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManu= facturerData.c new file mode 100644 index 000000000000..2e9e0a391ce5 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerD= ata.c @@ -0,0 +1,51 @@ +/** @file + This file provides Smbios Type3 Data + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) Chassis Manufacturer data. +// +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) =3D { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE , // Type, + 0, // Length, + 0 // Handle + }, + 1, // Manufactrurer + MiscChassisTypeMainServerChassis, // Type + 2, // Version + 3, // SerialNumber + 4, // AssetTag + ChassisStateSafe, // BootupState + ChassisStateSafe, // PowerSupplySt= ate + ChassisStateSafe, // ThermalState + ChassisSecurityStatusNone, // SecurityState + { + 0, // OemDefined[0] + 0, // OemDefined[1] + 0, // OemDefined[2] + 0 // OemDefined[3] + }, + 2, // Height + 1, // NumberofPower= Cords + 0, // ContainedElem= entCount + 0, // ContainedElem= entRecordLength + { // ContainedElem= ents[0] + { + 0, // ContainedEl= ementType + 0, // ContainedEl= ementMinimum + 0 // ContainedEl= ementMaximum + } + } +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufa= cturerFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassis= ManufacturerFunction.c new file mode 100644 index 000000000000..69029c8532f6 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerF= unction.c @@ -0,0 +1,200 @@ +/** @file + This driver parses the mMiscSubclassDataTable structure and reports + any generated data to smbios. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + +UINT8 +GetChassisType ( + VOID + ) +{ + EFI_STATUS Status; + UINT8 ChassisType; + + Status =3D OemGetChassisType (&ChassisType); + if (EFI_ERROR (Status)) { + return 0; + } + + return ChassisType; +} + +/** + This function makes boot time changes to the contents of the + MiscChassisManufacturer (Type 3). + + @param RecordData Pointer to copy of RecordData from th= e Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscChassisManufacturer) +{ + CHAR8 *OptionalStrStart; + CHAR8 *StrStart; + UINTN RecordLength; + UINTN ManuStrLen; + UINTN VerStrLen; + UINTN AssertTagStrLen; + UINTN SerialNumStrLen; + UINTN ChaNumStrLen; + EFI_STRING Manufacturer; + EFI_STRING Version; + EFI_STRING SerialNumber; + EFI_STRING AssertTag; + EFI_STRING ChassisSkuNumber; + EFI_STRING_ID TokenToGet; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE3 *SmbiosRecord; + SMBIOS_TABLE_TYPE3 *InputData; + EFI_STATUS Status; + + UINT8 ContainedElementCount; + CONTAINED_ELEMENT ContainedElements =3D {0}; + UINT8 ExtendLength =3D 0; + + UINT8 ChassisType; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE3 *)RecordData; + + UpdateSmbiosInfo ( + mHiiHandle, + STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG), + AssetTagType03 + ); + UpdateSmbiosInfo ( + mHiiHandle, + STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER), + SerialNumberType03 + ); + UpdateSmbiosInfo ( + mHiiHandle, + STRING_TOKEN (STR_MISC_CHASSIS_VERSION), + VersionType03 + ); + UpdateSmbiosInfo ( + mHiiHandle, + STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER), + ManufacturerType03 + ); + + TokenToGet =3D STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER); + Manufacturer =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + ManuStrLen =3D StrLen (Manufacturer); + + TokenToGet =3D STRING_TOKEN (STR_MISC_CHASSIS_VERSION); + Version =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen =3D StrLen (Version); + + TokenToGet =3D STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER); + SerialNumber =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NUL= L); + SerialNumStrLen =3D StrLen (SerialNumber); + + TokenToGet =3D STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG); + AssertTag =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL); + AssertTagStrLen =3D StrLen (AssertTag); + + TokenToGet =3D STRING_TOKEN (STR_MISC_CHASSIS_SKU_NUMBER); + ChassisSkuNumber =3D HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet,= NULL); + ChaNumStrLen =3D StrLen (ChassisSkuNumber); + + ContainedElementCount =3D InputData->ContainedElementCount; + + if (ContainedElementCount > 1) { + ExtendLength =3D (ContainedElementCount - 1) * sizeof (CONTAINED_ELEME= NT); + } + + // + // Two zeros following the last string. + // + RecordLength =3D sizeof (SMBIOS_TABLE_TYPE3) + + ExtendLength + 1 + + ManuStrLen + 1 + + VerStrLen + 1 + + SerialNumStrLen + 1 + + AssertTagStrLen + 1 + + ChaNumStrLen + 1 + 1; + SmbiosRecord =3D AllocateZeroPool (RecordLength); + if (SmbiosRecord =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto Exit; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE3)); + + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength = + 1; + + ChassisType =3D GetChassisType (); + if (ChassisType !=3D 0) { + SmbiosRecord->Type =3D ChassisType; + } + + //ContainedElements + (VOID)CopyMem (SmbiosRecord + 1, &ContainedElements, ExtendLength); + + //ChassisSkuNumber + *((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength) = =3D 5; + + OptionalStrStart =3D (CHAR8 *)((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TA= BLE_TYPE3) + ExtendLength + 1); + UnicodeStrToAsciiStrS (Manufacturer, OptionalStrStart, ManuStrLen + 1); + StrStart =3D OptionalStrStart + ManuStrLen + 1; + UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1); + StrStart +=3D VerStrLen + 1; + UnicodeStrToAsciiStrS (SerialNumber, StrStart, SerialNumStrLen + 1); + StrStart +=3D SerialNumStrLen + 1; + UnicodeStrToAsciiStrS (AssertTag, StrStart, AssertTagStrLen + 1); + StrStart +=3D AssertTagStrLen + 1; + UnicodeStrToAsciiStrS (ChassisSkuNumber, StrStart, ChaNumStrLen + 1); + // + // Now we have got the full smbios record, call smbios protocol to add t= his record. + // + Status =3D LogSmbiosData ((UINT8*)SmbiosRecord, &SmbiosHandle); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type03 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + +Exit: + if (Manufacturer !=3D NULL) { + FreePool (Manufacturer); + } + + if (Version !=3D NULL) { + FreePool (Version); + } + + if (SerialNumber !=3D NULL) { + FreePool (SerialNumber); + } + + if (AssertTag !=3D NULL) { + FreePool (AssertTag); + } + + if (ChassisSkuNumber !=3D NULL) { + FreePool (ChassisSkuNumber); + } + + return 0; +} diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInsta= llableLanguagesData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNu= mberOfInstallableLanguagesData.c new file mode 100644 index 000000000000..67a35408b700 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableL= anguagesData.c @@ -0,0 +1,32 @@ +/** @file + This file provides Smbios Type13 Data + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + +// +// Static (possibly build generated) Bios Vendor data. +// + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguag= es) =3D +{ + { // Hdr + EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // Type, + 0, // Length, + 0 // Handle + }, + 0, // InstallableLang= uages + 0, // Flags + { + 0 // Reserved[15] + }, + 1 // CurrentLanguage +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInsta= llableLanguagesFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/Mi= scNumberOfInstallableLanguagesFunction.c new file mode 100644 index 000000000000..297203427150 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableL= anguagesFunction.c @@ -0,0 +1,154 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + +/** + Get next language from language code list (with separator ';'). + + @param LangCode Input: point to first language in the list. On + Otput: point to next language in the list, or + NULL if no more language in the list. + @param Lang The first language in the list. + +**/ +VOID +EFIAPI +GetNextLanguage ( + IN OUT CHAR8 **LangCode, + OUT CHAR8 *Lang + ) +{ + UINTN Index; + CHAR8 *StringPtr; + + if (LangCode =3D=3D NULL || *LangCode =3D=3D NULL || Lang =3D=3D NULL) { + return; + } + + Index =3D 0; + StringPtr =3D *LangCode; + while (StringPtr[Index] !=3D 0 && StringPtr[Index] !=3D ';') { + Index++; + } + + (VOID)CopyMem (Lang, StringPtr, Index); + Lang[Index] =3D 0; + + if (StringPtr[Index] =3D=3D ';') { + Index++; + } + *LangCode =3D StringPtr + Index; +} + +/** + This function returns the number of supported languages on HiiHandle. + + @param HiiHandle The HII package list handle. + + @retval The number of supported languages. + +**/ +UINT16 +EFIAPI +GetSupportedLanguageNumber ( + IN EFI_HII_HANDLE HiiHandle + ) +{ + CHAR8 *Lang; + CHAR8 *Languages; + CHAR8 *LanguageString; + UINT16 LangNumber; + + Languages =3D HiiGetSupportedLanguages (HiiHandle); + if (Languages =3D=3D NULL) { + return 0; + } + + LangNumber =3D 0; + Lang =3D AllocatePool (AsciiStrSize (Languages)); + if (Lang !=3D NULL) { + LanguageString =3D Languages; + while (*LanguageString !=3D 0) { + GetNextLanguage (&LanguageString, Lang); + LangNumber++; + } + FreePool (Lang); + } + FreePool (Languages); + return LangNumber; +} + + +/** + This function makes boot time changes to the contents of the + MiscNumberOfInstallableLanguages (Type 13). + + @param RecordData Pointer to copy of RecordData from th= e Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscNumberOfInstallableLanguages) +{ + UINTN LangStrLen; + CHAR8 CurrentLang[SMBIOS_STRING_MAX_= LENGTH + 1]; + CHAR8 *OptionalStrStart; + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE13 *SmbiosRecord; + SMBIOS_TABLE_TYPE13 *InputData =3D NULL;; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE13 *)RecordData; + + InputData->InstallableLanguages =3D GetSupportedLanguageNumber (mHiiHand= le); + + // + // Try to check if current langcode matches with the langcodes in instal= led languages + // + ZeroMem (CurrentLang, SMBIOS_STRING_MAX_LENGTH - 1); + (VOID)AsciiStrCpyS (CurrentLang, SMBIOS_STRING_MAX_LENGTH - 1, "en|US|is= o8859-1"); + LangStrLen =3D AsciiStrLen (CurrentLang); + + // + // Two zeros following the last string. + // + SmbiosRecord =3D AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE13) + LangSt= rLen + 1 + 1); + if (SmbiosRecord =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE13)); + + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE13); + + OptionalStrStart =3D (CHAR8 *)(SmbiosRecord + 1); + (VOID)AsciiStrCpyS (OptionalStrStart, SMBIOS_STRING_MAX_LENGTH - 1, Curr= entLang); + // + // Now we have got the full smbios record, call smbios protocol to add t= his record. + // + Status =3D LogSmbiosData ((UINT8*)SmbiosRecord, &SmbiosHandle); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type13 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + return Status; +} diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformati= onData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformation= Data.c new file mode 100644 index 000000000000..e72656d3b002 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c @@ -0,0 +1,34 @@ +/** @file + This driver parses the mMiscSubclassDataTable structure and reports + any generated data to the DataHub. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE32, MiscBootInformation) =3D { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type, + 0, // Length, + 0 // Handle + }, + { // Reserved[6] + 0, + 0, + 0, + 0, + 0, + 0 + }, + BootInformationStatusNoError // BootInformation= Status +}; diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformati= onFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInforma= tionFunction.c new file mode 100644 index 000000000000..db91385f6e5d --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunct= ion.c @@ -0,0 +1,67 @@ +/** @file + boot information boot time changes. + SMBIOS type 32. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosMisc.h" + +/** + This function makes boot time changes to the contents of the + MiscBootInformation (Type 32). + + @param RecordData Pointer to copy of RecordData from th= e Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ + +MISC_SMBIOS_TABLE_FUNCTION(MiscBootInformation) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE32 *SmbiosRecord; + SMBIOS_TABLE_TYPE32 *InputData; + + // + // First check for invalid parameters. + // + if (RecordData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + InputData =3D (SMBIOS_TABLE_TYPE32 *)RecordData; + + // + // Two zeros following the last string. + // + SmbiosRecord =3D AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1); + if (SmbiosRecord =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE32)); + + SmbiosRecord->Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE32); + + // + // Now we have got the full smbios record, call smbios protocol to add t= his record. + // + Status =3D LogSmbiosData ((UINT8*)SmbiosRecord, &SmbiosHandle); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type32 Table Log Failed! %r \n= ", + __FUNCTION__, __LINE__, Status)); + } + + FreePool (SmbiosRecord); + return Status; +} diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass= Strings.uni b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClas= sStrings.uni new file mode 100644 index 000000000000..17da6178e88f --- /dev/null +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings= .uni @@ -0,0 +1,23 @@ +/** @file + SMBIOS Type 4 strings + + Copyright (c) 2015, Hisilicon Limited. All rights reserved. + Copyright (c) 2015, Linaro Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +#langdef en-US "English" + +// +// Processor Information +// +#string STR_PROCESSOR_SOCKET_DESIGNATION #language en-US "Not Specifie= d" +#string STR_PROCESSOR_MANUFACTURE #language en-US "Not Specifie= d" +#string STR_PROCESSOR_VERSION #language en-US "Not Specifie= d" +#string STR_PROCESSOR_SERIAL_NUMBER #language en-US "Not Specifie= d" +#string STR_PROCESSOR_ASSET_TAG #language en-US "Not Specifie= d" +#string STR_PROCESSOR_PART_NUMBER #language en-US "Not Specifie= d" +#string STR_PROCESSOR_UNKNOWN #language en-US "Unknown" diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscLibStrings.uni= b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscLibStrings.uni new file mode 100644 index 000000000000..32f30b41566d --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscLibStrings.uni @@ -0,0 +1,21 @@ +/** @file + * Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + * + * Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ * Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ * Copyright (c) 2015, Linaro Limited. All rights reserved.
+ * SPDX-License-Identifier: BSD-2-Clause-Patent + * + * +**/ + + +/=3D# + +#langdef en-US "English" + +#include "Type00/MiscBiosVendor.uni" +#include "Type01/MiscSystemManufacturer.uni" +#include "Type02/MiscBaseBoardManufacturer.uni" +#include "Type03/MiscChassisManufacturer.uni" +#include "Type13/MiscNumberOfInstallableLanguages.uni" diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.un= i b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni new file mode 100644 index 000000000000..ba981e3db391 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni @@ -0,0 +1,17 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +#string STR_MISC_BIOS_VENDOR #language en-US "Not Specified" +#string STR_MISC_BIOS_VERSION #language en-US "Not Specified" +#string STR_MISC_BIOS_RELEASE_DATE #language en-US "Not Specified" +#string STR_MISC_BIOS_VENDOR #language en-US "Not Specified" +#string STR_MISC_BIOS_RELEASE_DATE #language en-US "12/02/2020" diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufac= turer.uni b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufact= urer.uni new file mode 100644 index 000000000000..9d723ba684b8 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.u= ni @@ -0,0 +1,20 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +#string STR_MISC_SYSTEM_MANUFACTURER #language en-US "Not Specified" +#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "Not Specified" +#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "Not Specified" +#string STR_MISC_SYSTEM_VERSION #language en-US "Not Specified" +#string STR_MISC_SYSTEM_VERSION #language en-US "Not Specified" +#string STR_MISC_SYSTEM_SERIAL_NUMBER #language en-US "Not Specified" +#string STR_MISC_SYSTEM_SKU_NUMBER #language en-US "Not Specified" +#string STR_MISC_SYSTEM_FAMILY #language en-US "Not Specified" diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManu= facturer.uni b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardMa= nufacturer.uni new file mode 100644 index 000000000000..47b6c71230fe --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacture= r.uni @@ -0,0 +1,20 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +#string STR_MISC_BASE_BOARD_MANUFACTURER #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_PRODUCT_NAME #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_PRODUCT_NAME #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_VERSION #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_VERSION #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_SERIAL_NUMBER #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_ASSET_TAG #language en-US "Not Specifi= ed" +#string STR_MISC_BASE_BOARD_CHASSIS_LOCATION #language en-US "Not Specifi= ed" diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufa= cturer.uni b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufa= cturer.uni new file mode 100644 index 000000000000..dacb195bff28 --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.= uni @@ -0,0 +1,17 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +#string STR_MISC_CHASSIS_MANUFACTURER #language en-US "Not Specified" +#string STR_MISC_CHASSIS_VERSION #language en-US "Not Specified" +#string STR_MISC_CHASSIS_SERIAL_NUMBER #language en-US "Not Specified" +#string STR_MISC_CHASSIS_ASSET_TAG #language en-US "Not Specified" +#string STR_MISC_CHASSIS_SKU_NUMBER #language en-US "Not Specified" diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInsta= llableLanguages.uni b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumb= erOfInstallableLanguages.uni new file mode 100644 index 000000000000..0b61b0cd179f --- /dev/null +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableL= anguages.uni @@ -0,0 +1,42 @@ +/** @file + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=3D# + +/=3D# +// +// Language String (Long Format) +// +#string STR_MISC_BIOS_LANGUAGES_ENG_LONG #language en-US "en|US|is= o8859-1" +#string STR_MISC_BIOS_LANGUAGES_FRA_LONG #language en-US "fr|CA|is= o8859-1" +#string STR_MISC_BIOS_LANGUAGES_CHN_LONG #language en-US "zh|TW|un= icode" +#string STR_MISC_BIOS_LANGUAGES_JPN_LONG #language en-US "ja|JP|un= icode" +#string STR_MISC_BIOS_LANGUAGES_ITA_LONG #language en-US "it|IT|is= o8859-1" +#string STR_MISC_BIOS_LANGUAGES_SPA_LONG #language en-US "es|ES|is= o8859-1" +#string STR_MISC_BIOS_LANGUAGES_GER_LONG #language en-US "de|DE|is= o8859-1" +#string STR_MISC_BIOS_LANGUAGES_POR_LONG #language en-US "pt|PT|is= o8859-1" + + +// +// Language String (Abbreviated Format) +// +#string STR_MISC_BIOS_LANGUAGES_ENG_ABBREVIATE #language en-US "enUS" +#string STR_MISC_BIOS_LANGUAGES_FRA_ABBREVIATE #language en-US "frCA" +#string STR_MISC_BIOS_LANGUAGES_CHN_ABBREVIATE #language en-US "zhTW" +#string STR_MISC_BIOS_LANGUAGES_JPN_ABBREVIATE #language en-US "jaJP" +#string STR_MISC_BIOS_LANGUAGES_ITA_ABBREVIATE #language en-US "itIT" +#string STR_MISC_BIOS_LANGUAGES_SPA_ABBREVIATE #language en-US "esES" +#string STR_MISC_BIOS_LANGUAGES_GER_ABBREVIATE #language en-US "deDE" +#string STR_MISC_BIOS_LANGUAGES_POR_ABBREVIATE #language en-US "ptPT" + +#string STR_MISC_BIOS_LANGUAGES_SIMPLECH_ABBREVIATE #language en-US "zhC= N" +#string STR_MISC_BIOS_LANGUAGES_SIMPLECH_LONG #language en-US "zh|= CN|unicode" + + --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#68396): https://edk2.groups.io/g/devel/message/68396 Mute This Topic: https://groups.io/mt/78784077/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-