From nobody Tue Feb 10 01:30:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+68098+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68098+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1606782874; cv=none; d=zohomail.com; s=zohoarc; b=MGf4RFI+/lniUaaj1BdXwVj/JqznQZenJWwmaEf0FZzLm/zAYhFoPHYM9kcWt5XfnjkPv8WjD0W3gH8BobP8qomnnVIgqvTd7GBywDSm3pmFE2jHHBkHtarmIMUb7HfHAC7R0Duehkrg26DBBPrcZnNeOYza+rFmROlXmJ4E9pQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606782874; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Mu0zWAnf59cT/zrtbqPgrAZOLOLFv68uq03YO4gYDK4=; b=BM4KjyOLVm8hSQ6OEKeLgQPx36wxivcFxoW8SkfkVRqV2XcLmxshc81VVWLa1jUvv8noUNDMNamN3+Fp6F/Ksa4woVx+gOCHZZLZklbtXuB6IFxP+XSMqYNF04vVLopJmfr6murcOHOStSynFVutYXGpbD/odX/J8a9Y6ZGj1dM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+68098+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1606782874329296.41021690261744; Mon, 30 Nov 2020 16:34:34 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id e1WKYY1788612xWVXeA0cerx; Mon, 30 Nov 2020 16:34:34 -0800 X-Received: from mail-pj1-f65.google.com (mail-pj1-f65.google.com [209.85.216.65]) by mx.groups.io with SMTP id smtpd.web12.3075.1606782868636295854 for ; Mon, 30 Nov 2020 16:34:28 -0800 X-Received: by mail-pj1-f65.google.com with SMTP id r20so154915pjp.1 for ; Mon, 30 Nov 2020 16:34:28 -0800 (PST) X-Gm-Message-State: EszHxWUYqGmsYTWjl6mZExdxx1787277AA= X-Google-Smtp-Source: ABdhPJxxQyeKyxXbpewSg8+ybFjZ23rB6siTmbtp64MjQKvBKcBlAPOVgKdLRApuMAuJC6AMWGt7Zw== X-Received: by 2002:a17:90a:62c3:: with SMTP id k3mr7889pjs.24.1606782867819; Mon, 30 Nov 2020 16:34:27 -0800 (PST) X-Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 22sm57899pjb.40.2020.11.30.16.34.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 16:34:27 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [PATCH v4 03/11] ArmPkg: Add register encoding definition for MMFR2 Date: Mon, 30 Nov 2020 17:33:50 -0700 Message-Id: <20201201003358.8780-4-rebecca@nuviainc.com> In-Reply-To: <20201201003358.8780-1-rebecca@nuviainc.com> References: <20201201003358.8780-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1606782874; bh=ou1Lo6lsLjGcMDPoEJ+cQ7WrhxCmwEOP9DxM4S9rHWk=; h=Cc:Date:From:Reply-To:Subject:To; b=H7z42Lcmcn4qcVPBrXKNjisPr2WrRdQz4ZXFxvsG6t25VRlErIlcnufsF1v/YfLorIV YSfkxzcr9PVIjfskvnS7Duf3brKVRQdrVZeMRoZ/4Ij19FT83UBYH12g31GOy5zhQR1WK 3TwJ4pS+QDB2dHmyEmSAdSH+cP9OoU6QN64= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add register encoding definition for Memory Model Feature Register 2. We need to define it here because we build for ARMv8.0, which doesn't have it. Signed-off-by: Rebecca Cran --- ArmPkg/Include/Chipset/AArch64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArc= h64.h index 0ade5cce91c3..7c2b592f92ee 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -112,6 +112,10 @@ #define ARM_VECTOR_LOW_A32_FIQ 0x700 #define ARM_VECTOR_LOW_A32_SERR 0x780 =20 +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we +// build for ARMv8.0, we need to define the register here. +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + #define VECTOR_BASE(tbl) \ .section .text.##tbl##,"ax"; \ .align 11; \ --=20 2.26.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#68098): https://edk2.groups.io/g/devel/message/68098 Mute This Topic: https://groups.io/mt/78622911/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-