From nobody Sun Apr 28 23:24:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+67027+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+67027+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1604549165; cv=none; d=zohomail.com; s=zohoarc; b=l6pmyXKRbZgiQgUgK4mJsbo9t5zTFOcapfugS5Y0DSdtZHlCZZPOicEx8sOaiDBGu2Tk/jqJKQTyz1EXs7QhKCj3brR0GE1z93cMmEdawRI5/LYmvgc4Xk43H94pfoJXntzxvGmcpXg2yxcdp8WCSevU6YbKavAILlvyub+Lu58= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604549165; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=u199N/x4zg9e7hOXQ72dW/b5Sh7o81XW6EJBXB9gutY=; b=JxbLJqjLlpum+2X4Ev588Pd9JDEaf62EAtmg7WNuzi6w+tSt3xjev+7HNTclTzz2K7OpXQsp3oNOU0egIJW7m2aLhG01oWpknG/DM71NDRS7Lwmi5b35KW++1qmhCPBGW7z4l5vrhIbLoPeUeo7HjEL39i5zk95n4eV3gBqGCcA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+67027+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1604549165145763.0384381492194; Wed, 4 Nov 2020 20:06:05 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id GPpqYY1788612x2lnuYj6AE9; Wed, 04 Nov 2020 20:06:04 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.2975.1604549163748739726 for ; Wed, 04 Nov 2020 20:06:03 -0800 IronPort-SDR: oQdkYhnKSW8gAK7jq/uKxjwQDB6nWvbekJpIhDeFp/l2OgoUv1pk0cC3aeq0U44pghQBcRuu1o pgDMbsm+ZYSQ== X-IronPort-AV: E=McAfee;i="6000,8403,9795"; a="165816571" X-IronPort-AV: E=Sophos;i="5.77,452,1596524400"; d="scan'208";a="165816571" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2020 20:06:00 -0800 IronPort-SDR: kjYLxm9z1/XuMndDWEPatEuwOmk21J+3GhRlUpztIgaffA4gGyf5lqtqyYocu7o0R8kkIildi6 HyWZUzDZWPdA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,452,1596524400"; d="scan'208";a="321050836" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.46]) by orsmga003.jf.intel.com with ESMTP; 04 Nov 2020 20:05:58 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar , Jiewen Yao Subject: [edk2-devel] [PATCH v5 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo Date: Thu, 5 Nov 2020 12:05:40 +0800 Message-Id: <20201105040541.23428-2-w.sheng@intel.com> In-Reply-To: <20201105040541.23428-1-w.sheng@intel.com> References: <20201105040541.23428-1-w.sheng@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: MH6igfuFOlO1mVGf2aimjqEyx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1604549164; bh=OVFl1zn29nN9O9DHke8EVj6rajfUSNOO/VV5tYSatOY=; h=Cc:Date:From:Reply-To:Subject:To; b=VWCiVL+6FG+QcOgI4YsAx3H3TBo5XpjoSbACFIcdol0IvsZ3dncR/qylQryfzRAyjxz lUzNSGfH9dv0y4fezut/0Yw03Y2eXNvTp9m05Sv9zWai62CRjErgzyLZjHcnotwVD5Mfj S0yLUWgV4qvfOgUGo+8PU3BPZWLSSIVOnxs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Change the variable name from mInternalGr3 to mInternalCr3. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3015 Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Jiewen Yao --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index ebfc46ad45..d67f036aea 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -32,7 +32,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64}, }; =20 -UINTN mInternalGr3; +UINTN mInternalCr3; =20 /** Set the internal page table base address. @@ -46,7 +46,7 @@ SetPageTableBase ( IN UINTN Cr3 ) { - mInternalGr3 =3D Cr3; + mInternalCr3 =3D Cr3; } =20 /** @@ -59,8 +59,8 @@ GetPageTableBase ( VOID ) { - if (mInternalGr3 !=3D 0) { - return mInternalGr3; + if (mInternalCr3 !=3D 0) { + return mInternalCr3; } return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); } @@ -252,7 +252,7 @@ ConvertPageEntryAttribute ( if ((Attributes & EFI_MEMORY_RO) !=3D 0) { if (IsSet) { NewPageEntry &=3D ~(UINT64)IA32_PG_RW; - if (mInternalGr3 !=3D 0) { + if (mInternalCr3 !=3D 0) { // Environment setup // ReadOnly page need set Dirty bit for shadow stack NewPageEntry |=3D IA32_PG_D; --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#67027): https://edk2.groups.io/g/devel/message/67027 Mute This Topic: https://groups.io/mt/78044936/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+67025+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+67025+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1604549164; cv=none; d=zohomail.com; s=zohoarc; b=GMBKoWcjPabWWO3wa0yTTuC172iasVmhG7DDzJEKV0Zv2Lgu4v4igWkNUluP/HasTY2W3EjBRlOR4gOzYx0mOvsXBft0GdK98XPQbHQ9ZGHet5laIjkeQNVYY5o/b029kA8hDHH9i9zo5HoI0xbcNhjl1EQ/2Dl3STZQhi8RpDc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604549164; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=a5HgLbtdzG58sXwhbj8tdK6TYILBIABxSAuHU0dcTv4=; b=fdZZRRAl63R2PhbI02aOtVm/RrHSL0Rrl92OugXZW9p2NwkGZFej6wU7XbFCfWe8mnLdawBsSRwl9pKlLk1JQy1hEgf4QA5rYoStY4VjWVSSAbfG9cxmcGN6xRLWke/NocvpILuOdxPh5BxWmo9ntROCqcitHAaCHJVnl1go3/Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+67025+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1604549164320548.5431587551562; Wed, 4 Nov 2020 20:06:04 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id FzgDYY1788612x89a5KozuzS; Wed, 04 Nov 2020 20:06:03 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web09.2971.1604549163082339270 for ; Wed, 04 Nov 2020 20:06:03 -0800 IronPort-SDR: aQy9vQoOx9c8swJA/UdFblz5Vcy4TFPK6g7lCVaEqrHwLJqt/8HK7rONZYzwugHofGIEBIF86O TkTFf+3LEQIw== X-IronPort-AV: E=McAfee;i="6000,8403,9795"; a="165816575" X-IronPort-AV: E=Sophos;i="5.77,452,1596524400"; d="scan'208";a="165816575" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2020 20:06:01 -0800 IronPort-SDR: GvVCqJ4XXYG/oddKaPiT4C2ciNLCdAkJ805CBWyuS+JfZ/xYM4HtE2n/1axiV+Ps+FwvevRF1C /o3kobL/dH0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,452,1596524400"; d="scan'208";a="321050847" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.46]) by orsmga003.jf.intel.com with ESMTP; 04 Nov 2020 20:06:00 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar , Jiewen Yao Subject: [edk2-devel] [PATCH v5 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Return level paging type for Internal CR3 Date: Thu, 5 Nov 2020 12:05:41 +0800 Message-Id: <20201105040541.23428-3-w.sheng@intel.com> In-Reply-To: <20201105040541.23428-1-w.sheng@intel.com> References: <20201105040541.23428-1-w.sheng@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: uc2jDP4f8g2jHawAIBm1V3kyx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1604549163; bh=v7PfzbizT7N72Lg4HeaJbNCsOyJGRUB3VXJmTMBP4GY=; h=Cc:Date:From:Reply-To:Subject:To; b=Xa0tZNG1rgT7uCdTuFw+Q+wymKrsQh/cjjq5cgaYtaC4i4unlrACBLvevA0K80pRqf5 8ym3YNeU5/fJ6OA0i6rMy3SP1vYR7q9OPGLRZCzfGljREPibOjxqkgSzx/950y13ENc76 ywxIr8R0t3npkD9dRHdL4FW4Fjb2J/B+6wc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If mInternalCr3 is non zero, it will use the page table from mInternalCr3. And it will use mInternalIs5LevelPaging to reflect the paging type. If mInternalCr3 is zero, it will use the page table from CR3, and reflect the paging type by CR4 LA57 bit. This patch is a bug fix when enable CET feature with 5 level paging. The page table of SMM shadows shack memory is generated in PiCpuSmmEntry(). This page table is not set to CR3 in PiCpuSmmEntry(), it is only for SMI entry. When CET feature is enabled, we need to set some attributes for SMM shadows shack memory in PiCpuSmmEntry(). We set this page table to mInternalCr3 for update the memory attribute. The CR4 LA57 bit does not reflect the paging type of mInternalCr3, so we need to use a virable (mInternalIs5LevelPaging) to reflect if mInternalCr3 is 5 level paging or 4 level paging. We also use the same function to update the memory attribue with the page table in CR3, use CR4 LA57 bit to reflect the paging type of CR3. So we need to use GetPageTableBase() and Is5LevelPageTableBase() to return the page table and its paging type for GetPageTableEntry() when set the memory attribute. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3015 Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Jiewen Yao --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 10 +++++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 47 ++++++++++++++++++= ++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 2 + 3 files changed, 56 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 7fb3a2d9e4..3eb6af62a7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -951,6 +951,16 @@ GetPageTableBase ( VOID ); =20 +/** + This function set the internal page table type to 5 level paging or 4 le= vel paging. + + @param Is5LevelPaging TRUE means 5 level paging. FALSE means 4 level pag= ing. +**/ +VOID +SetPageTableType ( + IN BOOLEAN Is5LevelPaging + ); + /** This function sets the attributes for the memory region specified by Bas= eAddress and Length from their current attributes to the attributes specified by Attr= ibutes. diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index d67f036aea..800394afc7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -33,6 +33,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { }; =20 UINTN mInternalCr3; +BOOLEAN mInternalIs5LevelPaging =3D FALSE; =20 /** Set the internal page table base address. @@ -65,6 +66,48 @@ GetPageTableBase ( return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); } =20 +/** + This function set the internal page table type to 5 level paging or 4 le= vel paging. + + @param Is5LevelPaging TRUE means 5 level paging. FALSE means 4 level pag= ing. +**/ +VOID +SetPageTableType ( + IN BOOLEAN Is5LevelPaging + ) +{ + mInternalIs5LevelPaging =3D Is5LevelPaging; +} + +/** + Return if the page table is 5 level paging. + + @return TRUE The page table base is 5 level paging. + @return FALSE The page table base is 4 level paging. +**/ +STATIC +BOOLEAN +Is5LevelPageTableBase ( + VOID + ) +{ + IA32_CR4 Cr4; + + // + // If mInternalCr3 is non zero, it will use the page table from mInterna= lCr3. + // And it will use mInternalIs5LevelPaging to reflect the paging type. + // + if (mInternalCr3 !=3D 0) { + return mInternalIs5LevelPaging; + } + + // + // If use page table from CR3, reflect the paging type by CR4 LA57 bit. + // + Cr4.UintN =3D AsmReadCr4 (); + return (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1); +} + /** Return length according to page attributes. =20 @@ -131,7 +174,6 @@ GetPageTableEntry ( UINT64 *L3PageTable; UINT64 *L4PageTable; UINT64 *L5PageTable; - IA32_CR4 Cr4; BOOLEAN Enable5LevelPaging; =20 Index5 =3D ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK; @@ -140,8 +182,7 @@ GetPageTableEntry ( Index2 =3D ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK; Index1 =3D ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK; =20 - Cr4.UintN =3D AsmReadCr4 (); - Enable5LevelPaging =3D (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1); + Enable5LevelPaging =3D Is5LevelPageTableBase (); =20 if (sizeof(UINTN) =3D=3D sizeof(UINT64)) { if (Enable5LevelPaging) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 810985df20..64f796e0d5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -387,6 +387,8 @@ SmmInitPageTable ( SetSubEntriesNum (Pml4Entry, 3); PTEntry =3D Pml4Entry; =20 + SetPageTableType (m5LevelPagingNeeded); + if (m5LevelPagingNeeded) { // // Fill PML5 entry --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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