This patch is a bug fix when enable CET feature with 5 level paging.
The page table of SMM shadows shack memory is generated in PiCpuSmmEntry().
This page table is not set to CR3 in PiCpuSmmEntry(), it is only for
SMI entry. When CET feature is enabled, we need to set some attributes for
SMM shadows shack memory in PiCpuSmmEntry().
We set this page table to mInternalCr3 for update the memory attribute.
The CR4 LA57 bit does not reflect the paging type of mInternalCr3,
so we need to use a virable (mInternalIs5LevelPaging) to reflect if
mInternalCr3 is 5 level paging or 4 level paging.
We also use the same function to update the memory attribue with the
page table in CR3, use CR4 LA57 bit to reflect the paging type of CR3.
So we need to use GetPageTableBase() and Is5LevelPageTableBase() to return
the page table and its paging type for GetPageTableEntry() when set the
memory attribute.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Sheng Wei (2):
UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo
UefiCpuPkg/PiSmmCpuDxeSmm: Return level paging type for Internal CR3
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 10 ++++
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 57 +++++++++++++++++++---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 2 +
3 files changed, 61 insertions(+), 8 deletions(-)
--
2.16.2.windows.1
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