From nobody Sat May 11 06:50:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+66905+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+66905+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1604377815; cv=none; d=zohomail.com; s=zohoarc; b=U7m1HPiBj1sHOHERjm4SQAhQi6q9KlquVh2lqQmXO68HBsjphdnnwLtu1raO3ErS87/U6aZh5Fwz8EcRvzNucUuzIn2hv5VmRtion0hGnlbjOGe6zfJmkqqSlEqS9LGPvwQ/b+9NpwITtmfJ7ybLNdaY+pDHFXhINYiImEpwSto= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604377815; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=Qv7H/I9LY5MGB3VuVO4YSKJ/3nfUGj2iLfvprYkz5hw=; b=j5qFLSfte7C5HUv1dfcIR/SqiIWtWFjICM0oljSOhhv13Qe2v7MQggSo5eAZ25TGntdLX9F/LO3KRuMFlKL/aQkNP8cfclXa6BEJT7RlfAVZB5dQojIGvQ32nTt/U5CKIHHaqTJyYBv3x/SiCNfTxFtnDDTXFDvxm1klEWz0wBE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+66905+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1604377815657297.4756007105842; Mon, 2 Nov 2020 20:30:15 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id uMqgYY1788612xmNiRnF4S7h; Mon, 02 Nov 2020 20:30:15 -0800 X-Received: from mga05.intel.com (mga05.intel.com []) by mx.groups.io with SMTP id smtpd.web11.57.1604377813420333081 for ; Mon, 02 Nov 2020 20:30:14 -0800 IronPort-SDR: b7k+3vPtN4titAD9tJ7wGXC/chbNjxCDFAzCcfNHKY1zZ49sCzS9qT2DA+nTHxbU3px8TLqBHS mFCk3mjBAwhA== X-IronPort-AV: E=McAfee;i="6000,8403,9793"; a="253706056" X-IronPort-AV: E=Sophos;i="5.77,446,1596524400"; d="scan'208";a="253706056" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2020 20:30:14 -0800 IronPort-SDR: w0Jv3EafKaVnQ092Wdcy7jKhRjoQySYTElj50nSDcj1BSECpr/1vb7LuLhTcSwlDoDEF4YWdcS cvQW39CxFD2g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,446,1596524400"; d="scan'208";a="470640375" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.46]) by orsmga004.jf.intel.com with ESMTP; 02 Nov 2020 20:30:12 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar , Jiewen Yao Subject: [edk2-devel] [PATCH v4 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo Date: Tue, 3 Nov 2020 12:30:07 +0800 Message-Id: <20201103043008.26536-2-w.sheng@intel.com> In-Reply-To: <20201103043008.26536-1-w.sheng@intel.com> References: <20201103043008.26536-1-w.sheng@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: 5DNpqoWJTWUDphaQvrqVygMHx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1604377815; bh=KLVZk493q3vhBY/dtE2e1dbnV79QQvNzgBAFYX7e4FE=; h=Cc:Date:From:Reply-To:Subject:To; b=lmpGPlzpnTgkUt/vLgtuu0BA62HK+WGDl+eyQhdbaermrF4ATncd7uokBNoXSHjqvcH ca5DvDIutO5t+nwr9AKrvMGLmc3sEJNiUHqkVwuqRBLmC/wHzKyk6QdU0iOYI+dhICory +R19qJZM8Tpywc0qeVXD+AFZwI8h0g5KqOY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Change the variable name from mInternalGr3 to mInternalCr3. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3015 Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Jiewen Yao Reviewed-by: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index ebfc46ad45..d67f036aea 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -32,7 +32,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64}, }; =20 -UINTN mInternalGr3; +UINTN mInternalCr3; =20 /** Set the internal page table base address. @@ -46,7 +46,7 @@ SetPageTableBase ( IN UINTN Cr3 ) { - mInternalGr3 =3D Cr3; + mInternalCr3 =3D Cr3; } =20 /** @@ -59,8 +59,8 @@ GetPageTableBase ( VOID ) { - if (mInternalGr3 !=3D 0) { - return mInternalGr3; + if (mInternalCr3 !=3D 0) { + return mInternalCr3; } return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); } @@ -252,7 +252,7 @@ ConvertPageEntryAttribute ( if ((Attributes & EFI_MEMORY_RO) !=3D 0) { if (IsSet) { NewPageEntry &=3D ~(UINT64)IA32_PG_RW; - if (mInternalGr3 !=3D 0) { + if (mInternalCr3 !=3D 0) { // Environment setup // ReadOnly page need set Dirty bit for shadow stack NewPageEntry |=3D IA32_PG_D; --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#66905): https://edk2.groups.io/g/devel/message/66905 Mute This Topic: https://groups.io/mt/78000109/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 11 06:50:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+66906+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+66906+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1604377822; cv=none; d=zohomail.com; s=zohoarc; b=MQETss25IcEFS8xFWvhRjKiGWLgTdqMQykY61mndkCL4BX9fMU/q3GYpRQxXNDpEOhIRHghMUqMXmzBdJmEXNdeOg2xxKX3mGxAuE/tN22bGbxLPYGc9MKLdDbEU78UIIa3hob7NytmGbRfhl7DhfwaOx3qe5Ez4Qy0F1ehse0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604377822; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=NiWwWRiAbuKxnyjtnY+gkgiAmpMWQaAb6KaeuCtePGU=; b=ZNm2Uwo2LC95gWqOt0tXbCF+7D3JGlcu3xYrNj6W6zePt3qhpgT51knTTtXwH89QY7XjnnQyg1H9OKC4e3uJYQRErhhQp1Zes/JvrebwbT/VbrbSfasSwL0yyFeiIh9K8jPcJ4CikDct912rpfkojfdWmGGXD1yISmfYuuNGfXo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+66906+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1604377822800728.006743999668; Mon, 2 Nov 2020 20:30:22 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id FEpQYY1788612xVODAsGQGo4; Mon, 02 Nov 2020 20:30:22 -0800 X-Received: from mga05.intel.com (mga05.intel.com []) by mx.groups.io with SMTP id smtpd.web11.57.1604377813420333081 for ; Mon, 02 Nov 2020 20:30:16 -0800 IronPort-SDR: vhSoJgN/tejYLdLhMWv/VmF2Rtk8KDwwAoekYleTp7/L5pd7XFt9r2hVpsceCWY4FP6St/vyMp N+EJN063tiuw== X-IronPort-AV: E=McAfee;i="6000,8403,9793"; a="253706074" X-IronPort-AV: E=Sophos;i="5.77,446,1596524400"; d="scan'208";a="253706074" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2020 20:30:16 -0800 IronPort-SDR: QzNoOgGjXIM9cGR6H9QJjSB9pY6/yDZuBolp24573brxQNCgyp2tq0iXfdQhVXrdggk/43FEGi ie1T10owkWnw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,446,1596524400"; d="scan'208";a="470640380" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.46]) by orsmga004.jf.intel.com with ESMTP; 02 Nov 2020 20:30:14 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar , Jiewen Yao Subject: [edk2-devel] [PATCH v4 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Return level paging type for Internal CR3 Date: Tue, 3 Nov 2020 12:30:08 +0800 Message-Id: <20201103043008.26536-3-w.sheng@intel.com> In-Reply-To: <20201103043008.26536-1-w.sheng@intel.com> References: <20201103043008.26536-1-w.sheng@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: ld3vKQkKJjFW4oClOeMOncnPx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1604377822; bh=puMfc3vhNtaRtNAOQkxhpFiJtFqumwaKet5eLahZJtI=; h=Cc:Date:From:Reply-To:Subject:To; b=bcpjvcCZn769KDVIfgooxXCyP0iDNb4MPKLbg4EWYs4PKwAMu4UAe/SD0YvqEHdyKuE 1N04nfsuiu4qY8ILpe1T5e0+IzIuoMLL3jTCjrqU/LyQ8pS9Nxrayczyg2YtbnurWgnae 8ZFebc2H+fZWwnP5zFkNg+ZDLwywPW7wtSk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If mInternalCr3 is non zero, it will use the page table from mInternalCr3. And it will use mInternalIs5LevelPaging to reflect the page table type. If use page table from CR3, reflect the page table type by CR4 LA57 bit. It is a fix for enable CET feature with 5 level paging. PiCpuSmmEntry() will generate the page table of SMM shack memory. If CET feature is enabled, it also includes the SMM shadows shack memory. And we need to set some attributes on SMM shadows shack memory in PiCpuSmmEntry() when CET feature is enabled. Since the page table of SMM shack memory is used in SMI entry, and it does = not set to CR3 in PiCpuSmmEntry(). We use mInternalCr3 as page table root when PiCpuSmmEntry() calls ConvertMemoryPageAttributes(). We need to use mInternalIs5LevelPaging determining whether 5-level paging is enabled or n= ot. If mInternalCr3 is zero, ConvertMemoryPageAttributes() will use the page ta= ble in CR3, and refects the page table type by CR4 LA57 bit. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3015 Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Jiewen Yao --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 10 +++++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 43 ++++++++++++++++++= ++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 2 + 3 files changed, 52 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 7fb3a2d9e4..3eb6af62a7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -951,6 +951,16 @@ GetPageTableBase ( VOID ); =20 +/** + This function set the internal page table type to 5 level paging or 4 le= vel paging. + + @param Is5LevelPaging TRUE means 5 level paging. FALSE means 4 level pag= ing. +**/ +VOID +SetPageTableType ( + IN BOOLEAN Is5LevelPaging + ); + /** This function sets the attributes for the memory region specified by Bas= eAddress and Length from their current attributes to the attributes specified by Attr= ibutes. diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index d67f036aea..890782a394 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -33,6 +33,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { }; =20 UINTN mInternalCr3; +BOOLEAN mInternalIs5LevelPaging =3D FALSE; =20 /** Set the internal page table base address. @@ -65,6 +66,44 @@ GetPageTableBase ( return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); } =20 +/** + This function set the internal page table type to 5 level paging or 4 le= vel paging. + + @param Is5LevelPaging TRUE means 5 level paging. FALSE means 4 level pag= ing. +**/ +VOID +SetPageTableType ( + IN BOOLEAN Is5LevelPaging + ) +{ + mInternalIs5LevelPaging =3D Is5LevelPaging; +} + +/** + Return if the page table is 5 level paging. + + @return TRUE The page table base is 5 level paging. + @return FALSE The page table base is 4 level paging. +**/ +STATIC +BOOLEAN +Is5LevelPageTableBase ( + VOID + ) +{ + IA32_CR4 Cr4; + + // If mInternalCr3 is non zero, it will use the page table from mInterna= lCr3. + // And it will use mInternalIs5LevelPaging to reflect the page table typ= e. + if (mInternalCr3 !=3D 0) { + return mInternalIs5LevelPaging; + } + + // If use page table from CR3, reflect the page table type by CR4 LA57 b= it. + Cr4.UintN =3D AsmReadCr4 (); + return (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1); +} + /** Return length according to page attributes. =20 @@ -131,7 +170,6 @@ GetPageTableEntry ( UINT64 *L3PageTable; UINT64 *L4PageTable; UINT64 *L5PageTable; - IA32_CR4 Cr4; BOOLEAN Enable5LevelPaging; =20 Index5 =3D ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK; @@ -140,8 +178,7 @@ GetPageTableEntry ( Index2 =3D ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK; Index1 =3D ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK; =20 - Cr4.UintN =3D AsmReadCr4 (); - Enable5LevelPaging =3D (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1); + Enable5LevelPaging =3D Is5LevelPageTableBase(); =20 if (sizeof(UINTN) =3D=3D sizeof(UINT64)) { if (Enable5LevelPaging) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 810985df20..6f2f4adb7d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -387,6 +387,8 @@ SmmInitPageTable ( SetSubEntriesNum (Pml4Entry, 3); PTEntry =3D Pml4Entry; =20 + SetPageTableType(m5LevelPagingNeeded); + if (m5LevelPagingNeeded) { // // Fill PML5 entry --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#66906): https://edk2.groups.io/g/devel/message/66906 Mute This Topic: https://groups.io/mt/78000110/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-