From nobody Sun May 5 02:54:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+66554+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+66554+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1603423921; cv=none; d=zohomail.com; s=zohoarc; b=PJtoda7Z/Y1cyiCgZ8BWORrefBtU9F1VRCu/qq7xAc8ICaPAIiQQyAt4zKOMJ8SHcPYVmcdujRuOTj6t8uWs1qTMe3CAhTtiQ4+8eRiRBLYx5ZaaR+ISJESjY3y4T5WRnLtOuMFd7jd4kczCOi0UkOR9oFYPiojAGtc5yTaXSWM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603423921; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=0mJj+lwovJLb4wSKV9f2eg6LobfvXGkuy89Jmlb+/KU=; b=WkuOkUolY/h8M39tfOYjbEVM8eHcWxWfwVL/7W5OroVcShdXwK3mqCMIqeFpf1yGNec0k4A8fsqZkz9IGxTab1hxQYqC9jRAfxVcQZAunjtTw154ThRaLE0NeFgcaJvnJy2DJs0MOVVZvOy8gX7ZPaMEYXQt2gLGnXLz/U3s/HA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+66554+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1603423921611134.40192534096423; Thu, 22 Oct 2020 20:32:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id qnd1YY1788612x8uUgRoXxbG; Thu, 22 Oct 2020 20:32:01 -0700 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.3650.1603423920725014836 for ; Thu, 22 Oct 2020 20:32:00 -0700 IronPort-SDR: aHLvvnJYSgS+8sAB1dsuzoyovvE8avn3PkQgCUT6omMi53xe1ZUwrJ8CzC9PHzZh+fG9U8lALS 7oAqvVcvCFeA== X-IronPort-AV: E=McAfee;i="6000,8403,9782"; a="165032493" X-IronPort-AV: E=Sophos;i="5.77,404,1596524400"; d="scan'208";a="165032493" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2020 20:31:59 -0700 IronPort-SDR: 8nktjgAJa4ghlWy0inihcli3LWrkJRi/Bxt11TSeiTWPu7+ZwH9hkuqSCzEZWVz6oZ5VPHrBEA cl4QWm9uHvtQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,404,1596524400"; d="scan'208";a="523362345" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.46]) by fmsmga006.fm.intel.com with ESMTP; 22 Oct 2020 20:31:56 -0700 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar , Jiewen Yao Subject: [edk2-devel] [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Adjust level paging type for Internal CR3 Date: Fri, 23 Oct 2020 11:31:53 +0800 Message-Id: <20201023033153.21360-1-w.sheng@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: D8GGznLfbAJqmzyem8KfmXAOx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1603423921; bh=S3PMFFqNdS9j1e28soXue0KD3rAMBIvd2rYiQozbD7g=; h=Cc:Date:From:Reply-To:Subject:To; b=fMIoIPoIyYkmYmQElnRBhnCK1ymFcjwFnXghhRxsJNY5reQrwl5vCTLooLhTlqnylkT qrAktMFqdLAV8cZgkXuHUYeBHHd992fcj32+T1clDlGGvfWK4wVeCDHgFEw/STAW8V+uX 7M1WOIuKVLJWWe8Cv6ZYdUWVlO0+aScgod0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When mInternalCr3 is used, get paging level type by a variable which is set when mInternalCr3 is generated. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3015 Change-Id: I1295d671a6c01c0a077e4b79fa83d500d49ef29c Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Jiewen Yao --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 41 ++++++++++++++++++= +++++++++++++++-------- 1 file changed, 33 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index ebfc46ad45..3264c72af2 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -32,7 +32,12 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64}, }; =20 -UINTN mInternalGr3; +UINTN mInternalCr3; + +// +// Variables from Protected Mode SMI Entry Template +// +extern BOOLEAN gSmmFeatureEnable5LevelPaging; =20 /** Set the internal page table base address. @@ -46,7 +51,7 @@ SetPageTableBase ( IN UINTN Cr3 ) { - mInternalGr3 =3D Cr3; + mInternalCr3 =3D Cr3; } =20 /** @@ -59,12 +64,34 @@ GetPageTableBase ( VOID ) { - if (mInternalGr3 !=3D 0) { - return mInternalGr3; + if (mInternalCr3 !=3D 0) { + return mInternalCr3; } return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); } =20 +/** + Return if the page table base is 5 level paging. + + @return TRUE The page table base is 5 level paging. + @return FALSE The page table base is 4 level paging. +**/ +STATIC +BOOLEAN +Is5LevelPageTableBase ( + VOID + ) +{ + IA32_CR4 Cr4; + + if (mInternalCr3 !=3D 0) { + return gSmmFeatureEnable5LevelPaging; + } + + Cr4.UintN =3D AsmReadCr4 (); + return (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1); +} + /** Return length according to page attributes. =20 @@ -131,7 +158,6 @@ GetPageTableEntry ( UINT64 *L3PageTable; UINT64 *L4PageTable; UINT64 *L5PageTable; - IA32_CR4 Cr4; BOOLEAN Enable5LevelPaging; =20 Index5 =3D ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK; @@ -140,8 +166,7 @@ GetPageTableEntry ( Index2 =3D ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK; Index1 =3D ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK; =20 - Cr4.UintN =3D AsmReadCr4 (); - Enable5LevelPaging =3D (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1); + Enable5LevelPaging =3D Is5LevelPageTableBase(); =20 if (sizeof(UINTN) =3D=3D sizeof(UINT64)) { if (Enable5LevelPaging) { @@ -252,7 +277,7 @@ ConvertPageEntryAttribute ( if ((Attributes & EFI_MEMORY_RO) !=3D 0) { if (IsSet) { NewPageEntry &=3D ~(UINT64)IA32_PG_RW; - if (mInternalGr3 !=3D 0) { + if (mInternalCr3 !=3D 0) { // Environment setup // ReadOnly page need set Dirty bit for shadow stack NewPageEntry |=3D IA32_PG_D; --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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