From nobody Wed May 8 21:02:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+66541+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+66541+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1603381821; cv=none; d=zohomail.com; s=zohoarc; b=UDXSG6rVi6FA4tB31SGbaciBNMFe7fbTH+95GaC6WdNHerCkXyjBVuNhBgpSrsuABdm2764HUKjRkKQKViRqTZ68LKATYomyBE5tJ/SOCgkdsY6kaLR4Wj/FOSLLlf5BcDtnPbTJSnxyn9oJlixHoFmBsUN68TZBKu8tBtgHAuU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603381821; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jUgLdomruncVg06bt+uS467hx37wS7C0S+JmQhr86gY=; b=ASedYnSZgiKB8GxH3gxj5DaHBox5Lpx8JbbhY2GD357SAJ2VPHUoxH7A+yM0Sb1PMeN/JdBmD+AzBOSj37qBrwfxvEEG5sBl5Up1UtfxdZUBWrCzj368f0kuXpe9ZMJxGT+jLwCc2+hDljV92xadcbFEc0d5qKf4Wv8/U7miWe4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+66541+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1603381821826709.1440491278099; Thu, 22 Oct 2020 08:50:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9x9XYY1788612xSfEk2zGjvB; Thu, 22 Oct 2020 08:50:21 -0700 X-Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by mx.groups.io with SMTP id smtpd.web10.734.1603381820331052855 for ; Thu, 22 Oct 2020 08:50:20 -0700 X-Received: by mail-wr1-f66.google.com with SMTP id s9so3038837wro.8 for ; Thu, 22 Oct 2020 08:50:20 -0700 (PDT) X-Gm-Message-State: u9lV0PN8q9t3KXPySinUTaiox1787277AA= X-Google-Smtp-Source: ABdhPJypjW4gHMXp3l0dbOJHL1t+U28XfxcmAWGqjkQbimQq8fWxv9FxWnpSCfOZLhGLS1kzifnq4w== X-Received: by 2002:a5d:5612:: with SMTP id l18mr3631255wrv.372.1603381818641; Thu, 22 Oct 2020 08:50:18 -0700 (PDT) X-Received: from white-rabbit.sw.nuviainc.com ([2.30.51.167]) by smtp.gmail.com with ESMTPSA id 133sm4377342wmb.2.2020.10.22.08.50.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 08:50:18 -0700 (PDT) From: "Tomas Pilar (tpilar)" To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Tanmay Jagdale Subject: [edk2-devel] [edk2-platform][PATCH 1/3] Silicon/Qemu: Renumber Dynamic PCDs to leave a gap Date: Thu, 22 Oct 2020 16:50:14 +0100 Message-Id: <20201022155016.228362-2-tomas@nuviateam.com> In-Reply-To: <20201022155016.228362-1-tomas@nuviateam.com> References: <20201022155016.228362-1-tomas@nuviateam.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tomas@nuviateam.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1603381821; bh=HSoTadY9Nsqzo5z8HDlu92CVvJsTR+4+kg1FTgWaYHs=; h=Cc:Date:From:Reply-To:Subject:To; b=s10EyDOr6RiQbMqnQbj8PrARXbUv+2oebEK79ObJSqwaQYXv5gR0MhpJgltdckMCo6X 23oDHZCUxj06gkbEdEg0xNHlHjGCWdT4lYtm9Rnl0lxKahiCKGWTCQ8nxffqiEgd9Auls Cki5mJB6hjyUmbk7xPZvCB+RuQb2ZkThyjk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" It is useful to have the PCDs of same type to be numbered close together and thus a gap should be left between PCDs of different types. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Tanmay Jagdale Signed-off-by: Tomas Pilar Reviewed-by: Leif Lindholm --- Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/Sbs= aQemu.dec index ed87d15de0..e8d55a530d 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -37,5 +37,5 @@ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x100000= 00000|UINT64|0x00000005 =20 [PcdsDynamic.common] - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000006 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x0000= 0007 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000100 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x0000= 0101 --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#66541): https://edk2.groups.io/g/devel/message/66541 Mute This Topic: https://groups.io/mt/77733004/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 8 21:02:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+66542+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+66542+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1603381822; cv=none; d=zohomail.com; s=zohoarc; b=ilF8Wmyt9ucYfB7I4lRYdDF1p4/fcwXQ2rhxuhOW2XQRW/536AiTT31mnUkNVZRfGCBh9AsrcBDSA9LQ6Ab6KV/8nFC3+xtJLXGgefoORRTVCauUEcglX0gUUaheakVLAuuslLpbtMS822JbOWT9uo4X19HfbdC8SuHSYz68+aU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603381822; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=iaBkcMni27/dICrbY4NLBEuo8OfaHRql2b+HbNlYTyM=; b=kCIXR2K8hRYO5XuE9gNt1XToc7Aop7u+F562f9+FLjgUL+5Q8a3vaRAHR+EG/MU+0FS3hGSyD9a93dhY3oJ6WWmyCS6dlQLfGHrfa7D/vuCuZpXV5RGU9GBWwndQqFUjE21qWdzA22sh8V/eJLdjLXJuNlWHYLKagi7op2TOgBk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+66542+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1603381822691592.72611098124; Thu, 22 Oct 2020 08:50:22 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id g4JPYY1788612xRSiEY8su8O; Thu, 22 Oct 2020 08:50:22 -0700 X-Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.groups.io with SMTP id smtpd.web11.721.1603381821121537465 for ; Thu, 22 Oct 2020 08:50:21 -0700 X-Received: by mail-wr1-f54.google.com with SMTP id y12so3050774wrp.6 for ; Thu, 22 Oct 2020 08:50:20 -0700 (PDT) X-Gm-Message-State: B8zLZrgCX6NBECCXFvboBZnjx1787277AA= X-Google-Smtp-Source: ABdhPJw/D68/VNluyYpAVL7zpHB/Q6BQU1N//srTqNCPpvBgTCSouhrCL2QpjIhvKLLy3wMfYi+iRw== X-Received: by 2002:adf:f2c1:: with SMTP id d1mr3632928wrp.179.1603381819492; Thu, 22 Oct 2020 08:50:19 -0700 (PDT) X-Received: from white-rabbit.sw.nuviainc.com ([2.30.51.167]) by smtp.gmail.com with ESMTPSA id 133sm4377342wmb.2.2020.10.22.08.50.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 08:50:19 -0700 (PDT) From: "Tomas Pilar (tpilar)" To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Tanmay Jagdale Subject: [edk2-devel] [edk2-platform][PATCH 2/3] Platform,Silicon/Qemu: Define PcdPcie*Limit variables Date: Thu, 22 Oct 2020 16:50:15 +0100 Message-Id: <20201022155016.228362-3-tomas@nuviateam.com> In-Reply-To: <20201022155016.228362-1-tomas@nuviateam.com> References: <20201022155016.228362-1-tomas@nuviateam.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tomas@nuviateam.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1603381822; bh=p1u3oczDO0YPqqY9/YohMjZvpNyKEidSmPkbcgjWiA4=; h=Cc:Date:From:Reply-To:Subject:To; b=SjweX9k0Rg+olCqWXkyQrf0yVoK8sou28q/UsPjJbaC0FtDTb3j1IjLtjN/iym6xDhf ZRDN8b8LU19Lp54bOCJ6eG2o0jTJm8Z9Xw5q+mvwS8eMzT1aWlsyi2shvGmZh/wk+zkOF udVxacSWAHjtxuwMplDZcL3FOKB5TR+NLYo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The ACPI tables require not only the base and the size of various PCIe memory windows, but also the limit defined as Limit =3D Base + Size - 1 Given that ASL does not permit basic constant arithmetics when defining resources or passing arguements to functions, we define PCDs that hold these limits. The PCDs can then be modified individually in platform DSC files. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Tanmay Jagdale Signed-off-by: Tomas Pilar Reviewed-by: Leif Lindholm --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 ++++++ Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 11 +++++++++++ 2 files changed, 17 insertions(+) diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/S= bsaQemu.dsc index 0e6d738bee..49bc5033f4 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -458,15 +458,21 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE gArmTokenSpaceGuid.PcdPciBusMax|255 gArmTokenSpaceGuid.PcdPciIoBase|0x0 gArmTokenSpaceGuid.PcdPciIoSize|0x00010000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x0000ffff gArmTokenSpaceGuid.PcdPciMmio32Base|0x80000000 gArmTokenSpaceGuid.PcdPciMmio32Size|0x70000000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFFFFFFF gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000 gArmTokenSpaceGuid.PcdPciMmio64Size|0xFF00000000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFFFFFFFFFF =20 # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this # PCD and PcdPciDisableBusEnumeration have not been assigned yet # TODO: PcdPciExpressBaseAddress set to max_uint64 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xf0000000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF + gArmTokenSpaceGuid.PcdPciIoTranslation|0x7fff0000 gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0 gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0 diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/Sbs= aQemu.dec index e8d55a530d..476dc82f98 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -36,6 +36,17 @@ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x10000|UINT3= 2|0x00000004 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x100000= 00000|UINT64|0x00000005 =20 + # PCDs complementing PCIe layout pulled into ACPI tables + # Limit =3D Base + Size - 1 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x0000ffff|UINT32|0= x00000006 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFFFFFFF|UINT= 32|0x00000007 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFFFFFFFFFF|UI= NT64|0x00000008 + + # PCDs complementing gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + # BarLimit =3D BaseAddress + BarSize - 1 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000|U= INT64|0x00000009 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF|= UINT64|0x00000010 + [PcdsDynamic.common] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000100 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x0000= 0101 --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#66542): https://edk2.groups.io/g/devel/message/66542 Mute This Topic: https://groups.io/mt/77733006/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 8 21:02:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+66543+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+66543+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1603381823; cv=none; d=zohomail.com; s=zohoarc; b=hyajXKNAeKNL26uRne8aAOt7YHGXTlbXvhvlFqV905gogUYDnux9UGEyD//arwi6h7Z6oHz+BWUQDtRvQ0/m648LbJkBso/nT40SePAacL4K67eKs7WEL1EaGFO5zs9pDlfIqMf/RyOn2uhXBAnN2Msz2NXH/akPuptxNcJeK3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603381823; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=5e71MufhKFMrY53oBnu3woAewh0g2e357bc+A6ufLKE=; b=QlKyWA/tQSby+pKJnKzMfKzHPlphhAXBrAYjFEG5k6UxJhbMf+wq1IDeQauwvfL/6lS5Oo7g9TYonbo/ae6umoMeCQJMHUdzQwdT3CuaGxoR1e8HSgyEcvQgjvPiRuLaJXEYsllh04ag2gLjRwvOfFA5ZEljKqG/IwKU3k1umog= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+66543+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 160338182313521.732546908352788; Thu, 22 Oct 2020 08:50:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id UtNWYY1788612xniTNpu1ebo; Thu, 22 Oct 2020 08:50:22 -0700 X-Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.groups.io with SMTP id smtpd.web08.788.1603381821925683222 for ; Thu, 22 Oct 2020 08:50:22 -0700 X-Received: by mail-wr1-f50.google.com with SMTP id x7so3057854wrl.3 for ; Thu, 22 Oct 2020 08:50:21 -0700 (PDT) X-Gm-Message-State: 9LrMkw3WM4aD4NCatLXOrFyax1787277AA= X-Google-Smtp-Source: ABdhPJwEEOPYfKFcin0pe5NrjFSDbWpQcupSq0PtrwBS2nQE8NZlugDKWtaFdWy/3VHmPjOvC34WkA== X-Received: by 2002:adf:e54b:: with SMTP id z11mr3642112wrm.128.1603381820244; Thu, 22 Oct 2020 08:50:20 -0700 (PDT) X-Received: from white-rabbit.sw.nuviainc.com ([2.30.51.167]) by smtp.gmail.com with ESMTPSA id 133sm4377342wmb.2.2020.10.22.08.50.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 08:50:19 -0700 (PDT) From: "Tomas Pilar (tpilar)" To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Tanmay Jagdale Subject: [edk2-devel] [edk2-platform][PATCH 3/3] Silicon/Qemu: Use PCDs to AcpiTables lib Date: Thu, 22 Oct 2020 16:50:16 +0100 Message-Id: <20201022155016.228362-4-tomas@nuviateam.com> In-Reply-To: <20201022155016.228362-1-tomas@nuviateam.com> References: <20201022155016.228362-1-tomas@nuviateam.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tomas@nuviateam.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1603381822; bh=0fRYE/yDm/Ej7hIQ7RJ2Y6GOpdqAHYRdR609q22LB+k=; h=Cc:Date:From:Reply-To:Subject:To; b=gsN7fyHyTWEhVE4K+6j+y/FuCGl1MzPzhOHJxO3a6LpRhBquRk7GLMbpkBik4dl+bgk HNsi4nlgChHXtLg3EqsZhoZYN7WyThWUurgvBrgJ41sRiJORXcDAPlJmkYhtCgb5UQR7k yIAZxe9eTr2X1COEKcFIZmmgYTqsW1QZGPI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The ACPI Tables providing library AcpiTables.inf uses a lot of information that is available in the form of PCDs for differnt platforms. This patch replaces hardcoded values describing the PCIe, AHCI, EHCI, and Serial with the appropriate PCDs. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Tanmay Jagdale Signed-off-by: Tomas Pilar Reviewed-by: Leif Lindholm --- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 29 ++++++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc | 6 +- Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 58 ++++++++++--------- Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 6 +- Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc | 2 +- .../Include/IndustryStandard/SbsaQemuAcpi.h | 6 -- 6 files changed, 68 insertions(+), 39 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu= /SbsaQemu/AcpiTables/AcpiTables.inf index 766e448836..9be34488eb 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -45,3 +45,32 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax + + gArmTokenSpaceGuid.PcdPciIoBase + gArmTokenSpaceGuid.PcdPciIoSize + gArmTokenSpaceGuid.PcdPciIoTranslation + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit + + gArmTokenSpaceGuid.PcdPciMmio32Base + gArmTokenSpaceGuid.PcdPciMmio32Size + gArmTokenSpaceGuid.PcdPciMmio32Translation + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit + + gArmTokenSpaceGuid.PcdPciMmio64Base + gArmTokenSpaceGuid.PcdPciMmio64Size + gArmTokenSpaceGuid.PcdPciMmio64Translation + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Dbg2.aslc index d74332d359..42777fc554 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc @@ -54,9 +54,9 @@ STATIC DBG2_TABLE Dbg2 =3D { OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) }, - ARM_GAS32 (SBSAQEMU_UART0_BASE), /* BaseAddressRegister */ - 0x1000, /* AddressSize */ - SBSAQEMU_UART_STR, /* NameSpaceString */ + ARM_GAS32 (FixedPcdGet32(PcdSerialRegisterBase)), /* BaseAddressRegis= ter */ + 0x1000, /* AddressSize */ + SBSAQEMU_UART_STR, /* NameSpaceString = */ } }; =20 diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQ= emu/AcpiTables/Dsdt.asl index f320077c81..e056d6cdb0 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl @@ -33,7 +33,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "S= BSAQEMU", Name (_HID, "ARMH0011") Name (_UID, Zero) Name (_CRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, 0x60000000, 0x00001000) + Memory32Fixed (ReadWrite, + FixedPcdGet32 (PcdSerialRegisterBase), + 0x00001000) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 } }) } @@ -48,7 +50,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "S= BSAQEMU", }) Name (_CCA, 1) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0x60100000, 0x1000) + Memory32Fixed (ReadWrite, + FixedPcdGet32 (PcdPlatformAhciBase), + FixedPcdGet32 (PcdPlatformAhciSize)) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 } }) } @@ -60,7 +64,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "S= BSAQEMU", =20 Method (_CRS, 0x0, Serialized) { Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0x60110000, 0x00010000) + Memory32Fixed (ReadWrite, + FixedPcdGet32 (PcdPlatformEhciBase), + FixedPcdGet32 (PcdPlatformEhciSize)) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive)= { 43 } }) Return (RBUF) @@ -157,7 +163,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", = "SBSAQEMU", Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1) =20 Method (_CBA, 0, NotSerialized) { - return (0xf0000000) + return (FixedPcdGet32 (PcdPciExpressBaseAddress)) } =20 LINK_DEVICE(0, GSI0, 0x23) @@ -335,8 +341,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", = "SBSAQEMU", ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0, // AddressMinimum - Minimum Bus Number - 255, // AddressMaximum - Maximum Bus Number + FixedPcdGet32 (PcdPciBusMin), // AddressMinimum - Minimum Bus Nu= mber + FixedPcdGet32 (PcdPciBusMax), // AddressMaximum - Maximum Bus Nu= mber 0, // AddressTranslation - Set to 0 256 // RangeLength - Number of Busses ) @@ -345,22 +351,22 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO"= , "SBSAQEMU", ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Granularity - 0x80000000, // Min Base Address - 0xEFFFFFFF, // Max Base Address - 0x00000000, // Translate - 0x70000000 // Length + 0x00000000, // Granularity + FixedPcdGet32 (PcdPciMmio32Base), // Min Base Address + FixedPcdGet32 (PcdPciMmio32Limit), // Max Base Address + FixedPcdGet32 (PcdPciMmio32Translation), // Translate + FixedPcdGet32 (PcdPciMmio32Size) // Length ) =20 QWordMemory ( // 64-bit BAR Windows ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Granularity - 0x100000000, // Min Base Address - 0xFFFFFFFFFF, // Max Base Address - 0x00000000, // Translate - 0xFF00000000 // Length + 0x00000000, // Granularity + FixedPcdGet64 (PcdPciMmio64Base), // Min Base Address + FixedPcdGet64 (PcdPciMmio64Limit), // Max Base Address + FixedPcdGet64 (PcdPciMmio64Translation), // Translate + FixedPcdGet64 (PcdPciMmio64Size) // Length ) =20 DWordIo ( // IO window @@ -369,11 +375,11 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO"= , "SBSAQEMU", MaxFixed, PosDecode, EntireRange, - 0x00000000, // Granularity - 0x00000000, // Min Base Address - 0x0000ffff, // Max Base Address - 0x7fff0000, // Translate - 0x00010000, // Length + 0x00000000, // Granularity + FixedPcdGet32 (PcdPciIoBase), // Min Base Address + FixedPcdGet32 (PcdPciIoLimit), // Max Base Address + FixedPcdGet32 (PcdPciIoTranslation), // Translate + FixedPcdGet32 (PcdPciIoSize), // Length ,,,TypeTranslation ) }) // Name(RBUF) @@ -387,11 +393,11 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO"= , "SBSAQEMU", Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, N= onCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x00000000F0000000, // Range Minimum - 0x00000000FFFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000010000000, // Length + 0x0000000000000000, // Granularity + FixedPcdGet64 (PcdPciExpressBaseAddress), // Range Minimum + FixedPcdGet64 (PcdPciExpressBarLimit), // Range Maximum + 0x0000000000000000, // Translation Offset + FixedPcdGet64 (PcdPciExpressBarSize), // Length ,, , AddressRangeMemory, TypeStatic) }) } diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Mcfg.aslc index 3b617d7036..7a53569faa 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc @@ -27,10 +27,10 @@ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCR= IPTION_TABLE Mcfg =3D { }, { { - SBSAQEMU_PCI_SEG0_CONFIG_BASE, + FixedPcdGet32 (PcdPciExpressBaseAddress), 0, - SBSAQEMU_PCI_SEG0_BUSNUM_MIN, - SBSAQEMU_PCI_SEG0_BUSNUM_MAX, + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax), EFI_ACPI_RESERVED_DWORD } } diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Spcr.aslc index 6340a401c3..432097307f 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc @@ -25,7 +25,7 @@ STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spc= r =3D { 32, 0, EFI_ACPI_6_0_DWORD, - SBSAQEMU_UART0_BASE + FixedPcdGet32 (PcdSerialRegisterBase) }, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, 0, /* Irq */ diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index f085765d26..4d5b05ba17 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -37,12 +37,6 @@ SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ = \ } =20 -#define SBSAQEMU_UART0_BASE 0x60000000 - -#define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000 -#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00 -#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF - #define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5 =20 #define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' } --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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