From nobody Fri Apr 19 19:06:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+65019+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+65019+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1599184323; cv=none; d=zohomail.com; s=zohoarc; b=m8Qkg5Q0TvYjpM4dRrlgDj15Lt//MxX+YyRqCDSluU2Z/KzsDyuE1a4PGpMNZwoqUkb48w6ok+iwx3EJCzvGPDV2RQ85dAH+l/ymzS3IBNK8SqY8uw7pb8k+kAdM7sYAEu7E9EWCnPgoS+PKT2bweTadfZd6CLhXTl5yzHokxR0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599184323; h=Content-Transfer-Encoding:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=r19iNSOq2QaV25/e4QygVK2yyqn/3JqMWpZ9MuGoTcA=; b=WbyVnIBOXaRR3WVsdSVWF40dZUtZtkzQq7PBXu72Dm7J1nkbXH1jNckbHH+qSVeVkCYPTYdK6gswnji4AKDvTQ9qIpOfHIVyyqzCxcY6sfxL7NLYvH+YVmqHv99umMMOmw28Uze1oQFAHH6sjLklM/FcXznLzHxPNjrF6nGoL6s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+65019+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1599184323768862.455899744953; Thu, 3 Sep 2020 18:52:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id VlBHYY1788612xQIi7biw1qc; Thu, 03 Sep 2020 18:52:02 -0700 X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web12.29280.1599184321461015379 for ; Thu, 03 Sep 2020 18:52:01 -0700 IronPort-SDR: IDaXnB4vaOWcVKuaeN0eLMHD7rqdmGwjoYfTDErq1qYuabGLM+wgtXWRLJ6TKdT3sLlZWqdPaT Bcaab0e5toAg== X-IronPort-AV: E=McAfee;i="6000,8403,9733"; a="145382152" X-IronPort-AV: E=Sophos;i="5.76,387,1592895600"; d="scan'208";a="145382152" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2020 18:52:00 -0700 IronPort-SDR: aYYEmgtUkdKi+VM/ppda6XgrABXzrA/AebOM77bLkdHAMv3Gh3oPvJ71sYwDPn9pbR0sqB4La1 CLspxhcz07vQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,387,1592895600"; d="scan'208";a="503282037" X-Received: from ydong10-desktop.ccr.corp.intel.com ([10.239.154.145]) by fmsmga005.fm.intel.com with ESMTP; 03 Sep 2020 18:51:58 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [PATCH v3] UefiCpuPkg/MpInitLib: Add check for Cr3/GDT/IDT. Date: Fri, 4 Sep 2020 09:51:56 +0800 Message-Id: <20200904015156.1273-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com X-Gm-Message-State: pwtZ63Nf9pqcJtwHHWnHHQEcx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1599184322; bh=n2FEDW9/Xd1Ix1taqvOJ9AjG4vsETJKvWLZAuduVskk=; h=Cc:Date:From:Reply-To:Subject:To; b=EgxxrvmaEAbJFeOCXpEsHEppPnekf5q7rxudwEKniD2X6Cwvcb1xuIvHA4wr4UWGbFV +j4hsGR3QBr36PtprrkUYR18pH8sV5K/KOAUvrh/GM2Kb5R06nXOCDgUHQ39IyvAgX73+ PnpLOtMR3Br9J6pCD3qdJkBN4Mhgu1NlQBI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2954 AP needs to run from real mode to 32bit mode to LONG mode. Page table (pointed by Cr3) and GDT are necessary to set up to correct value when CPU execution mode is switched to LONG mode. AP uses the same location page table (Cr3) and GDT as what BSP uses. But when the page table or GDT is above 4GB, it's impossible for CPU to use because GDTR.base and Cr3 are 32bits before switching to LONG mode. This patch adds check for the Cr3, GDT and IDT to not above 4G limitation. The check is avoided -- assumed successful -- if the new PcdEnableCpuApCr3GdtIdtCheck is FALSE (which is the default). The reason is that the 32-bit requirement is always ensured by edk2 itself; the requirement is only possibly invalidated by a particular UEFI shell application that manually moves the GDT/IDT/CR3 above 4GB. Platforms that don't intend to be compatible with such UEFI applications need not set the PCD to TRUE. If the PCD is TRUE and the check fails, then the StartupAllAPs(), StartupThisAP(), SwitchBSP() and EnableDisableAP() MP service APIs are rejected at once. Reporting an error immediately is more graceful than hanging when the APs attempt to switch to long mode. Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek --- V3: only add check for the DxeMplib, no need for PeiMpLib. V2: Change the check point. Just in the different caller to make the logic clear. V1 patch add check just before the use of the code. It make the logic complicated. UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 1 + UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 97 +++++++++++++++++++ UefiCpuPkg/UefiCpuPkg.dec | 4 + UefiCpuPkg/UefiCpuPkg.uni | 2 + 4 files changed, 104 insertions(+) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index 1771575c69..7792df516e 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -74,5 +74,6 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds ## = CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## = CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase ## = SOMETIMES_CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdEnableCpuApCr3GdtIdtCheck ## = CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## = CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## = CONSUMES diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index 2c00d72dde..332b4447bb 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -29,6 +29,66 @@ VOID *mReservedApLoopFunc =3D NULL; UINTN mReservedTopOfApStack; volatile UINT32 mNumberToFinish =3D 0; =20 +/** + Check whether Cr3/GDT/IDT value valid for the APs. + + @retval TRUE Pass the check. + @retval FALSE Fail the check. + +**/ +BOOLEAN +ValidCr3GdtIdtCheck ( + VOID + ) +{ + IA32_DESCRIPTOR Gdtr; + IA32_DESCRIPTOR Idtr; + + if (!PcdGetBool (PcdEnableCpuApCr3GdtIdtCheck)) { + return TRUE; + } + + // + // AP needs to run from real mode to 32bit mode to LONG mode. Page table + // (pointed by Cr3) and GDT are necessary to set up to correct value when + // CPU execution mode is switched to LONG mode. IDT also necessary if the + // exception happened. + // AP uses the same location page table (Cr3) and GDT/IDT as what BSP us= es. + // But when the page table or GDT is above 4GB, it's impossible for CPU + // to use because GDTR.base and Cr3 are 32bits before switching to LONG + // mode. + // Here add check for the Cr3, GDT.Base and range, IDT.Base and range are + // not above 32 bits limitation. + // + if (AsmReadCr3 () >=3D BASE_4GB) { + return FALSE; + } + + AsmReadGdtr (&Gdtr); + // + // Here code needs to check both Gdtr.Base and Gdtr.Base + Gdtr.Limit + // below BASE_4GB, but Gdtr.Base + Gdtr.Limit below BASE_4GB also means + // Gdtr.Base below BASE_4GB. so here just add Gdtr.Base + Gdtr.Limit + // check. + // + if (Gdtr.Base + Gdtr.Limit >=3D BASE_4GB) { + return FALSE; + } + + AsmReadIdtr (&Idtr); + // + // Here code needs to check both Idtr.Base and Idtr.Base + Idtr.Limit + // below BASE_4GB, but Idtr.Base + Idtr.Limit below BASE_4GB also means + // Idtr.Base below BASE_4GB. so here just add Idtr.Base + Idtr.Limit + // check. + // + if (Idtr.Base + Idtr.Limit >=3D BASE_4GB) { + return FALSE; + } + + return TRUE; +} + /** Enable Debug Agent to support source debugging on AP function. =20 @@ -394,6 +454,15 @@ MpInitChangeApLoopCallback ( { CPU_MP_DATA *CpuMpData; =20 + // + // Check the Cr3/GDT/IDT before waking up AP. + // If the check return fail, it will block later + // OS boot, so halt the system here. + // + if (!ValidCr3GdtIdtCheck ()) { + CpuDeadLoop (); + } + CpuMpData =3D GetCpuMpData (); CpuMpData->PmCodeSegment =3D GetProtectedModeCS (); CpuMpData->Pm16CodeSegment =3D GetProtectedMode16CS (); @@ -676,6 +745,13 @@ MpInitLibStartupAllAPs ( { EFI_STATUS Status; =20 + // + // Check whether Cr3/GDT/IDT valid for AP. + // + if (!ValidCr3GdtIdtCheck()) { + return EFI_UNSUPPORTED; + } + // // Temporarily stop checkAllApsStatus for avoid resource dead-lock. // @@ -783,6 +859,13 @@ MpInitLibStartupThisAP ( { EFI_STATUS Status; =20 + // + // Check whether Cr3/GDT/IDT valid for AP. + // + if (!ValidCr3GdtIdtCheck()) { + return EFI_UNSUPPORTED; + } + // // temporarily stop checkAllApsStatus for avoid resource dead-lock. // @@ -839,6 +922,13 @@ MpInitLibSwitchBSP ( EFI_TIMER_ARCH_PROTOCOL *Timer; UINT64 TimerPeriod; =20 + // + // Check whether Cr3/GDT/IDT valid for AP. + // + if (!ValidCr3GdtIdtCheck()) { + return EFI_UNSUPPORTED; + } + TimerPeriod =3D 0; // // Locate Timer Arch Protocol @@ -912,6 +1002,13 @@ MpInitLibEnableDisableAP ( EFI_STATUS Status; BOOLEAN TempStopCheckState; =20 + // + // Check whether Cr3/GDT/IDT valid for AP. + // + if (!ValidCr3GdtIdtCheck()) { + return EFI_UNSUPPORTED; + } + TempStopCheckState =3D FALSE; // // temporarily stop checkAllAPsStatus for initialize parameters. diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index d83c084467..08ec36e76c 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -148,6 +148,10 @@ # @Prompt Lock SMM Feature Control MSR. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x= 3213210B =20 + ## This value specifies whether need to check the Cr3/GDT/IDT value for = the APs. + # @Prompt Enable Cr3/GDT/IDT value check for the APs. + gUefiCpuPkgTokenSpaceGuid.PcdEnableCpuApCr3GdtIdtCheck|FALSE|BOOLEAN|0x3= 0000044 + [PcdsFixedAtBuild] ## List of exception vectors which need switching stack. # This PCD will only take into effect if PcdCpuStackGuard is enabled. diff --git a/UefiCpuPkg/UefiCpuPkg.uni b/UefiCpuPkg/UefiCpuPkg.uni index 219c1963bf..3461a83003 100644 --- a/UefiCpuPkg/UefiCpuPkg.uni +++ b/UefiCpuPkg/UefiCpuPkg.uni @@ -96,6 +96,8 @@ =20 #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmFeatureControlMsrLock_PROMP= T #language en-US "Lock SMM Feature Control MSR" =20 +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdEnableCpuApCr3GdtIdtCheck_PROMPT = #language en-US "Enable Cr3/GDT/IDT value check for the APs" + #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmFeatureControlMsrLock_HELP = #language en-US "Lock SMM Feature Control MSR?

\n" = "TRUE - locked.
\n" = "FALSE - unlocked.
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